LP3929TMEX-AACQ/NOPB

LP3929 www.ti.com SNVS442C – JULY 2006 – REVISED MAY 2013 LP3929 High Speed Bi-Directional Level Shifter and Ultra Low-Dropout CMOS Voltage Regulator and Line Protection Check for Samples: LP3929 FEATURES DESCRIPTION • • • The LP3929 is designed for portable and wireless applications requiring level translation and power supply generation in a compact footprint. 1 2 Ultra Small DSBGA 24 Bump Package 6-signal Level Translation 1.8 V to 2.85 V LDO Stable with Ceramic and High Quality Tantalum Capacitors KEY SPECIFICATIONS • • • Level Shifter: – 6-Signal Level Shifter (5 Bi-Directional and 1 Uni-Direction) – 3 ns (Typ) Propagation Delay – Channel-to-Channel Skew < 1 ns (Max) Low-Dropout Regulator: – 3.05 V to 5.5 V Input Range – 2.85 V at 200 mA – Fast Turn-On Time: 30 µs (Typ) – 110 mV (Max) Dropout with 200 mA Load – Thermal Shutdown at 160°C (Typ) Protection Block (B Side): – Robust IEC ESD Protection: ±15 kV Air Gap, ±8 kV Direct Contact – ASIP / EMI Filtering The device level translates 1.8 V LVCMOS on the host (A) side to 2.85 V LVCMOS levels on the card (B) side for a miniSD / SD 4-bit bi-directional data bus. Independent direct control of the CMD, Data0 and Data1-3 paths support mini SD state machine requirements. A shutdown pin is provided for the level shifters and regulator. The f_CLK_A is a feedback clock to the host which can be used to overcome level shifter bus delay. The built-in low-dropout voltage regulator is ideal for mobile phone and battery powered wireless applications. It provides up to 200 mA from a 3.05 V to 5.5 V input. It is stable with small 1.0 µF ±30% ceramic and high quality tantalum output capacitors, requiring smallest possible PC board area. The card (B port) side channels have integration of ASIP (Application Specific Integrated Passives) - on chip integrated pull-up, pull-down, series resistors and capacitors for EMC filtering. It is designed to tolerate IEC61000-4-2 level 4 ESD: ±15 kV air discharge, ±8 kV direct contact. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2013, Texas Instruments Incorporated LP3929 SNVS442C – JULY 2006 – REVISED MAY 2013 www.ti.com Typical Application Circuit VDDA A Side 1.8V B Side 2.85V CLK_B CLK_A CMD_B fCLK_A CMD_A CMD_DIR CPU or ASIC LP3929 D0_A Level Shift, ASIP and Integrated PSU D1_A D2_A A S I P D0_B m i n i S D D1_B D2_B D3_B D3_A DIR_0 WP CD DIR_1-3 VDDB EN VBAT 2 Integrated PSU 2.85V 200mA Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP3929 LP3929 www.ti.com SNVS442C – JULY 2006 – REVISED MAY 2013 BLOCK DIAGRAM CLK_B CLK_A fCLK_A CMD_B CMD_A CMD_DIR D0_B D0_A DIR_0 D1_B D1_A DIR_1-3 D2_B D2_A D3_B D3_A VDDA To XCVRs EN VDDA VDDA VDDB PSU VDDB = 2.85V @ 200 mA VBAT CD WP VDDB ESD Protection not shown Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP3929 3 LP3929 SNVS442C – JULY 2006 – REVISED MAY 2013 www.ti.com Package Outline CMD_ DIR A D2_A B D3_A C CLK_A D E DIR_0 VBAT D2_B VDDA VDDB D3_B EN VSS VSS CLK_B D0_A CMD_A CD CMD_B D0_B D1_A fCLK_A DIR_1-3 WP D1_B 1 2 3 4 5 Figure 1. Bump Underneath (Top View) 24 Bump DSBGA Package See Package Number YFR0024AAA Tape and Reel Information Top View of Package Orientation Pin 1 Marking Direction of Flow Figure 2. Tape and Reel Information (Top View) 4 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP3929 LP3929 www.ti.com SNVS442C – JULY 2006 – REVISED MAY 2013 Pin Descriptions Pin Name DSBGA Bump Identifier Port / Direction Type D0_A D1 Host / Bidirectional Push-Pull 1.8 V I/O Channel (1) D1_A E1 Host / Bidirectional Push-Pull 1.8 V I/O Channel (1) D2_A A1 Host / Bidirectional Push-Pull 1.8 V I/O Channel (1) D3_A B1 Host / Bidirectional Push-Pull 1.8 V I/O Channel (1) CMD_A D2 Host / Bidirectional Push-Pull 1.8 V I/O Channel (1) CLK_A C1 Host / Input High Z 1.8 V Input CLK Channel (1) fCLK_A E2 Host / Output Push-Pull 1.8 V Output CLK Channel DIR_0 A3 Host / Input High Z 1.8 V Input Direction Control D0 Channel: VDDA = A → B Direction (Write), VSS = B → A Direction (Read) DIR_1-3 E3 Host / Input High Z 1.8 V Input Direction Control D1-D3 Channel: VDDA = A → B Direction (Write), VSS = B → A Direction (Read) CMD_DIR A2 Host / Input High Z 1.8 V Input Direction Control CMD Channel: VDDA = A → B Direction (Write), VSS = B → A Direction (Read) EN C2 Host / Input High Z Device Enable with high impedance pull-down resistor (200 kΩ): VDDA = Device Active (on), VSS = Device Disabled (off) D0_B D5 Card / Bidirectional Push-Pull 2.85 V I/O Channel with high impedance pull-up to VDDB (70 kΩ) D1_B E5 Card / Bidirectional Push-Pull 2.85 V I/O Channel with high impedance pull-up to VDDB (70 kΩ) D2_B A5 Card / Bidirectional Push-Pull 2.85 V I/O Channel with high impedance pull-up to VDDB (70 kΩ) D3_B B5 Card / Bidirectional Push-Pull 2.85 V I/O Channel with high impedance pull-down to VSS (470 kΩ) CMD_B D4 Card / Bidirectional Push-Pull 2.85 V I/O Channel with high impedance pull-up to VDDB (15 kΩ) CLK_B C5 Card / Output Push-Pull 2.85 V Output CLK Channel VBAT A4 Host / Input Power 3.05 V to 5.5 V VDDA B3 Host / Input Power 1.71 V to 1.92 V, 1.8 V (typ) VDDB B4 Card / Output Power 2.85 V (LDO output) VSS C3 Ground VSS C4 Ground (1) Function WP E4 Host / Card Input Pull-up Pull-up to VDDA (100 kΩ) CD D3 Host / Card Input Pull-up Pull-up to VDDA (100 kΩ) Unused inputs must be terminated. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP3929 5 LP3929 SNVS442C – JULY 2006 – REVISED MAY 2013 www.ti.com Table 1. OPERATION MODES (1) Inputs (1) Mode EN CMD_DIR DIR_0 DIR_1-3 L X X X Level shifter / LDO = off (Shutdown Mode) H L L L All channels (D0-D3 and CMD): B → A Direction H L L H A → B Direction: D1-D3, B → A Direction: CMD and D0 H L H L A → B Direction: D0, B → A Direction: CMD and D1-D3 H L H H A → B Direction: D0-D3, B → A Direction: CMD H H L L A → B Direction: CMD, B → A Direction: D0-D3 H H L H A → B Direction: CMD and D1-D3, B → A Direction: D0 H H H L A → B Direction: CMD and D0, B → A Direction: D1-D3 H H H H All channels (D0-D3 and CMD): A → B Direction H = VDDA, L = VSS These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) −0.3V to +6.0V Supply Voltage (VBAT) −0.3V to +3.3V Supply Voltage (VDDA) LVCMOS A Port Input Voltage −0.3V to VDDA + 0.3V LVCMOS A Port I/O Voltage −0.3V to VDDA + 0.3V LVCMOS B Port I/O Voltage −0.3V to VDDB + 0.3V Junction Temperature 150°C Storage Temperature −65°C to +150°C Lead Temperature (3) 235°C Pad Temperature (3) 235°C Derate DSBGA Package above 25°C Maximum Power Dissipation Capacity at 25°C 22.9 mW/°C DSBGA 2.8 W HBM - MIL-STD-883E 3015.7 std. ESD Rating ± 2kV MM - JESD22-A115-A std. ± 200V CDM - 500V (JESD22-C 101) Std. ± 500V IEC61000-4-2 std., 330Ω, 150pF, Air Gap, B Side (4) ± 15kV IEC61000-4-2 std., 330Ω, 150pF, Direct Contact, B Side (4) (1) (2) (3) (4) ± 8kV ABSOLUTE MAXIMUM RATINGS are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that the device should be operated at these limits. The tables of ELECTRICAL CHARACTERISTICS specify conditions for device operation. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Additional information on lead temperature and pad temperature can be found in Texas Instruments Application Note (AN-1112). IEC61000-4-2 level 4 ESD tolerance applies to VDDB, D0_B–D3_B, CMD_B, CLK_B, WP and CP pins only. Device is tested in application (common ground, bypass capacitors of 1.0 µF present on VBAT, VDDA and VDDB). OPERATING CONDITIONS VBAT to VSS 3.05V to 5.5V VDDA to VSS 1.71V to 1.92V −30°C to +85°C Ambient Temperature 6 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP3929 LP3929 www.ti.com SNVS442C – JULY 2006 – REVISED MAY 2013 ELECTRICAL CHARACTERISTICS Unless otherwise specified: CVBAT = 1 µF, IOUT = 1 mA, CVDDB = 1 µF, CVDDA = 1 µF. Typical values and limits appearing in standard typeface apply for TA = 25°C. Limits appearing in boldface type apply over the entire ambient temperature range for operation, −30°C to +85°C. (1) (2) Symbol Parameter Conditions Min Typ Max Units 0.65×VDDA 1.92 V VDDA = 1.71V 1.1115 1.92 V VDDA = 1.92V 1.248 1.92 V 0 0.30×VDDA V VDDA = 1.71V 0 0.513 V VDDA = 1.92V 0 0.576 V LVCMOS A (Host) Port (VDDA = 1.71V to 1.92V) VIH Input Voltage High Level VIL Input Voltage Low Level IIH Input Current High Level −1 0 +1 µA EN = VSS −1 0 +1 µA EN = VDDA −1 0 +10 µA −1 0 +1 µA VIH = VDDA IIL Input Current Low Level VIL = VSS VOH Output Voltage High Level IOH = −4 mA 1.26 1.8 VDDA V VOL Output Voltage Low Level IOL = 4 mA VSS 0 0.45 V VDDB V LVCMOS B (Card) Port (VDDB = 2.85V) VIH Input Voltage High Level VIL Input Voltage Low Level IIH Input Current High Level 0.65×VDDB 0 VIH = VDDB D0_B to D2_B D3_B IIL Input Current Low Level VIL = VSS Short Circuit Current IOS − V 0.2 +2 µA 0 6.5 + 13 µA CMD_B −5 0.3 +5 µA D0_B to D2_B − 80 −40 0 µA D3_B −1 0.1 +1 µA − 300 − 200 − 20 µA CMD_B IOS + 0.35×VDDB −2 VOUTlow = VDDB 45 µA VOUThigh = VSS − 20 µA VOH Output Voltage High Level IOH = − 2 mA VOL Output Voltage Low Level IOL = 2 mA 0.75×VDDB V 0.25×VDDB V Supply Current IDD Supply Current IDDZ Supply Current — Shutdown COUT (1) (2) (3) Output Capacitance (3) All Channels Static: A → B mode, LDO unloaded VBAT 4 7 mA VDDA 95 200 µA EN = VSS VBAT 0.1 2 µA VDDA 0.2 2 µA 15 20 pF B (card) port Typical values are given for VDDA = 1.8V, VBAT = 3.6V, TA = 25°C Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are reference to ground unless otherwise specified. This electrical specification is ensured by design. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP3929 7 LP3929 SNVS442C – JULY 2006 – REVISED MAY 2013 www.ti.com LEVEL SHIFTER AC SWITCHING CHARACTERISTICS Unless otherwise specified: CVBAT = 1 µF, IOUT = 1 mA, CVDDB = 1 µF, CVDDA = 1 µF. Typical values and limits appearing in standard typeface apply for TA = 25°C. Limits appearing in boldface type apply over the entire ambient temperature range for operation, −30°C to +85°C. (1) (2) (3) (4) Symbol tPLH tPHL tRISE tFALL Typ Max Units Propagation Delay A to B or B to A Parameter CLB = 15 pF, CLA = 20 pF, 50%50% Conditions Min 3 7 ns Propagation Delay CLK_A to fCLK_A CLA = 20 pF, 50%-50% 5 14 ns Propagation Delay A to B or B to A CLB = 15 pF, CLA = 20 pF, 50%50% 3 7 ns Propagation Delay CLK_A to fCLK_A CLA = 20 pF, 50%-50% 5 14 ns Rise Time A Side Output, see Figure 4 CLA = 20 pF, 20%-70% 1.1 3 ns Rise Time B Side Output with ASIP, see Figure 4 CLB = 15 pF, 20%-70% 1.6 3 ns Fall Time A Side Output, see Figure 4 CLA = 20 pF, 20%-70% 1.0 3 ns Fall Time B Side Output with ASIP, see Figure 4 CLB = 15 pF, 20%-70% 1.9 3 ns