LP3964EMP-2.5/NOPB

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents LP3961, LP3964 SNVS056J – MAY 2000 – REVISED JUNE 2015 LP396x 800-mA Fast Ultra-Low-Dropout Linear Regulators 1 Features 3 Description • • • • • • • • • The LP396x series of fast ultra-low-dropout linear regulators operate from a 2.5-V to 7-V input supply. A wide range of preset output voltage options are available. These ultra-low dropout linear regulators respond very fast to step changes in load which makes them suitable for low-voltage microprocessor applications. The LP3961 and LP3964 are developed on a CMOS process which allows low quiescent current operation independent of output load current, as well as operation under extremely low dropout conditions. 1 • • • Input Supply Voltage: 2.5 V to 7 V Ultra-Low Dropout Voltage Low Ground Pin Current Load Regulation of 0.02% 15-µA Quiescent Current in Shutdown Mode Specified Output Current of 0.8-A DC Output Voltage Accuracy ±1.5% ERROR Flag Indicates Output Status (LP3961) Sense Option Improves Better Load Regulation (LP3964) Extremely Low Output Capacitor Requirements Overtemperature and Overcurrent Protection −40°C to 125°C Junction Temperature Range 2 Applications • • • • • • • • Microprocessor Power Supplies GTL, GTL+, BTL, and SSTL Bus Terminators Power Supplies for DSPs SCSI Terminator Post Regulators High-Efficiency Linear Regulators Battery Chargers Other Battery-Powered Applications Dropout Voltage: Ultra-low dropout voltage; typically 24 mV at 80-mA load current and 240 mV at 800-mA load current. Ground Pin Current: Typically 4 mA at 800-mA load current. ERROR Flag: ERROR flag goes low when the output voltage drops 10% below nominal value (for LP3961). SENSE: SENSE pin improves regulation at remote loads (for LP3964). Precision Output Voltage: Multiple output voltage options are available ranging from 1.2 V to 5 V and adjustable (LP3964), with a specified accuracy of ±1.5% at room temperature, and ±3% over all conditions (varying line, load, and temperature). Device Information(1) PACKAGE BODY SIZE (NOM) LP3961 LP3964 PART NUMBER SOT-223 (5) 6.50 mm × 3.56 mm TO-263 (5) 10.16 mm × 8.42 mm LP3964 TO-220 (5) 14.986 mm × 10.16 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. space LP3964 Typical Application Circuits LP3961 Typical Application Circuit A. * SD and ERROR pins must be pulled high through a 10-kΩ pullup resistor. Connect the ERROR pin to ground if this function is not used. * See note A on LP3961 Typical Application Circuit. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LP3961, LP3964 SNVS056J – MAY 2000 – REVISED JUNE 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configurations and Functions ....................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 4 5 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics ............................................. Detailed Description ............................................ 10 7.1 Overview ................................................................. 10 7.2 Functional Block Diagram ....................................... 10 7.3 Feature Description................................................. 11 7.4 Device Functional Modes........................................ 13 8 Application and Implementation ........................ 14 8.1 Application Information .......................................... 14 8.2 Typical Applications ................................................ 14 9 Power Supply Recommendations...................... 19 10 Layout................................................................... 19 10.1 Layout Guidelines ................................................. 19 10.2 Layout Example .................................................... 19 10.3 Heatsinking TO-220 Packages ............................. 20 11 Device and Documentation Support ................. 21 11.1 11.2 11.3 11.4 11.5 Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 21 21 21 21 21 12 Mechanical, Packaging, and Orderable Information ........................................................... 21 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision I (December 2014) to Revision J Page • Changed pin names to conform to TI nomenclature (VOUT to OUT, VIN to IN)....................................................................... 1 • Changed "I" to "O" to correct I/O type for ERROR flag ......................................................................................................... 3 • Deleted Lead temperature row - info in POA ........................................................................................................................ 4 • Deleted heatsinking sections re TO-263 and SOT-223 packages; not consistent with updated thermal metrics .............. 20 Changes from Revision H (April 2013) to Revision I • Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................................................................................................... 1 Changes from Revision G (April 2013) to Revision H 2 Page Submit Documentation Feedback Page Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3961 LP3964 LP3961, LP3964 www.ti.com SNVS056J – MAY 2000 – REVISED JUNE 2015 5 Pin Configurations and Functions 5-Pin NDC SOT-223 Package Top View 5-Pin NDH TO-220 Package (LP3964) Top View 5-Pin KTT SFM/TO-263 Package Top View Pin Functions PIN NO. NAME I/O LP3964 LP3961 SOT-223 TO-220 SFM/TO-263 DESCRIPTION ERROR 4 — — O ERROR flag GND 5 5 3 — Ground IN 2 2 2 I Input supply OUT 3 3 4 O Output voltage SD 1 1 1 I Shutdown SENSE/AD J — 4 5 I Remote sense pin or output adjust pin Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3961 LP3964 3 LP3961, LP3964 SNVS056J – MAY 2000 – REVISED JUNE 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) (2) MIN MAX UNIT Power dissipation (3) Internally Limited Input Supply Voltage (Survival) −0.3 7.5 V Shutdown Input Voltage (Survival) −0.3 VIN + 0.3 V −0.3 7.5 V Output Voltage (Survival) (4) (5) , IOUT (Survival) Short-Circuit Protected Maximum Voltage for ERROR pin VIN + 0.3 Maximum Voltage for SENSE pin Storage temperature, Tstg (1) (2) (3) (4) (5) V VOUT + 0.3 V 150 °C –65 Absolute maximum ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and test conditions, see Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. If Military- or Aerospace-specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications. The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal resistance, RθJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: P(MAX) = (TJ(MAX) – TA) / RθJA. If used in a dual-supply system where the regulator load is returned to a negative supply, the LP396X output must be diode-clamped to ground. The output PMOS structure contains a diode between the IN and OUT pins. This diode is normally reverse biased. This diode will get forward biased if the voltage at the OUT pin is forced to be higher than the voltage at the IN pin. This diode can typically withstand 200 mA of DC current and 1 A of peak current. 6.2 ESD Ratings V(ESD) (1) Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) Electrostatic discharge VALUE UNIT ±2000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.. 6.3 Recommended Operating Conditions MIN MAX 2.5 7 V −0.3 VIN + 0.3 V 0.8 A 125 °C Input supply voltage (operating) (1) Shutdown input voltage (operating) Maximum operating current (DC) −40 Operating junction temperature (1) UNIT The minimum operating value for VIN is equal to either [VOUT(NOM) + VDROPOUT] or 2.5 V, whichever is greater. 6.4 Thermal Information LP3961, LP3964 THERMAL METRIC (1) NDC KTT LP3964 NDH UNIT 5 PINS RθJA Junction-to-ambient thermal resistance 65.2 40.3 32.1 RθJC(top) Junction-to-case (top) thermal resistance 47.2 43.4 43.8 RθJB Junction-to-board thermal resistance 9.9 23.1 18.7 ψJT Junction-to-top characterization parameter 3.4 11.5 8.8 ψJB Junction-to-board characterization parameter 9.7 22.1 18.0 RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 1.0 1.3 (1) 4 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3961 LP3964 LP3961, LP3964 www.ti.com SNVS056J – MAY 2000 – REVISED JUNE 2015 6.5 Electrical Characteristics Unless otherwise specified: TJ = 25°C, VIN = VO(NOM) + 1 V, IL = 10 mA, COUT = 33 µF, VSD = VIN – 0.3 V. MIN (1) TYP (2) MAX (1) 10 mA ≤ IL ≤ 800 mA, VOUT + 1 ≤ VIN ≤ 7 V –1.5% 0% 1.5% 10 mA ≤ IL ≤ 800 mA, VOUT + 1 ≤ VIN ≤ 7 V, –40°C ≤ TJ ≤ 125°C –3% PARAMETER VO Output voltage tolerance VADJ ΔVOL ΔVO / ΔIOUT TEST CONDITIONS (3) Adjust pin voltage (ADJ version) Output voltage line regulation (3) Output voltage load regulation (3) VIN – VOUT Dropout voltage (4) 10 mA ≤ IL ≤ 800 mA, VOUT + 1.5 V ≤ VIN ≤ 7 V 1.198 10 mA ≤ IL ≤ 800 mA, VOUT + 1.5 V ≤ VIN ≤ 7 V, –40°C ≤ TJ ≤ 125°C 1.180 3% 1.216 V VOUT + 1 V < VIN < 7 V 0.02% VOUT + 1 V < VIN < 7 V, –40°C ≤ TJ ≤ 125°C 0.06% 10 mA < IL < 800 mA 0.02% 10 mA < IL < 800 mA, –40°C ≤ TJ ≤ 125°C 0.08% IL = 80 mA 24 30 35 IL = 800 mA 240 IL = 800 mA, –40°C ≤ TJ ≤ 125°C Ground pin current in normal operation mode 1.234 1.253 IL = 80 mA, –40°C ≤ TJ ≤ 125°C IGND UNIT 300 mV 350 IL = 80 mA 3 IL = 80 mA, –40°C ≤ TJ ≤ 125°C 9 10 IL = 800 mA 4 IL = 800 mA, –40°C ≤ TJ ≤ 125°C 14 mA 15 IGND Ground pin current in shutdown mode (5) VSD ≤ 0.2 V IO(PK) Peak output current See (6) 1.2 See (6), –40°C ≤ TJ ≤ 125°C 1.1 15 VSD ≤ 0.2 V, –40°C ≤ TJ ≤ 125°C 25 µA 75 1.5 A 2.8 A 165 °C 10 °C SHORT-CIRCUIT PROTECTION ISC Short-circuit current OVERTEMPERATURE PROTECTION Tsh(t) Shutdown threshold Tsh(h) Thermal shutdown hysteresis SHUTDOWN INPUT Output = High VSDT Shutdown threshold Output = High, –40°C ≤ TJ ≤ 125°C Output = Low Output = Low, –40°C ≤ TJ ≤ 125°C (1) (2) (3) (4) (5) (6) VIN VIN – 0.3 V 0 0.2 Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. The limits are used to calculate TI's Average Outgoing Quality Level (AOQL). Typical numbers are at 25°C and represent the most likely parametric norm. Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the input line voltage. Output voltage load regulation is defined as the change in output voltage from the nominal value due to change in load current. The line and load regulation specification contains only the typical number. However, the limits for line and load regulation are included in the output voltage tolerance specification. Dropout voltage is defined as the minimum input-to-output differential voltage at which the output drops 2% below the nominal value. Dropout voltage specification applies only to output voltages of 2.5 V and above. For output voltages below 2.5 V, the drop-out voltage is nothing but the input-to-output differential voltage because the minimum input voltage is 2.5 V. This specification has been tested for –40°C ≤ TJ ≤ 85°C because the temperature rise of the device is negligible under shutdown conditions. The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal resistance, RθJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: P(MAX) = (TJ(MAX) – TA) / RθJA. Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3961 LP3964 5 LP3961, LP3964 SNVS056J – MAY 2000 – REVISED JUNE 2015 www.ti.com Electrical Characteristics (continued) Unless otherwise specified: TJ = 25°C, VIN = VO(NOM) + 1 V, IL = 10 mA, COUT = 33 µF, VSD = VIN – 0.3 V. PARAMETER TEST CONDITIONS MIN (1) TYP (2) MAX (1) UNIT TdOFF Turnoff delay IL = 800 mA 20 TdON Turnon delay IL = 800 mA 25 µs µs ISD SD input current VSD = VIN 1 nA ERROR FLAG COMPARATOR VT Threshold See (7) See (7), –40°C ≤ TJ ≤ 125°C VTH Threshold hysteresis See (7) See (7), –40°C ≤ TJ ≤ 125°C VEF(Sat) ERROR flag saturation 10% 5% 16% 5% 2% Isink = 100 µA 8% 0.02 Isink = 100 µA V 0.1 Td Flag reset delay 1 µs Ilk ERROR flag pin leakage current 1 nA Imax ERROR flag pin sink current 1 mA VERROR = 0.5 V (overtemperature) AC PARAMETERS PSRR Ripple rejection ρn(l/f) Output noise density en Output noise voltage (rms) (7) 6 VIN = VOUT + 1.5 V, COUT = 100 µF, VOUT = 3.3 V 60 VIN = VOUT + 0.3 V, COUT = 100 µF, VOUT = 3.3 V 40 f = 120 Hz 0.8 BW = 10 Hz to 100 kHz 150 BW = 300 Hz to 300 kHz 100 dB µV µVRMS ERROR flag threshold and hysteresis are specified as percentage of regulated output voltage. Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3961 LP3964 LP3961, LP3964 www.ti.com SNVS056J – MAY 2000 – REVISED JUNE 2015 6.6 Typical Characteristics Unless otherwise specified, VIN = VO(NOM) + 1 V, VOUT = 2.5 V, COUT = 33 µF, IOUT = 10 mA, CIN = 68 µF, VSDT = VIN, and TA = 25°C. Figure 1. Drop-Out Voltage vs Temperature for Different Load Currents Figure 2. Drop-Out Voltage vs Temperature for Different Output Voltages (IOUT = 800 mA) Figure 3. Ground Pin Current vs Input Voltage (VSD = VIN) Figure 4. Ground Pin Current vs Input Voltage (VSD = 100 mV) Figure 5. Ground Current vs Temperature (VSD = VIN) Figure 6. Ground Current vs Temperature (VSD = 0 V) Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3961 LP3964 7 LP3961, LP3964 SNVS056J – MAY 2000 – REVISED JUNE 2015 www.ti.com Typical Characteristics (continued) Unless otherwise specified, VIN = VO(NOM) + 1 V, VOUT = 2.5 V, COUT = 33 µF, IOUT = 10 mA, CIN = 68 µF, VSDT = VIN, and TA = 25°C. 8 Figure 7. Ground Pin Current vs Shutdown Pin Voltage Figure 8. Input Voltage vs Output Voltage Figure 9. Output Noise Density, VOUT = 2.5 V Figure 10. Output Noise Density, VOUT = 5 V Figure 11. Load Transient Response Figure 12. Ripple Rejection vs Frequency Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3961 LP3964 LP3961, LP3964 www.ti.com SNVS056J – MAY 2000 – REVISED JUNE 2015 Typical Characteristics (continued) Unless otherwise specified, VIN = VO(NOM) + 1 V, VOUT = 2.5 V, COUT = 33 µF, IOUT = 10 mA, CIN = 68 µF, VSDT = VIN, and TA = 25°C. Figure 13. δVOUT vs Temperature Figure 14. Noise Density VIN = 3.5 V, VOUT = 2.5 V, IL = 10 mA Figure 15. Line Transient Response Figure 16. Line Transient Response Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3961 LP3964 9 LP3961, LP3964 SNVS056J – MAY 2000 – REVISED JUNE 2015 www.ti.com 7 Detailed Description 7.1 Overview The LP3961/LP3964 are a series of ultra-low dropout linear regulators. Fixed output products have output voltage options from 1.2 V to 5 V, adjustable output voltage is only available for LP3964. These regulators can provide maximum 800-mA load current. The device can operate under extremely low dropout conditions. The LP3961 has an ERROR flag pin, this pin will go low when the output voltage drops 10% below nominal value. The LP3964 (fixed output products) provides a SENSE pin. The SENSE pin can improve regulation at remote loads. The LP3961, LP3964 also provide short-circuit protection and reverse current path. The devices can be operated with shutdown (SD) pin control. 7.2 Functional Block Diagram Figure 17. LP3961 Block Diagram Figure 18. LP3964 Block Diagram 10 Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3961 LP3964 LP3961, LP3964 www.ti.com SNVS056J – MAY 2000 – REVISED JUNE 2015 Functional Block Diagram (continued) Figure 19. LP3964 Adjustable Version Block Diagram 7.3 Feature Description 7.3.1 Short-Circuit Protection The LP3961 and LP3964 are short-circuit protected and in the event of a peak overcurrent condition, the shortcircuit control loop will rapidly drive the output PMOS pass element off. Once the power pass element shuts down, the control loop will rapidly cycle the output on and off until the average power dissipation causes the thermal shutdown circuit to respond to servo the on/off cycling to a lower frequency. Please refer to the section on thermal information for power dissipation calculations. 7.3.2 ERROR Flag Operation The LP3961 produces a logic low signal at the ERROR flag pin when the output drops out of regulation due to low input voltage, current limiting, or thermal limiting. This flag has a built-in hysteresis. The timing diagram in Figure 20 shows the relationship between the ERROR pin and the output voltage. In this example, the input voltage is changed to demonstrate the functionality of the ERROR flag. The internal ERROR flag comparator has an open drain output stage. Hence, the ERROR pin should be pulled high through a pull-up resistor. Although the ERROR pin can sink current of 1 mA, this current is an energy drain from the input supply. Hence, the value of the pull-up resistor should be in the range of 100 kΩ to 1 MΩ. The ERROR pin must be connected to ground if this function is not used. It should also be noted that when the SD pin is pulled low, the ERROR pin is forced to be invalid for reasons of saving power in shutdown mode. Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3961 LP3964 11 LP3961, LP3964 SNVS056J – MAY 2000 – REVISED JUNE 2015 www.ti.com Feature Description (continued) Figure 20. ERROR Flag Operation 7.3.3 SENSE Pin In applications where the regulator output is not very close to the load, LP3964 can provide better remote load regulation using the SENSE pin. Figure 21 depicts the advantage of the SENSE option. LP3961 regulates the voltage at the OUT pin. Hence, the voltage at the remote load will be the regulator output voltage minus the drop across the trace resistance. For example, in the case of a 3.3-V output, if the trace resistance is 100 mΩ, the voltage at the remote load will be 3.22 V with 800 mA of load current, ILOAD. The LP3964 regulates the voltage at the SENSE pin. Connecting the SENSE pin to the remote load will provide regulation at the remote load, as shown in Figure 21. If the sense option pin is not required, the SENSE pin must be connected to the OUT pin. Figure 21. Improving Remote Load Regulation Using LP3964 12 Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3961 LP3964 LP3961, LP3964 www.ti.com SNVS056J – MAY 2000 – REVISED JUNE 2015 Feature Description (continued) 7.3.4 Dropout Voltage The dropout voltage of a regulator is defined as the minimum input-to-output differential required to stay within 2% of the output voltage. The LP3961 and LP3964 use an internal MOSFET with an Rds(on) of 240 mΩ (typically). For CMOS LDOs, the dropout voltage is the product of the load current and the Rds(on) of the internal MOSFET. 7.3.5 Reverse Current Path The internal MOSFET in LP3961 and LP3964 has an inherent parasitic diode. During normal operation, the input voltage is higher than the output voltage and the parasitic diode is reverse biased. However, if the output is pulled above the input in an application, then current flows from the output to the input as the parasitic diode gets forward biased. The output can be pulled above the input as long as the current in the parasitic diode is limited to 200-mA continuous and 1-A peak. 7.4 Device Functional Modes 7.4.1 Operation With VOUT(TARGET) + 0.35 V ≤ VIN ≤ 7 V For the fixed output voltage products, the devices operate if the input voltage is equal to or exceeds VOUT(TARGET) + 0.35 V. At input voltages below the minimum VIN requirement, the devices do not operate correctly and output voltage may not reach target value. 7.4.2 Operation With Shutdown (SD) Pin Control A CMOS logic low level signal at the shutdown (SD) pin will turn off the regulator. The SD pin must be actively terminated through a 10-kΩ pullup resistor for a proper operation. This pin must be tied to the IN pin if not used . Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3961 LP3964 13 LP3961, LP3964 SNVS056J – MAY 2000 – REVISED JUNE 2015 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LP3961, LP3964 products can provide 800-mA output current with 2.5-V to 7-V input voltage. An input capacitor of at least 68-uF is required. A minimum 33-uF output capacitor is required for loop stability. Pin SD must be tied to input if not used. For LP3961, the ERROR pin should be pulled high through a pull up resistor; if this function is not used, ERROR pin must be connected to ground . For LP3964, if the sense option is not required, the SENSE pin must be connected to the OUT pin. 8.2 Typical Applications Figure 22. LP3961 Typical Application Circuit Figure 23. LP3964 Typical Application Circuits 14 Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3961 LP3964 LP3961, LP3964 www.ti.com SNVS056J – MAY 2000 – REVISED JUNE 2015 Typical Applications (continued) 8.2.1 Design Requirements DESIGN PARAMETERS VALUE Input voltage 5.3 V, ±10% Output voltage 3.3 V, ±3% Output current 800 mA (maximum) Input capacitor 68 uF (minimum) Output capacitor 33 uF (minimum) ERROR pullup resistor (LP3964 only) 10 kΩ 8.2.2 Detailed Design Procedure 8.2.2.1 External Capacitors Like any low-dropout regulator, external capacitors are required to assure stability. these capacitors must be correctly selected for proper performance. 8.2.2.1.1 Input Capacitor The LP3961 or LP3964 requires a low source impedance to maintain regulator stability because the internal bias circuitry is connected directly to the IN pin. The input capacitor must be located less than 1 cm from the LP3961 or LP3964 device and connected directly to the IN and GND pins using traces which have no other currents flowing through them (see the Layout Guidelines section). The minimum allowable input capacitance for a given application depends on the type of the capacitor and equivalent series resistance (ESR). A lower ESR capacitor allows the use of less capacitance, while higher ESR types (like aluminum electrolytics) require more capacitance. The lowest value of input capacitance that can be used for stable full-load operation is 68 µF (assuming it is a ceramic or low-ESR Tantalum with ESR less than 100 mΩ). To determine the minimum input capacitance amount and ESR value, an approximation is used: CIN ESR (mΩ) / CIN (µF) ≤ 1.5 (1) This shows that input capacitors with higher ESR values can be used if sufficient total capacitance is provided. Capacitor types (aluminum, ceramic, and tantalum) can be mixed in parallel, but the total equivalent input capacitance/ESR must be defined as above to assure stable operation. IMPORTANT: The input capacitor must maintain its ESR and capacitance in the stable range over the entire temperature range of the application to assure stability (see the Capacitor Characteristics section). 8.2.2.1.2 Output Capacitor An output capacitor is also required for loop stability. It must be located less than 1 cm from the LP3961 or LP3964 device and connected directly to the OUT and GND pins using traces which have no other currents flowing through them (see the Layout Guidelines section). The minimum value of the output capacitance that can be used for stable full-load operation is 33 µF, but it may be increased without limit. The ESR of the output capacitor is critical because it forms a zero to provide phase lead which is required for loop stability. The ESR must fall within the specified range: 0.2 Ω ≤ COUT ESR ≤ 5 Ω (2) The lower limit of 200 mΩ means that ceramic capacitors are not suitable for use as LP3961 or LP3964 output capacitors (but can be used on the input). Some ceramic capacitance can be used on the output if the total equivalent ESR is in the stable range: when using a 100-µF Tantalum as the output capacitor, approximately 3 µF of ceramic capacitance can be applied before stability becomes marginal. IMPORTANT: The output capacitor must meet the requirements for minimum amount of capacitance and also have an appropriate ESR value over the full temperature range of the application to assure stability (see the Capacitor Characteristics section). Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3961 LP3964 15 LP3961, LP3964 SNVS056J – MAY 2000 – REVISED JUNE 2015 www.ti.com 8.2.2.2 Selecting a Capacitor It is important to note that capacitance tolerance and variation with temperature must be taken into consideration when selecting a capacitor so that the minimum required amount of capacitance is provided over the full operating temperature range. In general, a good Tantalum capacitor will show very little capacitance variation with temperature, but a ceramic may not be as good (depending on dielectric type). Aluminum electrolytics also typically have large temperature variation of capacitance value. Equally important to consider is a capacitor's ESR change with temperature: this is not an issue with ceramics, as their ESR is extremely low. However, it is very important in Tantalum and aluminum electrolytic capacitors. Both show increasing ESR at colder temperatures, but the increase in aluminum electrolytic capacitors is so severe they may not be feasible for some applications (see the Capacitor Characteristics section). 8.2.2.3 Capacitor Characteristics 8.2.2.3.1 Ceramic For values of capacitance in the 10- to 100-µF range, ceramics are usually larger and more costly than Tantalums but give superior AC performance for bypassing high-frequency noise because of very low ESR (typically less than 10 mΩ). However, some dielectric types do not have good capacitance characteristics as a function of voltage and temperature. Z5U and Y5V dielectric ceramics have capacitance that drops severely with applied voltage. A typical Z5U or Y5V capacitor can lose 60% of its rated capacitance with half of the rated voltage applied to it. The Z5U and Y5V also exhibit a severe temperature effect, losing more than 50% of nominal capacitance at high and low limits of the temperature range. X7R and X5R dielectric ceramic capacitors are strongly recommended if ceramics are used, as they typically maintain a capacitance range within ±20% of nominal over full operating ratings of temperature and voltage. Of course, they are typically larger and more costly than Z5U/Y5U types for a given voltage and capacitance. 8.2.2.3.2 Tantalum Solid Tantalum capacitors are recommended for use on the output because their typical ESR is very close to the ideal value required for loop compensation. They also work well as input capacitors if selected to meet the ESR requirements previously listed. Tantalums also have good temperature stability: a good quality Tantalum will typically show a capacitance value that varies less than 10 to 15% across the full temperature range of 125°C to −40°C. ESR will vary only about 2X going from the high to low temperature limits. The increasing ESR at lower temperatures can cause oscillations when marginal quality capacitors are used (if the ESR of the capacitor is near the upper limit of the stability range at room temperature). 8.2.2.3.3 Aluminum This capacitor type offers the most capacitance for the money. The disadvantages are that they are larger in physical size, not widely available in surface mount, and have poor AC performance (especially at higher frequencies) due to higher ESR and ESL. Compared by size, the ESR of an aluminum electrolytic is higher than either Tantalum or ceramic, and it also varies greatly with temperature. A typical aluminum electrolytic can exhibit an ESR increase of as much as 50X when going from 25°C down to −40°C. It should also be noted that many aluminum electrolytics only specify impedance at a frequency of 120 Hz, which indicates they have poor high-frequency performance. Only aluminum electrolytics that have an impedance specified at a higher frequency (from 20 kHz to 100 kHz) should be used for the LP396X. Derating must be applied to the manufacturer's ESR specification, because it is typically only valid at room temperature. Any applications using aluminum electrolytics should be thoroughly tested at the lowest ambient operating temperature where ESR is maximum. 16 Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3961 LP3964 LP3961, LP3964 www.ti.com SNVS056J – MAY 2000 – REVISED JUNE 2015 8.2.2.4 RFI and EMI Susceptibility Radio frequency interference (RFI) and electromagnetic interference (EMI) can degrade the performance of any integrated circuit because of the small dimensions of the geometries inside the device. In applications where circuit sources are present which generate signals with significant high-frequency energy content (> 1 MHz), care must be taken to ensure that this does not affect the IC regulator. If RFI and EMI noise is present on the input side of the LP396x regulator (such as applications where the input source comes from the output of a switching regulator), good ceramic bypass capacitors must be used at the input pin of the LP396x. If a load is connected to the LP396x output which switches at high speed (such as a clock), the high-frequency current pulses required by the load must be supplied by the capacitors on the LP396x output. Because the bandwidth of the regulator loop is less than 100 kHz, the control circuitry cannot respond to load changes above that frequency. The means the effective output impedance of the LP396x at frequencies above 100 kHz is determined only by the output capacitors. In applications where the load is switching at high speed, the output of the LP396x may need RF isolation from the load. It is recommended that some inductance be placed between the LP396x output capacitor and the load, and good RF bypass capacitors be placed directly across the load. PCB layout is also critical in high-noise environments, because RFI and EMI is easily radiated directly into PC traces. Noisy circuitry should be isolated from clean circuits where possible, and grounded through a separate path. At MHz frequencies, ground planes begin to look inductive and RFI/EMI can cause ground bounce across the ground plane. In multilayer PCB applications, care should be taken in layout so that noisy power and ground planes do not radiate directly into adjacent layers which carry analog power and ground. 8.2.2.5 Output Adjustment An adjustable output device has output voltage range of 1.216 V to 5.1 V. To obtain a desired output voltage, the following equation can be used with R1 always a 10-kΩ resistor. (3) For output stability, CF must be between 68 pF and 100 pF. 8.2.2.6 Turnon Characteristics for Output Voltages Programmed to 2.0 V or Below As VIN increases during start-up, the regulator output will track the input until VIN reaches the minimum operating voltage (typically about 2.2 V). For output voltages programmed to 2 V or below, the regulator output may momentarily exceed its programmed output voltage during start up. Outputs programmed to voltages above 2 V are not affected by this behavior. 8.2.2.7 Output Noise Noise is specified in two ways: • Spot noise or output noise density is the RMS sum of all noise sources, measured at the regulator output, at a specific frequency (measured with a 1-Hz bandwidth). This type of noise is usually plotted on a curve as a function of frequency. • Total output noise or broadband noise is the RMS sum of spot noise over a specified bandwidth, usually several decades of frequencies. Attention should be paid to the units of measurement. Spot noise is measured in units µV/√Hz or nV/√Hz and total output noise is measured in µV(rms). The primary source of noise in low-dropout regulators is the internal reference. In CMOS regulators, noise has a low-frequency component and a high-frequency component, which depend strongly on the silicon area and quiescent current. Noise can be reduced in two ways: by increasing the transistor area or by increasing the current drawn by the internal reference. Increasing the area will decrease the chance of fitting the die into a smaller package. Increasing the current drawn by the internal reference increases the total supply current (ground pin current). Using an optimized trade-off of ground pin current and die size, LP396x achieves low noise performance and low quiescent current operation. Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3961 LP3964 17 LP3961, LP3964 SNVS056J – MAY 2000 – REVISED JUNE 2015 www.ti.com The total output noise specification for LP396x is presented in the Electrical Characteristics table. The output noise density at different frequencies is represented by a curve under typical performance characteristics. 8.2.2.8 Shutdown Operation A CMOS logic level signal at the shutdown (SD) pin will turnoff the regulator. Pin SD must be actively terminated through a 10-kΩ pullup resistor for a proper operation. If this pin is driven from a source that actively pulls high and low (such as a CMOS rail-to-rail comparator), the pull-up resistor is not required. This pin must be tied to the IN pin if not used. 8.2.2.9 Maximum Output Current Capability LP3961 and LP3964 can deliver a continuous current of 800 mA over the full operating temperature range. A heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of the application. Under all possible conditions, the junction temperature must be within the range specified under operating conditions. The total power dissipation of the device is given by: PD = (VIN − VOUT) × IOUT + VIN × IGND (4) where IGND is the operating ground current of the device (specified under the Electrical Characteristics table). The maximum allowable temperature rise (TRmax) depends on the maximum ambient temperature (TAmax) of the application, and the maximum allowable junction temperature (TJmax): TRmax = TJmax− TAmax (5) The maximum allowable value for junction to ambient Thermal Resistance, RθJA, can be calculated using the formula: RθJA = TRmax / PD (6) LP3961 and LP3964 are available in TO-220, SFM/TO-263, and SOT-223 packages. The thermal resistance depends on amount of copper area or heat sink, and on air flow. 8.2.3 Application Curves Figure 24. Line Transient Response (IOUT = 800 mA) 18 Figure 25. Line Transient Response (IOUT = 800 mA) Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3961 LP3964 LP3961, LP3964 www.ti.com SNVS056J – MAY 2000 – REVISED JUNE 2015 9 Power Supply Recommendations The LP396x devices are designed to operate from an input voltage supply range between 2.5 V and 7 V. The input voltage range provides adequate headroom in order for the device to have a regulated output. This input supply must be well regulated. An input capacitor of at least 68 μF is required. 10 Layout 10.1 Layout Guidelines Good PC layout practices must be used or instability can be induced because of ground loops and voltage drops. The input and output capacitors must be directly connected to the IN, OUT, and GND pins of the LP396x using traces which do not have other currents flowing in them (Kelvin connect). The best way to do this is to lay out CIN and COUT near the device with short traces to the IN, OUT, and GND pins. The regulator ground pin should be connected to the external circuit ground so that the regulator and its capacitors have a single-point ground. It should be noted that stability problems have been seen in applications where vias to an internal ground plane were used at the ground points of the LP396x IC and the input and output capacitors. This was caused by varying ground potentials at these nodes resulting from current flowing through the ground plane. Using a singlepoint ground technique for the regulator and its capacitors fixed the problem. Because high current flows through the traces going into the IN pin and coming from the OUT pin, Kelvin connect the capacitor leads to these pins so there is no voltage drop in series with the input and output capacitors. 10.2 Layout Example SD ERROR Pullup Resistor Pullup Resistor OUT IN Input Capacitor Output Capacitor Ground Figure 26. LP3961 TO-263 Package Typical Layout Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3961 LP3964 19 LP3961, LP3964 SNVS056J – MAY 2000 – REVISED JUNE 2015 www.ti.com Layout Example (continued) SD SENSE Pull-up Resistor IN OUT Input Capacitor Output Capacitor Ground Figure 27. LP3964 TO-263 Package Typical Layout 10.3 Heatsinking TO-220 Packages The thermal resistance of a TO-220 package can be reduced by attaching it to a heatsink or a copper plane on a PC board. The heatsink to be used in the application should have a heatsink-to-ambient thermal resistance, RθHA ≤ RθJA − RθCH − RθJC (7) In this equation, RθCH is the thermal resistance from the junction to the surface of the heatsink and RθJC is the thermal resistance from the junction to the surface of the case. 20 Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3961 LP3964 LP3961, LP3964 www.ti.com SNVS056J – MAY 2000 – REVISED JUNE 2015 11 Device and Documentation Support 11.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY LP3961 Click here Click here Click here Click here Click here LP3964 Click here Click here Click here Click here Click here 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3961 LP3964 21 PACKAGE OPTION ADDENDUM www.ti.com 8-Dec-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) LP3961EMP-1.8/NOPB ACTIVE SOT-223 NDC 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LBAB LP3961EMP-2.5 NRND SOT-223 NDC 5 1000 Non-RoHS & Green Call TI Level-1-260C-UNLIM -40 to 125 LBBB LP3961EMP-2.5/NOPB ACTIVE SOT-223 NDC 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LBBB LP3961EMP-3.3 NRND SOT-223 NDC 5 1000 Non-RoHS & Green Call TI Level-1-260C-UNLIM -40 to 125 LAZB LP3961EMP-3.3/NOPB ACTIVE SOT-223 NDC 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LAZB LP3961EMP-5.0 NRND SOT-223 NDC 5 1000 Non-RoHS & Green Call TI Level-1-260C-UNLIM -40 to 125 LBSB LP3961EMP-5.0/NOPB ACTIVE SOT-223 NDC 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LBSB Samples LP3961EMPX-1.8/NOPB ACTIVE SOT-223 NDC 5 2000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LBAB Samples LP3961EMPX-2.5/NOPB ACTIVE SOT-223 NDC 5 2000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LBBB Samples LP3961EMPX-3.3 NRND SOT-223 NDC 5 2000 Non-RoHS & Green Call TI Level-1-260C-UNLIM -40 to 125 LAZB LP3961ES-1.8 NRND DDPAK/ TO-263 KTT 5 45 Non-RoHS & Green Call TI Level-3-235C-168 HR -40 to 125 LP3961ES -1.8 LP3961ES-1.8/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 RoHS-Exempt & Green SN Level-3-245C-168 HR -40 to 125 LP3961ES -1.8 Samples LP3961ES-2.5/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 RoHS-Exempt & Green SN Level-3-245C-168 HR -40 to 125 LP3961ES -2.5 Samples LP3961ES-3.3/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 RoHS-Exempt & Green SN Level-3-245C-168 HR -40 to 125 LP3961ES -3.3 Samples LP3961ESX-2.5/NOPB ACTIVE DDPAK/ TO-263 KTT 5 500 RoHS-Exempt & Green SN Level-3-245C-168 HR -40 to 125 LP3961ES -2.5 Samples LP3961ESX-3.3/NOPB ACTIVE DDPAK/ TO-263 KTT 5 500 RoHS-Exempt & Green SN Level-3-245C-168 HR -40 to 125 LP3961ES -3.3 Samples LP3964EMP-1.8/NOPB ACTIVE SOT-223 NDC 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LBFB Samples LP3964EMP-2.5/NOPB ACTIVE SOT-223 NDC 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LBHB Samples Addendum-Page 1 Samples Samples Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 8-Dec-2022 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) LP3964EMP-3.3/NOPB ACTIVE SOT-223 NDC 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LBJB LP3964EMP-ADJ NRND SOT-223 NDC 5 1000 Non-RoHS & Green Call TI Level-1-260C-UNLIM -40 to 125 LBPB LP3964EMP-ADJ/NOPB ACTIVE SOT-223 NDC 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LBPB Samples LP3964EMPX-2.5/NOPB ACTIVE SOT-223 NDC 5 2000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LBHB Samples LP3964EMPX-ADJ/NOPB ACTIVE SOT-223 NDC 5 2000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LBPB Samples LP3964ES-1.8 NRND DDPAK/ TO-263 KTT 5 45 Non-RoHS & Green Call TI Level-3-235C-168 HR -40 to 125 LP3964ES -1.8 LP3964ES-1.8/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 RoHS-Exempt & Green SN Level-3-245C-168 HR -40 to 125 LP3964ES -1.8 Samples LP3964ES-2.5/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 RoHS-Exempt & Green SN Level-3-245C-168 HR -40 to 125 LP3964ES -2.5 Samples LP3964ES-3.3/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 RoHS-Exempt & Green SN Level-3-245C-168 HR -40 to 125 LP3964ES -3.3 Samples LP3964ES-ADJ NRND DDPAK/ TO-263 KTT 5 45 Non-RoHS & Green Call TI Level-3-235C-168 HR -40 to 125 LP3964ES -ADJ LP3964ES-ADJ/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 RoHS-Exempt & Green SN Level-3-245C-168 HR -40 to 125 LP3964ES -ADJ Samples LP3964ESX-2.5/NOPB ACTIVE DDPAK/ TO-263 KTT 5 500 RoHS-Exempt & Green SN Level-3-245C-168 HR -40 to 125 LP3964ES -2.5 Samples LP3964ESX-3.3/NOPB ACTIVE DDPAK/ TO-263 KTT 5 500 RoHS-Exempt & Green SN Level-3-245C-168 HR -40 to 125 LP3964ES -3.3 Samples LP3964ESX-ADJ/NOPB ACTIVE DDPAK/ TO-263 KTT 5 500 RoHS-Exempt & Green SN Level-3-245C-168 HR -40 to 125 LP3964ES -ADJ Samples LP3964ET-ADJ/NOPB ACTIVE TO-220 NDH 5 45 RoHS & Green SN Level-1-NA-UNLIM -40 to 125 LP3964ET -ADJ Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 8-Dec-2022 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of