LP3962, LP3965
www.ti.com
SNVS066H – MAY 2000 – REVISED APRIL 2013
LP3962/LP3965 1.5A Fast Ultra Low Dropout Linear Regulators
Check for Samples: LP3962, LP3965
FEATURES
DESCRIPTION
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The LP3962/LP3965 series of fast ultra low-dropout
linear regulators operate from a +2.5V to +7.0V input
supply. Wide range of preset output voltage options
are available. These ultra low dropout linear
regulators respond very fast to step changes in load
which makes them suitable for low voltage
microprocessor applications. The LP3962/LP3965 are
developed on a CMOS process which allows low
quiescent current operation independent of output
load current. This CMOS process also allows the
LP3962/LP3965 to operate under extremely low
dropout conditions.
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Ultra Low Dropout Voltage
Low Ground Pin Current
Load Regulation of 0.04%
15µA Quiescent Current in Shutdown Mode
Specified Output Current of 1.5A DC
Available in SOT-223,SFM/TO-263 and TO-220
Packages
Output Voltage Accuracy ± 1.5%
Error Flag Indicates Output Status (LP3962)
Sense Option Improves Better Load
Regulation (LP3965)
Extremely Low Output Capacitor
Requirements
Overtemperature/Overcurrent Protection
−40°C to +125°C Junction Temperature Range
APPLICATIONS
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Microprocessor Power Supplies
GTL, GTL+, BTL, and SSTL Bus Terminators
Power Supplies for DSPs
SCSI Terminator
Post Regulators
High Efficiency Linear Regulators
Battery Chargers
Other Battery Powered Applications
Dropout Voltage: Ultra low dropout voltage; typically
38mV at 150mA load current and 380mV at 1.5A load
current.
Ground Pin Current: Typically 5mA at 1.5A load
current.
Shutdown Mode: Typically 15µA quiescent current
when the shutdown pin is pulled low.
Error Flag: Error flag goes low when the output
voltage drops 10% below nominal value (for LP3962).
SENSE: Sense pin improves regulation at remote
loads. (For LP3965)
Precision Output Voltage: Multiple output voltage
options are available ranging from 1.2V to 5.0V and
adjustable (LP3965), with a specified accuracy of
±1.5% at room temperature, and ±3.0% over all
conditions (varying line, load, and temperature).
Typical Application Circuits
*SD and ERROR pins must be pulled high through a 10kΩ pull-up resistor. Connect the ERROR pin to ground if this
function is not used. See Application Hints section for more information.
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2013, Texas Instruments Incorporated
LP3962, LP3965
SNVS066H – MAY 2000 – REVISED APRIL 2013
www.ti.com
*SD and ERROR pins must be pulled high through a 10kΩ pull-up resistor. Connect the ERROR pin to ground if this
function is not used. See Application Hints section for more information.
Block Diagram LP3962
2
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Copyright © 2000–2013, Texas Instruments Incorporated
Product Folder Links: LP3962 LP3965
LP3962, LP3965
www.ti.com
SNVS066H – MAY 2000 – REVISED APRIL 2013
Block Diagram LP3965
Block Diagram LP3965-ADJ
Connection Diagram
Figure 1. Top View
SOT-223-5 Package
Figure 2. Top View
TO-220-5 Package
Bent, Staggered Leads
Figure 3. Top View
SFM/TO-263-5 Package
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Copyright © 2000–2013, Texas Instruments Incorporated
Product Folder Links: LP3962 LP3965
3
LP3962, LP3965
SNVS066H – MAY 2000 – REVISED APRIL 2013
www.ti.com
Pin Descriptions for SOT-223-5 Package
LP3962
Pin #
Name
LP3965
Function
Name
Function
1
SD
Shutdown
SD
Shutdown
2
VIN
Input Supply
VIN
Input Supply
3
VOUT
4
ERROR
5
GND
Output Voltage
ERROR Flag
VOUT
SENSE/ADJ
Ground
GND
Output Voltage
Remote Sense Pin or Output
Adjust Pin
Ground
Pin Descriptions for TO-220-5 and SFM/TO-263-5 Packages
LP3962
Pin #
Name
LP3965
Function
Name
Function
1
SD
Shutdown
SD
Shutdown
2
VIN
Input Supply
VIN
Input Supply
3
GND
Ground
4
VOUT
Output Voltage
5
ERROR
ERROR Flag
GND
Ground
VOUT
Output Voltage
SENSE/ADJ
Remote Sense Pin or Output
Adjust Pin
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2)
−65°C to +150°C
Storage Temperature Range
Lead Temperature (Soldering, 5 sec.)
ESD Rating
260°C
(3)
Power Dissipation
2 kV
(4)
Internally Limited
−0.3V to +7.5V
Input Supply Voltage (Survival)
−0.3V to VIN+0.3V
Shutdown Input Voltage (Survival)
Output Voltage (Survival),
(5) (6)
−0.3V to +7.5V
,
IOUT (Survival)
Short Circuit Protected
Maximum Voltage for ERROR Pin
VIN+0.3V
Maximum Voltage for SENSE Pin
VOUT+0.3V
(1)
(2)
(3)
(4)
(5)
(6)
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Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which
the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and test conditions,
see Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.
At elevated temperatures, devices must be derated based on package thermal resistance. The devices in TO-220 package must be
derated at θjA = 50°C/W (with 0.5in2, 1oz. copper area), junction-to-ambient (with no heat sink). The devices in the SFM/TO-263
surface-mount package must be derated at θjA = 60°C/W (with 0.5in2, 1oz. copper area), junction-to-ambient. The devices in SOT-223
package must be derated at θjA = 90°C/W (with 0.5in2, 1oz. copper area), junction-to-ambient.
If used in a dual-supply system where the regulator load is returned to a negative supply, the LP396X output must be diode-clamped to
ground.
The output PMOS structure contains a diode between the VIN and VOUT terminals. This diode is normally reverse biased. This diode will
get forward biased if the voltage at the output terminal is forced to be higher than the voltage at the input terminal. This diode can
typically withstand 200mA of DC current and 1Amp of peak current.
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Copyright © 2000–2013, Texas Instruments Incorporated
Product Folder Links: LP3962 LP3965
LP3962, LP3965
www.ti.com
SNVS066H – MAY 2000 – REVISED APRIL 2013
Operating Ratings
(1)
2.5V to 7.0V
Shutdown Input Voltage (Operating)
−0.3V to VIN+0.3V
Input Supply Voltage (Operating),
Maximum Operating Current (DC)
1.5A
Operating Junction Temp. Range
−40°C to +125°C
(1)
The minimum operating value for VIN is equal to either [VOUT(NOM) + VDROPOUT] or 2.5V, whichever is greater.
Electrical Characteristics
LP3962/LP3965
Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range.
Unless otherwise specified: VIN = VO(NOM) + 1V, IL = 10 mA, COUT = 33µF, VSD = VIN-0.3V.
Symbol
Parameter
Conditions
Typ
(1)
LP3962/5
(2)
Units
Min
Max
0
-1.5
-3.0
+1.5
+3.0
%
1.198
1.180
1.234
1.253
V
Output Voltage Tolerance (3)
10 mA ≤ IL ≤ 1.5A
VOUT +1 ≤ VIN≤ 7.0V
VADJ
Adjust Pin Voltage (ADJ version)
10 mA ≤ IL ≤ 1.5A
VOUT +1.5V ≤ VIN≤ 7.0V
1.216
ΔV OL
Output Voltage Line Regulation
VOUT+1V
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