LP3971
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SNVS432V – JANUARY 2006 – REVISED MAY 2013
LP3971 Power Management Unit for Advanced Application Processors
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FEATURES
KEY SPECIFICATIONS
•
•
1
2
•
•
•
•
•
•
•
•
•
Compatible with Advanced Applications
Processors Requiring DVM (Dynamic Voltage
Management)
Three Buck Regulators for Powering High
Current Processor Functions or I/O's
6 LDO's for Powering RTC, Peripherals, and
I/O's
Backup Battery Charger with Automatic
Switch for Lithium-Manganese Coin Cell
Batteries and Super Capacitors
I2C Compatible High Speed Serial Interface
Software Control of Regulator Functions and
Settings
Precision Internal Reference
Thermal Overload Protection
Current Overload Protection
Tiny 40-pin 5x5 mm WQFN Package
•
Buck Regulators
– Programmable VOUT from 0.725 to 3.3V
– Up to 95% Efficiency
– Up to 1.6A Output Current
– ±3% Output Voltage Accuracy
LDO’s
– Programmable VOUT of 1.0V–3.3V
– ±3% output voltage accuracy
– 150/300/370 mA output currents
– LDO RTC 30 mA
– LDO 1 300 mA
– LDO 2 150 mA
– LDO 3 150 mA
– LDO 4 150 mA
– LDO 5 370 mA
– 100 mV (typ) dropout
APPLICATIONS
DESCRIPTION
•
•
•
•
•
The LP3971 is a multi-function, programmable Power
Management Unit, designed especially for advanced
application processors. The LP3971 is optimized for
low power handheld applications and provides 6 low
dropout, low noise linear regulators, three DC/DC
magnetic buck regulators, a back-up battery charger
and two GPIO’s. A high speed serial interface is
included to program individual regulator output
voltages as well as on/off control.
PDA Phones
Smart Phones
Personal Media Players
Digital Cameras
Application Processors
– Marvell PXA
– Freescale
– Samsung
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
LP3971
SNVS432V – JANUARY 2006 – REVISED MAY 2013
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Simplified Application Circuit
Back-up
Battery
VIN
+
-
LDO1
BUCK1
LDO2
LDO3
BUCK2
LP3971 PMU
LDO4
LDO5
BUCK3
SYNC
SCL
SDA
GPIO2
GPIO1/nCHG_EN
EXT_WAKEUP
SPARE
PWR_ON
nTEST_JIG
PWR_EN
nRSTI
SYS_EN
nRSTO
nBATT_FLT
RTC
Figure 1.
2
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Li-ion/polymer cell
14
31
20
Vin_BUCK1
26
Vin_BUCK2
VDDA
27
6
Vin_BUCK3
VIN
DC SOURCE
4.5 ± 5.5V
VinLDO4
Cvdd
4.7 PF
VinLDO5
See notes
+
LP3971 PMIC
SYNC
40
Cchg_det
4.7 PF
APPLICATION
PROCESSOR
35
Clock
divider
37 PWR_EN
Lsw1 2.2 PH
COMP
39
EOC
CPU
CORE
SW1
BUCK1
10 PF
VFB1
5
VinBUBATT 15
Lsw2 2.2 PH
19
Vout
Switch
+ -
VoutLDO_RTC
23
VIN
Wake up
LDO1
Power
ON-OFF
Logic
LDO3
7
12
Logic Control
and registers
LDO4
13
VinLDO5
25
LDORTC
LDO2
Cldo1
1.0 PF
PLL
Cldo4
0.47 PF
VoutLDO5
LDO5
VIN SYS_EN
VoutLDO2 8
Cldo3
0.47 PF
VoutLDO4
VinLDO4
PWR_EN
CODEC
AP_IO
VoutLDO3
RESET
Internal HW reset for
test purposes
MVT
Cldo2
0.47 PF
2
GPIO2 30
9
BG
36
VoutLDO1
GPIO1/nCHG_EN 29
nRSTI
UART
10 PF
28
SYS_EN
OSC
3
Lsw3 2.2 PH
SW3
VFB3
BUCK3
SPARE
USB
10 PF
32
PWR_ON 1
nTEST_JIG
VBUCK2
SW2
VFB2
BUCK2
Vout Switch
Power On
Reset
SRAM
Cldo5
0.47 PF
16 VoutLDO_RTC
CldoRTC
1.0 PF
See notes
3.3V
VDDA
RTC
10k
I2C
Thermal
Shutdown
22
I2C_SCL
10k
21 I2C_SDA
BIAS
24 nRSTO
vref
4
EXT_WAKEUP
17 nBATT_FLT
VREF
Cvrefh
10 nF
11
38
18
33
PGND1 PGND2 PGND3
34
BGND1,2,3
10
GND1
•
The I2C lines are pulled up via a I/O source
•
VINLDO4, 5 can either be powered from main battery source, or by a buck regulator or VIN.
Figure 2.
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Connection Diagrams
Figure 3. 40-Pin WQFN
Package Number RSB0040A
30 29 28 27 26 25 24 23 22 21
21 22 23 24 25 26 27 28 29 30
31
20
20
31
32
19
19
32
33
33
18
18
34
17
17
34
35
16
16
35
36
15
15
36
37
14
14
37
38
13
13
38
39
12
12
39
40
11
11
40
1
2
3
4
5
6
7
8
9 10
10 9
8
Top View
7
6
5
4
3
2
1
Bottom View
Note: Circle marks Pin 1 position.
Table 1. Default VOUT Coding
Z
Default VOUT
0
1.3
1
1.8
2
2.5
3
2.8
4
3.0
5
3.3
6
1.0
7
1.4
8
1.2
9
1.25
A
1.35
Y
Default Enable Option:
SYS_EN or PWR_EN
Pin Descriptions (1)
(1)
4
Pin #
Name
I/O
Type
1
PWR_ON
I
D
This is an active HI push button input which can be used to signal PWR_ON
and PWR_OFF events to the CPU by controlling the ext_wakup [pin4] and
select contents of register 8H'02
Description
2
nTEST_JIG
I
D
This is an active LOW input signal used for detecting an external HW event. The
response is seen in the ext_wakup [pin4] and select contents of register 8H'02
3
SPARE
I
D
This is an input signal used for detecting a external HW event. The response is
seen in the ext_wakup [pin4] and select contents of register 8H'02. The polarity
on this pin is assignable
4
EXT_WAKEUP
O
D
This pin generates a single 10mS pulse output to CPU in response to input from
pin[s] 1, 2, and 3. Flags CPU to interrogate register 8H'02
5
FB1
I
A
Buck1 input feedback terminal
6
VIN
I
PWR
Battery Input (Internal circuitry and LDO1-3 power input)
7
VOUT LDO1
O
PWR
LDO1 output
8
VOUT LDO2
O
PWR
LDO2 output
A: Analog Pin D: Digital Pin G: Ground Pin P: Power Pin I: Input Pin I/O: Input/Output Pin O: Output Pin
Note: In this document active low logic items are prefixed with a lowercase “n”
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Pin Descriptions(1) (continued)
Pin #
Name
I/O
Type
9
nRSTI
I
D
Active low Reset pin. Signal used to reset the IC (by default is pulled high
internally). Typically a push button reset.
Description
10
GND1
G
G
Ground
11
VREF
O
A
Bypass Cap. for the high internal impedance reference.
12
VOUT LDO3
O
PWR
LDO3 output
13
VOUT LDO4
O
PWR
LDO4 output
14
VIN LDO4
I
PWR
Power input to LDO4, this can be connected to either from a 1.8V supply to
main Battery supply.
15
VIN BUBATT
I
PWR
Back Up Battery input supply.
16
VOUT LDO_RTC
O
PWR
LDO_RTC output supply to the RTC of the application processor.
17
nBATT_FLT
O
D
Main Battery fault output, indicates the main battery is low
(discharged) or the dc source has been removed from the system. This gives
the processor an indicator that the power will shut down. During this time the
processor will operate from the back up coin cell.
18
PGND2
G
G
Buck2 NMOS Power Ground
19
SW2
O
PWR
Buck2 switcher output
20
VIN Buck2
I
PWR
Battery input power to Buck2
21
SDA
I/O
D
I2C Data (Bidirectional)
22
SCL
I
D
I2C Clock
23
FB2
I
A
Buck2 input feedback terminal
24
nRSTO
O
D
Reset output from the PMIC to the processor
25
VOUT LDO5
O
PWR
LDO5 output
26
VIN LDO5
I
PWR
Power input to LDO5, this can be connected to VIN or to a separate 1.8V supply.
27
VDDA
I
PWR
Analog Power for VREF, BIAS
28
FB3
I
A
Buck3 Feedback
29
GPIO1 /
nCHG_EN
I/O
D
General Purpose I/O / Ext. backup battery charger enable pin. This pin enables
the main battery / DC source power to charge the backup battery. This pin
toggled via the application processor. By grounding this pin the DC source
continuously charges the backup battery
30
GPIO2
I/O
D
General Purpose I/O
31
VIN Buck3
I
PWR
Battery input power to Buck3
32
SW3
O
PWR
Buck3 switcher output
33
PGND3
G
G
Buck3 NMOS Power Ground
34
BGND1,2,3
G
G
Bucks 1, 2 and 3 analog Ground
35
SYNC
I
D
Frequency Synchronization: Connection to an external clock signal PLL to
synchronize the PMIC internal oscillator.
36
SYS_EN
I
D
Input Digital enable pin for the high voltage power domain supplies. Output from
the Monahans processor.
37
PWR_EN
I
D
Digital enable pin for the Low Voltage domain supplies. Output signal from the
Monahans processor
38
PGND1
G
G
Buck1 NMOS Power Ground
39
SW1
O
PWR
Buck1 Switcher output
40
VIN Buck1
I
PWR
Battery input power to Buck1
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings (1) (2)
−0.3V to +6.5V
All Inputs
GND to GND SLUG
±0.3V
Junction Temperature (TJ-MAX)
150°C
−65°C to +150°C
Storage Temperature
Power Dissipation
(TA = 70°C) (3)
3.2W
Junction-to-Ambient Thermal
Resistance θJA (3)
25°C/W
Maximum Lead Temp (Soldering)
ESD Rating
260°C
(4)
Human Body Model
2 kV
Machine Model
(1)
(2)
(3)
(4)
200V
If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test
conditions, see the Electrical Characteristics tables.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAXOP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance
of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA x PD-MAX).
The Human body model is a 100 pF capacitor discharged through a 1.5 k Ω resistor into each pin. (MIL-STD-883 3015.7) The machine
model is a 200 pF capacitor discharged directly into each pin. (EAIJ)
Operating Ratings
VIN LDO 4,5
2.7V to 5.5V
VEN
1.74 to (VIN
−40°C to +125°C
Junction Temperature (TJ)
Operating Temperature (TA)
−40°C to +85°C
Maximum Power Dissipation
(TA = 70°C) (1) (2)
2.2W
(1)
(2)
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAXOP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance
of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA x PD-MAX).
Junction-to-ambient thermal resistance (θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set
forth in the JEDEC standard JESD51–7. The test board is a 4-layer FR-4 board measuring 102 mm x 76 mm x 1.6 mm with a 2x1 array
of thermal vias. The ground plane on the board is 50 mm x 50 mm. Thickness of copper layers are 36 µm/1.8 µm/18 µm/36 µm (1.5 oz/1
oz/1 oz/1.5 oz). Ambient temperature in simulation is 22°C, still air. Power dissipation is 1W. Junction-to-ambient thermal resistance is
highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid
to thermal dissipation issues in board design. The value of θJA of this product can vary significantly, depending on PCB material, layout,
and environmental conditions. In applications where high maximum power dissipation exists (high VIN, high IOUT), special care must be
paid to thermal dissipation issues. For more information on these topics, please refer to Application Note 1187: Leadless Leadframe
Package (LLP) and the Power Efficiency and Power Dissipation section of this datasheet.
General Electrical Characteristics (1)
Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the
entire junction temperature range for operation, −40°C to +125°C. (2) (3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VIN, VDDA, VIN Buck1, 2
and 3
Battery Voltage
2.7
3.6
5.5
V
VINLDO4, VINLDO5
Power Supply for LDO 4 and 5
1.74
3.6
5.5
V
(1)
(2)
(3)
6
No input supply should be higher then VDDA
All voltages are with respect to the potential at the GND pin.
All limits specified at room temperature and at temperature extremes. All room temperature limits are production tested, specified
through statistical analysis or by design. All limits at temperature extremes are specified via correlation using standard Statistical Quality
Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
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General Electrical Characteristics(1) (continued)
Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the
entire junction temperature range for operation, −40°C to +125°C.(2) (3)
Symbol
Parameter
TSD
(4)
Thermal Shutdown
Conditions
(4)
Min
Typ
Temperature
160
Hysteresis
20
Max
Units
°C
Specified by design.Not prodution tested.
Supply Specification (1) (2)
IMAX
Maximum Output
VOUT (Volts)
Supply
Range (V)
LDO_RTC
(1)
(2)
(3)
(4)
Resolution (mV)
(4)
Tracking
Current (mA)
N/A
30 or 10
LDO1
1.8 to 3.3
100
300
LDO2
1.8 to 3.3
100
150
LDO3
1.8 to 3.3
100
150
LDO4
1.0 to 3.3
50-600
150
LDO5
1.0 to 3.3
50-600
370
BUCK 1
0.8 to 3.3
50-600
1600
BUCK 2
0.8 to 3.3
50-600
1600
BUCK 3
0.8 to 3.3
50-600
1600
(3)
All voltages are with respect to the potential at the GND pin.
All limits specified at room temperature and at temperature extremes. All room temperature limits are production tested, specified
through statistical analysis or by design. All limits at temperature extremes are specified via correlation using standard Statistical Quality
Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
Specified by design. Not production tested. design.
LDO_RTC voltage can track LDO1 voltage. LP3971 has a tracking function (nIO_TRACK). When enabled, LDO_RTC voltage will track
LDO1 voltage within 200mV down to 2.8V when LDO1 is enabled
Default Voltage Options
Version
Enable
LDO_RTC
LP3971SQ-B410
LP3971SQ-D510
Version B
LP3971Q-F211
Version C
LP3971SQ-W416
Version A
Version SW
--
2.8
--
2.8
--
2.8
--
2.8
LDO1
SYS_EN
3.0 (w/
Trkg)
SYS_EN
3.3 (w/
Trkg)
SYS_EN
3.3
SYS_EN
3.0
LDO2
SYS_EN
3.0
SYS_EN
3.3
SYS_EN
3.3
SYS_EN
3.3
LDO3
SYS_EN
3.0
SYS_EN
3.3
SYS_EN
3.3
PWR_EN
2.5
LDO4
PWR_EN
1.3
PWR_EN
1.3
SYS_EN
1.8
SYS_EN
1.0
LDO5
PWR_EN
1.1
PWR_EN
1.1
PWR_EN
3.3
PWR_EN
1.0
BUCK1
PWR_EN
1.4
PWR_EN
1.4
PWR_EN
1.5
PWR_EN
1.2
BUCK2
SYS_EN
3.0
SYS_EN
3.3
SYS_EN
2.5
SYS_EN
3.0
BUCK3
SYS_EN
1.8
SYS_EN
1.8
SYS_EN
1.8
SYS_EN
1.8
Version
LP3971SQ-N510
LP3971SQ-P55A
LP3971SQ-B510
LP3971SQ-O509
Enable
set to default 00 on system
enable delay
LDO_RTC
Track
2.8
No Track
2.8
Track
2.8
NoTrack
2.8
LDO1
SYS_EN
3.3
SYS_EN
3.3
SYS_EN
3.0
SYS_EN
3.3
LDO2
SYS_EN
3.0
SYS_EN
3.3
SYS_EN
3.0
SYS_EN
3.3
LDO3
SYS_EN
3.0
SYS_EN
3.3
SYS_EN
3.0
PWR_EN
3.3
LDO4
PWR_EN
1.3
SYS_EN
1.35
PWR_EN
1.3
SYS_EN
1.25
LDO5
PWR_EN
1.1
PWR_EN
1.8
PWR_EN
1.1
SYS_EN
1.25
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BUCK1
PWR_EN
1.4
PWR_EN
1.35
PWR_EN
1.4
PWR_EN
3.3
BUCK2
SYS_EN
3.3
SYS_EN
3.3
SYS_EN
3.3
SYS_EN
3.3
BUCK3
SYS_EN
1.8
SYS_EN
3.3
SYS_EN
1.8
SYS_EN
1.3
Version
LP3971SQ-G824
LP3971SQ-Q418
LP3971SQ-2G16
Enable
LDO_RTC
No
Track
2.8
No Track
2.8
No Track
2.8
LDO1
SYS_
EN
2.5
SYS_EN
3.0
SYS_EN
3.3
LDO2
SYS_
EN
2.5
SYS_EN
3.0
SYS_EN
3.3
LDO3
SYS_
EN
3.3
PWR_EN
3.3
PWR_EN
3.3
LDO4
SYS_
EN
3.0
SYS_EN
1.2
SYS_EN
1.0
LDO5
PWR_
EN
2.5
PWR_EN
1.2
PWR_EN
1.0
BUCK1
PWR_
EN
3.3
PWR_EN
1.35
PWR_EN
1.0
BUCK2
SYS_
EN
1.2
SYS_EN
3.0
PWR_EN
1.1
BUCK3
SYS_
EN
2.5
SYS_EN
1.8
SYS_EN
1.8
Version
LP3971SQ-7848
Enable
LDO_RTC
No Track
2.8
LDO1
SYS_EN
3.0
LDO2
SYS_EN
2.6
LDO3
SYS_EN
3.3
LDO4
SYS_EN
1.2
LDO5
SYS_EN
1.8
BUCK1
PWR_EN
1.2
BUCK2
PWR_EN
1.2
BUCK3
SYS_EN
3.0
Version
LP3971SQ-8858
Enable
8
LDO_RTC
No Track
2.8
LDO1
SYS_EN
3.3
LDO2
SYS_EN
3.3
LDO3
SYS_EN
3.3
LDO4
SYS_EN
1.2
LDO5
SYS_EN
1.8
BUCK1
PWR_EN
1.2
BUCK2
PWR_EN
1.2
BUCK3
SYS_EN
3.3
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LDO RTC
Unless otherwise noted, VIN = 3.6V, CIN = 1.0 μF, COUT = 0.47 µF, COUT (VRTC) = 1.0 μF ceramic. Typical values and limits
appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature
range for operation, −40°C to +125°C. (1) (2) (3) and (4)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
2.632
2.8
2.968
V
0.15
%/V
VOUT
Accuracy
Output Voltage Accuracy
VIN Connected, Load Current = 1 mA
ΔVOUT
Line Regulation
VIN = (VOUT nom + 1.0V) to 5.5V
Current = 1 mA
Load Regulation
From Main Battery
Load Current = 1 mA to 30 mA
0.05
From Backup Battery
VIN = 3.0V
Load Current = 1 mA to 10 mA
0.5
ISC
Short Circuit Current Limit
(5)
Load
From Main Battery
VIN = VOUT +0.3V to 5.5V
100
From Backup Battery
30
%/mA
mA
VIN - VOUT
Dropout Voltage
Load Current = 10 mA
IQ_Max
Maximum Quiescent Current
IOUT = 0 mA
30
μA
TP1
RTC LDO Input Switched from Main Battery VIN Falling
to Backup Battery
2.9
V
TP2
RTC LDO Input Switched from Backup
Battery to Main Battery
VIN Rising
3.0
V
CO
Output Capacitor
Capacitance for Stability
ESR
(1)
(2)
(3)
(4)
(5)
375
0.7
5
mV
μF
1.0
500
mΩ
All voltages are with respect to the potential at the GND pin.
All limits specified at room temperature and at temperature extremes. All room temperature limits are production tested, specified
through statistical analysis or by design. All limits at temperature extremes are specified via correlation using standard Statistical Quality
Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value.
LDO_RTC voltage can track LDO1 voltage. LP3971 has a tracking function (nIO_TRACK). When enabled, LDO_RTC voltage will track
LDO1 voltage within 200mV down to 2.8V when LDO1 is enabled.
VIN minimum for line regulation values is 2.7V for LDOs 1–3 and 1.8V for LDOs 4 and 5. Condition does not apply to input voltages
below the minimum input operating voltage.
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LDO 1 to 5
Unless otherwise noted, VIN = 3.6V, CIN = 1.0 μF, COUT = 0.47 µF, COUT (VRTC) = 1.0 μF ceramic. Typical values and limits
appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature
range for operation, −40°C to +125°C. (1) (2) (3) (4) (5) (6) and (7).
Symbol
Parameter
Conditions
Min
Typ
Output Voltage Accuracy (Default VOUT)
Load Current = 1 mA
ΔVOUT
Line Regulation
VIN =3.1V to 5.0V,
Load Regulation
VIN = 3.6V,
Load Current = 1 mA to IMAX
Short Circuit Current Limit
LDO1–4, VOUT = 0V
400
LDO5, VOUT = 0V
500
ISC
(8)
Load Current = 1 mA
(3)
VIN - VOUT
Dropout Voltage
Load Current = 50 mA
PSRR
Power Supply Ripple Rejection
f = 10 kHz, Load Current = IMAX
45
IQ
Quiescent Current “On”
IOUT = 0 mA
40
Quiescent Current “On”
IOUT = IMAX
Quiescent Current “Off”
EN is de-asserted
TON
Turn On Time
Start up from Shut-down
COUT
Output Capacitor
Capacitance for Stability
0°C ≤ TJ ≤ 125°C
0.33
0.47
−40°C ≤ TJ ≤ 125°C
0.68
1.0
(3)
(4)
(5)
(6)
(7)
(8)
Units
3
%
0.15
%/V
0.011
%/mA
mA
150
mV
dB
60
µA
0.03
μsec
300
µF
ESR
(1)
(2)
Max
−3
VOUT
Accuracy
5
500
mΩ
All voltages are with respect to the potential at the GND pin.
All limits specified at room temperature and at temperature extremes. All room temperature limits are production tested, specified
through statistical analysis or by design. All limits at temperature extremes are specified via correlation using standard Statistical Quality
Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value.
LDO_RTC voltage can track LDO1 voltage. LP3971 has a tracking function (nIO_TRACK). When enabled, LDO_RTC voltage will track
LDO1 voltage within 200mV down to 2.8V when LDO1 is enabled.
VIN minimum for line regulation values is 2.7V for LDOs 1–3 and 1.8V for LDOs 4 and 5. Condition does not apply to input voltages
below the minimum input operating voltage.
An increase in the load current results in a slight decrease in the output voltage and vice versa.
Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This
specification does not apply for input voltages below 2.7V for LDOs 1–3 and 1.8V for LDOs 4 and 5.
VIN minimum for line regulation values is 2.7V for LDOs 1–3 and 1.8V for LDOs 4 and 5. Condition does not apply to input voltages
below the minimum input operating voltage.
LDO Dropout Voltage vs. Load Current Collect Data For All LDO’s
Dropout Voltage
vs.
Load Current
Change in Output Voltage
vs.
Load Current
200
CHANGE IN OUTPUT VOLTAGE (mV)
300
DROPOUT VOLTAGE (mV)
250
200
150
100
REG1 3.3V OUTPUT
50
150
100
REG1 3.3V OUTPUT
REG2 2.5V OUTPUT
50
REG3 1.3V OUTPUT
0
-50
VIN = 3.6V
0
10
0
200
400
600
800
1000
1200
-100
0
200
400
600
800
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 4.
Figure 5.
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1200
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LDO1 Line Regulation
VOUT = 1.8 volts VIN 3 to 4 volts Load = 100 mA
LDO1 Load Transient
VIN = 4.1 volts VOUT = 1.8 volts no-load-100 mA
4.03 Ps
4.0 Ps
Figure 6.
Figure 7.
Enable Start-up time (LDO1)
LDO1 channel 2 LDO4 Channel 1 Sys_enable from 0 volts Load = 100mA
4.03 Ps
Figure 8.
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Buck Converters SW1, SW2, SW3
Unless otherwise noted, VIN = 3.6V, CIN = 10 μF, COUT = 10 μF, LOUT = 2.2 μH ceramic. Typical values and limits appearing in
normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for
operation, −40°C to +125°C. (1) (2) (3) and (4).
Symbol
Parameter
Conditions
Min
Output Voltage Accuracy
Default VOUT
Eff
Efficiency
Load Current = 500 mA
ISHDN
Shutdown Supply Current
EN is de-asserted
Sync Mode Clock Frequency
Synchronized from 13 MHz System
Clock
fOSC
Internal Oscillator Frequency
IPEAK
Peak Switching Current Limit
IQ
Quiescent Current “On”
Typ
−3
VOUT
Max
Units
+3
%
95
%
μA
0.1
10.4
13
15.6
2.0
MHz
2.1
No Load PFM Mode
21
No Load PWM Mode
200
MHz
2.4
A
μA
RDSON (P)
Pin-Pin Resistance PFET
240
RDSON (N)
Pin-Pin Resistance NFET
200
mΩ
TON
Turn On Time
Start up from Shut-down
500
μsec
CIN
Input Capacitor
Capacitance for Stability
8
µF
CO
Output Capacitor
Capacitance for Stability
8
µF
(1)
(2)
(3)
(4)
mΩ
All voltages are with respect to the potential at the GND pin.
All limits specified at room temperature and at temperature extremes. All room temperature limits are production tested, specified
through statistical analysis or by design. All limits at temperature extremes are specified via correlation using standard Statistical Quality
Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
The input voltage range recommended for ideal applications performance for the specified output voltages is given below:VIN = 2.7V to
5.5V for 0.80V < VOUT < 1.8VVIN = (VOUT+ 1V) to 5.5V for 1.8V ≤ VOUT ≤ 3.3V
Test condition: for VOUT less than 2.7V, VIN = 3.6V; for VOUT greater than or equal to 2.7V, VIN = VOUT+ 1V.
Buck 1 Output Efficiency vs. Load Current Varied from 1mA to 1.5 Amps
VIN = 3, 3.5 volts VOUT = 1.4 volts Forced PWM
VIN = 4.0, 4.5 volts VOUT = 1.4 volts Forced PWM
100.00
90.00
VIN = 3V
VIN = 3.5V
60.00
40.00
20.00
54.00
VIN = 4.5V
36.00
18.00
0.00
0.00
1
1e1
1e2
1e3
1
1e4
OUTPUT CURRENT (mA)
1e1
1e2
1e3
1e4
OUTPUT CURRENT (mA)
Figure 9.
12
VIN = 4V
72.00
EFFICIENCY (%)
EFFICIENCY (%)
80.00
Figure 10.
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Line Transient Response
VIN = 3, 3.6 V, VOUT = 1.2 V, 250 mA load
VIN = 3, 3.5 volts VOUT = 1.4 volts Forced PWM
90.00
VIN = 5.5V
EFFICIENCY (%)
72.00
VIN = 5V
54.00
36.00
18.00
0.00
1
1e1
1e2
1e3
4.03 Ps
1e4
OUTPUT CURRENT (mA)
Figure 11.
Figure 12.
Mode Change
Load transients 20 mA to 560 mA
VOUT = 1.4 volts [PFM to PWM] VIN = 4.1 volts
Load Transient
3.6 VIN, 3.3 VOUT, 0 – 100 mA load
4.03 Ps
4.0 Ps
Figure 13.
Figure 14.
Startup
Startup into PWM Mode 980 mA [channel 2]
VOUT = 1.4 volts VIN = 4.1 volts
4.03 Ps
Figure 15.
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Back-Up Charger Electrical Characteristics
Unless otherwise noted, VIN = VBATT = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits
appearing in boldface type apply over the entire junction temperature range for operation, −40°C to +125°C. (1) (2) and (3).
Symbol
Parameter
Conditions
Min
VIN
Operational Voltage Range
Voltage at VIN
IOUT
Backup Battery Charging Current
VIN = 3.6V, Backup_Bat = 2.5V, Backup
Battery Charger Enabled (3)
VOUT
Charger Termination Voltage
VIN = 5.0V Backup Battery Charger
Enabled. Programmable
Backup Battery Charger Short Circuit
Current
PSRR
Typ
3.3
Max
Units
5.5
V
190
μA
3.1
V
Backup_Bat = 0V, Backup Battery Charger
Enabled
9
mA
Power Supply Ripple Rejection Ratio
IOUT ≤ 50 μA, VOUT = 3.15V
VOUT + 0.4 ≤ VBATT = VIN ≤ 5.0V
f < 10 kHz
15
dB
IQ
Quiescent Current
IOUT < 50 μA
25
μA
COUT
Output Capacitance
0 μA ≤ IOUT ≤ 100 μA
0.1
μF
Output Capacitor ESR
(1)
(2)
(3)
2.91
5
500
mΩ
All voltages are with respect to the potential at the GND pin.
All limits specified at room temperature and at temperature extremes. All room temperature limits are production tested, specified
through statistical analysis or by design. All limits at temperature extremes are specified via correlation using standard Statistical Quality
Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
Back-up battery charge current is programmable via the I2C compatible interface. Refer to the Application Section for more information.
LP3971 Battery Switch Operation
The LP3971 has provisions for two battery connections, the main battery Vbat and Backup Battery.
The function of the battery switch is to connect power to the RTC LDO from the appropriate battery, depending
on conditions described below:
• If only the backup battery is applied, the switch will automatically connect the RTC LDO power to this battery.
• If only the main battery is applied, the switch will automatically connect the RTC LDO power to this battery.
• If both batteries are applied, and the main battery is sufficiently charged (Vbat > 3.1V), the switch will
automatically connect the RTC LDO power to the main battery.
• As the main battery is discharged a separate circuit called nBATT_FLT will warn the system. Then if no action
is taken to restore the charge on the main battery, and discharging is continued the battery switch will
disconnect the input of the RTC_LDO from the main battery and connect to the backup battery.
• The main battery voltage at which the RTC LDO is switched over from main to backup battery is 2.8V
typically.
• There is a hysteric voltage in this switch operation so; the RTC LDO will not be reconnected to main battery
until main battery voltage is greater than 3.1V typically.
• The system designer may wish to disable the battery switch when only a main battery is used. This is
accomplished by setting the “no back up battery bit” in the control register 8h’0B bit 7 NBUB. With this bit set
to “1”, the above described switching will not occur, that is the RTC LDO will remain connected to the main
battery even as it is discharged below the 2.9V threshold. The Backup battery input should also be connected
to main battery.
14
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Logic Inputs and Outputs DC Operating Conditions
(1)
Logic Inputs (SYS_EN, PWR_EN, SYNC, nRSTI, PWR_ON, nTEST_JIG, SPARE and GPI's)
Symbol
Parameter
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
ILEAK
Input Leakage Current
(1)
Conditions
Min
Max
Units
0.5
V
VRTC
−0.5V
V
−1
+1
µA
Min
Max
Units
0.5
V
All voltages are with respect to the potential at the GND pin.
Logic Outputs (nRSTO, EXT_WAKEUP and GPO's)
Symbol
Parameter
Conditions
VOL
Output Low Level
Load = +0.2 mA = IOL Max
VOH
Output High Level
Load = −0.1 mA = IOL Max
ILEAK
Output Leakage Current
VON = VIN
VRTC
−0.5V
V
+5
µA
Logic Output (nBATT_FLT)
Symbol
Conditions
Min
Typ
Max
Units
nBATT_FLT Threshold Voltage
Parameter
Programmable via Serial Interface Default =
2.8V
2.4
2.8
3.4
V
VOL
Output Low Level
Load = +0.4 mA = IOL Max
0.5
V
VOH
Output High Level
Load = −0.2 mA = IOH Max
ILEAK
Input Leakage Current
VRTC
−0.5V
V
+5
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I2C Compatible Serial Interface Electrical Specifications (SDA and SCL)
Unless otherwise noted, VIN = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing
in boldface type apply over the entire junction temperature range for operation, −40°C to +125°C. (1) (2) and (3)
Max
Units
VIL
Symbol
Low Level Input Voltage
Parameter
(4)
Conditions
−0.5
0.3
VRTC
V
VIH
High Level Input Voltage
(4)
0.7
VRTC
VRTC
VOL
Low Level Output Voltage
(4)
0
0.2
VTRC
IOL
Low Level Output Current
VOL = 0.4V
(4)
Min
Typ
3.0
mA
FCLK
Clock Frequency
(4)
tBF
Bus-Free Time Between Start and Stop
(4)
1.3
μs
tHOLD
Hold Time Repeated Start Condition
(4)
0.6
μs
tCLKLP
CLK Low Period
(4)
1.3
μs
tCLKHP
CLK High Period
(4)
0.6
μs
tSU
Set Up Time Repeated Start Condition
(4)
0.6
μs
tDATAHLD
Data Hold Time
(4)
0
μs
tCLKSU
Data Set Up Time
(4)
100
ns
TSU
Set Up Time for Start Condition
(4)
0.6
TTRANS
Maximum Pulse Width of Spikes that Must
be Suppressed by the Input Filter of Both
DATA & CLK Signals
(4)
(1)
(2)
(3)
(4)
16
400
kHz
μs
50
ns
All voltages are with respect to the potential at the GND pin.
All limits specified at room temperature and at temperature extremes. All room temperature limits are production tested, specified
through statistical analysis or by design. All limits at temperature extremes are specified via correlation using standard Statistical Quality
Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
The I2C signals behave like open-drain outputs and require an external pull-up resistor on the system module in the 2 kΩ to 20 kΩ
range.
Specified by design. Not production tested
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BUCK CONVERTER OPERATION
DEVICE INFORMATION
The LP3971 includes three high efficiency step down DC-DC switching buck converters. Using a voltage mode
architecture with synchronous rectification, the buck converters have the ability to deliver up to 1600 mA
depending on the input voltage, output voltage, ambient temperature and the inductor chosen.
There are three modes of operation depending on the current required - PWM, PFM, and shutdown. The device
operates in PWM mode at load currents of approximately 100 mA or higher, having voltage tolerance of ±3%
with 95% efficiency or better. Lighter load currents cause the device to automatically switch into PFM for reduced
current consumption. Shutdown mode turns off the device, offering the lowest current consumption (IQ, SHUTDOWN
= 0.01 µA typ).
Additional features include soft-start, under voltage protection, current overload protection, and thermal shutdown
protection.
The part uses an internal reference voltage of 0.5V. It is recommended to keep the part in shutdown until the
input voltage is 2.7V or higher.
CIRCUIT OPERATION
The buck converter operates as follows. During the first portion of each switching cycle, the control block turns
on the internal PFET switch. This allows current to flow from the input through the inductor to the output filter
capacitor and load. The inductor limits the current to a ramp with a slope of (VIN–VOUT)/L, by storing energy in a
magnetic field.
During the second portion of each cycle, the controller turns the PFET switch off, blocking current flow from the
input, and then turns the NFET synchronous rectifier on. The inductor draws current from ground through the
NFET to the output filter capacitor and load, which ramps the inductor current down with a slope of –VOUT/L.
The output filter stores charge when the inductor current is high, and releases it when inductor current is low,
smoothing the voltage across the load.
The output voltage is regulated by modulating the PFET switch on time to control the average current sent to the
load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and
synchronous rectifier at the SW pin to a low-pass filter formed by the inductor and output filter capacitor. The
output voltage is equal to the average voltage at the SW pin.
PWM OPERATION
During PWM operation the converter operates as a voltage mode controller with input voltage feed forward. This
allows the converter to achieve good load and line regulation. The DC gain of the power stage is proportional to
the input voltage. To eliminate this dependence, feed forward inversely proportional to the input voltage is
introduced.
While in PWM (Pulse Width Modulation) mode, the output voltage is regulated by switching at a constant
frequency and then modulating the energy per cycle to control power to the load. At the beginning of each clock
cycle the PFET switch is turned on and the inductor current ramps up until the comparator trips and the control
logic turns off the switch. The current limit comparator can also turn off the switch in case the current limit of the
PFET is exceeded. Then the NFET switch is turned on and the inductor current ramps down. The next cycle is
initiated by the clock turning off the NFET and turning on the PFET.
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VSW
2V/DIV
IL
200 mA/DIV
VIN = 3.6V
VOUT = 1.5V
IOUT = 400 mA
VOUT
10 mV/DIV
AC Coupled
TIME (200 ns/DIV)
Figure 16. Typical PWM Operation
Internal Synchronous Rectification
While in PWM mode, the converters uses an internal NFET as a synchronous rectifier to reduce rectifier forward
voltage drop and associated power loss. Synchronous rectification provides a significant improvement in
efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier
diode.
Current Limiting
A current limit feature allows the converters to protect itself and external components during overload conditions.
PWM mode implements current limiting using an internal comparator that trips at 2.0 A (typ). If the output is
shorted to ground the device enters a timed current limit mode where the NFET is turned on for a longer duration
until the inductor current falls below a low threshold, ensuring inductor current has more time to decay, thereby
preventing runaway.
PFM OPERATION
At very light loads, the converter enters PFM mode and operates with reduced switching frequency and supply
current to maintain high efficiency.
The part will automatically transition into PFM mode when either of two conditions occurs for a duration of 32 or
more clock cycles:
A:
The inductor current becomes discontinuous.
B:
The peak PMOS switch current drops below the IMODE level, (Typically IMODE < 30 mA + VIN/42Ω).
2V/DIV
VSW
IL
200 mA/DIV
VIN = 3.6V
VOUT = 1.5V
IOUT = 20 mA
VOUT
20 mV/DIV
AC Coupled
TIME (4 Ps/DIV)
Figure 17. Typical PFM Operation
18
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During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage
during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy
load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output
FETs such that the output voltage ramps between
Input
0
1
0
X
Output = 0
0
1
1
0
X
Output = 1
0
Factory fm disabled
GPIO_tstiob
Enabled
GPIO
GPIO
GPIO2
gpin2
0
0
1
HiZ
0
1
0
1
Input (dig)->
input
0
1
1
Output = 0
0
1
1
1
Output = 1
0
The LP3971 has provision for two battery connections, the main battery Vbat and Backup Battery (See
Applications Schematic Diagrams Figure 1 and Figure 2).
The function of the battery switch is to connect power to the RTC LDO from the appropriate battery, depending
on conditions described below:
• If only the backup battery is applied, the switch will automatically connect the RTC LDO power to this battery.
• If only the main battery is applied, the switch will automatically connect the RTC LDO power to this battery.
• If both batteries are applied, and the main battery is sufficiently charged (VBAT > 3.1V), the switch will
automatically connect the RTC LDO power to the main battery.
• As the main battery is discharged by use, the user will be warned by a separate circuit called nBATT_FLT.
Then if no action is taken to restore the charge on the main battery, and discharging is continued the battery
switch will protect the RTC LDO by disconnecting from the main battery and connecting to the backup battery.
– The main battery voltage at which the RTC LDO is switched from main to backup battery is 2.9V typically.
– There is a hysterisis voltage in this switch operation so, the RTC LDO will not be reconnected to main
battery until main battery voltage is greater than 3.1V typically.
• Additionally, the user may wish to disable the battery switch, such as, in the case when only a main battery is
used. This is accomplished by setting the “no back up battery bit” in the control register 8h’89 bit 7 NBUB.
With this bit set to “1”, the above described switching will not occur, that is the RTC LDO will remain
connected to the main battery even as it is discharged below the 2.9 Volt threshold.
REGULATED VOLTAGES OK
All the power domains have own register bit (X_OK) that processor can read via serial interface to be sure that
enabled powers are OK (regulating). Note that these read only bits are only valid when regulators are settled
(avoid reading these bits during voltage change or power up).
THERMAL MANAGEMENT
Application: There is a mode wherein all 6 comparators (flags) can be turned on via the “enallflags” control
register bit. This mode allows the user to interrogate the device or system temperature under the set operating
conditions. Thus, the rate of temperature change can also be estimated. The system may then negotiate for
speed and power trade off, or deploy cooling maneuvers to optimize system performance. The “enallflags” bit
needs enabled only when the “bct bits are read to conserve power.
Note: The thermal management flags have been verified functional. Presently these registers are accessible by
factory only. If there is a demand for this function, the relevant register controls may be shifted into the user
programmable bank; the temperature range and resolution of these flags, might also be refined/redefined.
Application Note - LP3971 Reset Sequence
INITIAL COLD START POWER ON SEQUENCE
1. The Back up battery is connected to the PMU, power is applied to the back-up battery pin, the RTC_LDO
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turns on and supplies a stable output voltage to the VCC_BATT pin of the Applications processor (initiating
the power-on reset event) with nRSTO asserted from the LP3971 to the processor.
2. nRSTO de-asserts after a minimum of 50 mS.
3. The Applications processor waits for the de-assertion of nBATT_FLT to indicate system power (VIN) is
available.
4. After system power (VIN) is applied, the LP3971 de-asserts nBATT_FLT. Note that BOTH nRSTO and
nBATT_FLT need to be de-asserted before SYS_EN is enabled. The sequence of the two signals is
independent of each other.
5. The Applications processor asserts SYS_EN, the LP3971 enables the system high-voltage power supplies.
The Applications processor starts its countdown timer set to 125 mS.
6. The LP3971 enables the high-voltage power supplies.
– LDO1 power for VCC_MVT (Power for internal logic and I/O Blocks), BG (Bandgap reference voltage),
OSC13M (13 MHz oscillator voltage) and PLL enabled first, followed by others if delay is on.
7. Countdown timer expires; the Applications processor asserts PWR_EN to enable the low-voltage power
supplies. The processor starts the countdown timer set to 125 mS period.
8. The Applications processor asserts PWR_EN (ext. pin or I2C), the LP3971 enables the low-voltage
regulators.
9. Countdown timer expires; If enabled power domains are OK (I2C read) the power up sequence continues by
enabling the processors 13 MHz oscillator and PLL’s.
10. The Applications processor begins the execution of code.
t3
t1
t4
VIN BU Batt
1.
VCC_RTC
nRSTO
2.
VIN Main Batt
3,4.
nBATT_FLT
SYS_EN
5.
PXA27x Output
6.
High-Volt_PD
PWR_EN
7.
PXA27x Output
8.
Low-Volt_PD
t2
nRESET_OUT
PXA27x Output
13 MHZ_OSC
PXA27x Output
t5
9,10.
Note that BOTH nRSTO and nBATT_FLT need to be de-asserted before SYS_EN is enabled. The sequence of the
two signals is independent of each other and can occur is either order.
POWER-ON TIMING
Symbol
Description
t1
Delay from VCC_RTC assertion to nRSTO de-assertion
Min
t2
Delay from nBATT_FLT de-assertion to nRSTI assertion
Typ
Max
50
mS
100
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Units
µS
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Symbol
Description
t3
Delay from nRST de-assertion to SYS_EN assertion
Min
Typ
10
Max
Units
mS
t4
Delay from SYS_EN assertion to PWR_EN assertion
125
mS
t5
Delay from PWR_EN assertion to nRSTO de-assertion
125
mS
HARDWARE RESET SEQUENCE
Hardware reset initiates when the nRSTI signal is asserted (low). Upon assertion of nRST the processor enters
hardware reset state. The LP3971 holds the nRST low long enough (50 ms typ.) to allow the processor time to
initiate the reset state.
RESET SEQUENCE
1. nRSTI is asserted.
2. nRSTO is asserted and will de-asserts after a minimum of 50 mS
3. The Applications processor waits for the de-assertion of nBATT_FLT to indicate system power (VIN) is
available.
4. After system power (VIN) is turned on, the LP3971 de-asserts nBATT_FLT.
5. The Applications processor asserts SYS_EN, the LP3971 enables the system high-voltage power supplies.
The Applications processor starts its countdown timer.
6. The LP3971 enables the high-voltage power supplies.
7. Countdown timer expires; the Applications processor asserts PWR_EN to enable the low-voltage power
supplies. The processor starts the countdown timer.
8. The Applications processor asserts PWR_EN, the LP3971 enables the low-voltage regulators.
9. Countdown timer expires; If enabled power domains are OK (I2C read) the power up sequence continues by
enabling the processors 13 MHz oscillator and PLL’s.
10. The Applications processor begins the execution of code.
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APPLICATION HINTS
LDO CONSIDERATIONS
External Capacitors
The LP3971’s regulators require external capacitors for regulator stability. These are specifically designed for
portable applications requiring minimum board space and smallest components. These capacitors must be
correctly selected for good performance.
Input Capacitor
An input capacitor is required for stability. It is recommended that a 1.0 µF capacitor be connected between the
LDO input pin and ground (this capacitance value may be increased without limit).
This capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean
analogue ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.
Important: Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a low
impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input,
it must be specified by the manufacturer to have a surge current rating sufficient for the application.
There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance and
temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain
approximately 1.0 µF over the entire operating temperature range.
Output Capacitor
The LDO’s are designed specifically to work with very small ceramic output capacitors. A 1.0 μF ceramic
capacitor (temperature types Z5U, Y5V or X7R) with ESR between 5 mΩ to 500 mΩ, are suitable in the
application circuit.
For this device the output capacitor should be connected between the VOUT pin and ground.
It is also possible to use tantalum or film capacitors at the device output, COUT (or VOUT), but these are not as
attractive for reasons of size and cost (see Capacitor Characteristics).
The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR
value that is within the range 5 mΩ to 500 mΩ for stability.
No-Load Stability
The LDO’s will remain stable and in regulation with no external load. This is an important consideration in some
circuits, for example CMOS RAM keep-alive applications.
Capacitor Characteristics
The LDO’s are designed to work with ceramic capacitors on the output to take advantage of the benefits they
offer. For capacitance values in the range of 0.47 µF to 4.7 µF, ceramic capacitors are the smallest, least
expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The
ESR of a typical 1.0 µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR
requirement for stability for the LDO’s.
For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure
correct device operation. The capacitor value can change greatly, depending on the operating conditions and
capacitor type. In particular, the output capacitor selection should take account of all the capacitor parameters, to
ensure that the specification is met within the application. The capacitance can vary with DC bias conditions as
well as temperature and frequency of operation. Capacitor values will also show some decrease over time due to
aging. The capacitor parameters are also dependant on the particular case size, with smaller sizes giving poorer
performance figures in general. As an example, Figure 23 shows a typical graph comparing different capacitor
case sizes in a Capacitance vs. DC Bias plot. As shown in the graph, increasing the DC Bias condition can result
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CAP VALUE (% OF NOMINAL 1 PF)
in the capacitance value falling below the minimum value given in the recommended capacitor specifications
table. Note that the graph shows the capacitance out of spec for the 0402 case size capacitor at higher bias
voltages. It is therefore recommended that the capacitor manufacturers’ specifications for the nominal value
capacitor are consulted for all conditions, as some capacitor sizes (e.g. 0402) may not be suitable in the actual
application.
0603, 10V, X5M
100%
80%
60%
40%
0402, 6.3V, X5R
20%
0
1.0
2.0
3.0
4.0
5.0
DC BIAS (V)
Figure 23. Graph Showing a Typical Variation in Capacitance vs. DC Bias
The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a
temperature range of −55°C to +125°C, will only vary the capacitance to within ±15%. The capacitor type X5R
has a similar tolerance over a reduced temperature range of −55°C to +85°C. Many large value ceramic
capacitors, larger than 1 µF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance
can drop by more than 50% as the temperature varies from 25°C to 85°C. Therefore X7R is recommended over
Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25°C.
Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more
expensive when comparing equivalent capacitance and voltage ratings in the 0.47 µF to 4.7 µF range.
Another important consideration is that tantalum capacitors have higher ESR values than equivalent size
ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the
stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic
capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about
2:1 as the temperature goes from 25°C down to –40°C, so some guard band must be allowed.
BUCK CONSIDERATIONS
Inductor Selection
There are two main considerations when choosing an inductor; the inductor should not saturate, and the inductor
current ripple is small enough to achieve the desired output voltage ripple. Different saturation current rating
specs are followed by different manufacturers so attention must be given to details. Saturation current ratings are
typically specified at 25°C so ratings at max ambient temperature of application should be requested from
manufacturer.
There are two methods to choose the inductor saturation current rating.
Method 1
The saturation current is greater than the sum of the maximum load current and the worst case average to peak
inductor current. This can be written as
ISAT > IOUTMAX + IRIPPLE
*
§ VOUT
¨
¨ VIN
©
§
¨
¨
©
§
¨
¨
©
42
§ VIN - VOUT
¨
¨ 2* L
©
*
§1
¨
¨f
©
§
¨
¨
©
where IRIPPLE =
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SNVS432V – JANUARY 2006 – REVISED MAY 2013
• IRIPPLE: Average to peak inductor current
• IOUTMAX: Maximum load current (1500 mA)
• VIN: Maximum input voltage in application
• L: Min inductor value including worst case tolerances (30% drop can be considered for method 1)
• f: Minimum switching frequency (1.6 MHz)
• VOUT: Output voltage
Method 2
A more conservative and recommended approach is to choose an inductor that has saturation current rating
greater than the max current limit of TBD mA.
A 2.2 μH inductor with a saturation current rating of at least TBD mA is recommended for most applications. The
inductor’s resistance should be less than 0.3Ω for a good efficiency. Table 2 lists suggested inductors and
suppliers. For low-cost applications, an unshielded bobbin inductor could be considered. For noise critical
applications, a toroidal or shielded bobbin inductor should be used. A good practice is to lay out the board with
overlapping footprints of both types for design flexibility. This allows substitution of a low-noise shielded inductor,
in the event that noise from low-cost bobbin models is unacceptable.
Input Capacitor Selection
A ceramic input capacitor of 10 μF, 6.3V is sufficient for most applications. Place the input capacitor as close as
possible to the VIN pin of the device. A larger value may be used for improved input voltage filtering. Use X7R or
X5R types, do not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting
case sizes like 0805 and 0603. The input filter capacitor supplies current to the PFET switch of the converter in
the first half of each cycle and reduces voltage ripple imposed on the input power source. A ceramic capacitor’s
low ESR provides the best noise filtering of the input voltage spikes due to this rapidly changing current. Select a
capacitor with sufficient ripple current rating. The input current ripple can be calculated as:
where r =
VOUT
VIN
§
* ¨¨1 ©
VOUT
2
+
VIN
r
12
§
¨
¨
©
IRMS = IOUTMAX *
(VIN - VOUT) * VOUT
L * f * IOUTMAX * VIN
(3)
The worst case is when VIN = 2 * VOUT
Table 2. Suggested Inductors and Their Suppliers
Model
Vendor
FDSE0312-2R2M
Toko
Dimensions LxWxH (mm)
3.0 x 3.0 x 1.2
D.C.R (Typ)
160 mΩ
DO1608C-222
Coilcraft
6.6 x 4.5 x 1.8
80 mΩ
Output Capacitor Selection
Use a 10 μF, 6.3V ceramic capacitor. Use X7R or X5R types, do not use Y5V. DC bias characteristics of ceramic
capacitors must be considered when selecting case sizes like 0805 and 0603. DC bias characteristics vary from
manufacturer to manufacturer and dc bias curves should be requested from them as part of the capacitor
selection process. The output filter capacitor smooths out current flow from the inductor to the load, helps
maintain a steady output voltage during transient load changes and reduces output voltage ripple. These
capacitors must be selected with sufficient capacitance and sufficiently low ESR to perform these functions.
The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its
ESR and can be calculated as:
VPP-C =
IRIPPLE
4 * f *C
(4)
Voltage peak-to-peak ripple due to ESR can be expressed as follows
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VPP-ESR = (2 * IRIPPLE) * RESR
(5)
Because these two components are out of phase the rms value can be used to get an approximate value of
peak-to-peak ripple.
Voltage peak-to-peak ripple, root mean squared can be expressed as follows
VPP-RMS =
VPP-C2 + VPP-ESR2
(6)
Note that the output voltage ripple is dependent on the inductor current ripple and the equivalent series
resistance of the output capacitor (RESR).
The RESR is frequency dependent (as well as temperature dependent); make sure the value used for calculations
is at the switching frequency of the part.
Table 3. Suggested Capacitor and Their Suppliers
Model
Type
Vendor
Voltage
Case Size
Inch (mm)
GRM21BR60J106K
Ceramic, X5R
Murata
6.3V
0805 (2012)
JMK212BJ106K
Ceramic, X5R
Taiyo-Yuden
6.3V
0805 (2012)
C2012X5R0J106K
Ceramic, X5R
TDK
6.3V
0805 (2012)
Buck Output Ripple Management
If VIN and ILOAD increase, the output ripple associated with the Buck Regulators also increases. The figure below
shows the safe operating area. To ensure operation in the area of concern it is recommended that the system
designer circumvents the output ripple issues to install schottky diodes on the Bucks(s) that are expected to
perform under these extreme corner conditions.
(Schottky diodes are recommended to reduce the output ripple, if system requirements include this shaded area
of operation. VIN > 5.1V and ILOAD > 1.24)
5.5
VIN (V)
5.0
4.5
4.0
3.5
3.0
0
0.5
1.0
1.5
LOAD CURRENT (A)
Board Layout Considerations
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance
of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss
in the traces. These can send erroneous signals to the DC-DC converter IC, resulting in poor regulation or
instability.
Good layout for the converters can be implemented by following a few simple design rules.
1. Place the converters, inductor and filter capacitors close together and make the traces short. The traces
between these components carry relatively high switching currents and act as antennas. Following this rule
reduces radiated noise. Special care must be given to place the input filter capacitor very close to the VIN
and GND pin.
2. Arrange the components so that the switching current loops curl in the same direction. During the first half of
each cycle, current flows from the input filter capacitor through the converter and inductor to the output filter
capacitor and back through ground, forming a current loop. In the second half of each cycle, current is pulled
up from ground through the converter by the inductor to the output filter capacitor and then back through
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3.
4.
5.
6.
SNVS432V – JANUARY 2006 – REVISED MAY 2013
ground forming a second current loop. Routing these loops so the current curls in the same direction
prevents magnetic field reversal between the two half-cycles and reduces radiated noise.
Connect the ground pins of the converter and filter capacitors together using generous component-side
copper fill as a pseudo-ground plane. Then, connect this to the ground-plane (if one is used) with several
vias. This reduces ground-plane noise by preventing the switching currents from circulating through the
ground plane. It also reduces ground bounce at the converter by giving it a low-impedance ground
connection.
Use wide traces between the power components and for power connections to the DC-DC converter circuit.
This reduces voltage errors caused by resistive losses across the traces.
Route noise sensitive traces, such as the voltage feedback path, away from noisy traces between the power
components. The voltage feedback trace must remain close to the converter circuit and should be direct but
should be routed opposite to noisy components. This reduces EMI radiated onto the DC-DC converter’s own
voltage feedback trace. A good approach is to route the feedback trace on another layer and to have a
ground plane between the top layer and layer on which the feedback trace is routed. In the same manner for
the adjustable part it is desired to have the feedback dividers on the bottom layer.
Place noise sensitive circuitry, such as radio RF blocks, away from the DC-DC converter, CMOS digital
blocks and other noisy circuitry. Interference with noise-sensitive circuitry in the system can be reduced
through distance.
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REVISION HISTORY
Changes from Revision U (May 2013) to Revision V
•
46
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 45
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LP3971SQ-2G16/NOPB
NRND
WQFN
RSB
40
1000
RoHS & Green
SN
Level-1-260C-UNLIM
LP3971SQ-B410/NOPB
NRND
WQFN
RSB
40
1000
RoHS & Green
SN
Level-1-260C-UNLIM
71-2G16
LP3971SQ-D510/NOPB
NRND
WQFN
RSB
40
1000
RoHS & Green
SN
Level-1-260C-UNLIM
71-D510
LP3971SQ-N510/NOPB
NRND
WQFN
RSB
40
1000
RoHS & Green
SN
Level-1-260C-UNLIM
71-N510
-40 to 125
71-B410
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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