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LP3972
SNVS468L – SEPTEMBER 2006 – REVISED NOVEMBER 2015
LP3972 Power Management Unit for Advanced Application Processors
1 Features
2 Applications
•
•
•
•
•
1
•
•
•
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Compatible With Advanced Applications
Processors Requiring Dynamic Voltage
Management (DVM)
Backup Battery Charger With Automatic Switch for
Lithium-Manganese Coin-Cell Batteries and Super
Capacitors
I2C-Compatible High-Speed Serial Interface
Software Control of Regulator Functions and
Settings
Thermal and Current Overload Protections
Three Buck Regulators for Powering High-Current
Processor Functions or I/Os
– Programmable VOUT from 0.725 V to 3.3 V
– Up to 95% Efficiency and 1.6-A Output Current
– ±3% Output Voltage Accuracy
Six LDOs for Powering RTC, Peripherals, and
I/Os
– Programmable VOUT of 1 V to 3.3 V
– ±3% Output Voltage Accuracy
– LDO_RTC 30 mA
– LDO1 300 mA
– LDO2 150 mA
– LDO3 150 mA
– LDO4 150 mA
– LDO5 400 mA
Smart Phones
Personal Media Players
Digital Cameras
Application Processors
– Marvell PXA
– Freescale
– Samsung
3 Description
The LP3972 is a multi-function programmable power
management unit (PMU) designed especially for
advanced application processors. The LP3972 is
optimized for low-power handheld applications and
provides six low-dropout low-noise linear regulators,
three DC-DC magnetic buck regulators, a backup
battery charger, and two GPIOs. A high-speed serial
interface is included to program individual regulator
output voltages as well as on and off control.
Device Information(1)
PART NUMBER
LP3972
PACKAGE
WQFN (40)
BODY SIZE (NOM)
5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
Back-up
Battery
VIN
+
-
LDO1
BUCK1
LDO2
LDO3
BUCK2
LP3972
LDO4
LDO5
BUCK3
SYNC
SCL
SDA
GPIO2
GPIO1/nCHG_EN
SPARE
EXT_WAKEUP
PWR_EN
PWR_ON
nTEST_JIG
nRSTI
SYS_EN
nRSTO
nBATT_FLT
RTC
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP3972
SNVS468L – SEPTEMBER 2006 – REVISED NOVEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Tables...................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
1
1
1
2
3
5
7
Absolute Maximum Ratings ...................................... 7
ESD Ratings ............................................................ 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 8
Electrical Characteristics........................................... 8
Electrical Characteristics: LDO RTC......................... 8
Electrical Characteristics: LDOs 1 to 5 ..................... 9
Electrical Characteristics: Buck Converters SW1,
SW2, SW3 ............................................................... 10
7.9 Electrical Characteristics: Backup Charger............. 10
7.10 Electrical Characteristics: I2C Compatible Serial
Interface (SDA and SCL) ......................................... 11
7.11 Logic Inputs and Outputs DC Operating
Conditions ................................................................ 11
7.12 I2C Compatible Serial Interface Timing
Requirements (SDA and SCL)................................. 12
7.13 Power-On Timing Delays ...................................... 12
7.14 Typical Characteristics ......................................... 13
8
Detailed Description ............................................ 15
8.1
8.2
8.3
8.4
8.5
8.6
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
15
16
17
21
21
30
Application and Implementation ........................ 48
9.1 Application Information............................................ 48
9.2 Typical Application ................................................. 48
10 Power Supply Recommendations ..................... 54
11 Layout................................................................... 55
11.1 Layout Guidelines ................................................. 55
11.2 Layout Example .................................................... 56
12 Device and Documentation Support ................. 57
12.1
12.2
12.3
12.4
12.5
12.6
Device Support......................................................
Related Documentation .......................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
57
57
57
57
57
57
13 Mechanical, Packaging, and Orderable
Information ........................................................... 57
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision K (May 2013) to Revision L
•
Added Device Information and Pin Configuration and Functions sections, ESD Ratings and Thermal Information
tables, Feature Description, Device Functional Modes, Application and Implementation, Power Supply
Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and Orderable
Information sections................................................................................................................................................................ 1
Changes from Revision J (May 2013) to Revision K
•
2
Page
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 55
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SNVS468L – SEPTEMBER 2006 – REVISED NOVEMBER 2015
5 Device Comparison Tables
Table 1. Supply Specifications
VOUT (V) (1) (2)
SUPPLY
(1)
(2)
IMAX: MAXIMUM CURRENT
RANGE
RESOLUTION
(V)
(mV)
CURRENT (mA)
LDO_RTC
2.8
N/A
30-mA DC source 10-mA backup source
LDO1 (VCC_MVT)
1.7 to 2
25
300
LDO2
1.8 to 3.3
100
150
LDO3
1.8 to 3.3
100
150
150
LDO4
1.0 to 3.3
50 - 600
LDO5 (VCC_SRAM)
0.850 to 1.5
25
400
BUCK1 (VCC_APPS)
0.725 to 1.5
25
1600
BUCK2
0.8 to 3.3
50 - 600
1600
BUCK3
0.8 to 3.3
50 - 600
1600
All voltages are with respect to the potential at the GND pin.
The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. (MIL-STD-883 3015.7) The machine
model is a 200-pF capacitor discharged directly into each pin. (EAIJ).
Table 2. Default Voltage Options (1) (2) (3)
VERSION
LP3972SQ-A514
LP3972SQ-A413
Version A
Version A
Enable
LDO_RTC
—
2.8 V
—
LDO1
SYS_EN
1.8 V
SYS_EN
1.8 V
LDO2
SYS_EN
1.8 V (D)
SYS_EN
1.8 V (D)
LDO3
SYS_EN
3 V (D)
SYS_EN
3 V (D)
LDO4
SYS_EN
3 V (D)
SYS_EN
2.8 V (D)
LDO5
PWR_EN
1.4 V
PWR_EN
1.4 V
BUCK1
PWR_EN
1.4 V
PWR_EN
1.4 V
BUCK2
SYS_EN
3.3 V
SYS_EN
3V
BUCK3
SYS_EN
1.8 V
SYS_EN
1.8 V
VERSION
P3972SQ-E514
Enable
LDO_RTC
2.8 V
LP3972SQ-I514
Version E
Version I
—
2.8 V
—
LDO1
SYS_EN
1.8 V
SYS_EN
1.8 V
LDO2
SYS_EN
1.8 V (E)
SYS_EN
1.8 V (E)
LDO3
SYS_EN
3 V (D)
SYS_EN
3 V (E)
LDO4
SYS_EN
3 V (D)
SYS_EN
3 V (E)
LDO5
PWR_EN
1.4 V
PWR_EN
1.4 V
BUCK1
PWR_EN
1.4 V
PWR_EN
1.4 V
BUCK2
SYS_EN
3.3 V
SYS_EN
3.3 V
BUCK3
SYS_EN
1.8 V
SYS_EN
1.8 V
(1)
(2)
(3)
2.8 V
All voltages are with respect to the potential at the GND pin
The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. (MIL-STD-883 3015.7) The machine
model is a 200-pF capacitor discharged directly into each pin. (EAIJ).
E = Regulator is ENABLED during start-up. D = Regulator is DISABLED during start-up.
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Table 2. Default Voltage Options(1)(2)(3) (continued)
VERSION
Enable
LDO_RTC
LP3972SQ-I414
LP3972SQ-0514
Version I
Version 0
—
2.8 V
Tracking enabled
LDO1
SYS_EN
1.8 V
SYS_EN
1.8 V
LDO2
SYS_EN
1.8 V (E)
SYS_EN
1.8 V (E)
LDO3
SYS_EN
3 V (E)
SYS_EN
3.3 V (E)
LDO4
SYS_EN
3 V (E)
SYS_EN
3 V (E)
LDO5
PWR_EN
1.4 V
PWR_EN
1.4 V
BUCK1
PWR_EN
1.4 V
PWR_EN
1.4 V
BUCK2
SYS_EN
3V
SYS_EN
3.3 V
BUCK3
SYS_EN
1.8 V
SY_EN
1.8 V
VERSION
LP3972SQ-5810
Enable
Version 5
LDO_RTC
—
2.8 V
LDO1
SYS_EN
1.8 V
LDO2
SYS_EN
1.8 V (E)
LDO3
SYS_EN
2.5 V (E)
LDO4
PWR_EN
1.3 V (E)
LDO5
PWR_EN
1.1 V
BUCK1
PWR_EN
1.35 V
BUCK2
SYS_EN
1.2 V
BUCK3
SYS_EN
1.8 V
4
3.3 V w/ tracking
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SNVS468L – SEPTEMBER 2006 – REVISED NOVEMBER 2015
6 Pin Configuration and Functions
RSB Package
40-Pin WQFN
Top View
RSB Package
40-Pin WQFN
Bottom View
21 22 23 24 25 26 27 28 29 30
30 29 28 27 26 25 24 23 22 21
31
20
20
31
32
19
19
32
33
33
18
18
34
17
17
34
35
16
16
35
36
15
15
36
37
14
14
37
38
13
13
38
39
12
12
39
40
11
11
40
1
2
3
4
5
6
7
8
10 9
9 10
8
7
6
5
4
3
2
1
Pin Functions
PIN
I/O
TYPE (1)
DESCRIPTION
PWR_ON
I
D
This is an active HI push button input which can be used to signal PWR_ON
and PWR_OFF events to the CPU by controlling the EXT_WAKEUP [pin4] and
select contents of register 8H'88.
2
nTEST_JIG
I
D
This is an active LOW input signal used for detecting an external HW event.
The response is seen in the EXT_WAKEUP [pin4] and select contents of
register 8H'88.
3
SPARE
I
D
This is an input signal used for detecting a external HW event. The response is
seen in the EXT_WAKEUP [pin4] and select contents of register 8H'88. The
polarity on this pin is assignable.
4
EXT_WAKEUP
O
D
This pin generates a single 10-ms pulse output to CPU in response to input
from pins 1, 2, and 3. Flags CPU to interrogate register 8H'88.
5
FB1
I
A
Buck1 input feedback pin.
6
VIN
I
PWR
Battery input (internal circuitry and LDO1-3 power input)
7
VOUT LDO1
O
PWR
LDO1 output
8
VOUT LDO2
O
PWR
LDO2 output
9
nRSTI
I
D
Active low reset pin. Signal used to reset the device (by default is pulled high
internally). Typically a push button reset.
10
GND1
G
G
Ground
11
VREF
O
A
Bypass capacitor for the high internal impedance reference.
12
VOUT LDO3
O
PWR
LDO3 output
13
VOUT LDO4
O
PWR
LDO4 output
14
VIN LDO4
I
PWR
Power input to LDO4 — this can be connected to either from a 1.8-V supply to
main battery supply.
15
VIN BUBATT
I
PWR
Backup battery input supply.
16
VOUT
LDO_RTC
O
PWR
NUMBER
NAME (2)
1
LDO_RTC output supply to the RTC of the application processor.
17
nBATT_FLT
O
D
Main battery fault output, indicates the main battery is low (discharged) or the
DC source has been removed from the system. This gives the processor an
indicator that the power will shut down. During this time the processor will
operate from the backup coin cell.
18
PGND2
G
G
Buck2 NMOS power ground
19
SW2
O
PWR
(1)
(2)
Buck2 switcher output
A: Analog Pin D: Digital Pin G: Ground Pin P: Power Pin I: Input Pin I/O: Input/Output Pin O: Output Pin
In this document, active-low logic items are prefixed with a lowercase "n".
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Pin Functions (continued)
PIN
NUMBER
NAME (2)
I/O
TYPE (1)
DESCRIPTION
20
VIN BUCK2
I
PWR
21
SDA
I/O
D
Battery input power to Buck2
I2C Data (Bidirectional)
22
SCL
I
D
I2C Clock
23
FB2
I
A
Buck2 input feedback pin
24
nRSTO
O
D
Reset output from the PMIC to the processor
25
VOUT LDO5
O
PWR
LDO5 output
26
VIN LDO5
I
PWR
Power input to LDO5, this can be connected to VIN or to a separate 1.8-V
supply.
27
VDDA
I
PWR
Analog Power for VREF, BIAS
28
FB3
I
A
Buck3 Feedback
29
GPIO1 /
nCHG_EN
I/O
D
General purpose I/O / Ext. backup battery charger enable pin. This pin enables
the main battery or DC source power to charge the backup battery. This pin
toggled via the application processor. By grounding this pin the DC source
continuously charges the backup battery.
30
GPIO2
I/O
D
General purpose I/O
31
VIN BUCK3
I
PWR
Battery input power to Buck3
32
SW3
O
PWR
Buck3 switcher output
33
PGND3
G
G
Buck3 NMOS Power ground
34
BGND1,2,3
G
G
Bucks 1, 2 and 3 analog ground
35
SYNC
I
D
Frequency synchronization: Connection to an external clock signal PLL to
synchronize the PMIC internal oscillator.
36
SYS_EN
I
D
Input digital enable pin for the high voltage power domain supplies. Output
from the Monahans processor.
37
PWR_EN
I
D
Digital enable pin for the low-voltage domain supplies. Output signal from the
Monahans processor
38
PGND1
G
G
Buck1 NMOS power ground
39
SW1
O
PWR
Buck1 switcher output
40
VIN BUCK1
I
PWR
Battery input power to Buck1
6
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SNVS468L – SEPTEMBER 2006 – REVISED NOVEMBER 2015
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
All inputs
−0.3
6.5
V
GND-to-GND SLUG
−0.3
0.3
V
Junction temperature, TJ-MAX
150
°C
Power dissipation (TA = 70°C) (3)
3.2
W
260
°C
150
°C
Maximum lead temperature (soldering)
Storage temperature, Tstg
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, contact the TI Sales Office/Distributors for availability and specifications.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =
125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the
part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).
7.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Machine model
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
NOM
MAX
UNIT
2.7
5.5
VINLDO4, 5
1.74
VIN
V
Junction temperature, TJ
−40
125
°C
Operating temperature, TA
−40
85
°C
2.2
W
Maximum power dissipation (TA = 70°C) (1) (2) (3)
(1)
(2)
(3)
V
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =
125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the
part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).
Junction-to-ambient thermal resistance (RθJA) is taken from a thermal modeling result, performed under the conditions and guidelines
set forth in the JEDEC standard JESD51–7. The test board is a 4-layer FR-4 board measuring 102 mm × 76 mm × 1.6 mm with a 2 × 1
array of thermal vias. The ground plane on the board is 50 mm × 50 mm. Thickness of copper layers are 36 µm/1.8 µm/18 µm/36 µm
(1.5 oz/1 oz/1 oz/1.5 oz). Ambient temperature in simulation is 22°C, still air. Power dissipation is 1W. Junction-to-ambient thermal
resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care
must be paid to thermal dissipation issues in board design. The value of RθJA of this product can vary significantly, depending on PCB
material, layout, and environmental conditions. In applications where high maximum power dissipation exists (high VIN, high IOUT),
special care must be paid to thermal dissipation issues. For more information on these topics, see Texas Instruments Application Note
Leadless Leadframe Package (LLP)(SNOA401).
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =
125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the
part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).
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7.4 Thermal Information
LP3972
THERMAL METRIC (1)
RSB (WQFN)
UNIT
40 PINS
RθJA
(1)
Junction-to-ambient thermal resistance
25
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
7.5 Electrical Characteristics
Typical values and limits apply for TJ = 25°C; minimum and maximum limits apply over the entire junction temperature range
for operation, −40°C to +125°C, unless otherwise specified. All voltages are with respect to the potential at the GND pin. (1) (2)
PARAMETER
TEST CONDITIONS
VIN, VDDA, VIN
bucks 1, 2 and 3
Battery voltage
VINLDO4, VINLDO5
Power supply for LDOs 4 and 5
(1)
(2)
(3)
TYP
MAX
2.7
3.6
5.5
V
3.6
VIN
V
1.74
Temperature
Thermal shutdown (3)
TSD
MIN
160
Hysteresis
UNIT
°C
20
All limits specified at room temperature and at temperature extremes. All room temperature limits are production tested, ensured through
statistical analysis or ensured by design. All limits at temperature extremes are ensured via correlation using standard Statistical Quality
Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
Input supply must not be higher then VDDA.
This electrical specification is ensured by design.
7.6 Electrical Characteristics: LDO RTC
VIN = 3.6 V, CIN = 1 µF, COUT = 0.47 µF, COUT (VRTC) = 1 µF ceramic (unless otherwise noted).
Typical values and limits apply for TJ = 25°C; minimum and maximum limits apply over the entire junction temperature range
for operation, −40°C to +125°C, unless otherwise specified. All voltages are with respect to the potential at the GND
pin. (1) (2) (3)
PARAMETER
VOUT accuracy
MIN
TYP
MAX
UNIT
2.632
2.8
2.968
V
VIN = (VOUT(NOM) + 1 V) to 5.5 V (4)
Load current = 1 mA
0.15
%/V
From main battery
Load current = 1 mA to 30 mA
0.05
From backup battery, VIN = 3 V
Load current = 1 mA to 10 mA
0.5
VIN connected, load current = 1 mA
Line regulation
ΔVOUT
Load regulation
ISC
TEST CONDITIONS
Output voltage accuracy
Short-circuit current limit
%/mA
From main battery
VIN = VOUT + 0.3 V to 5.5 V
100
From backup battery
VIN – VOUT
Dropout voltage
Load current = 10 mA
IQ_MAX
Maximum quiescent current
IOUT = 0 mA
30
TP1
RTC LDO input switched from
main battery to backup battery
VIN falling
2.9
TP2
RTC LDO input switched from
backup battery to main battery
VIN rising
3
COUT
Output capacitor
(1)
(2)
(3)
(4)
8
Capacitance for stability
ESR
mA
30
375
0.7
5
mV
µA
V
V
1
µF
500
mΩ
All limits specified at room temperature and at temperature extremes. All room temperature limits are production tested, ensured through
statistical analysis or ensured by design. All limits at temperature extremes are ensured via correlation using standard Statistical Quality
Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value.
LDO_RTC voltage can track LDO3 voltage. LP3972 has a tracking function (nIO_TRACK). When enabled, LDO_RTC voltage tracks
LDO3 voltage within 200 mV down to 2.8 V when LDO3 is enabled.
VIN minimum for line regulation values is 2.7 V for LDOs 1–3 and 1.8 V for LDOs 4 and 5. Condition does not apply to input voltages
below the minimum input operating voltage.
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7.7 Electrical Characteristics: LDOs 1 to 5
VIN = 3.6 V, CIN = 1 µF, COUT = 0.47 µF, COUT (VRTC) = 1.0 µF ceramic (unless otherwise noted). Typical values and limits
apply for TJ = 25°C; minimum and maximum limits apply over the entire junction temperature range for operation, −40°C to
+125°C, unless otherwise specified. All voltages are with respect to the potential at the GND pin. (1) (2) (3) (4) (5) (6)
PARAMETER
Output voltage accuracy
VOUT accuracy
(default VOUT)
TEST CONDITIONS
Load current = 1 mA
Line regulation
VIN = 3.1 V to 5 V (7),
Load Current = 1 mA
Load regulation
VIN = 3.6 V,
Load current = 1 mA to IMAX
ΔVOUT
MIN
TYP
–3%
0.15
0.011
LDO1–4, VOUT = 0 V
400
LDO5, VOUT = 0 V
500
Short-circuit current limit
VIN – VOUT
Dropout voltage
Load current = 50 mA (8)
PSRR
Power Supply Ripple
Rejection
ƒ = 10 kHz, load current = IMAX
Quiescent current On
IOUT = 0 mA
40
Quiescent current On
IOUT = IMAX
60
Quiescent current Off
EN is de-asserted
Turnon time
Start-up from shutdown
TON
COUT
Output capacitor
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
%/V
%/mA
mA
150
45
mV
dB
µA
0.03
300
Capacitance for stability
0°C ≤ TJ ≤ 125°C
0.33
0.47
−40°C ≤ TJ ≤ 125°C
0.68
1.0
ESR
UNIT
3%
ISC
IQ
MAX
µs
µF
5
500
mΩ
All limits specified at room temperature and are production tested, ensured through statistical analysis or ensured by design. All limits at
temperature extremes are ensured via correlation using standard Statistical Quality Control (SQC) methods. All limits are used to
calculate Average Outgoing Quality Level (AOQL).
Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value.
LDO_RTC voltage can track LDO3 voltage. LP3972 has a tracking function (nIO_TRACK). When enabled, LDO_RTC voltage tracks
LDO3 voltage within 200 mV down to 2.8 V when LDO3 is enabled.
VIN minimum for line regulation values is 2.7 V for LDOs 1–3 and 1.8 V for LDOs 4 and 5. Condition does not apply to input voltages
below the minimum input operating voltage.
An increase in the load current results in a slight decrease in the output voltage and vice versa.
Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This
specification does not apply for input voltages below 2.7 V for LDOs 1 to 3 and 1.8 V for LDOs 4 and 5.
VIN minimum for line regulation values is 2.7 V for LDOs 1–3 and 1.8 V for LDOs 4 and 5. Condition does not apply to input voltages
below the minimum input operating voltage.
Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value.
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7.8 Electrical Characteristics: Buck Converters SW1, SW2, SW3
VIN = 3.6 V, CIN = 10 µF, COUT = 10 µF, LOUT = 2.2-µH ceramic (unless otherwise noted). Values and limits apply for TJ =
25°C. All voltages are with respect to the potential at the GND pin. (1) (2) (3)
PARAMETER
TEST CONDITIONS
VOUT
Output voltage accuracy
Default VOUT
Eff
Efficiency
Load current = 500 mA
ISHDN
Shutdown supply current
EN is de-asserted
Sync mode clock frequency
Synchronized from 13-MHz system clock
ƒOSC
Internal oscillator frequency
IPEAK
Peak switching current limit
MIN
TYP
−3%
MAX
UNIT
3%
95%
0.1
10.4
13
µA
15.6
2
2.1
No-load PFM mode
21
No-load PWM mode
20
MHz
MHz
2.4
A
IQ
Quiescent current On
RDSON (P)
Pin-pin resistance PFET
240
mΩ
RDSON (N)
Pin-pin resistance NFET
200
mΩ
TON
Turnon time
Start-up from shutdown
500
µs
CIN
Input capacitor
Capacitance for stability
8
µF
COUT
Output capacitor
Capacitance for stability
8
µF
(1)
(2)
(3)
µA
All limits specified at room temperature and at temperature extremes. All room temperature limits are production tested, ensured through
statistical analysis or ensured by design. All limits at temperature extremes are ensured via correlation using standard Statistical Quality
Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
The input voltage range recommended for ideal applications performance for the specified output voltages is VIN = 2.7 V to 5.5 V for 0.8
V < VOUT < 1.7 VVIN = (VOUT + 1 V) to 5.5 V for 1.8 V ≤ VOUT ≤ 3.3 V.
Test condition for VOUT < 2.7 V, VIN = 3.6 V; for VOUT ≥ to 2.7 V, VIN = VOUT + 1 V.
7.9 Electrical Characteristics: Backup Charger
VIN = VBATT = 3.6 V (unless otherwise noted). Typical values and limits apply for TJ = 25°C; minimum and maximum limits
apply over the entire junction temperature range for operation, −40°C to +125°C. All voltages are with respect to the potential
at the GND pin. (1) (2)
PARAMETER
TEST CONDITIONS
VIN
Operational voltage range
Voltage at VIN
IOUT
Backup battery charging
current
VIN = 3.6 V, Backup_Bat = 2.5 V
backup battery charger enabled
VOUT
Charger termination voltage
VIN = 5 V, backup battery charger enabled;
programmable
Backup battery charger short
circuit current
Backup_Bat = 0 V, backup battery charger
enabled
PSRR
Power supply ripple rejection
ratio
IQ
Quiescent current
COUT
(1)
(2)
10
Output capacitance
Output capacitor ESR
MIN
TYP
3.3
2.91
MAX
5.5
UNIT
V
190
µA
3.1
V
9
mA
IOUT ≤ 50 µA, VOUT = 3.15 V
VOUT + 0.4 ≤ VBATT = VIN ≤ 5 V
ƒ < 10 kHz
15
dB
IOUT < 50 µA
25
µA
0 µA ≤ IOUT ≤ 100 µA
0.1
5
µF
500
mΩ
All limits specified at room temperature and at temperature extremes. All room temperature limits are production tested, ensured through
statistical analysis or ensured by design. All limits at temperature extremes are ensured via correlation using standard Statistical Quality
Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
Backup battery charge current is programmable via the I2C-compatible interface.
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7.10 Electrical Characteristics: I2C Compatible Serial Interface (SDA and SCL)
VIN = 3.6 V (unless otherwise noted). Typical values and limits appearing in normal type apply for TJ = 25°C; minimum and
maximum limits apply over the entire junction temperature range for operation, −40°C to +125°C. All voltages are with respect
to the potential at the GND pin. (1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VIL
Low level input voltage
See (3)
−0.5
0.3 VRTC
VIH
High level input voltage
See (3)
0.7 VRTC
VRTC
VOL
Low level output voltage
See (3)
0
0.2 VTRC
IOL
Low level output current
VOL = 0.4 V (3)
3
FCLK
Clock frequency
See (3)
(1)
(2)
(3)
UNIT
V
mA
400
kHz
All limits specified at room temperature and are production tested, ensured through statistical analysis or ensured by design.
The I2C signals behave like open-drain outputs and require an external pullup resistor on the system module in the 2-kΩ to 20-kΩ range.
This electrical specification is ensured by design.
7.11 Logic Inputs and Outputs DC Operating Conditions
VIN = VBATT = 3.6 V (unless otherwise noted). Typical values and limits apply for TJ = 25°C; minimum and maximum limits
apply over the entire junction temperature range for operation, −40°C to +125°C. All voltages are with respect to the potential
at the GND pin.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC INPUTS (SYS_EN, PWR_EN, SYNC, nRSTI, PWR_ON, nTEST_JIG, SPARE and GPIs)
VIL
Low-level input voltage
VIH
High-level input voltage
ILEAK
Input leakage current
0.5
V
1
µA
0.5
V
5
µA
3.4
V
0.5
V
5
µA
VRTC − 0.5 V
V
−1
LOGIC OUTPUTS (nRSTO, EXT_WAKEUP and GPOs)
VOL
Output low level
Load = 0.2 mA = IOL maximum
VOH
Output high level
Load = −0.1 mA = IOL maximum
ILEAK
Output leakage current
VON = VIN
VRTC − 0.5 V
V
LOGIC OUTPUT (nBATT_FLT)
nBATT_FLT threshold
voltage
Programmable via serial interface
Default = 2.8 V
VOL
Output low level
Load = 0.4 mA = IOL maximum
VOH
Output high level
Load = −0.2 mA = IOH maximum
ILEAK
Input leakage current
2.4
2.8
VRTC − 0.5 V
V
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7.12 I2C Compatible Serial Interface Timing Requirements (SDA and SCL)
All voltages are with respect to the potential at the GND pin. See (1) (2) (3)
MIN
NOM
MAX
UNIT
tBF
Bus-free time between start and stop
1.3
µs
tHOLD
Hold Time repeated start condition
0.6
µs
tCLKLP
CLK low period
1.3
µs
tCLKHP
CLK high period
0.6
µs
tSU
Setup time repeated start condition
0.6
µs
tDATAHLD
Data hold time
0
µs
tCLKSU
Data set up time
100
ns
TSU
Setup time for start condition
0.6
µs
TTRANS
Maximum pulse width of spikes that must be suppressed by the input filter
of both DATA and CLK signals
(1)
(2)
(3)
50
ns
All limits specified at room temperature and are production tested, ensured through statistical analysis or ensured by design.
The I2C signals behave like open-drain outputs and require an external pullup resistor on the system module in the 2-kΩ to 20-kΩ range.
This electrical specification is ensured by design.
7.13 Power-On Timing Delays
See Initial Cold Start Power-On Sequence.
DESCRIPTION
MIN
t1
Delay from VCC_RTC assertion to nRSTO de-assertion
t2
Delay from nBATT_FLT de-assertion to nRSTI assertion
t3
TYP
50
MAX
UNIT
ms
100
µs
Delay from nRST de-assertion to SYS_EN assertion
10
ms
t4
Delay from SYS_EN assertion to PWR_EN assertion
125
ms
t5
Delay from PWR_EN assertion to nRSTO de-assertion
125
ms
12
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7.14 Typical Characteristics
7.14.1 LDO Dropout Voltage vs Load Current Collect Data for all LDOs
200
CHANGE IN OUTPUT VOLTAGE (mV)
DROPOUT VOLTAGE (mV)
300
250
200
150
100
REG1 3.3V OUTPUT
50
0
150
100
REG1 3.3V OUTPUT
REG3 1.3V OUTPUT
0
-50
VIN = 3.6V
-100
0
200
400
600
800
REG2 2.5V OUTPUT
50
1000 1200
0
200
400
600
800
1000 1200
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 1. Dropout Voltage vs Load Current
Figure 2. Change In Output Voltage vs Load Current
4.03 Ps
VIN = 3 V to 4 V
4.0 Ps
VOUT = 1.8 V
Load = 100 mA
VIN = 4.1 V
Figure 3. LDO1 Line Regulation
VOUT = 1.8 V
No-Load = 100 mA
Figure 4. LDO1 Load Transient
4.03 Ps
SYS_ENABLE from 0
Load (V) = 100 mA
LDO1 Channel 2
LDO4 Channel 1
Figure 5. Enable Start-Up Time (LDO1)
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7.14.2 Buck1 Output Efficiency vs. Load Current Varied From 1 mA to 1.5 A
100.00
90.00
VIN = 3V
VIN = 4V
72.00
EFFICIENCY (%)
EFFICIENCY (%)
80.00
VIN = 3.5V
60.00
40.00
20.00
54.00
VIN = 4.5V
36.00
18.00
0.00
0.00
1
1e1
1e2
1e3
1
1e4
1e1
OUTPUT CURRENT (mA)
VIN = 3 V, 3.5 V
1e2
1e3
1e4
OUTPUT CURRENT (mA)
VOUT = 1.4 V
VIN = 4 V to 4.5 V
Figure 6. Buck1 Efficiency
VOUT = 1.4 V
Figure 7. Buck1 Efficiency
90.00
VIN = 5.5V
EFFICIENCY (%)
72.00
VIN = 5V
54.00
36.00
18.00
0.00
1
1e1
1e2
1e3
4.0 Ps
1e4
VIN = 4.1 V
OUTPUT CURRENT (mA)
VIN = 3 V, 3.5 V
VOUT = 1.4 V (PFM to PWM)
VOUT = 1.4 V
Figure 9. Mode Change Load Transients 20 mA To 560 mA
Figure 8. Buck1 Efficiency
4.03 Ps
VIN = 4.1 V
VOUT = 1.4 V
980 mA [Channel 2]
Figure 10. Start-up into PWM Mode
14
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8 Detailed Description
8.1 Overview
The LP3972 includes three high-efficiency step-down DC-DC switching buck converters. Using a voltage mode
architecture with synchronous rectification, the buck converters have the ability to deliver up to 1600 mA
depending on the input voltage, output voltage, ambient temperature, and the inductor chosen.
There are three modes of operation depending on the current required: PWM, PFM, and shutdown. The device
operates in PWM mode at load currents of approximately 100 mA or higher, having voltage tolerance of ±3%
with 95% efficiency or better. Lighter load currents cause the device to automatically switch into PFM for reduced
current consumption. Shutdown mode turns off the device, offering the lowest current consumption (IQ, SHUTDOWN
= 0.01 µA typical).
Additional features include soft-start, undervoltage protection, current-overload protection, and thermal-shutdown
protection.
The part uses an internal reference voltage of 0.5 V. TI recommends that the device be kept in shutdown until
the input voltage is 2.7 V or higher.
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8.2 Functional Block Diagram
Li-ion/polymer cell
14
31
20
Vin_BUCK1
26
Vin_BUCK2
VDDA
27
6
Vin_BUCK3
VIN
DC SOURCE
4.5 ± 5.5V
VinLDO4
Cvdd
4.7 PF
VinLDO5
See notes
+
LP3972 PMIC
SYNC
40
Cchg_det
4.7 PF
APPLICATION
PROCESSOR
35
Clock
divider
37 PWR_EN
Lsw1 2.2 PH
COMP
39
EOC
CPU
CORE
SW1
BUCK1
10 PF
VFB1
5
VinBUBATT 15
Lsw2 2.2 PH
19
Vout
Switch
+ -
VoutLDO_RTC
23
VIN
Wake up
LDO1
Power
ON-OFF
Logic
LDO3
7
12
Logic Control
and registers
LDO4
13
VinLDO5
25
LDORTC
LDO2
Cldo1
1.0 PF
PLL
Cldo4
0.47 PF
VoutLDO5
LDO5
VIN SYS_EN
VoutLDO2 8
Cldo3
0.47 PF
VoutLDO4
VinLDO4
PWR_EN
CODEC
AP_IO
VoutLDO3
RESET
Internal HW reset for
test purposes
MVT
Cldo2
0.47 PF
2
GPIO2 30
9
BG
36
VoutLDO1
GPIO1/nCHG_EN 29
nRSTI
UART
10 PF
28
SYS_EN
OSC
3
Lsw3 2.2 PH
SW3
VFB3
BUCK3
SPARE
USB
10 PF
32
PWR_ON 1
nTEST_JIG
VBUCK2
SW2
VFB2
BUCK2
Vout Switch
Power On
Reset
SRAM
Cldo5
0.47 PF
16 VoutLDO_RTC
CldoRTC
1.0 PF
See notes
3.3V
VDDA
RTC
10k
I2C
Thermal
Shutdown
22
I2C_SCL
10k
21 I2C_SDA
BIAS
24 nRSTO
vref
4
EXT_WAKEUP
17 nBATT_FLT
VREF
Cvrefh
10 nF
16
11
38
18
33
PGND1 PGND2 PGND3
34
BGND1,2,3
10
GND1
•
The I2C lines are pulled up via a I/O source.
•
VINLDOs 4, 5 can either be powered from main battery source or by a buck regulator or VIN.
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8.3 Feature Description
8.3.1 Buck Converter Operation
8.3.1.1 Circuit Operation
The buck converter operates as follows: during the first portion of each switching cycle, the control block turns on
the internal PFET switch. This allows current to flow from the input through the inductor to the output filter
capacitor and load. The inductor limits the current to a ramp with a slope of (VIN – VOUT)/L, by storing energy in a
magnetic field.
During the second portion of each cycle, the controller turns the PFET switch off, blocking current flow from the
input, and then turns the NFET synchronous rectifier on. The inductor draws current from ground through the
NFET to the output filter capacitor and load, which ramps the inductor current down with a slope of –VOUT/L.
The output filter stores charge when the inductor current is high, and releases it when inductor current is low,
smoothing the voltage across the load.
The output voltage is regulated by modulating the PFET switch on time to control the average current sent to the
load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and
synchronous rectifier at the SW pin to a low-pass filter formed by the inductor and output filter capacitor. The
output voltage is equal to the average voltage at the SW pin.
8.3.1.2 PWM Operation
During pulse width modulation (PWM) operation the converter operates as a voltage mode controller with input
voltage feed forward. This allows the converter to achieve good load and line regulation. The DC gain of the
power stage is proportional to the input voltage. To eliminate this dependence, feed forward inversely
proportional to the input voltage is introduced.
While in PWM mode, the output voltage is regulated by switching at a constant frequency and then modulating
the energy per cycle to control power to the load. At the beginning of each clock cycle the PFET switch is turned
on, and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The
current limit comparator can also turn off the switch in case the current limit of the PFET is exceeded. Then the
NFET switch is turned on and the inductor current ramps down. The next cycle is initiated by the clock turning off
the NFET and turning on the PFET.
VSW
2V/DIV
IL
200 mA/DIV
VIN = 3.6V
VOUT = 1.5V
IOUT = 400 mA
VOUT
10 mV/DIV
AC Coupled
TIME (200 ns/DIV)
Figure 11. Typical PWM Operation
8.3.1.2.1 Internal Synchronous Rectification
While in PWM mode, the converters uses an internal NFET as a synchronous rectifier to reduce rectifier forward
voltage drop and associated power loss. Synchronous rectification provides a significant improvement in
efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier
diode.
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Feature Description (continued)
8.3.1.2.2 Current Limiting
A current limit feature allows the converters to protect itself and external components during overload conditions.
PWM mode implements current limiting using an internal comparator that trips at 2 A (typical). If the output is
shorted to ground the device enters a timed current limit mode where the NFET is turned on for a longer duration
until the inductor current falls below a low threshold, ensuring inductor current has more time to decay, thereby
preventing runaway.
8.3.1.3 PFM Operation
At very light loads, the converter enters pulse frequency modulation (PFM) mode and operates with reduced
switching frequency and supply current to maintain high efficiency.
The part automatically transitions into PFM mode when either of two conditions occurs for a duration of 32 or
more clock cycles:
1. The inductor current becomes discontinuous.
2. The peak PMOS switch current drops below the IMODE level (typically IMODE < 30 mA + VIN/42 Ω).
2V/DIV
VSW
IL
200 mA/DIV
VIN = 3.6V
VOUT = 1.5V
IOUT = 20 mA
VOUT
20 mV/DIV
AC Coupled
TIME (4 Ps/DIV)
Figure 12. Typical PFM Operation
During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage
during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy
load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output
FETs such that the output voltage ramps between < 0.6% and 3.1 V), the switch
automatically connects the LDO_RTC power to the main battery.
• As the main battery is discharged a separate circuit called nBATT_FLT warns the system. Then if no action is
taken to restore the charge on the main battery, and discharging is continued the battery switch disconnects
the input of the LDO_RTC from the main battery and connect to the backup battery.
• The main battery voltage at which the LDO_RTC is switched over from main to backup battery is 2.8 V
typically.
• There is a hysteric voltage in this switch operation, thus the LDO_RTC is not reconnected to main battery
until main battery voltage is greater than 3.1 V typically.
• The system designer may wish to disable the battery switch when only a main battery is used. This is
accomplished by setting the no backup battery bit in the control register 8h’0B bit 7 NBUB. With this bit set to
1, the switching does not occur; that is, the LDO_RTC remains connected to the main battery even as it is
discharged below the 2.9-V threshold. The backup battery input must also be connected to main battery.
20
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8.4 Device Functional Modes
8.4.1 Start-Up Mode
Start-up mode is entered once the battery backup supply is connected to LP3972. The RTC LDO is then turned
on to power the VCC_BATT pin of the application processor. Start-up state exits once nRSTO de-asserts (after a
minimum of 50 ms) and when nBATT_FLT de-asserts once system power is available.
8.4.2 Shutdown Mode
During shutdown the PFET switch, reference, control and bias circuitry of the converters are turned off. The
NFET switch opens in shutdown to discharge the output. When the converter is enabled, EN, soft start is
activated. It is recommended to disable the converter during the system power up and undervoltage conditions
when the supply is less than 2.7V.
8.4.3 Standby Mode
Once NRSTO and nBATT_FLT are de-asserted the LP3972 waits for SYS_EN signal in standby mode. All highvoltage power domains are still disabled in this state.
8.4.4 Active Mode
Once SYS_EN goes high the device begins turning on the high-voltage power supplies. Once PWR_EN goes
high the LP3972 enables the low-voltage power supplies. The Apps processor must monitor the “Power OK”
status bits before beginning execution of code to make sure all supplies have been properly enabled.
8.5 Programming
8.5.1 LP3972 Reset Sequence
8.5.1.1 LP3972 Controls
8.5.1.1.1 Digital Interface Control Signals
SIGNAL
DEFINITION
ACTIVE STATE
SIGNAL DIRECTION
SYS_EN
High Voltage Power Enable
High
Input
PWR_EN
Low Voltage Power Enable
High
Input
SCL
Serial Bus Clock Line
Clock
Input
SDA
Serial Bus Data Line
nRSTI
Forces an unconditional
hardware reset
Low
Input
nRSTO
Forces an unconditional
hardware reset
Low
Output
nBATT_FLT
Main Battery removed or
discharged indicator
Low
Output
PWR_ON
Wake-up Input to CPU
High
Input
nTEST_JIG
Wake-up Input to CPU
Low
Input
SPARE
Wake-up Input to CPU
High/Low
Input
EXT_WAKEUP
Wake-up Output for application
processor
High
Output
GPIO1 / nCHG_EN
General Purpose I/O /External
backup Battery Charger enable
—
Bidirectional /Input
GPIO2
General Purpose I/O
—
Bidirectional
Bidirectional
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8.5.1.1.2 Power Domain Enables
Table 3. Hardware and Software Enable Options for Each Supply
PMU OUTPUT
HW ENABLE
SW ENABLE
LDO_RTC
—
—
LDO1 (VCC_MVT)
SYS_EN
LDO1_EN
LDO2
SYS_EN
LDO2_EN
LDO3
SYS_EN
LDO3_EN
LDO4
SYS_EN
LDO4_EN
LDO5 (VCC_SRAM)
PWR_EN
S_EN
Buck1 (VCC_APPS)
PWR_EN
A_EN
BUCK2
SYS_EN
B2_EN
BUCK3
SYS_EN
B3_EN
8.5.1.1.3 Power Domains Sequencing (Delay)
By default SYS_EN must be on to have PWR_EN enable but this feature can be switched off by register bit
BP_SYS.
By default always enables SYS_EN LDO1 and, after a typical 1-ms delay, others. Also when SYS_EN is set off
the LDO1 goes off last. This function can be switched off or delay can be changed by DELAY bits via serial
interface as seen in Table 4.
8h’80 Bit 5:4
Table 4. Programmable Supply Delay Options
DELAY (bits)
DELAY (ms)
00
0
01
0.5
10
1
11
1.5
8.5.1.1.4 Power Supply Enable
SYS_EN and PWR_EN can be changed by programmable register bits.
8.5.1.1.5 Wake-up Functionality (PWR_ON, NTEST_JIG, SPARE and EXT_WAKEUP)
Three input pins can be used to assert wake-up output for 10 ms for application processor notification to wake
up. SPARE Input can be programmed through I2C-compatible interface to be active low or high (SPARE bit,
Default is active low 1). A reason for a wake-up event can be read through I2C-compatible interface also.
Additionally, wake-up inputs have 30 ms de-bounce filtering, and PWR_ON distinguishes between short and long
(∼1 s) pulses (push-button input). The LP3972 also has an internal thermal shutdown early warning that
generates a wake-up to the system also. This is generated usually at 125°C.
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PWR_ON
nTEST_JIG
SPARE
OR
EXT_WAKEUP
PWR_ON
EXT_WAKEUP
nTEST_JIG
10 ms
SPARE
Internal Thermal Early Warning
Figure 15. Wake-Up Functionality
Table 5. Wake-Up Functions
WAKE-UP REGISTER BITS
REASON FOR WAKE-UP
WUP0
SPARE
WUP1
TEST_JIG
WUP2
PWR_ON short pulse
WUP3
PWR_ON long pulse
TSD_EW
TSD Early Warning
8.5.1.1.6 Internal Thermal Shutdown Procedure
Thermal shutdown is build to generate early warning (typically 125°C) which triggers the EXT_WAKEUP for the
processor acknowledge. When a thermal shutdown triggers (typical 160°C) the PMU resets the system until the
device cools down.
8.5.1.1.7 Battery Switch and Backup Battery Charger
When backup battery is connected but the main battery has been removed or its supply voltage too low, the
LP3972 uses the backup battery for generating LDO_RTC voltage. When Main Battery is available the battery
FET switches over to the main battery for LDO_RTC voltage. When the main battery voltage is too low or
removed nBATT_FLT is asserted. If no backup battery exists, the battery switch to backup can be switched off
by nBU_BAT_EN bit. User can set the battery fault determination voltage and battery charger current via I2Ccompatible interface. Enabling of backup battery charger can be done via serial interface (nBAT_CHG_EN) or
external charger enable pin (nCHG_EN). The GPIO1/nCHG_EN pin is set as an external charger enable input by
default.
8.5.1.1.8 General Purpose I/O Functionality (GPIO1 And GPIO2)
The LP3972 has 2 general purpose I/Os for system control. I2C-compatible interface is used for setting any of the
pins to input, output or hi-Z mode. Inputs value can be read via serial interface (GPIO1,2 bits). The
GPIO1/nCHG_EN pin functionality needs to be set to GPIO by serial interface register bit nEXTCHGEN
(GPIO/CHG).
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Table 6. GPIO1 Configuration Options
PORT FUNCTION
reg
batmonchg
GPIO
GPIO
CONTROLS
Nextchgen_sel
bucen
GPIO1
Gpin 1
Function
X
X
1
0
Input = 0
0
Enabled
X
X
1
0
Input = 1
0
Not enabled
0
1
0
1
X
X
X
X
X
1
X
0
0
0
X
HiZ
1
0
0
X
Input (dig)->
Input
0
1
0
X
Output = 0
0
1
1
0
X
Output = 1
0
Enabled
Table 7. GPIO2 Configuration Options
GPIO
GPIO
GPIO_tstiob
GPIO2
gpin2
0
0
1
HiZ
0
1
0
1
Input (dig)->
input
0
1
1
Output = 0
0
1
1
1
Output = 1
0
The LP3972 has provision for two battery connections, the main battery VBAT and backup battery (see Figure 27).
The function of the battery switch is to connect power to the LDO_RTC from the appropriate battery, depending
on conditions described as follows:
• If only the backup battery is applied, the switch automatically connects the LDO_RTC power to this battery.
• If only the main battery is applied, the switch automatically connects the LDO_RTC power to this battery.
• If both batteries are applied, and the main battery is sufficiently charged (VBAT > 3.1 V), the switch
automatically connects the RTC LDO power to the main battery.
• As the main battery is discharged by use, the user is warned by a separate circuit called nBATT_FLT. Then if
no action is taken to restore the charge on the main battery, and discharging is continued the battery switch
protects the LDO_RTC by disconnecting from the main battery and connecting to the backup battery.
– The main battery voltage at which the LDO_RTC is switched from main to backup battery is 2.9 V
typically.
– There is a hysteresis voltage in this switch operation so, the LDO_RTC is not reconnected to main battery
until main battery voltage is greater than 3.1 V typically.
• Additionally, the user may wish to disable the battery switch, such as, in the case when only a main battery is
used. This is accomplished by setting the no backup battery bit in the control register 8h’89 bit 7 NBUB. With
this bit set to 1, the switching does not occur; that is, the LDO_RTC remains connected to the main battery
even as it is discharged below the 2.9-V threshold.
8.5.1.1.9 Regulated Voltages OK
All the power domains have own register bit (X_OK) that processor can read via serial interface to be sure that
enabled powers are OK (regulating). Note that these read only bits are only valid when regulators are settled
(avoid reading these bits during voltage change or power up).
8.5.1.1.10 Thermal Management
There is a mode wherein all 6 comparators (flags) can be turned on via the enallflags control register bit. This
mode allows the user to interrogate the device or system temperature under the set operating conditions. Thus,
the rate of temperature change can also be estimated. The system may then negotiate for speed and power
trade off, or deploy cooling maneuvers to optimize system performance. The enallflags bit needs enabled only
when the bct bits are read to conserve power.
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NOTE
The thermal management flags have been verified functional. Presently these registers
are accessible by factory only. If there is a demand for this function, the relevant register
controls may be shifted into the user programmable bank; the temperature range and
resolution of these flags, might also be refined or redefined.
8.5.1.1.11 Thermal Warning
Two of six low-power comparators, each consuming less than 1 µA, are always enabled to operate the T =
125°C warning flag with hysteresis. This allows continuous monitoring of a thermal-warning flag feature with very
low power consumption.
8.5.1.1.12 LP3972 Thermal Flags Functional Diagram, Data from Initial Silicon
Figure 16 shows extra features from the thermal shutdown circuit:
1) Thermal warning flag @ Temp ~ > ~125oC is issued at the wakeup port:
~30oC hysteresis
Temp 125oC
Warning flag
2) Binary coded thermal management flags in status registers, bct:
flag6
flag5
flag4
flag3
flag2
flag1
cool
17oC 20oC
43oC
46oC
62oC 65oC 83oC 86oC 106oC 108oC 128oC 130oC Temp
Figure 16. Thermal Shutdown Circuit Features
8.5.1.2 Initial Cold Start Power-On Sequence
1. The backup battery is connected to the PMU, power is applied to the backup battery pin, the LDO_RTC turns
on and supplies a stable output voltage to the VCC_BATT pin of the Applications processor (initiating the
power-on reset event) with nRSTO asserted from the LP3972 to the processor.
2. nRSTO de-asserts after a minimum of 50 ms.
3. The applications processor waits for the de-assertion of nBATT_FLT to indicate system power (VIN) is
available.
4. After system power (VIN) is applied, the LP3972 de-asserts nBATT_FLT. Note that BOTH nRSTO and
nBATT_FLT need to be de-asserted before SYS_EN is enabled. The sequence of the two signals is
independent of each other.
5. The Applications processor asserts SYS_EN, the LP3972 enables the system high-voltage power supplies.
The applications processor starts its countdown timer set to 125 ms.
6. The LP3972 enables the high-voltage power supplies.
– LDO1 power for VCC_MVT (power for internal logic and I/O Blocks), BG (bandgap reference voltage),
OSC13M (13-MHz oscillator voltage) and PLL enabled first, followed by others if delay is on.
7. Countdown timer expires; the applications processor asserts PWR_EN to enable the low-voltage power
supplies. The processor starts the countdown timer set to 125 ms period.
8. The applications processor asserts PWR_EN (ext. pin or I2C), the LP3972 enables the low-voltage
regulators.
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9. Countdown timer expires; if enabled power domains are OK (I2C read) the power-up sequence continues by
enabling the 13-MHz oscillator of the processor and PLLs.
10. The applications processor begins the execution of code.
See Power-On Timing Delays for more information.
t3
t1
t4
VIN BU Batt
1.
VCC_RTC
2.
nRSTO
VIN Main Batt
3,4.
nBATT_FLT
SYS_EN
5.
PXA27x Output
6.
High-Volt_PD
PWR_EN
7.
PXA27x Output
8.
Low-Volt_PD
t2
nRESET_OUT
PXA27x Output
13 MHZ_OSC
PXA27x Output
t5
9,10.
* Note that BOTH nRSTO and nBATT_FLT need to be de-asserted before SYS_EN is enabled. The sequence of the
two signals is independent of each other and can occur is either order.
Figure 17. Cold Start Power-On Efficiency
8.5.1.3 Hardware Reset Sequence
Hardware reset initiates when the nRSTI signal is asserted (low). Upon assertion of nRST the processor enters
hardware reset state. The LP3972 holds the nRST low long enough (50 ms typica) to allow the processor time to
initiate the reset state.
8.5.1.4 Reset Sequence
1. nRSTI is asserted.
2. nRSTO is asserted and de-asserts after a minimum of 50 ms.
3. The Applications processor waits for the de-assertion of nBATT_FLT to indicate system power (VIN) is
available.
4. After system power (VIN) is turned on, the LP3972 de-asserts nBATT_FLT.
5. The applications processor asserts SYS_EN, the LP3972 enables the system high-voltage power supplies.
The applications processor starts its countdown timer set to 125 ms.
6. The LP3972 enables the high-voltage power supplies.
7. Countdown timer expires; the applications processor asserts PWR_EN to enable the low-voltage power
supplies. The processor starts the countdown timer set to 125 ms.
8. The applications processor asserts PWR_EN, the LP3972 enables the low-voltage regulators.
9. Countdown timer expires; if enabled power domains are OK (I2C read) the power-up sequence continues by
enabling the 13-MHz oscillator of the processor and PLLs.
10. The applications processor begins the execution of code.
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8.5.2 I2C Compatible Interface
8.5.2.1 I2C Data Validity
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of
the data line can only be changed when CLK is LOW.
SCL
SDA
data valid
data
change
allowed
data
change
allowed
data
change
allowed
data valid
Figure 18. Data Validity
8.5.2.2 I2C Start And Stop Conditions
START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA
signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA
transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP bits.
The I2C bus is considered to be busy after START condition and free after STOP condition. During data
transmission, I2C master can generate repeated START conditions. First START and repeated START
conditions are equivalent, function-wise.
SDA
SCL
S
P
START condition
STOP condition
Figure 19. Stop and Start Conditions
8.5.2.3 Transferring Data
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
The number of bytes that can be transmitted per transfer is unrestricted. Each byte of data has to be followed by
an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter releases
the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the
9th clock pulse, signifying an acknowledge. A receiver which has been addressed must generate an
acknowledge after each byte has been received.
After the START condition, a chip address is sent by the I2C master. This address is seven bits long followed by
an eighth bit which is a data direction bit (R/W). The LP3972 address is 34h. For the eighth bit, a 0 indicates a
WRITE and a1 indicates a READ. The second byte selects the register to which the data will be written. The third
byte contains data to write to the selected register.
8.5.2.4 I2C Chip Address - 7h'34
Table 8. I2C Slave Address
MSB
ADR6
Bit7
ADR5
Bit6
ADR4
Bit5
ADR3
Bit4
ADR2
Bit3
ADR1
Bit2
ADR0
Bit1
R/W
Bit0
0
1
1
0
1
0
0
R/W
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8.5.2.4.1 Write Cycle
start
msb Chip Address lsb
w
ack
Msb Register Add lsb
ack
msb
DATA
lsb
ack
stop
w
ack
addr = 02h
ack
DGGUHVV K¶02 data
ack
stop
SCL
SDA
start
Id = 34h
Figure 20. Write Cycle
8.5.2.4.2 Read Cycle
When a READ function is to be accomplished, a WRITE function must precede the READ function as follows.
start
msb Chip Address lsb
w ack
msb Register Add lsb
ack
rs
w ack
addr = 00h
ack
rs
msb Chip Address lsb
r
ack
msb
DATA
lsb
ack
stop
SCL
SDA
start
Id = 34h
Id = 34h
r ack
$GGUHVV K¶00 data
ack stop
w = write (SDA = "0")
r = read (SDA = "1")
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
id = 34h (Chip Address)
Figure 21. Read Cycle
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
8
9
S
2
START
condition
I C - bus.
clock pulse for
acknowledgement
9ROWDJH µµ%¶¶
5 Ps TYP
9ROWDJH µµ$¶¶
VCC_APPS
Figure 22. I2C DVM Timing For VCC_APPS (Buck1)
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8.5.2.5 Multi-Byte I2C Command Sequence
To correctly function with the Monahan’s Power Management I2C the I2C serial interface of the device supports
random register multi-byte command sequencing: During a multi-byte write the Master sends the start command
followed by the device address, which is sent only once, followed by the 8-bit register address, then 8 bits of
data. The I2C slave must then accept the next random register address followed by 8 bits of data and continue
this process until the master sends a valid stop condition.
A typical multi-byte random register transfer is outlined in the following:
Device Address
Register A Address, Ach,
Register A Data, Ach
Register M Address, Ach,
Register M Data, Ach
Register X Address, Ach,
Register X Data, Ach
Register Z Address, Ach,
Register Z Data, Ach, Stop
NOTE
The PMIC is not required to see the I2C device address for each transaction. A, M, X, and
Z are Random numbers.
ack from slave
start
msb Chip Address lsb
w ack
ack from slave
msb Register Add lsb
ack
msb
ack from slave
DATA
lsb
ack
ack from slave
msb Register Add lsb
Register 0x24
ack
msb
ack from slave
DATA
lsb
ack
stop
Register 0x2A
Figure 23. Multi-Byte I2C Command
8.5.2.6 Incremental Register I2C Command Sequence
The LP3972 supports address increment (burst mode). When there is a defined register address n data bytes
can be sent, and the register address is incremented after each data byte has been sent. Address incrimination
may be required for non XScale applications. User can define whether multi-byte (default) to random address or
address incrimination will be used.
ack from slave
start
msb Chip Address lsb
w ack
ack from slave
msb Register Add lsb
Register 0x24
ack
msb
ack from slave
DATA1
lsb
ack
Data (reg_0x24)
msb
ack from slave
DATA2
lsb
Data (reg_0x25)
ack
msb
ack from slave
DATA3
lsb
ack
stop
Data (reg_0x26)
Figure 24. Incremental Register I2C Command
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8.6 Register Maps
Table 9. LP3972 Control Register
REGISTER ADDRESS
REGISTER NAME
READ/WRITE
8h’07
SCR
R/W
System Control Register
REGISTER DESCRIPTION
8h’10
OVER1
R/W
Output Voltage Enable Register 1
8h’11
OVSR1
R
Output Voltage Status Register 1
8h’12
OVER2
R/W
Output Voltage Enable Register 2
8h’13
OVSR2
R
Output Voltage Status Register 2
8h’20
VCC1
R/W
Voltage Change Control Register
1
8h’23
ADTV1
R/W
Buck1 Target Voltage 1 Register
8h’24
ADTV2
R/W
Buck1 DVM Target Voltage 2
Register
8h’25
AVRC
R/W
VCC_APPS Voltage Ramp Control
8h’26
CDTC1
W
Dummy Register
8h’27
CDTC2
W
Dummy Register
8h’29
SDTV1
R/W
LDO5 Target Voltage 1
8h’2A
SDTV2
R/W
LDO5 Target Voltage 2
8h’32
MDTV1
R/W
LDO1 Target Voltage 1 Register
8h’33
MDTV2
R/W
LDO1 Voltage 2 Register
8h’39
L2VCR
R/W
LDO2 Voltage Control Registers
8h’3A
L34VCR
R/W
LDO3 & LDO4 Voltage Control
Registers
8h’80
SCR1
R/W
System Control Register 1
8h’81
SCR2
R/W
System Control Register 2
8h’82
OEN3
R/W
Output Voltage Enable Register 3
8h’83
OSR3
R/W
Output Voltage Status Register 3
8h’84
LOER4
R/W
Output Voltage Enable Register 3
8h’85
B2TV
R/W
VCC_Buck2 Target Voltage
8h’86
B3TV
R/W
VCC_Buck3 Target Voltage
8h’87
B32RC
R/W
Buck 3:2 Voltage Ramp Control
8h’88
ISRA
R
8h’89
BCCR
R/W
8h’8E
II1RR
R
Internal 1 Revision Register
8h’8F
II2RR
R
Internal 2 Revision Register
Interrupt Status Register A
Backup Battery Charger Control
Register
8.6.1 Serial Interface Register Selection Codes
8.6.1.1 System Control Status Register
Register is an 8-bit register which specifies the control bits for the PMIC clocks. This register works in
conjunction with the SYNC pin where an external clock PLL buffer operating at 13 MHz is synchronized with the
oscillators of the buck converters.
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8.6.1.1.1 System Control Register (SCR) 8h’07
Bit
7
6
5
4
Designation
3
2
1
Reserved
Reset Value
0
0
0
0
0
CLK_SCL
0
0
0
0
8.6.1.1.2 System Control Register (SCR) 8h’07 Definitions
Bit
Access
Name
7-1
—
—
0
R/W
CLK_SCL
Description
Reserved
External Clock Select
0 = Internal oscillator clock for buck converters
1 = External 13-MHz oscillator clock for buck converters
8.6.1.2 Output Voltage Enable Register 1
This register enables or disables the low voltage supplies LDO1 and Buck1. See details below.
8.6.1.2.1 Output Voltage Enable Register 1 (OVER1) 8h’10
Bit
7
6
5
Designation
4
3
Reserved
Reset Value
0
0
0
0
0
2
1
0
S_EN
Reserved
A_EN
1
0
1
8.6.1.2.2 Output Voltage Enable Register 1 (OVER1) 8h’10 Definitions
Bit
Access
Name
Description
7-3
—
—
Reserved
2
R/W
S_EN
VCC_SRAM (LDO5) Supply Output Enabled
0 = VCC_SRAM (LDO5) Supply Output Disabled
1 = VCC_SRAM (LDO5) Supply Output Enabled
1
—
—
Reserved
0
R/W
A_EN
VCC_APPS (Buck1) Supply Output Enabled
0 = VCC_APPS (Buck1) Supply Output Disabled
1 = VCC_APPS_ (Buck1) Supply Output Enabled
8.6.1.3 Output Voltage Status Register
This 8-bit register is used to indicate the status of the low-voltage supplies. By polling each of the specify
supplies is within its specified operating range.
8.6.1.3.1 Output Voltage Status Register 1 (OVSR1) 8h’11
Bit
7
Designation
LP_OK
6
Reset Value
0
5
4
3
Reserved
0
0
0
0
2
1
0
S_OK
Reserved
A_OK
0
0
0
8.6.1.3.2 Output Voltage Status Register 1 (OVSR1) 8h’11 Definitions
Bit
Access
Name
Description
7
R
LP_OK
Low Voltage Supply Output Voltage Status
0 - VCC_APPS (Buck1) and VCC_SRAM (LDO5) output voltage < 90% of
selected value
1 - VCC_APPS (Buck1) and VCC_SRAM (LDO5) output voltage > 90% of
selected value
6:3
—
—
2
R
S_OK
Reserved
VCC-SRAM Supply Output Voltage Status
0 - VCC_SRAM (LDO5) output voltage < 90% of selected value
1 - VCC_SRAM (LDO5) output voltage > 90% of selected value
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Bit
Access
Name
1
—
—
0
R
A_OK
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Description
Reserved
VCC_APPS Supply output Voltage Status
0 - VCC_APPS (Buck1) output voltage < 90% of selected value
1 - VCC_APPS (Buck1) output voltage > 90% of selected value
8.6.1.4 Output Voltage Enable Register 2
This 8 bit output register enables and disables the output voltages on the LDOs 2,3,4 supplies.
8.6.1.4.1 Output Voltage Enable Register 2 (OVER2) 8h’12
Bit
7
6
Designation
Reset Value
(1)
5
Reserved
0
0
0
4 (1)
3 (1)
2 (1)
LDO4_EN
LDO3_EN
LDO2_EN
0
0
0
1
0
Reserved
0
0
One-time factory programmable EPROM registers for default values
8.6.1.4.2 Output Voltage Enable Register 2 (OVER2) 8h’12 Definitions
BIT
ACCESS
NAME
7
—
—
DESCRIPTION
Reserved
6
—
—
Reserved
5
—
—
Reserved
4
R/W
LDO4_EN
LDO4 Output Voltage Enable
0 = LDO4 Supply Output Disabled, Default
1 = LDO4 Supply Output Enabled
3
R/W
LDO3_EN
LDO3 Output Voltage Enable
0 = LDO3 Supply Output Disabled, Default
1 = LDO3 Supply Output Enabled
2
R/W
LDO2_EN
LDO2 Output Voltage Enable
0 = LDO2 Supply Output Disabled, Default
1 = LDO2 Supply Output Enabled
1
—
—
Reserved
0
—
—
Reserved
8.6.1.5 Output Voltage Status Register 2
8.6.1.5.1 Output Voltage Status Register 2 (OVSR2) 8h’13
BIT
7
6
5
4
3
2
1
0
Designation
LDO_OK
N/A
N/A
LDO4_OK
LDO3_OK
LDO2_OK
N/A
N/A
Reset Value
0
0
0
0
0
0
0
0
8.6.1.5.2 Output Voltage Status Register 2 (OVSR2) 8h’13 Definitions
32
BIT
ACCESS
NAME
7
R
LDO_OK
DESCRIPTION
6
—
—
Reserved
5
—
—
Reserved
4
R
LDO4_OK
LDO4 Output Voltage Status
0 - (VCC_LDO4) output voltage < 90% of selected value
1 - (VCC_LDO4) output voltage > 90% of selected value
3
R
LDO3_OK
LDO3 Output Voltage Status
0 - (VCC_LDO3) output voltage < 90% of selected value
1 - (VCC_LDO3) output voltage > 90% of selected value
LDOs 2-4 Supply Output Voltage Status
0 - (LDOs 2-4) output voltage < 90% of selected value
1 - (LDOs 2-4) output voltage > 90% of selected value
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BIT
ACCESS
NAME
2
R
LDO2_OK
DESCRIPTION
1
—
—
Reserved
0
—
—
Reserved
LDO2 Output Voltage Status
0 - (VCC_LDO2) output voltage < 90% of selected value
1 - (VCC_LDO2) output voltage > 90% of selected value
8.6.1.6 DVM Voltage Change Control Register 1
8.6.1.6.1 DVM Voltage Change Control Register 1 (VCC1) 8h’20
BIT
7
6
5
4
Designation
MVS
MGO
SVS
SGO
Reset Value
0
0
0
0
3
2
Reserved
0
1
0
AVS
AGO
0
0
0
8.6.1.6.2 DVM Voltage Change Control Register 1 (VCC1) 8h’20 Definitions
BIT
ACCESS
NAME
DESCRIPTION
7
R/W
MVS
VCC_MVT (LDO1) Voltage Select
0 - Change VCC_MVT Output Voltage to MDVT1
1 - Change VCC_MVT Output Voltage to MDVT2
6
R/W
MGO
Start VCC_MVT (LDO1) Voltage Change
0 - Hold VCC_MVT Output Voltage at current Level
1 - Ramp VCC_MVT Output Voltage as selected by MVS
5
R/W
SVS
VCC_SRAM (LDO5) Voltage Select
0 - Change VCC_SRAM Output Voltage to SDTV1
1 - Change VCC_SRAM Output Voltage to SDTV2
4
R/W
SGO
Start VCC_SRAM (LDO5) Voltage Change
0 - Hold VCC_SRAM Output Voltage at current Level
1 - Change VCC_SRAM Output Voltage as selected by SVS
3:2
—
—
1
R/W
AVS
Reserved
VCC_APPS (Buck1) Voltage Select
0 - Ramp VCC_APPS Output Voltage to ADVT1
1 - Ramp VCC_APPS Output Voltage to ADVT2
0
R/W
AGO
Start VCC_APPS(Buck1) Voltage Change
0 - Hold VCC_APPS Output Voltage at current Level
1 - Ramp VCC_APPS Output Voltage as selected by AVS
8.6.1.7 Buck1 (VCC_APPS) Voltage 1
8.6.1.7.1 Buck1 (VCC_APPS) Target Voltage 1 Register (ADTV1) 8h’23
BIT
7
6
Designation
Reset Value
(1)
5
4 (1)
3 (1)
0
0
1
Reserved
0
2 (1)
1 (1)
0 (1)
Buck1 Output Voltage (B1OV1)
0
0
1
1
One-time factory programmable
8.6.1.7.2 Buck1 (VCC_apps) Target Voltage 1 Register (ADTV1) 8h’23 Definitions
BIT
ACCESS
NAME
DESCRIPTION
7:5
—
—
Reserved
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BIT
ACCESS
NAME
4:0
R/W
B1OV1
www.ti.com
DESCRIPTION
Data Code
5h’0
5h’1
5h’2
5h’3
5h’4
5h’5
5h’6
5h’7
5h’8
5h’9
5h’A
5h’B
5h’C
5h’D
5h’E
5h’F
Output Voltage
0.725
0.750
0.775
0.800
0.825
0.850
0.875
0.900
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
Data Code
5h’10
5h’11
5h’12
5h’13
5h’14
5h’15
5h’16
5h’17
5h’18
5h’19
5h’1A
5h'1B (default)
5h’1C
5h’1D
5h’1E
5h’1F
Output Voltage
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400 (default)
1.425
1.450
1.475
1.500
8.6.1.8 Buck1 (VCC_APPS) Target Voltage 2 Register
8.6.1.8.1 Buck1 (VCC_APPS) Target Voltage 2 Register (ADTV2) 8h’24
BIT
7
6
Designation
Reset Value
5
4
3
Reserved
0
2
1
0
Buck1 Output Voltage (B1OV2)
0
0
0
1
0
1
1
8.6.1.8.2 Buck1 (VCC_APPS) Target Voltage 2 Register (ADTV2) 8h’24 Definitions
BIT
ACCESS
NAME
7:5
—
—
4:0
R/W
B1OV2
DESCRIPTION
Reserved
Data Code
5h’0
5h’1
5h’2
5h’3
5h’4
5h’5
5h’6
5h’7
5h’8
5h’9
5h’A
5h’B
5h’C
5h’D
5h’E
5h’F
Output Voltage
0.725
0.750
0.775
0.800
0.825
0.850
0.875
0.900
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
Data Code
5h’10
5h’11
5h’12
5h’13
5h’14
5h’15
5h’16
5h’17
5h’18
5h’19
5h’1A
5h’1B
5h’1C
5h’1D
5h’1E
5h’1F
Output Voltage
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
1.475
1.500
8.6.1.9 Buck1 (VCC_APPS) Voltage Ramp Control Register
8.6.1.9.1 Buck1 (VCC_APPS) Voltage Ramp Control Register (AVRC) 8h’25
BIT
7
6
Designation
Reset Value
5
4
3
Reserved
0
2
1
0
1
0
Ramp Rate (B1RR)
0
0
0
1
0
8.6.1.9.2 Buck1 (VCC_APPS) Voltage Ramp Control Register (AVRC) 8h’25 Definitions
34
BIT
ACCESS
NAME
7:5
—
—
DESCRIPTION
Reserved
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BIT
SNVS468L – SEPTEMBER 2006 – REVISED NOVEMBER 2015
ACCESS
NAME
DESCRIPTION
DVM Ramp Speed
4:0
R/W
Data Code
5h’0
5h’1
5h’2
5h’3
5h’4
5h’5
5h’6
5h’7
5h’8
5h’9
5h’A
4h’B-4h’1F
B1RR
Ramp Rate (mV/us)
Instant
1
2
3
4
5
6
7
8
9
10 (default)
Reserved
8.6.1.10 VCC_comm Target Voltage 1 Dummy Register (CDTV1)
8.6.1.10.1 VCC_comm Target Voltage 1 Dummy Register (CDTV1) 8h’26 Write Only (1)
BIT
7
6
Designation
Reset Value
(1)
5
4
3
0
0
0
2
Reserved
0
1
0
0
0
1
0
0
0
1* (1)
0 (1)
Output Voltage
0
0
2
CDTV1 must be writable by an I C controller. This is a dummy register
8.6.1.11 VCC_COMM Target Voltage 2 Dummy Register (CDTV2)
8.6.1.11.1 VCC_COMM Target Voltage 2 Dummy Register (CDTV2) 8h’27 Write Only (1)
BIT
7
6
Designation
Reset Value
(1)
5
4
3
0
0
0
2
Reserved
0
Output Voltage
0
0
2
CDTV2 must be writable by an I C controller. This is a dummy register and cannot be read.
This is a variable voltage supply to the internal SRAM of the application processor.
8.6.1.12 LDO5 (VCC_SRAM) Target Voltage 1 Register
8.6.1.12.1 LDO5 (VCC_SRAM) Target Voltage 1 Register (SDTV1) 8h'29
BIT
7
6
Designation
Reset Value
(1)
5
4 (1)
3 (1)
0
0
1
Reserved
0
2 (1)
LDO 5 Output Voltage (L5OV)
0
0
1
1
One-time factory programmable EPROM registers for default values
8.6.1.12.2 LDO5 (VCC_SRAM) Target Voltage 1 Register (SDTV1) 8h’29 Definitions
BIT
ACCESS
NAME
7:5
—
—
DESCRIPTION
Reserved
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36
BIT
ACCESS
NAME
4:0
R/W
B1OV
www.ti.com
DESCRIPTION
Data Code
5h’0
5h’1
5h’2
5h’3
5h’4
5h’5
5h’6
5h’7
5h’8
5h’9
5h’A
5h’B
5h’C
5h’D
5h’E
5h’F
Output Voltage
—
—
—
—
—
0.850
0.875
0.900
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
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Data Code
5h’10
5h’11
5h’12
5h’13
5h’14
5h’15
5h’16
5h’17
5h’18
5h’19
5h’1A
5h’1B (default)
5h’1C
5h’1D
5h’1E
5h’1F
Output Voltage
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400 (default)
1.425
1.450
1.475
1.500
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SNVS468L – SEPTEMBER 2006 – REVISED NOVEMBER 2015
8.6.1.13 LDO5 (VCC_SRAM) Target Voltage 2 Register
8.6.1.13.1 LDO5 (VCC_SRAM) Target Voltage 2 Register (SDTV2) 8h’2A
BIT
7
6
Designation
Reset Value
5
4
3
Reserved
0
2
1
0
1
1
LDO 5 Output Voltage (L5OV)
0
0
0
1
0
8.6.1.13.2 LDO5 (VCC_SRAM) Target Voltage 2 Register (SDTV2) 8h’2A Definitions
BIT
ACCESS
NAME
7:5
—
—
4:0
R/W
B1OV
DESCRIPTION
Reserved
Data Code
5h’0
5h’1
5h’2
5h’3
5h’4
5h’5
5h’6
5h’7
5h’8
5h’9
5h’A
5h’B
5h’C
5h’D
5h’E
5h’F
Output Voltage
—
—
—
—
—
0.850
0.875
0.900
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
Data Code
5h’10
5h’11
5h’12
5h’13
5h’14
5h’15
5h’16
5h’17
5h’18
5h’19
5h’1A
5h’1B
5h’1C
5h’1D
5h’1E
5h’1F
Output Voltage
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
1.475
1.500
VCC_MVT is low tolerance regulated power supply for the application processor ring oscillator and logic for
communicating to the LP3972. VCC_MVT is enabled when SYS_EN is asserted and disabled when SYS_EN is
deasserted.
8.6.1.14 LDO1 (VCC_MVT) Target Voltage 1 Register (MDTV1)
8.6.1.14.1 LDO1 (VCC_MVT) Target Voltage 1 Register (MDTV1) 8h’32
BIT
7
6
Designation
Reset Value
(1)
5
4 (1)
3 (1)
Reserved
0
2 (1)
1 (1)
0 (1)
0
0
Output Voltage (OV)
0
0
0
0
1
One-time factory programmable EPROM registers for default values.
8.6.1.14.2 LDO1 (VCC_MVT) Target Voltage 1 Register (MDTV1) 8h’32 Definitions
BIT
ACCESS
NAME
7:5
—
—
4:0
R/W
L1OV
DESCRIPTION
Reserved
Data Code
5h’0
5h’1
5h’2
5h’3
5h’4 (default)
5h’5
5h’6
5h’7
5h’8
5h’9
5h’A
5h’B
5h’C
5h’D-5h’F
Output Voltage
1.700
1.725
1.750
1.775
1.800 (default)
1.825
1.850
1.875
1.900
1.925
1.950
1.975
2.000
Reserved
Notes:
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8.6.1.15 LDO1 (VCC_MVT) Target Voltage 2 Register
8.6.1.15.1 LDO1 (VCC_MVT) Target Voltage 2 Register (MDTV2) 8h’33
BIT
7
6
Designation
Reset Value
5
4
3
Reserved
0
2
1
0
1
1
Output Voltage (OV)
0
0
0
1
0
8.6.1.15.2 LDO1 (VCC_MVT) Target Voltage 2 Register (MDTV2) 8h’33 Definitions
BIT
ACCESS
NAME
7:5
—
—
4:0
R/W
L1OV
DESCRIPTION
Reserved
Data Code
5h’0
5h’1
5h’2
5h’3
5h’4 (default)
5h’5
5h’6
5h’7
5h’8
5h’9
5h’A
5h’B
5h’C
5h’D-5h’F
Output Voltage
1.700
1.725
1.750
1.775
1.800 (default)
1.825
1.850
1.875
1.900
1.925
1.950
1.975
2.000
Reserved
Notes:
8.6.1.16 LDO2 Voltage Control Register (L12VCR)
8.6.1.16.1 LDO2 Voltage Control Register (L12VCR) 8h’39
BIT
7 (1)
Designation
Reset Value
(1)
6 (1)
5 (1)
4 (1)
3
2
LDO2 Output Voltage (L2OV)
0
0
0
1
0
0
0
Reserved
0
0
0
One-time factory programmable EPROM registers for default values.
8.6.1.16.2 LDO2 Voltage Control Register (L12VCR) 8h’39 Definitions
38
BIT
ACCESS
NAME
7:4
R/W
L2OV
Data Code
4h’0 (default)
4h’1
4h’2
4h’3
4h’4
4h’5
4h’6
4h’7
4h’8
4h’9
4h’A
4h’B
4h’C
4h’D
4h’E
4h’F
DESCRIPTION
3:0
—
—
Reserved
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Output Voltage
1.8 (Default)
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
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8.6.1.17 LDO4 – LDO3 Voltage Control Register (L34VCR)
8.6.1.17.1 LDO4 – LDO3 Voltage Control Register (L34VCR) 8h’3A
BIT
7 (1)
Designation
Reset Value
(1)
6 (1)
5 (1)
4 (1)
3 (1)
0
0
LDO4 Output Voltage (L4OV)
0
0
0
2 (1)
1 (1)
0 (1)
LDO3 Output Voltage (L3OV)
0
0
0
One-time factory programmable EPROM registers for default values.
8.6.1.17.2 LDO4 – LDO3 Voltage Control Register (L34VCR) 8h’3A Definitions
BIT
ACCESS
NAME
7:4
R/W
L4OV
Data Code
4h’0
4h’1
4h’2
4h’3
4h’4
4h’5
4h’6
4h’7
4h’8
4h’9
4h’A
4h’B
4h’C
4h’D
4h’E (default0
4h’F
DESCRIPTION
Output Voltage
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.50
1.80
1.90
2.50
2.80
3.00 (default) (Default)
3.30
3:0
R/W
L3OV
Data Code
4h’0
4h’1
4h’2
4h’3
4h’4
4h’5
4h’6
4h’7
4h’8
4h’9
4h’A
4h’B
4h’C (default)
4h’D
4h’E
4h’F
Output Voltage
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0 (Default)
3.1
3.2
3.3
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8.6.2 TI-Defined Control and Status Registers
8.6.2.1 System Control Register 1 (SCR1)
8.6.2.1.1 System Control Register 1 (SCR1) 8h’80
BIT
7 (1)
Designation
BPSEN
Reset Value
0
(1)
6 (1)
5 (1)
SENDL
1
0
4
3
2
1
0
FPWM3
FPWM2
FPWM1
BK_SLOMOD
BK_SSEN
0
0
0
0
0
One-time factory programmable EPROM registers for default values.
8.6.2.1.2 System Control Register 1 (SCR1) 8h’80 Definitions
BIT
ACCESS
NAME
7
R/W
BPSEN
DESCRIPTION
Bypass System enable safety Lock. Prevents activation of PWR_EN
when SYS_EN is low.
0 = PWR_EN "AND" with SYS_EN signal, Default
1 = PWR_EN independent of SYS_EN
Delay time for High Voltage Power Domains LDO2, LDO3, LDO4,
Buck2, and Buck3 after activation of SYS_EN. VCC_LDO1 has no
delay.
Data Code
2h’0
2h’1
2h’2
2h’3
Delay (ms)
0.0
0.5
1 (Default)
1.4
6:5
R/W
SENDL
4
R/W
FPWM3
Buck3 PWM/PFM Mode select
0 - Auto Switch between PFM and PWM operation
1 - PWM Mode Only does not switch to PFM
3
R/W
FPWM2
Buck2 PWM/PFM Mode select
0 - Auto Switch between PFM and PWM operation
1 - PWM Mode Only does not switch to PFM
2
R/W
FPWM1
Buck1 PWM/PFM Mode select
0 - Auto Switch between PFM and PWM operation
1 - PWM Mode Only does not switch to PFM
1
R
BK_SLOMOD
0
R
BK_SSEN
Buck Spread Spectrum Modulation Bucks 1-3
0 = 10 kHz triangular wave spread spectrum modulation
1 = 2 kHz triangular wave spread spectrum modulation
Spread spectrum function Bucks 1-3
0 = SS Output Disabled
1 = SS Output Enabled
8.6.2.2 System Control Register 2 (SCR2)
8.6.2.2.1 System Control Register 2 (SCR2) 8h’81
BIT
Designation
(1)
7
6
5 (1)
4
BBCS
SHBU
BPTR
WUP3
1
0
1
1
3
2
1
GPIO2
0
0
GPIO1
0
1
0
One time factory programmable EPROM registers for default values.
8.6.2.2.2 System Control Register 2 (SCR2) 8h’81 Definitions
40
BIT
ACCESS
NAME
7
R/W
BBCS
6
R/W
SHBU
DESCRIPTION
Sets GPIO1 as control input for backup battery charger
0 - Backup battery Charger GPIO Disabled
1 - Backup battery Charger GPIO Pin Enabled
Shut down backup battery to prevent battery drain during shipping
0 = Backup Battery Enabled
1 = Backup battery Disabled
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BIT
ACCESS
NAME
5
R/W
BPTR
Bypass LDO_RTC Output Voltage to LDO3 Output Voltage Tracking
0 - LDO_RTC3 Tracking enabled
1 - LDO_RTC3 Tracking disabled, Default
DESCRIPTION
4
R/W
WUP3
Spare Wake-up control input
0 - Active High
1 - Active Low
3:2
R/W
GPIO2
Configure direction and output sense of GPIO2 Pin
Data Code
2h’00
2h’01
2h’02
2h’03
1:0
R/W
GPIO1
GPIO2
Hi-Z
Output Low
Input
Output high
Configure direction and output sense of GPIO1 Pin
Data Code
2h’00
2h’01
2h’02
2h’03
GPIO1
Hi-Z
Output Low
Input
Output high
8.6.2.3 Output Enable 3 Register (OEN3) 8h’82
BIT
7
6
Designation
Reset Value
(1)
Reserved
0
4 (1)
3
2 (1)
1
0 (1)
B3EN
ENFLAG
B2EN
Reserved
L1EN
1
0
1
0
1
5
0
0
One time factory programmable EPROM registers for default values.
8.6.2.4 Output Enable 3 Register (OEN3) 8h’82 Definitions
BIT
ACCESS
NAME
7:5
—
—
4
R/W
B3EN
3
R/W
ENFLAG
2
R/W
B2EN
1
—
—
0
R/W
L1EN
DESCRIPTION
Reserved
VCC_Buck3 Supply Output Enabled
0 = VCC_Buck3 Supply Output Disabled
1 = VCC_Buck3 Supply Output Enabled, Default
Enable for Temperature Flags (BCT)
0 = Temperature Flag Disabled
1 = Temperature Flag Enabled
VCC_Buck2 Supply Output Enabled
0 = VCC_Buck2 Supply Output Disabled
1 = VCC_Buck2 Supply Output Enabled, Default
Reserved
LDO1 (MVT)Output Voltage Enable
0 = LDO1 Supply Output Disabled
1 = LDO1 Supply Output Enabled, Default
8.6.2.5 Status Register 3 (OSR3) 8h’83
7
6
5
4
3
2
1
0
Designation
BIT
BT_OK
B3_OK
B2_OK
LDO1_OK
Reserved
BCT2
BCT1
BCT0
Reset Value
0
0
0
0
0
0
0
0
8.6.2.6 Status Register 3 (OSR3) Definitions 8h’83
BIT
ACCESS
NAME
7
R
BT_OK
DESCRIPTION
Bucks 2-3 Supply Output Voltage Status
0 - (Bucks 1-3) output voltage < 90% Default value
1 - (Bucsk 1-3) output voltage > 90% Default value
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BIT
ACCESS
NAME
6
R
B3_OK
Buck3 Supply Output Voltage Status
0 - (Buck3) output voltage < 90% Default value
1 - (Buck3) output voltage > 90% Default value
DESCRIPTION
5
R
B2_OK
Buck2 Supply Output Voltage Status
0 - (Buck2) output voltage < 90% Default value
1 - (Buck2) output voltage > 90% Default value
4
R
LDO1_OK
3
—
—
2:0
R
BCT
LDO1 Output Voltage Status
0 - (VCC_LDO1) output voltage < 90% of selected value
1 - (VCC_LDO1) output voltage > 90% of selected value
Reserved
Binary coded thermal management flag status register
Temperature
Ascending °C
40
60
80
100
120
140
160
Reserved
Data Code
000
001
010
011
100
101
110
111
8.6.2.7 Logic Output Enable Register (LOER) 8h’84
7
6 (1)
5 (1)
4 (1)
3 (1)
2 (1)
1 (1)
0 (1)
Designation
Reserved
B3ENC
B2ENC
B1ENC
L5EC
L4EC
L3EC
L2EC
Reset Value
0
1
1
0
0
1
1
1
BIT
(1)
One time factory programmable EPROM registers for default values.
8.6.2.8 Logic Output Enable Register (LOER) Definitions 8h’84
42
BIT
ACCESS
NAME
7
—
—
DESCRIPTION
6
R/W
B3ENC
Connects Buck3 enable to SYS_EN or PWR_EN Logic Control pin
0 - Buck3 enable connected to PWR_EN
1 - Buck3 enable connected to SYS_EN, Default
5
R/W
B2ENC
Connects Buck2 enable to SYS_EN or PWR_EN Logic Control pin
0 - Buck2 enable connected to PWR_EN
1 - Buck2 enable connected to SYS_EN, Default
4
R/W
B1ENC
Connects Buck1 enable to SYS_EN or PWR_EN Logic Control pin
0 - Buck1 enable connected to PWR_EN, Default
1 - Buck1 enable connected to SYS_EN
3
R/W
L5EC
Connects LDO5 enable to SYS_EN or PWR_EN Logic Control pin
0 - LDO5 enable connected to PWR_EN, Default
1 - LDO5 enable connected to SYS_EN
2
R/W
L4EC
Connects LDO4 enable to SYS_EN or PWR_EN Logic Control pin
0 - LDO4 enable connected to PWR_EN
1 - LDO4 enable connected to SYS_EN, Default
1
R/W
L3EC
Connects LDO3 enable to SYS_EN or PWR_EN Logic Control pin
0 - LDO3 enable connected to PWR_EN
1 - LDO3 enable connected to SYS_EN, Default
0
R/W
L2EC
Connects LDO2 enable to SYS_EN or PWR_EN Logic Control pin
0 - LDO2 enable connected to PWR_EN
1 - LDO2 enable connected to SYS_EN, Default
Reserved
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8.6.2.9 VCC_BUCK2 Target Voltage Register (B2TV) 8h’85
Bit
7
6
Designation
Reset Value
(1)
5
4 (1)
3 (1)
0
1
1
Reserved
0
2 (1)
1 (1)
0 (1)
Buck2 Output Voltage (B2OV)
0
0
0
1
One time factory programmable EPROM registers for default values.
8.6.2.10 VCC_BUCK2 Target Voltage Register (B2TV) 8h’85 Definitions
Bit
Access
7:5
—
4:0
R/W
Name
Description
Reserved
B2OV
Output Voltage
Data Code
5h’01
5h’02
5h’03
5h’04
5h’05
5h’06
5h’07
5h’08
5h’09
5h’0A
5h’0B
5h’0C
(V)
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
Data Code
5h’0D
5h’0E
5h’0F
5h’10
5h’11
5h’12
5h’13
5h’14
5h’15
5h’16
5h’17
5h’18
5h’19 (default)
(V)
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.80
1.90
2.50
2.80
3.00
3.30 (default)
8.6.2.11 BUCK3 Target Voltage Register (B3TV) 8h’86
Bit
7
6
Designation
Reset Value
(1)
5
4 (1)
3 (1)
0
1
0
Reserved
0
0
2 (1)
1 (1)
0 (1)
Buck3 Output Voltage (B3OV)
1
0
0
One time factory programmable EPROM registers for default values.
8.6.2.12 BUCK3 Target Voltage Register (B3TV) 8h’86 Definitions
Bit
Access
7:5
—
4:0
R/W
Name
Description
Reserved
B3OV
Output Voltage
Data Code
5h’01
5h’02
5h’03
5h’04
5h’05
5h’06
5h’07
5h’08
5h’09
5h’0A
5h’0B
5h’0C
(V)
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
Data Code
5h’0D
5h’0E
5h’0F
5h’11
5h’12
5h’13
5h’14 (default)
5h’15
5h’16
5h’17
5h’18
5h’19
(V)
1.40
1.45
1.50
1.60
1.65
1.70
1.80 (default)
1.90
2.50
2.80
3.00
3.30
Default
8.6.2.13 VCC_BUCK3:2 Voltage Ramp Control Register (B32RC)
8.6.2.13.1 VCC_BUCK3:2 Voltage Ramp Control Register (B32RC) 8h’87
Bit
7
Designation
Reset Value
6
5
4
3
0
1
Ramp Rate (B3RR)
1
0
1
2
1
0
Ramp Rate (B2RR)
0
1
0
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8.6.2.13.2 Buck3:2 Voltage Ramp Control Register (B3RC) 8h’87 Definitions
Bit
Access
Name
7:4
R/W
B3RR
Data Code
4h’0
4h’1
4h’2
4h’3
4h’4
4h’5
4h’6
4h’7
4h’8
4h’9
4h’A
Description
Ramp Rate mV/µS
Instant
1
2
3
4
5
6
7
8
9
10
3:0
R/W
B2RR
Data Code
4h’0
4h’1
4h’2
4h’3
4h’4
4h’5
4h’6
4h’7
4h’8
4h’9
4h’A (default)
Ramp Rate mV/µS
Instant
1
2
3
4
5
6
7
8
9
10 (default)
8.6.2.14 Interrupt Status Register ISRA
This register specifies the status bits for the interrupts generated by the LP3972 device.
8.6.2.14.1 Interrupt Status Register ISRA 8h’88
Bit
7
6
5
4
3
2
1
0
Designation
Reserved
T125
GPI2
GPI1
WUP3
WUP2
WUPT
WUPS
Reset Value
0
0
0
0
0
0
0
0
8.6.2.14.2 Interrupt Status Register ISRA 8h’88 Definitions
44
Bit
Access
Name
7
—
—
Description
6
R
T125
Status bit for thermal warning PMIC T>125°C
0 = PMIC Temp. < 125°C
1 = PMIC Temp. > 125°C
5
R
GPI2
Status bit for the input read in from GPIO 2 when set as Input
0 = GPI2 Logic Low
1 = GPI2 Logic High
4
R
GPI1
Status bit for the input read in from GPIO 1 when set as Input
0 = GPI1 Logic Low
1 = GPI1 Logic High
3
R
WUP3
PWR_ON Pin long pulse wake-up status
0 = No wake-up event
1 = Long pulse wake-up event
2
R
WUP2
PWR_ON Pin Short pulse wake-up Status
0 = No wake-up event
1 = Short pulse wake-up event
1
R
WUPT
TEST_JIG Pin wake-up Status
0 = No wake-up event
1 = Wake-up event
0
R
WUPS
SPARE pin wake-up status
0 = No wake-up event
1 = Wake-up event
Reserved
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8.6.2.15 Backup Battery Charger Control Register (BCCR)
This register specifies the status of the main battery supply (NBUB bit).
8.6.2.15.1 Backup Battery Charger Control Register (BCCR) 8h’89
7 (1)
6
Designation
NBUB
CNBFL
Reset Value
0
0
Bit
(1)
5 (1)
4 (1)
3 (1)
2
nBFLT
0
1
BUCEN
1
0
0
0
IBUC
0
1
One-time factory programmable EPROM registers for default values.
8.6.2.15.2 Backup Battery Charger Control Register (BCCR) 8h’89 Definitions
Bit
Access
Name
7
R/W
NBUB
No backup battery default setting. Logic does not allow switch-over to backup
battery.
0 = Backup Battery Enabled, Default
1 = Backup Battery Disabled
Description
6
R/W
CNBFL
Control for nBATT_FLT output signal
0 = nBATT_FLT Enabled
1 = nBATT_FLT Disabled
nBATT_FLT monitors the battery voltage and can be set to the Assert voltages
listed below.
5:3
R/W
BFLT
2
R/W
BUCEN
Data Code
3h’01
3h’02
3h’03
3h’04
3h’05
Asserted
2.6
2.8 (default)
3.0
3.2
3.4
De-Asserted
2.8
3.0 (Default)
3.2
3.4
3.6
Enables backup battery charger
0 = Backup Battery Charger Disabled
1 = Backup Battery Charger Enabled
Charger current setting for backup battery
1:0
8.6.2.16
Bit
R/W
Data Code
2h’00
2h’01 (default)
2h’02
2h’03
IBUC
Marvell PXA Internal 1 Revision Register (II1RR) 8h’8E
7
6
5
4
0
0
0
0
Designation
Reset Value
BU Charger I (µA)
260
190 (Default)
325
390
3
2
1
0
0
0
0
0
II1RR
8.6.2.17 Marvell PXA Internal 1 Revision Register (II1RR) (Ii1rr) 8h’8E Definitions
Bit
Access
Name
7:0
R
II1RR
8.6.2.18
Bit
Description
Intel internal usage register for revision information.
Marvell PXA Internal 2 Revision Register (II1RR) 8h’8F
7
6
5
4
Designation
Reset Value
3
2
1
0
0
0
0
0
II2RR
0
0
0
0
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8.6.2.19 Marvell PXA Internal 2 Revision Register (II1RR) 8h’8F Definitions
Bit
Access
Name
7:0
R
II2RR
Description
Intel internal usage register for revision information.
8.6.2.20 Register Programming Examples
8.6.2.20.1 Example 1: Start-of-Day (SOD) Sequence
PMIC Register
Address
PMIC Register
Name
Register Data
8h’23
ADTVI
00011011
Sets the SOD VCC_APPS voltage
8h’29
SDTV1
00011011
Sets the SOD VCC_SRAM voltage
8h’10
OVER1
00000111
Enables VCC_SRAM and VCC_APPS to their programmed values.
Description
SODl multi-byte random register transfer is shown in Figure 25:
Device ID
Start
Ack
W
0 1 1 0 1 0 0 0
ADTV1 (8Z[23)
Register Data (00011011)
Register Address
0 0 1 0 0 0 1 1
Ack
SDTV1 (8Z[29)
Data
0 0 0 1 1 0 1 1
Ack
Register Data (00011011)
Register Address
0 0 1 0 1 0 0 1
Ack
OVER1 (8Z[10)
Data
0 0 0 1 1 0 1 1
Ack
Register Data (00000111)
Register Address
0 0 0 1 0 0 0 0
Ack
Data
0 0 0 0 0 1 1 1
Ack
Stop
Figure 25. SOD Multi-Byte Random Register Transfer
Device Address
Register A Address, Ach,
Register A Data, Ach
Register M Address, Ach,
Register M Data, Ach
Register X Address, Ach,
Register X Data, Ach
Register Z Address, Ach,
Register Z Data, Ach, Stop
8.6.2.20.2 Example 2: Voltage Change Sequence
PMIC Register
Address
PMIC Register
Name
Register Data
8h’24
ADTV2
00010111
Sets the VCCAPPS_ target voltage 2 to 1.3 V.
8h’2A
SDTV2
00001111
Sets the VCC_SRAM target voltage 2 to 1.1 V.
8h’20
VCC1
00110011
Enables VCC_SRAM and VCC_APPS to change to their programmed target
values.
46
Description
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8.6.2.20.3 I2C Data Exchange Between Master and Slave Device
Start
Device ID
W
Ack
0 1 1 0 1 0 0 0
ADTV2 (8Z[24)
Register Data (00010111)
Register Address
0 0 1 0 0 1 0 0
Ack
SDTV2 (8Z[2A)
Data
0 0 0 1 0 1 1 1
Ack
Register Data (00001111)
Register Address
0 0 1 0 1 0 1 0
Ack
VCC1 (8Z[20)
Data
0 0 0 0 1 1 1 1
Ack
Register Data (00110011)
Register Address
0 0 1 0 0 0 0 0
Ack
Data
0 0 1 1 0 0 1 1
Ack
Stop
Figure 26. Master and Slave Data Exchange
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LP3972 is designed for powering systems that use advanced application processors. The device is
specifically optimized for lower power handheld applications using Lithium-Ion main battery, DC chargers, and
battery backup. The device is internally powered from the VIN and VDDA pins, and voltage must be in 2.7-V to
5.5-V range. The device has flexible configurability; output supply voltages and start-up delays for the buck
converters and LDOs are configured via I2C registers.
9.2 Typical Application
APPLICATION
PROCESSOR
2.7 V - 5.5 V
Battery
VIN
SW1
CPU CORE
VDDA
VINLDO5
FB1
PGND1
VINLDO4
SW2
USB
VINBUCK3
4.5 V - 5.5 V
DC Source
Backup
Battery
VINBUCK2
FB2
PGND2
VINBUCK1
SW3
UART
FB3
PGND3
VINBUBATT
BG
VOUTLDO1
VoutLDO_RTC
MVT
AP_IO
VOUTLDO3
LP3972
PWR_ON
PLL
VOUTLDO4
GPIO1/nCHG_EN
nTEST_JIG
SRAM
VOUTLDO5
GPIO2
SPARE
RTC
VOUTLDO_RTC
nRSTI
3.3 V
SYNC
CODEC
SCL
SDA
PWR_EN
SYS_EN
VOUTLDO2
nRSTO
EXIT_WAKEUP
nBATT_FLT
VREF
GND1
BGND1,2,3
Figure 27. LP3972 Typical Application
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Typical Application (continued)
9.2.1 Design Requirements
For typical PMU advanced application processor applications, use the parameters listed in Table 10.
Table 10. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Minimum input voltage
2.7
Maximum input voltage
5.5
External SYNC clock used
No
LDO RTC output voltage
2.8 V
LDO1 output voltage
1.8 V
LDO2 output voltage
1.8 V
LDO3 output voltage
3V
LDO4output voltage
3V
LDO5 output voltage
1.4 V
BUCK1 output voltage
1.4 V
BUCK2 output voltage
3.3 V
BUCK3 output voltage
1.8 V
Low voltage designated rails
LDO5, BUCK1
High voltage designated rails
LDO1, LDO2, LDO3, LDO4, BUCK2, BUCK3
9.2.2 Detailed Design Procedure
9.2.2.1 LDO Considerations
9.2.2.1.1 External Capacitors
Regulators of the LP3972require external capacitors for regulator stability. These are specifically designed for
portable applications requiring minimum board space and smallest components. These capacitors must be
correctly selected for good performance.
9.2.2.1.2 Input Capacitor
An input capacitor is required for stability. It is recommended that a 1-µF capacitor be connected between the
LDO input pin and ground (this capacitance value may be increased without limit).
This capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean
analogue ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.
NOTE
Tantalum capacitors can suffer catastrophic failures due to surge current when
connected to a low impedance source of power (like a battery or a very large
capacitor). If a tantalum capacitor is used at the input, it must be ensured by the
manufacturer to have a surge current rating sufficient for the application.
There are no requirements for the equivalent series resistance (ESR) on the input capacitor, but tolerance and
temperature coefficient must be considered when selecting the capacitor to ensure the capacitance remains
approximately 1 µF over the entire operating temperature range.
9.2.2.1.3 Output Capacitor
The LDOs are designed specifically to work with very small ceramic output capacitors. A 1-µF ceramic capacitor
(temperature types Z5U, Y5V or X7R) with ESR between 5 mΩ to 500 mΩ, are suitable in the application circuit.
For this device the output capacitor must be connected between the VOUT pin and ground.
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It is also possible to use tantalum or film capacitors at the device output, COUT (or VOUT), but these are not as
attractive for reasons of size and cost (see Capacitor Characteristics).
The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR
value that is within the range 5 mΩ to 500 mΩ for stability.
9.2.2.1.4 No-Load Stability
The LDOs remain stable and in regulation with no external load. This is an important consideration in some
circuits, for example CMOS RAM keep-alive applications.
9.2.2.1.5 Capacitor Characteristics
The LDOs are designed to work with ceramic capacitors on the output to take advantage of the benefits they
offer. For capacitance values in the range of 0.47 µF to 4.7 µF, ceramic capacitors are the smallest, least
expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The
ESR of a typical 1-µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR
requirement for stability for the LDOs.
CAP VALUE (% OF NOMINAL 1 PF)
For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure
correct device operation. The capacitor value can change greatly, depending on the operating conditions and
capacitor type. In particular, the output capacitor selection must take account of all the capacitor parameters, to
ensure that the specification is met within the application. The capacitance can vary with DC bias conditions as
well as temperature and frequency of operation. Capacitor values may also show some decrease over time due
to aging. The capacitor parameters are also dependant on the particular case size, with smaller sizes giving
poorer performance figures in general. As an example, Figure 28 shows a typical graph comparing different
capacitor case sizes. As shown in Figure 28, increasing the DC bias condition can result in the capacitance value
falling below the minimum value given in the recommended capacitor specifications table. Note that the graph
shows the capacitance out of spec for the 0402 case size capacitor at higher bias voltages. It is therefore
recommended that the capacitor manufacturers’ specifications for the nominal value capacitor are consulted for
all conditions, as some capacitor sizes (for example, 0402) may not be suitable in the actual application.
0603, 10V, X5M
100%
80%
60%
40%
0402, 6.3V, X5R
20%
0
1.0
2.0
3.0
4.0
5.0
DC BIAS (V)
Figure 28. Typical Variation in Capacitance vs DC Bias
Capacitance of the ceramic capacitor can vary with temperature. The capacitor type X7R, which operates over a
temperature range of −55°C to +125°C, only varies the capacitance to within ±15%. The capacitor type X5R has
a similar tolerance over a reduced temperature range of −55°C to +85°C. Many large value ceramic capacitors,
larger than 1 µF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance can drop by
more than 50% as the temperature varies from 25°C to 85°C. Therefore X7R is recommended over Z5U and
Y5V in applications where the ambient temperature changes significantly above or below 25°C.
Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more
expensive when comparing equivalent capacitance and voltage ratings in the 0.47-µF to 4.7-µF range.
Another important consideration is that tantalum capacitors have higher ESR values than equivalent size
ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the
stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic
capacitor with the same ESR value. The ESR of a typical tantalum increases about 2:1 as the temperature goes
from 25°C down to –40°C, so some guard band must be allowed.
50
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9.2.2.2 Buck Considerations
9.2.2.2.1 Inductor Selection
There are two main considerations when choosing an inductor; the inductor must not saturate, and the inductor
current ripple is small enough to achieve the desired output voltage ripple. Different saturation current rating
specificationss are followed by different manufacturers so attention must be given to details. Saturation current
ratings are typically specified at 25°C so ratings at maximum ambient temperature of application should be
requested from manufacturer.
There are two methods to choose the inductor saturation current rating.
9.2.2.2.1.1 Method 1
The saturation current is greater than the sum of the maximum load current and the worst case average to peak
inductor current (Equation 2):
ISAT > IOUTMAX + IRIPPLE
*
§ VOUT
¨
¨ VIN
©
§
¨
¨
©
§
¨
¨
©
§ VIN - VOUT
¨
¨ 2* L
©
*
§1
¨
¨f
©
§
¨
¨
©
where IRIPPLE =
where
•
•
•
•
•
•
IRIPPLE: Average to peak inductor current
IOUTMAX: Maximum load current (1500 mA)
VIN: Maximum input voltage in application
L: Minimum inductor value including worst case tolerances (30% drop can be considered for Method 1)
f: Minimum switching frequency (1.6 MHz)
VOUT: Output voltage
(2)
9.2.2.2.1.2 Method 2
A more conservative and recommended approach is to choose an inductor that has saturation current rating
greater than the maximum current limit of 3 A.
A 2.2-µH inductor with a saturation current rating of at least 3 A is recommended for most applications.
Resistance of the inductor must be less than 0.3 Ω for a good efficiency. Table 11 lists suggested inductors and
suppliers. For low-cost applications, an unshielded bobbin inductor could be considered. For noise critical
applications, a toroidal or shielded bobbin inductor should be used. A good practice is to lay out the board with
overlapping footprints of both types for design flexibility. This allows substitution of a low-noise shielded inductor,
in the event that noise from low-cost bobbin models is unacceptable.
9.2.2.2.2 Input Capacitor Selection
A ceramic input capacitor of 10 µF, 6.3 V is sufficient for most applications. Place the input capacitor as close as
possible to the VIN pin of the device. A larger value may be used for improved input voltage filtering. Use X7R or
X5R types, do not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting
case sizes like 0805 and 0603. The input filter capacitor supplies current to the PFET switch of the converter in
the first half of each cycle and reduces voltage ripple imposed on the input power source. A ceramic capacitor’s
low ESR provides the best noise filtering of the input voltage spikes due to this rapidly changing current. Select a
capacitor with sufficient ripple current rating. The input current ripple can be calculated as in Equation 3:
where r =
VOUT
VIN
§
* ¨¨1 ©
VOUT
2
+
VIN
r
12
§
¨
¨
©
IRMS = IOUTMAX *
(VIN - VOUT) * VOUT
L * f * IOUTMAX * VIN
(3)
The worst case is when VIN = 2 × VOUT.
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Table 11. Suggested Inductors And Their Suppliers
MODEL
VENDOR
FDSE0312-2R2M
Toko
DO1608C-222
Coilcraft
52
DIMENSIONS L × W × H (mm)
DCR (typical)
3 × 3 × 1.2
160 mΩ
6.6 × 4.5 × 1.8
80 mΩ
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9.2.2.2.3 Output Capacitor Selection
Use a 10-µF, 6.3-V ceramic capacitor. Use X7R or X5R types, do not use Y5V. DC bias characteristics of
ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. DC bias characteristics
vary from manufacturer to manufacturer, and DC bias curves should be requested as part of the capacitor
selection process. The output filter capacitor smooths out current flow from the inductor to the load, helps
maintain a steady output voltage during transient load changes and reduces output voltage ripple. These
capacitors must be selected with sufficient capacitance and sufficiently low ESR to perform these functions.
The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its
ESR and can be calculated as:
IRIPPLE
VPP-C =
4 * f *C
(4)
Voltage peak-to-peak ripple due to ESR can be expressed as in Equation 5:
VPP-ESR = (2 × IRIPPLE) × RESR
(5)
Because these two components are out of phase the RMS value can be used to get an approximate value of
peak-to-peak ripple.
Voltage peak-to-peak ripple, root mean squared can be expressed as follows:
VPP-RMS =
VPP-C2 + VPP-ESR2
(6)
Output voltage ripple is dependent on the inductor current ripple and the equivalent series resistance of the
output capacitor (RESR).
The RESR is frequency dependent (as well as temperature dependent); make sure the value used for calculations
is at the switching frequency of the part.
Table 12. Suggested Capacitor and Their Suppliers
VENDOR
VOLTAGE
CASE SIZE INCH (mm)
GRM21BR60J106K
MODEL
Ceramic, X5R
TYPE
Murata
6.3 V
0805 (2012)
JMK212BJ106K
Ceramic, X5R
Taiyo-Yuden
6.3 V
0805 (2012)
C2012X5R0J106K
Ceramic, X5R
TDK
6.3 V
0805 (2012)
9.2.2.2.4 Buck Output Ripple Management
If VIN and ILOAD increase, the output ripple associated with the buck regulators also increases. Figure 29 shows
the safe operating area. To ensure operation in the area of concern, TI recommends that the system designer
circumvents the output ripple issues to install Schottky diodes on the buck(s) that are expected to perform under
these extreme corner conditions. Schottky diodes are recommended to reduce the output ripple, if system
requirements include this shaded area of operation. VIN > 1.5 V and ILOAD > 1.24 A.
5.5
VIN (V)
5.0
4.5
4.0
3.5
3.0
0
0.5
1.0
1.5
LOAD CURRENT (A)
Figure 29. Application Conditions for Schottky Diodes
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9.2.3 Application Curves
4.03 Ps
VIN = 3 V to 3.6 V
VOUT = 1.2 V
4.03 Ps
250-mA Load
VIN = 3.6 V
Figure 30. Line Transient Response
VOUT = 3.3 V
0 – 100 mA Load
Figure 31. Load Transient
10 Power Supply Recommendations
The LP3972 is designed to operate from a single-cell lithium-ion battery and a coin-cell backup battery. VIN input
must be between 2.7 V and 5.5 V. The RTC LDO input automatically switches between main and backup
batteries at VIN > 3 V, and device operational range is VIN between 3.3 V and 5.5 V. Decoupling capacitance at
VIN pin can be shared for all LDO and Buck inputs. It must be placed as close to device as possible.
54
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11 Layout
11.1 Layout Guidelines
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance
of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss
in the traces. These can send erroneous signals to the DC-DC converter device, resulting in poor regulation or
instability.
Good layout for the converters can be implemented by following a few simple design rules.
1. Place the converters, inductor and filter capacitors close together and make the traces short. The traces
between these components carry relatively high switching currents and act as antennas. Following this rule
reduces radiated noise. Special care must be given to place the input filter capacitor very close to the VIN
and GND pin.
2. Arrange the components so that the switching current loops curl in the same direction. During the first half of
each cycle, current flows from the input filter capacitor through the converter and inductor to the output filter
capacitor and back through ground, forming a current loop. In the second half of each cycle, current is pulled
up from ground through the converter by the inductor to the output filter capacitor and then back through
ground forming a second current loop. Routing these loops so the current curls in the same direction
prevents magnetic field reversal between the two half-cycles and reduces radiated noise.
3. Connect the ground pins of the converter and filter capacitors together using generous component-side
copper fill as a pseudo-ground plane. Then, connect this to the ground-plane (if one is used) with several
vias. This reduces ground-plane noise by preventing the switching currents from circulating through the
ground plane. It also reduces ground bounce at the converter by giving it a low-impedance ground
connection.
4. Use wide traces between the power components and for power connections to the DC-DC converter circuit.
This reduces voltage errors caused by resistive losses across the traces.
5. Route noise sensitive traces, such as the voltage feedback path, away from noisy traces between the power
components. The voltage feedback trace must remain close to the converter circuit and must be direct but
must be routed opposite to noisy components. This reduces EMI radiated onto the DC-DC converter’s own
voltage feedback trace. A good approach is to route the feedback trace on another layer and to have a
ground plane between the top layer and layer on which the feedback trace is routed. In the same manner for
the adjustable part it is desired to have the feedback dividers on the bottom layer.
6. Place noise sensitive circuitry, such as radio RF blocks, away from the DC-DC converter, CMOS digital
blocks and other noisy circuitry. Interference with noise-sensitive circuitry in the system can be reduced
through distance.
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11.2 Layout Example
VINBUCK1
SW1
PGND1
PWR_EN
SYS_EN
SYNC
BGND1,2,3
PGND3
SW3
VINBUCK3
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
SCL
10
21
GND1
FB2
9
nRSTI
nRSTO
8
VOUTLDO2
VOUTLDO5
7
VOUTLDO1
VINLDO5
6
VIN
VDDA
5
FB1
FB3
4
EXT_WAKEUP
GPIO1/nCHG_EN
3
SPARE
GPIO2
2
nTEST_JIG
1
PWR_ON
SDA
15
16
17
18
19
VINLDO4
VINBUBATT
VOUTLDO_RTC
nBATT_FLT
PGND2
SW2
VINBUCK2
14
VOUTLDO4
20
13
VOUTLDO3
VREF
12
11
KEY
Ground Plane Cut
Ground Plane Via
Power Plane Via
Figure 32. LP3972 Layout
56
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Related Documentation
For additional information, see the following:
TI Application Note Leadless Leadframe Package (LLP) (SNOA401)
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LP3972SQ-0514/NOPB
NRND
WQFN
RSB
40
1000
RoHS & Green
SN
Level-1-260C-UNLIM
LP3972SQ-5810/NOPB
NRND
WQFN
RSB
40
1000
RoHS & Green
SN
Level-1-260C-UNLIM
72-0514
LP3972SQ-A413/NOPB
NRND
WQFN
RSB
40
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
72-A413
LP3972SQ-A514/NOPB
NRND
WQFN
RSB
40
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
72-A514
LP3972SQ-E514/NOPB
NRND
WQFN
RSB
40
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
72-E514
LP3972SQ-I414/NOPB
NRND
WQFN
RSB
40
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
72-I414
LP3972SQ-I514/NOPB
NRND
WQFN
RSB
40
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
72-I514
72-5810
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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