LP3985
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SNVS087AC – OCTOBER 2000 – REVISED MAY 2013
LP3985 Micropower, 150mA Low-Noise Ultra Low-Dropout CMOS Voltage Regulator
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FEATURES
DESCRIPTION
•
•
•
The LP3985 is designed for portable and wireless
applications with demanding performance and space
requirements.
1
2
•
•
Miniature 5-I/O DSBGA and USON Package
Logic Controlled Enable
Stable with Ceramic and High Quality
Tantalum Capacitors
Fast Turn-on
Thermal Shutdown and Short-Circuit Current
Limit
The LP3985 is stable with a small 1µF ±30% ceramic
or high-quality tantalum output capacitor. The DSBGA
requires the smallest possible PC board area - the
total application circuit area can be less than 2.0mm x
2.5mm, a fraction of a 1206 case size.
The LP3985's performance is optimized for battery
powered systems to deliver ultra low noise, extremely
low dropout voltage and low quiescent current.
Regulator ground current increases only slightly in
dropout, further prolonging the battery life.
APPLICATIONS
•
•
•
•
CDMA Cellular Handsets
Wideband CDMA Cellular Handsets
GSM Cellular Handsets
Portable Information Appliances
An optional external bypass capacitor reduces the
output noise without slowing down the load transient
response. Fast startup time is achieved by utilizing an
internal power-on circuit that actively pre-charges the
bypass capacitor.
KEY SPECIFICATIONS
•
•
•
•
•
•
•
•
•
2.5 to 6.0V Input Range
150mA Verified Output
50dB PSRR at 1kHz @ VIN = VOUT + 0.2V
≤1.5μA Quiescent Current when Shut Down
Fast Turn-On time: 200μs (typ.)
100mV Maximum Dropout with 150mA Load
30μVrms Output Noise (typ.) Over 10Hz to
100kHz
−40 to +125°C Junction Temperature Range for
Operation
2.5V, 2.6V, 2.7V, 2.8V, 2.85V, 2.9V, 3.0V, 3.1V,
3.2V, 3.3V, 4.7V, 4.75V, 4.8V and 5.0V outputs
standard
Power supply rejection is better than 50dB at low
frequencies and starts to roll off at 1kHz. High power
supply rejection is maintained down to low input
voltage levels common to battery operated circuits.
The device is ideal for mobile phone and similar
battery powered wireless applications. It provides up
to 150mA, from a 2.5V to 6V input. The LP3985
consumes less than 1.5µA in disable mode and has
fast turn-on time less than 200µs.
Typical Application Circuit
1(C3)
5(C1)
VIN
VOUT
1PF
1PF
LP3985
3(A1)
VEN
4(A3)
BYPASS
2(B2)
*
Pin Numbers in parenthesis indicate DSBGA package.
* Optional Noise Reduction Capacitor.
Figure 1.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2013, Texas Instruments Incorporated
LP3985
SNVS087AC – OCTOBER 2000 – REVISED MAY 2013
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DESCRIPTION (CONTINUED)
The LP3985 is available in a 5-bump thin DSBGA and a 5-pin USON package. Performance is specified for
−40°C to +125°C temperature range and is available in 2.5V, 2.6V, 2.7V, 2.8V, 2.85V, 2.9V, 3.0V. 3.1V, 3.2V,
3.3V, 4.7V, 4.75V, 4.8V and 5.0V output voltages. For other output voltage options between 2.5V to 5.0V or for a
dual LP3985, please contact a Texas Instruments sales office.
Block Diagram
VIN
VOUT
VEN
ON
t 1.40V
Vreference
1.23V
OFF
d 0.4V
Fast Turn
On Circuit
R1
Bypass
R2
Over Current &
Thermal Protection
GND
Figure 2.
PIN DESCRIPTIONS
Name
* DSBGA
USON
VEN
A1
3
Enable Input Logic, Enable High
Function
GND
B2
2
Common Ground
VOUT
C1
5
Output Voltage of the LDO
VIN
C3
1
Input Voltage of the LDO
BYPASS
A3
4
Optional Bypass Capacitor for Noise Reduction
Connection Diagram
Figure 3. Top View USON 5-Pin Package
Package Number MF05A
Figure 4. Top View 5-Bump DSBGA Package
Package Number TLA05
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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ORDERING INFORMATION (1) (2)
Orderable
Voltage Option (V)
SOT23-5 package
LP3985IM5-2.5/NOPB
2.5
LP3985IM5X-2.5/NOPB
LP3985IM5-2.6/NOPB
2.6
LP3985IM5X-2.6/NOPB
LP3985IM5-2.7/NOPB
2.7
LP3985IM5X-2.7/NOPB
LP3985IM5-2.8/NOPB
2.8
LP3985IM5X-2.8/NOPB
LP3985IM5-2.85/NOPB
2.85
LP3985IM5X-2.85/NOPB
LP3985IM5-2.9/NOPB
2.9
LP3985IM5X-2.9/NOPB
LP3985IM5-3.0/NOPB
3
LP3985IM5X-3.0/NOPB
LP3985IM5-3.1/NOPB
3.1
LP3985IM5X-3.1/NOPB
LP3985IM5-3.2/NOPB
3.2
LP3985IM5X-3.2/NOPB
LP3985IM5-3.3/NOPB
3.3
LP3985IM5X-3.3/NOPB
LP3985IM5-4.7/NOPB
4.7
LP3985IM5X-4.7/NOPB
LP3985IM5-5.0/NOPB
5.0
LP3985IM5X-5.0/NOPB
(1)
(2)
For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
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ORDERING INFORMATION(1)(2) (continued)
Orderable
Voltage Option (V)
DSBGA package
LP3985ITL-2.5/NOPB
2.5
LP3985ITLX-2.5/NOPB
LP3985ITL-2.6/NOPB
2.6
LP3985ITLX-2.6/NOPB
LP3985ITL-2.7/NOPB
2.7
LP3985ITLX-2.7/NOPB
LP3985ITL-2.8/NOPB
2.8
LP3985ITLX-2.8/NOPB
LP3985ITL-2.85/NOPB
2.85
LP3985ITLX-2.85/NOPB
LP3985ITL-2.9/NOPB
2.9
LP3985ITLX-2.9/NOPB
LP3985ITL-3.0/NOPB
3
LP3985ITLX-3.0/NOPB
LP3985ITL-3.1/NOPB
3.1
LP3985ITLX-3.1/NOPB
LP3985ITL-3.2/NOPB
3.2
LP3985ITLX-3.2/NOPB
LP3985ITL-3.3/NOPB
3.3
LP3985ITLX-3.3/NOPB
LP3985ITL-4.75/NOPB
4.75
LP3985ITLX-4.75/NOPB
LP3985ITL-4.8/NOPB
4.8
LP3985ITLX-4.8/NOPB
LP3985ITL-5.0/NOPB
5.0
LP3985ITLX-5.0/NOPB
4
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SNVS087AC – OCTOBER 2000 – REVISED MAY 2013
Absolute Maximum Ratings (1) (2) (3)
−0.3 to 6.5V
VIN, VEN
−0.3 to (VIN+0.3) ≤ 6.5V
VOUT
Junction Temperature
150°C
Storage Temperature
−65°C to +150°C
Lead Temp.
235°C
Pad Temp. (4)
235°C
Maximum Power Dissipation
SOT23-5 (5)
DSBGA (5)
364mW
314mW
ESD Rating (6)
Human Body Model
Machine Model
(1)
(2)
(3)
(4)
(5)
(6)
2kV
150V
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is verified. Operating Ratings do not imply verified performance limits. For verified performance limits and
associated test conditions, see the Electrical Characteristics tables.
All voltages are with respect to the potential at the GND pin.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Additional information on lead temperature and pad temperature can be found in Texas Instruments Application Note AN1112(SNOA401).
The Absolute Maximum power dissipation depends on the ambient temperature and can be calculated using the formula: PD = (TJ TA)/θJA,where TJ is the junction temperature, TA is the ambient temperature, and θ JA is the junction-to-ambient thermal resistance. The
364mW rating for SOT23-5 appearing under Absolute Maximum Ratings results from substituting the Absolute Maximum junction
temperature, 150°C, for TJ, 70°C for TA, and 220°C/W for θJA. More power can be dissipated safely at ambient temperatures below
70°C . Less power can be dissipated safely at ambient temperatures above 70°C. The Absolute Maximum power dissipation can be
increased by 4.5mW for each degree below 70°C, and it must be derated by 4.5mW for each degree above 70°C.
The human body model is 100pF discharged through 1.5kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged
directly into each pin.
Operating Ratings (1) (2)
VIN
2.5 to 6V
VEN
0 to (VIN+0.3) ≤ 6V
−40°C to +125°C
Junction Temperature
Thermal Resistance
θJA (SOT23-5)
θJA (DSBGA)
220°C/W
255°C/W
Maximum Power Dissipation
SOT23-5 (3)
DSBGA (3)
(1)
(2)
(3)
250mW
216mW
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is verified. Operating Ratings do not imply verified performance limits. For verified performance limits and
associated test conditions, see the Electrical Characteristics tables.
All voltages are with respect to the potential at the GND pin.
Like the Absolute Maximum power dissipation, the maximum power dissipation for operation depends on the ambient temperature. The
250mW rating for SOT23-5 appearing under Operating Ratings results from substituting the maximum junction temperature for
operation, 125°C, for TJ, 70°C for TA, and 220°C/W for θJA into PD = (TJ - TA)/θJA from above. More power can be dissipated at ambient
temperatures below 70°C . Less power can be dissipated at ambient temperatures above 70°C. The maximum power dissipation for
operation can be increased by 4.5mW for each degree below 70°C, and it must be derated by 4.5mW for each degree above 70°C.
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Electrical Characteristics
Unless otherwise specified: VIN = VOUT(nom) + 0.5V, CIN = 1 µF, IOUT = 1mA, COUT = 1 µF, CBYPASS = 0.01µF. Typical values and
limits appearing in standard typeface are for TJ = 25°C. Limits appearing in boldface type apply over the entire junction
temperature range for operation, −40°C to +125°C. (1) (2)
Symbol
Parameter
Conditions
Output Voltage
Tolerance
IOUT = 1mA
Line Regulation Error
VIN = (VOUT(nom) + 0.5V) to 6.0V,
For 4.7 to 5.0 options
For all other options
ΔVOUT
Load Regulation Error (3)
Output AC Line Regulation
PSRR
Power Supply Rejection Ratio
IQ
Quiescent Current
Dropout Voltage
(4)
Typ
Units
Max
−2
−3
2
3
% of
VOUT(nom)
−0.19
−0.1
0.19
0.1
%/V
IOUT = 1 mA to 150 mA
LP3985IM5 (SOT23-5)
0.0025
0.005
LP3985 (DSBGA)
0.0004
0.002
%/mA
VIN = VOUT(nom) + 1V,
IOUT = 150 mA (Figure 5)
1.5
VIN = VOUT(nom) + 0.2V,
f = 1 kHz,
IOUT = 50 mA (Figure 6)
50
VIN = VOUT(nom) + 0.2V,
f = 10 kHz,
IOUT = 50 mA (Figure 6)
40
mVP-P
dB
VEN = 1.4V, IOUT = 0 mA
For 4.7 to 5.0 options
For all other options
100
85
165
150
VEN = 1.4V, IOUT = 0 to 150 mA
For 4.7 to 5.0 options
For all other options
155
140
250
200
VEN = 0.4V
0.003
1.5
IOUT = 1 mA
0.4
2
IOUT = 50 mA
20
35
IOUT = 100 mA
45
70
IOUT = 150 mA
60
100
µA
ISC
Short Circuit Current Limit
Output Grounded
(Steady State)
600
IOUT(PK)
Peak Output Current
VOUT ≥ VOUT(nom) - 5%
550
(5)
Limit
Min
mV
mA
300
mA
TON
Turn-On Time
CBYPASS = 0.01 µF
200
µs
en
Output Noise Voltage (6)
BW = 10 Hz to 100 kHz,
COUT = 1µF
30
µVrms
Output Noise Density
CBP = 0
230
nV/ √Hz
IEN
Maximum Input Current at EN
VEN = 0.4 and VIN = 6.0
±1
VIL
Maximum Low Level Input Voltage VIN = 2.5 to 6.0V
at EN
VIH
Minimum High Level Input Voltage VIN = 2.5 to 6.0V
at EN
TSD
(1)
(2)
(3)
(4)
(5)
(6)
6
nA
0.4
1.4
V
V
Thermal Shutdown Temperature
160
°C
Thermal Shutdown Hysteresis
20
°C
All limits are verified. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C or
correlated using Statistical Quality Control (SQC) methods. All hot and cold limits are specified by correlating the electrical
characteristics to process and temperature variations and applying statistical process control.
The target output voltage, which is labeled VOUT(nom), is the desired voltage option.
An increase in the load current results in a slight decrease in the output voltage and vice versa.
Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value. This specification
does not apply for input voltages below 2.5V.
Turn-on time is time measured between the enable input just exceeding VIH and the output voltage just reaching 95% of its nominal
value.
The output noise varies with output voltage option. The 30µVrms is measured with 2.5V voltage option. To calculate an approximated
output noise for other options, use the equation: (30µVrms)(X)/2.5, where X is the voltage option value.
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Recommended Output Capacitor
Symbol
COUT
Parameter
Conditions
Capacitance (1)
Output Capacitor
Min
1.0
0.7
ESR
(1)
Limit
Nominal
Value
5
Max
Units
µF
500
mΩ
The minimum value of capacitance for stability and correct operation is 0.7µF. The Capacitor tolerance should be ± 30% or better over
the temperature range. The full range of operating conditions for the capacitor in the application should be considered during device
selection to ensure this minimum capacitance specification is met. The recommended capacitor type is X7R to meet the full device
temperature spec of -40ºC to 125ºC. See the capacitor section in Application Hints.
Timing Diagrams
Figure 5. Line Transient Input Test Signal
Figure 6. PSRR Input Test Signal
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Typical Performance Characteristics
Unless otherwise specified, CIN = COUT = 1 µF Ceramic, CBYPASS = 0.01 µF, VIN = VOUT + 0.2V, TA = 25°C, Enable pin is tied to
VIN.
Output Voltage Change vs Temperature
Dropout Voltage vs Load Current
VIN = VOUT + 0.5V
VOUT CHANGE (%)
0.4
0
-0.4
-0.8
-50
-25
0
25
50
75
100
125
TEMPERATURE (°C)
8
Figure 7.
Figure 8.
Ground Current vs Load Current
Ground Current vs VIN @ 25°C
Figure 9.
Figure 10.
Ground Current vs VIN @ −40°C
Ground Current vs VIN @ 125°C
Figure 11.
Figure 12.
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Typical Performance Characteristics (continued)
Unless otherwise specified, CIN = COUT = 1 µF Ceramic, CBYPASS = 0.01 µF, VIN = VOUT + 0.2V, TA = 25°C, Enable pin is tied to
VIN.
Short Circuit Current (DSBGA)
Short Circuit Current (DSBGA)
Figure 13.
Figure 14.
Short Circuit Current (SOT)
Short Circuit Current (SOT)
Figure 15.
Figure 16.
Short Circuit Current (SOT)
Short Circuit Current (SOT)
Figure 17.
Figure 18.
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Typical Performance Characteristics (continued)
Unless otherwise specified, CIN = COUT = 1 µF Ceramic, CBYPASS = 0.01 µF, VIN = VOUT + 0.2V, TA = 25°C, Enable pin is tied to
VIN.
10
Short Circuit Current (DSBGA)
Short Circuit Current (DSBGA)
Figure 19.
Figure 20.
Output Noise Spectral Density
Ripple Rejection (VIN = VOUT + 0.2V)
Figure 21.
Figure 22.
Ripple Rejection (VIN = VOUT + 1V)
Ripple Rejection (VIN = 5.0V)
Figure 23.
Figure 24.
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Typical Performance Characteristics (continued)
Unless otherwise specified, CIN = COUT = 1 µF Ceramic, CBYPASS = 0.01 µF, VIN = VOUT + 0.2V, TA = 25°C, Enable pin is tied to
VIN.
Startup Time (VIN = VOUT + 0.2V)
Startup Time (VIN = 4.2V)
Figure 25.
Figure 26.
Startup Time (VIN = VOUT + 0.2V)
Startup Time (VIN = 4.2V)
Figure 27.
Figure 28.
Startup Time (VIN = VOUT + 0.2V)
Startup Time (VIN = 4.2V)
Figure 29.
Figure 30.
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Typical Performance Characteristics (continued)
Unless otherwise specified, CIN = COUT = 1 µF Ceramic, CBYPASS = 0.01 µF, VIN = VOUT + 0.2V, TA = 25°C, Enable pin is tied to
VIN.
12
Line Transient Response
Line Transient Response
Figure 31.
Figure 32.
Load Transient Response (VIN = 3.2V)
Load Transient Response (VIN = 4.2V)
Figure 33.
Figure 34.
Load Transient Response (VIN = 3.2V)
Load Transient Response (VIN = 4.2V)
Figure 35.
Figure 36.
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Typical Performance Characteristics (continued)
Unless otherwise specified, CIN = COUT = 1 µF Ceramic, CBYPASS = 0.01 µF, VIN = VOUT + 0.2V, TA = 25°C, Enable pin is tied to
VIN.
Enable Response (VIN = VOUT + 0.2V)
Enable Response (VIN = 4.2V)
Figure 37.
Figure 38.
Enable Response (VIN = VOUT + 0.2V)
Enable Response (VIN = 4.2V)
Figure 39.
Figure 40.
Output Impedance (VIN = 4.2V)
Output Impedance (VIN = VOUT + 0.2V)
Figure 41.
Figure 42.
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APPLICATION HINTS
EXTERNAL CAPACITORS
Like any low-dropout regulator, the LP3985 requires external capacitors for regulator stability. The LP3985 is
specifically designed for portable applications requiring minimum board space and smallest components. These
capacitors must be correctly selected for good performance.
INPUT CAPACITOR
An input capacitance of ≊ 1µF is required between the LP3985 input pin and ground (the amount of the
capacitance may be increased without limit).
This capacitor must be located a distance of not more than 1cm from the input pin and returned to a clean
analog ground. A ceramic capacitor is recommended although a good quality tantalum or film capacitor may be
used at the input.
Important: Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a lowimpedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input,
it must be verified by the manufacturer to have a surge current rating sufficient for the application.
There are no requirements for the ESR on the input capacitor, but tolerance and temperature coefficient must be
considered when selecting the capacitor to ensure the capacitance will remain within the operational range over
the full range of temperature and operating conditions.
OUTPUT CAPACITOR
Correct selection of the output capacitor is important to ensure stable operation in the intended application.
The output capacitor must meet all the requirements specified in the recommended capacitor table over all
conditions in the application. These conditions include DC-bias, frequency and temperature. Unstable operation
will result if the capacitance drops below the minimum specified value. (See the next section Capacitor
Characteristics).
The LP3985 is designed specifically to work with very small ceramic output capacitors. A 1.0µF ceramic
capacitor (dialectric type X7R) with ESR between 5mΩ to 500mΩ is suitable in the LP3985 application circuit.
X5R capacitors may be used but have a narrower temperature range. With these and other capacitor types (Y5V,
Z6U) that may be used, selection is dependant on the range of operating conditions and temperature range for
that application. (see section on Capacitor Characteristics).
It may also be possible to use tantalum or film capacitors at the output, but these are not as attractive for
reasons of size and cost (see next section Capacitor Characteristics).
It is also recommended that the output capacitor be placed within 1cm from the output pin and returned to a
clean ground line.
CAPACITOR CHARACTERISTICS
The LP3985 is designed to work with ceramic capacitors on the output to take advantage of the benefits they
offer: for capacitance values in the range of 1µF to 4.7µF range, ceramic capacitors are the smallest, least
expensive and have the lowest ESR values (which makes them best for eliminating high frequency noise). The
ESR of a typical 1µF ceramic capacitor is in the range of 20mΩ to 40mΩ, which easily meets the ESR
requirement for stability by the LP3985.
For both input and output capacitors careful interpretation of the capacitor specification is required to ensure
correct device operation. The capacitor value can change greatly dependant on the conditions of operation and
capacitor type.
In particular the output capacitor selection should take account of all the capacitor parameters to ensure that the
specification is met within the application. Capacitance value can vary with DC bias conditions as well as
temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging.
The capacitor parameters are also dependant on the particular case size with smaller sizes giving poorer
performance figures in general. As an example Figure 43 shows a typical graph showing a comparison of
capacitor case sizes in a Capacitance vs. DC Bias plot. As shown in the graph, as a result of the DC Bias
14
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CAP VALUE (% OF NOM. 1 PF)
condition the capacitance value may drop below the minimum capacitance value given in the recommended
capacitor table (0.7µF in this case). Note that the graph shows the capacitance out of spec for the 0402 case
size capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers'
specifications for the nominal value capacitor are consulted for all conditions as some capacitor sizes (e.g. 0402)
may not be suitable in the actual application.
0603, 10V, X5R
100%
80%
60%
0402, 6.3V, X5R
40%_
20%
_
0
1.0
2.0
_
3.0
_
4.0
_
5.0
_
DC BIAS (V)
Figure 43. Graph Showing A Typical Variation in Capacitance vs DC Bias
The ceramic capacitor's capacitance can vary with temperature. The capacitor type X7R, which operates over a
temperature range of −55°C to +125°C, will only vary the capacitance to within ±15%. The capacitor type X5R
has a similar tolerance over a reduced temperature range of −55°C to +85°C. Most large value ceramic
capacitors (≊ 2.2µF) are manufactured with Z5U or Y5V temperature characteristics. Their capacitance can drop
by more than 50% as the temperature goes from 25°C to 85°C. Therefore X7R is recommended over Z5U and
Y5V in applications where the ambient temperature will change significantly above or below 25°C.
Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more
expensive when comparing equivalent capacitance and voltage ratings in the 1µF to 4.7µF range.
Another important consideration is that tantalum capacitors have higher ESR values than equivalent size
ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the
stable range, it would have to be larger in capacitance (which means bigger and more costly ) than a ceramic
capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about
2:1 as the temperature goes from 25°C down to −40°C, so some guard band must be allowed.
NOISE BYPASS CAPACITOR
Connecting a 0.01µF capacitor between the CBYPASS pin and ground significantly reduces noise on the regulator
output. This cap is connected directly to a high impedance node in the band gap reference circuit. Any significant
loading on this node will cause a change on the regulated output voltage. For this reason, DC leakage current
through this pin must be kept as low as possible for best output voltage accuracy.
The types of capacitors best suited for the noise bypass capacitor are ceramic and film. High-quality ceramic
capacitors with either NPO or COG dielectric typically have very low leakage. Polypropolene and polycarbonate
film capacitors are available in small surface-mount packages and typically have extremely low leakage current.
Unlike many other LDO's, addition of a noise reduction capacitor does not effect the load transient response of
the device.
NO-LOAD STABILITY
The LP3985 will remain stable and in regulation with no external load. This is specially important in CMOS RAM
keep-alive applications.
Submit Documentation Feedback
Copyright © 2000–2013, Texas Instruments Incorporated
Product Folder Links: LP3985
15
LP3985
SNVS087AC – OCTOBER 2000 – REVISED MAY 2013
www.ti.com
ON/OFF INPUT OPERATION
The LP3985 is turned off by pulling the VEN pin low, and turned on by pulling it high. If this feature is not used,
the VEN pin should be tied to VIN to keep the regulator output on at all time. To assure proper operation, the
signal source used to drive the VEN input must be able to swing above and below the specified turn-on/off voltage
thresholds listed in the Electrical Characteristics section under VIL and VIH.
FAST ON-TIME
The LP3985 output is turned on after Vref voltage reaches its final value (1.23V nominal). To speed up this
process, the noise reduction capacitor at the bypass pin is charged with an internal 70µA current source. The
current source is turned off when the bandgap voltage reaches approximately 95% of its final value. The turn on
time is determined by the time constant of the bypass capacitor. The smaller the capacitor value, the shorter the
turn on time, but less noise gets reduced. As a result, turn on time and noise reduction need to be taken into
design consideration when choosing the value of the bypass capacitor.
DSBGA MOUNTING
The DSBGA package requires specific mounting techniques which are detailed in Texas Instruments Application
Note AN-1112(SNOA401). Referring to the section Surface Mount Technology (SMT) Assembly Considerations,
it should be noted that the pad style which must be used with the 5-bump package is NSMD (non-solder mask
defined) type.
For best results during assembly, alignment ordinals on the PC board may be used to facilitate placement of the
DSBGA device.
DSBGA LIGHT SENSITIVITY
Exposing the DSBGA device to direct sunlight will cause mis-operation of the device. Light sources such as
halogen lamps can effect electrical performance if brought near to the device.
The wavelengths which have most detrimental effect are reds and infra-reds, which means that the fluorescent
lighting used inside most buildings has very little effect on performance. A DSBGA test board was brought to
within 1cm of a fluorescent desk lamp and the effect on the regulated output voltage was negligible, showing a
deviation of less than 0.1% from nominal.
16
Submit Documentation Feedback
Copyright © 2000–2013, Texas Instruments Incorporated
Product Folder Links: LP3985
LP3985
www.ti.com
SNVS087AC – OCTOBER 2000 – REVISED MAY 2013
REVISION HISTORY
Changes from Revision AB (May 2013) to Revision AC
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 16
Submit Documentation Feedback
Copyright © 2000–2013, Texas Instruments Incorporated
Product Folder Links: LP3985
17
PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LP3985IM5-2.5
NRND
SOT-23
DBV
5
1000
TBD
Call TI
Call TI
-40 to 125
LCSB
LP3985IM5-2.5/NOPB
ACTIVE
SOT-23
DBV
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LCSB
LP3985IM5-2.7/NOPB
ACTIVE
SOT-23
DBV
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LCUB
LP3985IM5-2.8
NRND
SOT-23
DBV
5
1000
TBD
Call TI
Call TI
-40 to 125
LCJB
LP3985IM5-2.8/NOPB
ACTIVE
SOT-23
DBV
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LCJB
LP3985IM5-2.9/NOPB
ACTIVE
SOT-23
DBV
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LCYB
LP3985IM5-3.0
NRND
SOT-23
DBV
5
1000
TBD
Call TI
Call TI
-40 to 125
LCRB
LP3985IM5-3.0/NOPB
ACTIVE
SOT-23
DBV
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LCRB
LP3985IM5-3.2/NOPB
ACTIVE
SOT-23
DBV
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LDPB
LP3985IM5-3.3
NRND
SOT-23
DBV
5
1000
TBD
Call TI
Call TI
-40 to 125
LDQB
LP3985IM5-3.3/NOPB
ACTIVE
SOT-23
DBV
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LDQB
LP3985IM5-4.7
NRND
SOT-23
DBV
5
1000
TBD
Call TI
Call TI
-40 to 125
LDRB
LP3985IM5-4.7/NOPB
ACTIVE
SOT-23
DBV
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LDRB
LP3985IM5-5.0
NRND
SOT-23
DBV
5
1000
TBD
Call TI
Call TI
-40 to 125
LDSB
LP3985IM5-5.0/NOPB
ACTIVE
SOT-23
DBV
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LDSB
LP3985IM5X-2.5/NOPB
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LCSB
LP3985IM5X-2.8/NOPB
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LCJB
LP3985IM5X-285/NOPB
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LCXB
LP3985IM5X-3.0
NRND
SOT-23
DBV
5
3000
TBD
Call TI
Call TI
-40 to 125
LCRB
LP3985IM5X-3.0/NOPB
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LCRB
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
1-Nov-2013
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LP3985IM5X-3.3
NRND
SOT-23
DBV
5
3000
TBD
Call TI
Call TI
-40 to 125
LDQB
LP3985IM5X-3.3/NOPB
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LDQB
LP3985IM5X-4.7/NOPB
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LDRB
LP3985IM5X-5.0/NOPB
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LDSB
LP3985ITL-2.5/NOPB
ACTIVE
DSBGA
YZR
5
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
5
LP3985ITL-2.6/NOPB
ACTIVE
DSBGA
YZR
5
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
5
LP3985ITL-2.7/NOPB
ACTIVE
DSBGA
YZR
5
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
5
LP3985ITL-2.8/NOPB
ACTIVE
DSBGA
YZR
5
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
5
LP3985ITL-2.9/NOPB
ACTIVE
DSBGA
YZR
5
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
5
LP3985ITL-285/NOPB
ACTIVE
DSBGA
YZR
5
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
5
LP3985ITL-3.0/NOPB
ACTIVE
DSBGA
YZR
5
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
5
LP3985ITL-3.1/NOPB
ACTIVE
DSBGA
YZR
5
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
5
LP3985ITL-3.2/NOPB
ACTIVE
DSBGA
YZR
5
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
5
LP3985ITL-3.3/NOPB
ACTIVE
DSBGA
YZR
5
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
5
LP3985ITL-4.75/NOPB
ACTIVE
DSBGA
YZR
5
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
5
LP3985ITL-4.8/NOPB
ACTIVE
DSBGA
YZR
5
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
LP3985ITL-5.0/NOPB
ACTIVE
DSBGA
YZR
5
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
5
LP3985ITLX-2.5/NOPB
ACTIVE
DSBGA
YZR
5
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
5
Addendum-Page 2
5
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
1-Nov-2013
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LP3985ITLX-2.6/NOPB
ACTIVE
DSBGA
YZR
5
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
5
LP3985ITLX-2.7/NOPB
ACTIVE
DSBGA
YZR
5
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
5
LP3985ITLX-2.8/NOPB
ACTIVE
DSBGA
YZR
5
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
5
LP3985ITLX-2.9/NOPB
ACTIVE
DSBGA
YZR
5
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
5
LP3985ITLX-285/NOPB
ACTIVE
DSBGA
YZR
5
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
5
LP3985ITLX-3.0/NOPB
ACTIVE
DSBGA
YZR
5
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
5
LP3985ITLX-3.1/NOPB
ACTIVE
DSBGA
YZR
5
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
5
LP3985ITLX-3.2/NOPB
ACTIVE
DSBGA
YZR
5
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
5
LP3985ITLX-3.3/NOPB
ACTIVE
DSBGA
YZR
5
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
5
LP3985ITLX-4.75/NOPB
ACTIVE
DSBGA
YZR
5
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
5
LP3985ITLX-4.8/NOPB
ACTIVE
DSBGA
YZR
5
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
LP3985ITLX-5.0/NOPB
ACTIVE
DSBGA
YZR
5
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
5
-40 to 125
5
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Addendum-Page 3
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
LP3985IM5-2.5
SOT-23
DBV
5
1000
178.0
8.4
LP3985IM5-2.5/NOPB
SOT-23
DBV
5
1000
178.0
LP3985IM5-2.7/NOPB
SOT-23
DBV
5
1000
178.0
LP3985IM5-2.8
SOT-23
DBV
5
1000
LP3985IM5-2.8/NOPB
SOT-23
DBV
5
LP3985IM5-2.9/NOPB
SOT-23
DBV
LP3985IM5-3.0
SOT-23
DBV
LP3985IM5-3.0/NOPB
SOT-23
LP3985IM5-3.2/NOPB
LP3985IM5-3.3
W
Pin1
(mm) Quadrant
3.2
3.2
1.4
4.0
8.0
Q3
8.4
3.2
3.2
1.4
4.0
8.0
Q3
8.4
3.2
3.2
1.4
4.0
8.0
Q3
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
5
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
5
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
DBV
5
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
SOT-23
DBV
5
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
SOT-23
DBV
5
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LP3985IM5-3.3/NOPB
SOT-23
DBV
5
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LP3985IM5-4.7
SOT-23
DBV
5
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LP3985IM5-4.7/NOPB
SOT-23
DBV
5
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LP3985IM5-5.0
SOT-23
DBV
5
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LP3985IM5-5.0/NOPB
SOT-23
DBV
5
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LP3985IM5X-2.5/NOPB
SOT-23
DBV
5
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LP3985IM5X-2.8/NOPB
SOT-23
DBV
5
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LP3985IM5X-285/NOPB
SOT-23
DBV
5
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LP3985IM5X-3.0
SOT-23
DBV
5
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LP3985IM5X-3.0/NOPB
SOT-23
DBV
5
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LP3985IM5X-3.3
SOT-23
DBV
5
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LP3985IM5X-3.3/NOPB
SOT-23
DBV
5
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LP3985IM5X-4.7/NOPB
SOT-23
DBV
5
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LP3985IM5X-5.0/NOPB
SOT-23
DBV
5
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LP3985ITL-2.5/NOPB
DSBGA
YZR
5
250
178.0
8.4
1.09
1.55
0.76
4.0
8.0
Q1
LP3985ITL-2.6/NOPB
DSBGA
YZR
5
250
178.0
8.4
1.09
1.55
0.76
4.0
8.0
Q1
LP3985ITL-2.7/NOPB
DSBGA
YZR
5
250
178.0
8.4
1.09
1.55
0.76
4.0
8.0
Q1
LP3985ITL-2.8/NOPB
DSBGA
YZR
5
250
178.0
8.4
1.09
1.55
0.76
4.0
8.0
Q1
LP3985ITL-2.9/NOPB
DSBGA
YZR
5
250
178.0
8.4
1.09
1.55
0.76
4.0
8.0
Q1
LP3985ITL-285/NOPB
DSBGA
YZR
5
250
178.0
8.4
1.09
1.55
0.76
4.0
8.0
Q1
LP3985ITL-3.0/NOPB
DSBGA
YZR
5
250
178.0
8.4
1.09
1.55
0.76
4.0
8.0
Q1
LP3985ITL-3.1/NOPB
DSBGA
YZR
5
250
178.0
8.4
1.09
1.55
0.76
4.0
8.0
Q1
LP3985ITL-3.2/NOPB
DSBGA
YZR
5
250
178.0
8.4
1.09
1.55
0.76
4.0
8.0
Q1
LP3985ITL-3.3/NOPB
DSBGA
YZR
5
250
178.0
8.4
1.09
1.55
0.76
4.0
8.0
Q1
LP3985ITL-4.75/NOPB
DSBGA
YZR
5
250
178.0
8.4
1.09
1.55
0.76
4.0
8.0
Q1
LP3985ITL-4.8/NOPB
DSBGA
YZR
5
250
178.0
8.4
1.09
1.55
0.76
4.0
8.0
Q1
LP3985ITL-5.0/NOPB
DSBGA
YZR
5
250
178.0
8.4
1.09
1.55
0.76
4.0
8.0
Q1
LP3985ITLX-2.5/NOPB
DSBGA
YZR
5
3000
178.0
8.4
1.09
1.55
0.76
4.0
8.0
Q1
LP3985ITLX-2.6/NOPB
DSBGA
YZR
5
3000
178.0
8.4
1.09
1.55
0.76
4.0
8.0
Q1
LP3985ITLX-2.7/NOPB
DSBGA
YZR
5
3000
178.0
8.4
1.09
1.55
0.76
4.0
8.0
Q1
LP3985ITLX-2.8/NOPB
DSBGA
YZR
5
3000
178.0
8.4
1.09
1.55
0.76
4.0
8.0
Q1
LP3985ITLX-2.9/NOPB
DSBGA
YZR
5
3000
178.0
8.4
1.09
1.55
0.76
4.0
8.0
Q1
LP3985ITLX-285/NOPB
DSBGA
YZR
5
3000
178.0
8.4
1.09
1.55
0.76
4.0
8.0
Q1
LP3985ITLX-3.0/NOPB
DSBGA
YZR
5
3000
178.0
8.4
1.09
1.55
0.76
4.0
8.0
Q1
LP3985ITLX-3.1/NOPB
DSBGA
YZR
5
3000
178.0
8.4
1.09
1.55
0.76
4.0
8.0
Q1
LP3985ITLX-3.2/NOPB
DSBGA
YZR
5
3000
178.0
8.4
1.09
1.55
0.76
4.0
8.0
Q1
LP3985ITLX-3.3/NOPB
DSBGA
YZR
5
3000
178.0
8.4
1.09
1.55
0.76
4.0
8.0
Q1
LP3985ITLX-4.75/NOPB
DSBGA
YZR
5
3000
178.0
8.4
1.09
1.55
0.76
4.0
8.0
Q1
LP3985ITLX-4.8/NOPB
DSBGA
YZR
5
3000
178.0
8.4
1.09
1.55
0.76
4.0
8.0
Q1
LP3985ITLX-5.0/NOPB
DSBGA
YZR
5
3000
178.0
8.4
1.09
1.55
0.76
4.0
8.0
Q1
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LP3985IM5-2.5
SOT-23
DBV
5
1000
210.0
185.0
35.0
LP3985IM5-2.5/NOPB
SOT-23
DBV
5
1000
210.0
185.0
35.0
LP3985IM5-2.7/NOPB
SOT-23
DBV
5
1000
210.0
185.0
35.0
LP3985IM5-2.8
SOT-23
DBV
5
1000
210.0
185.0
35.0
LP3985IM5-2.8/NOPB
SOT-23
DBV
5
1000
210.0
185.0
35.0
LP3985IM5-2.9/NOPB
SOT-23
DBV
5
1000
210.0
185.0
35.0
LP3985IM5-3.0
SOT-23
DBV
5
1000
210.0
185.0
35.0
LP3985IM5-3.0/NOPB
SOT-23
DBV
5
1000
210.0
185.0
35.0
LP3985IM5-3.2/NOPB
SOT-23
DBV
5
1000
210.0
185.0
35.0
LP3985IM5-3.3
SOT-23
DBV
5
1000
210.0
185.0
35.0
LP3985IM5-3.3/NOPB
SOT-23
DBV
5
1000
210.0
185.0
35.0
LP3985IM5-4.7
SOT-23
DBV
5
1000
210.0
185.0
35.0
LP3985IM5-4.7/NOPB
SOT-23
DBV
5
1000
210.0
185.0
35.0
LP3985IM5-5.0
SOT-23
DBV
5
1000
210.0
185.0
35.0
LP3985IM5-5.0/NOPB
SOT-23
DBV
5
1000
210.0
185.0
35.0
LP3985IM5X-2.5/NOPB
SOT-23
DBV
5
3000
210.0
185.0
35.0
LP3985IM5X-2.8/NOPB
SOT-23
DBV
5
3000
210.0
185.0
35.0
LP3985IM5X-285/NOPB
SOT-23
DBV
5
3000
210.0
185.0
35.0
LP3985IM5X-3.0
SOT-23
DBV
5
3000
210.0
185.0
35.0
LP3985IM5X-3.0/NOPB
SOT-23
DBV
5
3000
210.0
185.0
35.0
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LP3985IM5X-3.3
SOT-23
DBV
5
3000
210.0
185.0
35.0
LP3985IM5X-3.3/NOPB
SOT-23
DBV
5
3000
210.0
185.0
35.0
LP3985IM5X-4.7/NOPB
SOT-23
DBV
5
3000
210.0
185.0
35.0
LP3985IM5X-5.0/NOPB
SOT-23
DBV
5
3000
210.0
185.0
35.0
LP3985ITL-2.5/NOPB
DSBGA
YZR
5
250
210.0
185.0
35.0
LP3985ITL-2.6/NOPB
DSBGA
YZR
5
250
210.0
185.0
35.0
LP3985ITL-2.7/NOPB
DSBGA
YZR
5
250
210.0
185.0
35.0
LP3985ITL-2.8/NOPB
DSBGA
YZR
5
250
210.0
185.0
35.0
LP3985ITL-2.9/NOPB
DSBGA
YZR
5
250
210.0
185.0
35.0
LP3985ITL-285/NOPB
DSBGA
YZR
5
250
210.0
185.0
35.0
LP3985ITL-3.0/NOPB
DSBGA
YZR
5
250
210.0
185.0
35.0
LP3985ITL-3.1/NOPB
DSBGA
YZR
5
250
210.0
185.0
35.0
LP3985ITL-3.2/NOPB
DSBGA
YZR
5
250
210.0
185.0
35.0
LP3985ITL-3.3/NOPB
DSBGA
YZR
5
250
210.0
185.0
35.0
LP3985ITL-4.75/NOPB
DSBGA
YZR
5
250
210.0
185.0
35.0
LP3985ITL-4.8/NOPB
DSBGA
YZR
5
250
210.0
185.0
35.0
LP3985ITL-5.0/NOPB
DSBGA
YZR
5
250
210.0
185.0
35.0
LP3985ITLX-2.5/NOPB
DSBGA
YZR
5
3000
210.0
185.0
35.0
LP3985ITLX-2.6/NOPB
DSBGA
YZR
5
3000
210.0
185.0
35.0
LP3985ITLX-2.7/NOPB
DSBGA
YZR
5
3000
210.0
185.0
35.0
LP3985ITLX-2.8/NOPB
DSBGA
YZR
5
3000
210.0
185.0
35.0
LP3985ITLX-2.9/NOPB
DSBGA
YZR
5
3000
210.0
185.0
35.0
LP3985ITLX-285/NOPB
DSBGA
YZR
5
3000
210.0
185.0
35.0
LP3985ITLX-3.0/NOPB
DSBGA
YZR
5
3000
210.0
185.0
35.0
LP3985ITLX-3.1/NOPB
DSBGA
YZR
5
3000
210.0
185.0
35.0
LP3985ITLX-3.2/NOPB
DSBGA
YZR
5
3000
210.0
185.0
35.0
LP3985ITLX-3.3/NOPB
DSBGA
YZR
5
3000
210.0
185.0
35.0
LP3985ITLX-4.75/NOPB
DSBGA
YZR
5
3000
210.0
185.0
35.0
LP3985ITLX-4.8/NOPB
DSBGA
YZR
5
3000
210.0
185.0
35.0
LP3985ITLX-5.0/NOPB
DSBGA
YZR
5
3000
210.0
185.0
35.0
Pack Materials-Page 4
MECHANICAL DATA
YZR0005xxx
D
0.600±0.075
E
TLA05XXX (Rev C)
D: Max = 1.502 mm, Min =1.441 mm
E: Max = 1.045 mm, Min =0.984 mm
4215043/A
NOTES:
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
www.ti.com
12/12
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