LP3985ITLX-3.1/NOPB

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LP3985 SNVS087AE – OCTOBER 2000 – REVISED MAY 2015 LP3985 Micropower, 150-mA Low-Noise Ultra-Low-Dropout CMOS Voltage Regulator 1 Features 3 Description • • • • • • • The LP3985 is designed for portable and wireless applications with demanding performance and space requirements. LP3985 performance is optimized for battery-powered systems to deliver ultra low noise, extremely low dropout voltage, and low quiescent current. Regulator ground current increases only slightly in dropout, further prolonging the battery life. 1 • • • • • • Input Voltage: 2.5 V to 6 V 100-mV Maximum Dropout with 150-mA Load 150-mA Verified Output 50-dB PSRR at 1 kHz at VIN = VOUT + 0.2 V ≤ 1.5-μA Quiescent Current when Shut Down Fast Turn-On time: 200 μs (typ.) 30-μVRMS Output Noise (typical) over 10 Hz to 100 kHz −40°C to 125°C Junction Temperature Range for Operation 2.5-V, 2.6-V, 2.7-V, 2.8-V, 2.85-V, 2.9-V, 3-V, 3.1V, 3.2-V, 3.3-V, 4.7-V, 4.75-V, 4.8-V and 5-V Outputs Standard Logic Controlled Enable Stable with Ceramic and High-Quality Tantalum Capacitors Fast Turnon Thermal Shutdown and Short-Circuit Current Limit An optional external bypass capacitor reduces the output noise without slowing down the load transient response. Fast startup time is achieved by utilizing an internal power-on circuit that actively pre-charges the bypass capacitor. Power supply rejection is better than 50 dB at low frequencies and starts to roll off at 1 kHz. High power supply rejection is maintained down to low input voltage levels common to battery operated circuits. The device is ideal for mobile phone and similar battery-powered wireless applications. It provides up to 150 mA, from a 2.5-V to 6-V input. The LP3985 consumes less than 1.5 µA in disable mode and has fast turn-on time less than 200 µs. 2 Applications • • • • The LP3985 is stable with a small 1-µF ±30% ceramic or high-quality tantalum output capacitor. The DSBGA requires the smallest possible PC board area - the total application circuit area can be less than 2 mm x 2.5 mm, a fraction of a 1206 case size. CDMA Cellular Handsets Wideband CDMA Cellular Handsets GSM Cellular Handsets Portable Information Appliances space The LP3985 is available with fixed output voltages from 2.5 V to 5 V. Contact Texas Instruments Sales for specific voltage option needs. Simplified Schematic 1(C3) Device Information(1) 5(C1) IN PART NUMBER OUT 1µF 1µF LP3985 3(A1) 2(B2) BODY SIZE DSBGA (5) 1.502 mm x 1.045 mm (MAX) SOT-23 (5) 2.90 mm x 1.60 mm (NOM) (1) For all available packages, see the Package Option Addendum at the end of the datasheet. 4(A3) EN LP3985 PACKAGE BYPASS * Pin Numbers in parenthesis indicate DSBGA package. * Optional Noise Reduction Capacitor. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LP3985 SNVS087AE – OCTOBER 2000 – REVISED MAY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 4 5 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Performance Characteristics ........................ Detailed Description ............................................ 13 7.1 Overview ................................................................. 13 7.2 Functional Block Diagram ....................................... 13 7.3 Feature Description................................................. 13 7.4 Device Functional Modes........................................ 14 8 Application and Implementation ........................ 15 8.1 Application Information............................................ 15 8.2 Typical Application ................................................. 15 9 Power Supply Recommendations...................... 18 10 Layout................................................................... 19 10.1 10.2 10.3 10.4 Layout Guidelines ................................................. Layout Examples................................................... DSBGA Mounting.................................................. DSBGA Light Sensitivity ....................................... 19 19 19 19 11 Device and Documentation Support ................. 21 11.1 11.2 11.3 11.4 Documentation Support ....................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 21 21 21 21 12 Mechanical, Packaging, and Orderable Information ........................................................... 21 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision AD (October 2014) to Revision AE Page • Changed update pin names to TI nomenclature; replace Handling Ratings with ESD Ratings ........................................... 1 • Deleted Voltage Options table - information in POA ............................................................................................................. 1 • Added GND as type for ground pins ..................................................................................................................................... 3 • Added Thermal Considerations sub-section ........................................................................................................................ 17 Changes from Revision AC (May 2013) to Revision AD • Added Device Information and Handling Rating tables, Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and Orderable Information sections; moved some curves to Application Curves section; add new Thermal Information........................................................................................................................................................ 1 Changes from Revision AB (May 2013) to Revision AC • 2 Page Page Changed layout of National Data Sheet to TI format ........................................................................................................... 20 Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3985 LP3985 www.ti.com SNVS087AE – OCTOBER 2000 – REVISED MAY 2015 5 Pin Configuration and Functions DBV Package 5 Pin SOT-23 Top View EN 3 GND 2 IN 1 5 OUT 4 BYPASS YZR Package 5 Pin DSBGA Top View BYPASS IN A3 C3 GND B2 A1 C1 EN OUT Pin Functions PIN (1) NAME DSBGA NUMBER (1) SOT-23 NUMBER TYPE DESCRIPTION BYPASS A3 4 I/O EN A1 3 I GND B2 2 GND IN C3 1 I Input voltage of the LDO OUT C1 5 O Output voltage of the LDO Optional bypass capacitor for noise reduction Enable input logic, enable high Common ground The pin numbering scheme for the DSBGA package was revised in April 2002 to conform to JEDEC standard. Only the pin numbers were revised. No changes to the physical location of the inputs/outputs were made. For reference purposes, the obsolete numbering scheme had VEN as pin 1, GND as pin 2, VOUT as pin 3, VIN as pin 4, and BYPASS as pin 5. Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3985 3 LP3985 SNVS087AE – OCTOBER 2000 – REVISED MAY 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) (3) MIN MAX IN, EN –0.3 6.5 OUT −0.3 (VIN + 0.3) < 6.5 Junction temperature 150 Lead temperature 235 Pad temperature (4) SOT-23 (5) 364 DSBGA (5) 314 Storage temperature, Tstg (2) (3) (4) (5) V °C 235 Maximum power dissipation (1) UNIT –65 mW 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to potential at the GND pin. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Additional information on lead temperature and pad temperature can be found in Texas Instruments Application Note AN-1187 Leadless Leadframe Package (LLP) (SNOA401). The Absolute Maximum power dissipation depends on the ambient temperature and can be calculated using the formula: PD = (TJ TA)/RθJA,where TJ is the junction temperature, TA is the ambient temperature, and RθJA is the junction-to-ambient thermal resistance. The 364-mW rating for SOT23-5 appearing under Absolute Maximum Ratings results from substituting the Absolute Maximum junction temperature, 150°C for TJ, 70°C for TA, and 220°C/W for RθJA. More power can be dissipated safely at ambient temperatures below 70°C . Less power can be dissipated safely at ambient temperatures above 70°C. The Absolute Maximum power dissipation can be increased by 4.5 mW for each degree below 70°C, and it must be derated by 4.5 mW for each degree above 70°C. 6.2 ESD Ratings V(ESD) (1) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) VALUE UNIT ±2000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VIN Supply input voltage VEN ON/OFF input voltage IOUT Output current TJ Operating junction temperature (1) MIN MAX 2.5 (1) 6 0 −40 UNIT V VIN V 150 mA 125 °C Recommended minimum VIN is the greater of 2.5-V or VOUT(MAX) + rated dropout voltage (max) for operating load current. 6.4 Thermal Information LP3985 THERMAL METRIC (1) SOT-23 (DBV) DSBGA (YZR) UNIT 5 PINS RθJA Junction-to-ambient thermal resistance 220 RθJC(top) Junction-to-case (top) thermal resistance 79.8 0.8 RθJB Junction-to-board thermal resistance 31.6 107.9 ψJT Junction-to-top characterization parameter 3.1 0.5 ψJB Junction-to-board characterization parameter 31.1 107.9 RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A (1) 4 255 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3985 LP3985 www.ti.com SNVS087AE – OCTOBER 2000 – REVISED MAY 2015 6.5 Electrical Characteristics Unless otherwise specified: VIN = VOUT(nom) + 0.5 V, CIN = 1 μF, IOUT = 1 mA, COUT = 1 μF, CBYPASS = 0.01 μF. Minimum (MIN) and Maximum (MAX) values apply over –40°C ≤ TJ ≤ 125°C and typical values are TA = 25°C, unless otherwise indicated. (1) (2) PARAMETER ΔVOUT Output voltage tolerance IOUT = 1 mA Line regulation error VIN = (VOUT(nom) + 0.5 V) to 6 V, For 4.7-V to 5-V options For all other options Load regulation error (4) Output AC line regulation PSRR IQ TEST CONDITIONS Power supply rejection ratio Quiescent current Dropout voltage (5) –0.19 –0.1 0.19 0.1 %/V LP3985 (DSBGA) 0.0004 0.002 %/mA VIN = VOUT(nom) + 1 V, IOUT = 150 mA (Figure 1) 1.5 mVP-P VIN = VOUT(nom) + 0.2 V, f = 1 kHz, IOUT = 50 mA (Figure 2) 50 dB VIN = VOUT(nom) + 0.2 V, ƒ = 10 kHz, IOUT = 50 mA (Figure 2) 40 dB VEN = 1.4 V, IOUT = 0 mA For 4.7-V to 5-V options For all other options 100 85 165 150 VEN = 1.4 V, IOUT = 0 to 150 mA For 4.7-V to 5-V options For all other options 155 140 250 200 VEN = 0.4 V 0.003 1.5 IOUT = 1 mA 0.4 2 mV IOUT = 50 mA 20 35 mV IOUT = 100 mA 45 70 mV IOUT = 150 mA 60 100 mV Peak output current VOUT ≥ VOUT(nom) – 5% TON Turnon time (6) CBYPASS = 0.01 µF Output noise voltage (7) BW = 10 Hz to 100 kHz, COUT = 1 µF Output noise density CBP = 0 IEN Maximum input current at EN VEN = 0.4 V and VIN = 6 V VIL Maximum low-level input voltage at EN VIN = 2.5 V to 6 V VIH Minimum high-level input voltage at EN VIN = 2.5 V to 6 V TSD Thermal shutdown temperature µA 300 600 mA 550 mA 200 µs 30 µVRMS 230 nV/ √Hz ±1 nA 0.4 V V 1.4 160 Thermal shutdown hysteresis (7) % of VOUT(nom) %/mA IOUT(PK) (6) UNIT 2 (3) 3 0.005 Short circuit current limit (2) (3) (4) (5) MAX 0.0025 ISC (1) TYP IOUT = 1 mA to 150 mA LP3985IM5 (SOT23-5) Output Grounded (Steady State) en MIN –2 (3) –3 20 °C °C All limits are verified. All electrical characteristics having room-temperature limits are tested during production with TA = 25°C or correlated using Statistical Quality Control (SQC) methods. All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. The target output voltage, which is labeled VOUT(NOM), is the desired voltage option. TA = 25°C only. An increase in the load current results in a slight decrease in the output voltage and vice versa. Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value. This specification does not apply for input voltages below 2.5V. Turnon time is time measured between the enable input just exceeding VIH and the output voltage just reaching 95% of its nominal value. The output noise varies with output voltage option. The 30 µVRMS is measured with 2.5-V voltage option. To calculate an approximated output noise for other options, use the equation: (30µVRMS)(X)/2.5, where X is the voltage option value. Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3985 5 LP3985 SNVS087AE – OCTOBER 2000 – REVISED MAY 2015 www.ti.com Figure 1. Line Transient Input Test Signal Figure 2. PSRR Input Test Signal 6 Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3985 LP3985 www.ti.com SNVS087AE – OCTOBER 2000 – REVISED MAY 2015 6.6 Typical Performance Characteristics Unless otherwise specified, CIN = COUT = 1 µF ceramic, CBYPASS = 0.01 µF, VIN = VOUT + 0.2 V, TA = 25°C, EN pin is tied to VIN. VIN = VOUT + 0.5V VOUT CHANGE (%) 0.4 0 -0.4 -0.8 -50 -25 0 25 50 75 100 125 TEMPERATURE (°C) Figure 3. Output Voltage Change vs Temperature Figure 4. Dropout Voltage vs Load Current Figure 5. Ground Current vs Load Current Figure 6. Ground Current vs VIN at 25°C Figure 7. Ground Current vs VIN at −40°C Figure 8. Ground Current vs VIN at 125°C Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3985 7 LP3985 SNVS087AE – OCTOBER 2000 – REVISED MAY 2015 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, CIN = COUT = 1 µF ceramic, CBYPASS = 0.01 µF, VIN = VOUT + 0.2 V, TA = 25°C, EN pin is tied to VIN. 8 Figure 9. Short Circuit Current (DSBGA) Figure 10. Short Circuit Current (DSBGA) Figure 11. Short Circuit Current (SOT) Figure 12. Short Circuit Current (SOT) Figure 13. Short Circuit Current (SOT) Figure 14. Short Circuit Current (SOT) Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3985 LP3985 www.ti.com SNVS087AE – OCTOBER 2000 – REVISED MAY 2015 Typical Performance Characteristics (continued) Unless otherwise specified, CIN = COUT = 1 µF ceramic, CBYPASS = 0.01 µF, VIN = VOUT + 0.2 V, TA = 25°C, EN pin is tied to VIN. Figure 16. Short Circuit Current (DSBGA) Figure 15. Short Circuit Current (DSBGA) VIN = VOUT + 0.2 V Figure 17. Output Noise Spectral Density VIN = VOUT + 1 V Figure 18. Ripple Rejection VIN = 5 V Figure 19. Ripple Rejection Figure 20. Ripple Rejection Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3985 9 LP3985 SNVS087AE – OCTOBER 2000 – REVISED MAY 2015 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, CIN = COUT = 1 µF ceramic, CBYPASS = 0.01 µF, VIN = VOUT + 0.2 V, TA = 25°C, EN pin is tied to VIN. VIN = VOUT + 0.2 V VIN = VOUT + 0.2 V Figure 21. Start-up Time VIN = 4.2 V Figure 22. Start-up Time VIN = VOUT + 0.2 V Figure 23. Start-up Time Figure 24. Start-up Time VIN = 4.2 V Figure 26. Line Transient Response Figure 25. Start-up Time 10 Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3985 LP3985 www.ti.com SNVS087AE – OCTOBER 2000 – REVISED MAY 2015 Typical Performance Characteristics (continued) Unless otherwise specified, CIN = COUT = 1 µF ceramic, CBYPASS = 0.01 µF, VIN = VOUT + 0.2 V, TA = 25°C, EN pin is tied to VIN. VIN = 3.2 V Figure 27. Line Transient Response Figure 28. Load Transient Response VIN = 4.2 V VIN = 3.2 V Figure 29. Load Transient Response Figure 30. Load Transient Response VIN = VOUT + 0.2 V VIN = 4.2 V Figure 31. Load Transient Response Figure 32. Enable Response Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3985 11 LP3985 SNVS087AE – OCTOBER 2000 – REVISED MAY 2015 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, CIN = COUT = 1 µF ceramic, CBYPASS = 0.01 µF, VIN = VOUT + 0.2 V, TA = 25°C, EN pin is tied to VIN. VIN = VOUT + 0.2 V VIN = 4.2 V Figure 33. Enable Response VIN = 4.2 V Figure 34. Enable Response VIN = VOUT + 0.2 V Figure 35. Output Impedance 12 Figure 36. Output Impedance Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3985 LP3985 www.ti.com SNVS087AE – OCTOBER 2000 – REVISED MAY 2015 7 Detailed Description 7.1 Overview The LP3985 family of fixed-output, ultra-low-dropout and low noise regulators offers exceptional, cost-effective performance for battery powered applications. Available in output voltages from 2.5 V to 5 V, the family is capable of delivering 150-mA continuous load current. Standard regulator features, such as overcurrent and overtemperature protection, are also included. The LP3985 contains several features to facilitate battery powered designs: • Multiple voltage options • Low dropout voltage, typical dropout of 60 mV at 150-mA load current • Low quiescent current and low ground current, typically 140 μA at 150-mA load, and 85-μA at 0-mA load • A shutdown feature is available, allowing the regulator to consume only 0.003 µA typically when the EN pin is pulled low • Overtemperature protection and overcurrent protection circuitry is designed to safeguard the device during unexpected conditions • Enhanced stability: The LP3985 is stable with output capacitor, which allows the use of ceramic capacitors on the output • Power supply rejection is better than 50 dB at low frequencies and starts to roll off at 1 kHz. • Low noise: A BYPASS pin allows for low-noise operation, with a typical output noise of 30 µVRMS, with the use of a 10-nF bypass capacitor. 7.2 Functional Block Diagram IN EN ON t 1.4V OUT Vreference 1.23V Fast Turnon Circuit R1 OFF d 0.4V BYPASS R2 Overcurrent & Thermal Protection GND 7.3 Feature Description 7.3.1 No-Load Stability The LP3985 will remain stable and in regulation with no external load. This is specially important in CMOS RAM keep-alive applications. 7.3.2 On/Off Input Operation The LP3985 is turned off by pulling the EN pin low, and turned on by pulling it high. If this feature is not used, the EN pin should be tied to VIN to keep the regulator output on at all time. To assure proper operation, the signal source used to drive the EN input must be able to swing above and below the specified turnon/turnoff voltage thresholds listed in Electrical Characteristics under VIL and VIH. Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3985 13 LP3985 SNVS087AE – OCTOBER 2000 – REVISED MAY 2015 www.ti.com Feature Description (continued) 7.3.3 Fast On-Time The LP3985 output is turned on after VREF voltage reaches its final value (1.23 V, nominal). To speed up this process, the noise reduction capacitor at the BYPASS pin is charged with an internal 70-µA current source. The current source is turned off when the bandgap voltage reaches approximately 95% of its final value. The turnon time is determined by the time constant of the bypass capacitor. The smaller the capacitor value, the shorter the turn on time, but less noise gets reduced. As a result, turn on time and noise reduction need to be taken into design consideration when choosing the value of the bypass capacitor. 7.4 Device Functional Modes 7.4.1 Operation with VOUT(TARGET) + 0.3 V ≤ VIN ≤ 6 V The device operates if the input voltage is equal to, or exceeds, VOUT(TARGET) + 0.3 V. At input voltages below the minimum VIN requirement, the devices does not operate correctly, and output voltage may not reach target value. 7.4.2 Operation Using the EN Pin If the voltage on the EN pin is less than 0.4 V, the device is disabled, and in this state shutdown current does not exceed 1.5 μA. Raising VEN above 1.4 V initiates the start-up sequence of the device. 14 Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3985 LP3985 www.ti.com SNVS087AE – OCTOBER 2000 – REVISED MAY 2015 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LP3985 can provide 150-mA output current with 2.5-V to 6-V input. It is stable with a small 1-µF ±30% ceramic or high-quality tantalum output capacitor. The DSBGA requires the smallest possible PC board area – the total application circuit area can be less than 2 mm x 2.5 mm, a fraction of a 1206 case size. An optional external bypass capacitor reduces the output noise without slowing down the load transient response. Fast startup time is achieved by utilizing an internal power-on circuit that actively pre-charges the bypass capacitor. Typical output noise is 30 µVRMS at frequencies from 10 Hz to 100 kHz. Typical power supply rejection is 50 dB at 1 kHz. 8.2 Typical Application 1(C3) 5(C1) IN OUT 1µF 1µF LP3985 3(A1) 4(A3) EN BYPASS * 2(B2) Pin Numbers in parenthesis indicate DSBGA package. * Optional Noise Reduction Capacitor. Figure 37. LP3985 Typical Application 8.2.1 Design Requirements DESIGN PARAMETERS VALUE Input voltage 4.2 V, ±10% provided by the DC-DC converter switching at 1 MHz Output voltage 3 V, ±5% Output current 150 mA (maximum) RMS noise, 10 Hz to100 kHz 30 μVRMS PSRR at 1 kHz 50 dB 8.2.2 Detailed Design Procedure 8.2.2.1 External Capacitors Like any low-dropout regulator, the LP3985 requires external capacitors for regulator stability. The LP3985 is specifically designed for portable applications requiring minimum board space and smallest components. These capacitors must be correctly selected for good performance. 8.2.2.2 Input Capacitor An input capacitance of approximately 1 µF is required between the LP3985 input pin and ground (the amount of the capacitance may be increased without limit). Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3985 15 LP3985 SNVS087AE – OCTOBER 2000 – REVISED MAY 2015 www.ti.com This capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean analog ground. A ceramic capacitor is recommended although a good quality tantalum or film capacitor may be used at the input. NOTE Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a low-impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be verified by the manufacturer to have a surge current rating sufficient for the application. There are no requirements for the ESR on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain within the operational range over the full range of temperature and operating conditions. 8.2.2.3 Output Capacitor Correct selection of the output capacitor is important to ensure stable operation in the intended application. The output capacitor must meet all the requirements specified in the recommended capacitor table over all conditions in the application. These conditions include DC-bias, frequency and temperature. Unstable operation will result if the capacitance drops below the minimum specified value. (See the next section Capacitor Characteristics). The LP3985 is designed specifically to work with very small ceramic output capacitors. A 1-µF ceramic capacitor (dialectric type X7R) with ESR between 5 mΩ to 500 mΩ is suitable in the LP3985 application circuit. X5R capacitors may be used but have a narrower temperature range. With these and other capacitor types (Y5V, Z6U) that may be used, selection is dependant on the range of operating conditions and temperature range for that application. (see Capacitor Characteristics ). It may also be possible to use tantalum or film capacitors at the output, but these are not as attractive for reasons of size and cost (see Capacitor Characteristics). It is also recommended that the output capacitor be placed within 1 cm from the output pin and returned to a clean ground line. 8.2.2.4 Capacitor Characteristics The LP3985 is designed to work with ceramic capacitors on the output to take advantage of the benefits they offer: for capacitance values in the range of 1 µF to 4.7 µF, ceramic capacitors are the smallest, least expensive, and have the lowest ESR values (which makes them best for eliminating high frequency noise). The ESR of a typical 1-µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR requirement for stability by the LP3985. For both input and output capacitors careful interpretation of the capacitor specification is required to ensure correct device operation. The capacitor value can change greatly dependant on the conditions of operation and capacitor type. In particular the output capacitor selection should take account of all the capacitor parameters to ensure that the specification is met within the application. Capacitance value can vary with DC bias conditions as well as temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging. The capacitor parameters are also dependant on the particular case size with smaller sizes giving poorer performance figures in general. As an example Figure 38 shows a typical graph showing a comparison of capacitor case sizes in a Capacitance vs. DC Bias plot. As shown in the graph, as a result of the DC Bias condition the capacitance value may drop below the minimum capacitance value given in the recommended capacitor table (0.7 µF in this case). Note that the graph shows the capacitance out of spec for the 0402 case size capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers' specifications for the nominal value capacitor are consulted for all conditions as some capacitor sizes (for example, 0402) may not be suitable in the actual application. 16 Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3985 LP3985 SNVS087AE – OCTOBER 2000 – REVISED MAY 2015 CAP VALUE (% of NOMINAL 1 PF) www.ti.com 0603, 10V, X5R 100% 80% 60% 0402, 6.3V, X5R 40% 20% 0 1.0 2.0 3.0 4.0 5.0 DC BIAS (V) Figure 38. Graph Showing A Typical Variation In Capacitance vs DC Bias The ceramic capacitor's capacitance can vary with temperature. The capacitor type X7R, which operates over a temperature range of −55°C to 125°C, will only vary the capacitance to within ±15%. The capacitor type X5R has a similar tolerance over a reduced temperature range of −55°C to 85°C. Most large value ceramic capacitors (around 2.2 µF) are manufactured with Z5U or Y5V temperature characteristics. Their capacitance can drop by more than 50% as the temperature goes from 25°C to 85°C. Therefore X7R is recommended over Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25°C. Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 1-µF to 4.7-µF range. Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly ) than a ceramic capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about 2:1 as the temperature goes from 25°C down to −40°C, so some guard band must be allowed. 8.2.2.5 Noise Bypass Capacitor Connecting a 0.01-µF capacitor between the CBYPASS pin and ground significantly reduces noise on the regulator output. This cap is connected directly to a high impedance node in the band gap reference circuit. Any significant loading on this node will cause a change on the regulated output voltage. For this reason, DC leakage current through this pin must be kept as low as possible for best output voltage accuracy. The types of capacitors best suited for the noise bypass capacitor are ceramic and film. High-quality ceramic capacitors with either NPO or COG dielectric typically have very low leakage. Polypropolene and polycarbonate film capacitors are available in small surface-mount packages and typically have extremely low leakage current. Unlike many other LDOs, addition of a noise reduction capacitor does not effect the load transient response of the device. 8.2.2.6 Thermal Considerations CAUTION Due to the limited power dissipation characteristics of the available SOT-23 (DBV) and DSBGA (YZR) packages, all possible combinations of output current (IOUT), input voltage (VIN), output voltage (VOUT), and ambient temperatures (TA) cannot be ensured. Power dissipation, PD is calculated from the following formula: PD = ((VIN – VOUT) × IOUT) . Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3985 17 LP3985 SNVS087AE – OCTOBER 2000 – REVISED MAY 2015 www.ti.com The LP3985 regulator has internal thermal limiting designed to protect the device during overload conditions. For continuous normal conditions, the recommended maximum operating junction temperature is 125°C. It is important to give careful consideration to all sources of thermal resistance from junction to ambient. Additional heat sources mounted nearby must also be considered. For surface-mount devices, heat sinking is accomplished by using the heat-spreading capabilities of the PC board and its copper traces. Copper board stiffeners and plated through-holes can also be used to spread the heat generated by power devices. Example: Given an output voltage of 3.3 V, an input voltage range of 4 V to 6 V, a maximum output current of 100 mA, and a maximum ambient temperature of 50°C, what is the maximum operating junction temperature? The power dissipated by the device is found using the formula: PD(MAX) = ((VIN(MAX) ± VOUT) × IOUT(MAX)) where • • • IOUT(MAX) = 100 mA VIN(MAX) = 6 V VOUT = 3.3 V (1) For example, PD(MAX) = ((6 V – 3.3 V) × 100 mA ) = 0.27 W. Using the 5-pin SOT-23 (DBV) package, the LP3985 junction-to-ambient thermal resistance (RθJA) has a rating of 220°C/W using the standard JEDEC JESD51-7 PCB (High-K) circuit board. The junction temperature rise above ambient is found using the formula: TRISE = PD(MAX) × RθJA; for example, TJ(MAX) = 50°C + 59.4°C = 109.4°C. 8.2.3 Application Curves VIN = 4.2 V VIN = 4.2 V Figure 39. Start-up Time Figure 40. Enable Response 9 Power Supply Recommendations The LP3985 is designed to operate from an input voltage supply range between 2.5 V and 6 V. The input-voltage range provides adequate headroom in order for the device to have a regulated output. This input supply must be well regulated. If the input supply is noisy, additional input capacitors with low ESR can help to improve the output noise performance. 18 Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3985 LP3985 www.ti.com SNVS087AE – OCTOBER 2000 – REVISED MAY 2015 10 Layout 10.1 Layout Guidelines For best overall performance, place all circuit components on the same side of the circuit board and as near as practical to the respective LDO pin connections. Place ground return connections to the input and output capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and negatively affects system performance. This grounding and layout scheme minimizes inductive parasitics, and thereby reduces load-current transients, minimizes noise, and increases circuit stability. A ground reference plane is also recommended and is either embedded in the PCB itself or located on the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the output voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO device. In most applications, this ground plane is necessary to meet thermal requirements. 10.2 Layout Examples VIN VOUT Input Capacitor OUT IN Output Capacitor GND Ground Bypass Capacitor EN BYPASS Figure 41. LP3985 SOT-23 Package Typical Layout IN OUT Input Capacitor C3 GND B2 Bypass Capacitor A3 BYPASS Output Capacitor C1 A1 EN Figure 42. LP3985 DSBGA Package Typical Layout 10.3 DSBGA Mounting The DSBGA package requires specific mounting techniques which are detailed in Texas Instruments Application Note 1112 DSBGA Wafer Level Chip Scale Package (SNVA009). Referring to the section Surface Mount Technology (SMT) Assembly Considerations, it should be noted that the pad style which must be used with the 5-bump package is NSMD (non-solder mask defined) type. For best results during assembly, alignment ordinals on the PC board may be used to facilitate placement of the DSBGA device. 10.4 DSBGA Light Sensitivity Exposing the DSBGA device to direct sunlight will cause mis-operation of the device. Light sources such as halogen lamps can effect electrical performance if brought near to the device. Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3985 19 LP3985 SNVS087AE – OCTOBER 2000 – REVISED MAY 2015 www.ti.com DSBGA Light Sensitivity (continued) The wavelengths which have most detrimental effect are reds and infra-reds, which means that the fluorescent lighting used inside most buildings has very little effect on performance. A DSBGA test board was brought to within 1 cm of a fluorescent desk lamp and the effect on the regulated output voltage was negligible, showing a deviation of less than 0.1% from nominal. 20 Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3985 LP3985 www.ti.com SNVS087AE – OCTOBER 2000 – REVISED MAY 2015 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation, see the following: • Texas Instruments Application Note AN-1187 Leadless Leadframe Package (LLP) (SNOA401). • Texas Instruments Application Note AN-1112 DSBGA Wafer Level Chip Scale Package (SNVA009). 11.2 Trademarks All trademarks are the property of their respective owners. 11.3 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LP3985 21 PACKAGE OPTION ADDENDUM www.ti.com 29-Nov-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) LP3985IM5-2.5 NRND SOT-23 DBV 5 1000 Non-RoHS & Non-Green Call TI Call TI -40 to 125 LCSB LP3985IM5-2.5/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LCSB Samples LP3985IM5-2.7/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LCUB Samples LP3985IM5-2.8/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LCJB Samples LP3985IM5-2.9/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LCYB Samples LP3985IM5-3.0/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LCRB Samples LP3985IM5-3.2/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LDPB Samples LP3985IM5-3.3 NRND SOT-23 DBV 5 1000 Non-RoHS & Green Call TI Level-1-260C-UNLIM -40 to 125 LDQB LP3985IM5-3.3/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LDQB Samples LP3985IM5-4.7/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LDRB Samples LP3985IM5-5.0/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LDSB Samples LP3985IM5X-2.5/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LCSB Samples LP3985IM5X-2.8/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LCJB Samples LP3985IM5X-285/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LCXB Samples LP3985IM5X-3.0 NRND SOT-23 DBV 5 3000 Non-RoHS & Green Call TI Level-1-260C-UNLIM -40 to 125 LCRB LP3985IM5X-3.0/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LCRB Samples LP3985IM5X-3.3/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LDQB Samples LP3985IM5X-4.7/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LDRB Samples LP3985IM5X-5.0/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LDSB Samples Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 29-Nov-2022 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) LP3985ITL-2.5/NOPB ACTIVE DSBGA YZR 5 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 5 Samples LP3985ITL-2.6/NOPB ACTIVE DSBGA YZR 5 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 5 Samples LP3985ITL-2.7/NOPB ACTIVE DSBGA YZR 5 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 5 Samples LP3985ITL-2.8/NOPB ACTIVE DSBGA YZR 5 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 5 Samples LP3985ITL-2.9/NOPB ACTIVE DSBGA YZR 5 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 5 Samples LP3985ITL-285/NOPB ACTIVE DSBGA YZR 5 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 5 Samples LP3985ITL-3.0/NOPB ACTIVE DSBGA YZR 5 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 5 Samples LP3985ITL-3.1/NOPB ACTIVE DSBGA YZR 5 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 5 Samples LP3985ITL-3.3/NOPB ACTIVE DSBGA YZR 5 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 5 Samples LP3985ITL-4.8/NOPB ACTIVE DSBGA YZR 5 250 RoHS & Green SNAGCU Level-1-260C-UNLIM 5 Samples LP3985ITL-5.0/NOPB ACTIVE DSBGA YZR 5 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 5 Samples LP3985ITLX-2.5/NOPB ACTIVE DSBGA YZR 5 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 5 Samples LP3985ITLX-2.7/NOPB ACTIVE DSBGA YZR 5 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 5 Samples LP3985ITLX-2.8/NOPB ACTIVE DSBGA YZR 5 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 5 Samples LP3985ITLX-285/NOPB ACTIVE DSBGA YZR 5 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 5 Samples LP3985ITLX-3.0/NOPB ACTIVE DSBGA YZR 5 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 5 Samples LP3985ITLX-3.1/NOPB ACTIVE DSBGA YZR 5 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 5 Samples LP3985ITLX-3.3/NOPB ACTIVE DSBGA YZR 5 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 5 Samples LP3985ITLX-5.0/NOPB ACTIVE DSBGA YZR 5 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 5 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 29-Nov-2022 NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of