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LP3990-Q1
SNVSA66A – OCTOBER 2014 – REVISED DECEMBER 2015
LP3990-Q1 150-mA Linear Voltage Regulator for Digital Applications
1 Features
3 Description
•
•
The LP3990-Q1 regulator is designed to meet the
requirements of portable, battery-powered systems
providing an accurate output voltage, low-noise, and
low-quiescent current. The LP3990-Q1 will provide a
0.8-V output from the low input voltage of 2 V at up to
a 150-mA load current. When switched into shutdown
mode via a logic signal at the enable pin (EN), the
power consumption is reduced to virtually zero.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Range
Input Voltage Range: 2 V to 6 V
1% Voltage Accuracy at Room Temperature
Output Voltage Range: 0.8 V to 3.3 V
Output Current: 150 mA
Logic Controlled Enable
Thermal-Overload and Short-Circuit Protection
Virtually Zero IQ (Disabled), < 10 nA
Very Low IQ (Enabled): 43 µA
Low Output Noise: 150 µVRMS
PSRR: 55 dB at 1 kHz
Fast Start-Up: 105 µs
Stable with Ceramic Capacitor
Output Stable - Capacitors, 1 µF
No Noise Bypass Capacitor Required
The LP3990-Q1 is designed to be stable with spacesaving ceramic capacitors with values as low as 1 µF.
Performance is specified for a –40°C to +125°C
junction temperature range.
For output voltage options please refer to package
option addendum (POA) or contact the Texas
Instruments Sales Office.
Device Information(1)
PART NUMBER
LP3990-Q1
PACKAGE
DSBGA (4)
BODY SIZE
1.324 mm x 1.045 mm (MAX)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
Infotainment
Instrumentation
Body Electronics
Simplified Schematic
VIN
IN
CIN
1 µF
LP3990
VEN
ON
OFF
GND
VOUT
OUT
COUT
1 µF
EN
GND
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP3990-Q1
SNVSA66A – OCTOBER 2014 – REVISED DECEMBER 2015
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
4
5
5
6
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Output Capacitor, Recommended Specifications .....
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 10
8
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application ................................................. 11
9 Power Supply Recommendations...................... 14
10 Layout................................................................... 14
10.1
10.2
10.3
10.4
Layout Guidelines .................................................
Layout Example ....................................................
DSBGA Mounting..................................................
DSBGA Light Sensitivity .......................................
14
15
15
15
11 Device and Documentation Support ................. 16
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
16
16
12 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (October 2014) to Revision A
Page
•
Changed "For output voltages other than 0.8 V, 1.2 V, 1.35 V, 1.5 V, 1.8 V, 2.5 V, 2.8 V, or 3.3 V, please contact
the Texas Instruments sales office." to "For output voltage options please refer to package option addendum (POA)
or contact the Texas Instruments Sales Office." .................................................................................................................... 1
•
Changed Handling Ratings to ESD Ratings table ................................................................................................................. 4
•
Added introductory sentence for Design Requirements ...................................................................................................... 11
2
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5 Pin Configuration and Functions
DSBGA (YZR)
4 Pins
EN
A2
IN
B2
IN
B2
EN
A2
A1
GND
B1
OUT
B1
OUT
A1
GND
TOP VIEW
BOTTOM VIEW
Pin Functions
PIN
NO.
NAME
A1
GND
A2
EN
B1
OUT
B2
IN
I/O
—
DESCRIPTION
Common ground.
I
Enable Input; Enables the regulator when ≥ 0.95 V.
Disables the Regulator when ≤ 0.4 V.
Enable Input has 1-MΩ (typical) pulldown resistor to GND.
O
Voltage output. A 1-µF low-ESR capacitor must be connected to this pin. Connect this output to the
load circuit.
I
Voltage supply Input. A 1-µF capacitor must be connected at this input.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
Input voltage
MIN
MAX
UNIT
–0.3
6.5
V
Output voltage
–0.3
ENABLE input voltage
–0.3
Storage temperature range , Tstg
(2)
(3)
(4)
(5)
V
6.5
V
150
°C
See (5)
Continuous power dissipation internally limited
(1)
See
(4)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, contact the TI Sales Office/Distributors for availability and specifications.
All voltages are with respect to the potential at the GND pin.
The lower of VIN + 0.3 V or 6.5 V.
Internal thermal shutdown circuitry protects the device from permanent damage.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Human-body model (HBM), per AEC Q100-002
Electrostatic discharge
(1)
UNIT
±2000
Charged-device model (CDM), per AEC Q100-011
V
±1500
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Input voltage, VIN
2
6
V
Enable input voltage, VEN
0
VIN
V
–40
125
°C
Junction temperature, TJ
(1)
(1)
TJ-MAX = (TA-MAX + (RθJA × PD-MAX)).
6.4 Thermal Information
LP3990
THERMAL METRIC (1)
YZR (DSBGA)
UNIT
4 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
188.9
°C/W
1.0
°C/W
105.3
°C/W
0.7
°C/W
105.2
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
Unless otherwise noted, VEN = 950 mV, VIN = VOUT + 1 V or VIN = 2 V, whichever is higher. CIN = 1 µF, IOUT = 1 mA, COUT =
0.47 µF. (1) (2)
PARAMETER
VIN
Input voltage
Output voltage tolerance
ΔVOUT
Line regulation error
TEST CONDITIONS
See (3)
MIN
TYP
2
ILOAD = 1 mA, TJ = 25°C
Over full line and load regulation
VIN = (VOUT(NOM) + 1 V) to 6 V
Load regulation error
IOUT = 1 mA
to 150 mA
VDO
Dropout voltage
IOUT = 150 mA, see (4) (5)
ILOAD
Load current
TJ = 25°, see (5) (6)
IQ
Quiescent current
–1%
1%
2.5%
0.1
0.02
0.1
VOUT = 0.8 V to 1.95 V
–0.005
0.002
0.005
VOUT = 2 V to 3.3 V
–0.002
0.0005
0.002
120
200
V
%/V
%/mA
mV
0
µA
VEN = 950 mV, IOUT = 0 mA
43
80
VEN = 950 mV, IOUT = 150 mA
65
120
0.002
0.2
550
1000
See (7)
ISC
Short circuit current limit
IOUT
Maximum output current
PSRR
Power Supply Rejection
Ratio
ƒ = 1 kHz, IOUT = 1 mA to 150 mA
55
ƒ = 10 kHz, IOUT = 150 mA
35
eη
Output noise voltage (5)
BW = 10 Hz to 100
kHz
Thermal shutdown
junction temperature
UNIT
6
–2.5%
VEN = 0.4 V (output disabled), TJ = 25°C
TSHUTDOWN
MAX
µA
mA
150
VOUT = 0.8 V
60
VOUT = 1.5 V
125
VOUT = 3.3 V
180
Junction temperature (TJ) rising until the output
is disabled
dB
µVRMS
155
Hysteresis
°C
15
ENABLE CONTROL CHARACTERISTICS
IEN (8)
Maximum input current
at EN pin
VEN = 0 V (Output is disabled)
TJ = 25°C
VEN = 6 V
Low input threshold
VIN = 2 V to 6 V
VEN falling from ≥ VIH until the output is disabled
VIH
High input threshold
VIN = 2 V to 6 V
VEN rising from ≤ VIL until the output is enabled
(3)
(4)
(5)
(6)
(7)
(8)
0.1
6
10
2.5
VIL
(1)
(2)
0.001
µA
0.4
V
0.95
All voltages are with respect to the device GND terminal, unless otherwise stated.
Minimum and Maximum limits are ensured through test, design, or statistical correlation over the operating junction temperature range
(TJ) of –40°C to 125°C, unless otherwise stated. Typical values represent the most likely parametric norm at TJ = 25°C, and are
provided for reference purposes only.
VIN(MIN) = VOUT(NOM) + 0.5 V, or 2 V, whichever is higher.
Dropout voltage is voltage difference between input and output at which the output voltage drops to 100 mV below its nominal value.
This parameter applies only for output voltages above 2 V.
This electrical specification is verified by design.
The device maintains the regulated output voltage without the load.
Short-circuit current is measured with VOUT pulled to 0 V and VIN worst case = 6 V.
ENABLE pin has 1-MΩ (typical) resistor connected to GND.
6.6 Output Capacitor, Recommended Specifications
See (1)
PARAMETER
COUT
(1)
(2)
(3)
Output capacitance
TEST CONDITIONS
Capacitance (2)
ESR
MIN
TYP
MAX
0.7 (3)
1
500
UNIT
5
µF
mΩ
Unless otherwise specified, values and limits apply for TJ = 25°C.
The full operating conditions for the application must be considered when selecting a suitable capacitor to ensure that the minimum
value of capacitance is always met. Recommended capacitor type is X7R. However, dependent on application, X5R, Y5V, and Z5U can
also be used. (See Detailed Design Procedure.)
Limit applies over the full operating junction temperature range (TJ) of −40°C to 125°C.
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6.7 Timing Requirements
NOM (1)
MAX (2)
VOUT = 0.8 V
80
150
VOUT = 1.5 V
105
200
VOUT = 3.3 V
175
250
8
16
mV (pkpk)
55
100
mV
MIN
Transient
response
(1)
(2)
(3)
From VEN ↑ VIH to
VOUT 95% level
(VIN(MIN) to 6 V)
Turnon time (3)
TON
Line transient response
(ΔVOUT)
Trise = Tfall = 30 µs (3),
ΔVIN = 600 mV
Load transient response
(ΔVOUT)
Trise = Tfall = 1 µs (3),
IOUT = 1 mA to 150 mA
COUT = 1 µF
UNIT
µs
Nominal values apply for TJ = 25°C.
Maximum limits apply over the full operating junction temperature (TJ) range of −40°C to 125°C.
This electrical specification is verified by design.
6.8 Typical Characteristics
2.00
80
1.50
70
GROUND CURRENT (PA)
VOUT CHANGE (%)
Unless otherwise specified, CIN = 1-µF ceramic, COUT = 0.47-µF ceramic, VIN = VOUT(NOM) + 1 V, TA = 25°C, VOUT(NOM) = 1.5 V;
VEN = VIN.
1.00
0.50
0.00
-0.50
-1.00
-1.50
TJ = 125°C
60
50
40
TJ = -40°C
30
TJ = 25°C
20
10
-2.00
-40
-25
0
25
50
75
100
0
125
0
25
TEMPERATURE (°C)
75
100
90
90
80
80
70
70
60
TJ = 125°C
125
150
60
TJ = 125°C
50
TJ = 25°C
TJ = 25°C
40
40
TJ = -40°C
30
TJ = -40°C
30
20
20
2
2.5
3
3.5
4
4.5
5
5.5
6
2
VIN
2.5
3
3.5
4
4.5
5
5.5
6
VIN
ILOAD = 0 mA
ILOAD = 1 mA
Figure 3. Ground Current vs VIN
6
100
Figure 2. Ground Current vs Load Current
100
GND I (PA)
GND I (PA)
Figure 1. Output Voltage Change vs Temperature
50
50
LOAD CURRENT (mA)
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Figure 4. Ground Current vs VIN
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Typical Characteristics (continued)
Unless otherwise specified, CIN = 1-µF ceramic, COUT = 0.47-µF ceramic, VIN = VOUT(NOM) + 1 V, TA = 25°C, VOUT(NOM) = 1.5 V;
VEN = VIN.
100
VIN = 2.5V
800
90
TJ = 125°C
CURRENT
(mA)
GND I (µA)
80
70
TJ = 25°C
60
TJ = -40°C
50
600
400
200
0
VOUT
30
20
2
2.5
3
3.5
4
4.5
5
5.5
(1V/Div)
40
6
TIME (100 Ps/DIV)
VIN
ILOAD = 150 mA
Figure 6. Short Circuit Current
Figure 5. Ground Current vs VIN
CIN = 1 PF
VIN = 6V
COUT = 0.47 PF
IL = 1 to 150 mA
600
VIN (V)
400
(1V/Div)
'VOUT
0
VOUT
3.1
2.5
200
(10 mV/Div)
CURRENT
(mA)
800
TIME (100 Ps/DIV)
TIME (100 Ps/DIV)
Figure 8. Line Transient
0
0
-10
-10
COUT = 0.47 PF
-20
RIPPLE REJECTION (dB)
RIPPLE REJECTION (dB)
Figure 7. Short Circuit Current
-30
IL = 1 mA
-40
-50
COUT = 1 PF
-60
-70
-80
COUT = 1 PF
-20
-30
-40
ILOAD = 150 mA
-50
COUT = 0.47 PF
-60
-70
-80
-90
-90
100
1k
10k
100k
100
1M
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 9. Power Supply Rejection Ratio
Figure 10. Power Supply Rejection Ratio
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Typical Characteristics (continued)
Unless otherwise specified, CIN = 1-µF ceramic, COUT = 0.47-µF ceramic, VIN = VOUT(NOM) + 1 V, TA = 25°C, VOUT(NOM) = 1.5 V;
VEN = VIN.
10
NOISE (PV/ Hz)
VOUT
VOUT = 3.3V
(1V/Div)
VEN
(500 mV/Div)
IL = 1 mA
VOUT = 1.5V
0.1
0.01
0.1
TIME (50 Ps/DIV)
1
10
100
FREQUENCY (kHz)
Figure 11. Enable Start-Up Time
8
1
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Figure 12. Noise Density
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7 Detailed Description
7.1 Overview
The LP3990-Q1 is designed to meet the requirements of portable, battery-powered digital systems providing an
accurate output voltage with fast start-up. When disabled via a low logic signal at the enable pin (EN), the power
consumption is reduced to virtually zero.
The device is designed to perform with a single 1-μF input capacitor and a single 1-μF ceramic output capacitor.
7.2 Functional Block Diagram
LP3990
IN
OUT
Current
Limit
Thermal
Shutdown
+
ON
VREF
800 mV
OFF
EN
1M
GND
7.3 Feature Description
7.3.1 Enable (EN)
The LP3990-Q1 Enable (EN) pin is internally held low by a 1-MΩ resistor to GND. The EN pin voltage must be
higher than the VIH threshold to ensure that the device is fully enabled under all operating conditions. The EN pin
voltage must be lower than the VIL threshold to ensure that the device is fully disabled. If the EN pin is left open
the LP3990-Q1 output is disabled.
7.3.2 Thermal Overload Protection (TSD)
Thermal Shutdown disables the output when the junction temperature rises to approximately 155°C which allows
the device to cool. When the junction temperature cools to approximately 140°C, the output circuitry enables.
Based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may
cycle on and off. This thermal cycling limits the dissipation of the regulator and protects it from damage as a
result of overheating.
The Thermal Shutdown circuitry of the LP3990-Q1 has been designed to protect against temporary thermal
overload conditions. The Thermal Shutdown circuitry was not intended to replace proper heat-sinking.
Continuously running the LP3990-Q1 device into thermal shutdown may degrade device reliability.
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7.4 Device Functional Modes
7.4.1 Enable (EN)
The LP3990-Q1 EN pin is internally held low by a 1-MΩ resistor to GND. The EN pin voltage must be higher than
the VIH threshold to ensure that the device is fully enabled under all operating conditions.
7.4.2 Minimum Operating Input Voltage (VIN)
The LP3990-Q1 does not include any dedicated UVLO circuitry. The LP3990-Q1 internal circuitry is not fully
functional until VIN is at least 2 V. The output voltage is not regulated until VIN ≥ (VOUT + VDO), or 2 V, whichever
is higher.
10
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LP3990-Q1 is a linear voltage regulator for digital applications designed to be stable with space-saving
ceramic capacitors as small as 1 µF.
8.2 Typical Application
Figure 13 shows the typical application circuit for the LP3990-Q1. The input and output capacitances may need
to be increased above the 1 μF shown for some applications.
VIN
IN
CIN
1 µF
LP3990
VEN
ON
VOUT
OUT
COUT
1 µF
EN
OFF
GND
GND
GND
Figure 13. LP3990-Q1 Typical Application
8.2.1 Design Requirements
For typical design parameters, see Table 1.
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
2 V to 6 V
Output voltage
1.8 V
Output current
100 mA
Output capacitor range
1 µF
Input/output capacitor ESR range
5 mΩ to 500 mΩ
8.2.2 Detailed Design Procedure
To
•
•
•
•
begin the design process, determine the following:
Available input voltage range
Output voltage needed
Output current needed
Input and output capacitors
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8.2.2.1 Power Dissipation and Device Operation
The permissible power dissipation for any package is a measure of the capability of the device to pass heat from
the power source, the junctions of the device, to the ultimate heat sink, the ambient environment. Thus, the
power dissipation is dependent on the ambient temperature and the thermal resistance across the various
interfaces between the die junction and ambient air.
The maximum allowable power dissipation for the device in a given package can be calculated using Equation 1:
PD-MAX = ((TJ-MAX – TA) / RθJA)
(1)
The actual power being dissipated in the device can be represented by Equation 2:
PD = (VIN – VOUT) × IOUT
(2)
Equation 1 and Equation 2 establish the relationship between the maximum power dissipation allowed due to
thermal consideration, the voltage drop across the device, and the continuous current capability of the device.
Equation 1 and Equation 2 should be used to determine the optimum operating conditions for the device in the
application.
In applications where lower power dissipation (PD) and/or excellent package thermal resistance (RθJA) is present,
the maximum ambient temperature (TA-MAX) may be increased.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum
ambient temperature (TA-MAX) may have to be derated. TA-MAX is dependent on the maximum operating junction
temperature (TJ-MAX-OP = 125°C), the maximum allowable power dissipation in the device package in the
application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (RθJA),
as given by Equation 3:
TA-MAX = (TJ-MAX-OP – (RθJA × PD-MAX))
(3)
Alternately, if TA-MAX can not be derated, the PD value must be reduced. This can be accomplished by reducing
VIN in the VIN – VOUT term as long as the minimum VIN is met, or by reducing the IOUT term, or by some
combination of the two.
8.2.2.2 External Capacitors
In common with most regulators, the LP3990-Q1 requires external capacitors for regulator stability. The LP3990Q1 is specifically designed for portable applications requiring minimum board space and smallest components.
These capacitors must be correctly selected for good performance.
8.2.2.3 Input Capacitor
An input capacitor is required for stability. It is recommended that a 1-µF capacitor be connected between the
LP3990-Q1 IN pin and GND pin (this capacitance value may be increased without limit).
This capacitor must be located a distance of not more than 1 cm from the IN pin and returned to a clean
analogue ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.
Important: To ensure stable operation it is essential that good PCB design practices are employed to minimize
ground impedance and keep input inductance low. If these conditions cannot be met, or if long leads are used to
connect the battery or other power source to the LP3990-Q1, then it is recommended that the input capacitor is
increased. Also, tantalum capacitors can suffer catastrophic failures due to surge current when connected to a
low-impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the
input, it must be ensured by the manufacturer to have a surge current rating sufficient for the application.
There are no requirements for the equivalent series resistance (ESR) on the input capacitor, but tolerance and
temperature coefficient must be considered when selecting the capacitor to ensure the capacitance remains
approximately 1 µF over the entire operating temperature range.
8.2.2.4 Output Capacitor
The LP3990-Q1 is designed specifically to work with very small ceramic output capacitors. A 1-µF ceramic
capacitor (temperature types Z5U, Y5V or X7R/X5R) with ESR between 5 mΩ to 500 mΩ, is suitable in the
LP3990-Q1 application circuit.
For this device the output capacitor must be connected from the OUT pin to the GND pin.
12
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It is also possible to use tantalum or film capacitors at the device output, but these are not as attractive for
reasons of size and cost (see Capacitor Characteristics).
The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR
value that is within the range 5 mΩ to 500 mΩ for stability.
8.2.2.5 No-Load Stability
The LP3990-Q1 remains stable and in regulation with no external load. This is an important consideration in
some circuits, for example CMOS RAM keep-alive applications.
8.2.2.6 Capacitor Characteristics
The LP3990-Q1 is designed to work with ceramic capacitors on the output to take advantage of the benefits they
offer. For capacitance values in the range of 0.47 µF to 4.7 µF, ceramic capacitors are the smallest, least
expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The
ESR of a typical 1-µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR
requirement for stability for the LP3990-Q1.
For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure
correct device operation. The capacitor value can change greatly, depending on the operating conditions and
capacitor type.
CAP VALUE (% of NOMINAL 1 PF)
In particular, the output capacitor selection must take account of all the capacitor parameters, to ensure that the
specification is met within the application. The capacitance can vary with DC bias conditions as well as
temperature and frequency of operation. Capacitor values also show some decrease over time due to aging. The
capacitor parameters are also dependant on the particular case size, with smaller sizes giving poorer
performance figures in general. As an example, Figure 14 shows a typical graph comparing different capacitor
case sizes in a Capacitance vs. DC Bias plot. As shown in Figure 14, increasing the DC Bias condition can result
in the capacitance value falling below the minimum value given in the recommended capacitor specifications
table (0.7 µF in this case). Note that the graph shows the capacitance out of spec for the 0402 case size
capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers’ specifications for
the nominal value capacitor are consulted for all conditions, as some capacitor sizes (for example, 0402) may not
be suitable in the actual application.
0603, 10V, X5R
100%
80%
60%
0402, 6.3V, X5R
40%
20%
0
1.0
2.0
3.0
4.0
5.0
DC BIAS (V)
Figure 14. Typical Variation In Capacitance vs DC Bias
Capacitance of the ceramic capacitor can vary with temperature. The capacitor type X7R, which operates over a
temperature range of –55°C to 125°C, only varies the capacitance to within ±15%. The capacitor type X5R has a
similar tolerance over a reduced temperature range of –55°C to 85°C. Many large value ceramic capacitors,
larger than 1 µF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance can drop by
more than 50% as the temperature varies from 25°C to 85°C. Therefore, X7R and X5R types are recommended
over Z5U and Y5V in applications where the ambient temperature changes significantly above or below 25°C.
Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more
expensive when comparing equivalent capacitance and voltage ratings in the 0.47-µF to 4.7-µF range.
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Another important consideration is that tantalum capacitors have higher ESR values than equivalent size
ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the
stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic
capacitor with the same ESR value. The ESR of a typical tantalum increases about 2:1 as the temperature goes
from 25°C down to –40°C, so some guard band must be allowed.
8.2.2.7 Enable Control
The LP3990-Q1 features an active high Enable pin, EN, which turns the device on when pulled high. When not
enabled the regulator output is off and the device typically consumes 2 nA.
If the application does not require the enable switching feature, the EN pin must be tied to VIN to keep the
regulator output permanently on.
To ensure proper operation, the signal source used to drive the EN input must be able to swing above and below
the specified turn-on/off voltage thresholds listed in the Electrical Characteristics section under VIL and VIH.
An internal 1-MΩ pull-down resistor ties the EN input to ground, ensuring that the device remains off if the EN pin
is left open circuit.
8.2.3 Application Curves
(500 mV/Div)
'VOUT
(50 mV/Div)
LOAD CURRENT
(mA)
VEN
CIN = 1 PF
COUT = 0.47 PF
(1V/Div)
VOUT
IL = 150 mA
TIME (50 Ps/DIV)
Figure 15. Enable Start-Up Time
150
1
TIME (20 Ps/DIV)
Figure 16. Load Transient
9 Power Supply Recommendations
This device is designed to operate from an input supply voltage range of 2 V to 6 V. The input supply must be
well regulated and free of spurious noise. To ensure that the LP3990-Q1 output voltage is well regulated, the
input supply must be at least VOUT + 0.5 V, or 2 V, whichever is higher. A minimum capacitor value of 1-μF is
required to be within 1 cm of the IN pin.
10 Layout
10.1 Layout Guidelines
The dynamic performance of the LP3990-Q1 is dependant on the layout of the PCB. PCB layout practices that
are adequate for typical LDOs may degrade the load regulation, PSRR, noise, or transient performance of the
LP3990-Q1.
Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP3990-Q1, and as
close to the package as is practical. The ground connections for CIN and COUT must be back to the LP3990-Q1
ground pin using as wide, short copper traces as is practical.
Connections using long trace lengths, narrow trace widths, or connections through vias must be avoided. These
add parasitic inductances and resistance that results in inferior performance especially during transient
conditions.
14
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Layout Guidelines (continued)
A Ground Plane, either on the opposite side of a two-layer PCB, or embedded in a multi-layer PCB, is strongly
recommended. This Ground Plane provides a circuit reference plane to assure accuracy.
10.2 Layout Example
VIN
VOUT
LP3990TL
B2
B1
COUT
CIN
A2
A1
Power Ground
VEN
Figure 17. LP3990-Q1 DSBGA Layout
10.3 DSBGA Mounting
The DSBGA package requires specific mounting techniques, which are detailed in TI Application Note DSBGA
Wafer Level Chip Scale Package (SNVA009).
For best results during assembly, alignment ordinals on the PC board may be used to facilitate placement of the
DSBGA device.
10.4 DSBGA Light Sensitivity
Exposing the DSBGA device to direct light may affect the operation of the device. Light sources, such as halogen
lamps, can affect electrical performance, if placed in close proximity to the device.
The wavelengths that have the most deterimental effect are reds and infra-reds, which means the fluorescent
lighting used inside most buildings has little effect on performance.
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
AN-1112 DSBGA Wafer Level Chip Scale Package (SNVA009)
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
LP3990QTLX-1.2Q1
ACTIVE
DSBGA
YZR
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
LP3990QTLX-1.8Q1
ACTIVE
DSBGA
YZR
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
LP3990QTLX-2.8Q1
ACTIVE
DSBGA
YZR
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
