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LP5012PWR

LP5012PWR

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    TSSOP24

  • 描述:

    12-CHANNEL I2C CONSTANT-CURRENT

  • 数据手册
  • 价格&库存
LP5012PWR 数据手册
LP5009, LP5012 LP5009, LP5012 SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 www.ti.com LP50xx 9-, 12-Channel, 12-Bit PWM Ultra-low Quiescent Current I2C RGB LED Drivers 1 Features 2 Applications • LED lighting, indicator lights, and fun lights for: • • • • • • • • Operating voltage range: – VCC range: 2.7 V to 5.5 V – EN, SDA, and SCL pins compatible with 1.8-V, 3.3-V, and 5-V power rails – Output maximum voltage: 6 V 12 Constant-current sinks with high precision – 25.5 mA Maximum per channel with VCC in full range – 35 mA Maximum per channel when VCC ≥ 3.3 V – Device-to-device error: ±5%; channel-tochannel error: ±5% Ultra-low quiescent current: – Shutdown mode: 1 µA (maximum) with EN low – Power-saving mode: 10 µA (typical) with EN high and all LEDs off for > 30 ms Integrated 12-bit, 29-kHz PWM generator for each channel: – Independent color-mixing register per channel – Independent brightness-control register per RGB LED module – Optional logarithmic- or linear-scale brightness control – Integrated 3-phase PWM-shifting scheme 3 Programmable banks (R, G, B) for easy software control of each color 2 External hardware address pins allow connecting up to 4 devices Broadcast slave address allows configuring multiple devices simultaneously Auto-increment allows writing or reading consecutive registers within one transmission Up to 400-kHz fast-mode I2C speed • • • • • • • • Smart speaker (with voice assistant) Smart home appliances Video doorbell Electronic smart lock Smoke and heat detector STB and DVR Smart router Handheld device 3 Description In smart homes and other applications that use human-machine-interaction, high-performance RGB LED drivers are required. LED animation effects such as flashing, breathing and chasing that greatly improves user experience, and minimal system noise is essential. The LP50xx device is an 9- or 12-channel constant current sink LED driver. The LP50xx device includes integrated color mixing and brightness control, and pre-configuration simplifies the software coding process. Integrated 12-bit, 29-kHz PWM generators for each channel enable smooth, vivid color for LEDs, and eliminate audible noise. Device Information PART NUMBER(1) LP5009 LP5012 LP5009 LP5012 (1) PACKAGE BODY SIZE (NOM) WQFN (20) 3.00 mm × 3.00 mm TSSOP (24) 7.80 mm × 4.40 mm For all available packages, see the orderable addendum at the end of the data sheet. VCC VMCU CVCC VLED VCC OUT0 EN OUT1 SDA SCL OUT2 ADDR0 MCU ADDR1 LP5012 OUT09 VCAP CVCAP OUT10 IREF RIREF GND OUT11 Simplified Schematic An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated intellectual property matters and other important disclaimers. PRODUCTION DATA. Product Folder Links: LP5009 LP5012 1 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Description (continued).................................................. 3 6 Pin Configuration and Functions...................................4 7 Specifications.................................................................. 7 7.1 Absolute Maximum Ratings........................................ 7 7.2 ESD Ratings............................................................... 7 7.3 Recommended Operating Conditions.........................7 7.4 Thermal Information....................................................7 7.5 Electrical Characteristics.............................................8 7.6 Timing Characteristics.................................................9 7.7 Typical Characteristics.............................................. 10 8 Detailed Description......................................................12 8.1 Overview................................................................... 12 8.2 Functional Block Diagram......................................... 12 8.3 Feature Description...................................................12 8.4 Device Functional Modes..........................................18 8.5 Programming............................................................ 19 8.6 Register Maps...........................................................23 9 Application and Implementation.................................. 35 9.1 Application Information............................................. 35 9.2 Typical Application.................................................... 35 10 Power Supply Recommendations..............................37 11 Layout........................................................................... 37 11.1 Layout Guidelines................................................... 37 11.2 Layout Examples.....................................................38 12 Device and Documentation Support..........................40 12.1 Related Links.......................................................... 40 12.2 Receiving Notification of Documentation Updates..40 12.3 Support Resources................................................. 40 12.4 Trademarks............................................................. 40 12.5 Electrostatic Discharge Caution..............................40 12.6 Glossary..................................................................40 13 Mechanical, Packaging, and Orderable Information.................................................................... 40 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (July 2019) to Revision B (August 2020) Page • Updated the numbering format for tables, figures and cross-references throughout the document...................1 • Added PW package option to data sheet .......................................................................................................... 1 Changes from Revision * (May 2019) to Revision A (July 2019) Page • Changed from Advance Information to Production Data ................................................................................... 1 2 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 5 Description (continued) The LP50xx device controls each LED output with a 12-bit PWM resolution at 29-kHz switching frequency, which helps achieve a smooth dimming effect and eliminates audible noise. The independent color mixing and intensity control registers make the software coding straightforward. When targeting a fade-in, fade-out type breathing effect, the global R, G, B bank control reduces the microcontroller loading significantly. The LP50xx device also implements a PWM phase-shifting function to help reduce the input power budget when LEDs turn on simultaneously. The LP50xx device implements an automatic power-saving mode to achieve ultra-low quiescent current. When channels are all off for 30 ms, the device total power consumption is down to 10 µA, which makes the LP50xx device a potential choice for battery-powered end equipment. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 3 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 IREF EN SCL SDA VCC 20 19 18 17 16 6 Pin Configuration and Functions VCAP 1 15 ADDR1 OUT0 2 14 ADDR0 OUT1 3 13 NC Thermal Pad 9 10 OUT8 NC OUT7 11 8 5 OUT6 OUT3 7 NC OUT5 12 6 4 OUT4 OUT2 Not to scale VCAP 1 OUT0 2 OUT1 IREF EN SCL SDA VCC 20 19 18 17 16 Figure 6-1. LP5009 RUK Package 20-Pin WQFN With Exposed Thermal Pad Top View Thermal 3 15 ADDR1 14 ADDR0 13 OUT11 Pad 9 10 OUT8 OUT9 OUT7 11 8 5 OUT6 OUT3 7 OUT10 OUT5 12 6 4 OUT4 OUT2 Not to scale Figure 6-2. LP5012 RUK Package 20-Pin WQFN With Exposed Thermal Pad Top View 4 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 ADDR0 1 24 NC AGND 2 23 NC ADDR1 3 22 NC VCC 4 21 OUT8 SDA 5 20 OUT7 PGND 6 19 OUT6 SCL 7 18 DGND EN 8 17 OUT5 IREF 9 16 OUT4 VCAP 10 15 OUT3 NC 11 14 OUT2 OUT0 12 13 OUT1 Figure 6-3. LP5009 PW Package 24-Pin TSSOP Top View ADDR0 1 24 OUT11 AGND 2 23 OUT10 ADDR1 3 22 OUT9 VCC 4 21 OUT8 SDA 5 20 OUT7 PGND 6 19 OUT6 SCL 7 18 DGND EN 8 17 OUT5 IREF 9 16 OUT4 VCAP 10 15 OUT3 NC 11 14 OUT2 OUT0 12 13 OUT1 Figure 6-4. LP5012 PW Package 24-Pin TSSOP Top View Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 5 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 Pin Functions PIN RUK NO. NAME I/O DESCRIPTION LP5009 LP5012 LP5009 LP5012 ADDR0 14 14 1 1 — I2C slave-address selection pin. This pin must not be left floating. ADDR1 15 15 3 3 — I2C slave-address selection pin. This pin must not be left floating. EN 19 19 8 8 I IREF 20 20 9 9 — Output current-reference global-setting pin. 11, 12, 13 — 22, 23, 24 — — No internal connection. OUT0 2 2 12 12 O Current sink output 0. If not used, this pin can be left floating. OUT1 3 3 13 13 O Current sink output 1. If not used, this pin can be left floating. OUT2 4 4 14 14 O Current sink output 2. If not used, this pin can be left floating. OUT3 5 5 15 15 O Current sink output 3. If not used, this pin can be left floating. OUT4 6 6 16 16 O Current sink output 4. If not used, this pin can be left floating. OUT5 7 7 17 17 O Current sink output 5. If not used, this pin can be left floating. OUT6 8 8 19 19 O Current sink output 6. If not used, this pin can be left floating. OUT7 9 9 20 20 O Current sink output 7. If not used, this pin can be left floating. OUT8 10 10 21 21 O Current sink output 8. If not used, this pin can be left floating. OUT9 — 11 — 22 O Current sink output 9. If not used, this pin can be left floating. OUT10 — 12 — 23 O Current sink output 10. If not used, this pin can be left floating. OUT11 — 13 — 24 O Current sink output 11. If not used, this pin can be left floating. SCL 18 18 7 7 I I2C bus clock line. If not used, this pin must be connected to GND or VCC. SDA 17 17 5 5 I/O I2C bus data line. If not used, this pin must be connected to GND or VCC. VCAP 1 1 10 10 — Internal LDO output pin, this pin must be connected to a 1-µF capacitor to GND. Place the capacitor as close to the device as possible. VCC 16 16 4 4 — Power supply. GND Thermal pad Thermal pad — — — Exposed thermal pad also serves the ground pin for the WQFN package. AGND — — 2 2 — Analog circuits ground. AGND, PGND and DGND must be conntected together. PGND — — 6 6 — Power ground. AGND, PGND and DGND must be conntected together. DGND — — 18 18 — Digital circuits ground. AGND, PGND and DGND must be conntected together. NC 6 PW NO. Chip enable input pin. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 7 Specifications 7.1 Absolute Maximum Ratings over operating ambient temperature range (unless otherwise noted)(1) MIN MAX Voltage on EN, IREF, OUTx, SCL, SDA, VCC –0.3 6 V Voltage on ADDRx –0.3 VCC + 0.3 V –0.3 2 V Voltage on VCAP Continuous power dissipation UNIT Internally limited Junction temperature, TJ-MAX –40 125 °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. 7.3 Recommended Operating Conditions over operating ambient temperature range (unless otherwise noted) MIN MAX 2.7 5.5 V Voltage on OUTx 0 5.5 V Voltage on ADDRx, EN, SDA, SCL 0 5.5 V Operating ambient temperature, TA –40 85 °C Input voltage on VCC UNIT 7.4 Thermal Information LP5009 or LP5012 THERMAL METRIC(1) RUK (QFN) PW (TSSOP) 20 PINS 24 Pins UNIT RθJA Junction-to-ambient thermal resistance 53.7 98.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 55.3 41.5 °C/W RθJB Junction-to-board thermal resistance 27.4 53.5 °C/W ψJT Junction-to-top characterization parameter 1.9 5.0 °C/W ψJB Junction-to-board characterization parameter 27.4 53.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 12.9 n/a °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 7 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 7.5 Electrical Characteristics over operating ambient temperature range (–40°C < TA< 85°C) (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VCC) VVCC Supply voltage 2.7 VEN = 0 V Standby supply current 5.5 V 0.2 1 VEN = 3.3 V, Chip_EN = 0 (bit) 6 10 Normal-mode supply current With 10-mA LED current per OUTx 4 6 mA Power-save mode supply current VEN = 3.3 V, Chip_EN = 1 (bit), Power_Save_EN = 1 (bit), all the LEDs off duration > tPSM 6 10 µA VUVR Undervoltage restart VVCC rising 2.5 V VUVF Undervoltage shutdown VVCC falling VUV_HYS Undervoltage shutdown hysteresis IVCC Shutdown supply current 2 µA V 0.2 V OUTPUT STAGE (OUTx) Maximum sink current (OUT0–OUTx) (For VVCC in full range, Max_Current_Option = LP5012, x = 11. For LP5009, x = 8.) 0 (bit), PWM = 100% IMAX mA Maximum sink current (OUT0–OUTx) (For VVCC ≥ 3.3 V, Max_Current_Option = 1 LP5012, x = 11. For LP5009, x = 8.) (bit), PWM = 100% 35 Internal sink current limit (OUT0–OUTx) (For LP5012, x = 11. For LP5009, x = 8.) VVCC in full range, Max_Current_Option = 0 (bit), VIREF = 0 V 35 55 85 Internal sink current limit (OUT0–OUTx) (For LP5012, x = 11. For LP5009, x = 8.) VVCC ≥ 3.3V, Max_Current_Option=1 (bit), VIREF = 0 V 40 75 120 Ilkg Leakage current (OUT0–OUTx) (For LP5012, x = 11. For LP5009, x = 8.) PWM = 0% 0.1 1 IERR_DD Device to device current error, IERR_DD = (IAVE - ISET)/ISET × 100% Channels' current are set to 10 mA. PWM = 100% at 25°C. Already includes the VIREF and KIREF tolerance –5% 5% IERR_CC Channel to channel current error, IERR_CC = (IOUTX - IAVE)/IAVE × 100% Channels' current are set to 10 mA. PWM = 100% at 25°C. Already includes the VIREF and KIREF tolerance –5% 5% ILIM mA VIREF IREF voltage 0.7 KIREF IREF ratio 105 ƒPWM PWM switching frequency VSAT 8 25.5 Output saturation voltage 21 VVCC in full range, Max_Current_Option = 0 (bit), output current set to 20 mA, the voltage when the LED current has dropped 5% VVCC ≥ 3.3 V, Max_Current_Option = 1 (bit), output current set to 20 mA, the voltage when the LED current has dropped 5% Submit Document Feedback V 29 0.25 µA kHz 0.35 V 0.3 0.4 Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 7.5 Electrical Characteristics (continued) over operating ambient temperature range (–40°C < TA< 85°C) (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LOGIC INPUTS (EN, SCL, SDA, ADDRx) VIL Low level input voltage VIH High level input voltage 1.4 ILOGIC Input current –1 VSDA SDA output low level 0.4 V 1 µA 0.4 V V IPULLUP = 5 mA PROTECTION CIRCUITS T(TSD) Thermal-shutdown junction temperature T(HYS) Thermal shutdown temperature hysteresis 160 °C 15 °C 7.6 Timing Characteristics over operating ambient temperature range (-40°C < TA< 85°C) (unless otherwise noted) PARAMETER MIN ƒOSC Internal oscillator frequency tPSM Power save mode deglitch time tEN_H EN first rising edge until first I2C access tEN_L EN first falling edge until first ƒSCL I2C clock frequency TYP MAX 15 I2C 20 reset 30 UNIT MHz 40 ms 500 µs 3 400 µs kHz 1 Hold time (repeated) START condition 0.6 µs 2 Clock low time 1.3 µs 3 Clock high time 600 ns 4 Setup time for a repeated START condition 600 ns 5 Data hold time 6 Data setup time 7 Rise time of SDA and SCL 20 + 0.1 Cb 300 ns 8 Fall time of SDA and SCL 15 + 0.1 Cb 300 ns 9 Setup time for STOP condition 600 ns 10 Bus free time between a STOP and a START condition 1.3 µs Cb Capacitive load parameter for each bus line Load of 1 pF corresponds to one nanosecond. 10 0 ns 100 ns 200 pF Figure 7-1. I2C Timing Parameters Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 9 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 35 32.5 30 27.5 25 22.5 20 17.5 15 12.5 10 7.5 5 2.5 0 40 35 Output Current (mA) Output Current (mA) 7.7 Typical Characteristics 30 25 5mA-Average Current 10mA-Average Current 25.5mA-Average Current 35mA-Average Current 20 15 10 5 0 5 0 -40 -30 -20 -10 10 15 20 25 30 35 40 45 50 55 60 65 70 RIREF(k:) D005 Figure 7-2. IOUT Target vs RIREF 0 10 20 30 40 50 60 70 80 90 Ambient Temperature (°C) D001 VCC = 3.3 V Figure 7-3. Output Current vs Temperature 40 2 35 1.6 Max in 5mA Min in 5mA Max in 10mA Min in 10mA Max in 25.5mA Min in 25.5mA 0.8 25 5mA-Average Current 10mA-Average Current 25.5mA-Average Current 35mA-Average Current 20 15 Accuracy (%) Output Current (mA) 1.2 30 0.4 0 -0.4 -0.8 10 -1.2 5 -1.6 0 -40 -30 -20 -10 VCC = 5 V 0.055 0.05 1.2 0.045 0.4 Max in 5mA Min in 5mA Max in 10mA Min in 10mA Max in 25.5mA Min in 25.5mA -0.4 -0.8 Output Current (A) 2 0.8 Accuracy (%) Figure 7-5. Channel-to-Channel Current Accuracy 1.6 0 0 10 20 30 40 50 60 70 80 90 Ambient Temperature (°C) D003 VCC = 3.3 V Figure 7-4. Output Current vs Temperature 50-PA IREF 100-PA IREF 150-PA IREF 200-PA IREF 250-PA IREF 300-PA IREF 350-PA IREF 0.04 0.035 0.03 0.025 0.02 0.015 -1.2 0.01 -1.6 0.005 -2 -40 -30 -20 -10 0 0 10 20 30 40 50 60 70 80 90 Ambient Temperature (°C) D004 VCC = 5 V 0 0.25 0.5 0.75 1 1.25 1.5 1.75 Output Pin Voltage (V) 2 2.25 2.5 D006 VCC = 3.3 V Figure 7-6. Channel-to-Channel Current Accuracy vs Temperature 10 -2 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Ambient Temperature (°C) D002 Figure 7-7. OUT Pin Voltage vs Current Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 0.055 50-PA IREF 100-PA IREF 150-PA IREF 0.05 Output Current (A) 0.045 200-PA IREF 250-PA IREF 300-PA IREF 350-PA IREF 0.04 0.035 0.03 0.025 0.02 0.015 0.01 0.005 0 0 0.25 0.5 0.75 1 1.25 1.5 1.75 Output Pin Voltage (V) 2 2.25 2.5 D007 VCC = 5 V Figure 7-8. OUT Pin Voltage vs Output Current Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 11 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 8 Detailed Description 8.1 Overview The LP50xx device is an 9- or 12-channel constant-current-sink LED driver. The LP50xx device includes all necessary power rails, an on-chip oscillator, and a two-wire serial I2C interface. The maximum constant-current value of all channels is set by a single external resistor. Two hardware address pins allow up to four devices on the same bus. An automatic power-saving mode is implemented to keep the total current consumption under 10 µA, which makes the LP50xx device a potential choice for battery-powered end equipment. The LP50xx device is optimized for RGB LEDs regarding both live effects and software efforts. The LP50xx device controls each LED output with 12-bit PWM resolution at 29-kHz switching frequency, which helps achieve a smooth dimming effect and eliminates audible noise. The independent color-mixing and intensity-control registers make the software coding straightforward. When targeting a fade-in, fade-out type breathing effect, the global RGB bank control reduces the microcontroller loading significantly. The LP50xx device also implements a PWM phase-shifting function to help reduce the input power budget when LEDs turn on simultaneously. 8.2 Functional Block Diagram VCC VLED VCC Bandgap OUT0 OUT1 V1P8 LDO VCAP Oscillator 15MHz EN 12 Bits 29 kHz PWM Generators SDA SCL OUT2 OUT9 Digital Interface Digital Control OUT10 ADDR0 ADDR1 IREF OUT11 IREF Setting Current GND Thermal Shutdown 8.3 Feature Description 8.3.1 PWM Control for Each Channel Most traditional LED drivers are designed for the single-color LEDs, in which the high-resolution PWM generator is used for intensity control only. However, for RGB LEDs, both the color mixing and intensity control must be addressed to achieve the target effect. With the traditional solution, the users must handle the color mixing and intensity control simultaneously with a single PWM register. Several undesired effects occur: the limited dimming steps, the complex software design and the color distortion when using a logarithmic scale control. The LP50xx device is designed with independent color mixing and intensity control, which makes the RGB LED effects fancy and the control experience straightforward. With the inputs of the color-mixing register and the intensity-control register, the final PWM generator output for each channel is 12-bit resolution and 29-kHz dimming frequency, which helps achieve a smooth dimming effect and eliminates audible noise. See Figure 8-1. 12 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 LP5009, LP5012 www.ti.com Color-Mixing SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 Brightness-Control PWM Generators 12 Bits / 29KHz PWM OUT0 12 Bits / 29KHz PWM OUT1 8 Bits Color 12 Bits / 29KHz PWM OUT2 8 Bits Color 12 Bits / 29KHz PWM OUT9 12 Bits / 29KHz PWM OUT10 12 Bits / 29KHz PWM OUT11 8 Bits Color 8 Bits Color 8 Bits Color 8 Bits Brightness 8 Bits Brightness 8 Bits Color Figure 8-1. PWM Control Scheme for Each Channel 8.3.1.1 Independent Color Mixing Per RGB LED Module Each output channel has its own individual 8-bit color-setting register (OUTx_COLOR). The device allows every RGB LED module to achieve >16 million (256 × 256 × 256) color-mixing. 8.3.1.2 Independent Intensity Control Per RGB LED Module When color is fixed, the independent intensity-control is used to achieve accurate and flexible dimming control for every RGB LED module. 8.3.1.2.1 Intensity-Control Register Configuration Every three consecutive output channels are assigned to their respective intensity-control register (LEDx_BRIGHTNESS). For example, OUT0, OUT1, and OUT2 are assigned to LED0_BRIGHTNESS, so it is recommended to connect the RGB LEDs in the sequence as shown in Table 8-1. The LP50xx device allows 256step intensity control for each RGB LED module, which helps achieve a smooth dimming effect. Keeping FFh (default value) in the LED0_BRIGHTNESS register results in 100% dimming duty cycle. With this setting, users can just configure the color mixing register by channel to achieve the target dimming effect in a single-color LED application. 8.3.1.2.2 Logarithmic- or Linear-Scale Intensity Control For human-eye-friendly visual performance, a logarithmic-scale dimming curve is usually implemented in LED drivers. However, for RGB LEDs, if using a single register to achieve both color mixing and intensity control, color distortion can be observed easily when using a logarithmic scale. The LP50xx device, with independent color-mixing and intensity-control registers, implements the logarithmic scale dimming control inside the intensity control function, which solves the color distortion issue effectively. See Figure 8-2. Also, the LP50xx device allows users to configure the dimming scale either logarithmically or linearly through the global Log_Scale_EN register. If a special dimming curve is desired, using the linear scale with software correction is the most flexible approach. See Figure 8-3. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 13 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 Brightness Control 8 Bits Brightness Linear OR Logarithmic Log_Scale_EN 8 Bits Brightness Linear OR Logarithmic Figure 8-2. Logarithmic- or Linear-Scale Intensity Control Logarithmic Scale Dimming Curve 100% 80% 80% PWM Output Duty PWM Output Duty Linear Scale Dimming Curve 100% 60% 40% 20% 60% 40% 20% 0% 0% 0 32 64 96 128 160 192 224 255 0 32 LEDx_BRIGHTNESS Register Input 64 96 128 160 192 224 255 LEDx_BRIGHTNESS Register Input Figure 8-3. Logarithmic vs Linear Dimming Curve 8.3.1.3 12-Bit, 29-kHz PWM Generator Per Channel 8.3.1.3.1 PWM Generator With the inputs of the color mixing and the intensity control, the final output PWM duty cycle is defined as the product obtained by multiplying the color-mixing register value by the related intensity-control register value. The final output PWM duty cycle has 12 bits of control accuracy, which is achieved by a 9 bits of pure PWM resolution and 3 bits of digital dithering control. For 3-bit dithering, every eighth pulse is made 1 LSB longer to increase the average value by 1 / 8th. The LP50xx device allows users to enable or disable the dithering function through the PWM_Dithering_EN register. When enabled (default), the output PWM duty-cycle accuracy is 12 bits. When disabled, the output PWM duty-cycle accuracy is 9 bits. To eliminate the audible noise due to the PWM switching, the LP50xx device sets the PWM switching frequency at 29 kHz, above the 20-kHz human hearing range. 8.3.1.4 PWM Phase-Shifting A PWM phase-shifting scheme allows delaying the time when each LED driver is active. When the LED drivers are not activated simultaneously, the peak load current from the pre-stage power supply is significantly 14 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 decreased. The scheme also reduces input-current ripple and ceramic-capacitor audible ringing. LED drivers are grouped into three different phases. • • • Phase 1—the rising edge of the PWM pulse is fixed. The falling edge of the pulse is changed when the duty cycle changes. Phase 1 is applied to LED0, LED3, LED6, LED9. Phase 2—the middle point of the PWM pulse is fixed. The pulse spreads in both directions when the PWM duty cycle is increased. Phase 2 is applied to LED1, LED4, LED7, LED10. Phase 3—the falling edge of the PWM pulse is fixed. The rising edge of the pulse is changed when the duty cycle changes. Phase 3 is applied to LED2, LED5, LED8, LED11. Cycle Time LED0 Phase 1 LED3 LED9 LED1 Phase 2 LED4 LED10 LED2 Phase 3 LED5 LED11 Phase 1 Phase 2 Phase 3 Figure 8-4. PWM Phase-Shifting 8.3.2 LED Bank Control For most LED-animation effects, like blinking and breathing, all the RGB LEDs have the same lighting pattern. Instead of controlling the individual LED separately, which occupies the microcontroller resources heavily, the LP50xx device provides an easy coding approach, the LED bank control. Each channel can be configured as either independent control or bank control through the LEDx_Bank_EN register. When LEDx_Bank_EN = 0 (default), the LED is controlled independently by the related color-mixing and intensity-control registers. When LEDx_Bank_EN = 1, the LP50xx device drives the LEDs in LED bank-control mode. The LED bank has its own independent PWM control scheme, which is the same structure as the PWM scheme of each channel. See PWM Control for Each Channel for more details. When a channel is configured in LED bank-control mode, the related color mixing and intensity control is governed by the bank control registers (BANK_A_COLOR, BANK_B_COLOR, BANK_C_COLOR, and BANK_BRIGHTNESS) regardless of the inputs on its own color-mixing and intensity-control registers. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 15 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 Bank Color-Mixing Bank A: 8 Bits Color Bank B: 8 Bits Color Bank C: 8 Bits Color Bank Brightness-Control Bank PWM Generators 12 Bits / 29kHz PWM 8 Bits Brightness 12 Bits / 29kHz PWM 12 Bits / 29kHz PWM Figure 8-5. Bank PWM Control Scheme Table 8-1. Bank Number and LED Number Assignment OUT NUMBER BANK NUMBER OUT0 Bank A OUT1 Bank B OUT2 Bank C OUT3 Bank A OUT4 Bank B OUT5 Bank C OUT6 Bank A OUT7 Bank B OUT8 Bank C OUT9 (LP5012 only) Bank A OUT10 (LP5012 only) Bank B OUT11 (LP5012 only) Bank C RGB LED MODULE NUMBER LED0 LED1 LED2 LED3 With the bank control configuration, the LP50xx device enables users to achieve smooth and live LED effects globally with an ultrasimple software effort. Figure 8-6 shows an example using LED0 as an independent RGB indicator and others with group breathing effect. Bank A CH3/6/9 Independent CH0/1/2 Bank B CH4/7/10 Bank C CH5/8/11 Figure 8-6. Bank PWM Control Example 16 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 8.3.3 Current Range Setting The constant-current value (ISET) of all 12 channels is set by a single external resistor, RIREF. The value of RIREF can be calculated by Equation 1. RIREF KIREF u VIREF ISET (1) where: • • KIREF = 105 VIREF = 0.7 V With the IREF pin floating, the output current is close to zero. With the IREF pin shorted to GND, the LP50xx device provides internal current-limit protection, and the output-channel maximum current is limited to ILIM. The LP50xx device supports two levels of maximum output current, IMAX. • • When VCC is in the range from 2.7 V to 5.5 V, and the Max_Current_Option (bit) = 0, IMAX = 25.5 mA. When VCC is in the range from 3.3 V to 5.5 V, and the Max_Current_Option (bit) = 1, IMAX = 35 mA. 8.3.4 Automatic Power-Save Mode When all the LED outputs are inactive, the LP50xx device is able to enter power-save mode automatically, thus lowering idle-current consumption down to 10 μA (typical). Automatic power-save mode is enabled when register bit Power_Save_EN = 1 (default) and all the LEDs are off for a duration of > 30 ms. Almost all analog blocks are powered down in power-save mode. If any I2C command to the device occurs, the LP50xx device returns to NORMAL mode. 8.3.5 Protection Features 8.3.5.1 Thermal Shutdown The LP50xx device implements a thermal shutdown mechanism to protect the device from damage due to overheating. When the junction temperature rises to 160°C (typical), the device switches into shutdown mode. The LP50xx device releases thermal shutdown when the junction temperature of the device is reduced to 145°C (typical). 8.3.5.2 UVLO The LP50xx device has an internal comparator that monitors the voltage at VCC. When VCC is below VUVF, reset is active and the LP50xx device is in the INITIALIZATION state. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 17 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 8.4 Device Functional Modes VCC Power Up EN = L SHUTDOWN From all states EN = H RESET = FF or UVLO = H From all states INITIALIZATION STANDBY Chip_EN = 1 Chip_EN = 0 TSD=H I2C Command POWER SAVE THERMAL SHUTDOWN NORMAL Power_Save_EN =1 and All LEDs off > 30ms TSD=L Figure 8-7. Functional Modes • • • • • • 18 INITIALIZATION: The device enters into INITIALIZATION mode when EN = H. In this mode, all the registers are reset. Entry can also be from any state, if the RESET (register) = FFh or UVLO is active. NORMAL: The device enters the NORMAL mode when Chip_EN (register) = 1. ICC is 10 mA (typical). POWER SAVE: The device automatically enters the POWER SAVE mode when Power_Save_EN (register) = 1 and all the LEDs are off for a duration of > 30 ms. In POWER SAVE mode, analog blocks are disabled to minimize power consumption, but the registers retain the data and keep it available via I2C. ICC is 10 µA (typical). In case of any I2C command to this device, it returns to the NORMAL mode. SHUTDOWN: The device enters into SHUTDOWN mode from all states on VCC power up or when EN = L. ICC is < 1 µA (maximum). STANDBY: The device enters the STANDBY mode when Chip_EN (register) = 0. In this mode, all the OUTx pins are shut down, but the registers retain the data and keep it available via I2C. STANDBY is the lowpower-consumption mode, when all circuit functions are disabled. ICC is 10 µA (typical). THERMAL SHUTDOWN: The device automatically enters the THERMAL SHUTDOWN mode when the junction temperature exceeds 160°C (typical). In this mode, all the OUTx outputs are shut down. If the junction temperature decreases below 145°C (typical), the device returns to the NORMAL mode. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 8.5 Programming 8.5.1 I2C Interface The I2C-compatible two-wire serial interface provides access to the programmable functions and registers on the device. This protocol uses a two-wire interface for bidirectional communications between the devices connected to the bus. The two interface lines are the serial data line (SDA) and the serial clock line (SCL). Every device on the bus is assigned a unique address and acts as either a master or a slave depending on whether it generates or receives the serial clock, SCL. The SCL and SDA lines must each have a pullup resistor placed somewhere on the line and remain HIGH even when the bus is idle. 8.5.1.1 Data Validity The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the state of the data line can only be changed when the clock signal is LOW. SDA SCL Data Li ne Stable; Data V alid Chang e of Data Allo wed Figure 8-8. Data Validity 8.5.1.2 Start and Stop Conditions START and STOP conditions classify the beginning and the end of the data transfer session. A START condition is defined as the SDA signal transitioning from HIGH to LOW while the SCL line is HIGH. A STOP condition is defined as the SDA transitioning from LOW to HIGH while SCL is HIGH. The bus master always generates START and STOP conditions. The bus is considered to be busy after a START condition and free after a STOP condition. During data transmission, the bus master can generate repeated START conditions. First START and repeated START conditions are functionally equivalent. SDA SCL S P Start Cond itio n Stop Condition Figure 8-9. Start and Stop Conditions Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 19 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 8.5.1.3 Transferring Data Every byte put on the SDA line must be eight bits long, with the most-significant bit (MSB) being transferred first. Each byte of data must be followed by an acknowledge bit. The acknowledge-related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The device pulls down the SDA line during the ninth clock pulse, signifying an acknowledge. The device generates an acknowledge after each byte has been received. There is one exception to the acknowledge-after-every-byte rule. When the master is the receiver, it must indicate to the transmitter an end of data by not acknowledging (negative acknowledge) the last byte clocked out of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down. After the START condition, the bus master sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE, and a 1 indicates a READ. The second byte selects the register to which the data is written. The third byte contains data to write to the selected register. Data O utp ut by Tran smitte r NACK Data O utp ut by Tran smitte r ACK SCL Fr om Master 1 2 8 Start Condition 9 Clock Pulse fo r Acknowledgment Figure 8-10. Acknowledge and Not Acknowledge on I2C Bus 8.5.1.4 I2C Slave Addressing The device slave address is defined by connecting GND or VCC to the ADDR0 and ADDR1 pins. A total of four independent slave addresses can be realized by combinations when GND or VCC is connected to the ADDR0 and ADDR1 pins (see Table 8-2 and Table 8-3). The device responds to a broadcast slave address regardless of the setting of the ADDR0 and ADDR1 pins. Global writes to the broadcast address can be used for configuring all devices simultaneously. The device supports global read using a broadcast address; however, the data read is only valid if all devices on the I2C bus contain the same value in the addressed register. 20 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 Table 8-2. Slave-Address Combinations SLAVE ADDRESS ADDR1 ADDR0 GND GND 0010100 GND VCC 0010101 VCC GND 0010110 VCC VCC 0010111 INDEPENDENT BROADCAST 0001100 Table 8-3. Chip Address SLAVE ADDRESS Bit 7 Bit 6 Bit 5 Bit 4 R/ W Bit 3 Bit 2 Bit 1 Bit 0 Independent 0 0 1 0 1 ADDR1 ADDR0 1 or 0 Broadcast 0 0 0 1 1 0 0 1 or 0 8.5.1.5 Control-Register Write Cycle • • • • • • • • • The master device generates a start condition. The master device sends the slave address (7 bits) and the data direction bit (R/ W = 0). The slave device sends an acknowledge signal if the slave address is correct. The master device sends the control register address (8 bits). The slave device sends an acknowledge signal. The master device sends the data byte to be written to the addressed register. The slave device sends an acknowledge signal. If the master device sends further data bytes, the control register address of the slave is incremented by 1 after the acknowledge signal. To reduce program load time, the device supports address auto incrementation. The register address is incremented after each 8 data bits. The write cycle ends when the master device creates a stop condition. ack from slave star t ack from slave MSB Chip Addr LSB w ack MSB Register Ad dr L SB ack ack from slave MSB Data L SB ack stop Figure 8-11. Write Cycle 8.5.1.6 Control-Register Read Cycle • • • • • • • • • • • The master device generates a start condition. The master device sends the slave address (7 bits) and the data direction bit (R/ W = 0). The slave device sends an acknowledge signal if the slave address is correct. The master device sends the control register address (8 bits). The slave device sends an acknowledge signal. The master device generates a repeated-start condition. The master device sends the slave address (7 bits) and the data direction bit (R/ W = 1). The slave device sends an acknowledge signal if the slave address is correct. The slave device sends the data byte from the addressed register. If the master device sends an acknowledge signal, the control-register address is incremented by 1. The slave device sends the data byte from the addressed register. To reduce program load time, the device supports address auto incrementation. The register address is incremented after each 8 data bits. The read cycle ends when the master device does not generate an acknowledge signal after a data byte and generates a stop condition. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 21 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 ack from slave star t MSB Chip Addr LSB w ack from slave repeated start MSB Register Addr LSB rs ack from slave MSB Chip Addr LSB r data from slave nack from master MSB Data L SB stop Figure 8-12. Read Cycle 8.5.1.7 Auto-Increment Feature The auto-increment feature allows writing or reading several consecutive registers within one transmission. For example, when an 8-bit word is sent to the device, the internal address index counter is incremented by 1, and the next register is written. The auto-increment feature is enabled by default and can be disabled by setting the Auto_Incr_EN bit = 0 in the DEVICE_CONFIG1 register. The auto-increment feature is applied for the full register address from 0h to FFh. 22 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 8.6 Register Maps Table 8-4 lists the memory-mapped registers of the device. Table 8-4. Register Maps REGISTER NAME ADDR TYPE D7 D6 DEVICE_ CONFIG0 00h R/ W RESERVED Chip_EN DEVICE_ CONFIG1 01h R/ W LED_CONFIG0 02h R/ W BANK_ BRIGHTNESS 03h R/ W Bank_Brightness FFh BANK_A_ COLOR 04h R/ W Bank_A_Color 00h BANK_B_ COLOR 05h R/ W Bank_B_Color 00h BANK_C_ COLOR 06h R/ W Bank_C_Color 00h LED0_ BRIGHTNESS 07h R/ W LED0_Brightness FFh LED1_ BRIGHTNESS 08h R/ W LED1_Brightness FFh LED2_ BRIGHTNESS 09h R/ W LED2_Brightness FFh LED3_ BRIGHTNESS 0Ah R/ W LED3_Brightness (Only for LP5012) FFh OUT0_COLOR 0Bh R/ W OUT0_Color 00h OUT1_COLOR 0Ch R/ W OUT1_Color 00h OUT2_COLOR 0Dh R/ W OUT2_Color 00h OUT3_COLOR 0Eh R/ W OUT3_Color 00h OUT4_COLOR 0Fh R/ W OUT4_Color 00h OUT5_COLOR 10h R/ W OUT5_Color 00h OUT6_COLOR 11h R/ W OUT6_Color 00h OUT7_COLOR 12h R/ W OUT7_Color 00h OUT8_COLOR 13h R/ W OUT8_Color 00h RESERVED D5 D4 D3 D2 D1 D0 RESERVED Log_Scale_EN RESERVED Power_Save_ EN Auto_Incr_EN PWM_ Dithering_EN DEFAULT 00h Max_Current_ Option LED_Global Off 3Ch LED3_Bank_EN (Only for LED2_Bank_EN LED1_Bank_EN LED0_Bank_EN LP5012) 00h Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 23 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 Table 8-4. Register Maps (continued) REGISTER NAME ADDR TYPE OUT9_COLOR 14h R/ W OUT9_Color (Only for LP5012) 00h OUT10_COLOR 15h R/ W OUT10_Color (Only for LP5012) 00h OUT11_COLOR 16h R/ W OUT11_Color (Only for LP5012) 00h RESET 17h W Reset 00h 24 D7 D6 D5 D4 D3 Submit Document Feedback D2 D1 D0 DEFAULT Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 Table 8-5. Access Type Codes ACCESS TYPE CODE DESCRIPTION Read Type R R Read W Write Write Type W Reset or Default Value Value after reset or the default value -n 8.6.1 DEVICE_CONFIG0 (Address = 0h) [reset = 0h] DEVICE_CONFIG0 is shown in Figure 8-13 and described in Table 8-6. Return to Table 8-4. Figure 8-13. DEVICE_CONFIG0 Register 7 6 5 4 3 2 RESERVED Chip_EN RESERVED R/ W-0h R/ W-0h R/ W-0h 1 0 1 0 Table 8-6. DEVICE_CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/ W 0h Reserved 6 Chip_EN R/ W 0h 1 = LP50xx enabled 0 = LP50xx not enabled RESERVED R/ W 0h Reserved 5–0 8.6.2 DEVICE_CONFIG1 (Address = 1h) [reset = 3Ch] DEVICE_CONFIG1 is shown in Figure 8-14 and described in Table 8-7. Return to Table 8-4. Figure 8-14. DEVICE_CONFIG1 Register 7 6 5 4 RESERVED Log_Scale_EN Power_Save_E N 3 Auto_Incr_EN R/ W-0h R/ W-1h R/ W-1h R/ W-1h 2 PWM_Dithering Optional_Headr LED_Global Off _EN oom R/ W-1h R/ W-0h R/ W-0h Table 8-7. DEVICE_CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7–6 RESERVED R/ W 0h Reserved 5 Log_Scale_EN R/ W 1h 1 = Logarithmic scale dimming curve enabled 0 = Linear scale dimming curve enabled 4 Power_Save_EN R/ W 1h 1 = Automatic power-saving mode enabled 0 = Automatic power-saving mode not enabled 3 Auto_Incr_EN R/ W 1h 1 = Automatic increment mode enabled 0 = Automatic increment mode not enabled 2 PWM_Dithering_EN R/ W 1h 1 = PWM dithering mode enabled 0 = PWM dithering mode not enabled 1 Max_Current_Option R/ W 0h 1 = Output maximum current IMAX = 35 mA. 0 = Output maximum current IMAX = 25.5 mA. 0 LED_Global Off R/ W 0h 1 = Shut down all LEDs 0 = Normal operation Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 25 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 8.6.3 LED_CONFIG0 (Address = 2h) [reset = 00h] LED_CONFIG0 is shown in Figure 8-15 and described in Table 8-8. Return to Table 8-4. Figure 8-15. LED_CONFIG0 Register 7 6 5 4 3 2 1 0 LED0_Bank_E LED3_Bank_EN LED2_Bank_EN LED1_Bank_EN N RESERVED R/ W-0h R/ W-0h R/ W-0h R/ W-0h R/ W-0h Table 8-8. LED_CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/ W 0h Reserved 3 LED3_Bank_EN R/ W 0h 1 = LED3 bank control mode enabled 0 = LED3 Independent control mode enabled 2 LED2_Bank_EN R/ W 0h 1 = LED2 bank control mode enabled 0 = LED2 independent control mode enabled 1 LED1_Bank_EN R/ W 0h 1 = LED1 bank control mode enabled 0 = LED1 independent control mode enabled 0 LED0_Bank_EN R/ W 0h 1 = LED0 bank control mode enabled 0 = LED0 independent control mode enabled 8.6.4 BANK_BRIGHTNESS (Address = 3h) [reset = FFh] BANK_BRIGHTNESS is shown in Figure 8-16 and described in Table 8-9. Return to Table 8-4. Figure 8-16. BANK_BRIGHTNESS Register 7 6 5 4 3 2 1 0 1 0 Bank_Brightness R/ W-FFh Table 8-9. BANK_BRIGHTNESS Register Field Descriptions Bit Field 7–0 Type Bank_Brightness R/ W Reset Description FFh FFh = 100% of full brightness ... 80h = 50% of full brightness ... 00h = 0% of full brightness 8.6.5 BANK_A_COLOR (Address = 4h) [reset = 00h] BANK_A_COLOR is shown in Figure 8-17 and described in Table 8-10. Return to Table 8-4. Figure 8-17. BANK_A_COLOR Register 7 6 5 4 3 2 Bank_A_Color R/ W-0h 26 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 Table 8-10. BANK_A_COLOR Register Field Descriptions Bit 7–0 Field Bank_A_Color Type R/ W Reset Description 0h FFh = The color mixing percentage is 100%. ... 80h = The color mixing percentage is 50%. ... 00h = The color mixing percentage is 0%. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 27 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 8.6.6 BANK_B_COLOR (Address = 5h) [reset = 00h] BANK_B_COLOR is shown in Figure 8-18 and described in Table 8-11. Return to Table 8-4. Figure 8-18. BANK_B_COLOR Register 7 6 5 4 3 2 1 0 Bank_B_Color R/ W-0h Table 8-11. BANK_B_COLOR Register Field Descriptions Bit Field 7–0 Type Bank_B_Color R/ W Reset Description 0h FFh = The color mixing percentage is 100%. ... 80h = The color mixing percentage is 50%. ... 00h = The color mixing percentage is 0%. 8.6.7 BANK_C_COLOR (Address = 6h) [reset = 00h] BANK_C_COLOR is shown in Figure 8-19 and described in Table 8-12. Return to Table 8-4. Figure 8-19. BANK_C_COLOR Register 7 6 5 4 3 2 1 0 Bank_C_Color R/ W-0h Table 8-12. BANK_C_COLOR Register Field Descriptions Bit Field 7–0 Type Bank_C_Color R/ W Reset Description 0h FFh = The color mixing percentage is 100%. ... 80h = The color mixing percentage is 50%. ... 00h = The color mixing percentage is 0%. 8.6.8 LED0_BRIGHTNESS (Address = 7h) [reset = FFh] LED0_BRIGHTNESS is shown in Figure 8-20 and described in Table 8-13. Return to Table 8-4. Figure 8-20. LED0_BRIGHTNESS Register 7 6 5 4 3 2 1 0 LED0_Brightness R/ W-FFh Table 8-13. LED0_BRIGHTNESS Register Field Descriptions Bit 7–0 Field LED0_Brightness Type R/ W Reset Description FFh FFh = 100% of full intensity ... 80h = 50% of full intensity ... 00h = 0% of full intensity 8.6.9 LED1_BRIGHTNESS (Address = 8h) [reset = FFh] LED1_BRIGHTNESS is shown in Figure 8-21 and described in Table 8-14. 28 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 Return to Table 8-4. Figure 8-21. LED1_BRIGHTNESS Register 7 6 5 4 3 2 1 0 1 0 1 0 LED1_Brightness R/ W-FFh Table 8-14. LED1_BRIGHTNESS Register Field Descriptions Bit Field 7–0 Type LED1_Brightness R/ W Reset Description FFh FFh = 100% of full intensity ... 80h = 50% of full intensity ... 00h = 0% of full intensity 8.6.10 LED2_BRIGHTNESS (Address = 9h) [reset = FFh] LED2_BRIGHTNESS is shown in Figure 8-22 and described in Table 8-15. Return to Table 8-4. Figure 8-22. LED2_BRIGHTNESS Register 7 6 5 4 3 2 LED2_Brightness R/ W-FFh Table 8-15. LED2_BRIGHTNESS Register Field Descriptions Bit Field 7–0 Type LED2_Brightness R/ W Reset Description FFh FFh = 100% of full intensity ... 80h = 50% of full intensity ... 00h = 0% of full intensity 8.6.11 LED3_BRIGHTNESS (Address = 0Ah) [reset = FFh] LED3_BRIGHTNESS is shown in Figure 8-23 and described in Table 8-16. Return to Table 8-4. Figure 8-23. LED3_BRIGHTNESS Register 7 6 5 4 3 2 LED3_Brightness R/ W-FFh Table 8-16. LED3_BRIGHTNESS Register Field Descriptions Bit 7–0 Field LED3_Brightness Type R/ W Reset Description FFh FFh = 100% of full intensity ... 80h = 50% of full intensity ... 00h = 0% of full intensity Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 29 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 8.6.12 OUT0_COLOR (Address = 0Bh) [reset = 00h] OUT0_COLOR is shown in Figure 8-24 and described in Table 8-17. Return to Table 8-4. Figure 8-24. OUT0_COLOR Register 7 6 5 4 3 2 1 0 OUT0_Color R/ W-00h Table 8-17. OUT0_COLOR Register Field Descriptions Bit Field 7–0 Type OUT0_Color R/ W Reset Description 00h FFh = The color mixing percentage is 0%. ... 80h =The color mixing percentage is 50%. ... 00h = The color mixing percentage is 100%. 8.6.13 OUT1_COLOR (Address = 0Ch) [reset = 00h] OUT1_COLOR is shown in Figure 8-25 and described in Table 8-18. Return to Table 8-4. Figure 8-25. OUT1_COLOR Register 7 6 5 4 3 2 1 0 OUT1_Color R/ W-00h Table 8-18. OUT1_COLOR Register Field Descriptions Bit Field 7–0 Type OUT1_Color R/ W Reset Description 00h FFh = The color mixing percentage is 0%. ... 80h =The color mixing percentage is 50%. ... 00h = The color mixing percentage is 100%. 8.6.14 OUT2_COLOR (Address = 0Dh) [reset = 00h] OUT2_COLOR is shown in Figure 8-26 and described in Table 8-19. Return to Table 8-4. Figure 8-26. OUT2_COLOR Register 7 6 5 4 3 2 1 0 OUT2_Color R/ W-00h Table 8-19. OUT2_COLOR Register Field Descriptions Bit 7–0 Field OUT2_Color Type R/ W Reset Description 00h FFh = The color mixing percentage is 0%. ... 80h =The color mixing percentage is 50%. ... 00h = The color mixing percentage is 100%. 8.6.15 OUT3_COLOR (Address = 0Eh) [reset = 00h] OUT3_COLOR is shown in Figure 8-27 and described in Table 8-20. 30 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 Return to Table 8-4. Figure 8-27. OUT3_COLOR Register 7 6 5 4 3 2 1 0 OUT3_Color R/ W-00h Table 8-20. OUT3_COLOR Register Field Descriptions Bit Field 7–0 Type OUT3_Color R/ W Reset Description 00h FFh = The color mixing percentage is 0%. ... 80h =The color mixing percentage is 50%. ... 00h = The color mixing percentage is 100%. 8.6.16 OUT4_COLOR (Address = 0Fh) [reset = 00h] OUT4_COLOR is shown in Figure 8-28 and described in Table 8-21. Return to Table 8-4. Figure 8-28. OUT4_COLOR Register 7 6 5 4 3 2 1 0 OUT4_Color R/ W-00h Table 8-21. OUT4_COLOR Register Field Descriptions Bit Field 7–0 Type OUT4_Color R/ W Reset Description 00h FFh = The color mixing percentage is 0%. ... 80h =The color mixing percentage is 50%. ... 00h = The color mixing percentage is 100%. 8.6.17 OUT5_COLOR (Address = 10h) [reset = 00h] OUT5_COLOR is shown in Figure 8-29 and described in Table 8-22. Return to Table 8-4. Figure 8-29. OUT5_COLOR Register 7 6 5 4 3 2 1 0 OUT5_Color R/ W-00h Table 8-22. OUT5_COLOR Register Field Descriptions Bit 7–0 Field OUT5_Color Type R/ W Reset Description 00h FFh = The color mixing percentage is 0%. ... 80h =The color mixing percentage is 50%. ... 00h = The color mixing percentage is 100%. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 31 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 8.6.18 OUT6_COLOR (Address = 11h) [reset = 00h] OUT6_COLOR is shown in Figure 8-30 and described in Table 8-23. Return to Table 8-4. Figure 8-30. OUT6_COLOR Register 7 6 5 4 3 2 1 0 OUT6_Color R/ W-00h Table 8-23. OUT6_COLOR Register Field Descriptions Bit Field 7–0 Type OUT6_Color R/ W Reset Description 00h FFh = The color mixing percentage is 0%. ... 80h =The color mixing percentage is 50%. ... 00h = The color mixing percentage is 100%. 8.6.19 OUT7_COLOR (Address = 12h) [reset = 00h] OUT7_COLOR is shown in Figure 8-31 and described in Table 8-24. Return to Table 8-4. Figure 8-31. OUT7_COLOR Register 7 6 5 4 3 2 1 0 OUT7_Color R/ W-00h Table 8-24. OUT7_COLOR Register Field Descriptions Bit Field 7–0 Type OUT7_Color R/ W Reset Description 00h FFh = The color mixing percentage is 0%. ... 80h =The color mixing percentage is 50%. ... 00h = The color mixing percentage is 100%. 8.6.20 OUT8_COLOR (Address = 13h) [reset = 00h] OUT8_COLOR is shown in Figure 8-32 and described in Table 8-25. Return to Table 8-4. Figure 8-32. OUT8_COLOR Register 7 6 5 4 3 2 1 0 OUT8_Color R/ W-00h Table 8-25. OUT8_COLOR Register Field Descriptions Bit 7–0 Field OUT8_Color Type R/ W Reset Description 00h FFh = The color mixing percentage is 0%. ... 80h =The color mixing percentage is 50%. ... 00h = The color mixing percentage is 100%. 8.6.21 OUT9_COLOR (Address = 14h) [reset = 00h] OUT9_COLOR is shown in Figure 8-33 and described in Table 8-26. 32 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 Return to Table 8-4. Figure 8-33. OUT9_COLOR Register 7 6 5 4 3 2 1 0 OUT9_Color R/ W-00h Table 8-26. OUT9_COLOR Register Field Descriptions Bit Field 7–0 Type OUT9_Color R/ W Reset Description 00h FFh = The color mixing percentage is 0%. ... 80h =The color mixing percentage is 50%. ... 00h = The color mixing percentage is 100%. 8.6.22 OUT10_COLOR (Address = 15h) [reset = 00h] OUT10_COLOR is shown in Figure 8-34 and described in Table 8-27. Return to Table 8-4. Figure 8-34. OUT10_COLOR Register 7 6 5 4 3 2 1 0 OUT10_Color R/ W-00h Table 8-27. OUT10_COLOR Register Field Descriptions Bit Field 7–0 Type OUT10_Color R/ W Reset Description 00h FFh = The color mixing percentage is 0%. ... 80h =The color mixing percentage is 50%. ... 00h = The color mixing percentage is 100%. 8.6.23 OUT11_COLOR (Address = 16h) [reset = 00h] OUT11_COLOR is shown in Figure 8-35 and described in Table 8-28. Return to Table 8-4. Figure 8-35. OUT11_COLOR Register 7 6 5 4 3 2 1 0 OUT11_Color R/ W-00h Table 8-28. OUT11_COLOR Register Field Descriptions Bit Field 7–0 Type OUT11_Color R/ W Reset Description 00h FFh = The color mixing percentage is 0%. ... 80h =The color mixing percentage is 50%. ... 00h = The color mixing percentage is 100%. 8.6.24 RESET (Address = 17h) [reset = 00h] RESET is shown in Figure 8-36 and described in Table 8-29. Return to Table 8-4. Figure 8-36. RESET Register 7 6 5 4 3 2 1 0 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 33 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 Figure 8-36. RESET Register (continued) Reset W-00h Table 8-29. OUT14_COLOR Register Field Descriptions 34 Bit Field Type Reset Description 7–0 Reset W 00h FFh = Reset all the registers to default value. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The LP50xx device is a 9- or 12-channel constant-current-sink LED driver. The LP50xx device improves the user experience in color mixing and intensity control, for both live effects and coding effort. The optimized performance for RGB LEDs makes it a good choice for human-machine interaction applications. 9.2 Typical Application The LP50xx design supports up to four devices in parallel with different configurations on the ADDR0 and ADDR1 pins. VCC VMCU CVCC VLED RPULLUP VC C RPULLUP OUT0 EN OUT1 SDA SCL OUT2 ADDR 0 MCU ADDR 1 LP5012 OUT9 VCAP CVCAP OUT10 IREF RIREF GND VCC OUT11 CVCC VLED VC C OUT0 EN OUT1 SDA SCL OUT2 ADDR 0 ADDR 1 LP5012 OUT9 VCAP CVCAP OUT10 IREF RIREF GND OUT11 Figure 9-1. Driving Dual LP5012 Application Example Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 35 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 9.2.1 Design Requirements Set the LED current to 15 mA using the RIREF resistor. Select the proper value for the other external components, like VCAP pin capacitor and the SCL/SDA pullup resisters. 9.2.2 Detailed Design Procedure LP50xx scales up the reference current (IREF) set by the external resistor (RIREF) to sink the output current (IOUT) at each output port. The following formula can be used to calculate the external resistor (RIREF): RIREF =KIREF × VIREF ISET (2) The SCL and SDA lines must each have a pullup resistor placed somewhere on the line (the pullup resistors are normally located on the bus master). In typical applications, values of 1.8 kΩ to 4.7 kΩ are used. VCAP is internal LDO output pin. This pin must be connected through a 1-µF capacitor to GND. Place the capacitor as close to the device as possible. TI recommends having a 1-µF capacitor between VCC and GND to ensure proper operation. Place the capacitor as close to the device as possible. 9.2.3 Application Curves The test condition for Figure 9-2 is that the testing under bank control, with the register’s (0x04, 0x05, 0x06) value is 0xF0. The test condition for Figure 9-3 is that the testing under bank control, with the register’s (0x04, 0x05, 0x06) value is 0x0F. Figure 9-2. Current Waveform of OUT0, OUT1, OUT2 and OUT3 36 Figure 9-3. Current Waveform of OUT0, OUT1, OUT2 and OUT3 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 10 Power Supply Recommendations The device is designed to operate from a VVCC input-voltage supply range from 2.7 V and 5.5 V. This input supply must be well-regulated and able to withstand maximum input current and maintain stable voltage without voltage drop even in a load-transition condition (start-up or rapid intensity change). The resistance of the input supply rail must be low enough that the input-current transient does not cause a drop below a 2.7-V level in the LP50xx VVCC supply voltage. 11 Layout 11.1 Layout Guidelines To prevent thermal shutdown, the junction temperature, TJ, must be less than T(TSD). If the voltage drop across the output channels is high, the device power dissipation can be large. The LP50xx device has very good thermal performance because of the thermal pad design; however, the PCB layout is also very important to ensure that the device has good thermal performance. Good PCB design can optimize heat transfer, which is essential for the long-term reliability of the device. Use the following guidelines when designing the device layout: • • • • Place the CVCAP, CVCCand RIREF as close to the device as possible. Also, TI recommends putting the ground plane as Figure 11-1 and Figure 11-2. Maximize the copper coverage on the PCB to increase the thermal conductivity of the board. The major heat flow path from the package to the ambient is through copper on the PCB. Maximum copper density is extremely important when no heat sinks are attached to the PCB on the other side from the package. Add as many thermal vias as possible directly under the package ground pad to optimize the thermal conductivity of the board. Use either plated-shut or plugged and capped vias for all the thermal vias on both sides of the board to prevent solder voids. To ensure reliability and performance, the solder coverage must be at least 85%. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 37 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 11.2 Layout Examples IREF EN SCL SDA VCC 19 18 17 16 GND 20 GND VCAP 1 15 ADDR1 To LED OUT0 2 14 ADDR0 To LED OUT1 3 To LED OUT2 4 12 To LED OUT3 5 11 GND 10 OUT8 To LED 9 OUT7 To LED 8 OUT6 To LED 7 OUT5 To LED 6 13 OUT4 To LED GND GND Figure 11-1. LP5009RUK Layout Example IREF EN SCL SDA VCC 19 18 17 16 GND 20 GND VCAP 1 15 ADDR1 To LED OUT0 2 14 ADDR0 To LED OUT1 3 13 OUT11 To LED To LED OUT2 4 12 OUT10 To LED To LED OUT3 5 11 OUT9 10 OUT8 To LED 9 OUT7 To LED 8 OUT6 To LED 7 OUT5 To LED 6 OUT4 To LED GND GND To LED GND Figure 11-2. LP5012RUK Layout Example 38 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 CVCC GND RIREF CVCAP To LED ADDR0 1 24 AGND 2 23 ADDR1 3 22 VCC 4 21 OUT8 To LED SDA 5 20 OUT7 To LED PGND 6 19 OUT6 To LED GND SCL 7 18 DGND EN 8 17 OUT5 To LED IREF 9 16 OUT4 To LED VCAP 10 15 OUT3 To LED NC 11 14 OUT2 To LED OUT0 12 13 OUT1 To LED Figure 11-3. LP5009PW Layout Example CVCC GND RIREF CVCAP To LED ADDR0 1 24 OUT11 To LED AGND 2 23 OUT10 To LED ADDR1 3 22 OUT9 To LED VCC 4 21 OUT8 To LED SDA 5 20 OUT7 To LED PGND 6 19 OUT6 To LED GND SCL 7 18 DGND EN 8 17 OUT5 To LED IREF 9 16 OUT4 To LED VCAP 10 15 OUT3 To LED NC 11 14 OUT2 To LED OUT0 12 13 OUT1 To LED Figure 11-4. LP5012PW Layout Example Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 39 LP5009, LP5012 www.ti.com SLVSEH2B – MAY 2019 – REVISED AUGUST 2020 12 Device and Documentation Support 12.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to order now. Table 12-1. Related Links PARTS PRODUCT FOLDER ORDER NOW TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY LP5009 Click here Click here Click here Click here Click here LP5012 Click here Click here Click here Click here Click here 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and without revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane. 40 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LP5009 LP5012 PACKAGE OPTION ADDENDUM www.ti.com 28-Sep-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) LP5009PWR ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 LP5009PWR LP5009RUKR ACTIVE WQFN RUK 20 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LP5009 LP5012PWR ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 LP5012PWR LP5012RUKR ACTIVE WQFN RUK 20 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LP5012 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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