LP55271
www.ti.com
SNVS460A – SEPTEMBER 2006 – REVISED MAY 2013
Tiny LED Driver for Camera Flash and Four LEDs With I2C Programmability, Connectivity
Test, and Audio Synchronization
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FEATURES
APPLICATIONS
•
•
1
2
•
•
•
•
•
•
•
•
•
High Current Boost DC-DC Converter
(up to 1-A Output Current)
Programmable Boost Output Voltage
370-mA Flash LED Constant-Current Driver
With Low Tolerance and a Safety Circuit
Synchronization Pin for Flash Timing
Two Single-Ended Audio Inputs With Gain
Control
Four Constant-Current 15-mA LED Drivers
With 8-Bit Programmable Brightness Control
Audio Synchronization Feature
I2C Compatible Control Interface
Built-in LED Connectivity Test to Maximize
Manufacturing Yield
Small DSBGA-30 Package (2.5 mm x 3.0 mm x
0.6 mm)
Camera Flash, Funlight, and Backlight Driving
in Battery-Powered Devices
DESCRIPTION
The LP55271 is a lighting management unit for
handheld devices with I2C compatible control
interface. The LP55271 has a step-up DC/DC
converter with high current output and it drives
display and keypad backlights and powers the
camera flash LED. In addition the DC/DC converter
has the output current to power for example an audio
amplifier simultaneously. The chip has four 8-bit
programmable high efficiency constant current LED
drivers and a FLASH LED driver. Built-in audio
synchronization feature allows the user to
synchronize one of the LEDs to audio input.
Typical Application
VIN
3.0 to 5.5V
AUDIO
SIGNAL
C1
CVDD1
CVDD2
100 nF
100 nF
VDD1
VDD2
ASE1
D1
COUT1 COUT2
10 PF 10 PF
10 PF
VOUT
SW1
SW2
47 nF
C2
FB
ASE2
LED1
47 nF
AUDIO
SIGNAL
L1
CIN 4.7 PH
LED2
2
CAMERA
TEST
INTERFACE
LP55271
LED3
LED4
FLASH_SYNC
FLASH
IFLASH
SDA
RT 1.3 k:
SCL
MCU
RF
RT
NRST
82 k:
VDD_IO
CVDD_IO
100 nF
GNDs
VREF
CVREF
VDDA
100 nF
CVDDA
4.7 PF
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
LP55271
SNVS460A – SEPTEMBER 2006 – REVISED MAY 2013
www.ti.com
DESCRIPTION (CONTINUED)
The LP55271 has an integrated 370 mA flash driver with a safety stop feature and 46 mA torch mode. An
external enable pin is provided for the synchronizing the flash with the camera action. An external software
independent test interface provides a fast way to find a broken path or short on LED circuits. Very small DSBGA
package together with minimum number of external components is a best fit for handheld devices.
CONNECTION DIAGRAMS
DSBGA-30 package, 2.466 x 2.974 x 0.60 mm body size, 0.5 mm pitch, Package Number YZR0030
5
LED2
LED1
GND_
LED
FB
SW2
SW1
SW1
SW2
FB
GND_
LED
LED1
LED2
5
4
LED4
LED3
T1
T2
GND_
SW2
GND_
SW1
GND_
SW1
GND_
SW2
T2
T1
LED3
LED4
4
3
NRST
SCL
GND
VDD1
FLASH_
SYNC
GNDC
GNDC
FLASH_
SYNC
VDD1
GND
SCL
NRST
3
2
IFLASH
ASE2
ASE1
RT
SDA
FLASH
FLASH
SDA
RT
ASE1
ASE2
IFLASH
2
1
VDD2
VDDA
VREF
GNDA
VDDIO
GND_
FLASH
GND_
FLASH
VDDIO
GNDA
VREF
VDDA
VDD2
1
A
B
C
D
E
F
F
E
D
B
A
Figure 1. Top View
C
Figure 2. Bottom View
Table 1. Pin Descriptions
(1)
2
Type
(1)
Pin
Name
D3
VDD1
P
Supply Voltage
Description
A1
VDD2
P
Supply Voltage
F5
SW1
A
Boost Converter Switch
E5
SW2
A
Boost Converter Switch
D5
FB
A
Boost Converter Feedback
B5
LED1
O
LED1 Driver Output
A5
LED2
O
LED2 Driver Output
B4
LED3
O
LED3 Driver Output
A4
LED4
O
LED4 Driver Output
F2
FLASH
O
Flash LED Driver Output
F3
GNDC
G
Ground for Core Circuitry
D2
RT
A
Oscillator Frequency Setting
C1
VREF
A
Reference Voltage
B1
VDDA
P
Internal LDO
F4
GND_SW1
G
Boost Converter Ground
E4
GND_SW2
G
Boost Converter Ground
C5
GND_LED
G
LEDs 1 to 4 Driver Ground Connection
F1
GND_FLASH
G
Flash Driver Ground Connection
A: Analog Pin D: Digital Pin G: Ground Pin P: Power Pin, I: Input Pin I/O: Input/Output Pin O: Output Pin OD: Open Drain Pin
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Table 1. Pin Descriptions (continued)
Pin
Name
Type (1)
A2
IFLASH
A
Resistor for Flash Current Setting
D1
GNDA
G
Analog Ground Connection
C3
GND
G
Ground
E1
VDD_IO
P
Supply Voltage for Digital Interface
A3
NRST
DI
Low Active Reset
B3
SCL
DI
I2C Compatible Interface Clock Signal
E2
SDA
OD
I2C Compatible Interface Data Signal
Description
E3
FLASH_SYNC
DI
FLASH LED Control
D4
T2
DO
Test Pin (Result)
C4
T1
DI
Test Pin (Clock)
C2
ASE1
AI
Audio Input
B2
ASE2
AI
Audio Input
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LP55271
SNVS460A – SEPTEMBER 2006 – REVISED MAY 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2) (3)
Voltage on power pins (VDD1,2)
-0.3V to +6.0V
Voltage on analog pins
-0.3V to VDD1,2+0.3V with 6.0V max
Voltage on input/output pins
-0.3V to VDD1,2+0.3V with 6.0V max
V(all other pins): Voltage to GND
-0.3V to 6.0V
I(VREF)
10 µA
I(FLASH)
500 mA
Continuous Power Dissipation
(4)
Internally Limited
Junction Temperature (TJ-MAX)
125ºC
Storage Temperature Range
-65ºC to +150ºC
Maximum Lead Temperature (Reflow soldering, 3 times) (5)
ESD Rating, Human Body Model (6)
(1)
(2)
(3)
(4)
(5)
(6)
260ºC
2 kV
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test
conditions, see the Electrical Characteristics tables.
All voltages are with respect to the potential at the GND pins.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 160ºC (typ.) and
disengages at TJ = 140ºC (typ.).
For detailed soldering specifications and information, see application note AN1112 : DSBGA Wafer Level Chip Scale Package.
The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. MIL-STD-883 3015.7
Operating Ratings
(1)
,
(2)
Voltage on power pins (VDD1,2)
3.0 to 5.5V
Voltage on ASE1, ASE2
0V to 1.6V
VDD_IO
1.65V to VDD1
Junction Temperature (TJ) Range
Ambient Temperature (TA) Range
(1)
(2)
(3)
-30ºC to +125ºC
(3)
-30ºC to +85ºC
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test
conditions, see the Electrical Characteristics tables.
All voltages are with respect to the potential at the GND pins.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =
125ºC), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the
part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).
Thermal Properties
Junction-to-Ambient Thermal Resistance (θJA) (1)
(1)
4
60 - 100ºC/W
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
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SNVS460A – SEPTEMBER 2006 – REVISED MAY 2013
Electrical Characteristics (1)
(2)
Limits in standard typeface are for TJ = 25ºC. Limits in boldface type apply over the operating ambient temperature range (30ºC < TA < +85ºC). Unless otherwise noted, specifications apply to the LP55271 Block Diagram with: VIN = 3.6V, CIN = 10
µF, COUT1 = 10 µF, COUT2 = 10 µF, CVDD_IO = 100 nF, CVREF = 100 nF, CVDDA = 4.7 µF, CVDD1 = 100 nF, CVDD2 = 100 nF, L1 =
4.7 µH. (3)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
1
5
µA
ISHUT DOWN
Current of VDD1 + VDD2 pins +
Leakage Current of SW1, SW2,
LED1 to 4 and FLASH
Voltage on VDD_IO = 0V, NRST = L,
NSTBY(bit) = L
Active Mode Supply Current
(VDD1 + VDD2 current)
NRST = H, NSTBY(bit) = H, no
load, EN_BOOST(bit) = L, SCL,
SDA = H
350
µA
IDD
No load supply current
(VDD1 + VDD2 current)
NSTBY(bit) = H, EN_BOOST(bit) =
H, SCL, SDA, NRST = H,
AUTOLOAD_EN(bit) = L
850
µA
IDD
IVDDIO
VDD_IO Standby Supply current
NSTBY(bit) = L
VDDA
(1)
(2)
(3)
IVDDA = 1 mA
-4%
2,8V
1
µA
+4%
V
All voltages are with respect to the potential at the GND pins.
Min and Max limits are specified by design, test, or statistical analysis. Typical numbers represent the most likely norm.
Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
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LP55271
SNVS460A – SEPTEMBER 2006 – REVISED MAY 2013
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LP55271 BLOCK DIAGRAM
V IN
L1 4.7 ?H
COUT1
10 ?F
CIN
10 ?F
SW1
RT 82 k?
SW2
INTERNAL
OSC
PWM
VREF
47 nF
GNDSW1
ERROR
AMP
CVREF
100 nF
C1
47 nF
C2
COUT2
10 ?F
GNDSW2
FB
GAIN
CONTROL
AND ADC
LEVEL
DETEC.
LIGHTING
CONTROL
T1
T2
DAC
OUTPUT
SELECTOR
LED1
LED CONNECTIVITY TEST
LIGHTING
CONTROL
DAC
DAC
CAMERA
FLASH_SYNC
DAC
SCL
SDA
SERIAL
INTERFACE
NRST
REGISTERS
MICROCONTROLLER
TIME
LIMIT
LED2
LED3
FUNLIGHT
KEYPAD
AND
BACKLIGHT
0 TO 15 mA
/LED
LED4
FLASH
370 mA
FLASH
GND_LED
GND_FLASH
VDD_IO
FINITE STATE
MACHINE
CVDD_IO
100 nF
VDD1
VIN
EPROM
POR
FLASH
CONTROL
THERMAL
SHUTDOWN
INTERNAL LDO
2.8V
VDD2
CVDD1
100 nF
CVDD2
RF 1300?
GND
GNDC
GNDA
VDDA
CVDDA
4.7 ?F
100 nF
6
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SNVS460A – SEPTEMBER 2006 – REVISED MAY 2013
DEVICE INFORMATION
Modes of Operation
RESET
NRST = L
or
POR= H
NSTBY(bit)=L
and
NRST=H
STANDBY
NSTBY(bit)=H
and
NRST=H
NSTBY(bit) = H
and
NRST=H
NSTBY(bit)=L
and
NRST=H
INTERNAL
STARTUP
SEQUENCE
TSD=H
VREF = 95%OK
1
~ 10 ms DELAY
1
EN_BOOST(bit)=H
1
EN_BOOST(bit)=L
BOOST STARTUP
EN_BOOST(bit)=H
1
~ 10 ms DELAY
NORMAL MODE
1) TSD =L
RESET: In the reset mode all the internal registers are reset to the default values. Reset is entered always if
input NRST is LOW or internal Power On Reset (POR) is active. Power on reset will activate during the
chip startup or when the supply voltage VDD2 falls below 1.5V. Once VDD2 rises above 1.5V, POR will
inactivate and the chip will continue to the STANDBY mode. NSTBY control bit is low after POR by
default.
STANDBY: The standby mode is entered if the register bit NSTBY is LOW and reset is not active. This is the
low power consumption mode, when all circuit functions are disabled. Registers can be written in this
mode and the control bits are effective immediately after start up.
STARTUP: When NSTBY bit is written high, the internal startup sequence powers up all the needed internal
blocks (VREF, Oscillator, etc.). To ensure the correct oscillator initialization, a 10 ms delay is generated by
the internal state-machine. If the chip temperature rises too high, the thermal shutdown (TSD) disables the
chip operation and startup mode is entered until no thermal shutdown event is present.
BOOST STARTUP: Soft-start for boost output is generated in the boost startup mode. The boost output is raised
in a low current PWM mode during the 10 ms delay generated by the state-machine. The boost startup is
entered from internal startup sequence if EN_BOOST is HIGH or from normal mode when EN_BOOST is
written HIGH.
NORMAL: During normal mode the user controls the chip using the Control Registers. The registers can be
written in any sequence and any number of bits can be altered in a register in one write.
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LP55271
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Magnetic Boost DC/DC Converter
The LP55271 boost DC/DC converter generates a 4.00 – 5.40V output voltage to drive the LEDs from a single
Li-Ion battery (3.0V to 4.5V). The output voltage is controlled with a 4-bit register in 8 steps. The converter is a
magnetic switching PWM mode DC/DC converter with a current limit. The converter has 2.0 MHz / 1.0 MHz
selectable switching frequency operation, when the timing resistor RT is 82 kΩ.
The LP55271 boost converter uses pulse-skipping elimination method to stabilize the noise spectrum. Even with
light load or no load a minimum length current pulse is fed to the inductor. An internal active load is used to
remove the excess charge from the output capacitor when needed.
The topology of the magnetic boost converter is called CPM control, current programmed mode, where the
inductor current is measured and controlled with the feedback. The output voltage control changes the resistor
divider in the feedback loop.
Figure 3 shows the boost topology with the protection circuitry. Four different protection schemes are
implemented:
1. Over voltage protection, limits the maximum output voltage.
– Keeps the output below breakdown voltage.
– Prevents boost operation if battery voltage is much higher than desired output.
2. Over current protection, limits the maximum inductor current.
– Voltage over switching NMOS is monitored; too high voltages turn the switch off.
3. Feedback (FB) protection for no connection.
4. Duty cycle limiting, done with digital control.
2 MHz clock
VIN
Duty control
V OUT
SW
FB
UVCOMP
2V
R
S
+
OVPCOMP
R
+
-
RESETCOMP
+
-
+
SWITCH
R
R
ERRORAMP
ACTIVE
LOAD
R
SLOPER
LOOPC
OCPCOMP
+
-
IMAX
Figure 3. Boost Converter Topology
8
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MAGNETIC BOOST DC/DC CONVERTER ELECTRICAL CHARACTERISTICS
Limits in standard typeface are for TJ = 25ºC. Limits in boldface type apply over the operating ambient temperature range (30ºC < TA < +85ºC). Unless otherwise noted, specifications apply to the LP55271 Block Diagram with: VIN = 3.6V, CIN = 10
µF, COUT1 = 10 µF, COUT2 = 10 µF, CVDDIO = 100 nF, CVREF = 100 nF, CVDDA = 4.7 µF, CVDD1 = 100 nF, CVDD2 = 100 nF, L1 =
4.7 µH. (4)
Symbol
ILOAD
Parameter
Test Conditions
Load Current (1)
3.2V ≤ VIN ≤ 4.5V
VOUT = 5.0V
Output Voltage Accuracy (FB pin)
3.2V ≤ VIN ≤ 4.5V
VOUT (target value) = 5.0V,
active load off
VOUT
Output Voltage (FB Pin)
Min
−5
3.0V ≤ VIN ≤ (5.0V+VSCHOTTKY)
active load off
VIN = 3.6V, ISW = 1.0A
0.20
PWM Mode Switching Frequency
RT = 82 kΩ
FREQ_SEL (bit) = 1
FREQ_SEL (bit) = 0
2.0
1.0
Frequency Accuracy
3.2V ≤ VDD1,2 ≤ 5.0V
RT = 82 kΩ
tPULSE
Switch Pulse Minimum Width
no load
tSTARTUP
ICL_OUT
(4)
(1)
Unit
670
mA
+5
%
V
VIN VSCHOTTKY
Switch ON Resistance
fPWF
Max
5.0
VIN > (5.0V + VSCHOTTKY)
RDSON
Typ
−6
-9
±3
Ω
0.4
MHz
+6
+9
%
25
ns
Startup Time
10
ms
SW1 + SW2 current limit
1.7
A
Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
Specified currents are the worst case currents. If input voltage is larger or output voltage is smaller, current can be increased according
to graph "Boost Maximum Output Current".
BOOST STANDBY MODE
User can set the boost converter to STANDBY mode by writing the register bit EN_BOOST low when there is no
load to avoid idle current consumption. When EN_BOOST is written high, the converter starts in low current
PWM (Pulse Width Modulation) mode for 10 ms and then goes to normal PWM mode.
BOOST CONTROL REGISTERS
User can control the boost output voltage and the switching frequency according to the following tables.
Boost Output Voltage
[3:0] Register
Boost Output Voltage (V)
(Typical)
0000
4.00
0001
4.20
0011
4.40
0111
4.60 default
1000
4.80
1001
5.00
1011
5.20
1111
5.40
FREQ_SEL Bit
Boost Switching Frequency
(Typical)
0
1.0 MHz default
1
2.0 MHz
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Boost Converter Typical Performance Characteristics
TJ = 25ºC. Unless otherwise noted, typical performance characteristics apply to the LP55271 Block Diagram with:
VIN = 3.6V, VOUT = 5.0V, CIN = 10 µF, COUT1 = 10 µF, COUT2 = 10 µF, CVDD_IO = 100 nF, CVREF = 100 nF, CVDDA =
4.7 µF, CVDD1 = 100 nF, CVDD2 = 100 nF, L1 = 4.7 µH (1).
Boost Typical Waveforms at 100 mA Load
fBOOST = 2.0 MHz
300 mA
500 mA
670 mA
L = TDK VLCF5020T-4R7N1R7-1
VSWITCH
(5V/DIV)
ICOIL=150 mA
AVERAGE
(100mA/DIV)
ILOAD = 100 mA
VOUT
(10 mV/DIV)
Boost Converter Efficiency
Figure 4.
Figure 5.
Battery Current vs Voltage
Boost Frequency vs RT Resistor
ILOAD = 670 mA
FREQ_SEL (bit) =1
VOUT = 5.4V
FREQ_SEL (bit) =0
VOUT = 4.0V
Figure 6.
(1)
10
Figure 7.
Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
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Boost Line Regulation 3.0V - 3.6V
Boost Startup to 5.4V with no Load
VIN (3.0V TO 3.6V)
VIN (500 mV/DIV)
VOUT = 5V (10 mV/DIV)
EN_AUTOLOAD (bit) = 1
ILOAD = 50 mA
Figure 8.
Figure 9.
Boost Load Transient Response, 50 mA to 100 mA
Boost Maximum Output Current
ILOAD
(20 mA/DIV)
VOUT = 4.0V
VOUT = 5V
(50 mV/DIV)
VOUT = 5.4V
fBOOST = 2.0 MHz
Figure 10.
Figure 11.
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Flash Driver
LP55271 has an internal constant current driver that is capable for sinking low (46 mA) and high (370 mA)
current mainly targeted for torch and flash LED in camera phone applications. 370 mA flash driver can be
hardware or software enabled. Flash safety function prevents hardware damages due to possible overheating
when the flash has been stuck on because of a hardware, software or user error.
Flash safety counter starts counting when the flash is activated and disables the flash automatically when the
pre-defined 1.0s or 2.0s time limit is reached. Flash is activated with FLASH_SYNC bit or FLASH_SYNC pin, as
defined in the table below. Safety time limit is defined by SAFETY_TIME bit. (Time limit is 2.0s if SAFETY_TIME
bit is low and 1.0s if the bit is high.)
Flash driver currents — both torch and flash — are set with external resistor R F. The flash current is 480/RF
amperes and the torch current is 60/RF amperes. User should not use lower resistance value than 1200Ω.
Table 2. Flash LED Control (1)
(1)
EN_TORCH bit
EN_FLASH bit
FLASH_SYNC bit or pin
SAFETY_TIME bit
0
0
X
X
Flash LED Action
Off
1
0
X
X
Torch
X
1
Change from LOW to HIGH to
engage; from HIGH to LOW to
disengage
0 for 2.0 seconds;
1 for 1.0 second
Flash
X = don’t care
Table 3. Flash Programming Example
Address
Data
00H
8FH
Sets safety time to 1.0s. In this example LED1 to LED4 are enabled.
Function
00H
9FH
Enables torch.
00H
FFH
Activates FLASH. EN_FLASH bit and FLASH_SYNC bit are written simultaneously because EN_FLASH
disables torch.
00H
BFH
Disables FLASH. If FLASH is disabled by safety time, FLASH_SYNC bit needs to be written to 0 before next
FLASH.
FLASH DRIVER ELECTRICAL CHARACTERISTICS
Limits in standard typeface are for TJ = 25ºC. Limits in boldface type apply over the operating ambient
temperature range (-30ºC < TA < +85 ºC). Unless otherwise noted, specifications apply to the LP55271 Block
Diagram with: VIN = 3.6V, CIN = 10 µF, COUT1 = 10 µF, COUT2 = 10 µF, CVDDIO = 100 nF, CVREF = 100 nF, CVDDA =
4.7 µF, CVDD1 = 100 nF, CVDD2 = 100 nF, L1 = 4.7 µH, RF = 1300Ω
Symbol
Parameter
Test Conditions
Flash Mode Sink Current (1)
IFLASH
(1)
ITORCH
Torch Mode Sink Current
ILEAKAGE
Flash Driver Leakage Current
tFLASH
Flash Turn-On Time
Min
Saturation Voltage
tSAFETY
Safety Time Accuracy
Typ
Max
370
-7.5
Unit
mA
+7.5
%
3.0V ≤ VIN ≤ 5.5V
46
mA
VFB = 5.0V
0.1
µA
20
µs
550
mV
(2)
VSAT
(1)
(2)
3.0V ≤ VIN ≤ 5.5V,
VFLASH = 1.0V
3.0V ≤ VIN ≤ 5.5V,
Current Decreased to 95% of the
Maximum Sink Current
-9
+9
%
Min and Max limits are specified by design, test, or statistical analysis. Typical numbers represent the most likely norm.
Flash turn-on time is measured from the moment the flash is activated until the flash current crosses 90% of its target value.
Constant Current Sink Outputs LED1, LED2, LED3, LED4
LP55271 has four independent backlight/keypad LED drivers. All the drivers are regulated constant current sinks.
LED currents are controlled by 8-bit current mode DACs. Every driver can be controlled in two ways:
1. Brightness control with constant current drivers
12
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2. Direct ON/OFF control. The current is pre-set by 8-bit current mode DAC.
In addition, LED1 driver can be synchronized to audio input signal amplitude.
By using brightness control user can set brightness of every single LED by using 8-bit brightness control
registers. If analog audio is available on system the user can use audio synchronization for synchronizing LED1
to the music. Direct ON/OFF control is mainly for switching LEDs on and off.
LED Control Register (00 hex) has control bits for direct on/off control of all the LEDs. Note that the LEDs have
to be turned on in order to control them with audio synchronization (LED1 only) or brightness control.
The brightness is programmed as described in the following.
ILED = n x (15 mA / 255)
where
•
•
n = LED[7:0] (8-bit)
step = 15 mA / 255 ≈ 0.05882 mA
(1)
For example if 13.2 mA is required for driver current:
n = 13.2 mA / (15 mA / 255) ≈ 224
224 = 1110 0000, E0 hex
Table 4. LED1 to LED4 Brightness Control
LED1[7:0], LED2[7:0], LED3[7:0] and
LED4[7:0] Registers
Driver Current, mA
(typical)
0000 0000
0
0000 0001
0.059
0000 0010
0.118
•
•
1110 0000
13.176
•
•
1111 1110
14.941
1111 1111
15
LED1 TO LED4 DRIVERS ELECTRICAL CHARACTERISTICS
Limits in standard typeface are for TJ = 25ºC. Limits in boldface type apply over the operating ambient
temperature range (-30ºC < TA < +85ºC). Unless otherwise noted, specifications apply to the LP55271 Block
Diagram with: VIN = 3.6V, CIN = 10 µF, COUT1 = 10 µF, COUT2 = 10 µF, CVDDIO = 100 nF, CVREF = 100 nF, CVDDA =
4.7 µF, CVDD1 = 100 nF, CVDD2 = 100 nF, L1 = 4.7 µH. (1)
Symbol
Parameter
IMAX
Maximum Sink Current
ILEAKAGE
Leakage Current
Test Conditions
Typ
Max
15
VFB = 5.0V
ILED
Current Tolerance
ISINK = 13.2 mA (target value)
IMATCH
Sink Current Matching Between
LED 1 to 4 (1)
ISINK = 13.2 mA
VSAT
Saturation Voltage
3.0V ≤ VIN ≤ 5.5V,
Current Decreased to 95% of the
Maximum Sink Current
(1)
(1)
Min
Unit
mA
0.03
µA
13.2
mA
-7
+7
%
1
150
%
230
mV
Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
Sink current matching is the maximum difference from the average.
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Audio Synchronization
The LED1 output can be synchronized to incoming audio signal with Audio Synchronization feature. Audio
Synchronization synchronizes LED1 based on input signal’s peak amplitude. Programmable gain and automatic
gain control function are also available for adjustment of input signal amplitude to light response. Control of LED1
brightness refreshing frequency is done with four different frequency configurations. The digitized input signal has
a DC component that is removed by a digital DC-remover. The DC-remover is a high-pass filter where corner
frequency is user selectable by using DC_FREQ bit. LP55271 has 2-channel audio (stereo) input for audio
synchronization, as shown in Figure 12. The inputs accept signals in the range of 0V to 1.6V peak-to-peak and
these signals are mixed into a single wave so that they can be filtered simultaneously.
LP55271 audio synchronization is mainly done digitally and it consists following signal path blocks (see
Figure 12).
• Input buffer
• AD converter
• Automatic Gain Control (AGC) and manually programmable gain
• Peak detector
Automatic Gain Control (AGC) adjusts the input signal to suitable range automatically. User can disable AGC
and the gain can be set manually with programmable gain. Audio synchronization is based on peak detection
method.
EN_AGC GAIN_SEL
[2:0]
ASE1
ADC
ASE2
SPEED_CTRL[1:0]
15k
15k
Threshold
&
AGC
PEAK
DETECTOR
LED1
CONTROL
HOLD
THRESHOLD
[3:0]
Figure 12.
Audio Synchronization Input Electrical Parameters
Symbol
Parameter
Test Conditions
ZIN
Input Impedance of ASE1, ASE2
AIN
ASE1, ASE2 Audio Input Level
Range (peak-to-peak)
Min input level needs maximum gain;
Max input level for minimum gain.
Min
Typ
10
15
0
Max
Unit
kΩ
1600
mV
CONTROL OF AUDIO SYNCHRONIZATION
The following table describes the controls required for audio synchronization. LED1 brightness control through
serial interface is not available when audio synchronization is enabled.
Table 5. Audio Synchronization Control
EN_SYNC
Audio synchronization enabled. Set EN_SYNC = 1 to enable audio synchronization or 0 to disable.
EN_AGC
Automatic gain control. Set EN_AGC = 1 to enable automatic control or 0 to disable.
When EN_AGC is disabled, the audio input signal gain value is defined by GAIN_SEL.
GAIN_SEL[2:0]
Input signal gain control. Gain has a range from 0 dB to -46 dB.
SPEED_CTRL[1:0]
Control for refreshing frequency. Sets the typical refreshing rate for the LED1 output.
THRESHOLD[3:0]
Control for the audio input threshold. Sets the typical threshold for the audio inputs signals.
May be needed if there is noise on the audio lines.
DC_FREQ
Control for the high-pass filter corner frequency.
0 = 80 Hz
1 = 510 Hz
14
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Table 6. Audio Input Threshold Setting
Threshold[3:0]
Threshold Level, mV (typical)
0000
Disabled
0001
0.2
0010
0.4
*
*
*
*
1110
2.5
1111
2.7
Table 7. Typical Gain Values vs. Audio Input Amplitude
Audio Input Amplitude mVP-P
Gain Value dB
0 to 10
0
0 to 20
-6
0 to 40
-12
1 to 85
-18
3 to 170
-24
5 to 400
-31
10 to 800
-37
20 to 1600
-46
Table 8. Input Signal Gain Control
GAIN_SEL[2:0]
Gain dB
000
0
001
-6
010
-12
011
-18
100
-24
101
-31
110
-37
111
-46
Table 9. Refreshing Frequency
SPEED_CTRL[1:0]
Refreshing Rate Hz
00
FASTEST
01
15
10
7.6
11
3.8
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Logic Interface Characteristics
Limits in standard typeface are for TJ = 25ºC. Limits in boldface type apply over the operating ambient temperature range (30ºC < TA < +85ºC). Unless otherwise noted, specifications apply to the LP55271 Block Diagram with: VIN = 3.6V, CIN = 10
µF, COUT1 = 10 µF, COUT2 = 10 µF, CVDDIO = 100 nF, CVREF = 100 nF, CVDDA = 4.7 µF, CVDD1 = 100 nF, CVDD2 = 100 nF, L1 =
4.7 µH (1)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
0.2 x
VDD_IO
V
Logic Inputs SCL and FLASH_SYNC
VIL
Input Low Level
VIH
Input High Level
II
Input Current
fSCL
SCL Pin Clock Frequency
0.8 x
VDD_IO
VDD_IO = 1.65V to VDD1,2
V
-1.0
1.0
400
µA
kHz
Logic Input NRST
VIL
Input Low Level
VIH
Input High Level
0.5
II
Input Current
tNRST
Reset Pulse Width
1.2
VDD_IO = 1.65V to VDD1,2
V
V
-1.0
1.0
10
µA
µs
Logic Input/Output SDA
VOL
Output Low Level
IOUT = 3 mA
IL
Output leakage current
VOUT = 2.8V
(1)
0.3
0.5
V
1.0
µA
Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
I2C Compatible Interface
I2C SIGNALS
The SCL pin is used for the I2C clock and the SDA pin is used for bidirectional data transfer. Both these signals
need a pull-up resistor according to I2C specification. The values of the pull-up resistors are determined by the
capacitance of the bus (typ. ~1.8 kΩ). Signal timing specifications are shown in table I2C Timing Parameters.
I2C DATA VALIDITY
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of
the data line can only be changed when CLK is LOW.
SCL
SDA
data
change
allowed
data
valid
data
change
allowed
data
valid
data
change
allowed
Figure 13. I2C Signals: Data Validity
I2C START AND STOP CONDITIONS
START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA
signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA
transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP bits.
The I2C bus is considered to be busy after START condition and free after STOP condition. During data
transmission, I2C master can generate repeated START conditions. First START and repeated START
conditions are equivalent, function-wise.
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SDA
SCL
S
P
START condition
STOP condition
Figure 14. I2C Start and Stop Conditions
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated
by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver
must pull down the SDA line during the 9th clock pulse, signifying an acknowledge. A receiver which has been
addressed must generate an acknowledge after each byte has been received.
After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an
eighth bit which is a data direction bit (R/W). The LP55271 address is 4C hex. For the eighth bit, a “0” indicates a
WRITE and a “1” indicates a READ. The second byte selects the register to which the data will be written. The
third byte contains data to write to the selected register.
When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in
the I2C Read Cycle waveform.
MSB
ADR6
Bit7
LSB
ADR5
bit6
ADR4
bit5
ADR3
bit4
ADR2
bit3
ADR1
bit2
ADR0
bit1
R/W
bit0
2
I C SLAVE address (chip address)
Figure 15. I2C Chip Address 4C hex for LP55271
ack from slave
start
msb Chip Address lsb
ack from slave
ack from slave
w
ack
msb Register Add lsb
ack
msb
Data
w
ack
addr = 02 hex
ack
address 02
lsb
ack
stop
SCL
SDA
start
Id = 4C
data
ack
stop
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
id = chip address, 4C hex for LP55271.
Figure 16. I2C Write Cycle
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start msb Chip Address lsb w
ack from slave data from slave ack from master
ack from slave repeated start
ack from slave
rs
msb Register Add lsb
msb Chip Address lsb r
msb
Data
lsb
stop
SCL
SDA
start
Id = 4C
w ack
addr = 00 hex
ack rs
r ack Address 00 hex data ack stop
Id
Figure 17. I2C Read Cycle
SDA
10
8
7
6
1
8
2
7
SCL
1
5
3
4
9
Figure 18. I2C Timing Diagram
I2C TIMING PARAMETERS (VDD1,2 = 3.0 to 4.5V, VDDIO = 1.65V to VDD1,2)
Symbol
(1)
Parameter
1
Hold Time (repeated) START Condition
2
3
Limit (1)
Min
Max
Unit
0.6
µs
Clock Low Time
1.3
µs
Clock High Time
600
ns
4
Setup Time for a Repeated START Condition
600
5
Data Hold Time (Output direction, delay generated by LP55271)
300
900
ns
5
Data Hold Time (Input direction)
0
900
ns
6
Data Setup Time
7
Rise Time of SDA and SCL
20+0.1Cb
300
ns
8
Fall Time of SDA and SCL
15+0.1Cb
300
ns
9
Set-up Time for STOP condition
600
ns
10
Bus Free Time between a STOP and a START Condition
1.3
µs
Cb
Capacitive Load for Each Bus Line
10
ns
100
ns
200
pF
Specified by design. Not production tested.
Test Interface
The test bus can be controlled externally or internally. For the external control, the LP55271 pins VDD1,2 only
need to be powered. External control is independent on status of NRST and VDDIO pins. T1 is an input and it has
an internal 6 kΩ pull-down resistor. T2 is an output line for the test result with an internal 200 kΩ pull-down
resistor. When T1 is low, T2 is always pulled down; when T1 is high, T2 is indicating the result of the test.
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4.2V
FLASH
LED4
LED3
LED2
LED1
T1
COUNTER
PASS/
FAIL
V
500 PA
T2
Figure 19. High Level Schematic Representation of the Test Interface
The device is capable of detecting a defective unit in three cases:
• Production test 1: The LP55271 is assembled on a printed wiring board (PWB), but there is no LEDs
connected on current sink outputs. An external 4.2V test voltage is supplied on the VDD1 and VDD2 pins, from
which follows that the reset operating mode is entered with POR. Test pin T1 is pulled high. The chip will
send an acknowledge “1” onto the T2 pin if the chip is in working order; otherwise T2 stays low (0). Refer to
Test Interface Timing Diagram.
• Production test 2: The LP55271 is assembled on a PWB with the external components shown in LP55271
Block Diagram. 4.2V voltage is connected to VDD1, VDD2 and FB pins (see Figure 19), from which follows that
the reset operating mode is entered with POR. Test pin T1 is pulled high. The chip will send an acknowledge
“1” onto the T2 pin if the chip is in working order; otherwise T2 stays low (0). If the ACK is “1”, a repetitive test
pattern “0-1-0-1-0-1-0-1-0-1-0-1” is applied to T1 pin and if the LED corresponding the pattern (see Test
Interface Timing Diagram) is connected properly T2 gives “1”, otherwise T2 stays low. The last “1”
disengages the test.
• Field test: Build-in self-test through the I2C compatible control interface. The LP55271 is enabled
(NSTBY(bit) = 1, EN_BOOST(bit) = 1) and external test pins T1 and T2 are disconnected. The result can be
read through the I2C compatible control interface. LED test is enabled by writing to address 0Ch hex data
01h. Result can be read from the same address during the next I2C cycle. Note: I2C compatible interface
clock signal controls the timing of the test procedure. For that reason the clock signal frequency should be 50
kHz or less during the build-in self-test.
T1
1
2
3
4
T2
DUT
OK
LED1
OK
LED2
OK
LED3
OK
LED4
OK
FLED
OK
5
Figure 20. Test Interface Timing Diagram
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Table 10. Test Interface Timing Parameters
Symbol
Test Conditions
Limit (1)
Parameter
Min
1
Setup Time after VDD1,2 = 4.2V
1
ms
2
Clock High Time
200
µs
Clock Low Time
200
3
(1)
Unit
Max
VDD1,2 = 4.2V
4
Test Result Settling Time
5
Data Hold Time
µs
0
10
µs
10
ns
Specified by design. Not production tested.
Test Interface Characteristics
Limits in standard typeface are for TJ = 25ºC.
Parameter (1)
Symbol
Test Conditions
Min
Typ
Max
Unit
0.5
V
Logic Input T1
VIL
Input Low Level
VIH
Input High Level
VDD1,2 = 4.2V
1.2
V
Logic Output T2
VOL
Output Low Level
VDD1,2 = 4.2V, IOUT = 3 mA
(pull-up current)
VOH
Output High Level
VDD1,2 = 4.2V, IOUT = -3 mA
(pull-down current)
0.3
VDD1,2 0,5
0.5
V
3.9
V
500
µA
Internal Current Sink
ISINK
Sink Current
VDD1,2 = 4.2V
Connectivity Test Pass Range
VPASS1
Voltage Over the Internal Current
Sink; Low Level
VPASS2
Voltage Over the Internal Current
Sink; High Level
VPASS3
Voltage Over the Internal Current
Sink; Low Level
VPASS4
Voltage Over the Internal Current
Sink; High Level
(1)
20
0.10
Production test cases
VDD1,2 = 4.2V
VOUT = 3.9V to 4.2V
-50
V
+50
%
+10
%
+30
%
2.90
-10
V
0.40
Field test cases
VDD1,2 = 3.0V to 4.2V
VOUT = 5.0V ± 5%
-30
V
3.95
-10
V
+10
%
Specified by design. Not production tested.
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APPLICATION INFORMATION
Recommended External Components
OUTPUT CAPACITOR, COUT1, COUT2
The output capacitors COUT1, COUT2 directly affect the magnitude of the output ripple voltage. In general, the
higher the value of COUT, the lower the output ripple magnitude. Multilayer ceramic capacitors with low ESR are
the best choice. At the lighter loads, the low ESR ceramics offer a much lower VOUT ripple that the higher ESR
tantalums of the same value. At the higher loads, the ceramics offer a slightly lower VOUT ripple magnitude than
the tantalums of the same value. However, the dv/dt of the VOUT ripple with the ceramics is much lower that the
tantalums under all load conditions. Capacitor voltage rating must be sufficient, 10V is recommended
Some ceramic capacitors, especially those in small packages, exhibit a strong capacitance reduction
with the increased applied voltage. The capacitance value can fall to below half of the nominal
capacitance. Too low output capacitance can make the boost converter unstable.
INPUT CAPACITOR, CIN
The input capacitor CIN directly affects the magnitude of the input ripple voltage and to a lesser degree the VOUT
ripple. A higher value CIN will give a lower VIN ripple. Capacitor voltage rating must be sufficient, 10V or greater is
recommended.
OUTPUT DIODE, D1
The output diode for a boost converter must be chosen correctly depending on the output voltage and the output
current. The diode must be rated for a reverse voltage greater than the output voltage used. The average current
rating must be greater than the maximum load current expected, and the peak current rating must be greater
than the peak inductor current (~1.7A at maximum load). A Schottky diode should be used for the output diode.
Schottky diodes with a low forward voltage drop (VF) and fast switching speeds are ideal for increasing efficiency
in portable applications. Do not use ordinary rectifier diodes, since slow switching speeds and long recovery
times cause the efficiency and the load regulation to suffer. In Schottky barrier diodes reverse leakage current
increases quickly with the junction temperature. Therefore, reverse power dissipation and the possibility of
thermal runaway has to be considered when operating under high temperature conditions. Examples of suitable
diodes are Diodes Incorporated type DFLS220L, ON Semiconductor type MBRA210LT3 and Philips type
PMEG1020.
INDUCTOR, L1
The LP55271 high switching frequency enables the use of the small surface mount inductor. A 4.7 µH shielded
inductor is suggested for 2 MHz switching frequency. The inductor should have a saturation current rating higher
than the peak current it will experience during circuit operation (~1.7A at maximum load). Less than 300 mΩ ESR
is suggested for high efficiency. Open core inductors cause flux linkage with circuit components and interfere
with the normal operation of the circuit. This should be avoided. For high efficiency, choose an inductor with a
high frequency core material such as ferrite to reduce the core losses. To minimize radiated noise, use a toroid,
pot core or shielded core inductor. The inductor should be connected to the SW1 and SW2 pins as close to the
IC as possible. Example of a suitable inductor is TDK type VLCF5020T-4R7N1R7-1.
Table 11. Recommended External Components
Symbol
Symbol Explanation
Value
Unit
Type
CVDD1
VDD1 Bypass Capacitor
100
nF
Ceramic, X5R
CVDD2
VDD2 Bypass Capacitor
100
nF
Ceramic, X5R
COUT1,2
Output Capacitors from FB to GND
2 x 10 µF ± 10%
µF
Ceramic, X5R, 10V
CIN
Input Capacitor from Battery Voltage to GND
10 ± 10%
µF
Ceramic, X5R, 10V
CVDDIO
VDD_IO Bypass Capacitor
100
nF
Ceramic, X5R
CVDDA
VDDA Bypass Capacitor
4.7
µF
Ceramic, X5R, 6.3V
C1,2
Audio Input Capacitors
47
nF
Ceramic, X5R
RT
Oscillator Frequency Bias Resistor
82
kΩ
1%
RF
Flash Current Set Resistor for 370 mA Sink Current
1300
Ω
1%
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Table 11. Recommended External Components (continued)
Symbol
Symbol Explanation
Value
Unit
Type
CVREF
Reference Voltage Capacitor, between VREF and GND
100
nF
Ceramic, X5R
L1
Boost Converter Inductor
4.7
µH
Shielded, low ESR,
ISAT ~1.7A
D1
Rectifying Diode, VF at maxload
0.35
V
Schottky diode
Flash LED
User defined
LED1 to LED4
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Control Registers
Table 12. LP55271 Control Registers and Default Values
ADDR
(HEX)
REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
00
LED Control Register
safety_time
flash_sync
en_flash
en_torch
en_led1
en_led2
en_led3
en_led4
0
0
0
0
0
0
0
0
01
LED1
led1[7]
led1[6]
led1[5]
led1[4]
led1[3]
led1[2]
led1[1]
led1[0]
0
0
0
0
0
0
0
0
led2[7]
led2[6]
led2[5]
led2[4]
led2[3]
led2[2]
led2[1]
led2[0]
0
0
0
0
0
0
0
0
led3[6]
led3[5]
led3[4]
led3[3]
led3[2]
led3[1]
led3[0]
02
LED2
03
LED3
led3[7]
0
0
0
0
0
0
0
0
04
LED4
led4[7]
led4[6]
led4[5]
led4[4]
led4[3]
led4[2]
led4[1]
led4[0]
0
0
0
0
0
0
0
0B
ENABLES
nstby
en_boost
en_autoload
freq_sel
0
0
1
0
0C
LED Test Control
led1_ok
led2_ok
led3_ok
led4_ok
flashled_ok
en_test
r/o
r/o
r/o
r/o
r/o
0
boost[3]
boost[2]
boost[1]
0
1
1
1
dc_freq
en_agc
en_sync
speed_ctrl[1]
speed_ctrl[2]
0
0
0
0
0
0D
Boost Output
2A
Audio Sync Control1
gain_sel[2]
gain_sel[1]
gain_sel[0]
0
0
0
0
2B
Audio Sync Control2
threshold[3]
threshold[2]
threshold[1]
threshold[0]
0
0
1
1
boost[0]
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Product Folder Links: LP55271
23
LP55271
SNVS460A – SEPTEMBER 2006 – REVISED MAY 2013
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REVISION HISTORY
Changes from Original (April 2013) to Revision A
•
24
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 23
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Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LP55271
PACKAGE OPTION ADDENDUM
www.ti.com
29-Aug-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LP55271TL/NOPB
ACTIVE
DSBGA
YZR
30
TBD
Call TI
Call TI
-30 to 85
D55B
LP55271TLX/NOPB
ACTIVE
DSBGA
YZR
30
TBD
Call TI
Call TI
-30 to 85
D55B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
29-Aug-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
YZR0030xxx
0.600±0.075
D
E
TLA30XXX (Rev C)
4215057/A
NOTES:
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
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12/12
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