LP5550SQX

LP5550 www.ti.com SNVS378G – OCTOBER 2005 – REVISED APRIL 2013 LP5550 PowerWise™ Technology Compliant Energy Management Unit Check for Samples: LP5550 FEATURES DESCRIPTION • The LP5550 is a PWI 1.0 compliant Energy Management System for reducing power consumption of stand-alone mobile phone processors such as base-band or applications processors. 1 2 • • • • • • • Supports High-Efficiency PowerWise Technology Adaptive Voltage Scaling PWI Open Standard Interface for System Power Management Digitally Controlled Intelligent Voltage Scaling 1 MHz PWM Switching Frequency Auto or PWI Controlled PFM Mode Transition Internal Soft Start/Startup Sequencing 3 Programmable LDOs for I/O, PLL, and Memory Retention Supply Generation Power OK Output APPLICATIONS • • • • • GSM/GPRS/EDGE & UMTS Cellular Handsets Hand-Held Radios PDAs Battery Powered Devices Portable Instruments The LP5550 contains an advanced, digitally controlled switching regulator for supplying variable voltage to processor core and memory. The device also incorporates 3 programmable LDO-regulators for powering I/O, PLLs and maintaining memory retention in shutdown-mode. The device is controlled via the PWI open-standard interface. The LP5550 operates cooperatively with PowerWise technology compatible processors to optimize supply voltages adaptively over process and temperature variations or dynamically using frequency/voltage pre-characterized look-up tables. System Diagram VBAT LP5550 SoC + LDO3 ENABLE Embedded Memory Processor Core AVS/DVS domain SW SW RESETN VO3 FB AVS SCLK Slave Power Controller (SPC) Hardware Performance Monitor (HPM) SPWI PWROK PWI Advanced Power Controller (APC) VO1 LDO1 PLL VO2 I/O Bus LDO2 Figure 1. System Diagram 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2013, Texas Instruments Incorporated LP5550 SNVS378G – OCTOBER 2005 – REVISED APRIL 2013 www.ti.com VO3 PWROK VFB DGND VO3 DGND VFB ABC VO1 VO1 AGND ENABLE SCLK VO2 Top View SPWI VBAT1 VO2 RESETN VBAT1 RESETN ENABLE SPWI VBAT2 PWROK ABC AGND SCLK SWGND SW VBATSW VBATSW SW SWGND VBAT2 Connection Diagrams Bottom View Figure 2. 16-Pin WQFN Package See Package Number RGH0016A Typical Application 1 4.7 PF SPWI RESETN VO2 VBAT1 SCLK 16 ENABLE VBATT VO1 AGND 2.2 PF LP5550SQ DGND VFB PWROK VBATSW VO3 SW SWGND VBAT2 1 PF VBATT VBATT 3.0V - 5.5V + - 10 PF 0.1 PF 10 PH 10 PF Figure 3. Typical Application Circuit Pin Descriptions Pin No. 2 Name I/O Type Description 1 SCLK I D PowerWise Interface (PWI) clock input 2 SPWI I/O D PowerWise Interface (PWI) bi-directional data 3 RESETN I D Reset, active low 4 VO2 O A LDO2 output, for supplying the I/O voltage on the SoC 5 VBAT1 P P Battery supply voltage 6 VO1 O A LDO1 output, for supplying a fixed voltage to a PLL etc. on the SoC 7 DGND G G Digital ground 8 PWROK O D Power OK, active high output signal Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LP5550 LP5550 www.ti.com SNVS378G – OCTOBER 2005 – REVISED APRIL 2013 Pin Descriptions (continued) Pin No. I/O Type 9 VBATSW Name P P Battery supply voltage for switching regulator Description 10 SW O A Switcher pin connected to coil 11 SWGND G G Switcher ground 12 VBAT2 P P Battery supply voltage 13 VO3 O A LDO3 output, on-chip memory supply voltage 14 VFB I A Switcher output voltage for supplying SoC core logic 15 AGND G G Analog Ground 16 ENABLE I D Enable, active high A: Analog Pin D: Digital Pin I: Input Pin O: Output Pin I/O: Input/Output Pin P: Power Pin G: Ground Pin These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) (4) VBAT1, VBAT2, VBATSW -0.3 to +6.0V VO1, VO2, VO3 to GND -0.3 to +VBAT1+0.3V ENABLE, RESETN, VFB, SW, SPWI, SCLK, PWROK -0.3 to VBAT2+0.3V DGND, AGND, SWGND to GND SLUG ±0.3V Junction Temperature (TJ-MAX) 150°C Storage Temperature Range -65°C to 150°C Maximum Continuous Power Dissipation (PD-MAX) (5) 1.0 W Maximum Lead Temperature (Soldering) See (5) ESD Rating (1) (2) (3) (4) (5) (6) (6) Human Body Model All pins 2.0kV Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits and associated test conditions, see the Electrical Characteristics tables. All voltages are with respect to the potential at the GND pin. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. For detailed soldering specifications and information, please refer to Application Note AN-1187 : Leadless Leadframe Package (LLP) (SNOA401). The amount of Absolute Maximum power dissipation allowed for the device depends on the ambient temperature and can be calculated using the formula P = (TJ – TA)/θJA, (1) where TJ is the junction temperature, TA is the ambient temperature, and JA is the junction-toambient thermal resistance. Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design.Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ=150°C (typ.) and disengages at TJ=140°C (typ.). The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LP5550 3 LP5550 SNVS378G – OCTOBER 2005 – REVISED APRIL 2013 www.ti.com Operating Ratings (1) (2) VBAT1, VBAT2, VBATSW 3.0V to 5.5V −40°C to +125°C Junction Temperature (TJ) Range Ambient Temperature (TA) Range (3) (1) −40°C to +85°C Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits and associated test conditions, see the Electrical Characteristics tables. All voltages are with respect to the potential at the GND pin. In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAXOP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). (2) (3) Thermal Properties (4) Junction-to-Ambient Thermal Resistance (θJA) (4) 39.8°C/W Junction-to-ambient thermal resistance (θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the JEDEC standard JESD51-7. The test board is a 4-layer FR-4 board measuring 102mm x 76mm x 1.6mm with a 2x1 array of thermal vias. The ground plane on the board is 50mm x 50mm. Thickness of copper layers are 36µm/18µm/18µm/36µm (1.5oz/1oz/1oz/1.5oz). Ambient temperature in simulation is 22°C, still air. Power dissipation is 1W.Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design.The value of θJA of this product can vary significantly, depending on PCB material, layout, and environmental conditions. In applications where high maximum power dissipation exists (high VIN, high IOUT), special care must be paid to thermal dissipation issues. For more information on these topics, please refer to Application Note AN-1187: Leadless Leadframe Package (LLP) (SNOA401) and the Power Efficiency and Power Dissipation section of this datasheet. General Electrical Characteristics Unless otherwise noted, VBAT1,2,SW, RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C (1) (2) (3) Symbol IQ TSD (1) (2) Typ Max Unit Shutdown Supply current Parameter VBAT1,2,SW = 2.0V, all circuits off. Conditions Min 1 6 µA Sleep State Supply Current VBAT1,2,SW = 3.6V, LDO3 (VO3) on, PWI on. All other circuits off. 70 85 µA Acitve State Supply Current (No load, PFM mode) VBAT1,2,SW = 3.6V, LDOs 1 and 2 on, Switcher on, PWI on. 140 165 µA Thermal Shutdown Threshold 160 Thermal Shutdown Hysteresis 10 °C All voltages are with respect to the potential at the GND pin. Min and Max limits are ensured by design, test, or statistical analysis. Typical (Typ) numbers are not specified, but do represent the most likely norm. Unless otherwise specified, conditions for Typ specifications are: VIN = 3.6V and TA = 25°C control. Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics (3) LDO1 (PLL/Fixed Voltage) Characteristics Unless otherwise noted, VBAT1,2,SW, RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C (1) (2) (3) Symbol Min Typ Max Unit Output Voltage Accuracy 1mA ≤ IOUT ≤ 100mA, VOUT = 1.2V, 3.0V ≤ VBAT1,2,SW ≤ 5.5V -3% 1.2 3% V VOUT Range Programmable Output Voltage Range 0µA ≤ IOUT ≤ 100mA, Programming Resolution = 100mV 0.7 1.2 2.2 V IOUT Recommended Output Current 3.0V ≤ VBAT1,2,SW ≤ 5.5V Short Circuit Current Limit VOUT = 0V Quiescent Current IOUT = 0mA (4) VOUT Accuracy IQ (1) (2) (3) (4) 4 Parameter Conditions 100 350 35 45 mA µA All voltages are with respect to the potential at the GND pin. Min and Max limits are ensured by design, test, or statistical analysis. Typical (Typ) numbers are not specified, but do represent the most likely norm. Unless otherwise specified, conditions for Typ specifications are: VIN = 3.6V and TA = 25°C control. Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics Quiescent current for LDO1, LDO2, and LDO3 do not include shared functional blocks such as the bandgap reference. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LP5550 LP5550 www.ti.com SNVS378G – OCTOBER 2005 – REVISED APRIL 2013 LDO1 (PLL/Fixed Voltage) Characteristics (continued) Unless otherwise noted, VBAT1,2,SW, RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C(1)(2)(3) Symbol ΔVOUT Parameter Conditions Max Unit 0.125 %/V 0.0085 %/mA -0.125 Load Regulation VIN = 3.6V, 1mA ≤ IOUT ≤ 100mA -0.0085 Line Transient Regulation 3.6V ≤ VIN ≤ 3.9V, TRISE,FALL = 10 µs 27 mV Load Transient Regulation VIN = 3.6V, 10mA ≤ IOUT ≤ 90 mA, TRISE,FALL = 100 ns 86 mV 0.103 mVRMS 56 dB Output Noise Voltage 10Hz ≤ f ≤ 100kHz, COUT = 2.2µF Power Supply Ripple Rejection Ratio f = 1kHz, COUT = 2.2µF COUT Output Capacitance Output Capacitor ESR 0µA ≤ IOUT ≤ 100mA Start-Up Time from Shut-down COUT = 1µF, IOUT = 100mA tSTART-UP Typ Line Regulation PSRR eN Min 3.0V ≤ VBAT1,2,SW ≤ 5.5V, IOUT = 50mA f = 10kHz, COUT = 2.2µF 36 1 2.2 5 dB 20 µF 500 mΩ 54 µs LDO2 (I/O Voltage) Characteristics Unless otherwise noted, VBAT1,2,SW , RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C (1) (2) (3) Symbol Min Typ Max Unit Output Voltage Accuracy 1mA ≤ IOUT ≤ 250mA, VOUT = 2.5V, VOUT +0.4V ≤ VBAT1,2,SW ≤ 5.5V -3% 2.5 3% V VOUT Range Programmable Output Voltage Range 0µA ≤ IOUT ≤ 250mA, 1.5-2.3V =100mV step, 2.5V, 2.8V, 3.0V and 3.3V 1.5 3.3 3.3 V IOUT Recommended Output Current VOUT +0.4V ≤ VBAT1,2,SW ≤ 5.5V Output Current Limit VOUT = 0V Dropout Voltage (4) IOUT = 125mA 70 260 mV Quiescent Current IOUT = 0mA (5) 55 60 µA Line Regulation VOUT +0.4V ≤ VBAT1,2,SW ≤ 5.5V, IOUT = 125mA -0.125 0.125 %/V Load Regulation VIN = 3.6V, 1mA ≤ IOUT ≤ 250mA -0.011 0.011 %/mA Line Transient Regulation 3.6V ≤ VIN ≤ 3.9V, TRISE,FALL = 10 us 24 mV Load Transient Regulation VIN = 3.6V, 25mA ≤ IOUT ≤ 225 mA, TRISE,FALL = 100 ns 246 mV Output Noise Voltage 10Hz ≤ f ≤ 100kHz, COUT = 4.7µF 0.120 mVRMS Power Supply Ripple Rejection Ratio f = 1kHz, COUT = 4.7µF 46 dB f = 10kHz, COUT = 4.7µF 34 VOUT Accuracy IQ ΔVOUT eN PSRR COUT Parameter Output Capacitance Output Capacitor ESR tSTART-UP (1) (2) (3) (4) (5) Start-Up Time from Shut-down Conditions 0µA ≤ IOUT ≤ 250mA COUT = 4.7µF, IOUT = 250mA 250 mA 740 2 4.7 5 20 µF 500 mΩ 144 µs All voltages are with respect to the potential at the GND pin. Min and Max limits are ensured by design, test, or statistical analysis. Typical (Typ) numbers are not specified, but do represent the most likely norm. Unless otherwise specified, conditions for Typ specifications are: VIN = 3.6V and TA = 25°C control. Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value. This specification does not apply in cases it implies operation with an input voltage below the 3.0V minimum appearing under Operating Ratings. For example, this specification does not apply for devices having 1.5V outputs because the specification would imply operation with an input voltage at or about 1.5V Quiescent current for LDO1, LDO2, and LDO3 do not include shared functional blocks such as the bandgap reference. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LP5550 5 LP5550 SNVS378G – OCTOBER 2005 – REVISED APRIL 2013 www.ti.com LDO3 (Memory Retention Voltage) Characteristics Unless otherwise noted, VBAT1,2,SW , RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C (1) (2) (3) Symbol Parameter VOUT Accuracy Output Voltage Accuracy Min Typ Max Unit Active state: Tracking VAVS IOUT ≤ 50mA,VOUT = 1.2V, 3.0V ≤ VBAT1,2,SW ≤ 5.5V Conditions -3% 1.2 3% V Sleep state: Memory retention voltage regulation IOUT ≤ 5mA,VOUT = 1.2V, 3.0V ≤ VBAT1,2,SW ≤ 5.5V -3% 1.2 3% V VOFFSET Active State Buffer offset (= VO3-VFB) IOUT = 50 mA, VOUT = 0.6 V 13 mV IOUT = 50 mA, VOUT = 1.2V 28 mV VOUT Range Programmable Output Voltage Range (Sleep state) 0µA ≤ IOUT ≤ 5mA, Programming Resolution = 50mV 1.2 1.35 V Active mode, IOUT = 10µA (4) 33 44 µA Sleep mode, IOUT = 10µA (4) 10 16 µA Recommended Output Current, Active state 3.0V ≤ VBAT1,2,SW ≤ 5.5V 50 Recommended Output Current, Sleep state 3.0V ≤ VBAT1,2,SW ≤ 5.5V 5 Short Circuit Current Limit, Active state VOUT = 0V eN Output Voltage Noise 10Hz ≤ f ≤ 100kHz, COUT = 1µF PSRR Power Supply Ripple Rejection Ratio f = 217Hz, COUT = 1.0µF COUT Output Capacitance IQ Quiescent Current IOUT Output Capacitor ESR (1) (2) (3) (4) 0.6 mA 230 0µA ≤ IOUT ≤ 5mA 0.7 0.158 mVRMS 36 dB 1 5 2.2 µF 500 mΩ All voltages are with respect to the potential at the GND pin. Min and Max limits are ensured by design, test, or statistical analysis. Typical (Typ) numbers are not specified, but do represent the most likely norm. Unless otherwise specified, conditions for Typ specifications are: VIN = 3.6V and TA = 25°C control. Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics Quiescent current for LDO1, LDO2, and LDO3 do not include shared functional blocks such as the bandgap reference. Switcher (Core Voltage) Characteristics Unless otherwise noted, VBAT1,2,SW , RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C (1) (2) (3) Symbol Parameter VOUT Accuracy Conditions IOUT = 150 mA, VOUT = 1.2V, 3.0V < VBAT1,2,SW