LP5900TL-2.6EV

User's Guide SNVA123C – September 2005 – Revised April 2013 AN-1396 LP5900 DSBGA Evaluation Board Information 1 Introduction This evaluation board is designed to enable the evaluation of the LP5900 voltage regulator. Each board is assembled and tested in the factory. This evaluation board has the DSBGA-4 bump package mounted. 2 General Description The LP5900 is a linear regulator capable of suppling 150 mA output current. Designed to meet the requirements of RF/Analog circuits, the LP5900 provides low device noise, high PSRR, low quiescent current, and low line transient response. Using new innovative design techniques the LP5900 offers classleading noise performance without a noise bypass capacitor. The device has been designed to work with 0.47 µF input and output ceramic capacitors down to 0603 component size. 3 Operation The input voltage, applied between VIN and GND, should be at least 1.0 V greater than VOUT and no more than 5.5 V. The minimum operating voltage is 2.5 V. Loads can be connected to VOUT with reference to GND. VOUT and VIN sense pins are provided on the board to allow accurate measurements directly onto the input and output pins of the device, eliminating any voltage drop on the PCB traces or connecting wires to the load. ON/OFF control is provided by a logic signal on the VEN pin. A minimum of 1.2 V is required at this pin to enable the LDO. The LDO will be shutdown when the VEN pin is set to 0.4 V or less. VIN and VEN can be tied together in applications where the LP5900 is operated continuously from the battery. However, if ON/OFF control is required, the VEN pin should be driven from a separate signal to ensure correct operation of the fast start-up circuit. The device has a 1MΩ internal resistor from VEN to GND. All trademarks are the property of their respective owners. SNVA123C – September 2005 – Revised April 2013 Submit Documentation Feedback AN-1396 LP5900 DSBGA Evaluation Board Information Copyright © 2005–2013, Texas Instruments Incorporated 1 Schematic Diagram 4 www.ti.com Schematic Diagram The evaluation board schematic is shown in Figure 1. VIN sense VOUT sense (A2) VIN VIN (B2) 0.47 PF CIN LP5900 (A1) VEN VOUT VOUT 0.47 PF COUT VEN GND (B1) GND Figure 1. Evaluation Board Schematic 5 PCB Layout The layout of the evaluation board is shown in Figure 2. Figure 2. Evaluation Board Component and Pin Layout Board Size:- 21mm x 21mm 2 AN-1396 LP5900 DSBGA Evaluation Board Information SNVA123C – September 2005 – Revised April 2013 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Hardware www.ti.com 6 Hardware Designator Value Amount Footprint U1 LP5900 1 YZR0004CDA CIN 0.47µF 1 0603 X7R, X5R COUT 0.47µF 1 0603 X7R, X5R Test Pins 6 IN, OUT, IN SENSE, OUT SENSE, ON/OFF, GND SNVA123C – September 2005 – Revised April 2013 Submit Documentation Feedback Note AN-1396 LP5900 DSBGA Evaluation Board Information Copyright © 2005–2013, Texas Instruments Incorporated 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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