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Design
LP5907-Q1
SNVSA34E – SEPTEMBER 2014 – REVISED DECEMBER 2019
LP5907-Q1 Automotive 250-mA, Ultra-Low-Noise, Low-IQ LDO
1 Features
3 Description
•
The LP5907-Q1 is a low-noise LDO that can supply
250 mA of output current. Designed to meet the
requirements of RF and analog circuits, the LP5907Q1 provides low noise, high PSRR, low quiescent
current, and low line or load transient response
figures. Using new innovative design techniques, the
LP5907-Q1 offers class-leading noise performance
without a noise bypass capacitor and the ability for
remote output capacitor placement.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 qualified for automotive applications:
– Temperature grade 1: –40°C to 125°C, TA
Input voltage range: 2.2 V to 5.5 V
Output voltage range: 1.2 V to 4.5 V
Stable with 1-µF ceramic input and output
capacitors
No noise bypass capacitor required
Remote output capacitor placement
Thermal-overload and short-circuit protection
Output current: 250 mA
Low output voltage noise: < 6.5 µVRMS
PSRR: 82 dB at 1 kHz
Output voltage tolerance: ±2%
Virtually zero IQ (disabled): < 1 µA
Very low IQ (enabled): 12 µA
Start-up time: 80 µs
Low dropout: 120 mV (typical)
–40°C to 125°C junction temperature range for
operation
The device is designed to work with a 1-µF input and
a 1-µF output ceramic capacitor (no separate noise
bypass capacitor is required).
This device is available with fixed output voltages
from 1.2 V to 4.5 V in 25-mV steps. Contact Texas
Instruments Sales for specific voltage option needs.
Device Information(1)
PART NUMBER
LP5907-Q1
PACKAGE
BODY SIZE (NOM)
SOT-23 (5)
2.90 mm × 1.60 mm
X2SON (4)
1.00 mm x 1.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
ADAS cameras and radar
Automotive infotainment
Telematics systems
Navigation systems
Simplified Schematic
INPUT
IN
1 PF
ENABLE
OUT
LP5907-Q1
OUTPUT
1 PF
EN
GND
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP5907-Q1
SNVSA34E – SEPTEMBER 2014 – REVISED DECEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
5
5
5
5
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Output and Input Capacitors .....................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 14
8
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application .................................................. 15
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Examples................................................... 19
11 Device and Documentation Support ................. 20
11.1
11.2
11.3
11.4
11.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (December 2018) to Revision E
Page
•
Changed device status from advance information to production data for DQN (X2SON) package....................................... 1
•
Changed DQN values and added RθJC(top) parameter to Thermal Information table .............................................................. 5
•
Added X2SON rows to ΔVOUT parameter in Electrical Characteristics table.......................................................................... 6
Changes from Revision C (May 2018) to Revision D
Page
•
Added DQN (X2SON) package to document as Preview ..................................................................................................... 1
•
Added Layout Example for the DQN Package figure........................................................................................................... 19
Changes from Revision B (September 2016) to Revision C
Page
•
Added ESD classification level sub-bullets to Features section ............................................................................................ 1
•
Changed DBV values in Thermal Information table .............................................................................................................. 5
•
Deleted footnote 1 from Thermal Information table ............................................................................................................... 5
•
Added Overshoot on start-up with EN row to Electrical Characteristics table ...................................................................... 7
•
Changed Device Comparison table: changed table title, added new rows and new data, moved to new sub-section ...... 13
Changes from Revision A (June 2016) to Revision B
Page
•
Changed wording of title ........................................................................................................................................................ 1
•
Changed "Low Output Voltage Noise: < 10 µVRMS" to "Low Output Voltage Noise: < 6.5 µVRMS"......................................... 1
•
Changed items listed in Applications ..................................................................................................................................... 1
•
Changed wording of first sentence of Description ................................................................................................................. 1
2
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SNVSA34E – SEPTEMBER 2014 – REVISED DECEMBER 2019
Changes from Original (September 2014) to Revision A
Page
•
Added Features bullets re: automotive .................................................................................................................................. 1
•
Added top navigator icon for TI Designs ................................................................................................................................ 1
•
Changed " linear regulator" to "LDO" ..................................................................................................................................... 1
•
Changed storage temperature from Handling Ratings to Abs Max table; replaced Handling Ratings with ESD
Ratings per new format ......................................................................................................................................................... 5
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LP5907-Q1
SNVSA34E – SEPTEMBER 2014 – REVISED DECEMBER 2019
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5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
DQN Package
4-Pin X2SON
Bottom View
OUT GND
IN
1
GND
2
5 OUT
1
2
5
EN
3
4 N/C
4
3
IN
EN
Pin Functions
PIN
I/O
DESCRIPTION
3
I
Enable input. A low voltage (< VIL) on this pin turns the regulator off and
discharges the output pin to GND through an internal 230-Ω pulldown resistor. A
high voltage (> VIH) on this pin enables the regulator output. This pin has an
internal 1-MΩ pulldown resistor to hold the regulator off by default.
2
2
–
Common ground
1
4
I
Input voltage supply. Connect a 1-µF capacitor at this input.
N/C
4
—
–
No internal electrical connection.
OUT
5
1
O
Regulated output voltage. Connect a minimum 1-µF low-ESR capacitor to this
pin. Connect this output to the load circuit. An internal 230-Ω (typical) pulldown
resistor prevents a charge remaining on VOUT when the regulator is in the
shutdown mode (VEN low).
NAME
SOT23-5
X2SON-4
EN
3
GND
IN
4
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SNVSA34E – SEPTEMBER 2014 – REVISED DECEMBER 2019
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
VIN
Input voltage
MIN
MAX
UNIT
–0.3
6
V
VOUT
Output voltage
–0.3
See
VEN
Enable input voltage
–0.3
6
Continuous power dissipation (4)
TJMAX
Junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
(4)
(3)
V
V
Internally limited
–65
W
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to the GND pin.
Abs Max VOUT is the VIN + 0.3 V or 6 V, whichever is less.
Internal thermal shutdown circuitry protects the device from permanent damage.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC
Q100-002 (1)
V(ESD)
(1)
Electrostatic discharge
Charged-device model (CDM), per AEC
Q100-011
All pins
±2000
Corner pins (1,3,4,5)
±1000
Other pin (2)
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
VIN
Input supply voltage
2.2
5.5
VEN
Enable input voltage
0
5.5
V
IOUT
Output current
0
250
mA
TJ-MAX-OP
Operating junction temperature (3)
–40
125
°C
(1)
(2)
(3)
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to the GND pin.
TJ-MAX-OP = [TA(MAX) + (PD(MAX) × RθJA )].
6.4 Thermal Information
LP5907-Q1
THERMAL METRIC (1)
DBV (SOT-23)
DQN (X2SON-4)
5 PINS
4-PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
186.9
197.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
112.3
139.4
°C/W
RθJB
Junction-to-board thermal resistance
52.3
130.2
°C/W
ψJT
Junction-to-top characterization parameter
27.5
6.4
°C/W
ψJB
Junction-to-board characterization parameter
51.8
130.2
°C/W
RθJC(top)
Junction-to-case (bottom) thermal resistance
—
139.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SNVSA34E – SEPTEMBER 2014 – REVISED DECEMBER 2019
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6.5 Electrical Characteristics
VIN = VOUT(NOM) + 1 V, VEN = 1.2 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF (unless otherwise noted) (1) (2) (3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GENERAL
VIN
Input voltage
Output voltage tolerance
ΔVOUT
ILOAD
TA = 25°C
2.2
5.5
VIN = (VOUT(NOM) + 1 V) to
5.5 V,
IOUT = 1 mA to 250 mA
SOT-23 package
VOUT ≥ 1.8 V
–2
2
VOUT < 1.8 V
–3
3
VIN = (VOUT(NOM) + 1 V) to
5.5 V,
IOUT = 1 mA to 250 mA
X2SON package
VOUT > 2.5 V
–2
2
VOUT ≤ 2.5 V
–3
3
Line regulation
VIN = (VOUT(NOM) + 1 V) to 5.5 V,
IOUT = 1 mA
Load regulation
IOUT = 1 mA to 250 mA
0.02
0
VEN = 1.2 V, IOUT = 0 mA
Quiescent current (4)
IQ
IG
Ground current (5)
VDO
Dropout voltage (6)
ISC
Short-circuit current limit
PSRR
Power-supply rejection ratio (8)
12
25
VEN = 1.2 V, IOUT = 250 mA
250
425
VEN = 0.3 V (Disabled)
0.2
1
VEN = 1.2 V, IOUT = 0 mA
14
IOUT = 100 mA
50
TA = 25°C (7)
250
500
f = 100 Hz, IOUT = 20 mA
90
f = 1 kHz, IOUT = 20 mA
82
f = 10 kHz, IOUT = 20 mA
65
f = 100 kHz, IOUT = 20 mA
60
IOUT = 1 mA
10
IOUT = 250 mA
6.5
Output noise voltage (8)
BW = 10 Hz to 100 kHz
RAD
Output automatic discharge
pulldown resistance
VEN < VIL (output disabled)
230
Thermal shutdown
TJ rising
160
Thermal hysteresis
TJ falling from shutdown
mA
µA
µA
250
eN
TSD
%/mA
250
IOUT = 250 mA
%VOUT
%/V
0.001
Output load current
V
mV
mA
dB
µVRMS
Ω
°C
15
LOGIC INPUT THRESHOLDS
VIL
Low input threshold
VIN = 2.2 V to 5.5 V,
VEN falling until the output is disabled
VIH
High input threshold
VIN = 2.2 V to 5.5 V,
VEN rising until the output is enabled
IEN
Input current at EN pin (9)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
6
VEN = 5.5 V and VIN = 5.5 V
VEN = 0 V and VIN = 5.5 V
0.4
1.2
V
V
5.5
0.001
µA
All voltages are with respect to the device GND terminal, unless otherwise stated.
Minimum and maximum limits are ensured through test, design, or statistical correlation over the junction temperature (TJ) range of
–40°C to 125°C, unless otherwise stated. Typical values represent the most likely parametric norm at TA = 25°C, and are provided for
reference purposes only.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =
125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the
part/package in the application RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX). See Application and
Implementation.
Quiescent current is defined here as the difference in current between the input voltage source and the load at VOUT.
Ground current is defined here as the total current flowing to ground as a result of all input voltages applied to the device.
Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its
nominal value.
Short-circuit current (ISC) for the LP5907-Q1 is equivalent to current limit. To minimize thermal effects during testing, ISC is measured
with VOUT pulled to 100 mV below its nominal voltage.
This specification is verified by design.
There is a 1-MΩ resistor between EN and ground on the device.
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Electrical Characteristics (continued)
VIN = VOUT(NOM) + 1 V, VEN = 1.2 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF (unless otherwise noted)(1)(2)(3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TRANSIENT CHARACTERISTICS
Line transient
ΔVOUT
–1
VIN = (VOUT(NOM) + 1.6 V) to
(VOUT(NOM) + 1.6 V) in 30 µs
IOUT = 1 mA to 250 mA in 10 µs
Load transient (8)
Overshoot on start-up
tON
VIN = (VOUT(NOM) + 1 V) to
(VOUT(NOM) + 1.6 V) in 30 µs
(8)
1
–40
IOUT = 250 mA to 1 mA in 10 µs
(8)
mV
40
Stated as a percentage of VOUT(NOM)
5%
Overshoot on start-up with EN (8)
Stated as a percentage of VOUT(NOM), VIN =
VOUT + 1 V to 5.5 V, 0.7 µF < COUT < 10 µF, 0
mA < IOUT < 250 mA, EN rising until the output
is enabled
1%
Turnon time
From VEN > VIH to VOUT = 95% of VOUT(NOM),
TA = 25°C
80
150
µs
6.6 Output and Input Capacitors
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(2)
CIN
Input capacitance
COUT
Output capacitance (2)
ESR
Output/input capacitance (2)
(1)
(2)
Capacitance for stability
MIN (1)
TYP
0.7
1
0.7
1
5
MAX
UNIT
10
500
µF
mΩ
The minimum capacitance should be greater than 0.5 μF over the full range of operating conditions. The capacitor tolerance should be
30% or better over the full temperature range. The full range of operating conditions for the capacitor in the application should be
considered during device selection to ensure this minimum capacitance specification is met. X7R capacitors are recommended however
capacitor types X5R, Y5V and Z5U may be used with consideration of the application and conditions.
This specification is verified by design.
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6.7 Typical Characteristics
VIN = 3.7 V, VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, TA = 25°C (unless otherwise noted)
1
16
14
0.9
10
VEN (V)
IQ( A)
12
8
6
0.8
0.7
4
0.6
2
VIH Rising
VIL Falling
0
2.3
2.8
3.3
3.8 4.3
VIN(V)
4.8
5.3
0.5
5.8
2
2.5
3
3.5
SVA-30180569
4
VIN (V)
4.5
5
5.5
6
D001
Figure 2. VEN Thresholds vs VIN
Figure 1. Quiescent Current vs Input Voltage
5
1.4
4.5
1.2
4
3.5
VOUT (V)
VOUT (V)
1
0.8
0.6
3
2.5
2
1.5
0.4
1
0.2
RLOAD = 1.2 k:
RLOAD = 4.8 :
RLOAD = 4.5 k:
RLOAD = 18 :
0.5
0
0
0
0.5
1
1.5
2
2.5
VIN (V)
0
1
2
D002
VOUT = 1.2 V, VEN = VIN
5
6
D003
Figure 4. VOUT vs VIN
350
2.900
300
2.875
250
2.850
VIN= 3.6V
2.825
VOUT(V)
GROUND CURRENT ( A)
4
VOUT = 4.5 V, VEN = VIN
Figure 3. VOUT vs VIN
200
2.800
150
2.775
100
2.750
VIN = 3.0V
VIN = 3.8V
VIN = 4.2V
VIN = 5.5V
50
0
0
50
100 150 200
IOUT(mA)
250
-40°C
90°C
25°C
2.725
2.700
300
0
SVA-30180571
Figure 5. Ground Current vs Output Current
8
3
VIN (V)
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50
100
150
LOAD (mA)
200
250
SVA-30180567
Figure 6. Load Regulation
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Typical Characteristics (continued)
VIN = 3.7 V, VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, TA = 25°C (unless otherwise noted)
2.900
2V/DIV
Load = 10 mA
2.875
VOUT
2.850
2V/DIV
VOUT(V)
2.825
2.800
VIN = VEN
2.775
2.750
-40°C
90°C
25°C
2.725
2.700
3.0
1A/DIV
IIN
2 ms/DIV
3.5
4.0
4.5
VIN(V)
5.0
5.5
SVA-30180568
SVA-30180509
Figure 7. Line Regulation
Figure 8. Inrush Current
VOUT
(AC Coupled)
10 mV/
DIV
VOUT
(AC Coupled)
10 mV/
DIV
VIN
1V/DIV
VIN
1V/DIV
10 s/DIV
10 s/DIV
SVA-30180511
SVA-30180510
VIN = 3.2 V ↔ 4.2 V, load = 250 mA
VIN = 3.2 V ↔ 4.2 V, load = 1 mA
Figure 10. Line Transient
Figure 9. Line Transient
VOUT
100 mV/DIV
VOUT
100 mV/DIV
LOAD
200 mA/DIV
LOAD
200 mA/DIV
100 s/DIV
100 s/DIV
SVA-30180513
SVA-30180512
Load = 0 mA ↔ 250 mA, 90°C
Load = 0 mA ↔ 250 mA, –40°C
Figure 12. Load Transient
Figure 11. Load Transient
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Typical Characteristics (continued)
VIN = 3.7 V, VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, TA = 25°C (unless otherwise noted)
1V/DIV
100 mV/DIV
VOUT
VOUT
LOAD
1V/DIV
200 mA/DIV
EN
100 s/DIV
20 s/DIV
SVA-30180515
SVA-30180514
0 mA
Load = 0 mA ↔ 250 mA, 25°C
Figure 14. Start-Up
Figure 13. Load Transient
1V/DIV
VOUT
1V/DIV
EN
20 s/DIV
SVA-30180516
250 mA
Figure 15. Start-Up
Figure 16. Noise Density Test
0
120
250 mA
200 mA
150 mA
100 mA
50 mA
20 mA
-20
100
-40
80
PSRR (dB)
DROPOUT VOLTAGE (mV)
140
60
40
-60
-80
Dropout Voltage
20
-100
0
0
50
100
150
200
LOAD CURRENT (mA)
250
-120
0.1
SVA-30180573
Figure 17. Dropout Voltage vs Load Current
10
1
10
FREQUENCY (kHz)
100
D004
Figure 18. PSRR Loads Averaged 100 Hz To 100 KHz
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Typical Characteristics (continued)
VIN = 3.7 V, VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, TA = 25°C (unless otherwise noted)
0
-20
PSRR (dB)
-40
-60
250 mA
200 mA
150 mA
100 mA
50 mA
20 mA
-80
-100
-120
0.01
0.1
1
10
100
FREQUENCY (kHz)
1000
10000
D005
Figure 19. PSRR Loads Averaged 10 Hz To 10 MHz
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7 Detailed Description
7.1 Overview
Designed to meet the needs of sensitive RF and analog circuits, the LP5907-Q1 provides low noise, high PSRR,
low quiescent current, as well as low line and load transient response figures. Using new innovative design
techniques, the LP5907-Q1 offers class leading noise performance without the need for a separate noise filter
capacitor.
The LP5907-Q1 is designed to perform with a single 1-µF input capacitor and a single 1-µF ceramic output
capacitor. With a reasonable PCB layout, the single 1-µF ceramic output capacitor can be placed up to 10 cm
away from the LP5907-Q1 package.
7.2 Functional Block Diagram
OUT
IN
POR
EN
EN
+
RF
CF
+
VBG
1.20V
RAD
EN
+
EN
EN
1M
VIH
12
GND
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7.3 Feature Description
7.3.1 LP5907-Q1 Voltage Options
Table 1 lists the available voltage options for the LP5907-Q1 SOT-23 package.
Table 1. Voltage Options
SOT-23 PACKAGE ORDER NUMBER
VOLTAGE OPTION (V)
LP5907QMFX-1.2Q1
1.2
—
1.3
—
1.5
LP5907QMFX-1.8Q1
1.8
LP5907QMFX-2.5Q1
2.5
LP5907QMFX-2.8Q1
2.8
2.85
2.9
LP5907QMFX-3.0Q1
3.0
LP5907QMFX-3.3Q1
3.3
LP5907QMFX-3.8Q1
3.8
LP5907QMFX-4.5Q1
4.5
7.3.2 Enable (EN)
The LP5907-Q1 EN pin is internally held low by a 1-MΩ resistor to GND. The EN pin voltage must be higher than
the VIH threshold to ensure that the device is fully enabled under all operating conditions. The EN pin voltage
must be lower than the VIL threshold to ensure that the device is fully disabled and the automatic output
discharge is activated.
7.3.3 Low Output Noise
Any internal noise at the LP5907-Q1 reference voltage is reduced by a first order low-pass RC filter before it is
passed to the output buffer stage. The low-pass RC filter has a –3 dB cut-off frequency of approximately 0.1 Hz.
7.3.4 Output Automatic Discharge
The LP5907-Q1 output employs an internal 230-Ω (typical) pulldown resistance to discharge the output when the
EN pin is low, and the device is disabled.
7.3.5 Remote Output Capacitor Placement
The LP5907-Q1 requires at least a 1-µF capacitor at the OUT pin, but there are no strict requirements about the
location of the capacitor in regards the OUT pin. In practical designs, the output capacitor may be located up to
10 cm away from the LDO.
7.3.6 Thermal Overload Protection (TSD)
Thermal shutdown disables the output when the junction temperature rises to approximately 160°C which allows
the device to cool. When the junction temperature cools to approximately 145°C, the output circuitry enables.
Based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may
cycle on and off. This thermal cycling limits the dissipation of the regulator and protects it from damage as a
result of overheating.
The thermal shutdown circuitry of the LP5907-Q1 has been designed to protect against temporary thermal
overload conditions. The thermal shutdown circuitry was not intended to replace proper heat-sinking.
Continuously running the LP5907-Q1 device into thermal shutdown may degrade device reliability.
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7.4 Device Functional Modes
7.4.1 Enable (EN)
The LP5907-Q1 Enable (EN) pin is internally held low by a 1-MΩ resistor to GND. The EN pin voltage must be
higher than the VIH threshold to ensure that the device is fully enabled under all operating conditions.
When the EN pin is pulled low, and the output is disabled, the output automatic discharge circuitry is activated.
Any charge on the OUT pin is discharged to GND through the internal 230-Ω (typical) pull-down resistance.
7.4.2 Minimum Operating Input Voltage (VIN)
The LP5907-Q1 does not include any dedicated undervoltage lockout circuitry. The LP5907-Q1 internal circuitry
is not fully functional until VIN is at least 2.2 V. The output voltage is not regulated until VIN has reached at least
the greater of 2.2 V or (VOUT + VDO).
14
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
Figure 20 shows the typical application circuit for the LP5907-Q1. Input and output capacitances may need to be
increased above the 1 µF minimum for some applications.
8.2 Typical Application
INPUT
IN
1 PF
ENABLE
OUT
LP5907-Q1
OUTPUT
1 PF
EN
GND
GND
Figure 20. LP5907-Q1 Typical Application
8.2.1 Design Requirements
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
2.2 to 5.5 V
Output voltage
1.8 V
Output current
200 mA
Output capacitor range
0.7 to 10 µF
Input/output capacitor ESR range
5 to 500 mΩ
8.2.2 Detailed Design Procedure
To
•
•
•
•
begin the design process, determine the following:
Available input voltage range
Output voltage needed
Output current needed
Input and Output capacitors
8.2.2.1 Power Dissipation and Device Operation
The permissible power dissipation for any package is a measure of the capability of the device to pass heat from
the power source, the junctions of the device, to the ultimate heat sink, the ambient environment. Thus, the
power dissipation is dependent on the ambient temperature and the thermal resistance across the various
interfaces between the die junction and ambient air.
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The maximum allowable power dissipation for the device in a given package can be calculated using Equation 1:
PD-MAX = ((TJ-MAX – TA) / RθJA)
(1)
The actual power being dissipated in the device can be represented by Equation 2:
PD = (VIN - VOUT) × IOUT
(2)
Equation 1 and Equation 2 establish the relationship between the maximum power dissipation allowed due to
thermal consideration, the voltage drop across the device, and the continuous current capability of the device.
These two equations should be used to determine the optimum operating conditions for the device in the
application.
In applications where lower power dissipation (PD) and/or excellent package thermal resistance (RθJA) is present,
the maximum ambient temperature (TA-MAX) may be increased.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum
ambient temperature (TA-MAX) may have to be derated. TA-MAX is dependent on the maximum operating junction
temperature (TJ-MAX-OP = 125°C), the maximum allowable power dissipation in the device package in the
application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (RθJA),
as given by Equation 3:
TA-MAX = (TJ-MAX-OP – (RθJA × PD-MAX))
(3)
Alternately, if TA-MAX can not be derated, the PD value must be reduced. This can be accomplished by reducing
VIN in the VIN – VOUT term as long as the minimum VIN is met, or by reducing the IOUT term, or by some
combination of the two.
8.2.2.2 External Capacitors
Like most LDOs, the LP5907-Q1 requires external capacitors for regulator stability. The device is specifically
designed for portable applications requiring minimum board space and smallest components. These capacitors
must be correctly selected for good performance.
8.2.2.3 Input Capacitor
An input capacitor is required for stability. The input capacitor should be at least equal to, or greater than, the
output capacitor for good load transient performance. At least a 1-µF capacitor has to be connected between the
LP5907-Q1 input pin and ground for stable operation over full load current range. Basically, it is acceptable to
have more output capacitance than input, as long as the input is at least 1 µF.
The input capacitor must be located a distance of not more than 1 cm from the IN pin and returned to a clean
analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.
Important: To ensure stable operation it is essential that good PCB practices are employed to minimize ground
impedance and keep input inductance low. If these conditions cannot be met, or if long leads are to be used to
connect the battery or other power source to the LP5907-Q1, TI recommends increasing the input capacitor to at
least 10 µF. Also, tantalum capacitors can suffer catastrophic failures due to surge current when connected to a
low-impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the
input, it must be verified by the manufacturer to have a surge current rating sufficient for the application. The
initial tolerance, applied voltage de-rating, and temperature coefficient must all be considered when selecting the
input capacitor to ensure the actual capacitance is never less than 0.7 µF over the entire operating range.
8.2.2.4 Output Capacitor
The LP5907-Q1 is designed specifically to work with a very small ceramic output capacitor, typically 1 µF. A
ceramic capacitor (dielectric types X5R or X7R) in the 1-µF to 10-µF range, and with equivalent series resistance
(ESR) between 5 mΩ to 500 mΩ, is suitable in the LP5907-Q1 application circuit. For this device connect the
output capacitor between the OUT pin and a good connection back to the GND pin.
It may also be possible to use tantalum or film capacitors at the device output, VOUT, but these are not as
attractive for reasons of size and cost (see Capacitor Characteristics).
The output capacitor must meet the requirement for the minimum value of capacitance and have an ESR value
that is within the range 5 mΩ to 500 mΩ for stability. Like the input capacitor, the initial tolerance, applied voltage
de-rating, and temperature coefficient must all be considered when selecting the input capacitor to ensure the
actual capacitance is never less than 0.7 µF over the entire operating range.
16
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8.2.2.5 Capacitor Characteristics
The LP5907-Q1 is designed to work with ceramic capacitors on the input and output to take advantage of the
benefits they offer. For capacitance values in the range of 1 µF to 10 µF, ceramic capacitors are the smallest,
least expensive, and have the lowest ESR values, thus making them best for eliminating high frequency noise.
The ESR of a typical 1-µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR
requirement for stability for the LP5907-Q1.
A better choice for temperature coefficient in a ceramic capacitor is X7R. This type of capacitor is the most stable
and holds the capacitance within ±15% over the temperature range. Tantalum capacitors are less desirable than
ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance
and voltage ratings in the 1 µF to 10 µF range.
Another important consideration is that tantalum capacitors have higher ESR values than equivalent size
ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the
stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic
capacitor with the same ESR value. The ESR of a typical tantalum increases about 2:1 as the temperature goes
from 25°C down to –40°C, so some guard band must be allowed.
8.2.2.6 Remote Capacitor Operation
The LP5907-Q1 requires at least a 1-µF capacitor at the OUT pin, but there are no strict requirements about the
location of the capacitor in regards to the pin. In practical designs the output capacitor may be located up to 10
cm away from the LDO. This means that there is no need to have a special capacitor close to the output pin if
there is already respective capacitors in the system (like a capacitor at the input of supplied part). The remote
capacitor feature helps user to minimize the number of capacitors in the system.
As a good design practice, keep the wiring parasitic inductance at a minimum, which means to use as wide as
possible traces from the LDO output to the capacitors, keeping the LDO output trace layer as close as possible
to ground layer and avoiding vias on the path. If there is a need to use vias, implement as many as possible vias
between the connection layers. The recommendation is to keep parasitic wiring inductance less than 35 nH. For
the applications with fast load transients, it is recommended to use an input capacitor equal to or larger to the
sum of the capacitance at the output node for the best load transient performance.
8.2.2.7 No-Load Stability
The LP5907-Q1 remains stable, and in regulation, with no external load.
8.2.2.8 Enable Control
The LP5907-Q1 may be switched ON or OFF by a logic input at the EN pin. A voltage on this pin greater than
VIH turns the device on, while a voltage less than VIL turns the device off.
When the EN pin is low, the regulator output is off and the device typically consumes less than 1 µA.
Additionally, an output pulldown circuit is activated which ensures that any charge stored on COUT is discharged
to ground.
If the application does not require the use of the shutdown feature, the EN pin can be tied directly to the IN pin to
keep the regulator output permanently on.
An internal 1-MΩ pulldown resistor ties the EN input to ground, ensuring that the device remains off if the EN pin
is left open circuit. To ensure proper operation, the signal source used to drive the EN pin must be able to swing
above and below the specified turnon or turnoff voltage thresholds listed in the Electrical Characteristics under
VIL and VIH.
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8.2.3 Application Curves
1V/DIV
VOUT
100 mV/DIV
LOAD
200 mA/DIV
VOUT
1V/DIV
EN
100 s/DIV
20 s/DIV
SVA-30180515
SVA-30180514
Figure 22. Load Transient Response
Figure 21. Start-Up
9 Power Supply Recommendations
This device is designed to operate from an input supply voltage range of 2.2 V to 5.5 V. The input supply must
be well regulated and free of spurious noise. To ensure that the LP5907-Q1 output voltage is well regulated and
dynamic performance is optimum, the input supply must be at least VOUT + 1 V. A minimum capacitor value of
1 µF is required to be within 1 cm of the IN pin.
18
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10 Layout
10.1 Layout Guidelines
The dynamic performance of the LP5907-Q1 is dependant on the layout of the PCB. PCB layout practices that
are adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP5907-Q1.
Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP5907-Q1, and as
close as is practical to the package. The ground connections for CIN and COUT must be back to the LP5907-Q1
ground pin using as wide and short copper traces as are practical.
Avoid connections using long trace lengths, narrow trace widths, and/or connections through vias. These add
parasitic inductances and resistance that results in inferior performance especially during transient conditions
10.2 Layout Examples
VIN
VOUT
CIN
1
IN
2
GND
3
EN
5
OUT
GND
COUT
GND
Enable
4
N/C
Figure 23. LP5907MF-x.x (SOT-23) Typical Layout
OUT
IN
1
4
COUT
CIN
EN
2
3
GND PLANE
Represents via used for application
specific connections
Figure 24. Layout Example for the DQN Package
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
20
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LP590712QDQNRQ1
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
D1
LP590713QDQNRQ1
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
D2
LP590715QDQNRQ1
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
D3
LP590718QDQNRQ1
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
D4
LP590722QDQNRQ1
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
FV
LP590725QDQNRQ1
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
D5
LP5907285QDQNRQ1
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
D7
LP590728QDQNRQ1
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
D6
LP590729QDQNRQ1
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
D8
LP590730QDQNRQ1
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
D9
LP590733QDQNRQ1
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
DA
LP590738QDQNRQ1
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
DB
LP590745QDQNRQ1
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
DC
LP5907QMFX-1.2Q1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
RAFQ
LP5907QMFX-1.8Q1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
RAGQ
LP5907QMFX-2.5Q1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
RAJQ
LP5907QMFX-2.8Q1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
RAKQ
LP5907QMFX-3.0Q1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
RALQ
LP5907QMFX-3.3Q1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
RAHQ
LP5907QMFX-3.8Q1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
RAMQ
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
7-Oct-2021
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
RoHS & Green
Call TI | SN
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LP5907QMFX-4.5Q1
ACTIVE
SOT-23
DBV
5
3000
Level-1-260C-UNLIM
-40 to 125
RAIQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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