LP5996SD-3030EV

User's Guide SNVA111B – November 2006 – Revised April 2013 AN-1377 LP3996 / LP5996 Evaluation Board 1 General Information This board is designed to allow the evaluation of either the LP3996 or the LP5996 Dual Voltage Regulator. Each board is pre-assembled and tested in the factory. The board contains the LP3996 / LP5996 in a 10 lead WSON package with all the associated passive components to enable all features of either device to be tested. The LP3996 / LP5996 are Dual, Low Drop-out Voltage Regulators with independent enable pins. LDO1 can deliver a maximum current of 150mA. while LDO2 can deliver up to 300mA. The LP3996 has an ERROR Flag associated with LDO2. The flag is set to Low if LDO2 is out of regulation and by adding a capacitor between the SET pin and GND, the flag may also be used as a delayed Power-On-reset (POR), see Figure 1. 1µF ceramic capacitors are fitted from VIN, VOUT1 and VOUT2 to GND. The POR feature is not included in the LP5996. Both devices also have a Bypass pin and by connecting a capacitor (10nF typ.) to GND, the output noise can be reduced substantially. 2 Operation The input voltage, applied between VIN and GND, should be at least 0.5V greater than the highest VOUT and no more than 6.0V. The minimum operating voltage is 2.0V. Loads can be connected to VO1 and VO2 pins with reference to GND. Internal short circuit protection is provided for each LDO. Additional sense pins, VINS, VO1S and VO2S are provided on the board to allow accurate measurements directly on the input and output pins of the device, eliminating any voltage drop on the PCB traces or connecting wires to the loads. Input leads should be kept reasonably short to minimize inductance. If longer input leads (>1m) are required it may be necessary to increase the value of the input capacitor to 2.2µF to ensure stability. ON/OFF control is provided by logic signals on EN1 and EN2. A minimum of 0.95V is required on these pins to enable the corresponding LDO. The LDOs will be shutdown with the enable pins set to 0.4V or less. If ON/OFF control is not required, then either or both enable pins may be connected to VIN. The device has 1MΩ internal resistors from EN1 and EN2 to GND. On the LP3996 only, the active low POR flag on LDO2 is asserted when the output of LDO2 drops below 90% (typical) of its regulated value indicating that LDO2 is out of regulation due to an overload or fault condition. During start-up, or following the removal of a fault condition, the flag will remain in the Low state until the output of LDO2 reaches 92% (typical) of its maximum value. By adding, a capacitor between the SET pin and GND, a delay can be programmed to the rising state of the POR output which may then be used as a Power-On-Reset for a micro controller within the user's application, for example. The Delay time is set by the following formula: tDELAY = VTH(SET) x CSET ISET (1) Typically, VTH(DELAY) is 1.25V and IDELAY is 1µA. So for the 0.1µF capacitor (C2) fitted, the delay time will be around 125ms. The POR output is an open drain NMOS transistor. It is pulled up to to VIN by a 470kΩ resistor (R1) fitted to the evaluation board. Note that when the POR is in the HIGH state, any significant loading, a 1MΩ Oscilloscope input, for example, will cause the voltage to drop due the 470kΩ pull-up. A 10X probe should be used. In the LOW state, with a sink current of 250µA, the POR pin will have a level of 20mV (typical). All trademarks are the property of their respective owners. SNVA111B – November 2006 – Revised April 2013 Submit Documentation Feedback AN-1377 LP3996 / LP5996 Evaluation Board Copyright © 2006–2013, Texas Instruments Incorporated 1 Schematic Diagram www.ti.com Output noise is minimized by the inclusion of a 10nF bypass capacitor (C5). Together with an internal resistor, this forms a low-pass filter for the internal reference voltage which reduces the noise on both VOUT1 and VOUT2. 3 Schematic Diagram R1 470 k: VINS VO1S LP3996 VIN VIN VOUT1 EN1 EN1 VOUT2 EN2 EN2 POR CBYP SET VO1 VO2S VO2 C1 1.0 PF C5 10 nF GND POR C2 0.1 PF C3 1.0 PF C4 1.0 PF Figure 1. Evaluation Board Schematic 2 AN-1377 LP3996 / LP5996 Evaluation Board SNVA111B – November 2006 – Revised April 2013 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated PCB Layout www.ti.com 4 PCB Layout Figure 2. Evaluation Board Component and Pin Layout Board Size: 1.200 inches x 1.000 inch 5 Bill of Materials for LP3996 / LP5996 WSON Evaluation Board Item Manufacturer Part # Description C1 (VIN to GND) Murata GRM188R61A105K 1.0µF, 10V, X5R, 0603, 10% C2 (VSET to GND) Murata GRM188R61C104K 0.1µF, 16V, X5R, 0603, 10% LP3996 only. C3 (VOUT1 to GND) Murata GRM188R61A105K 1.0µF, 10V, X5R, 0603, 10% C4 (VOUT2 to GND Murata GRM188R61A105K 1.0µF, 10V, X5R, 0603, 10% C5 (Bypass Capacitor) Murata GRM1887U1H103J 10 nF, 50V, U2J, 0603, 5% R1 (POR Pull-up) Vishay CRCW06034703F 470kΩ, 0603, 1% LP3996 only. Test Pins SNVA111B – November 2006 – Revised April 2013 Submit Documentation Feedback AN-1377 LP3996 / LP5996 Evaluation Board Copyright © 2006–2013, Texas Instruments Incorporated 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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