LP8340CLD-ADJ/NOPB

LP8340 www.ti.com SNVS221D – FEBRUARY 2003 – REVISED APRIL 2013 LP8340 Low Dropout, Low IQ, 1.0A CMOS Linear Regulator Check for Samples: LP8340 FEATURES DESCRIPTION • • • • • • • • • • The LP8340 low-dropout CMOS linear regulator is available in 5V, 3.3V, 2.5V, 1.8V and adjustable output versions. Packaged in the 6ld WSON package and 3ld PFM. The LP8340 can deliver up to 1.0A output current. 1 2 ±1.5% Typical VOUT Tolerance 420mV Typical Dropout @ 1.0A (VO = 5V) Wide Operating Range 2.7V to 10V Internal 1.0A PMOS Output Transistor 19µA Typical Quiescent Current Thermal Overload Limiting Foldback Current Limiting Zener Trimmed Bandgap Reference Space Saving WSON package Temperature Range – LP8340C 0°C to 125°C – LP8340I −40°C to 125°C Typical dropout voltage is 420mV at 1.0A for the 5.0V version, 540mV at 1.0A for the 3.3V version, 670mV at 1.0A for the 2.5V version and 680mV at 800mA for the 1.8V version. The LP8340 includes a zener trimmed bandgap voltage reference, foldback current limiting and thermal overload limiting. The LP8340 features a PMOS output transistor which unlike PNP type low dropout regulators requires no base drive current. This allows the device ground current to remain less than 50µA over operating temperature, supply voltage and irrespective of the load current. APPLICATIONS • • • • Hard Disk Drives Notebook Computers Battery Powered Electronics Portable Instrumentation Typical Applications VOUT VIN VIN 1.0µF Ceramic VOUT VOUT Sense (LLP only) 1.0µF Ceramic GND Figure 1. Fixed VOUT 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2013, Texas Instruments Incorporated LP8340 SNVS221D – FEBRUARY 2003 – REVISED APRIL 2013 www.ti.com 1.5V 3.3V VIN VOUT 1.0µF Ceramic 1.0µF Ceramic 25k ADJ 125k GND Figure 2. Adjustable VOUT Connection Diagrams Bottom View VIN 1 GND 2 Bottom View VIN 1 N/C 3 GND 2 N/C 3 PIN 1 ID PIN 1 ID HEATSINK is GND HEATSINK is GND 6 VIN 5 4 VOUT Sense VOUT 6 VIN Figure 3. 6-Pin WSON Package Fixed Output Voltage See Package Number NGD0006A 5 VOUT 4 ADJ Figure 4. 6-Pin WSON Package Adjustable Output Voltage See Package Number NGD0006A NOTE VIN Pins (Pin 1 & 6) must be connected together externally for full 1 amp operation (500mA max per pin). VOUT Sense (Pin 5) must be connected to VOUT (Pin 4). Top View Figure 5. PFM Package See Package Number NDP0003B These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP8340 LP8340 www.ti.com SNVS221D – FEBRUARY 2003 – REVISED APRIL 2013 Absolute Maximum Ratings (1) (2) (3) VIN, VOUT, VOUT Sense, ADJ −0.3V to 12V Storage Temperature Range −65°C to 160°C Junction Temperature (TJ) 150°C See (4) Power Dissipation ESD Rating Human Body Model (5) 2kV Machine Model (1) 200V Absolute Maximum ratings indicate limits beyond which damage may occur. Electrical specifications do not apply when operating the device outside of its rated operating conditions. All voltages are with respect to the potential at the ground pin. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. (2) (3) TJ(MAX) - TA PD = TJA Maximum Power dissipation for the device is calculated using the following equations: where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction-to-ambient thermal resistance. The value of the θJA for the WSON package is specifically dependant on the PCB trace area, trace material, and the number of layers and thermal vias. For improved thermal resistance and power dissipation for the WSON package, refer to Application Note AN-1187 (SNOA401). Human body model 1.5kΩ in series with 100pF. (4) (5) Operating Ratings (1) (2) Supply Voltage 2.7 to 10V Temperature Range LP8340C 0°C to 125°C −40°C to 125°C LP8340I (1) (2) Absolute Maximum ratings indicate limits beyond which damage may occur. Electrical specifications do not apply when operating the device outside of its rated operating conditions. All voltages are with respect to the potential at the ground pin. LP8340C Electrical Characteristics Unless otherwise specified all limits ensured for VIN = VO+ 1V, CIN = COUT = 10μF, TJ = 25°C. Boldface limits apply over the full operating temperature range of TJ = 0°C to 125°C Symbol Parameter Conditions Min (1) Typ (2) Units 10 10 V VIN Input Voltage LP8340-ADJ,1.8, 2.5 LP8340-3.3, 5.0 VOUT Output Voltage LP8340-ADJ, ADJ = OUT IOUT = 10mA, VIN = 2.7V, TJ = 25°C 100μA ≤IOUT≤ 800mA, 3.0V ≤VIN≤VOUT +4V 800mA