LP8501
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SNVS548D – SEPTEMBER 2008 – REVISED AUGUST 2013
LP8501 Multi-Purpose 9-Output LED Driver
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FEATURES
DESCRIPTION
•
The LP8501 is an LED driver with 9 outputs,
designed to produce versatile lighting effects for
mobile devices. The device is equipped with an
internal program memory, which allows operation
without processor control. Internal program memory
is used by three independent program execution
engines to produce user-defined lighting effects for
the outputs.
1
2
•
•
•
•
•
•
•
•
•
Three Independent Program Execution
Engines for User-defined Programs with Large
SRAM Memory for Storing Lighting Programs
9 Programmable Source (High Side) Driver
Outputs with 25.5 mA Full-Scale Current, 8-bit
Current Setting Resolution and 12-Bit PWM
Control Resolution
Flexible Grouping Possibility for All 9 Outputs
Including GPO into Three Groups with Group
PWM and Fade-In/ Fade-Out Controls
Built-in LED Test
Adaptive Charge Pump with 1x and 1.5x Gain
Provides up to 95% LED Drive Efficiency, with
Soft Start and Overcurrent/Short Circuit
Protection
Automatic Power Save Mode; IVDD = 10 µA
(typ.)
Two Wire, I2C-Compatible, Control Interface
Small Application Circuit
Pin-configured LED Powering for LEDs 1 to 6
and for LEDs 7 to 9
Solution Area
LOAD (01).
Program execution is clocked with 32 768Hz clock. This clock can be generated internally, or an external 32 kHz
clock can be connected to CLK pin. Using external clock enables synchronization of LED timing to this clock
rather than to the internal clock.
The engines have different priorities; thus when more than one engine is controlling the same LED output: the
LED engine 1 has the highest priority, LED engine 2 second highest and LED engine 3 third highest.
Supported instruction set is listed in the tables below:
Table 1. LP8501 LED Driver Instructions
Inst.
Bit [15]
Bit
[14]
Ramp
0
pres
cale
Set PWM
0
1
0
pres
cale
Wait
Bit
[13]
Bit
[12]
0
0
Bit
[11]
Bit
[10]
Bit [9] Bit [8] Bit [7] Bit [6]
Step time
0
0
0
Time
Bit
[5]
Bit [4] Bit [3]
Sign
# of increments
0
PWM value
0
0
0
0
0
0
Bit
[2]
Bit
[1]
Bit
[0]
0
0
0
Table 2. LP8501 LED Mapping Instructions
Inst.
Bit
[15
]
Bit
[14]
Bit
[13]
Bit
[12]
Bit
[11]
Bit
[10]
Bit [9] Bit [8] Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] Bit [0]
mux_ld
_start
1
0
0
1
1
1
0
0
0
SRAM address 0–95
mux_ld
_end
1
0
0
1
1
1
0
0
1
SRAM address 0–95
mux_se 1
l
0
0
1
1
1
0
1
0
LED select
mux_clr 1
0
0
1
1
1
0
1
0
0
0
0
0
0
0
0
mux_in
c
1
0
0
1
1
1
0
1
1
0
0
0
0
0
0
0
mux_de 1
c
0
0
1
1
1
0
1
1
1
0
0
0
0
0
0
mux_se 1
t
0
0
1
1
1
1
1
1
SRAM address 0–95
Table 3. LP8501 Branch Instructions
Inst.
Bit [15]
Bi t
[14]
Bit
[13]
Bit [12]
Bit
[11]
Bit
[10]
Bit [9] Bit [8] Bit [7] Bit [6]
Go to
Start
0
0
0
0
0
0
Branch
1
0
1
Int
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
End
1
1
0
Int
Reset
X
X
X
X
X
X
X
X
X
X
X
Trigger
1
1
1
0
0
0
0
Bit
[5]
Bit
[4]
Bit [3]
Bit
[2]
Bit
[1]
Bit
[0]
0
0
0
0
0
0
Loop count
Step number
Wait for a trigger
Ext. trig
X
X
ENGI
NE3
Send a trigger
ENGI
NE2
ENGI
NE1
Ext.
trig
X
X
ENGI
NE3
X
ENG ENG
INE2 INE1
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RAMP
This is the instruction useful for smoothly changing from one PWM value into another PWM value on the D1 to
D9 outputs; in other words, generating ramps (with a negative or positive slope). The LP8501 allows
programming of very fast and very slow ramps.
Ramp instruction generates a PWM ramp, using the effective PWM value as a starting value. At each ramp step
the output is incremented/decremented by one unit, unless the step time span is 0 or number of increments is 0.
Time span for one ramp step is defined with prescale (bit [14]) and step time (bits [13:9]). Prescale = 0 sets 0.49
ms cycle time and prescale = 1 sets 15.6 ms cycle time; so the minimum time span for one step is 0.49 ms
(prescale * step time span = 0.49ms x 1) and the maximum time span is 15.6 ms x 31 = 484ms/step. Note: if all
the step time bits [13:9] are set to zero, instruction is treated as Set PWM instruction.
The number of increment define how many steps will be taken during one ramp instruction; maximum increment
value is 255d, which corresponds to incrementing from zero to the maximum value. If PWM reaches
minimum/maximum value (0/255) during the ramp instruction, ramp instruction will be executed to the end
regardless of saturation. This enables ramp instruction to be used as a combined ramp & wait instruction. Note:
Ramp instruction is the wait instruction when the increment bits [7:0] are set to zero.
Setting bit LOG_EN high/low sets logarithmic (1) or linear ramp (0) (bit 5 in registers 06h — 0Eh and in register
15h for GPO). By using the logarithmic ramp setting the visual effect appears like a linear ramp, because the
human eye behaves in a logarithmic way.
Name
prescale
sign
Value (d)
Description
0
Divides master clock (32 768 Hz) by 16 = 2048 Hz → 0.488 ms cycle time
1
Divides master clock (32 768 Hz) by 512 = 64 Hz → 15.625 ms cycle time
0
Increase PWM output
1
Decrease PWM output
step time
1 - 31
One ramp increment done in (step time) x (prescale). Note: 0 means Set PWM instruction
# of increments
0 - 255
The number of increment/decrement cycles Note: Value 0 takes the same time as increment by 1, but
it is the wait instruction.
RAMP INSTRUCTION APPLICATION EXAMPLE
Let's say that the LED dimming is controlled according to the linear scale and effective PWM value at the
moment t=0 is 140d (~55%,), as shown in Figure 21 below, and we want to reach a PWM value of 148d (~58%)
at the moment t = 1.5s. The parameters for the RAMP instruction will be:
• Prescale = 1 → 15.625 ms cycle time
• Step time = 12 → step time span will be 12*15.625 ms = 187.5 ms
• Sign = 0 → increase PWM output
• # of increments = 8 → take 8 steps
DIMMING
CONTROL
148
147
146
145
STEP TIME
SPAN =
187.5 ms
144
143
142
141
140
RAMP INSTRUCTION
375
750
1125
0
0
1
2
3
4
5
6
1500 TIME ELAPSED (ms)
7
8
STEP COUNT
Figure 21. Example of Ramp Instruction
22
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SET_PWM
This instruction is used for setting the PWM value on the outputs D1 to D9 without any ramps. Set PWM output
value from 0 to 255 with PWM value bits [7:0]. Instruction execution takes sixteen 32 kHz clock cycles (=488 µs).
Name
Value (d)
Description
PWM value
0 to 255
PWM output duty cycle 0 to 100%
WAIT
When a wait instruction is executed, the engine is set in a wait status, and the PWM values on the outputs are
frozen.
Name
Value (d)
prescale
time
Description
0
Divide master clock (32 768 Hz) by 16 which
means 0.488 ms cycle time
1
Divide master clock (32 768 Hz) by 512
which means 15.625 ms cycle time
1 — 31
Total wait time will be = (time) x (prescale).
Maximum 484 ms, minimum 0.488 ms
LED MAPPING INSTRUCTIONS
These commands define the engine-to-LED mapping. The mapping information is stored in a table, which is
stored in the SRAM (program memory of the LP8501). Mapping information can be located anywhere in SRAM
memory. LP8501 has three lighting engines (Engines) which can be mapped to 9 LED drivers or to one GPO pin.
One engine can control one or multiple LED drivers. There are totally seven commands for the engine-to-LED
driver control: mux_ld_start, mux_ld_end, mux_sel, mux_clr, mux_inc, mux_dec, mux_set. Note: the LED
mapping instructions do not update PWM values to LED outputs. PWM values are updated after ramp or
set_pwm instructions.
MUX_LD_START; MUX_LD_END
Mux_ld_start and mux_ld_ end define the mapping table location in the memory. With mux_ld_start instruction
the mapped row can be activated at the same time by setting map = 1.
Name
map
SRAM address
Value (d)
Description
0
Mapped row inactive
1
Set the mapped row active. MUX_LD_START only
0 - 95
Mapping table start/end address
MUX_SEL
With mux_sel instruction one, and only one, LED driver (or the GPO pin) can be connected to a lighting engine.
Connecting multiple LEDs to one engine is done with the mapping table. After the mapping has been released
from an LED, the PWM register value will still control the LED brightness. If the mapping is released from the
GPO pin, serial bus control takes over the GPO state.
Name
LED select
Value (d)
0 - 16
Description
0 = no drivers selected
1 = LED1 selected
2 = LED2 selected
...
9 = LED9 selected
16 = GPO
MUX _CLR
Mux_clr clears engine-to-driver mapping. After the mapping has been released from an LED, the PWM register
value will still control the LED brightness. If the mapping is released from the GPO pin, serial bus control takes
over the GPO state.
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MUX_INC
A mux_inc instruction sets the next row active in the mapping table each time it is called. For example, if the 2nd
row is active after a mux_inc instruction is called, the 3rd row will be active. If the mapping table end is reached,
activation will roll to the mapping table start address next time when the mux_inc instruction is called. The engine
will not push a new PWM value to the LED driver output before a SET_PWM or RAMP instruction is executed. If
the mapping has been released from an LED, the value in the PWM register will still control the LED brightness.
If the mapping is released from the GPO pin, serial bus control takes over the GPO state.
MUX_DEC
A mux_dec instruction sets the previous row active in the mapping table each time it is called. For example, if the
3rd row is active, after mux_dec instruction is called, the 2nd row will be active. If the mapping table start address
is reached, activation will roll to the mapping table end address the next time the mux_dec instruction is called.
The engine will not push a new PWM value to the LED driver output before a SET_PWM or RAMP instruction is
executed. If the mapping has been released from an LED, the value in the PWM register will still control the LED
brightness. If the mapping is released from the GPO pin, serial bus control takes over the GPO state.
MUX_SET
Mux_set sets the index pointer to point the mapping table row defined by bits [6:0] and sets the row active. The
engine will not push a new PWM value to the LED driver output before a SET_PWM or RAMP instruction is
executed. If the mapping has been released from an LED, the value in the PWM register will still control the LED
brightness. If the mapping is released from the GPO pin, serial bus control takes over the GPO state.
Name
Value (d)
SRAM address
Description
0 to 95
Any SRAM address containing mapping data
GO-TO-START
A go-to-start command resets the Program Counter register (address 37h 38h or 39h) and continues executing
the program from the I2C register program start address defined in 4Ch-4Eh. Command takes sixteen 32 kHz
clock cycles. Note that default value for all program memory registers is 00h, which is “Go-to-Start” command.
BRANCH
Branch instruction is mainly indented for repeating a portion of the program code several times. Step number
parameter defines how many steps loop start point is relative to the engine Start Address. The loop count
parameter defines how many times the instructions inside the loop are repeated. The LP8501 supports nested
looping, i.e., loop inside loop. The number of nested loops is not limited. Instruction takes sixteen 32 kHz clock
cycles.
Name
Value (d)
Description
loop count
0 to 63
The number of loops to be done. 0 means an infinite loop.
step number
0- to 95
How many steps loop start point is from engine Start Address.
INT
Sends interrupt to processor by pulling the INT pin down and setting the corresponding status bit high. Interrupt
can be cleared by reading interrupt bits in STATUS/INTERRUPT register at address 3Ah. With this instruction
program execution continues.
24
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END
Ends program execution and resets the PC. Instruction takes sixteen 32 kHz clock cycles. An end instruction can
have two parameters, INT and RESET. These parameters are described in tables below. Execution engine bits
(Register 00h bits [5:0]) are set to zero, i.e., hold mode.
Name
int
Value
Description
0
No interrupt will be sent. PWM registers values will remain intact. Program
counter value is set to 0.
1
Reset program counter value to 0 and send interrupt to processor by pulling
the INT pin down and setting corresponding status bit high to notify that
program has ended. PWM register values will remain intact. Interrupt can
be cleared by reading interrupt bits in STATUS/INTERRUPT register at
address 3Ah
Name
Value
reset
0
Description
Reset program counter value to 0 and hold. PWM register values remain
intact.
1
Reset program counter value to 0 and hold. PWM register values of the
non-mapped drivers will remain. PWM register values of the mapped drivers
will be set to '0000 0000'.
TRIGGER
Wait or send triggers can be used to synchronize operation between the program execution engines. A send
trigger instruction takes sixteen 32 kHz clock cycles and a wait-for trigger takes at least sixteen 32 kHz clock
cycles. The receiving engine stores the triggers which have been sent. Received triggers are cleared by wait for
trigger instruction. Wait for trigger instruction is executed until all the defined triggers have been received (note:
several triggers can be defined in the same instruction).
An external trigger input signal must stay low for at least two 32 kHz clock cycles to be executed. A trigger output
signal is three 32 kHz clock cycles long. An external trigger signal is active low, i.e. when trigger is send/received
the pin is pulled to GND. Sent external trigger is masked, i.e,. the device which has sent the trigger will not
recognize it. If send and wait external triggers are used on the same instruction, the send external trigger is
executed first, then the wait external trigger.
Name
Value (d)
Description
wait for a trigger
0 to 31
Wait for a trigger from the engine(s). Several triggers can be defined in the
same instruction. Bit [7] engages engine 1, bit [8] engages engine 2, bit [9]
engages engine 3 and bit [6] is for external trigger I/O. Bits [4] and [5] are
not in use.
send a trigger
0 to 31
Send a trigger to the engine(s). Several triggers can be defined in the same
instruction. Bit [1] engages engine 1, bit [2] engages engine 2, bit [3]
engages engine 3 and bit [6] is for external trigger I/O. Bits [4] and [5] are
not in use.
Power Saving
Automatic Power Save Mode
Automatic power save mode is enabled when the POWERSAVE_EN bit in register address 36h is ‘1’. Almost all
analog blocks are powered down in power save if an external clock signal is used. Only the charge pump
protection circuits remain active. However, if the internal clock has been selected, only the charge pump and
LED drivers are disabled during the power save; the digital part of the LED controller needs to stay active. In
both cases the charge pump enters the weak 1x mode. In this mode the charge pump utilizes a passive current
limited keep-alive switch, which keeps the output voltage at the battery level. During the program execution
LP8501 can enter power save if there is no PWM activity in any of the LED driver outputs. To prevent short
power save sequences during program execution, LP8501 has an instruction look-ahead filter. During program
execution engine 1, engine 2 and engine 3 instructions are constantly analyzed, and if there are time slots with
no PWM activity on LED driver outputs for 50 ms, the device will enter power save. In power save mode program
execution continues uninterruptedly. When an instruction that requires PWM activity is executed, a fast internal
startup sequence will be started automatically.
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PWM Cycle Power Save Mode
PWM cycle power save mode is enabled when the PWM_POWERSAVE bit in register 36h is set to '1'. In PWM
power save mode analog blocks are powered down during the down time of the PWM cycle. Blocks are powered
down depending upon whether an external or an internal clock is used. While the Automatic Power-Save Mode
saves energy when there is no PWM activity, the PWM Power-Save mode saves energy during PWM cycles.
Like the Automatic Power-Save Mode, PWM Power-Save Mode works also during program execution.
Powersave mode if
brightness = 0
longer than 50 ms
LED brightness
(adjusted with PWM
duty cycle)
POWER
SAVE
POWERSAVE
Time
Chip current consumption
(LED current not included)
Time
Figure 22. The Effect of Power-Save mode during a Lighting Sequence
Powersave mode if
brightness = 0
longer than 50 ms
LED brightness
(adjusted with PWM
duty cycle)
POWER
SAVE
POWERSAVE
Time
Chip current consumption
(LED current not included)
Time
Additional power
savings from PWM
powersave mode
Figure 23. The effect of Powersave and PWM Powersave modes during a lighting sequence
Logic Interface Operational Description
The LP8501 features a flexible logic interface for connecting to processor and peripheral devices.
Communication is done with and I2C-compatible interface; different logic input/output pins makes it possible to,
for example, trigger program execution or enable power saving for the device.
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IO LEVELS
I2C interface, CLK and TRIG pin input levels are defined by the EN pin. Using the EN pin as voltage reference for
logic inputs simplifies PWR routing and eliminates the need for a dedicated VIO pin. In the following block
diagram EN pin connections are illustrated.
VDD
Input
Buffer
EN
SDA
SCL
Level
Shifter
Level
Shifter
Figure 24. Using EN Pin As Digital IO Voltage Reference
GPO/INT Pins
The LP8501 has one General Purpose Output pin (GPO); the INT pin also can be configured as a GPO pin. The
GPO pin level is defined by VDD voltage. It also has its own PWM control register. GPO can be configured into
fader groups, and it can be used in LED engine programming. When INT is configured as GPO, its level is
defined by the VDD. State of the pins can be controlled with GPO register (3Bh). GPO pins are digital CMOS
outputs, and no pull-up/down resistors are needed.
When the INT pin GPO function is disabled, it operates as an open drain pin. The INT signal is active low, i.e.,
when interrupt signal is sent, the pin is pulled to GND. External pull-up resistor is needed for proper functionality.
Table 4. GPO register (3Bh)
Name
Bit
Description
INT_CONF
2
Enable INT pin GPO function
0 = INT pin functions as a INT pin
1 = INT pin functions as a GPO pin
GPO
1
0 = GPO pin state is low
1 = GPO pin state is high
GPO_INT
0
0 = INT pin state is low (INT_CONF=1)
1 = INT pin state is high (INT_CONF=0)
TRIG Pin
The TRIG pin can function as an external trigger input or output. The external trigger signal is active low if, when
trigger is sent/received, the pin is pulled to GND. TRIG is an open drain pin, and an external pull-up resistor is
needed for trigger line. The external trigger input signal must be at least two 32 kHz clock cycles long to be
recognized. Trigger output signal is three 32 kHz clock cycles long. If TRIG pin is not used on application, it
should be connected to GND to prevent floating of this pin and extra current consumption.
CLK Pin
The CLK pin is used for connecting an external 32 kHz clock to the LP8501. Using an external clock can improve
automatic power-save mode efficiency because the internal clock can be switched off automatically when the
device has entered powersave mode with an external clock present. The device can be used without the external
clock. If an external clock is not used on the application, the CLK pin should be connected to GND to prevent
floating of this pin and extra current consumption.
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I2C-Compatible Control Interface
The I2C compatible synchronous serial interface provides access to the programmable functions and registers on
the device. This protocol uses a two-wire interface for bidirectional communications between the IC's connected
to the bus. The two interface lines are the Serial Data Line (SDA), and the Serial Clock Line (SCL). Every device
on the bus is assigned a unique address and acts as either a Master or a Slave depending on whether it
generates or receives the serial clock SCL. The SCL and SDA lines should each have a pull-up resistor placed
somewhere on the line and remain HIGH even when the bus is idle. Note: CLK pin is not used for serial bus data
transfer.
Data Validity
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of
the data line can only be changed when clock signal is LOW.
SCL
SDA
data
change
allowed
data
valid
data
change
allowed
data
valid
data
change
allowed
Figure 25. Data Validity Diagram
Start and Stop Conditions
START and STOP conditions classify the beginning and the end of the data transfer session. A START condition
is defined as the SDA signal transitions from HIGH to LOW while SCL line is HIGH. A STOP condition is defined
as the SDA transitions from LOW to HIGH while SCL is HIGH. The bus master always generates START and
STOP conditions. The bus is considered to be busy after a START condition and free after a STOP condition.
During data transmission, the bus master can generate repeated START conditions. First START and repeated
START conditions are equivalent, function-wise.
Transferring Data
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated
by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LP8501 pulls
down the SDA line during the 9th clock pulse, signifying an acknowledge. The LP8501 generates an
acknowledge after each byte has been received.
There is one exception to the “acknowledge after every byte” rule. When the master is the receiver, it must
indicate to the transmitter an end of data by not-acknowledging (“negative acknowledge”) the last byte clocked
out of the slave. This “negative acknowledge” still includes the acknowledge clock pulse (generated by the
master), but the SDA line is not pulled down.
After the START condition, the bus master sends a chip address. This address is seven bits long followed by an
eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a “0” indicates a WRITE and a “1”
indicates a READ. The second byte selects the register to which the data will be written. The third byte contains
data to write to the selected register.
I2C-Compatible Chip Address
LP8501 serial bus address is 32h.
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MSB
LSB
ADR6
bit7
ADR5
bit6
ADR4
bit5
ADR3
bit4
ADR2
bit3
ADR1
bit2
ADR0
bit1
0
1
1
0
0
1
0
R/W
bit0
2
I C Slave Address (chip address)
Figure 26. LP8501 Chip Address
ack from slave
ack from slave
ack from slave
start
MSB Chip Addr LSB
w
ack
MSB Register Addr LSB
ack
MSB
Data LSB
ack
stop
start
id = 32h
w
ack
addr = 40h
ack
address 40h data
ack
stop
SCL
SDA
Figure 27. Write cycle (w = write; SDA = “0”) id = chip address = 32h for LP8501
ack from slave
start
MSB Chip Addr LSB
w
ack from slave
MSB Register Addr LSB
repeated start
ack from slave data from slave nack from master
rs
MSB Chip Address LSB
rs
id = 32h
r
MSB
Data
LSB
stop
address 3Fh data
nack stop
SCL
SDA
start
id =32h
w ack
address = 3Fh
ack
r ack
When a READ function is to be accomplished, a WRITE function must precede the READ function, as show above.
Figure 28. Read cycle (r = read; SDA = "1"), id = chip address = 32h for LP8501
Control Register Write Cycle
• Master device generates start condition.
• Master device sends slave address (7 bits) and the data direction bit (r/w = 0).
• Slave device sends acknowledge signal if the slave address is correct
• Master sends control register address (8 bits).
• Slave sends acknowledge signal.
• Master sends data byte to be written to the addressed register.
• Slave sends acknowledge signal.
• If master will send further data bytes, the slave’s control register address will be incremented by one after
acknowledge signal. In order to reduce program load time LP8501 supports address auto increment. Register
address is incremented after each 8 data bits. For example, the whole program memory page can be written
in one serial bus write sequence. Note: serial bus address auto increment is not supported for register
addresses from 16H to 1EH.
• Write cycle ends when the master creates stop condition.
Control Register Read Cycle
• Master device generates a start condition.
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•
•
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•
•
•
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Master device sends slave address (7 bits) and the data direction bit (r/w = 0).
Slave device sends acknowledge signal if the slave address is correct
Master sends control register address (8 bits).
Slave sends acknowledge signal.
Master device generates repeated start condition.
Master sends the slave address (7 bits) and the data direction bit (r/w = 1).
Slave sends acknowledge signal if the slave address is correct.
Slave sends data byte from addressed register.
If the master device sends acknowledge signal, the control register address will be incremented by one. Slave
device sends data byte from addressed register.
Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop
condition
Auto Increment Feature
The auto increment feature allows writing several consecutive registers within one transmission. Every time an 8bit word is sent to the LP8501, the internal address index counter will be incremented by one and the next
register will be written. The table below shows writing sequence to two consecutive registers. The auto increment
feature is enabled by writing the EN_AUTO_INCR bit high in the MISC register (address 36h). Note that the
serial bus address auto increment is not supported for register addresses from 16h to 1Eh (PWM registers).
MASTER
START
CHIP
ADDR =
32H
WRITE
LP8501
30
REG
ADDR
ACK
DATA
ACK
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DATA
ACK
STOP
ACK
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LP8501 Registers
The LP8501 is controlled by a set of registers through the two-wire serial interface port. Some register bits are
reserved for future use. The table below lists device registers, their addresses, and their abbreviations. A more
detailed description is given in section.
Table 5. Control Register Map
Hex
Address
00
01
02
03
04
05
06
Register Name
ENABLE / ENGINE
CNTRL1
ENGINE CNTRL2
GROUP 1 FADING
GROUP 2 FADING
GROUP 3 FADING
POWER CONFIG
D1 CONTROL
Bit(s)
Read/Wr
ite
Default Value
After Reset
Bit Mnemonic and Description
[6]
R/W
x0xxxxxx
CHIP_EN
0 = LP8501 not enabled
1 = LP8501 enabled
[5:4]
R/W
xx00xxxx
ENGINE1_EXEC
Engine 1 program execution control
[3:2]
R/W
xxxx00xx
ENGINE2_EXEC
Engine 2 program execution control
[1:0]
R/W
xxxxxx00
ENGINE3_EXEC
Engine 3 program execution control
[5:4]
R/W
xx00xxxx
ENGINE1_MODE
ENGINE 1 mode control
[3:2]
R/W
xxxx00xx
ENGINE2_MODE
ENGINE 2 mode control
[1:0]
R/W
xxxxxx00
ENGINE3_MODE
ENGINE 3 mode control
[7:4]
R/W
0000xxxx
FADE_IN
Fade-in time for group 1 fader
[3:0]
R/W
xxxx0000
FADE_OUT
Fade-in time for group 1 fader
[7:4
R/W
0000xxxx
FADE_IN
Fade-in time for group 2 fader
[3:0]
R/W
xxxx0000
FADE_OUT
Fade-in time for group 2 fader
[7:4
R/W
0000xxxx
FADE_IN
Fade-in time for group 3 fader
[3:0]
R/W
xxxx0000
FADE_OUT
Fade-in time for group 3 fader
[1]
R/W
xxxxxx0x
CHP_CON_1_6
D1 to D6 power selection
[0]
R/W
xxxxxxx0
CHP_CON_7_9
D7 to D9 power selection
[7:6]
R/W
00xxxxxx
GROUP_SELECT
Fader group selection for D1 output
[5]
R/W
xx0xxxxx
LOG_EN
Logarithmic dimming control for D1
07
D2 CONTROL
[7:6]
R/W
00xxxxxx
GROUP_SELECT
Fader group selection for D2 output
[5]
R/W
xx0xxxxx
Logarithmic dimming control for D2 output
08
D3 CONTROL
[7:6]
R/W
00xxxxxx
GROUP_SELECT
Fader group selection for D3 output
[5]
R/W
xx0xxxxx
LOG_EN
Logarithmic dimming control for D3 output
[7:6]
R/W
00xxxxxx
GROUP_SELECT
Fader group selection for D4 output
[5]
R/W
xx0xxxxx
LOG_EN
Logarithmic dimming control for D4 output
[7:6]
R/W
00xxxxxx
GROUP_SELECT
Fader group selection for D5 output
[5]
R/W
xx0xxxxx
LOG_EN
Logarithmic dimming control for D5 output
09
0A
D4 CONTROL
D5 CONTROL
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Table 5. Control Register Map (continued)
Hex
Address
0B
0C
0D
0E
0F TO 14
15
Register Name
D6 CONTROL
D7 CONTROL
D8 CONTROL
D9 CONTROL
Bit(s)
Read/Wr
ite
Default Value
After Reset
Bit Mnemonic and Description
[7:6]
R/W
00xxxxxx
GROUP_SELECT
Fader group selection for D6 output
[5]
R/W
xx0xxxxx
LOG_EN
Logarithmic dimming control for D6 output
[7:6]
R/W
00xxxxxx
GROUP_SELECT
Fader group selection for D7 output
[5]
R/W
xx0xxxxx
LOG_EN
Logarithmic dimming control for D7 output
[7:6]
R/W
00xxxxxx
GROUP_SELECT
Fader group selection for D8 output
[5]
R/W
xx0xxxxx
LOG_EN
Logarithmic dimming control for D8 output
[7:6]
R/W
00xxxxxx
GROUP_SELECT
Fader group selection for D9 output
[5]
R/W
xx0xxxxx
LOG_EN
Logarithmic dimming control for D9 output
RESERVED
[7:0]
GPO CONTROL
[7:6]
R/W
00xxxxxx
RESERVED FOR FUTURE USE
GROUP_SELECT
Fader group selection for GPO
[5]
R/W
xx0xxxxx
LOG_EN
Logarithmic dimming control for GPO
16
D1 PWM
[7:0]
R/W
00000000
PWM
PWM duty cycle control for D1
17
D2 PWM
[7:0]
R/W
00000000
PWM
PWM duty cycle control for D2
18
D3 PWM
[7:0]
R/W
00000000
PWM
PWM duty cycle control for D3
19
D4 PWM
[7:0]
R/W
00000000
PWM
PWM duty cycle control for D4
1A
D5 PWM
[7:0]
R/W
00000000
PWM
PWM duty cycle control for D5
1B
D6 PWM
[7:0]
R/W
00000000
PWM
PWM duty cycle control for D6
1C
D7 PWM
[7:0]
R/W
00000000
PWM
PWM duty cycle control for D7
1D
D8 PWM
[7:0]
R/W
00000000
PWM
PWM duty cycle control for D8
1E
D9 PWM
[7:0]
R/W
00000000
PWM
PWM duty cycle control for D9
1F TO 24
RESERVED
[7:0]
25
GPO PWM
[7:0]
R/W
00000000
PWM
PWM duty cycle control for GPO
26
D1 CURRENT CONTROL
[7:0]
R/W
10101111
CURRENT
D1 output current control register. Default 17.5 mA
(typ.)
27
D2 CURRENT CONTROL
[7:0]
R/W
10101111
CURRENT
D2 output current control register. Default 17.5 mA
(typ.)
28
D3 CURRENT CONTROL
[7:0]
R/W
10101111
CURRENT
D3 output current control register. Default 17.5 mA
(typ.)
29
D4 CURRENT CONTROL
[7:0]
R/W
10101111
CURRENT
D4 output current control register. Default current is
17.5 mA (typ.)
32
RESERVED FOR FUTURE USE
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Table 5. Control Register Map (continued)
Hex
Address
Register Name
Bit(s)
Read/Wr
ite
Default Value
After Reset
Bit Mnemonic and Description
2A
D5 CURRENT CONTROL
[7:0]
R/W
10101111
CURRENT
D5 output current control register. Default current is
17.5 mA (typ.)
2B
D6 CURRENT CONTROL
[7:0]
R/W
10101111
CURRENT
D6 output current control register. Default current is
17.5 mA (typ.)
2C
D7 CURRENT CONTROL
[7:0]
R/W
10101111
CURRENT
D7 output current control register. Default current is
17.5 mA (typ.)
2D
D8 CURRENT CONTROL
[7:0]
R/W
10101111
CURRENT
D8 output current control register. Default current is
17.5 mA (typ.)
2E
D9 CURRENT CONTROL
[7:0]
R/W
10101111
CURRENT
D9 output current control register. Default current is
17.5 mA (typ.)
RESERVED FOR FUTURE
USE
[7:0]
2F TO 35
36
CONFIG
RESERVED FOR FUTURE USE
[7]
R/W
0xxxxx0x
PWM_POWERSAVE
Enables PWM powersave option
[6]
R/W
x1xxxx0x
EN_AUTO_INCR
Serial bus address auto increment enable
[5]
R/W
xx0xxx0x
POWERSAVE_EN
Powersave mode enable
[4:3]
R/W
xxx00x0x
CP_MODE
Charge pump gain selection
[2]
R/W
xxxxx00x
FADE_TO_OFF
Automatic fade out enable
[1]
R/W
xxxxxx0x
RESERVED Note that this bit should always be set
to zero when writing register.
[0]
R/W
xxxxxx00
INT_CLK_EN
LED Clock source selection
37
ENGINE1 PC
[6:0]
R/W
x0000000
PC
Program counter for engine 1
38
ENGINE2 PC
[6:0]
R/W
x0000000
PC
Program counter for engine 2
39
ENGINE3 PC
[6:0]
R/W
x0000000
PC
Program counter for engine 3
3A
STATUS/INTERRUPT
[7]
R
0xxxxxxx
LED_TEST_MEASUREMENT_DONE
Indicates when the LED test measurement is done.
[6]
R
x1xxxxxx
MASK_BUSY
Mask bit for interrupt generated by START_UP
BUSY or ENGINE_BUSY
[5]
R
xx0xxxxx
START_UP BUSY
This bit indicates that the start-up sequence is
running
[4]
R
xxx0xxxx
ENGINE_BUSY
This bit indicates that a program execution engine is
clearing internal registers
[3]
R
xxxx0xxx
EXT_CLK_USED
Indicates when external clock signal bit is set
[2]
R
xxxxx0xx
ENG1_INT
Interrupt bit for program execution engine 1
[1]
R
xxxxxx0x
ENG2_INT
Interrupt bit for program execution engine 2
[0]
R
xxxxxxx0
ENG3_INT
Interrupt bit for program execution engine 3
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Table 5. Control Register Map (continued)
Hex
Address
3B
34
Register Name
GPO
3D
RESET
41
LED TEST CONTROL
Bit(s)
Read/Wr
ite
Default Value
After Reset
Bit Mnemonic and Description
[2]
R/W
xxxxx0xx
INT_CONF
INT pin can be configured to function as a GPO with
this bit.
[1]
R/W
xxxxxx0x
GPO
GPO pin control
[0]
R/W
xxxxxxx0
INT_GPO
GPO pin control for INT pin (when INT_CONF is set
to '1')
[7:0]
R/W
00000000
RESET
Writing 11111111 into this register resets the LP8501
[7]
R/W
0xxxxxxx
EN_LED_TEST_ADC
[6]
R/W
x0xxxxxx
EN_LED_TEST_INT
[5]
R/W
xx0xxxxx
LED_TEST_CONTINUOUS_CONV
Continuous LED test measurement selection
[4:0]
R/W
xxx00000
LED_TEST_CTRL
Control bits for LED test
N/A
LED_TEST_ADC
LED test result
42
LED TEST ADC
[7:0]
R
48
GROUP FADER1
[7:0]
R/W
00000000
GROUP FADER
49
GROUP FADER2
[7:0]
R/W
00000000
GROUP FADER
4A
GROUP FADER3
[7:0]
R/W
00000000
GROUP FADER
4C
ENG1 PROG START
ADDR
[6:0]
R/W
x0000000
ADDR
4D
ENG2 PROG START
ADDR
[6:0]
R/W
x0001000
ADDR
4E
ENG3 PROG START
ADDR
[6:0]
R/W
x0010000
ADDR
4F
PROG MEM PAGE SEL
[2:0]
R/W
xxxxx000
PAGE_SEL
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Table 5. Control Register Map (continued)
Hex
Address
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
76
Register Name
Bit(s)
Read/Wr
ite
Default Value
After Reset
Bit Mnemonic and Description
PROGRAM MEMORY
00h/10h/20h/30h/40h/50h
[15:8]
R/W
00000000
[7:0]
R/W
00000000
PROGRAM MEMORY
01h/11h/21h/31h/41h/51h
[15:8]
R/W
00000000
[7:0]
R/W
00000000
PROGRAM MEMORY
02h/12h/22h/32h/42h/52h
[15:8]
R/W
00000000
[7:0]
R/W
00000000
PROGRAM MEMORY
03h/13h/23h/33h/43h/53h
[15:8]
R/W
00000000
[7:0]
R/W
00000000
PROGRAM MEMORY
04h/14h/24h/34h/44h/54h
[15:8]
R/W
00000000
[7:0]
R/W
00000000
PROGRAM MEMORY
05h/15h/25h/35h/45h/55h
[15:8]
R/W
00000000
[7:0]
R/W
00000000
PROGRAM MEMORY
06h/16h/26h/36h/46h/56h
[15:8]
R/W
00000000
[7:0]
R/W
00000000
PROGRAM MEMORY
07H/17H/27H/37H/47H/57H
[15:8]
R/W
00000000
[7:0]
R/W
00000000
PROGRAM MEMORY
08h/18h/28h/38h/48h/58h
[15:8]
R/W
00000000
[7:0]
R/W
00000000
PROGRAM MEMORY
09h/19h/29h/39h/49h/59h
[15:8]
R/W
00000000
[7:0]
R/W
00000000
PROGRAM MEMORY
0Ah/1Ah/2Ah/3Ah/4Ah/5Ah
[15:8]
R/W
00000000
[7:0]
R/W
00000000
PROGRAM MEMORY
0Bh/1Bh/2Bh/3Bh/4Bh/5Bh
[15:8]
R/W
00000000
[7:0]
R/W
00000000
PROGRAM MEMORY
0Ch/1Ch/2Ch/3Ch/4Ch/5Ch
[15:8]
R/W
00000000
[7:0]
R/W
00000000
PROGRAM MEMORY
0Dh/1Dh/2Dh/3Dh/4Dh/5Dh
[15:8]
R/W
00000000
[7:0]
R/W
00000000
PROGRAM MEMORY
0Eh/1Eh/2Eh/3Eh/4Eh/5Eh
[15:8]
R/W
00000000
[7:0]
R/W
00000000
PROGRAM MEMORY
0FH/1FH/2FH/3FH/4FH/5F
H
[15:8]
R/W
00000000
[7:0]
R/W
00000000
GAIN CHANGE CONTROL
[7:6]
R/W
000xxxxx
THRESHOLD
Threshold voltage (typ.)
00 — 400 mV
01 — 300 mV
10 — 200 mV
11 — 100 mV
[5]
R/W
xx0xxxxx
RESERVED BIT
When writing to register, write always '0'
[4:3]
R/W
xx000xxx
TIMER
00 — 5 ms
01 — 10 ms
10 — 50 ms
11 — infinite
[2]
R/W
xx0xx0xx
FORCE_1x
Activates 1.5x to 1x timer
CMD
Every Instruction is 16-bit wide.
The LP8501 can store 96 instructions. Each
instruction consists of 16 bits. Because one register
has only 8 bits, one instruction requires two register
addresses. In order to reduce program load time the
LP8501 supports address auto-incrementation.
Register address is incremented after each 8 data
bits. Thus the whole program memory page can be
written in one serial bus write sequence.
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LP8501 Control Register Details
00 ENABLE/ ENGINE CONTROL1
• 00 - Bit [6] CHIP_EN
– 1 = internal startup sequence powers up all the needed internal blocks and the device enters normal mode
– 0 = standby mode is entered. Control registers can be written or read (writing into PWM and Channel1–3
PC registers and to register 00h ENGINE1–3_EXEC bits is not possible).
• 00 — Bits [5:4] ENGINE1_EXEC
– Engine 1 program execution control. Execution register bits define how the program is executed. Program
start address can be programmed to Program Counter (PC) register 37h.
– 00 = Hold: Hold causes the execution engine to finish the current instruction and then stop. Program
counter (PC) can be read or written only in this mode.
– 01 = Step: Execute the instruction at the location pointed by the PC, increment the PC by one and then
reset ENG1_EXEC bits to 00 (i.e. enter hold).
– 10 = Free Run: Start program execution from the instruction pointed by the PC.
– 11 = Execute Once: Execute the instruction pointed by the current PC value and reset ENG1_EXEC to 00
(i.e. enter hold). The difference between step and executeonce is that executeonce does not increment
the PC.
• 00 — Bits [3:2] ENGINE2_EXEC
– Engine 2 program execution control. Equivalent to above definition of control bits. Program start address
can be programmed to Program Counter (PC) register 38h.
• 00 — Bits [1:0] ENGINE3_EXEC
– Engine 3 program execution control. Equivalent to engine 1 control bits. Program start address can be
programmed to Program Counter (PC) register 39h.
01 ENGINE CONTROL2
• Operation modes are defined in this register.
– Disabled: Engines can be configured to disabled mode separately.
– Load Program: Writing to program memory is allowed only when the engine is in load program operation
mode and engine busy bit (3Ah) is not set. Serial bus master should check the busy bit before writing to
program memory. All the three engines are in hold while one or more engines are in load program mode.
PWM values are frozen, also. Program execution continues when all the engines are out of load program
mode. Load program mode resets the program counter of the respective engine. Loadprogram mode can
be entered from the disabledmode only. Entering loadprogram mode from the runprogram mode is not
allowed.
– Run Program: Run program mode executes the instructions stored in the program memory. Execution
register (ENG1_EXEC etc.) bits define how the program is executed (hold, step, freerun or executeonce).
Program start address can be programmed to Program Counter (PC) register. The Program Counter is
reset to zero when the PC’s upper limit value is reached.
– Halt: Instruction execution aborts immediately and engine operation halts.
• 01 — Bit [5:4] ENGINE1_MODE
– 00 = disabled
– 01 = load program to SRAM, reset engine 1 PC
– 10 = run program as defined by ENGINE1_EXEC bits
– 11 = halt, halts program execution. Current command execution stopped
• 01 — Bits [3:2] ENGINE2_MODE
– 00 = disabled
– 01 = load program to SRAM, reset engine 2 PC
– 10 = run program as defined by ENGINE2_EXEC bits
– 11 = halt, halts program execution. Current command execution stopped
• 01 — Bits [1:0] ENGINE3_MODE
– 00 = disabled
– 01 = load program to SRAM, reset engine 3 PC
36
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•
– 10 = run program as defined by ENGINE3_EXEC bits
– 11 = halt, halts program execution. Current command execution stopped
Note that changing mode from Run to Load is not allowed. Preferred sequence is 10 –> 00 –> 01.
02
•
•
•
GROUP 1 FADING
This is the register used to assign fade-in and fade-out times for group 1. Time can be set with 4 bits.
02 — Bits [7:4] FADE_IN
02 — Bits [3:0] FADE_OUT
FADE_IN/FADE_OUT
Time, s
0000
0.0
0001
0.05
0010
0.1
0011
0.2
0100
0.3
0101
0.4
0110
0.5
0111
0.6
1000
0.7
1001
0.8
1010
0.9
1011
1.0
1100
1.5
1101
2.0
1110
3.0
1111
4.0
03 GROUP 2 FADING
• See GROUP 1 FADING
04 GROUP 3 FADING
• See GROUP 1 FADING
05 POWER CONFIG
• 05 — Bit [0] CHP_CON_7_9
– 1 = VDD7_9 should be connected to
– 0 = VDD7_9 should be connected to
• 05 — Bit [1] CHP_CON_1_6
– 1 = VDD1_6 should be connected to
– 0 = VDD1_6 should be connected to
VOUT
VDD
VOUT
VDD
06 D1 CONTROL
• This is the register used to assign the D1 output to the GROUP FADER group 1, 2, or 3, or none of them.
This register selects between linear and logarithmic PWM brightness adjustment. By using logarithmic PWM
scale the visual effect looks like linear. Logarithmic adjustment converts internally an 8-bit PWM value to a
logarithmic 12-bit value.
• 06 — Bit [7:6] GROUP_SELECT
– 00 = No group fader set, clears group fader set for D1. Default setting.
– 01 = Fader group 1 controls the D1 driver. The user can set the overall output of the group by the GROUP
1 FADER register at the address 48h and the fade-in/fade-out time by the GROUP 1 FADING register at
the address 02h.
– 10 = Fader group 2 controls the D1 driver. The user can set the overall output of the group by the GROUP
2 FADER register at the address 49h and the fade-in/fade-out time by the GROUP 2 FADING register at
the address 03h.
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•
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– 11 = Fader group 3 controls the D1 driver. The user can set the overall output of the group by the GROUP
3 FADER register at the address 4Ah and the fade-in/fade-out time by the GROUP 3 FADING register at
the address 04h.
06 — Bit [5] LOG_EN
– 0 = linear adjustment.
– 1 = logarithmic adjustment.
– This bit is effective for both the program execution engine control and direct PWM control.
07 D2 CONTROL to 0E D9 CONTROL
• The control registers and control bits for D2 output to D9 output are similar to that given to D1.
15 GPO CONTROL
• The control register and control bits for GPO output are similar to that given to D1.
16 D1 PWM
• This is the PWM duty cycle control for D1 output. D1 PWM register is effective during direct control operation
- direct PWM control is active after power up by default. Note: serial bus address auto increment is not
supported for register addresses from 16 to 1E.
• 16 — Bits [7:0] PWM
– 16 - Bits [7:0] PWM These bits set the D1 output PWM as shown in Figure 29 below.
100
PWM %
75
50
25
0
00000000
10000000
11111111
PWM Bits
Figure 29.
17 D2 PWM to 1E D9 PWM
• PWM duty cycle control for outputs D2 to D9. The control registers and control bits for D2 output to D9 output
are similar to that given to D1.
25 GPO PWM
• PWM duty cycle control for GPO. The control register and control bits for GPO are similar to that given to D1.
26 D1 OUTPUT CURRENT CONTROL
• D1 LED driver current control register. The resolution is 8-bits and step size is 100 μA. .
38
CURRENT bits
Output Current
00000000
0.0 mA
00000001
0.1 mA
00000010
0.2 mA
...
...
10101111
17.5 mA default setting
....
....
11111110
25.4 mA
11111111
25.5 mA
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27 D2 CURRENT CONTROL to 2E D9 CURRENT CONTROL
• The control registers and control bits for D2 output up to D9 output are similar to that given to D1 output.
36 CONFIG
• This register contains miscellaneous control bits.
• 36 — Bit [7] PWM_POWERSAVE
– 1 = PWM powersave ON
– 0 = PWM powersave OFF
– See the Power Saving section for further details.
• 36 — Bit [6] EN_AUTO_INCR
– The automatic increment feature of the serial bus address enables a quick memory write of successive
registers within one transmission.
– 1 = serial bus address automatic increment is enabled.
– 0 = serial bus address automatic increment is disabled.
• 36 — Bit [5] POWERSAVE_EN
– 1 = power save mode is enabled.
– 0 = power save mode is disabled. See the Power Saving section for further details.
• 36 — Bits [4:3] CP_MODE
– Charge pump operation mode
– 00 = OFF
– 01 = forced to bypass mode (1x)
– 10 = forced to 1.5x mode; output voltage is boosted to 4.5V.
– 11 = automatic mode selection
• 36 — Bit [2] FADE_TO_OFF
– Enables group fading when device is shut down through CHIP_EN.
– 1 = Group fading ON.
– 0 = Group fading OFF.
• 36 — Bit [1] RESERVED
– This bit is reserved and should be written to zero.
• 36 — Bits [0] Clock selection bit
– Program execution is clocked with internal 32 kHz clock or with external clock. Clocking is controlled with
bits [1:0] n the following way:
– 0 = external clock source (CLK pin)
– 1 = internal clock
– External clock can be used if a clock signal is present on CLK-pin. External clock frequency must be 32
kHz for correct operation. If a higher or a lower frequency is used, it will affect on the program engine
operation speed.
– If external clock is not used in the application, CLK pin should be connected to GND to avoid oscillation on
this pin and extra current consumption.
37 ENGINE1 PC
• 37 — Bits [6:0] PC
– Program counter starting value for program execution engine 1; A value from 0000000 to 1100000. The
maximum value depends on program memory allocation between the three program execution engines.
38 ENGINE2 PC
• 38 — Bits [6:0] PC
– Program counter starting value for program execution engine 2; A value from 0000000 to 1100000.
39 ENGINE3 PC
• 39 — Bits [6:0] PC
– Program counter starting value for program execution engine 3; A value from 0000000 to 1100000.
3A STATUS/INTERRUPT
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3A — Bit [7] LED_TEST_MEASUREMENT_DONE
– This bit indicates when the LED test is done, and the result is written to the LED TEST ADC register.
Typically the conversion takes 2.7 milliseconds to complete.
– 1 = LED test done
– 0 = LED test not done
– This bit is a read-only bit, and it is cleared (to “0”) automatically after a read operation.
3A — Bit [6] MASK_BUSY
– Mask bit for interrupts generated by STARTUP_BUSY or ENGINE_BUSY.
– 1 = Interrupt events will be masked i.e. no external interrupt will be generated from STARTUP_BUSY or
ENGINE_BUSY event (default).
– 0 = External interrupt will be generated when STARTUP_BUSY or ENGINE_BUSY condition is no longer
true. Reading the register 3Ah clears the status bits [5:4] and releases INT pin to high state.
3A — Bit [5] STARTUP_BUSY
– A status bit which indicates that the device is running the internal start-up sequence. See Modes of
Operation for details.
– 1 = internal start-up sequence running. Note: STARTUP_BUSY = 1 always when CHIP_EN bit is '0'
– 0 = internal start-up sequence completed
3A — Bit[4] ENGINE_BUSY
– A status bit which indicates that a program execution engine is clearing internal registers. Serial bus
master should not write or read program memory or registers 00h, 01h, 37h to 39h or 4Ch to 4Eh, when
this bit is set to '1'.
– 1 = at least one of the engines is clearing internal registers
– 0 = engine ready
3A — Bit [3] EXT_CLK_USED
– 1 = external clock bit is set
– 0 = external clock bit is not set
– This bit is high when external clock signal on CLK pin is set from register. Does not detect automatically
the external clock, only the bit selection from register 36h.
3A — Bits [2:0] ENG1_INT, ENG2_INT, ENG3_INT
– 1 = interrupt set
– 0 = interrupt not set/clear
– Interrupt bits for program execution engine 1, 2 and 3, respectively. These bits are set by END instruction.
Reading the interrupt bit clears the interrupt.
3B GPO
• LP8501 has one General Purpose Output pin (GPO). Status of the pin can be controlled with this register.
Also, INT pin can be configured to function as a GPO by setting the bit INT_CONF. When INT is configured
to function as a GPO, output level is defined by the VDD voltage.
• 3B — Bit [2] INT_CONF
– 1 = INT pin is set to function as an interrupt pin (default).
– 0 = INT pin is configured to function as a GPO.
• 3B — Bit [1] GPO
– 0 =GPO pin state is low.
– 1 = GPO pin state is high.
– GPO pins are digital CMOS outputs, and no pull-up/down resistors are needed.
• 3B — Bit [0] GPO_INT
– 0 = INT pin state is low (if INT_CONF = 1).
– 1 = INT pin state is high (if INT_CONF = 1).
– When INT pin’s GPO function is disabled, it operates as an open drain pin. INT signal is active low, i.e.
when interrupt signal is send, the pin is pulled to GND. External pull-up resistor is needed for proper
functionality.
3D RESET
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3D — Bits [7:0] RESET
– Writing 11111111 into this register resets the LP8501. Internal registers are reset to the default values.
Reading RESET register returns 00000000.
41 LED TEST CONTROL
• LED test control register
• 41 — Bit [7] EN_LEDTEST_ADC
– Writing this bit high (1) starts single LED test conversation. LED test measurement cycle is 2.7
milliseconds.
• 41 — Bit [6] EN_LEDTEST_INT
– 1 = interrupt signal will be send to the INT pin when the LED test is accomplished.
– 0 = no interrupt signal will be send to the INT pin when the LED test is accomplished.
– Interrupt can be cleared by reading STATUS/INTERRUPT register 3Ah.
• 41 — Bit [5] CONTINUOUS_CONV
– 1 = Continuous LED test measurement. Not active in powersave mode.
– 0 = Continuous conversion is disabled.
• 41 — Bits [4:0] LED__TEST_CTRL
– These bits are used for choosing the LED driver output to be measured. VDD, INT-pin and charge-pump
output voltage can also be measured.
LED_TEST_CTRL bits
Measurement
00000
D1
00001
D2
00010
D3
00011
D4
00100
D5
00101
D6
00110
D7
000111
D8
01000
D9
01001 to 01110
Reserved
01111
VOUT
10000
VDD
10001
INT-pin voltage
10010
VDD1_6
10011
VDD7_9
10010 to 11111
N/A
42 LED TEST ADC
• 42 — Bits [7:0} LED_TEST_ADC
– This is used to store the LED test result. Read-only register. LED test ADC least significant bit
corresponds to 30 mV. The measured voltage V (typ.) is calculated as follows: V = (RESULT(DEC) x 0.03
-1.478 V. For example, if the result is 10100110 = 166(DEC), the measured voltage is 3.50V (typ.). See
Figure 30 below.
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5
VOLTAGE (V)
4
3
2
1
0
40
90
140
190
RESULT (DEC)
Figure 30.
48 GROUP FADER1
• 48 — Bits [7:0] GROUP_FADER
– An 8-bit register to control all the LED-drivers mapped to GROUP FADER1. Group fader allows the user
to control dimming of multiple LEDs with a single serial bus write. This is a faster method to control the
dimming of multiple LEDs compared to the dimming done with the PWM registers (address 16h to 1Eh),
which would need multiple writes.
49 GROUP FADER2
• 49 — Bits [7:0] GROUP_FADER
– See GROUP FADER1 description.
4A GROUP FADER3
• 4A — Bits [7:0]GROUP_FADER
– See GROUP FADER1 description.
4C ENGINE1 PROG START ADDR
• Program memory allocation for program execution engines is defined with PROG START ADDR registers.
• 4C — Bits [6:0] — ADDR
– Engine 1 program start address.
4D ENG2 PROG START ADDR
• 4D — Bits [6:0] — ADDR
– Engine 2 program start address.
4E ENG3 PROG START ADDR
• 4E — Bits [6:0] — ADDR
– Engine 3 program start address.
4F PROG MEM PAGE SELECT
• 4F — Bits [2:0] — PAGE_SEL
– These bits select the program memory page. The program memory is divided into six pages of 16
instructions; thus the total amount of the program memory is 96 instructions.
76 — GAIN CHANGE CONTROL
Note that these controls have effect only in automatic mode.
• 76 — Bits [7:6] — THRESHOLD
– Threshold voltage (typ.) pre-setting. Bits set the threshold voltage at which the charge pump gain changes
from 1.5x to 1x. The threshold voltage is defined as the voltage difference between highest voltage output
(D1 to D6) and input voltage VDD : VTHRESHOLD = VDD — MAX (voltage on D1 to D6).
– If VTHRESHOLD is larger than the set value (100 mV to 400 mV), the charge pump is in 1x mode.
– 00 = 400 mV
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–
–
–
–
–
01 = 300 mV
10 = 200 mV
11 = 100 mV
Note: Values above are typical and should not be used as product specification.
Note: Writing to THRESHOLD [7:6] bits by the user overrides factory settings. Factory settings are not
user accessible.
– 76 — Bit [5] — RESERVED
– This bit is reserved for future use. When writing to register 76h, this bit should be written '0'.
– 76 — Bits [4:3] — TIMER
– Automatic mode change from 1.5x to 1x is attempted at the interval specified with these bits. After the
specified interval time mode change to 1x is allowed if there is enough voltage over the LED drivers to
ensure proper operation. If FORCE_1x is set to '1' after the specified interval time 1x mode is always
tested.
– 00 = 5 ms
– 01 = 10 ms
– 10 = 50 ms
– 11 = infinite. The charge pump switches gain from 1x mode to 1.5x mode only. The gain reset back to
1x is enabled under certain conditions, for example in the powersave mode.
– 76 — Bit [2] — FORCE_1x
– Activates forced mode change. In forced mode charge pump mode change from 1.5x to 1x is
attempted at the interval specified with the TIMER bits.
– 1 = forced mode changes enabled
– 0 = forced mode changes disabled
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APPLICATIONS INFORMATION
Recommended External Components
The LP8501 requires 4 external capacitors for proper operation. Surface-mount multi-layer ceramic capacitors
are recommended. Tantalum and aluminium capacitors are not recommended because of their high ESR. For
the flying capacitors (C1 and C2) multi-layer ceramic capacitors should always be used. These capacitors are
small, inexpensive and have very low equivalent series resistance (ESR
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