LP8557IAYFQT

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LP8557, LP85571 SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 LP8557 High-Efficiency LED Backlight Driver For Tablets 1 Features 3 Description • The LP8557 and LP8557I are high-efficiency LED drivers each featuring an integrated DC-DC inductive boost converter and six high-precision current sinks. LP8557 is intended for applications that exclusively use a pulse width modulated (PWM) signal for controlling the brightness while LP8557I is intended for applications that can utilize an I2C master as well. 1 • • • • • • • • • • • High-Efficiency DC-DC Boost Converter With 28-V Integrated Power MOSFET 2.7-V to 5.5-V VDD Range for Supporting SingleCell Li-Ion Battery Applications Six 25-mA High-Precision LED Current Sinks Adaptive Boost Voltage and LED Current Sink Headroom Controls for Maximum System Efficiency LED String Count Auto-Detect for Maximum Design Flexibility Smart Phase Shift PWM Mode for Reduced Audible Noise PWM Input Duty Cycle Brightness Control, PWM Output Frequency Selectable Independent of Input Frequency Hybrid PWM Plus Current Dimming for Higher LED Drive Optical Efficiency Switching Frequency, PWM Output Frequency, and LED Current can be set Through Resistors or I2C Interface Programmable Boost SW Slew Rate Control and Spread Spectrum Scheme for Reduced Switching Noise and Improved EMI Performance UVLO, TSD, BST_OVP, BST_OCP, BST_UV, LED OPEN* and LED Short Fault Coverage Minimum Number of External Components The boost converter has adaptive output voltage control. This feature minimizes the power consumption by adjusting the voltage to the lowest sufficient level under all conditions. The adaptive current sink headroom voltage control scales the headroom voltage with the LED current for optimal system efficiency. The LED string auto-detect function enables use of the same device in systems with 1 to 6 LED strings for the maximum design flexibility. Proprietary hybrid PWM plus current mode dimming enables additional system power savings. Phase-shift PWM allows reduced audible noise and smaller boost output capacitors. Flexible CABC support combines brightness level selections based on the PWM input and I2C commands. Device Information(1) PART NUMBER LP8557 Simplified Schematic With PWM-Only Option L1 D1 VIN 7 V ± 28 V 1.1 ” VOUT / VIN ” 11 LED Efficiency With 6 LED Strings 90 VOUT SW PWM FB LED1 LED2 LP8557 LED3 LED4 RFSET FSET LED Drive Efficiency [%] T VDD RISET 1.906 mm x 1.64 mm COU CIN PWM BODY SIZE (MAX) (1) For all available packages, see the orderable addendum at the end of the data sheet. Tablet LCD Display LED Backlight 2.7 V ± 5.5 V DSBGA (16) LP8557I 2 Applications PACKAGE 88 86 84 82 6p8s 6p6s 6p4s LED5 ISET LED6 GNDs 80 0 20 40 60 Brightness [%] 80 100 C001 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LP8557, LP85571 SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Function and Configurations ......................... Specifications......................................................... 1 1 1 2 3 3 4 7.1 7.2 7.3 7.4 7.5 7.6 7.7 Absolute Maximum Ratings ...................................... 4 ESD Ratings.............................................................. 4 Recommended Operating Conditions....................... 4 Thermal Information .................................................. 4 Electrical Characteristics........................................... 5 Boost Converter Electrical Characteristics................ 5 LED Driver Electrical Characteristics (LED1 To LED6 Pins) ........................................................................... 5 7.8 PWM Interface Characteristics (PWM Pin) ............... 6 7.9 Logic Interface Characteristics (PWM, FSET/SDA, ISET/SCL Pins) .......................... 6 7.10 I2C Serial Bus Timing Parameters (SDA, SCL) ..... 7 7.11 Typical Characteristics ............................................ 8 8 Detailed Description ............................................ 11 8.2 8.3 8.4 8.5 8.6 9 Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Programming........................................................... Register Maps ......................................................... 11 12 20 20 24 Application and Implementation ........................ 31 9.1 Application Information............................................ 31 9.2 Typical Applications ............................................... 34 10 Power Supply Recommendations ..................... 38 11 Layout................................................................... 38 11.1 Layout Guidelines ................................................. 38 11.2 Layout Example .................................................... 42 12 Device and Documentation Support ................. 43 12.1 12.2 12.3 12.4 12.5 12.6 Device Support .................................................... Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 43 43 43 43 43 43 13 Mechanical, Packaging, and Orderable Information ........................................................... 43 8.1 Overview ................................................................. 11 4 Revision History Changes from Revision A (June 2014) to Revision B Page • moved storage temperature range to Abs Max table ............................................................................................................ 4 • Changed Handling Ratings table to ESD Ratings table ........................................................................................................ 4 • Updated Thermal Information table ....................................................................................................................................... 4 • Changed word "safety" to "fault detection" ........................................................................................................................... 11 • Deleted "to 25% of the brightness range" ........................................................................................................................... 16 • Changed PGEN register table and descriptions .................................................................................................................. 28 • Changed fixed typo "2.4.4 kHz" to "24.4 kHz" ..................................................................................................................... 28 • Added note to beginning of Application and Implementation section .................................................................................. 31 • Added Community Resources section ................................................................................................................................ 43 Changes from Original (December 2013) to Revision A Page • Changed formatting to match new TI datasheet guidelines; added Device Information and Handling Ratings table, Layout, and Device and Documentation Support sections; reformatted Detailed Description and Application and Implementation sections, fix typographical errors. ................................................................................................................ 1 • Changed 6 LED strings to 5 LED Strings to correct typo....................................................................................................... 8 • Added PWM Input Duty Measurement subsection............................................................................................................... 13 • Changed description for "0" BFSET as well as description of register table for BFSET bit ................................................ 29 2 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 LP8557, LP85571 www.ti.com SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 5 Device Comparison Table ORDERABLE DEVICE PACKAGE TOP MARK DEVICE OPTION LP8557AYFQT LP8557AYFQR LP8557IAYFQT LP8557IAYFQR "PWM Only" - Recommended for systems without an I2C master PACKAGE TYPE (DRAWING) PINS 250 D40 DSBGA (YFQ) "PWM and I2C" - Recommended for systems with an I2C master PACKAGE QTY. 16 D41 3000 250 3000 6 Pin Function and Configurations YFQ Package 16-Pin DSBGA 1 2 3 4 4 3 2 1 A SW GND SW FSET SDA ISET SCL ISET SCL FSET SDA GND SW SW A B SW GND SW FB LED3 LED3 FB GND SW SW B C VDD GND PWM LED2 LED2 PWM GND VDD C D LED6 LED5 LED4 LED1 LED1 LED4 LED5 LED6 D BOTTOM VIEW TOP VIEW Pin Functions PIN NAME NO. FB B3 TYPE A (1) DESCRIPTION Boost feedback pin. The FB and OVP circuitry monitors the voltage on this pin. FSET/SDA A3 I/O Dual function pin. When I2C is not used (for example, BRTMODE = 00b), this pin can be used to set ƒSW and/or ƒPWM by connecting a resistor from this pin to a ground reference. When I2C is used (for example, BRTMODE = 01, 10 or 11), connect this pin to an SDA line of an I2C bus. The LP8557 "PWM Only" device option uses this pin as an FSET pin. LP8557I "PWM and I2C" device option uses this pin as an SDA pin. GND C2 G Ground pin. ISET/SCL A4 I Dual function pin. When I2C is not used (for example, BRTMODE = 00b), this pin can be used to set the full-scale LED current by connecting a resistor from the pin to a ground reference. When I2C is used (for example, BRTMODE =01, 10, or 11), connect this pin to an SCL line of an I2C bus. The LP8557 "PWM Only" device option uses this pin as an ISET pin. LP8557I "PWM and I2C" device option uses this pin as an SCL pin. LED1 D4 A LED driver – current sink terminal. If unused, this pin may be left floating. LED2 C4 A LED driver – current sink terminal. If unused, this pin may be left floating. LED3 B4 A LED driver – current sink terminal. If unused, this pin may be left floating. LED4 D3 A LED driver – current sink terminal. If unused, this pin may be left floating. LED5 D2 A LED driver – current sink terminal. If unused, this pin may be left floating. LED6 D1 A LED driver – current sink terminal. If unused, this pin may be left floating. PWM C3 I PWM input pin. SW A1, B1 A A connection to the drain terminal of the integrated power MOSFET. SW_GND A2, B2 G A connection to the source terminal of the integrated power MOSFET. C1 P Device power supply pin. VDD (1) A: Analog Pin, G: Ground Pin, P: Power Pin, I: Digital Input Pin, I/O: Digital Input/Output Pin Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 3 LP8557, LP85571 SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings Over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX UNIT VDD Voltage range on VDD pin –0.3 6 V VIO Voltage range on digital IO pins –0.3 6 V VO Voltage range on SW, FB, LED1 to LED6 pins –0.3 31 V TJ Junction temperature –30 125 °C Tsldr Maximum lead temperature (soldering) 260 °C Tstg Storage temperature range 150 °C (1) (2) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the potential at the GND pin. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions Over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX 2.7 5.5 0 28 V Ambient temperature, TA –30 85 °C Junction temperature, TJ –30 125 °C VDD V (SW, FB, LED1 to LED6) (1) (2) UNIT V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability All voltage values are with respect to the potential at the GND pin. 7.4 Thermal Information LP8557/LP8557I THERMAL METRIC (1) (2) YFQ (DSBGA) UNIT 16 PINS RθJA Junction-to-ambient thermal resistance 75.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 0.5 °C/W RθJB Junction-to-board thermal resistance 16.2 °C/W ψJT Junction-to-top characterization parameter 0.2 °C/W ψJB Junction-to-board characterization parameter 16.2 °C/W (1) (2) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 LP8557, LP85571 www.ti.com SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 7.5 Electrical Characteristics Unless otherwise specified: TA = 25°C, VDD = 3.8 V. PARAMETER TEST CONDITIONS MIN TYP VDD Input voltage range IDDQ Standby current IDD Operating current ƒOSC Internal oscillator frequency accuracy TTSD Thermal shutdown threshold (2) 150 TTSD_hyst Thermal shutdown hysteresis (2) 20 (1) (2) MAX 2.7 No current going through LEDs UNIT 5.5 V 1 µA 2.2 mA –4% –7% (1) 4% 7% (1) °C Limits apply over the full operating ambient temperature range –30°C ≤ TA ≤ 85°C. Verified by design and not tested in production. 7.6 Boost Converter Electrical Characteristics Unless otherwise specified: TA = 25°C, VDD = 3.8 V (1). PARAMETER TEST CONDITIONS MIN ISW = 0.5 A TYP MAX UNIT Ω RDS_ON Switch ON resistance VBOOST_MIN Minimum output voltage 6 (2) 7 8 (2) V VBOOST_MAX Maximum output voltage 27 (2) 28 29 (2) V ISW_CL SW pin current limit 2.1 2.4 2.5 A ILOAD_MAX Maximum continuous load current ƒSW Switching frequency VOVP_TH Overvoltage protection voltage threshold VUVLO_TH UVLO threshold VUVLO_hyst UVLO hysteresis tPULSE Switch pulse minimum width tSTARTUP Boost start-up time (1) (2) (3) (3) 0.2 ISW_LIM = 2.4 A VIN = 3 V, VOUT = 24 V 160 mA 500 1000 kHz VBOOST_MAX + 1.6 V 2.5 50 (3) No load mV 80 ns 1 ms (3) Minimum (Min) and Maximum (Max) limits are specified by design, test, or statistical analysis. Limits apply over the full operating ambient temperature range –30°C ≤ TA ≤ 85°C. Verified by design and not tested in production. 7.7 LED Driver Electrical Characteristics (LED1 To LED6 Pins) Unless otherwise specified: TA = 25°C, VDD = 3.8 V (1). PARAMETER TEST CONDITIONS ILEAKAGE Leakage current ILED_MAX Maximum sink current LED1...6 ILED_ACC LED current accuracy (2) IMATCH Channel to Channel Matching ƒLED VSAT (1) (2) (3) (4) (5) TYP (2) (5) MAX UNIT 1 25 Output current set to 20 mA LED switching frequency (4) Saturation voltage MIN Outputs LED1...LED6, VOUT = 28 V Output current set to 20 mA –3% –4% (3) µA mA 3% 4% (3) 0.5 PFREQ = 000b PFREQ = 111b 4.9 39.1 kHz Output current set to 20 mA 200 mV Minimum (Min) and Maximum (Max) limits are specified by design, test, or statistical analysis. The LED current accuracy is defined as 100 × (ILED_AVE – ILED_Target) / ILED_AVE. The channel-to-channel LED current matching is defined as (ILED_MAX – ILED_MIN) / ILED_AVE. Limits apply over the full operating ambient temperature range –30°C ≤ TA ≤ 85°C. Verified by design and not tested in production. Saturation voltage is defined as the voltage when the LED current has dropped 10% from the value measured at 1 V. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 5 LP8557, LP85571 SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 www.ti.com 7.8 PWM Interface Characteristics (PWM Pin) See (1) PARAMETER TEST CONDITIONS MIN (2) TYP UNIT 25000 Hz ƒPWM PWM frequency tMIN_ON Minimum pulse ON time (2) 1 µs tMIN_OFF Minimum pulse OFF time (2) 1 µs tON Turnon delay from standby to backlight on (2) PWM pin goes from low to switching. tSTBY Turnoff delay from backlight off to standby (2) PWM pin goes from switching to low. 52 ƒIN < 2.4 kHz 12 ƒIN < 4.8 kHz 11 ƒIN < 9.6 kHz 10 ƒIN < 19.5 kHz 9 ƒIN < 25 kHz 8 PWMRES (1) (2) 75 MAX PWM input resolution (2) 9 ms ms bits Minimum (Min) and Maximum (Max) limits are specified by design, test, or statistical analysis. Verified by design and not tested in production. 7.9 Logic Interface Characteristics (PWM, FSET/SDA, ISET/SCL Pins) Limits apply over the full operating ambient temperature range –30°C ≤ TA ≤ 85°C (1). PARAMETER TEST CONDITIONS VIL Input low level VIH Input high level II Input current VOL Output low level ISDA = 3 mA IO Output leakage VSDA = 2.8 V (1) 6 MIN TYP MAX V 1 µA 1.44 –1 UNIT 0.4 V 0.5 V 1 µA Minimum (Min) and Maximum (Max) limits are specified by design, test, or statistical analysis. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 LP8557, LP85571 www.ti.com 7.10 SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 I2C Serial Bus Timing Parameters (SDA, SCL) See (1) and Figure 1. PARAMETER MIN MAX UNIT 400 kHz ƒSCL Clock Frequency 1 Hold Time (repeated) START Condition 0.6 μs 2 Clock Low Time 1.3 μs 3 Clock High Time 600 ns 4 Setup Time for a Repeated START Condition 600 ns 5 Data Hold Time 50 ns 6 Data Setup Time 100 ns 7 Rise Time of SDA and SCL 20 + 0.1Cb 300 ns 8 Fall Time of SDA and SCL 15 + 0.1Cb 300 ns 9 Set-up Time for STOP condition 600 ns 10 Bus Free Time between a STOP and a START Condition 1.3 μs Cb Capacitive Load Parameter for Each Bus Line Load of 1 pF corresponds to 1 ns. 10 tWAIT Wait time from VDD = 2.7 V to 1st I2C command (1) 150 200 ns μs Verified by design and not tested in production. Figure 1. I2C-Compatible Timing Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 7 LP8557, LP85571 SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 www.ti.com 7.11 Typical Characteristics 90 90 88 88 LED Drive Efficiency [%] LED Drive Efficiency [%] Unless otherwise specified: VIN = VDD = 3.8 V, L = 10 µH Cyntec PIME051E, D = Diodes PD3S130L-7, COUT = 2 × 4.7 µF, LED Vƒ = 2.85 V (typical), ILED_MAX = 25 mA per string. 86 84 82 6p8s 6p6s 6p4s 80 0 20 40 60 80 86 84 82 80 0 100 Brightness [%] 6p9s 6p7s 6p5s 88 88 LED Drive Efficiency [%] LED Drive Efficiency [%] 90 86 84 5p9s 5p7s 5p5s 80 20 40 60 80 5p8s 5p6s 5p4s 80 0 88 LED Drive Efficiency [%] LED Drive Efficiency [%] 88 86 84 4p8s 4p6s 4p4s 40 60 80 Brightness [%] 8 60 80 100 C001 86 84 82 4p9s 4p7s 4p5s 80 100 0 20 40 60 80 Brightness [%] C001 Figure 6. LED Efficiency With 4 LED Strings 40 Figure 5. LED Efficiency With 5 LED Strings 90 20 20 Brightness [%] 90 0 C001 82 Figure 4. LED Efficiency With 5 LED Strings 80 100 84 C001 82 80 86 100 Brightness [%] 60 Figure 3. LED Efficiency With 6 LED Strings Figure 2. LED Efficiency With 6 LED Strings 82 40 Brightness [%] 90 0 20 C001 100 C001 Figure 7. LED Efficiency With 4 LED Strings Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 LP8557, LP85571 www.ti.com SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 Typical Characteristics (continued) 90 90 88 88 LED Drive Efficiency [%] LED Drive Efficiency [%] Unless otherwise specified: VIN = VDD = 3.8 V, L = 10 µH Cyntec PIME051E, D = Diodes PD3S130L-7, COUT = 2 × 4.7 µF, LED Vƒ = 2.85 V (typical), ILED_MAX = 25 mA per string. 86 84 82 3p9s 3p7s 3p5s 80 0 20 40 60 80 86 84 82 80 100 Brightness [%] 3p8s 3p6s 3p4s 0 88 88 86 84 2p8s 2p6s 2p4s 80 20 40 60 80 0 LED Drive Efficiency [%] LED Drive Efficiency [%] 88 86 84 1p9s 1p7s 1p5s 60 80 Brightness [%] 60 80 100 C001 86 84 82 1p8s 1p6s 1p4s 80 100 0 20 40 60 80 Brightness [%] C001 Figure 12. LED Efficiency With 1 LED String 40 Figure 11. LED Efficiency With 2 LED Strings 88 40 20 Brightness [%] 90 20 2p9s 2p7s 2p5s 80 Figure 10. LED Efficiency With 2 LED Strings 0 C001 82 90 80 100 84 C001 82 80 86 100 Brightness [%] 60 Figure 9. LED Efficiency With 3 LED Strings 90 LED Drive Efficiency [%] LED Drive Efficiency [%] Figure 8. LED Efficiency With 3 LED Strings 82 40 Brightness [%] 90 0 20 C001 100 C001 Figure 13. LED Efficiency With 1 LED String Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 9 LP8557, LP85571 SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 www.ti.com Typical Characteristics (continued) 90 92 88 90 Boost Efficiency [%] LED Drive Efficiency [%] Unless otherwise specified: VIN = VDD = 3.8 V, L = 10 µH Cyntec PIME051E, D = Diodes PD3S130L-7, COUT = 2 × 4.7 µF, LED Vƒ = 2.85 V (typical), ILED_MAX = 25 mA per string. 86 84 82 0 20 40 60 80 86 84 2.7V 3.8V 5.5V 80 88 82 100 Brightness [%] 0 Figure 14. LED Efficiency as a Function of VIN/VDD 60 80 100 C001 Figure 15. Boost Efficiency as a Function of VIN/VDD 5 2.7V 3.8V 5.5V 2.7V 3.8V 5.5V 4 Matching [%] 8 Accuracy [%] 40 Brightness [%] 6p6s Load 10 6 4 2 3 2 1 0 0 0 20 40 60 80 100 Brightness [%] 0 0.4 Headroom Voltage [V] 5 3 2 20 40 60 80 Brightness [%] C001 0.2 2.7V 3.8V 5.5V 0 100 100 0.3 0 20 40 60 80 Brightness [%] C001 Figure 18. Device Operating Current as a Function of VDD 80 0.1 2.7V 3.8V 5.5V 1 60 Figure 17. LED Current Channel-Channel Matching as a Function of VDD 0.5 4 40 Brightness [%] 6 0 20 C001 Figure 16. LED Current Accuracy as a Function of VDD IDD [mA] 20 C001 6p6s Load 10 2.7V 3.8V 5.5V 100 C001 Figure 19. Current Sink Headroom Voltage as a Function of VDD Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 LP8557, LP85571 www.ti.com SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 8 Detailed Description 8.1 Overview The LP8557 and LP8557I are high-efficiency LED drivers each featuring an integrated DC-DC inductive boost converter and six high-precision current sinks. LP8557 is intended for applications that exclusively use a pulse width modulated (PWM) signal for controlling the brightness while LP8557I is intended for applications that can utilize an I2C master as well. The boost converter has adaptive output voltage control. This feature minimizes the power consumption by adjusting the voltage to the lowest sufficient level under all conditions. The adaptive current sink headroom voltage control scales the headroom voltage with the LED current for optimal system efficiency. The LED string auto-detect function enables use of the same device in systems with 1 to 6 LED strings for the maximum design flexibility. Proprietary hybrid PWM plus current mode dimming enables additional system power savings. Phase shift PWM allows reduced audible noise and smaller boost output capacitors. Flexible CABC support combines brightness level selections based on the PWM input and I2C commands. The LP8557 and LP8557I feature a full set of features that ensure robust operation of the device and external components. The set consists of input undervoltage lockout, thermal shutdown, overcurrent protection, overvoltage protection, and LED open and short detection. 8.2 Functional Block Diagram VIN VOUT VDD SW FB Boost Converter UVLO Reference Voltage Thermal shutdown Switching Frequency 500, 1000 kHz PWM Control BOOST_FREQ Oscillator Headroom Control POR Fault Detection (Open*/Short LED, OCP, OVP) LED Current Sinks LED1 PWM LED2 LED3 BRIGHTNESS FSET / SDA Digital Logic LED4 CONTROL LED5 ISET /SCL LED6 EPROM Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 11 LP8557, LP85571 SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 www.ti.com 8.3 Feature Description 8.3.1 Boost Converter Overview 8.3.1.1 Operation The boost DC-DC converter generates a 7-V to 28-V boost output voltage from a 2.7-V to 5.5-V boost input voltage. The converter is a magnetic switching PWM mode DC-DC inductive boost converter with a current limit. It uses current programmed mode control, where the inductor current is measured and controlled with the feedback. During start-up, the soft-start function reduces the peak inductor current. Figure 20 shows the boost block diagram. FB SW Startup VREF OVP Light Load R R + gm + - R S VFB R Osc/ ramp OCP + - 6 Figure 20. Boost Circuit Block Diagram 8.3.1.2 Adaptive Boost Output Voltage Control The boost converter operates in adaptive boost control mode. In this mode, the voltage at the LED pins is monitored by the control loop. It raises the boost voltage when the measured voltage of ANY of the LED strings falls below the voltage threshold of its corresponding LOW comparator. If the headrooms of ALL of the LED strings are above the voltage threshold of their corresponding MID comparator, then the boost voltage is lowered. VBOOST Driver headroom OUT1 string VF OUT6 string VF OUT5 string VF OUT4 string VF OUT3 string VF OUT2 string VF OUT1 string VF VBOOST Time Figure 21. Adaptive Headroom Detail 8.3.2 Brightness Control The brightness can be controlled using an external PWM signal or the Brightness registers accessible via an I2C interface or both. Which of these two input sources is selected is set by the BRTMODE bits. The LP8557 operates exclusively in BRTMODE = 00. While the LP8557I, by default, operates in BRTMODE = 11, it can operate in all BRTMODE settings by configuring the bits via the I2C interface. How the brightness is controlled in each of the four possible modes is described in the following sections. 12 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 LP8557, LP85571 www.ti.com SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 Feature Description (continued) 8.3.2.1 PWM Input Duty Measurement When using PWM input for brightness control the input PWM duty cycle is measured as described in following diagram and the brightness is controlled based on the result. When changing the brightness it must be noted that the measurement cycle is from rising edge to next rising edge and brightness change must be done accordingly (time from rising to rising edge is constant (=cycle time) and falling edge defines the brightness). Cycle Time tPWM 20% On-time tON1 20% 40% 40% PWM/INT Cycle Time tPWM On-time tON2 Duty = tON t PWM Change in Duty on this Edge Figure 22. PWM Input Duty Cycle Measurement 8.3.2.2 BRTMODE = 00b With BRTMODE = 00b, the LED output current is controlled by the PWM input duty cycle. The PWM detector block measures the duty cycle at the PWM pin and uses it to generate a PWM-based brightness code. Before the output is generated, the code goes through the curve shaper block. Then the code goes into the hybrid PWM & I Dimming block which determines the range of the PWM and Current control. The outcome of the hybrid PWM & I dimming block is current and/or up to 6 PWM output signals. MAXCURR CURRENT PWM Input PWM Detector Curve Shaper Hybrid PWM&I Dimming PWM Gen PWM THRESHOLD Figure 23. Brightness Data Path for BRTMODE = 00b Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 13 LP8557, LP85571 SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 www.ti.com Feature Description (continued) L1 2.7 V ± 5.5 V D1 VIN 7 V ± 28 V 1.1 ” VOUT / VIN ” 11 T VDD SW PWM PWM VOUT COU CIN FB LED1 LED2 LP8557 LED3 LED4 RFSET FSET RISET LED5 ISET LED6 GNDs Figure 24. Typical Application Circuit for Devices Configured With BRTMODE = 00 8.3.2.3 BRTMODE = 01b With BRTMODE = 01b, the LED output current is controlled by the BRTHI/BRTLO registers. Before the output is generated the BRTHI/BRTLO registers-based brightness code goes through the Curve Shaper block. Then the code goes into the hybrid PWM & I dimming block which determines the range of the PWM and current control. The outcome of the Hybrid PWM&I Dimming block is Current and/or up to 6 PWM output signals. MAXCURR CURRENT I2C Input Brightness Curve Shaper Hybrid PWM&I Dimming PWM Gen PWM THRESHOLD Figure 25. Brightness Data Path for BRTMODE = 01b 8.3.2.4 BRTMODE = 10b With BRTMODE = 10b, the LED output current is controlled by the PWM input duty cycle and the BRTHI/BRTLO registers. The PWM detector block measures the duty cycle at the PWM pin and uses it to generate PWM-based brightness code. Before the code is multiplied with the BRTHI/BRTLO registers-based brightness code, it goes through the curve shaper block. After the multiplication, the resulting code goes into the hybrid PWM & I dimming block which determines the range of the PWM and Current control. The outcome of the hybrid PWM & I dimming block is current or up to 6 PWM output signals. 14 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 LP8557, LP85571 www.ti.com SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 Feature Description (continued) I2C Input Brightness PWM Input PWM Detector MAXCURR CURRENT Curve Shaper Hybrid PWM&I Dimming PWM Gen PWM THRESHOLD Figure 26. Brightness Data Path for BRTMODE = 10b 8.3.2.5 BRTMODE = 11b With BRTMODE = 11b, the LED output current is controlled by the PWM input duty cycle and the BRTHI/BRTLO registers. The PWM detector block measures the duty cycle at the PWM pin and uses it to generate PWM-based brightness code. In this mode, the BRTHI/BRTLO registers-based brightness code goes through the curve shaper block before it is multiplied with the PWM input duty cycle-based brightness code. After the multiplication, the resulting code goes into the hybrid PWM & I dimming block which determines the range of the PWM and Current control. The outcome of the hybrid PWM & I dimming block is current and/or up to 6 PWM output signals. I2C Input Brightness PWM Input PWM Detector Curve Shaper MAXCURR CURRENT Hybrid PWM&I Dimming PWM Gen PWM THRESHOLD Figure 27. Brightness Data Path for BRTMODE = 11b Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 15 LP8557, LP85571 SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 www.ti.com Feature Description (continued) 7 V ± 28 V 2.7 V ± 5.5 V L1 D1 1.1 ” 9OUT / VIN ” 11 VOUT VIN COUT CIN VDD PWM SW PWM FB LED1 LED2 LP8557I LED3 LED4 SDA SDA LED5 LED6 SCL SCL GNDs Figure 28. Typical Application Circuit for Devices Configured With BRTMODE = 01, 10, or 11 8.3.2.6 Hybrid PWM & I Dimming Control Hybrid PWM & I dimming control combines PWM dimming and LED current-dimming control methods. With this dimming control, better optical efficiency is possible from the LEDs compared to pure PWM control while still achieving smooth and accurate control and low brightness levels. The switch point from current-to-PWM control can be set to get the optimal compromise between good matching of the LEDs brightness/white point at low brightness and good optical efficiency. 16 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 LP8557, LP85571 www.ti.com SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 Feature Description (continued) PWM CONTROL LED CURRENT 100% 25% 100% 50% BRIGHTNESS HYBRID PWM & CURRENT CONTROL PWM CONTROL CURRENT CONTROL LED CURRENT 100% 50% 25% 25% 50% 100% BRIGHTNESS PURE CURRENT CONTROL LED CURRENT 100% 50% 25% 25% 50% 100% BRIGHTNESS Figure 29. Dimming Methods 8.3.2.7 Phase Shift PWM Scheme The phase shift PWM (PSPWM) scheme allows delay of the time when each LED current sink is active. When the LED current sinks are not activated simultaneously, the peak load current from the boost output is greatly decreased. This reduces the ripple seen on the boost output and allows smaller output capacitors to be used. Reduced ripple also reduces the output ceramic capacitor audible ringing. The PSPWM scheme also increases the load frequency seen on the boost output by up to six times, therefore transferring the possible audible noise to the frequencies outside the audible range. The phase difference between each active driver is automatically determined as 360°/number of active drivers. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 17 LP8557, LP85571 SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 www.ti.com Feature Description (continued) Phase Delay 60 degrees Cycle Time 1/(fPWM) LED1 LED2 LED3 LED4 LED5 LED6 Figure 30. Phase Shift PWM Dimming Scheme Diagram 8.3.3 Slope and Advanced Slope The transition time between two brightness values can be programmed with the STEP bits from 0 to 200 ms. The same slope time is used for sloping up and down. With advanced slope the brightness changes can be made more pleasing to a human eye. It is implemented with a digital smoothing filter. The filter strength is set with SMOOTH bits. Brightness (PWM) Sloper Input Brightness (PWM) PWM Output Time Normal slope Advanced slope Time Slope Time Figure 31. Slope and Advanced Slope 8.3.4 LED String Count Auto Detection The LP8557 and LP8557I can auto-detect the number of the LED strings attached. During the auto-detect routine, the devices automatically remove the unused current sink(s) and adjust the phasing of the remaining current sinks. The LED OPEN* fault condition is not supported with auto-detect function enabled. On the LP8557I, the user may disable the function by setting CONFIG.AUTO bit to 0 via an I2C write. 18 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 LP8557, LP85571 www.ti.com SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 Feature Description (continued) 8.3.5 EMI Reduction Schemes LP8557I features two EMI reduction schemes. By default, the schemes are disabled; however, the schemes can be enabled by I2C writes to SSEN and SREN bits in COMMAND register. The schemes are unavailable on the LP8557. The first scheme, programmable slew rate control, uses a combination of three drivers for boost switch. Enabling all three drivers allows boost switch on/off transition times to be the shortest. On the other hand, enabling just one driver allows boost switch on/off transition times to be the longest. The longer the transition times, the lower the switching noise on the SW terminal. It should also be noted that the shortest transition times bring the best efficiency as the switching losses are the lowest. This scheme can be enabled by setting SREN=1 with an I2C write. The second EMI reduction scheme is the spread spectrum scheme. This scheme deliberately spreads the frequency content of the boost switching waveform, which inherently has a narrow bandwidth, makes the switching waveform's bandwidth wider and ultimately reduces its EMI spectral density. This scheme can be enabled by setting SSEN = 1 with an I2C write. Duty cycle D = 1 - VIN / VOUT tSW = 1 / fSW Slew rate control, programmable Spread spectrum scheme, programmable pseudo random duty cycle changes minimize EMI Figure 32. EMI Reduction Schemes 8.3.6 Fault Detection The LP8557 and LP8557I have fault detection for LED SHORT, UVLO, BST_OVP, BST_OCP, BST_UV, and TSD. Additionally, the LP8557I can support LED OPEN* fault. Faults are recorded in the STATUS register. Each time the STATUS register is read it is automatically cleared. 8.3.6.1 LED Short Detection Voltages at the individual current sinks are constantly monitored for the LED SHORT fault. This fault may occur when some LEDs in a string are electrically bypassed making that LED string shorter than the other LED strings. The reduced forward voltage causes the current sink attached to that string to have a higher headroom voltage than the other current sinks. When the headroom voltage is higher than the fault comparator threshold (configured with the 0V field in the LEDEN register), that current sink is disabled, and the PWM phasing is automatically adjusted. The fault comparator threshold is at 2 V, typical. 8.3.6.2 LED OPEN* Detection When the auto-detect function is disabled, each current sink is also monitored for the LED OPEN* condition. The condition is set when the headroom voltage on one or more current sinks is below the LOW comparator threshold, and the boost voltage is at the maximum. This fault condition may be caused by one or more OPEN LED strings or by one or more current sinks shorted to GND. The LP8557I immediately shuts down the backlight whenever an LED OPEN* condition is detected on any enabled LED drivers. The backlight does not turn on again (regardless of the COMMAND.ON bit) until the STATUS register is read. 8.3.6.3 Undervoltage Detection The device continuously monitors the voltage on the VDD pin. When the VDD voltage drops below 2.5 V the backlight is immediately shut down, and the UVLO bit is set in the STATUS register. The backlight automatically starts again when the voltage has increased above 2.5 V + 50 mV hysteresis. Hysteresis is implemented to avoid continuously triggering undervoltage. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 19 LP8557, LP85571 SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 www.ti.com Feature Description (continued) 8.3.6.4 Thermal Shutdown If the internal temperature reaches 150°C, the deviceimmediately shuts down the backlight to protect it from damage. The TSD bit is also set in the STATUS register. The device re-activates the backlight again when the internal temperature drops below 130°C. 8.3.6.5 Boost Overcurrent Protection The device automatically limits boost current to 2.4 A . When the 2.4-A limit is reached the BST_OCP bit is set in the STATUS register. It is normal for the device to trigger the boost current limit during the start-up or sudden brightness changes. The STATUS register can be cleared by reading the bit. If the bit is permanently set, it may indicate an issue in the application. 8.3.6.6 Boost Overvoltage Protection The device automatically limits boost voltage to VBOOST_MAX + 1.6 V. When the limit is reached the BST_OVP bit is set in the STATUS register. It is normal for the device to trigger the boost OVP limit during the start-up or sudden brightness changes. The status register can be cleared by reading the bit. If the bit is permanently set, it may indicate an issue in the application. 8.3.6.7 Boost Undervoltage Protection The device can detect when the boost voltage is below VBOOST – 2.5 V for longer than 6 ms. When the threshold is reached the BST_UV bit is set in the STATUS register. 8.4 Device Functional Modes 8.4.1 Shutdown Mode The device is in shutdown mode when the VDD pin is low. Current consumption in this mode from VDD pin is < 1 µA. 8.4.2 Active Mode In active mode the backlight is enabled either with setting the ON register bit high (LP8557I) or by activating PWM input (LP8557). The power supplying the VDD pin must be present. Brightness is controlled with I2C writes to brightness registers or by changing PWM input duty cycle (operation without I2C control). Configuration registers are not accessible in Active mode to prevent damage to the device by accidental writes. Current consumption from VDD terminal in this mode is typically 2.2 mA when LEDs are not drawing any current. 8.5 Programming 8.5.1 I2C-Compatible Serial Bus Interface 8.5.1.1 Interface Bus Overview The I2C-compatible synchronous serial interface provides access to the programmable functions and registers on the device. This protocol uses a two-wire interface for bi-directional communications between the devices connected to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL). These lines must be connected to a positive supply, via a pull-up resistor and remain HIGH even when the bus is idle. The default 7-bit I2C address for the LP8557I slave is 2Ch. 20 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 LP8557, LP85571 www.ti.com SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 Programming (continued) 8.5.1.2 Start and Stop Conditions START and STOP conditions classify the beginning and the end of the I2C session (see Figure 33). A START condition is defined as SDA transitioning from HIGH to LOW while SCL is HIGH. A STOP condition is defined as SDA transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP conditions. The I2C bus is considered busy after a START condition and free after a STOP condition. During data transmission the I2C master can generate repeated START conditions. A START and a repeated START condition are equivalent function-wise. The data on SDA must be stable during the HIGH period of the clock signal (SCL). In other words, the state of SDA can only be changed when SCL is LOW. SDA SCL S P Start Condition Stop Condition Figure 33. Start And Stop Conditions After the START condition, the I2C master sends the 7-bit address followed by an eighth read or write bit (R/W). R/W = 0 indicates a WRITE, and R/W = 1 indicates a READ. The second byte following the chip address selects the register address to which the data is written. The third byte contains the data for the selected register. 8.5.1.3 Data Transactions One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock (SCL). Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New data should be sent during the low SCL state. This protocol permits a single data line to transfer both command/control information and data using the synchronous serial clock. SDA SCL Data Line Stable: Data Valid Change of Data Allowed Figure 34. Bit Transfer Each data transaction is composed of a START Condition, a number of byte transfers (set by the software) and a STOP Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following sections provide further details of this process. 8.5.1.4 Acknowledge Cycle The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte transferred, and the acknowledge signal sent by the receiving device. The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to receive the next byte. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 21 LP8557, LP85571 SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 www.ti.com Programming (continued) Data Output By Transmitter Transmitter Stays Off the Bus During the Acknowledgement Clock Data Output By Receiver Acknowledgement Signal from Receiver SCL 1 2 3-6 7 8 9 S Start Condition Figure 35. Bus Acknowledge Cycle 8.5.1.5 Acknowledge After Every Byte Rule The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge signal after every byte received. There is one exception to the acknowledge after every byte rule. When the master is the receiver, it must indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down. 8.5.1.6 Control Register Write Cycle • Master device generates start condition. • Master device sends slave address (7 bits) and the data direction bit (r/w = 0). • Slave device sends acknowledge signal if the slave address is correct. • Master sends control register address (8 bits). • Slave sends acknowledge signal. • Master sends data byte to be written to the addressed register. • Slave sends acknowledge signal. • If master sends further data bytes the control register address is incremented by one after acknowledge signal. • Write cycle ends when the master creates stop condition. 8.5.1.7 Control Register Read Cycle • Master device generates a start condition. • Master device sends slave address (7 bits) and the data direction bit (r/w = 0). • Slave device sends acknowledge signal if the slave address is correct. • Master sends control register address (8 bits). • Slave sends acknowledge signal. • Master device generates repeated start condition. • Master sends the slave address (7 bits) and the data direction bit (r/w = 1). • Slave sends acknowledge signal if the slave address is correct. • Slave sends data byte from addressed register. • If the master device sends acknowledge signal, the control register address is incremented by one. Slave device sends data byte from addressed register. • Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop condition. 22 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 LP8557, LP85571 www.ti.com SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 Programming (continued) Table 1. Data Read and Write Cycles ADDRESS MODE Data Read [Ack] [Ack] [Ack] [Register Data] … additional reads from subsequent register address possible Data Write [Ack] [Ack] [Ack] … additional writes to subsequent register address possible Data from master; [] Data from slave 8.5.1.8 Register Read and Write Detail S Slave Address (7 bits) '0' A Control Register Add. A (8 bits) Register Data (8 bits) A P Data transfered, byte + Ack R/W From Slave to Master A - ACKNOWLEDGE (SDA Low) S - START CONDITION From Master to Slave P - STOP CONDITION Register Write Format Figure 36. Register Write Format S Slave Address (7 bits) '0' A Control Register Add. A Sr (8 bits) Slave Address (7 bits) R/W '1' A Data- Data (8 bits) A/ P NA Data transfered, byte + Ack/NAck R/W Direction of the transfer will change at this point From Slave to Master A - ACKNOWLEDGE (SDA Low) NA - ACKNOWLEDGE (SDA High) From Master to Slave S - START CONDITION Sr - REPEATED START CONDITION P - STOP CONDITION Register Read Format Figure 37. Register Read Format Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 23 LP8557, LP85571 SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 www.ti.com 8.6 Register Maps The register map is useful for LP8557I users intending to re-configure the register reset values. If reconfiguration is necessary, it has to be done every time the power on VDD pin is recycled. There is a restriction on register writes. The COMMAND, BRTLO, and BRTHI registers can be written at any time; however, the remaining registers only accept writes when the COMMAND.ON bit is low. All registers can be read at any time. Many registers contain empty bit locations. These blank areas are reserved for future use. When writing to a register any empty fields must not be modified; when reading a register, these empty fields should be ignored. 8.6.1 Register Bit Descriptions 8.6.1.1 COMMAND Address: 0x00h Reset: 0x00h (LP8557I) D7 D6 D5 RESET D4 D3 — D2 D1 D0 SREN SSEN ON Bits Field Type Default 7 RESET R/W 0b Description 6:3 reserved R/O 0000b 2 SREN R/W 0b Enable the boost slew rate control. 0 = Slew-rate control off (Default) 1 = Slew-rate control on 1 SSEN R/W 0b Enable the spread-spectrum boost clocking. 0 = Spread-spectrum off (Default) 1 = Spread-spectrum on 0 ON R/W See Description Write 1 to reset the device. This bit is self-clearing and is always 0 when read. Turn on the backlight. 0 = backlight off (Default) 1 = backlight on The COMMAND.ON bit is used to turn on the backlight. The COMMAND.SSEN and COMMAND.SREN bits may be updated at any time. It is not necessary for the backlight to be off when changing COMMAND.SSEN or COMMAND.SREN. 24 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 LP8557, LP85571 www.ti.com SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 8.6.1.2 STATUS Address: 0x01h Reset: 0x00h D7 D6 D5 D4 D3 D2 D1 D0 LED_OPEN* LED_SHORT – BST_UV BST_OVP BST_OCP TSD UVLO Description Bits Field Type Default 7 LED_OPEN* R/O 0b An LED_OPEN* condition was detected on one or more strings. The condition is set when the headroom voltage on one or more current sinks is below the LOW comparator threshold, and the boost voltage is at the maximum. This fault condition may be caused by one or more OPEN LED strings or by one or more current sinks shorted to GND. Once set this bit stays set until the STATUS register is read. An LED_OPEN* condition turns off the backlight when CONFIG.AUTO is 0. When CONFIG.AUTO is 1, the condition is never set. 6 LED_SHORT R/O 0b An LED SHORT condition was detected on one or more strings. The condition is set when the headroom voltage on one or more current sinks is above the FAULT comparator threshold and at least one driver has the headroom voltage in regulation (between LOW and MID comparator thresholds). This fault condition may be caused by one or more shorted LEDs on one or more (but not all) strings. Once set this bit stays set until the STATUS register is read. 5 reserved R/O 0b 4 BST_UV R/O 0b A boost output undervoltage condition was detected. The boost voltage is 2.5 V (typical) or more below the target. Once set this bit stays set until the STATUS register is read. 3 BST_OVP R/O 0b A boost overvoltage protection condition was detected. The boost voltage is 1.6 V (typical) above the VMAX value. Once set this bit stays set until the STATUS register is read. 2 BST_OCP R/O 0b A boost overcurrent protection condition was detected. Once set this bit stays set until the STATUS register is read. 1 TSD R/O 0b A thermal shutdown condition was detected. Once set, this bit stays set until the STATUS register is read. A thermal shutdown condition turns off the backlight. 0 UVLO R/O 0b An input undervoltage lockout condition was detected. Once set, this bit stays set until the STATUS register is read. An undervoltage lockout condition turns off the backlight. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 25 LP8557, LP85571 SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 www.ti.com 8.6.1.3 BRTLO Address: 0x03h Reset: 0x00h D7 D6 D5 D4 D3 D2 BRT[3:0] D1 D0 — Bits Field Type Default Description 7:4 BRT[3:0] R/W 0000b Least significant bits of the 12-bit wide brightness level. If controlling the brightness with 8-bit resolution, writing to this register is not needed. 6:0 reserved R/O 0000b Reserved. 8.6.1.4 BRTHI Address: 0x04h Reset: 0x00h D7 D6 D5 D4 D3 D2 D1 D0 BRT[11:4] Bits Field Type Default 7:0 BRT[11:4] R/W 00h Description Most significant bits of the 12-bit wide brightness level. If controlling the brightness with the 8-bit resolution, writing to this register is all that is needed. The brightness level can be updated via one (8 bits) or two (16 bits) register writes. The internal brightness level is 12 bits wide and is only updated when the BRTHI register is written. If the BRTHI register is written without a previous write to the BRTLO register, then the lower order bits of the internal brightness is synthesized from the BRTHI register value. BRTLO 26 BRTHI Brightness Comments write 0x95 write 0xFC 0xFC9 BRTLO[3:0] is ignored write 0x10 write 0xDC 0xDC1 set to an exact 12-bit value no write write 0x8C 0x8C8 synthesize low order bits no write write 0x0C 0x0C0 synthesize low order bits no write write 0x00 0x000 0% brightness no write write 0xFF 0xFFF 100% brightness Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 LP8557, LP85571 www.ti.com SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 8.6.1.5 CONFIG Address: 0x10h Reset: 0x07h (LP8557I) D7 D6 D5 PWMSB D4 D3 — D2 D1 AUTO D0 BRTMODE[1:0] Bits Field Type Default Description 7 PWMSB R/W 0b 6:3 reserved R/O 0000b 2 AUTO R/W 1b Automatic LED string configuration0 = enable LED strings using just LEDEN.ENABLE 1 = disable all open LED strings (Default) 1:0 BRTMODE R/W 11b Brightness mode 00 = PWM 01 = BRTHI/BRTLO registers 10 = PWM × unshaped BRTHI/BRTLO registers 11 = Unshaped PWM × BRTHI/BRTLO registers Enables PWM standby mode 0 = COMMAND.ON alone turns the backlight on/off (Default) 1 = turn off the backlight after 52 ms of PWM pin low The AUTO bit is set, and the LED string configuration is done automatically. The LP8557I allows users to disable the auto-detect function by setting AUTO bit to 0b. 8.6.1.6 CURRENT Address: 0x11h Reset: 0x07h (LP8557I) D7 D6 D5 ISET D4 D3 —— Bits Field Type Default 7 ISET R/W 0b 6:3 reserved R/O 0000b 2:0 MAXCURR R/W 111b D2 D1 D0 MAXCURR[2:0] Description Set full-scale LED current via the ISET pin. 0 = Full-scale current is set with MAXCURR bits. (Default) 1 = Full-scale current is set with an external, RISET, resistor. Full-scale current (100% brightness). 000 = 5 mA 001 = 10 mA 010 = 13 mA 011 = 15 mA 100 = 18 mA 101 = 20 mA 110 = 23 mA 111 = 25 mA (Default) The ISET bit determines how the maximum LED current is set. On the LP8557I (ISET = 0), the maximum LED current is 25 mA. It may be re-configured via the I2C interface by overriding MAXCURR bits. Note that reconfiguration must be done every time the power on VDD pin is recycled. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 27 LP8557, LP85571 SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 www.ti.com 8.6.1.7 PGEN Address: 0x12h Reset: 0x29h (LP8557I) D7 D6 PFSET — D5 D4 D3 THRESHOLD Bits Field Type Default 7 PFSET R/W 0b 6:3 reserved R/O 0101b 5:3 THRESHOLD R/W EPROM 2:0 PFREQ R/W 001b D2 D1 D0 PRFEQ[2:0] Description Set PWM output frequency via the FSET pin. 0 = PWM output frequency is set with PRFEQ bits. (Default) 1 = PWM output frequency is set with an external, RFSET, resistor. Adaptive dimming threshold. PWM dimming is used below threshold, and current dimming is used above threshold. 000 = 100% current diming 001 = PWM below 1.5625% (6-bit PWM) 010 = PWM below 3.125% (7-bit PWM) 011 = PWM below 6.25% (8-bit PWM) 100 = PWM below 12.5% (9-bit PWM) 101 = PWM below 25% (10-bit PWM) 110 = PWM below 50% (11-bit PWM) 111 = 100 %PWM below (12-bit PWM) PWM output frequency 000 = 4.9 kHz 001 = 9.8 kHz (Default) 010 = 14.6 kHz 011 = 19.5 kHz 100 = 24.4 kHz 101 = 29.3 kHz 110 = 34.2 kHz 111 = 39.1 kHz The PFSET bit distinguishes how the PWM dimming frequency is set. On the LP8557I (PFSET = 0), the PWM dimming frequency is 9.8 kHz by default. It may be re-configured via I2C interface by overriding PFREQ bits. Note that re-configuration must be done every time the power on VDD pin is recycled. 28 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 LP8557, LP85571 www.ti.com SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 8.6.1.8 BOOST Address: 0x13h Reset: 0x02h (LP8557I) D7 D6 BFSET BCSET D5 D4 D3 D2 — D1 D0 BCOMP BFREQ Bits Field Type Default Description 7 BFSET R/W 0b Set boost frequency via the FSET pin. 0 = Boost frequency is set with BFREQ bits. (Default) 1 = boost frequency is set with an external, RFSET, resistor. 6 BCSET R/W 0b Set boost inductor size via ISET pin. 0 = boost inductor and compensation is set with BCOMP bit. (Default) 1 = boost inductor is set with an external, RISET, resistor. 5:2 reserved R/O 0000b 1 BCOMP R/W 1b Boost compensation options. 0 = Boost compensation option 0 1 = Boost compensation option 1 (Default). 0 BFREQ R/W 0b Boost frequency. 0 = 500 kHz (Default) 1 = 1 MHz The BFSET bit distinguishes how the boost switching frequency is set. If BFSET = 0, the boost switching frequency is set by the BFREQ bit. If BFSET = 1, the switching frequency is set with an external resistor. On the LP8557I (BFSET = 0), the boost switching frequency is 500 kHz by default. It may be re-configured via the I2C interface by overriding the BFREQ bit. Please note the re-configuration must be done every time the power on the VDD pin is recycled. The BCSET bit distinguishes how the boost inductor and compensation is set. If BCSET = 0, the boost inductor and compensation is set by the BCOMP bit. If BCSET = 1, the boost inductor and compensation is set with an external resistor. On the LP8557I (BCSET = 0), the boost compensation is set to option 1 by default. It may be re-configured via I2C interface by overriding BCOMP bit. Please note the re-configuration must be done every time the power on the VDD pin is recycled. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 29 LP8557, LP85571 SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 www.ti.com 8.6.1.9 LEDEN Address: 0x14h Reset: 0xBFh (LP8557I) D7 D6 D5 D4 D3 - D2 D1 D0 ENABLE[6:1] Bits Field Type Default 7:6 reserved R/W 10b 5:0 ENABLE R/W 111111b Description LED string enables. 000001 = Only 1 current sink enabled. . . 001111 = Current sinks 1-4 enabled. 011111 = Current sinks 1-5 enabled. 111111 = All 6 current sinks enabled (Default) The ENABLE field configures the strings if the AUTO bit is 0. The LP8557I allows re-configuration of the ENABLE bits via I2C writes. Note that re-configuration must be done every time the power on the VDD pin is recycled. 8.6.1.10 STEP Address: 0x15h Reset: 0x00h (LP8557I) D7 D6 D5 D4 SMOOTH[1:0] D3 D2 — Bits Field Type Default 7:6 SMOOTH R/W 00b 5:2 reserved R/W 0000b 1:0 STEP R/W 00b D1 D0 STEP[1:0] Description Filter strength for digital smoothing filter. 00 = no smoothing (Default) 10 = light smoothing 10 = medium smoothing 11 = heaving smoothing Ramp time for a 0% to 100% current change. 00 = 0 ms (Default) 01 = 50 ms (12.2 µs/12-bit LSB) 10 = 100 ms (24.4 µs/12-bit LSB) 11 = 200 ms (48.8 µs/12-bit LSB) On LP8557I, it is possible to enable slope and advanced slope functions by re-configuration of the STEP and SMOOTH bits appropriately via I2C writes. Note that re-configuration must be done every time power on the VDD pin is recycled. The STEP field controls the rate of brightness level changes (slope function). Brightness transitions have a fixed step time. The time required to complete a ramp between two levels also depends upon the difference between the starting and ending current levels. For example, when STEP is set to 10b a brightness transition from 0% to 100% takes 100 ms, while a transition from 50% to 100% takes 50 ms. The SMOOTH field controls the digital smoothing filter (advanced slope function). This filter behaves much like an RC filter. It can be used to remove the overshoot that appears to occur on large brightness changes. The actual amount of smoothing is tailored for the STEP field setting. For example, medium filter strength is higher for 100-ms ramp times than for 50-ms ramp times. This gives 16 possible brightness-level ramping configurations. 30 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 LP8557, LP85571 www.ti.com SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information 9.1.1 Designing With LP8557 The LP8557 is intended for applications without an I2C master. It can be fully controlled with an external PWM signal. Boost switching frequency, boost compensation, PWM dimming frequency, and the maximum LED current can be set with external resistors. 9.1.1.1 Setting Boost Switching and PWM Dimming Frequencies Boost switching frequency and PWM dimming frequency are set by connecting a resistor from the FSET pin to GND. Available options are shown in Table 2. Table 2. Setting Boost Switching and PWM Dimming Frequencies With an External Resistor RFSET [Ω] (TOLERANCE) ƒSW (kHz) ƒPWM (kHz) 470k - 1M (±5%) 500 4.9 300k, 330k (±5%) 500 9.8 200k (±5%) 500 14.6 147k, 150k, 154k, 158k (±1%) 500 19.5 121k (±1%) 500 24.4 100k (±1%) 500 29.3 86.6k (±1%) 500 34.2 75.0k (±1%) 500 39.1 63.4k (±1%) 1000 4.9 52.3k, 53.6k (±1%) 1000 9.8 44.2k, 45.3k (±1%) 1000 14.6 39.2k (±1%) 1000 19.5 34.0k (±1%) 1000 24.4 30.1k (±1%) 1000 29.3 26.1k (±1%) 1000 34.2 23.2k (±1%) 1000 39.1 0 (grounded) 500 9.8 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 31 LP8557, LP85571 SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 www.ti.com 9.1.1.2 Setting Boost Compensation For stable LP8557 boost operation, appropriate boost compensation must be selected based on the selected boost switching frequency and the boost inductance. Table 3 shows recommended boost compensation options based on the boost switching frequency and selected boost circuit inductance. Table 3. Recommended Boost Compensation Options Based on the Boost Switching Frequency and Inductance ƒSW (kHz) L (µH) RECOMMENDED BOOST COMPENSATION OPTION 500 10 15 22 1 1 0 1000 4.7 6.8 10 1 1 0 The LP8557 boost converter compensation is set by placing an external resistor, RISET, from the ISET pin to GND. Note that the ISET pin is shared for setting the full-scale LED current in addition to setting the boost compensation. Setting the boost compensation and the full-scale LED current using an external resistor is shown in Table 4. 9.1.1.3 Setting Full-Scale Led Current The LP8557 full-scale current is set by placing an external resistor, RISET, from the ISET pin to GND. Note that the ISET pin is shared for setting the boost compensation in addition to the full-scale LED current. Setting the boost compensation and the full-scale LED current using an external resistor is shown in Table 4. Table 4. Setting Full-Scale LED Current and Boost Compensation Using an External Resistor RISET [Ω] (TOLERANCE) BOOST COMPENSATION OPTION ILED (mA) 470k - 1M (±5%) 1 5 300k, 330k (±5%) 1 10 200k (±5%) 1 13 147k, 150k, 154k, 158k (±1%) 1 15 121k (±1%) 1 18 100k (±1%) 1 20 86.6k (±1%) 1 23 75.0k (±1%) 1 25 63.4k (±1%) 0 5 52.3k, 53.6k (±1%) 0 10 44.2k, 45.3k (±1%) 0 13 39.2k (±1%) 0 15 34.0k (±1%) 0 18 30.1k (±1%) 0 20 26.1k (±1%) 0 23 23.2k (±1%) 0 25 0 (grounded) 1 20 9.1.2 Designing With LP8557I The LP8557I is intended for applications that can utilize an I2C master to control the device. Use of an external PWM signal is allowed for controlling the brightness levels; however, I2C commands are required to turn the backlight on or off. Boost switching frequency, boost compensation, PWM dimming frequency, and the maximum LED current are set to default values. Re-configuration is possible with I2C writes; however, re-programming has to be done every time power on the VDD pin is recycled. 32 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 LP8557, LP85571 www.ti.com SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 9.1.2.1 Setting Boost Switching Frequency The LP8557I boost converter switching frequency is set to 500 kHz by default. It may be re-programmed by overriding the BFREQ bit with an I2C write. Table 5 shows the boost switching frequency options available. Table 5. Available Boost Switching Frequencies BFREQ ƒSW [kHz] 0 500 1 1000 9.1.2.2 Setting Boost Compensation For stable LP8557I boost operation, appropriate boost compensation must be selected based on the selected boost switching frequency and the boost inductance. Table 6 shows recommended boost compensation options based on the boost switching frequency and selected boost circuit inductance. Table 6. Recommended Boost Compensation Options Based on the Boost Switching Frequency and Inductance ƒSW (kHz) L (µH) RECOMMENDED BOOST COMPENSATION OPTION 500 10 15 22 1 1 0 1000 4.7 6.8 10 1 1 0 The LP8557I boost converter compensation is set to option 1 by default. It may be re-programmed by overriding the BCOMP bit with an I2C write. Table 7 shows available boost compensation options. Table 7. Available Boost Compensation Options BCOMP BOOST COMPENSATION OPTION 0 0 1 1 9.1.2.3 Setting PWM Dimming Frequency The LP8557I PWM dimming frequency is set to 9.8 kHz by default. It may be re-programmed by overriding the PFREQ bits with an I2C write. Table 8 summarizes available PWM dimming frequencies. Table 8. Available PWM Dimming Frequencies PFREQ ƒPWM (kHz) 000 4.9 001 9.8 010 14.6 011 19.5 100 24.4 101 29.3 110 34.2 111 39.1 9.1.2.4 Setting Full-Scale LED Current The LP8557I full-scale LED current is set to 25 mA by default. It may be re-programmed by overriding MAXCURR bits with an I2C write. Table 9 shows available full-scale LED current levels. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 33 LP8557, LP85571 SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 www.ti.com Table 9. Available Full-Scale LED Currents MAXCURR ILED [mA] 000 5 001 10 010 13 011 15 100 18 101 20 110 23 111 25 9.2 Typical Applications 9.2.1 LP8557 PWM-Only Option L1 2.7 V ± 5.5 V D1 VIN 7 V ± 28 V 1.1 ” VOUT / VIN ” 11 T VDD SW PWM PWM VOUT COU CIN FB LED1 LED2 LP8557 LED3 LED4 RFSET FSET LED5 RISET ISET LED6 GNDs Figure 38. LP8557 PWM-Only Device Option 9.2.1.1 Design Requirements Table 10. Recommended Inductance MIN TYP ƒsw = 1 MHz 3.29 4.7 - 10 ƒsw = 500 kHz 7 10 - 22 MAX UNIT µH Table 11. Recommended Output Capacitance (1) MIN (1) 34 ƒsw = 1 MHz 2 ƒsw = 500 kHz 2 TYP MAX UNIT µF The recommended output capacitance is the de-rated capacitance. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 LP8557, LP85571 www.ti.com SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 9.2.1.2 Detailed Design Procedure 9.2.1.2.1 Boost Output Capacitor Selection The LP8557 inductive boost converter typically requires two 4.7-µF output capacitors. The voltage rating of the capacitor must be 35 V or higher as the OVP threshold is at 29.6 V (typ). Pay careful attention to the capacitor tolerance and DC bias response. For proper operation the degradation in capacitance due to tolerance, DC bias, and temperature should stay above 2 µF. This might require placing more than two devices in parallel in order to maintain the required output capacitance over the device operating temperature and output voltage range. 9.2.1.2.2 Schottky Diode Selection The Schottky diode must have a reverse breakdown voltage greater than the LP8557’s maximum output voltage. Additionally, the diode must have an average current rating high enough to handle the LP8557 maximum output current; at the same time the diode's peak current rating must be high enough to handle the peak inductor current. Schottky diodes are required due to their lower forward voltage drop (0.3V to 0.5V) and their fast recovery time. 9.2.1.2.3 Inductor Selection The chosen inductor must be from 10 to 22 µH (for 500-kHz operation) or 4.7 to 10 µH (for 1-MHz operation) and must have a saturation rating equal to, or greater than, the circuit's peak operating current. IPEAK can be found by the following calculation: I PEAK = é æ IOUT ´ VOUT VIN V ´ efficiency ö ù +ê x ç 1 - IN ÷ú VIN ´ efficiency êë 2 ´ ƒSW ´ L è VOUT ø úû (1) This assumes the device is operating in continuous conduction mode (CCM) which is typically the case when operating near the peak current. For smaller rated inductors, and when the device is operating in discontinuous conduction mode (DCM), the peak current can be found from: I PEAK = ƒSW 2 ´ IOUT ´ (VOUT - VIN ´ efficiency) ´ L ´ efficiency (2) The device operates in CCM when the following is true:   æ IOUT ´ VOUT VIN V ´ efficiency ö > ´ ç 1 - IN ÷ VIN ´ efficiency ƒSW ´ 2 ´ L è VOUT ø (3) 9.2.1.2.4 Boost Input andVDD Capacitor Selection The LP8557 VDD pin is typically tied to the same supply as the input of the boost power stage (VIN node). A 10µF input capacitor is recommended on that node. The voltage rating of the capacitor must be at least 10 V. If a supply powering the VDD pin is different from a supply powering the boost power stage, then 10-µF input capacitors are required on both VDD and VIN nodes. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 35 LP8557, LP85571 SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 www.ti.com 9.2.1.3 Application Curves VTX = 5 V/div VSW 10V/DIV IL 500mA/DIV VTX = 5 V/div VSW 10V/DIV VIN = 200 mV/div IL 500mA/DIV IIN = 1 A/div ILED = 1 A/div ILED = 1 A/div 100mV/DIV 1Ps/DIV 1Ps/DIV Figure 39. Steady State Operation With Light Load (200 µA/String, 6 Strings) Figure 40. Steady State Operation With Medium Load (5 mA/String, 6 Strings) VTX = 5 V/div VDD 5V/DIV VTX = 5 V/div VIN = 200 mV/div VPWM 5V/DIV VIN = 200 mV/div IL 500mA/DIV ILED 10mA/DIV IIN = 1 A/div IIN = 1 A/div ILED = 1 A/div ILED = 1 A/div VFBac 100mV/DIV VBOOST 10V/DIV 1Ps/DIV 2ms/DIV Figure 41. Steady State Operation With Heavy Load (25 mA/String, 6 Strings) VDD 5V/DIV VTX = 5 V/div VPWM 5V/DIV VIN = 200 mV/div Figure 42. Start-Up With a 1% Input PWM Duty VDD 5V/DIV VPWM 5V/DIV VTX = 5 V/div VIN = 200 mV/div ILED 20mA/DIV ILED 20mA/DIV IIN = 1 A/div IIN = 1 A/div ILED = 1 A/div ILED = 1 A/div VBOOST 10V/DIV VBOOST 10V/DIV ms/DIV 2ms/DIV Figure 43. Start-Up With a 50% Input PWM Duty 36 IIN = 1 A/div VFBac VFBac 100mV/DIV VSW 10V/DIV VIN = 200 mV/div Figure 44. Start-Up With a 99% Input PWM Duty Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 LP8557, LP85571 www.ti.com SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 VDD 5V/DIV VTX = 5 V/div VPWM 5V/DIV VIN = 200 mV/div VDD 5V/DIV VTX = 5 V/div VPWM 5V/DIV VIN = 200 mV/div ILED 20mA/DIV ILED 20mA/DIV IIN = 1 A/div IIN = 1 A/div ILED = 1 A/div ILED = 1 A/div VBOOST 10V/DIV VBOOST 10V/DIV 4ms/DIV ms/DIV Figure 46. Shutdown Operation Figure 45. Start-Up With a 100% Input PWM Duty 9.2.2 LP8557I PWM and I2C Device Option 7 V ± 28 V 2.7 V ± 5.5 V L1 D1 1.1 ” 9OUT / VIN ” 11 VOUT VIN COUT CIN VDD PWM SW PWM FB LED1 LED2 LP8557I LED3 LED4 SDA SDA LED5 LED6 SCL SCL GNDs Figure 47. Typical Application With LP8557I PWM and I2C Device Option 9.2.2.1 Design Requirements See Design Requirements. 9.2.2.2 Detailed Design Procedure See Detailed Design Procedure. 9.2.2.3 Application Curves See Application Curves. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 37 LP8557, LP85571 SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 www.ti.com 10 Power Supply Recommendations The device is designed to operate from an input voltage supply range from 2.7 V and 5.5 V. This input supply should be well regulated and able to withstand maximum input current and maintain stable voltage without voltage drop even at load transition condition (start-up or rapid brightness change). The resistance of the input supply rail should be low enough that the input current transient does not cause drop high enough in the LP8557 supply voltage that can cause false UVLO fault triggering. If the input supply is located more than a few inches from the LP8557 additional bulk capacitance may be required in addition to the ceramic bypass capacitors. Depending on device EPROM configuration and usage case the boost converter is configured to operate optimally with certain input voltage range. Examples are seen in the Detailed Design Procedure. In uncertain cases, TI recommends contacting a TI sales representative for confirmation of the compatibility of the use case, EPROM configuration, and input voltage range. 11 Layout 11.1 Layout Guidelines Figure 50 shows an example layout which applies the required proper layout guidelines to be used as a guide for laying out the LP8557 circuit. Table 12. Application Circuit Component List COMPONENT MANUFACTURER VALUE PART NUMBER SIZE (mm) CURRENT/VOLTAGE RATING, RESISTANCE, TEMPERATURE L Cyntec 10 µH PIME051E 5.4 × 5.2 × 1.5 2 A, 0.153 Ω 35 V, X5R COUT Murata 4.7 µF (×2) GRM188R6YA475KE15D 0603 (1.6 × 0.8 × 0.8) CIN TDK 10 µF C1608X5R1A106M080AC 0603 (1.6 × 0.8 × 0.8) 10 V, X5R Diode Rohm Semiconductor Schottky RB160M-40 SOD-123 (3.5 × 1.6 × 0.8) VR = 40 V, VF = 0.5 V The following guidelines apply to both LP8557 and LP8557I. The LP8557 inductive boost converter sees a high switched voltage at the SW pin, and a step current through the Schottky diode and output capacitor each switching cycle. The high switching voltage can create interference into nearby nodes due to electric field coupling (I = C × dV/dt). The large step current through the diode and the output capacitor can cause a large voltage spike at the SW and FB pins due to parasitic inductance in the step current conducting path (V = L × di/dt). Board layout guidelines are geared towards minimizing this electric field coupling and conducted noise. Figure 48 highlights these two noise-generating components. 38 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 LP8557, LP85571 www.ti.com SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 Voltage Spike VOUT + VF Schottky Pulsed voltage at SW Current through Schottky Diode and COUT IPEAK IAVE = IIN Parasitic PCB Inductances Current through inductor Affected Node due to capacitive coupling Cp1 L Lp1 2.7V to 5.5V D1 Lp2 Up to 28V COUT VDD SW Lp3 FSET/SDA FB ISET/SCL LP8557 LCD Display ILED1 PWM/INT ILED6 GNDs Figure 48. LP8557 Inductive Boost Converter Showing Pulsed Voltage at SW (High dv/dt) And Current Through the Schottky Diode and COUT (High di/dt) The following list details the main (layout sensitive) areas of the LP8557’s inductive boost converter in order of decreasing importance: 1. Output Capacitor – COUT+ to Schottky diode cathode connection – COUT– to GND bump of the LP8557 connection 2. Schottky Diode – Schottky diode anode to SW connection – Schottky diode cathode to COUT+ connection 3. Inductor – SW Node PCB capacitance to other traces 4. Input Capacitor – CIN+ to VDD bump connection – CIN– to GND connection 11.1.1 Boost Output Capacitor Placement Because the output capacitor is in the path of the inductor current discharge path, it detects a high-current step from 0 to IPEAK each time the switch turns off and the Schottky diode turns on. Any inductance along this series path from the diodes cathode, through COUT, and back into the LP8557 GND pin contributes to voltage spikes (VSPIKE = LP_ × dI/dt) at SW and OUT. These spikes can potentially over-voltage the SW and FB pins, or feed through to GND. To avoid this, COUT+ must be connected as close to the cathode of the Schottky diode as possible, and COUT− must be connected as close to the LP8557 GND pins as possible. The best placement for COUT is on the same layer as the LP8557 to avoid any vias that can add excessive series inductance. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 39 LP8557, LP85571 SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 www.ti.com 11.1.2 Schottky Diode Placement In the LP8557’s boost circuit the Schottky diode is in the path of the inductor current discharge. As a result the Schottky diode sees a high-current step from 0 to IPEAK each time the switch turns off, and the diode turns on. Any inductance in series with the diode can cause a voltage spike (VSPIKE = LP_ × dI/dt) at SW and OUT. This can potentially over-voltage the SW pin, or feed through to VOUT and through the output capacitor, into GND. Connecting the anode of the diode as close to the SW pin as possible, and connecting the cathode of the diode as close to COUT+ as possible, reduces the inductance (LP_) and minimize these voltage spikes. 11.1.3 Inductor Placement The node where the inductor connects to the LP8557 SW bump has 2 challenges. First, a large switched voltage (0 to (VOUT + VF_SCHOTTKY)) appears on this node every switching cycle. This switched voltage can be capacitively coupled into nearby nodes. Second, there is a relatively large current (input current) on the traces connecting the input supply to the inductor and connecting the inductor to the SW bump. Any resistance in this path can cause voltage drops that can negatively affect efficiency and reduce the input operating voltage range. To reduce the capacitive coupling of the signal on SW into nearby traces, the SW bump-to-inductor connection must be minimized in area. This limits the PCB capacitance from SW to other traces. Additionally, highimpedance nodes that are more susceptible to electric field coupling need to be routed away from SW and not directly adjacent or beneath. This is especially true for traces such as ISET/SCL, FSET/SDA, and PWM. A GND plane placed directly below SW dramatically reduces the capacitance from SW into nearby traces. Lastly, limit the trace resistance of the VBATT-to-inductor connection and from the inductor-to-SW connection, by use of short, wide traces. 11.1.4 Boost Input and VDD Capacitor Placement The LP8557 input capacitor filters the inductor current ripple and the internal MOSFET driver currents. The inductor current ripple can add input voltage ripple due to any series resistance in the input power path. The MOSFET driver currents can add voltage spikes on the input due to the inductance in series with the VIN/VDD and the input capacitor. Close placement of the input capacitor to the VDD pin and to the GND pin is critical because any series inductance between VIN/VDD and CIN+ or CIN– and GND can create voltage spikes that could appear on the VIN/VDD supply line and GND. Close placement of the input capacitor at the input side of the inductor is also critical. The source impedance (inductance and resistance) from the input supply, along with the input capacitor of the LP8557, forms a series RLC circuit. If the output resistance from the source (RS, Figure 49) is low enough, the circuit is underdamped and has a resonant frequency (typically the case). Depending on the size of LS, the resonant frequency could occur below, close to, or above the LP8557's switching frequency. This can cause the supply current ripple to be: 1. Approximately equal to the inductor current ripple when the resonant frequency occurs well above the LP8557 switching frequency. 2. Greater than the inductor current ripple when the resonant frequency occurs near the switching frequency. 3. Less than the inductor current ripple when the resonant frequency occurs well below the switching frequency. Figure 49 shows the series RLC circuit formed from the output impedance of the supply and the input capacitor. The circuit is redrawn for the AC case where the VIN supply is replaced with a short to GND and the LP8557 + Inductor is replaced with a current source (ΔIL). Equation 1 is the criteria for an under-damped response. Equation 2 is the resonant frequency. Equation 3 is the approximated supply current ripple as a function of LS, RS, and CIN. As an example, consider a 3.8-V supply with 0.1-Ω of series resistance connected to CIN (10 µF) through 50 nH of connecting traces. This results in an under-damped input-filter circuit with a resonant frequency of 225 kHz. Because both the 1-MHz and 500-kHz switching frequency options lie above the resonant frequency of the input filter, the supply current ripple is probably smaller than the inductor current ripple. In this case, using Equation 3, the supply current ripple can be approximated as 0.2 times the inductor current ripple (using a 500-kHz switching frequency) and 0.051 times the inductor current ripple using a 1-MHz switching frequency. 40 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 LP8557, LP85571 www.ti.com SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 'IL L ISUPPLY LS RS SW VDD + - VIN Supply CIN LP8557 ISUPPLY RS LS 'IL CIN 2 1. RS 1 > L S x C IN 4 x L S2 2. f RESONANT = 3. 1 2S LS x CIN 1 2S x fSW x CIN I SUPPLYRIPPLE | ' I L x 2 RS § · 1 ¨2S x fSW x LS ¸ ¨ ¸ x x fSW S C 2 IN © ¹ 2 Figure 49. Input RLC Network Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 41 LP8557, LP85571 SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 www.ti.com 11.2 Layout Example VIN L1 VOUT D1 CIN GND (bottom) COUT GND (top) LP8557 LED1-6 Figure 50. LP8557 and LP8557I Layout Example Low-pass filter near VDD input pin is recommended for noisy power condition to prevent unstable LED current. 10 Ω plus approximately 2.2 µF to 10 µF can be used as low-pass filter components. 42 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 LP8557, LP85571 www.ti.com SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015 12 Device and Documentation Support 12.1 Device Support 12.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 13. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY LP8557 Click here Click here Click here Click here Click here LP85571 Click here Click here Click here Click here Click here 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP8557 LP85571 43 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) LP8557AYFQR ACTIVE DSBGA YFQ 16 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -30 to 85 D40 LP8557AYFQT ACTIVE DSBGA YFQ 16 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -30 to 85 D40 LP8557IAYFQR ACTIVE DSBGA YFQ 16 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -30 to 85 D41 LP8557IAYFQT ACTIVE DSBGA YFQ 16 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -30 to 85 D41 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of