LP8725TLE-D/NOPB

LP8725 www.ti.com SNVS618G – DECEMBER 2009 – REVISED MAY 2013 LP8725 Power Management Unit for Application or Multimedia Processors and Subsystems Check for Samples: LP8725 FEATURES KEY SPECIFICATIONS • • 1 2 • • • • • • Two High-Efficiency Step-Down DC-DC Converters, IOUT = 600 mA, With a 4-MHz Switching Frequency Using Small 1-µH Inductors, With Options up to 800 mA Three Digital LDOs for up to 300-mA Load Current Each Two Low-Noise Analog 300-mA LDOs Two Low-Input Low-Output Regulators, IOUT = 300 mA I2C-Compatible Interface for Control of Internal Registers Adjustable Startup Sequence Through Serial Interface or Configuration Thermal Shutdown Protection APPLICATIONS • • Multimedia Processors Portable Handheld Products • • • • 190 mV typ. Dropout Voltage on digital LDOs @ 300 mA 2% typ. Output Voltage Accuracy on digital and analog LDOs 10 μVrms Output Noise on analog LDOs ±2% typ. Output Voltage Bucks up to 93% efficiency 30-bump DSBGA package (0.5 mm pitch) DESCRIPTION This device is a multi-function programmable Power Management Unit (PMU), optimized for sub block power solutions. This device integrates two highly efficient 600-mA step-down DC-DC converters configurable up to 800-mA load with Dynamic Voltage Scaling (DVS) via the serial interface, two low-noise analog LDOs, three digital LDOs for up to 300 mA load current each, two Low-Input Low-Output (LILO) regulators, and an I2C-compatible serial interface to allow a host controller access to the internal control registers. The device also features programmable power-on sequencing. LDO regulators provide high PSRR and low noise ideally suited for supplying power to both analog and digital loads. The device can be configured either as a Sub_PMU for modules (for example, camera or multimedia modules) or as a stand-alone PMU that powers the processor itself. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2013, Texas Instruments Incorporated LP8725 SNVS618G – DECEMBER 2009 – REVISED MAY 2013 www.ti.com TYPICAL APPLICATION (SUB-PMU) VIN3 VIN1 2.2 PF VIN2 2.2 PF 2.2 PF VIN1 VIN3 VINB1 VIN2 VINB1 LDO1 4.7 µF LDO 1 D FB1 SW1 LDO2 1 PH GNDB1 4.7 µF Voltage Reference VINB2 LDO 2 D 1.2V to 3.3V @ 300 mA 1 µF Thermal Shutdown VINB2 4.7 µF 1 µF LP8725 Buck 1 0.8V to 3.0V @ 800 mA 1.2V to 3.3V @ 300 mA LDO3 UVLO FB2 LDO3 D 1.2V to 3.3V @ 300 mA 1 µF Buck 2 SW2 0.8V to 3.0V @ 800 mA LDO3_EN 1 PH GNDB2 4.7 µF VSI LDO4 B2_EN LDO4 A 10k 1.5k 1.2V to 3.3V @ 300 mA 1 µF 1.5k SDA LDO5 SCL LDO5 A RESET_N EN Serial Interface and Control 1 µF LILO1 DVS LILO 1 D 1.2V to 3.3V @ 300 mA 0.8V to 3.3V @300 mA 1 µF DEFSEL CONFIG LILO2 VINLILO1 LILO 2 D 2.2 PF 0.8V to 3.3V @300 `mA 1 µF VINLILO2 2.2 PF GND 2 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LP8725 LP8725 www.ti.com SNVS618G – DECEMBER 2009 – REVISED MAY 2013 TYPICAL APPLICATION (PMU) VIN3 VIN1 2.2 µF VIN2 2.2 µF 2.2 µF VIN1 VIN3 VIN2 VINB1 VINB1 LDO1 4.7 PF LDO 1 D FB1 SW1 LDO2 1 µH GNDB1 4.7 µF Voltage Reference VINB2 LDO 2 D 1.2V to 3.3V @ 300 mA 1µF Thermal Shutdown VINB2 4.7 µF 1 µF LP8725 Buck 1 0.8V to 3.0V @ 800 mA 1.2V to 3.3V @ 300 mA LDO3 UVLO FB2 LDO3 D 1.2V to 3.3V @ 300 mA 1 µF Buck 2 SW2 0.8V to 3.0V @ 800 mA 4.7 µF 1 µH GNDB2 VSI PS_HOLD LDO3_EN LDO4 LDO4 A 10k 1.5k 1.2V to 3.3V @ 300 mA 1 µF 1.5k SDA LDO5 SCL LDO5 A RESET_N PWR_ON Serial Interface & Control 1 µF LILO1 DVS LILO 1 D VIN1 1.2V to 3.3V @ 300 mA 0.8V to 3.3V @ 300 mA 1 µF DEFSEL CONFIG LILO2 VINLILO1 LILO 2 D 2.2 µF 0.8V to 3.3V @ 300 mA 1 µF VINLILO2 2.2 µF GND Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LP8725 3 LP8725 SNVS618G – DECEMBER 2009 – REVISED MAY 2013 www.ti.com CONNECTION DIAGRAMS 5 GNDB1 SW1 VINB1 VINB2 SW2 GNDB2 5 GNDB2 SW2 VINB2 VINB1 SW1 GNDB1 4 VIN LILO1 FB1 SCL SDA FB2 VIN LILO2 4 VIN LILO2 FB2 SDA SCL FB1 VIN LILO1 3 LILO1 EN/ PWR_ ON GND RESET_N B2_EN/ PS_HOLD LILO2 3 LILO2 B2_EN/ PS_HOLD RESET_N GND EN/ PWR_ ON LILO1 2 VIN1 CON FIG DEF SEL DVS LDO3_ EN VIN3 2 VIN3 LDO3_ EN DVS DEF SEL CON FIG VIN1 1 LDO1 LDO2 VIN2 LDO3 LDO5 LDO4 1 LDO4 LDO5 LDO3 VIN2 LDO2 LDO1 F E D C B A A Bottom View 4 B C D E F Top View Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LP8725 LP8725 www.ti.com SNVS618G – DECEMBER 2009 – REVISED MAY 2013 PIN DESCRIPTIONS Name Pin No. Description B2_EN/PS_HOLD B3 CONFIG=0: B2_EN is the enable for BUCK2 output if this pin is high and if BUCK2_EN register bit is set to 0. (B2_EN and the register bit are logical OR.) Internal 500 KΩ pull-down resistor in this configuration only. CONFIG=1: PS_HOLD is a power supply hold input from an external processor. CONFIG E2 Connect to GND for SUB_PMU or connect to VIN1 for PMU. DEFSEL D2 Control input that sets default voltages and start-up sequence. Must be hard wired to VIN1 or GND for specific application. When DEFSEL=VIN1 then setup 1 is used for default voltages and startup sequences. When DEFSEL=GND then setup 2 is used for default voltages and startup sequences. DVS C2 Dynamic Voltage Scaling (operational when REG 0x00 is '0'). DVS=1 then BUCK voltage set BUCK1_V1 is in use. DVS=0 then BUCK voltage set BUCK1_V2 is in use. This pin must be driven to its logic high or low whenever the BUCK1 or BUCK2 outputs are enabled. EN/PWR_ON E3 CONFIG=0: EN=1 turns on outputs or standby mode if EN=0. CONFIG=1: PWR_ON=1 starts power up sequence after 30 ms of de-bounce time. Internal 500K pulldown resistor. FB1 E4 BUCK1 Feedback. Active pull-down when BUCK1 turns off. FB2 B4 BUCK2 Feedback. Active pull-down when BUCK2 turns off. GND D3 IC Ground GNDB1 F5 BUCK1 Ground. GNDB2 A5 BUCK2 Ground. LDO1 F1 LDO1 output. LDO2 E1 LDO2 output. LDO3 C1 LDO3 output. LDO3_EN B2 Enable for LDO3 output if this pin is high and if LDO3_EN register bit is set to 0. (LDO3_EN and the register bit are logical OR.) Internal 500 KΩ pull-down resistor. LDO4 A1 LDO4 output. LDO5 B1 LDO5 output LILO1 F3 LILO1 output. LILO2 A3 LILO2 output. RESET_N C3 CONFIG=0: Goes high typ. 30 ms after EN=1 and goes low when EN=0. CONFIG=1: Goes high typ. 60 ms after PWR_ON=1 and goes low 30 ms after PS_HOLD=0. External pull-up resistor is needed, typical 10 kΩ. SCL D4 Serial Interface Clock Input. External pull-up resistor is needed, typical 1.5 kΩ. SDA C4 Serial Interface Data Input/Output. Open Drain output, external pull-up resistor is needed, typical 1.5 kΩ. SW1 E5 BUCK1 Switch node of DC-DC converter BUCK1. SW2 B5 BUCK2 Switch node of DC-DC converter BUCK2. VIN1 F2 Input for LDO1. VINB1 D5 Input for BUCK1. VIN2 D1 Input for LDO2 and LDO3. VINB2 C5 Input for BUCK2. VIN3 A2 Input for LDO4 and LDO5. VINLILO1 F4 Input for LILO1. VINLILO2 A4 Input for LILO2. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LP8725 5 LP8725 SNVS618G – DECEMBER 2009 – REVISED MAY 2013 www.ti.com DEVICE DESCRIPTION Operation Modes POWER-ON-RESET: In SUB_PMU configuration - After VIN1 goes above UVLO high threshold, then all internal registers of LP8725 are reset to the default values from the DEFSEL setting, after which LP8725 goes to STANDBY mode. In PMU configuration - When PWR_ON goes high while VIN1 is above the UVLO high threshold, all internal registers of LP8725 are reset to the default values from the DEFSEL setting. This process duration max is typically 500 µs. STANDBY: In STANDBY mode only serial interface is working and all other PMU functions are disabled – PMU is in low-power condition. In STANDBY mode LP8725 can be (re)configured via Serial Interface. The LP8725 only enters STANDBY mode automatically in SUB_PMU configuration. STARTUP: STARTUP sequence is defined by registers contents. STARTUP sequence starts: 1) If rising edge on EN-pin in SUB_PMU configuration. 2) After cooling down from thermal shutdown event if EN=1 in SUB_PMU configuration. 3) If PWR_ON is still high after 30 ms (typical de-bounce time) in PMU configuration. It is not recommended to write to LP8725 registers during STARTUP. If doing so then current STARTUP sequence may become undefined. In SUB_PMU configuration RESET_N is de-asserted 30 ms (typical) after EN=1. In PMU configuration RESET_N is de-asserted a further 30 ms (typical) after PWR_ON de-bounce time has ended. It is not recommended to write to LP8725 registers during startup. If doing so then current STARTUP sequence may become undefined. IDLE: The LP8725 will enter into IDLE mode (normal operating mode) after end of startup sequence. In IDLE mode all LDOs and BUCK can be enabled/disabled via Serial Interface. Also in IDLE mode the LP8725 can be (re)configured via Serial Interface. SHUTDOWN: SHUTDOWN sequence follows the reverse order of the startup sequence defined by registers contents: 1) If falling edge on EN-pin in SUB_PMU configuration. 2) If PS_HOLD and PWR_ON both go low for typically 30 ms in PMU configuration. Device immediately shuts down if the temperature exceeds thermal shutdown threshold TSD +160°C. RESET_N is asserted when the device starts to shut down. It is not recommended to write to LP8725 registers during SHUT DOWN. If doing so then current SHUTDOWN sequence may become undefined. In SUB_PMU configuration the device shuts down to STANDBY mode. In PMU configuration the device shuts down completely (so registers will be reset on next PWR_ON high). SLEEP: The load current for each of the LDO outputs should be no greater than 5mA when the device is put into SLEEP mode. In Sleep mode Ground current is minimized. SLEEP mode is controlled by the serial interface, Register 0x00 bit 1. SLEEP Mode is controlled by the Serial Interface. Table 1. Application Configuration (1) (2) (1) (2) 6 CONFIG Application Pin B3 Function Pin E3 Function Slave Address, DEFSEL = 1 Slave Address, DEFSEL = 0 GND SUB_PMU B2_EN EN 7h'78 7h'7A VIN1 PMU PS_HOLD PWR_ON 7h'79 7h'7B The LP8725 and LP8725-A are both configured as either SUB_PMU or PMU by the wiring of the CONFIG pin on the application of power to the device. These are dependent on whether DEFSEL is connected to VIN1 or GND when PWR_ON/EN=1. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LP8725 LP8725 www.ti.com SNVS618G – DECEMBER 2009 – REVISED MAY 2013 OFF UVLO=1 (POR) OFF UVLO=1 AND PWR_ON=1 STANDBY EN=0 SHUTDOWN SEQ EN=1 STARTUP SEQ PS_HOLD=0 (SHUTDOWN SEQ) (POR AND STARTUP SEQ) IDLE PS_HOLD=1 SLEEP_MODE=1 SLEEP_MODE=1 IDLE SLEEP SLEEP SLEEP_MODE=0 SLEEP_MODE=0 Figure 1. SUB-PMU Mode, CONFIG = 0 Figure 2. PMU Mode, CONFIG = 1 Additional Functions DVS: Dynamic Voltage Scaling allows using 2 set voltages for BUCKs. This is controlled via Serial Interface. BUCK1 can also be controlled by the external DVS pin. FAULT DETECTION If BUCK1/BUCK2 and LDO1 are not masked then if one of the outputs is pulled down - e.g., short circuit, then RESET_N is asserted (low).. Table 2. Default Start-Up Enable Sequence (1) (1) Part No. DEFSEL Start-Up Sequence Shut Down Sequence LP8725 VIN1 (setup 1) BUCK1 then BUCK2 and LILO2 then LDO1, LDO2, LDO4 and LDO5 then LDO3 and LILO1 In reverse order of start-up sequence. LP8725 GND (setup 2) BUCK1 and LILO2 then BUCK2, LDO1, LDO2, LDO5 and LILO1 then LDO3 and LDO4. In reverse order of start-up sequence. LP8725-A VIN1 (setup 1) LDO1, LDO2, LDO5 and LILO1 then LDO4 and LILO2 In reverse order of start-up sequence. LP8725-A GND (setup 2) BUCK1 and BUCK2 then LDO2 and LDO3 then LDO1, LDO4 and LDO5 then LILO1 and LILO2 In reverse order of start-up sequence. LP8725-B VIN1 or GND BUCK1 then BUCK2 then LDO1 then LILO2 In reverse order of start-up sequence. LP8725-C VIN1 or GND BUCK1 then BUCK2 and LDO5 then LDO1 and LDO2 and LILO 1and LILO 2 then LDO3 and LDO4 In reverse order of start-up sequence. LP8725-D VIN1 or GND BUCK1 then BUCK2, LDO3, LILO1 and LILO2 In reverse order of start-up sequence. These are dependent on whether DEFSEL is connected to VIN1 or GND when PWR_ON/EN=1. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LP8725 7 LP8725 SNVS618G – DECEMBER 2009 – REVISED MAY 2013 www.ti.com Power On and Power Off Sequences EN EN BUCK (note 1) BUCK (note 1) DVS Control LDO (note 1) LDO (note 1) 30 ms RESET_N RESET_N Figure 3. Simplified startup Sequence if CONFIG=GND (SUB_PMU) PWR_ON PWR_ON 30 ms BUCK (note 1) BUCK (note 1) DVS Control LDO (note 1) LDO (note 1) 30 ms RESET_N RESET_N PS_HOLD PS_HOLD 30 ms (note 2) All timing is typical. Note 1 See detailed on/off sequence diagrams for the different DEFSEL options. Note 2 PS_HOLD needs to be held low for >30 ms before RESET_N is asserted low. PMU should then start shutdown sequence opposite of startup sequence. Figure 4. Simplified Startup Sequence if CONFIG=VIN1 (PMU) 8 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LP8725 LP8725 www.ti.com SNVS618G – DECEMBER 2009 – REVISED MAY 2013 Figure 5. LP8725 Startup and Shutdown Sequence if CONFIG=VIN1 Note 1, Note 2 SHUT DOWN sequence is in reverse order of START UP sequence Timing Code START UP sequence Timing Code 6 5 4 3 2 1 0 0 1 2 3 4 5 6 PWR_ON PWR_ON PS_HOLD PS_HOLD Buck 1 Buck 1 Buck 2 Buck 2 LDO1 LDO1 LDO2 LDO2 LDO3 LDO3 LDO4 LDO4 LDO5 LDO5 LILO 1 LILO 1 LILO 2 LILO 2 tON tS tS tS tS tS tOFF tS tS tS tS tS tS tS Note 4 START UP IDLE SHUT DOWN All timing is typical. tON/OFF 30 ms typ. de-bounce times tS Programmable time steps. (Typically 64 µs/step.) Time step accuracy is defined by OSC frequency accuracy. Note 1 STARTUP and SHUTDOWN sequences are defined by registers. Sequences given here are valid if there the registers are not rewritten via Serial Interface. Note 2 The timing showed here define time points when LDOs and BUCK are enabled/disabled. Enabling /disabling process duration depends on voltages and loading conditions. Buck startup duration is typically 170 µs. LDO startup duration is typically 35 µs. For details please see LDOs and BUCK Electrical Specifications. Note 4 At this time point registers are reset to POR default values. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LP8725 9 LP8725 SNVS618G – DECEMBER 2009 – REVISED MAY 2013 www.ti.com Figure 6. LP8725 Startup and Shutdown Sequence if CONFIG=GND, DEFSEL=GND Note 1, Note 2 START UP sequence SHUT DOWN sequence is in reverse order of START UP sequence Timing Code Timing Code 6 5 4 3 2 1 0 0 1 2 3 4 5 6 EN EN Buck 1 Buck 1 Buck 2 Buck 2 LDO1 LDO1 LDO2 LDO2 LDO3 LDO3 LDO4 LDO4 LDO5 LDO5 LILO 1 LILO 1 LILO 2 LILO 2 tBON tS tS tS tS tS tS tS tS tS tS tS tS Note 4 STANDBY START UP IDLE SHUT DOWN STANDBY All timing is typical. tBON 75 µs - Reference and bias turn ON. ts Programmable time steps. (Typically 64 µs/step.) Time step accuracy is defined by OSC frequency accuracy. Note 1 STARTUP and SHUTDOWN sequences are defined by registers. Sequences given here are valid if there the registers are not rewritten via Serial Interface. Note 2 The timing showed here define time points when LDOs and BUCK are enabled/disabled. Enabling /disabling process duration depends on voltages and loading conditions. Buck startup duration is typically 170 µs. LDO startup duration is typically 35 µs. For details please see LDOs and BUCK Electrical Specifications. Note 4 At this time point registers are reset to POR default values. 10 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LP8725 LP8725 www.ti.com SNVS618G – DECEMBER 2009 – REVISED MAY 2013 Figure 7. LP8725-A Startup and Shutdown Sequence if CONFIG=GND, DEFSEL=VIN1 Note 1, Note 2 SHUT DOWN sequence is in reverse order of START UP sequence Timing Code START UP sequence Timing Code 6 5 4 3 2 1 0 0 1 2 3 4 5 6 EN EN Note 3 Buck 1 Buck 1 Note 5 Buck 2 Buck 2 LDO1 LDO1 LDO2 LDO2 Note 5 LDO3 LDO3 LDO4 LDO4 LDO5 LDO5 LILO 1 LILO 1 LILO 2 LILO 2 tBON tS tS tS tS tS tS tS tS tS tS tS tS Note 4 STANDBY START UP IDLE SHUT DOWN STANDBY All timing is typical. tBON 75 µs - Reference and bias turn ON. tS Programmable time steps. (Typically 64 µs/step.) Time step accuracy is defined by OSC frequency accuracy. Note 1 STARTUP and SHUTDOWN sequences are defined by registers. Sequences given here are valid if there the registers are not rewritten via Serial Interface. Note 2 The timing showed here define time points when LDOs and BUCK are enabled/disabled. Enabling /disabling process duration depends on voltages and loading conditions. Buck startup duration is typically 170 µs. LDO startup duration is typically 35 µs. For details please see LDOs and BUCK Electrical Specifications. Note 3 BUCK1 is disabled. If it is enabled via Serial Interface and the startup sequence is not changed, then it will be disabled, with no delay, from falling edge of EN-pin. Note 4 At this time point registers are reset to POR default values. Note 5 BUCK2 and LDO3 are enabled by B2_EN and LDO3_EN respectively (or via serial interface). If these inputs are high when EN goes high then these outputs turn on after ts= 6. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LP8725 11 LP8725 SNVS618G – DECEMBER 2009 – REVISED MAY 2013 www.ti.com Figure 8. LP8725-A Startup and Shutdown Sequence if CONFIG=GND, DEFSEL=GND Note 1, Note 2 SHUT DOWN sequence is in reverse order of START UP sequence Timing Code START UP sequence Timing Code 6 5 4 3 2 1 0 0 1 2 3 4 5 6 EN EN Buck 1 Buck 1 Buck 2 Buck 2 LDO1 LDO1 LDO2 LDO2 LDO3 LDO3 LDO4 LDO4 LDO5 LDO5 LILO 1 LILO 1 LILO 2 LILO 2 tBON tS tS tS tS tS tS tS tS tS tS tS tS Note 4 STANDBY START UP IDLE SHUT DOWN STANDBY All timing is typical. tBON 75 µs - Reference and bias turn ON. tS Programmable time steps. (Typically 64 µs/step.) Time step accuracy is defined by OSC frequency accuracy. Note 1 STARTUP and SHUTDOWN sequences are defined by registers. Sequences given here are valid if there the registers are not rewritten via Serial Interface. Note 2 The timing showed here define time points when LDOs and BUCK are enabled/disabled. Enabling /disabling process duration depends on voltages and loading conditions. Buck startup duration is typically 170 µs. LDO startup duration is typically 35 µs. For details please see LDOs and BUCK Electrical Specifications. Note 4 At this time point registers are reset to POR default values. 12 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LP8725 LP8725 www.ti.com SNVS618G – DECEMBER 2009 – REVISED MAY 2013 Figure 9. LP8725-B Startup and Shutdown Sequence if CONFIG=VIN1, DEFSEL=VIN1 or DEFSEL=GND Note 1, Note 2 SHUT DOWN sequence is in reverse order of START UP sequence Timing Code START UP sequence Timing Code 6 5 4 3 2 1 0 0 1 2 3 4 5 6 PWR_ON PWR_ON PS_HOLD PS_HOLD Buck 1 Buck 1 Buck 2 Buck 2 LDO1 LDO1 Note 3 LDO2 LDO2 Note 5 LDO3 LDO3 Note 3 LDO4 LDO4 Note 3 LDO5 LDO5 Note 3 LILO 1 LILO 1 LILO 2 LILO 2 tON tS tS tS tS tS tOFF tS tS tS tS tS tS tS Note 4 START UP IDLE SHUT DOWN All timing is typical. tON/OFF 30 ms typ. de-bounce times. tS Programmable time steps. (Typically 64 µs/step.) Time step accuracy is defined by OSC frequency accuracy. Note 1 STARTUP and SHUTDOWN sequences are defined by registers. Sequences given here are valid if there the registers are not rewritten via Serial Interface. Note 2 The timing showed here define time points when LDOs and BUCK are enabled/disabled. Enabling /disabling process duration depends on voltages and loading conditions. Buck startup duration is typically 170 µs. LDO startup duration is typically 35 µs. For details please see LDOs and BUCK Electrical Specifications. Note 3 LDO2, 4, 5 and LILO1 are disabled. If they are enabled via Serial Interface and the startup sequence is not changed, then they will be disabled, with no delay, from falling edge of EN-pin. Note 4 At this time point registers are reset to POR default values. Note 5 LDO3 is enabled by LDO3_EN (or via serial interface). If this input is high when PWR_ON goes high then this output turns on after ts= 6. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LP8725 13 LP8725 SNVS618G – DECEMBER 2009 – REVISED MAY 2013 www.ti.com Figure 10. LP8725-B Startup and Shutdown Sequence if CONFIG=GND, DEFSEL=VIN1 or DEFSEL=GND Note 1, Note 2 SHUT DOWN sequence is in reverse order of START UP sequence Timing Code START UP sequence Timing Code 6 5 4 3 2 1 0 0 1 2 3 4 5 6 EN EN Buck 1 Buck 1 Buck 2 Buck 2 LDO1 LDO1 Note 3 LDO2 LDO2 Note 5 LDO3 LDO3 Note 3 LDO4 LDO4 Note 3 LDO5 LDO5 Note 3 LILO 1 LILO 1 LILO 2 LILO 2 tBON tS tS tS tS tS tS tS tS tS tS tS tS Note 4 STANDBY START UP IDLE SHUT DOWN STANDBY All timing is typical. tBON 75 µs - Reference and bias turn ON. tS Programmable time steps. (Typically 64 µs/step.) Time step accuracy is defined by OSC frequency accuracy. Note 1 STARTUP and SHUT DOWN sequences are defined by registers. Sequences given here are valid if there the registers are not rewritten via Serial Interface. Note 2 The timing showed here define time points when LDOs and BUCK are enabled/disabled. Enabling /disabling process duration depends on voltages and loading conditions. Buck startup duration is typically 170 µs. LDO startup duration is typically 35 µs. For details please see LDOs and BUCK Electrical Specifications. Note 3 LDO2, 4, 5 and LILO1 are disabled. If they are enabled via Serial Interface and the startup sequence is not changed, then they will be disabled, with no delay, from falling edge of EN-pin. Note 4 At this time point registers are reset to POR default values. Note 5 LDO3 is enabled by LDO3_EN (or via serial interface). If this input is high when PWR_ON goes high then this output turns on after ts= 6. 14 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LP8725 LP8725 www.ti.com SNVS618G – DECEMBER 2009 – REVISED MAY 2013 Figure 11. LP8725-C Startup and Shutdown Sequence if CONFIG=VIN1, DEFSEL=VIN1 or DEFSEL=GND Note 1, Note 2 SHUT DOWN sequence is in reverse order of START UP sequence Timing Code START UP sequence Timing Code 0 1 2 3 4 5 6 5 4 3 2 1 0 6 PWR_ON PWR_ON PS_HOLD PS_HOLD Buck 1 Buck 1 Buck 2 Buck 2 LDO1 LDO1 LDO2 LDO2 LDO3 LDO3 LDO4 LDO4 LDO5 LDO5 LILO 1 LILO 1 LILO 2 LILO 2 tON tS tS tS tS tS tOFF tS tS tS tS tS tS tS Note 4 START UP IDLE SHUT DOWN All timing is typical. tON/OFF 30 ms typ. de-bounce times. tS Programmable time steps. (Typically 64 µs/step.) Time step accuracy is defined by OSC frequency accuracy. Note 1 STARTUP and SHUTDOWN sequences are defined by registers. Sequences given here are valid if there the registers are not rewritten via Serial Interface. Note 2 The timing showed here define time points when LDOs and BUCK are enabled/disabled. Enabling /disabling process duration depends on voltages and loading conditions. Buck startup duration is typically 170 µs. LDO startup duration is typically 35 µs. For details please see LDOs and BUCK Electrical Specifications. Note 4 At this time point registers are reset to POR default values. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LP8725 15 LP8725 SNVS618G – DECEMBER 2009 – REVISED MAY 2013 www.ti.com Figure 12. LP8725-D Startup and Shutdown Sequence if CONFIG=VIN1, DEFSEL=VIN1 or DEFSEL=GND Note 1, Note 2 SHUT DOWN sequence is in reverse order of START UP sequence Timing Code START UP sequence Timing Code 6 5 4 3 2 1 0 0 1 2 3 4 5 6 PWR_ON PWR_ON PS_HOLD PS_HOLD Buck 1 Buck 1 Buck 2 Buck 2 Note 3 LDO1 LDO1 Note 3 LDO2 LDO2 LDO3 LDO3 Note 3 LDO4 LDO4 Note 3 LDO5 LDO5 LILO 1 LILO 1 LILO 2 LILO 2 tON tS tS tS tS tS tOFF tS tS tS tS tS tS tS Note 4 START UP IDLE SHUT DOWN All timing is typical. tON/OFF 30 ms typ. de-bounce times. tS Programmable time steps. (Typically 64 µs/step.) Time step accuracy is defined by OSC frequency accuracy. Note 1 STARTUP and SHUTDOWN sequences are defined by registers. Sequences given here are valid if there the registers are not rewritten via Serial Interface. Note 2 The timing showed here define time points when LDOs and BUCK are enabled/disabled. Enabling /disabling process duration depends on voltages and loading conditions. Buck startup duration is typically 170 µs. LDO startup duration is typically 35 µs. For details please see LDOs and BUCK Electrical Specifications. Note 3 LDO1, 2, 4, 5 are disabled. If they are enabled via Serial Interface and the startup sequence is not changed, then they will be disabled, with no delay, from falling edge of EN-pin. Note 4 At this time point registers are reset to POR default values. Note 5 LDO3 is enabled by LDO3_EN (or via serial interface). If this input is high when PWR_ON goes high then this output turns on after ts= 6. 16 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LP8725 LP8725 www.ti.com SNVS618G – DECEMBER 2009 – REVISED MAY 2013 Table 3. Default Output Voltages (1) (2) Output (1) (2) Max Current (mA) Voltage Range (V) Default output Voltage [V] and default ON/OFF (PWR_ON/EN=1) DEFSEL = VIN1 DEFSEL = GND BUCK1 800 0.8 to 3.0 1.0*/1.2** ON 1.2*/1.0** ON BUCK2 600 0.8 to 3.0 1.8*/1.8** ON 1.8*/1.8** ON LDO1 300 1.2 to 3.3 2.8 ON 2.6 ON LDO2 300 1.2 to 3.3 1.8 ON 2.8 ON LDO3 300 1.2 to 3.3 3.3 ON 2.8 ON LDO4 300 1.2 to 3.3 3.3 ON 2.8 ON LDO5 300 1.2 to 3.3 2.8 ON 2.8 ON LILO1 300 0.8 to 3.3 1.2 ON 3.3 ON LILO2 300 0.8 to 3.3 1.2 ON 1.2 ON These are dependent on whether DEFSEL is connected to VIN1 or GND when PWR_ON/EN=1. BUCK1 voltages are set to *BUCK1_V1 and **BUCK1_V2 as selected by DVS1_V and the DVS pin. BUCK2 voltages are set to *BUCK2_V1 and **BUCK2_V2 as selected by DVS2_V. Table 4. LP8725-A Alternative Part's Default Output Voltages (1) (2) (1) (2) Output Max Current (mA) Voltage Range (V) Default output Voltage [V] and default ON/OFF (PWR_ON/EN=1) DEFSEL = VIN1 DEFSEL = GND BUCK1 800 0.8 to 3.0 1.1*/1.0** OFF 1.3*/1.2** ON BUCK2 600 0.8 to 3.0 1.1*/1.0** OFF*** 1.3*/1.2** ON LDO1 300 1.2 to 3.3 2.6 ON 2.8 ON LDO2 300 1.2 to 3.3 3.0 ON 2.8 ON LDO3 300 1.2 to 3.3 3.3 OFF**** 2.8 ON LDO4 300 1.2 to 3.3 3.0 ON 2.8 ON LDO5 300 1.2 to 3.3 2.8 ON 2.8 ON LILO1 300 0.8 to 3.3 1.8 ON 1.8 ON LILO2 300 0.8 to 3.3 1.0 ON 1.8 ON These are dependent on whether DEFSEL is connected to VIN1 or GND when PWR_ON/EN=1. BUCK1 voltages are set to *BUCK1_V1 and **BUCK1_V2 as selected by DVS1_V and the DVS pin. BUCK2 voltages are set to *BUCK2_V1 and **BUCK2_V2 as selected by DVS2_V. *** Only if pin B2_EN=0 if in SUB_PMU configuration **** Only if pin LDO3_EN=0 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LP8725 17 LP8725 SNVS618G – DECEMBER 2009 – REVISED MAY 2013 www.ti.com Table 5. LP8725-B Alternative Part's Default Output Voltages (1) (2) Output (1) (2) Max Current (mA) Voltage Range (V) Default output Voltage [V] and default ON/OFF (PWR_ON/EN=1) DEFSEL = VIN1 DEFSEL = GND BUCK1 800 0.8 to 3.0 1.2*/1.2** ON 1.2*/1.2** ON BUCK2 600 0.8 to 3.0 1.8*/1.8** ON 1.8*/1.8** ON LDO1 300 1.2 to 3.3 2.6 ON 1.8 ON LDO2 300 1.2 to 3.3 2.8 OFF 2.8 OFF LDO3 300 1.2 to 3.3 2.8 OFF*** 2.8 OFF*** LDO4 300 1.2 to 3.3 1.2 OFF 1.2 OFF LDO5 300 1.2 to 3.3 1.2 OFF 1.2 OFF LILO1 300 0.8 to 3.3 2.5 OFF 2.5 OFF LILO2 300 0.8 to 3.3 3.3 ON 3.3 ON These are dependent on whether DEFSEL is connected to VIN1 or GND when PWR_ON/EN=1. BUCK1 voltages are set to *BUCK1_V1 and **BUCK1_V2 as selected by DVS1_V and the DVS pin. BUCK2 voltages are set to *BUCK2_V1 and **BUCK2_V2 as selected by DVS2_V. *** Only if pin LDO3_EN=0 Table 6. LP8725-C Alternative Part's Default Output Voltages (1) 18 (1) Output Max Current (mA) Voltage Range (V) Default output Voltage [V] and default ON/OFF (PWR_ON/EN=1) DEFSEL = VIN1 DEFSEL = GND BUCK1 800 0.8 to 3.0 1.2 ON 1.2 ON BUCK2 600 0.8 to 3.0 1.8 ON 1.8 ON LDO1 300 1.2 to 3.3 2.6 ON 2.6 ON LDO2 300 1.2 to 3.3 2.8 ON 2.8 ON LDO3 300 1.2 to 3.3 2.8 ON 2.8 ON LDO4 300 1.2 to 3.3 2.5 ON 2.5 ON LDO5 300 1.2 to 3.3 3.3 ON 3.3 ON LILO1 300 0.8 to 3.3 1.2 ON 1.2 ON LILO2 300 0.8 to 3.3 1.2 ON 1.2 ON These are dependent on whether DEFSEL is connected to VIN1 or GND when PWR_ON/EN=1. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LP8725 LP8725 www.ti.com SNVS618G – DECEMBER 2009 – REVISED MAY 2013 Table 7. LP8725-D Alternative Part's Default Output Voltages (1) (2) Output (1) (2) Max Current (mA) Voltage Range (V) Default output Voltage [V] and default ON/OFF (PWR_ON/EN=1) DEFSEL = VIN1 DEFSEL = GND BUCK1 800 0.8 to 3.0 1.3*/1.3** ON 1.3*/1.3** ON BUCK2 800 0.8 to 3.0 1.8*/1.8** ON 1.8*/1.8** ON LDO1 300 1.2 to 3.3 2.8 OFF 2.8 OFF LDO2 300 1.2 to 3.3 1.8 OFF 1.8 OFF LDO3 300 1.2 to 3.3 1.8 ON 1.8 ON LDO4 300 1.2 to 3.3 3.0 OFF 3.0 OFF LDO5 300 1.2 to 3.3 1.8 OFF 1.2 OFF LILO1 300 0.8 to 3.3 3.0 ON 3.0 ON LILO2 300 0.8 to 3.3 3.0 ON 3.0 ON These are dependent on whether DEFSEL is connected to VIN1 or GND when PWR_ON/EN=1. BUCK1 voltages are set to *BUCK1_V1 and **BUCK1_V2 as selected by DVS1_V and the DVS pin. BUCK2 voltages are set to *BUCK2_V1 and **BUCK2_V2 as selected by DVS2_V. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LP8725 19 LP8725 SNVS618G – DECEMBER 2009 – REVISED MAY 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) VIN1 -0.3V to +6V VIN2, VIN3, VINLILO1, VINLILO2, VINB1, VINB2 -0.3V to VIN1+0.3V and