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LP87524B-Q1
LP87524J-Q1, LP87524P-Q1
SNVSAW2B – APRIL 2017 – REVISED DECEMBER 2018
LP87524B/J/P-Q1 Four 4-MHz Buck Converters for AWR and IWR MMICs
1 Features
3 Description
•
•
The LP87524B/J/P-Q1 is designed to meet the power
management requirements of the latest processors
and platforms in various automotive power
applications. The device contains four step-down DCDC converter cores, which are configured as 4 single
phase outputs. The device is controlled by an I2Ccompatible serial interface and by enable signals.
1
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Input Voltage: 2.8 V to 5.5 V
Output Voltage: 0.6 V to 3.36 V
Four High-Efficiency Step-Down DC-DC Converter
Cores:
– Total Output Current Up To 10 A
– Output Voltage Slew-Rate 3.8 mV/µs
4-MHz Switching Frequency
Spread-Spectrum Mode and Phase Interleaving
Configurable General Purpose I/O (GPIOs)
I2C-Compatible Interface which Supports Standard
(100 kHz), Fast (400 kHz), Fast+ (1 MHz), and
High-Speed (3.4 MHz) Modes
Interrupt Function with Programmable Masking
Programmable Power Good Signal (PGOOD)
Output Short-Circuit and Overload Protection
Overtemperature Warning and Protection
Overvoltage Protection (OVP) and Undervoltage
Lockout (UVLO)
The automatic PFM/PWM (AUTO mode) operation
maximizes efficiency over a wide output-current
range. The LP87524B/J/P-Q1 supports remote
voltage sensing to compensate IR drop between the
regulator output and the point-of-load (POL) thus
improving the accuracy of the output voltage. In
addition the switching clock can be forced to PWM
mode and also synchronized to an external clock to
minimize the disturbances.
The LP87524B/J/P-Q1 device supports load-current
measurement without the addition of external currentsense resistors. In addition, the LP87524B/J/P-Q1
supports programmable start-up and shutdown
delays and sequences synchronized to enable
signals. The sequences can also include GPIO
signals to control external regulators, load switches
and processor reset. During start-up and voltage
change, the device controls the output slew rate to
minimize output voltage overshoot and the in-rush
current.
2 Applications
•
•
•
•
Device Information(1)
Automotive Infotainment
Cluster
Radar
Camera Power
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LP87524B-Q1
LP87524J-Q1
VQFN-HR (26)
4.50 mm × 4.00 mm
LP87524P-Q1
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VOUT1
SW_B0
VIN
VIN_B0
Efficiency vs Output Current
LOAD
FB_B0
100
VIN_B1
VIN_B2
VANA
VOUT2
SW_B1
NRST
SDA
SCL
nINT
90
LOAD
FB_B1
VOUT3
SW_B2
LOAD
FB_B2
Efficiency (%)
VIN_B3
80
70
CLKIN
60
EN1 (GPIO1)
EN2 (GPIO2)
EN3 (GPIO3)
1PH, VOUT = 1V, AUTO
1PH, VOUT = 1.8V, AUTO
1PH, VOUT = 2.5V, AUTO
VOUT4
SW_B3
LOAD
FB_B3
PGOOD
GNDs
50
0.001
0.01
0.1
Output Current (A)
1
5
D922
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP87524B-Q1
LP87524J-Q1, LP87524P-Q1
SNVSAW2B – APRIL 2017 – REVISED DECEMBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings ............................................................ 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics........................................... 6
I2C Serial Bus Timing Requirements...................... 11
Typical Characteristics ............................................ 13
Detailed Description ............................................ 14
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Descriptions ...............................................
Device Functional Modes........................................
14
15
15
30
7.5 Programming........................................................... 32
7.6 Register Maps ......................................................... 35
8
Application and Implementation ........................ 61
8.1 Application Information............................................ 61
8.2 Typical Application .................................................. 61
9 Power Supply Recommendations...................... 68
10 Layout................................................................... 69
10.1 Layout Guidelines ................................................. 69
10.2 Layout Example .................................................... 70
11 Device and Documentation Support ................. 71
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
71
71
71
71
71
71
71
12 Mechanical, Packaging, and Orderable
Information ........................................................... 71
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (December 2017) to Revision B
•
Page
Added LP87524P-Q1 GPN to SNVSAW2 data sheet ........................................................................................................... 1
Changes from Original (April 2017) to Revision A
•
2
Page
Added LP87524J-Q1 GPN to SNVSAW2 data sheet ........................................................................................................... 1
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Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: LP87524B-Q1 LP87524J-Q1 LP87524P-Q1
LP87524B-Q1
LP87524J-Q1, LP87524P-Q1
www.ti.com
SNVSAW2B – APRIL 2017 – REVISED DECEMBER 2018
5 Pin Configuration and Functions
RNF Package
26-Pin VQFN With Thermal Pad
Top View
VIN_B3
3
22
SW_B3
EN3
23
PGND_B23
2
24
SW_B2
FB_B2
25
VIN_B2
1
26
FB_B3
21
NRST
20
CLKIN
nINT
19
4
AGND
VANA
18
5
SCL
AGND
17
6
SDA
PGOOD
16
7
EN1
EN2
15
8
FB_B0
FB_B1
14
AGND
VIN_B0
SW_B0
PGND_B01
SW_B1
VIN_B1
Copyright © 2017–2018, Texas Instruments Incorporated
9
10
11
12
13
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3
LP87524B-Q1
LP87524J-Q1, LP87524P-Q1
SNVSAW2B – APRIL 2017 – REVISED DECEMBER 2018
www.ti.com
Pin Functions
PIN
TYPE
DESCRIPTION
NUMBER
NAME
1
FB_B2
A
2
EN3
D/I/O
3
CLKIN
D/I
External clock input. Connect to ground if external clock is not used.
4, 17,
Thermal Pad
AGND
G
Ground
Serial interface clock input for I2C access. Connect a pullup resistor.
Output voltage feedback (positive) for Buck2.
Programmable enable signal for buck regulators (can be also configured to select between two
buck output voltage levels). Alternative function is GPIO3.
5
SCL
D/I
6
SDA
D/I/O
Serial interface data input and output for I2C access. Connect a pullup resistor.
7
EN1
D/I/O
Programmable Enable signal for buck regulators (can be also configured to select between two
buck output voltage levels). Alternative function is GPIO1.
8
FB_B0
A
Output voltage feedback (positive) for Buck0
9
VIN_B0
P
Input for Buck0. The separate power pins VIN_Bx are not connected together internally - VIN_Bx
pins must be connected together in the application and be locally bypassed.
10
SW_B0
A
Buck0 switch node
11
PGND_B01
G
Power ground for Buck0 and Buck1
12
SW_B1
A
Buck1 switch node
13
VIN_B1
P
Input for Buck1. The separate power pins VIN_Bx are not connected together internally – VIN_Bx
pins must be connected together in the application and be locally bypassed.
14
FB_B1
A
Output voltage feedback (positive) for Buck1.
15
EN2
D/I/O
Programmable enable signal for Buck regulators (can be also configured to select between two
buck output voltage levels). Alternative function is GPIO2.
16
PGOOD
D/O
Power Good indication signal
18
VANA
P
19
nINT
D/O
Open-drain interrupt output, active LOW
20
NRST
D/I
Reset signal for the device.
21
FB_B3
A
Output voltage feedback (positive) for Buck3.
22
VIN_B3
P
Input for Buck3. The separate power pins VIN_Bx are not connected together internally – VIN_Bx
pins must be connected together in the application and be locally bypassed.
Supply voltage for analog and digital blocks. Must be connected to same node as with VIN_Bx.
23
SW_B3
A
Buck3 switch node
24
PGND_B23
G
Power Ground for Buck2 and Buck3
25
SW_B2
A
Buck2 switch node
26
VIN_B2
P
Input for Buck2. The separate power pins VIN_Bx are not connected together internally – VIN_Bx
pins must be connected together in the application and be locally bypassed.
A: Analog Pin, D: Digital Pin, G: Ground Pin, P: Power Pin, I: Input Pin, O: Output Pin
4
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LP87524J-Q1, LP87524P-Q1
www.ti.com
SNVSAW2B – APRIL 2017 – REVISED DECEMBER 2018
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
(2)
MIN
MAX
UNIT
Voltage on power connections
VIN_Bx, VANA
–0.3
6
V
Voltage on buck switch nodes
SW_Bx
–0.3
(VIN_Bx + 0.3 V) with 6 V
maximum
V
Voltage on buck voltage sense nodes
FB_Bx
–0.3
(VANA + 0.3 V) with 6 V
maximum
V
Voltage on NRST input
NRST
–0.3
6
V
Voltage on logic pins
(input or output pins)
SDA, SCL, nINT, CLKIN
–0.3
6
V
Voltage on logic pins
(input or output pins)
EN1 (GPIO1), EN2 (GPIO2), EN3
(GPIO3), PGOOD
–0.3
(VANA + 0.3 V) with 6 V
maximum
V
Junction temperature, TJ-MAX
−40
150
°C
Storage temperature, Tstg
–65
150
°C
260
°C
Maximum lead temperature (soldering, 10 sec.)
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic
discharge
Charged-device model (CDM), per AEC Q100-011
UNIT
±2000
All pins
±500
Corner pins (1, 8, 14 and 21)
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
INPUT VOLTAGE
Voltage on power connections
VIN_Bx, VANA
2.8
5.5
V
Voltage on NRST
NRST
1.65
VANA with 5.5 V
maximum
V
Voltage on logic pins
nINT, CLKIN
1.65
5.5
V
Voltage on logic pins
(input or output pins)
ENx, PGOOD
0
VANA with 5.5 V
maximum
V
1.65
1.95
V
3.1
VANA with 3.6 V
maximum
V
Junction temperature, TJ
−40
140
°C
Ambient temperature, TA
−40
125
°C
Voltage on I2C interface, standard (100
kHz), fast (400 khz), fast+ (1 MHz), and
high-speed (3.4 MHz) modes
Voltage on I2C interface, standard (100
kHz), fast (400 kHz), and fast+ (1 MHz)
modes
SCL, SDA
TEMPERATURE
Copyright © 2017–2018, Texas Instruments Incorporated
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SNVSAW2B – APRIL 2017 – REVISED DECEMBER 2018
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6.4 Thermal Information
LP875xx-Q1
THERMAL METRIC (1)
RNF (VQFN)
UNIT
26 PINS
RθJA
Junction-to-ambient thermal resistance
34.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
16.5
°C/W
RθJB
Junction-to-board thermal resistance
4.7
°C/W
ψJT
Junction-to-top characterization parameter
0.6
°C/W
ψJB
Junction-to-board characterization parameter
4.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.4
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, CPOL = 22 µF / phase, specified VVANA, VVIN_Bx , VNRST,
VVOUT_Bx and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = 3.7 V, and VOUT = 1 V,
unless otherwise noted. (1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
EXTERNAL COMPONENTS
CIN
Input filtering
capacitance
Connected from VIN_Bx to PGND_Bx
1.9
10
µF
COUT
Output filtering
Capacitance, local
Capacitance per phase
10
22
µF
CPOL
Point-of-Load (POL)
capacitance
Optional POL capacitance per phase
22
µF
COUT-
Output capacitance,
total (local and POL)
Total output capacitance, 1-phase output
ESRC
Input and output
capacitor ESR
[1-10] MHz
L
Inductor
Inductance of the inductor
DCRL
Inductor DCR
TOTAL
2
100
µF
10
mΩ
0.47
–30%
µH
30%
25
mΩ
BUCK REGULATOR
VVIN_Bx
Input voltage range
VVOUT_Bx
Output voltage
2.8
3.36
Programmable voltage range, 2.8 V ≤
VVIN_Bx ≤ 5.5 V
1.0
3.36
10
Step size, 0.73 V ≤ VOUT < 1.4 V
5
Step size, 1.4 V ≤ VOUT ≤ 3.36 V
20
Buck2: VIN ≥ 3 V
4 (3)
Buck2: 2.8 V ≤ VIN < 3 V
3 (3)
(1)
(2)
(3)
6
A
2.5 (3)
3 (3)
Buck0, Buck2
IOUT
mV
1.5 (3)
Buck3
Output current,
LP87524P
V
V
Buck0, Buck1
Output current,
LP87524B/J
5.5
0.6
Step size, 0.6 V ≤ VOUT < 0.73 V
IOUT
3.7
Programmable voltage range, 2.8 V ≤
VVIN_Bx ≤ 4 V
Buck1
1.5 (3)
Buck3
2.5 (3)
A
All voltage values are with respect to network ground.
Minimum (Min) and Maximum (Max) limits are specified by design, test, or statistical analysis. Typical (Typ) numbers are not verified, but
do represent the most likely norm.
The maximum output current can be limited by the forward current limit ILIM FWD and by the junction temperature. The power dissipation
inside the die depends on the length of the current pulse and efficiency and the junction temperature may increase to thermal shutdown
level if the board and ambient temperatures are high.
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SNVSAW2B – APRIL 2017 – REVISED DECEMBER 2018
Electrical Characteristics (continued)
Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, CPOL = 22 µF / phase, specified VVANA, VVIN_Bx , VNRST,
VVOUT_Bx and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = 3.7 V, and VOUT = 1 V,
unless otherwise noted.(1) (2)
PARAMETER
VVOUT_DC
TEST CONDITIONS
VOUT < 1 V, PWM mode
–20
20
VOUT ≥ 1 V, PWM mode
–2%
2%
VOUT < 1 V, PFM mode
–20
40
VOUT ≥ 1 V, PFM mode
–2%
2% + 20 mV
0.1
DCLDR
VOUT = 1 V, IOUT from 0 to IOUT(max)
ILIM
ILIM
FWD
FWD
NEG
RDS(ON) HS
FET
RDS(ON) LS
FET
fSW
Transient line response
Forward current limit
(peak for every
switching cycle),
LP87524B/J
Forward current limit
(peak for every
switching cycle),
LP87524P
IOUT = 0 A to 2 A, TR = TF = 10 µs, PWM
mode, COUT = 22 µF, L = 0.47 µH, CPOL =
22 µF
Start-up time (soft start)
mV
mVp-p
%/V
3%
mV
±40
VVIN_Bx stepping 3 V ↔ 3.5 V, TR = TF = 10
µs, IOUT = IOUT(max)
±5
mV
Buck0, Buck1: VVIN_Bx ≥ 3 V
2.3
2.7
3.0
Buck0, Buck1: 2.8 V ≤ VVIN_Bx < 3 V
2.0
2.7
3.0
Buck2: VVIN_Bx ≥ 3 V
4.7
5.4
6.0
Buck2: 2.8 V ≤ VVIN_Bx < 3 V
4.0
5.4
6.0
Buck3: VVIN_Bx ≥ 3 V
4.2
4.8
5.4
Buck3: 2.8 V ≤ VVIN_Bx < 3 V
3.6
4.8
5.4
Buck0, Buck2: VVIN_Bx ≥ 3 V
3.8
4.3
4.8
Buck0, Buck2: 2.8 V ≤ VVIN_Bx < 3 V
3.2
4.3
4.8
Buck1: VVIN_Bx ≥ 3 V
2.3
2.7
3.0
Buck1: 2.8 V ≤ VVIN_Bx < 3 V
2.0
2.7
3.0
Buck3: VVIN_Bx ≥ 3 V
4.2
4.8
5.4
Buck3: 2.8 V ≤ VVIN_Bx < 3 V
3.6
4.8
5.4
1.6
2
2.4
A
29
65
mΩ
17
35
mΩ
Each phase, between VIN_Bx and SW_Bx
pins (I = 1 A)
VOUT > 0.8
3.6
4
4.4
0.6 < VOUT ≤ 0.8
2.7
3
3.3
VOUT = 0.6
1.8
2
2.2
From ENx to VOUT = 0.35 V (slew-rate
control begins), COUT_TOTAL = 44 µF / phase
Output voltage slewrate (4)
(4)
–3%
On-resistance, low-side Each phase, between SW_Bx and
FET
PGND_Bx pins (I = 1 A)
Switching frequency,
PWM mode
mV
0.8%
IOUT = 0.1 A to 2 A, TR = TF = 1 µs, PWM
mode, COUT = 22 µF, L = 0.47 µH, CPOL =
22 µF
Negative current limit /
phase (peak for every
switching cycle)
On-resistance, highside FET
4
14
IOUT = IOUT(max)
UNIT
V
PFM mode, L = 0.47 µH
DC load regulation in
PWM mode
Transient load step
response
0.5
PWM mode, ESRC < 2 mΩ, L = 0.47 µH
DC line regulation
ILIM
MAX
DC output voltage
accuracy, includes
voltage reference, DC
load and line
regulations, process
and temperature
DCLNR
TLNSR
TYP
Minimum voltage between VIN_x and
VOUT to fulfill the electrical characteristics
Ripple voltage
TLDSR
MIN
Input and output
voltage difference
200
3.23
3.8
A
A
MHz
µs
4.4
mV/µs
Output capacitance, forward and negative current limits and load current may limit the maximum and minimum slew rates.
Copyright © 2017–2018, Texas Instruments Incorporated
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Electrical Characteristics (continued)
Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, CPOL = 22 µF / phase, specified VVANA, VVIN_Bx , VNRST,
VVOUT_Bx and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = 3.7 V, and VOUT = 1 V,
unless otherwise noted.(1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IPFM-PWM
PFM-to-PWM - current
threshold (5)
600
mA
IPWM-PFM
PWM-to-PFM - current
threshold (5)
200
mA
Output pulldown
resistance
Output voltage
monitoring for PGOOD
pin
Powergood threshold
for interrupt
BUCKx_PG_INT,
difference from final
voltage
Powergood threshold
for status bit
BUCKx_PG_STAT
Regulator disabled
160
230
300
Overvoltage monitoring (compared to DC
output voltage level, VVOUT_DC)
39
50
64
Undervoltage monitoring (compared to DC
output voltage level, VVOUT_DC)
–53
–40
–29
mV
Debounce time during regulator enable
PGOOD_SET_DELAY = 0
4
Debounce time during regulator enable
PGOOD_SET_DELAY = 1
10
Deglitch time during operation and after
voltage change
4
Rising ramp voltage, enable or voltage
change
Ω
11
10
µs
13
ms
10
µs
–20
–14
–8
8
14
20
–20
–14
–8
mV
Falling ramp voltage, voltage change
During operation, status signal is forced to
'0' during voltage change
mV
EXTERNAL CLOCK AND PLL
Nominal frequency
External input clock
1
Nominal frequency step size
Required accuracy from nominal frequency
24
1
–30%
MHz
10%
External clock
detection
Delay for missing clock detection
1.8
Delay and debounce for clock detection
20
Clock change delay
(internal to external)
Delay from valid clock detection to use of
external clock
600
µs
PLL output clock jitter
Cycle to cycle
300
ps, p-p
µs
PROTECTION FUNCTIONS
Thermal warning
Temperature rising, TDIE_WARN_LEVEL =
0
115
125
135
Temperature rising, TDIE_WARN_LEVEL =
1
127
137
147
140
150
Hysteresis
Thermal shutdown
VANAOVP
VANA overvoltage
Temperature rising
VANAUVLO
VANA undervoltage
lockout
20
Hysteresis
160
20
Voltage rising
5.6
5.8
6.1
Voltage falling
5.45
5.73
5.96
Hysteresis
°C
40
°C
V
mV
Voltage rising
2.51
2.63
2.75
Voltage falling
2.5
2.6
2.7
V
LOAD CURRENT MEASUREMENT
(5)
8
The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependent on the output voltage, input voltage, and
the inductor current level.
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SNVSAW2B – APRIL 2017 – REVISED DECEMBER 2018
Electrical Characteristics (continued)
Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, CPOL = 22 µF / phase, specified VVANA, VVIN_Bx , VNRST,
VVOUT_Bx and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = 3.7 V, and VOUT = 1 V,
unless otherwise noted.(1) (2)
PARAMETER
TEST CONDITIONS
Current measurement
range
Output current for maximum code
Resolution
LSB
MIN
MAX
UNIT
20.47
A
20
Measurement accuracy IOUT > 1 A
Measurement time
TYP
mA
VANAUVLO
From any state except
SHUTDOWN
READ
OTP
REGISTER
RESET
I2C RESET
STANDBY
REGULATOR
ENABLED
REGULATORS
DISABLED
ACTIVE
Figure 15. Device Operation Modes
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7.5 Programming
7.5.1 I2C-Compatible Interface
The I2C-compatible synchronous serial interface provides access to the programmable functions and registers on
the device. This protocol uses a two-wire interface for bidirectional communications between the devices
connected to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL). Every
device on the bus is assigned a unique address and acts as either a master or a slave depending on whether it
generates or receives the serial clock SCL. The SCL and SDA lines must each have a pullup resistor placed
somewhere on the line and remain HIGH even when the bus is idle. Note: CLK pin is not used for serial bus data
transfer. The LP87524B/J/P-Q1 supports standard mode (100 kHz), fast mode (400 kHz), fast mode+ (1 MHz),
and high-speed mode (3.4 MHz).
7.5.1.1 Data Validity
The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the
state of the data line can only be changed when clock signal is LOW.
SCL
SDA
data
change
allowed
data
valid
data
change
allowed
data
change
allowed
data
valid
Figure 16. Data Validity Diagram
7.5.1.2 Start and Stop Conditions
The LP87524B/J/P-Q1 is controlled via an I2C-compatible interface. START and STOP conditions classify the
beginning and end of the I2C session. A START condition is defined as SDA transitions from HIGH to LOW while
SCL is HIGH. A STOP condition is defined as SDA transition from LOW to HIGH while SCL is HIGH. The I2C
master always generates the START and STOP conditions.
SDA
SCL
S
P
START
Condition
STOP
Condition
Figure 17. Start and Stop Sequences
The I2C bus is considered busy after a START condition and free after a STOP condition. During data
transmission the I2C master can generate repeated START conditions. A START and a repeated START
condition are equivalent function-wise. The data on SDA must be stable during the HIGH period of the clock
signal (SCL). In other words, the state of SDA can only be changed when SCL is LOW. Figure 18 shows the
SDA and SCL signal timing for the I2C-compatible bus. See the Figure 1 for timing values.
32
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SNVSAW2B – APRIL 2017 – REVISED DECEMBER 2018
Programming (continued)
tBUF
SDA
tHD;STA
trCL
tfDA
tLOW
trDA
tSP
tfCL
SCL
tHD;STA
tSU;STA
tSU;STO
tHIGH
tHD;DAT
S
tSU;DAT
START
RS
P
S
REPEATED
START
STOP
START
Figure 18. I2C-Compatible Timing
7.5.1.3 Transferring Data
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated
by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The
LP87524B/J/P-Q1 pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The
LP87524B/J/P-Q1 generates an acknowledge after each byte has been received.
There is one exception to the acknowledge after every byte rule. When the master is the receiver, it must
indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out
of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master),
but the SDA line is not pulled down.
NOTE
If the NRST signal is low during I2C communication the LP87524B/J/P-Q1 device does not
drive SDA line. The ACK signal and data transfer to the master is disabled at that time.
After the START condition, the bus master sends a chip address. This address is seven bits long followed by an
eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE and a 1
indicates a READ. The second byte selects the register to which the data will be written. The third byte contains
data to write to the selected register.
ACK from slave
ACK from slave
START
MSB Chip Address LSB
ACK from slave
W ACK MSB Register Address LSB ACK
MSB
Data LSB
ACK STOP
W ACK
address 0x40 data
ACK STOP
SCL
SDA
START
id = 0x60
address = 0x40
ACK
Figure 19. Write Cycle (w = write; SDA = 0), id = Device Address = 0x60 for LP87524B/J/P-Q1
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Programming (continued)
ACK from slave
START
MSB Chip Address LSB
W
id = 0x60
W
ACK from slave
MSB Register Address LSB
REPEATED START
ACK from slave Data from slave NACK from master
RS
MSB Chip Address LSB
R
RS
id = 0x60
R
MSB
Data
LSB
STOP
SCL
SDA
START
address = 0x3F
ACK
ACK
address 0x3F data
ACK
NACK
STOP
When READ function is to be accomplished, a WRITE function must precede the READ function as shown above.
Figure 20. Read Cycle ( r = read; SDA = 1), id = Device Address = 0x60 for LP87524B/J/P-Q1
7.5.1.4 I2C-Compatible Chip Address
NOTE
The device address for the LP87524B/J/P-Q1 is 0x60
After the START condition, the I2C master sends the 7-bit address followed by an eighth bit, read or write (R/W).
R/W = 0 indicates a WRITE and R/W = 1 indicates a READ. The second byte following the device address
selects the register address to which the data will be written. The third byte contains the data for the selected
register.
MSB
LSB
1
Bit 7
1
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
R/W
Bit 0
I2C Slave Address (chip address)
A.
Here device address is 1100000Bin = 60Hex.
Figure 21. Example Device Address
7.5.1.5 Auto-Increment Feature
The auto-increment feature allows writing several consecutive registers within one transmission. Every time an 8bit word is sent to the device, the internal address index counter is incremented by one and the next register is
written. Table 8 below shows writing sequence to two consecutive registers. Note that auto increment feature
does not work for read.
Table 8. Auto-Increment Example
MASTER
ACTION
START
DEVICE
ADDRESS
= 0x60
LP87524B/J/PQ1
34
REGISTER
ADDRESS
WRITE
ACK
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DATA
ACK
DATA
ACK
STOP
ACK
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SNVSAW2B – APRIL 2017 – REVISED DECEMBER 2018
7.6 Register Maps
7.6.1 Register Descriptions
The LP87524B/J/P-Q1 is controlled by a set of registers through the I2C-compatible interface. The device
registers, their addresses, and their abbreviations are listed in Table 9. A more detailed description is given in the
OTP_REV to GPIO_OUT sections.
The asterisk (*) marking indicates register bits which are updated from OTP memory during READ OTP state.
NOTE
This register map describes the default values read from OTP memory for a device with
orderable code of LP87524BRNFRQ1, LP87524JRNFRQ1 and LP87524PRNFRQ1. For
other LP8752x versions the default values read from OTP memory can be different.
Table 9. Summary of LP87524B/J/P-Q1 Control Registers
Addr
Register
Read /
Write
D7
D6
0x01
OTP_REV
R
0x02
BUCK0_
CTRL1
0x04
D5
D4
D3
D2
D1
D0
R/W
EN_BUCK0
EN_PIN_
CTRL0
BUCK0_EN_PIN
SELECT[1:0]
EN_ROOF
_FLOOR0
EN_RDIS0
BUCK0_
FPWM
Reserved
BUCK1_
CTRL1
R/W
EN_BUCK1
EN_PIN_
CTRL1
BUCK1_EN_PIN
SELECT[1:0]
EN_ROOF
_FLOOR1
EN_RDIS1
BUCK1_
FPWM
Reserved
0x06
BUCK2_
CTRL1
R/W
EN_BUCK2
EN_PIN_
CTRL2
BUCK2_EN_PIN
SELECT[1:0]
EN_ROOF
_FLOOR2
EN_RDIS2
BUCK2_
FPWM
Reserved
0x08
BUCK3_
CTRL1
R/W
EN_BUCK3
EN_PIN_
CTRL3
BUCK3_EN_PIN
SELECT[1:0]
EN_ROOF
_FLOOR3
EN_RDIS3
BUCK3_
FPWM
Reserved
0x0A
BUCK0_
VOUT
R/W
BUCK0_VSET[7:0]
0x0B
BUCK0_
FLOOR_
VOUT
R/W
BUCK0_FLOOR_VSET[7:0]
0x0C
BUCK1_
VOUT
R/W
BUCK1_VSET[7:0]
0x0D
BUCK1_
FLOOR_
VOUT
R/W
BUCK1_FLOOR_VSET[7:0]
0x0E
BUCK2_
VOUT
R/W
BUCK2_VSET[7:0]
0x0F
BUCK2_
FLOOR_
VOUT
R/W
BUCK2_FLOOR_VSET[7:0]
0x10
BUCK3_
VOUT
R/W
BUCK3_VSET[7:0]
0x11
BUCK3_
FLOOR_
VOUT
R/W
BUCK3_FLOOR_VSET[7:0]
0x12
BUCK0_
DELAY
R/W
BUCK0_SHUTDOWN_DELAY[3:0]
BUCK0_STARTUP_DELAY[3:0]
0x13
BUCK1_
DELAY
R/W
BUCK1_SHUTDOWN_DELAY[3:0]
BUCK1_STARTUP_DELAY[3:0]
0x14
BUCK2_
DELAY
R/W
BUCK2_SHUTDOWN_DELAY[3:0]
BUCK2_STARTUP_DELAY[3:0]
0x15
BUCK3_
DELAY
R/W
BUCK3_SHUTDOWN_DELAY[3:0]
BUCK3_STARTUP_DELAY[3:0]
0x16
GPIO2_
DELAY
R/W
GPIO2_SHUTDOWN_DELAY[3:0]
GPIO2_STARTUP_DELAY[3:0]
0x17
GPIO3_
DELAY
R/W
GPIO3_SHUTDOWN_DELAY[3:0]
GPIO3_STARTUP_DELAY[3:0]
0x18
RESET
R/W
OTP_ID[7:0]
SW_
RESET
Reserved
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Register Maps (continued)
Table 9. Summary of LP87524B/J/P-Q1 Control Registers (continued)
Addr
Register
Read /
Write
D7
D6
D5
D4
D3
D2
D1
D0
0x19
CONFIG
R/W
DOUBLE_D
ELAY
CLKIN_PD
Reserved
EN3_PD
TDIE
_WARN
_LEVEL
EN2_PD
EN1_PD
Reserved
0x1A
INT_TOP1
R/W
Reserved
INT_
BUCK23
INT_
BUCK01
NO_SYNC
_CLK
TDIE_SD
TDIE_
WARN
INT_
OVP
I_LOAD_
READY
0x1B
INT_TOP2
R/W
0x1C
INT_BUCK_
0_1
R/W
Reserved
BUCK1_
PG_INT
BUCK1_
SC_INT
BUCK1_
ILIM_INT
Reserved
BUCK0_
PG_INT
BUCK0_
SC_INT
BUCK0_
ILIM_INT
0x1D
INT_BUCK_
2_3
R/W
Reserved
BUCK3_
PG_INT
BUCK3_
SC_INT
BUCK3_
ILIM_INT
Reserved
BUCK2_
PG_INT
BUCK2_
SC_INT
BUCK2_
ILIM_INT
0x1E
TOP_
STAT
R
SYNC_CLK
_STAT
TDIE_SD
_STAT
TDIE_
WARN_
STAT
OVP_
STAT
Reserved
0x1F
BUCK_0_1_
STAT
R
BUCK1_
STAT
BUCK1_
PG_STAT
Reserved
BUCK1_
ILIM_
STAT
BUCK0_
STAT
BUCK0_
PG_STAT
Reserved
BUCK0_
ILIM_
STAT
0x20
BUCK_2_3_
STAT
R
BUCK3_
STAT
BUCK3_
PG_STAT
Reserved
BUCK3_
ILIM_STAT
BUCK2_
STAT
BUCK2_
PG_STAT
Reserved
BUCK2_
ILIM_STAT
0x21
TOP_
MASK1
R/W
Reserved
SYNC_CLK
_MASK
Reserved
TDIE_WAR
N_MASK
Reserved
I_LOAD_
READY_
MASK
0x22
TOP_
MASK2
R/W
0x23
BUCK_0_1_
MASK
R/W
Reserved
BUCK1_
PG_MASK
Reserved
BUCK1_
ILIM_
MASK
Reserved
BUCK0_
PG_MASK
Reserved
BUCK0_
ILIM_
MASK
0x24
BUCK_2_3_
MASK
R/W
Reserved
BUCK3_
PG_MASK
Reserved
BUCK3_
ILIM_
MASK
Reserved
BUCK2_
PG_MASK
Reserved
BUCK2_
ILIM_
MASK
0x25
SEL_I_
LOAD
R/W
Reserved
LOAD_CURRENT_
BUCK_SELECT[1:0]
0x26
I_LOAD_2
R
Reserved
BUCK_LOAD_CURRENT[
9:8]
0x27
I_LOAD_1
R
0x28
PGOOD
_CTRL1
R/W
0x29
PGOOD
_CTRL2
R/W
0x2A
PGOOD_FL
T
R
0x2B
PLL_CTRL
R/W
36
Reserved
RESET_
REG_MASK
BUCK_LOAD_CURRENT[7:0]
PG3_SEL[1:0]
HALF_DEL
AY
EN_PG0_
NINT
PLL_MODE[1:0]
0x2C
PIN_
FUNCTION
R/W
0x2D
GPIO_
CONFIG
R/W
Reserved
0x2E
GPIO_IN
R
GPIO_OUT
Reserved
Reserved
EN_
SPREAD
_SPEC
0x2F
RESET_
REG
Reserved
R/W
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PG2_SEL[1:0]
PGOOD_SE
T_
DELAY
EN_PGFLT
_STAT
Reserved
PG1_SEL[1:0]
PG0_SEL[1:0]
Reserved
PGOOD_WI
NDOW
PGOOD_O
D
PGOOD_P
OL
PG3_FLT
PG2_FLT
PG1_FLT
PG0_FLT
EXT_CLK_FREQ[4:0]
EN_PIN_CT
RL
_GPIO3
EN_PIN_SE
LECT
_GPIO3
EN_PIN_CT
RL
_GPIO2
EN_PIN_SE
LECT
_GPIO2
GPIO3_SEL
GPIO2_SEL
GPIO1_SEL
GPIO3_OD
GPIO2_OD
GPIO1_OD
Reserved
GPIO3_DIR
GPIO2_DIR
GPIO1_DIR
Reserved
GPIO3_IN
GPIO2_IN
GPIO1_IN
Reserved
GPIO3_OU
T
GPIO2_OU
T
GPIO1_OU
T
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7.6.1.1 OTP_REV
Address: 0x01
Figure 22. OTP_REV Register
D7
D6
D5
D4
D3
D2
D1
D0
OTP_ID[7:0]
Table 10. OTP_REV Register Field Descriptions
Bits
Field
Type
7:0
OTP_ID[7:0]
R
Default
Description
0x71 for
LP87524B,
0x72 for
LP87524J, Identification code of the OTP EPROM version
0x3B for
LP87524P
*
7.6.1.2 BUCK0_CTRL1
Address: 0x02
Figure 23. BUCK0_CTRL1 Register
D7
D6
EN_BUCK0
EN_PIN_CTRL
0
D5
D4
BUCK0_EN_PIN_SELECT[1:0]
D3
D2
D1
D0
EN_ROOF_
FLOOR0
EN_RDIS0
BUCK0_FPWM
Reserved
Table 11. BUCK0_CTRL1 Register Field Descriptions
Bits
Field
Type
Default
7
EN_BUCK0
R/W
1*
Enable Buck0 regulator:
0 - Buck0 regulator is disabled
1 - Buck0 regulator is enabled
Description
6
EN_PIN_CTRL0
R/W
1*
Enable EN1/2/3 pin control for Buck0:
0 - Only the EN_BUCK0 bit controls Buck0
1 - EN_BUCK0 bit AND ENx pin control Buck0
5:4
BUCK0_EN_PIN
_SELECT[1:0]
R/W
0x0*
3
EN_ROOF_
FLOOR0
R/W
0
Enable Roof/Floor control of EN1/2/3 pin if EN_PIN_CTRL0 = 1:
0 - Enable/disable (1/0) control
1 - Roof/floor (1/0) control
2
EN_RDIS0
R/W
1
Enable output discharge resistor when Buck0 is disabled:
0 - Discharge resistor disabled
1 - Discharge resistor enabled
1
BUCK0_FPWM
R/W
0
Reserved
R/W
Enable EN1/2/3 pin control for Buck0:
0x0 - EN_BUCK0 bit AND EN1 pin control Buck0
0x1 - EN_BUCK0 bit AND EN2 pin control Buck0
0x2 - EN_BUCK0 bit AND EN3 pin control Buck0
0x3 - Reserved
0 for
LP87524B,
Forces the Buck0 regulator to operate in PWM mode:
LP87524J,
0 - Automatic transitions between PFM and PWM modes (AUTO mode).
1 for
1 - Forced to PWM operation
LP87524P
*
0*
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7.6.1.3 BUCK1_CTRL1
Address: 0x04
Figure 24. BUCK1_CTRL1 Register
D7
D6
EN_BUCK1
EN_PIN_CTRL
1
D5
D4
BUCK1_EN_PIN_SELECT[1:0]
D3
D2
D1
D0
EN_ROOF_
FLOOR1
EN_RDIS1
BUCK1_FPWM
Reserved
Table 12. BUCK1_CTRL1 Register Field Descriptions
Bits
Field
Type
Default
7
EN_BUCK1
R/W
1*
Enable Buck1 regulator:
0 - Buck1 regulator is disabled
1 - Buck1 regulator is enabled
6
EN_PIN_CTRL1
R/W
1*
Enable EN1/2/3 pin control for Buck1:
0 - Only EN_BUCK1 bit controls Buck1
1 - EN_BUCK1 bit AND ENx pin control Buck1
5:4
BUCK1_EN_PIN
_SELECT[1:0]
R/W
0x0*
3
EN_ROOF_
FLOOR1
R/W
0
Enable Roof/Floor control of EN1/2/3 pin if EN_PIN_CTRL1 = 1:
0 - Enable/Disable (1/0) control
1 - Roof/Floor (1/0) control
2
EN_RDIS1
R/W
1
Enable output discharge resistor when Buck1 is disabled:
0 - Discharge resistor disabled
1 - Discharge resistor enabled
1
BUCK1_FPWM
R/W
0
Reserved
R/W
38
Description
Enable EN1/2/3 pin control for Buck1:
0x0 - EN_BUCK1 bit AND EN1 pin control Buck1
0x1 - EN_BUCK1 bit AND EN2 pin control Buck1
0x2 - EN_BUCK1 bit AND EN3 pin control Buck1
0x3 - Reserved
0 for
LP87524B,
Forces the Buck1 regulator to operate in PWM mode:
LP87524J,
0 - Automatic transitions between PFM and PWM modes (AUTO mode).
1 for
1 - Forced to PWM operation
LP87524P
*
0
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7.6.1.4 BUCK2_CTRL1
Address: 0x06
Figure 25. BUCK2_CTRL1 Register
D7
D6
EN_BUCK2
EN_PIN_CTRL
2
D5
D4
BUCK2_EN_PIN_SELECT[1:0]
D3
D2
D1
D0
EN_ROOF_
FLOOR2
EN_RDIS2
BUCK2_FPWM
Reserved
Table 13. BUCK2_CTRL1 Register Field Descriptions
Bits
Field
Type
Default
7
EN_BUCK2
R/W
1*
Enable Buck2 regulator:
0 - Buck2 regulator is disabled
1 - Buck2 regulator is enabled
6
EN_PIN_CTRL2
R/W
1*
Enable EN1/2/3 pin control for Buck2:
0 - Only EN_BUCK2 bit controls Buck2
1 - EN_BUCK2 bit AND ENx pin control Buck2
5:4
BUCK2_EN_PIN
_SELECT[1:0]
R/W
0x0*
3
EN_ROOF_
FLOOR2
R/W
0
Enable Roof/Floor control of EN1/2/3 pin if EN_PIN_CTRL2 = 1:
0 - Enable/Disable (1/0) control
1 - Roof/Floor (1/0) control
2
EN_RDIS2
R/W
1
Enable output discharge resistor when Buck2 is disabled:
0 - Discharge resistor disabled
1 - Discharge resistor enabled
1
BUCK2_FPWM
R/W
1*
0
Reserved
R/W
0*
Copyright © 2017–2018, Texas Instruments Incorporated
Description
Enable EN1/2/3 pin control for Buck2:
0x0 - EN_BUCK2 bit AND EN1 pin control Buck2
0x1 - EN_BUCK2 bit AND EN2 pin control Buck2
0x2 - EN_BUCK2 bit AND EN3 pin control Buck2
0x3 - Reserved
Forces the Buck2 regulator to operate in PWM mode:
0 - Automatic transitions between PFM and PWM modes (AUTO mode)
1 - Forced to PWM operation
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7.6.1.5 BUCK3_CTRL1
Address: 0x08
Figure 26. BUCK3_CTRL1 Register
D7
D6
EN_BUCK3
EN_PIN_CTRL
3
D5
D4
BUCK3_EN_PIN_SELECT[1:0]
D3
D2
D1
D0
EN_ROOF_
FLOOR3
EN_RDIS3
BUCK3_FPWM
Reserved
Table 14. BUCK3_CTRL1 Register Field Descriptions
Bits
Field
Type
Default
7
EN_BUCK3
R/W
1*
Enable Buck3 regulator:
0 - Buck3 regulator is disabled
1 - Buck3 regulator is enabled
6
EN_PIN_CTRL3
R/W
1*
Enable EN1/2/3 pin control for Buck3:
0 - Only EN_BUCK3 bit controls Buck3
1 - EN_BUCK3 bit AND ENx pin control Buck3
5:4
BUCK3_EN_PIN
_SELECT[1:0]
R/W
0x0*
3
EN_ROOF_
FLOOR3
R/W
0
Enable Roof/Floor control of EN1/2/3 pin if EN_PIN_CTRL3 = 1:
0 - Enable/Disable (1/0) control
1 - Roof/Floor (1/0) control
2
EN_RDIS3
R/W
1
Enable output discharge resistor when Buck3 is disabled:
0 - Discharge resistor disabled
1 - Discharge resistor enabled
1
BUCK3_FPWM
R/W
1*
0
Reserved
R/W
0
40
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Description
Enable EN1/2/3 pin control for Buck3:
0x0 - EN_BUCK3 bit AND EN1 pin control Buck3
0x1 - EN_BUCK3 bit AND EN2 pin control Buck3
0x2 - EN_BUCK3 bit AND EN3 pin control Buck3
0x3 - Reserved
Forces the Buck3 regulator to operate in PWM mode:
0 - Automatic transitions between PFM and PWM modes (AUTO mode)
1 - Forced to PWM operation
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: LP87524B-Q1 LP87524J-Q1 LP87524P-Q1
LP87524B-Q1
LP87524J-Q1, LP87524P-Q1
www.ti.com
SNVSAW2B – APRIL 2017 – REVISED DECEMBER 2018
7.6.1.6 BUCK0_VOUT
Address: 0x0A
Figure 27. BUCK0_VOUT Register
D7
D6
D5
D4
D3
D2
D1
D0
BUCK0_VSET[7:0]
Table 15. BUCK0_VOUT Register Field Descriptions
Bits
Field
Type
Default
7:0
BUCK0_VSET[7:0]
R/W
0xFC for
LP87524B,
LP87524J,
0x4D for
LP87524P
*
Description
Sets the output voltage of Buck0 regulator
Reserved, DO NOT USE
0x00...0x09
0.6 V - 0.73 V, 10 mV steps
0x0A - 0.6 V
...
0x17 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0x18 - 0.735 V
...
0x9D - 1.4 V
1.4 V - 3.36 V, 20 mV steps
0x9E - 1.42 V
...
0xFF - 3.36 V
If the input voltage is above 4 V, do not use output voltages below 1.0 V.
7.6.1.7 BUCK0_FLOOR_VOUT
Address: 0x0B
Figure 28. BUCK0_FLOOR_VOUT Register
D7
D6
D5
D4
D3
D2
D1
D0
BUCK0_FLOOR_VSET[7:0]
Table 16. BUCK0_FLOOR_VOUT Register Field Descriptions
Bits
Field
Type
Default
7:0
BUCK0_FLOOR
_VSET[7:0]
R/W
0x00
Description
Sets the output voltage of Buck0 regulator when floor state is used:
Reserved, DO NOT USE
0x00...0x09
0.6 V - 0.73 V, 10 mV steps
0x0A - 0.6 V
...
0x17 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0x18 - 0.735 V
...
0x9D - 1.4 V
1.4 V - 3.36 V, 20 mV steps
0x9E - 1.42 V
...
0xFF - 3.36 V
If the input voltage is above 4 V, do not use output voltages below 1.0 V.
7.6.1.8 BUCK1_VOUT
Address: 0x0C
Figure 29. BUCK1_VOUT Register
D7
D6
D5
D4
D3
D2
D1
D0
BUCK1_VSET[7:0]
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41
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LP87524J-Q1, LP87524P-Q1
SNVSAW2B – APRIL 2017 – REVISED DECEMBER 2018
www.ti.com
Table 17. BUCK1_VOUT Register Field Descriptions
Bits
Field
Type
Default
7:0
BUCK1_VSET[7:0]
R/W
0x75*
Description
Sets the output voltage of Buck1 regulator:
Reserved, DO NOT USE
0x00...0x09
0.6 V - 0.73 V, 10 mV steps
0x0A - 0.6 V
...
0x17 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0x18 - 0.735 V
...
0x9D - 1.4 V
1.4 V - 3.36 V, 20 mV steps
0x9E - 1.42 V
...
0xFF - 3.36 V
If the input voltage is above 4 V, do not use output voltages below 1.0 V.
7.6.1.9 BUCK1_FLOOR_VOUT
Address: 0x0D
Figure 30. BUCK1_FLOOR_VOUT Register
D7
D6
D5
D4
D3
D2
D1
D0
BUCK1_FLOOR_VSET[7:0]
Table 18. BUCK1_FLOOR_VOUT Register Field Descriptions
Bits
Field
Type
Default
7:0
BUCK1_FLOOR
_VSET[7:0]
R/W
0x00
Description
Sets the output voltage of Buck1 regulator when floor state is used:
Reserved, DO NOT USE
0x00...0x09
0.6 V - 0.73 V, 10 mV steps
0x0A - 0.6 V
...
0x17 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0x18 - 0.735 V
...
0x9D - 1.4 V
1.4 V - 3.36 V, 20 mV steps
0x9E - 1.42 V
...
0xFF - 3.36 V
If the input voltage is above 4 V, do not use output voltages below 1.0 V.
7.6.1.10 BUCK2_VOUT
Address: 0x0E
Figure 31. BUCK2_VOUT Register
D7
D6
D5
D4
D3
D2
D1
D0
BUCK2_VSET[7:0]
42
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LP87524B-Q1
LP87524J-Q1, LP87524P-Q1
www.ti.com
SNVSAW2B – APRIL 2017 – REVISED DECEMBER 2018
Table 19. BUCK2_VOUT Register Field Descriptions
Bits
Field
Type
Default
7:0
BUCK2_VSET[7:0]
R/W
0xB1 for
LP87524B,
0x4D for
LP87524J,
LP87524P
*
Description
Sets the output voltage of Buck2 regulator:
Reserved, DO NOT USE
0x00...0x09
0.6 V - 0.73 V, 10 mV steps
0x0A - 0.6V
...
0x17 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0x18 - 0.735 V
...
0x9D - 1.4 V
1.4 V - 3.36 V, 20 mV steps
0x9E - 1.42 V
...
0xFF - 3.36 V
If the input voltage is above 4 V, do not use output voltages below 1.0 V.
7.6.1.11 BUCK2_FLOOR_VOUT
Address: 0x0F
Figure 32. BUCK2_FLOOR_VOUT Register
D7
D6
D5
D4
D3
D2
D1
D0
BUCK2_FLOOR_VSET[7:0]
Table 20. BUCK2_FLOOR_VOUT Register Field Descriptions
Bits
Field
Type
Default
7:0
BUCK2_FLOOR
_VSET[7:0]
R/W
0x00
Description
Sets the output voltage of Buck2 regulator when floor state is used:
Reserved, DO NOT USE
0x00...0x09
0.6 V - 0.73 V, 10 mV steps
0x0A - 0.6 V
...
0x17 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0x18 - 0.735 V
...
0x9D - 1.4 V
1.4 V - 3.36 V, 20 mV steps
0x9E - 1.42 V
...
0xFF - 3.36 V
If the input voltage is above 4 V, do not use output voltages below 1.0 V.
7.6.1.12 BUCK3_VOUT
Address: 0x10
Figure 33. BUCK3_VOUT Register
D7
D6
D5
D4
D3
D2
D1
D0
BUCK3_VSET[7:0]
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Table 21. BUCK3_VOUT Register Field Descriptions
Bits
Field
Type
Default
7:0
BUCK3_VSET[7:0]
R/W
0xCA for
LP87524B,
LP87524J,
0xB1 for
LP87524P
*
Description
Sets the output voltage of Buck3 regulator:
Reserved, DO NOT USE
0x00...0x09
0.6 V - 0.73 V, 10 mV steps
0x0A - 0.6 V
...
0x17 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0x18 - 0.735 V
...
0x9D - 1.4 V
1.4 V - 3.36 V, 20 mV steps
0x9E - 1.42 V
...
0xFF - 3.36 V
If the input voltage is above 4 V, do not use output voltages below 1.0 V.
7.6.1.13 BUCK3_FLOOR_VOUT
Address: 0x11
Figure 34. BUCK3_FLOOR_VOUT Register
D7
D6
D5
D4
D3
D2
D1
D0
BUCK3_FLOOR_VSET[7:0]
Table 22. BUCK3_FLOOR_VOUT Register Field Descriptions
Bits
Field
Type
Default
7:0
BUCK3_FLOOR
_VSET[7:0]
R/W
0x00
Description
Sets the output voltage of Buck3 regulator when Floor state is used:
Reserved, DO NOT USE
0x00...0x09
0.6 V - 0.73 V, 10 mV steps
0x0A - 0.6 V
...
0x17 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0x18 - 0.735 V
...
0x9D - 1.4 V
1.4 V - 3.36 V, 20 mV steps
0x9E - 1.42 V
...
0xFF - 3.36 V
If the input voltage is above 4 V, do not use output voltages below 1.0 V.
7.6.1.14 BUCK0_DELAY
Address: 0x12
Figure 35. BUCK0_DELAY Register
D7
D6
D5
BUCK0_SHUTDOWN_DELAY[3:0]
44
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D4
D3
D2
D1
D0
BUCK0_STARTUP_DELAY[3:0]
Copyright © 2017–2018, Texas Instruments Incorporated
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LP87524B-Q1
LP87524J-Q1, LP87524P-Q1
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SNVSAW2B – APRIL 2017 – REVISED DECEMBER 2018
Table 23. BUCK0_DELAY Register Field Descriptions
Bits
Field
Type
Default
7:4
BUCK0_
SHUTDOWN_
DELAY[3:0]
R/W
0x0 for
LP87524B,
LP87524J,
0x1 for
LP87524P
*
Shutdown delay of Buck0 from falling edge of ENx signal (DOUBLE_DELAY = 0 in
CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
delay options in Table 4):
0x0 - 0 ms
0x1 - 1 ms
...
0xF - 15 ms
Description
3:0
BUCK0_
STARTUP_
DELAY[3:0]
R/W
0x5 for
LP87524B,
LP87524J,
0x3 for
LP87524P
*
Start-up delay of Buck0 from rising edge of ENx signal (DOUBLE_DELAY = 0 in
CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
delay options in Table 4):
0x0 - 0 ms
0x1 - 1 ms
...
0xF - 15 ms
7.6.1.15 BUCK1_DELAY
Address: 0x13
Figure 36. BUCK1_DELAY Register
D7
D6
D5
D4
D3
BUCK1_SHUTDOWN_DELAY[3:0]
D2
D1
D0
BUCK1_STARTUP_DELAY[3:0]
Table 24. BUCK1_DELAY Register Field Descriptions
Bits
Field
Type
Default
7:4
BUCK1_
SHUTDOWN_
DELAY[3:0]
R/W
0x0 for
LP87524B,
LP87524J,
0x1 for
LP87524P
*
Shutdown delay of Buck1 from falling edge of ENx signal (DOUBLE_DELAY = 0 in
CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
delay options in Table 4):
0x0 - 0 ms
0x1 - 1 ms
...
0xF - 15 ms
Description
3:0
BUCK1_
STARTUP_
DELAY[3:0]
R/W
0x5 for
LP87524B,
LP87524J,
0x7 for
LP87524P
*
start-up delay of Buck1 from rising edge of ENx signal (DOUBLE_DELAY = 0 in
CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
delay options in Table 4):
0x0 - 0 ms
0x1 - 1 ms
...
0xF - 15 ms
7.6.1.16 BUCK2_DELAY
Address: 0x14
Figure 37. BUCK2_DELAY Register
D7
D6
D5
BUCK2_SHUTDOWN_DELAY[3:0]
D4
D3
D2
D1
D0
BUCK2_STARTUP_DELAY[3:0]
Table 25. BUCK2_DELAY Register Field Descriptions
Bits
Field
Type
Default
7:4
BUCK2_
SHUTDOWN_
DELAY[3:0]
R/W
0x0 for
LP87524B,
LP87524J,
0x1 for
LP87524P
*
Copyright © 2017–2018, Texas Instruments Incorporated
Description
Shutdown delay of Buck2 from falling edge of ENx signal (DOUBLE_DELAY = 0 in
CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
delay options in Table 4):
0x0 - 0 ms
0x1 - 1 ms
...
0xF - 15 ms
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45
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LP87524J-Q1, LP87524P-Q1
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Table 25. BUCK2_DELAY Register Field Descriptions (continued)
Bits
Field
Type
Default
3:0
BUCK2_
STARTUP_
DELAY[3:0]
R/W
0x2 for
LP87524B,
LP87524J,
0x5 for
LP87524P
*
46
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Description
start-up delay of Buck2 from rising edge of ENx signal (DOUBLE_DELAY = 0 in
CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
delay options in Table 4):
0x0 - 0 ms
0x1 - 1 ms
...
0xF - 15 ms
Copyright © 2017–2018, Texas Instruments Incorporated
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LP87524J-Q1, LP87524P-Q1
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SNVSAW2B – APRIL 2017 – REVISED DECEMBER 2018
7.6.1.17 BUCK3_DELAY
Address: 0x15
Figure 38. BUCK3_DELAY Register
D7
D6
D5
D4
D3
BUCK3_SHUTDOWN_DELAY[3:0]
D2
D1
D0
BUCK3_STARTUP_DELAY[3:0]
Table 26. BUCK3_DELAY Register Field Descriptions
Bits
Field
Type
Default
7:4
BUCK3_
SHUTDOWN_
DELAY[3:0]
R/W
0x1*
Shutdown delay of Buck3 from falling edge of ENx signal (DOUBLE_DELAY = 0 in
CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
delay options in Table 4):
0x0 - 0 ms
0x1 - 1 ms
...
0xF - 15 ms
Description
3:0
BUCK3_
STARTUP_
DELAY[3:0]
R/W
0x0*
Startup delay of Buck3 from rising edge of ENx signal (DOUBLE_DELAY = 0 in
CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
delay options in Table 4):
0x0 - 0 ms
0x1 - 1 ms
...
0xF - 15 ms
7.6.1.18 GPIO2_DELAY
Address: 0x16
Figure 39. GPIO2_DELAY Register
D7
D6
D5
D4
D3
GPIO2_SHUTDOWN_DELAY[3:0]
D2
D1
D0
GPIO2_STARTUP_DELAY[3:0]
Table 27. GPIO2_DELAY Register Field Descriptions
Bits
Field
Type
Default
Description
7:4
GPIO2_
SHUTDOWN_
DELAY[3:0]
R/W
0x0 for
LP87524B,
LP87524J,
0x1 for
LP87524P
*
Delay for GPIO2 falling edge from falling edge of ENx signal (DOUBLE_DELAY = 0 in
CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
delay options in Table 4):
0x0 - 0 ms
0x1 - 1 ms
...
0xF - 15 ms
3:0
GPIO2_
STARTUP_
DELAY[3:0]
R/W
0x5 for
LP87524B,
LP87524J,
0x9 for
LP87524P
*
Delay for GPIO2 rising edge from rising edge of ENx signal (DOUBLE_DELAY = 0 in
CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
delay options in Table 4):
0x0 - 0 ms
0x1 - 1 ms
...
0xF - 15 ms
7.6.1.19 GPIO3_DELAY
Address: 0x17
Figure 40. GPIO3_DELAY Register
D7
D6
D5
GPIO3_SHUTDOWN_DELAY[3:0]
Copyright © 2017–2018, Texas Instruments Incorporated
D4
D3
D2
D1
D0
GPIO3_STARTUP_DELAY[3:0]
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www.ti.com
Table 28. GPIO3_DELAY Register Field Descriptions
Bits
Field
Type
Default
Description
7:4
GPIO3_
SHUTDOWN_
DELAY[3:0]
R/W
0x0 *
Delay for GPIO3 falling edge from falling edge of ENx signal (DOUBLE_DELAY = 0 in
CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
delay options in Table 4):
0x0 - 0 ms
0x1 - 1 ms
...
0xF - 15 ms
3:0
GPIO3_
STARTUP_
DELAY[3:0]
R/W
0x3 for
LP87524B,
LP87524J,
0xD for
LP87524P
*
Delay for GPIO3 rising edge from rising edge of ENx signal (DOUBLE_DELAY = 0 in
CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
delay options in Table 4):
0x0 - 0 ms
0x1 - 1 ms
...
0xF - 15 ms
7.6.1.20 RESET
Address: 0x18
Figure 41. RESET Register
D7
D6
D5
D4
D3
D2
D1
Reserved
D0
SW_RESET
Table 29. RESET Register Field Descriptions
Bits
Field
Type
Default
7:1
Reserved
R/W
0x00
0
SW_RESET
R/W
0
Description
Software commanded reset. When written to 1, the registers are reset to default
values, OTP memory is read, and the I2C interface is reset.
The bit is automatically cleared.
7.6.1.21 CONFIG
Address: 0x19
Figure 42. CONFIG Register
D7
D6
D5
D4
D3
D2
D1
D0
DOUBLE_DEL
AY
CLKIN_PD
EN4_PD
EN3_PD
TDIE_WARN_
LEVEL
EN2_PD
EN1_PD
Reserved
Table 30. CONFIG Register Field Descriptions
Bits
Field
Type
Default
7
DOUBLE_DELAY
R/W
0*
Start-up and shutdown delays from ENx signals:
0 - 0 ms - 15 ms with 1-ms steps
1 - 0 ms - 30 ms with 2-ms steps
6
CLKIN_PD
R/W
1*
Selects the pulldown resistor on the CLKIN input pin:
0 - Pulldown resistor is disabled.
1 - Pulldown resistor is enabled.
5
Reserved
R/W
0*
4
EN3_PD
R/W
0*
3
TDIE_WARN_
LEVEL
R/W
48
Description
Selects the pulldown resistor on the EN3 (GPIO3) input pin:
0 - Pulldown resistor is disabled.
1 - Pulldown resistor is enabled.
1 for
LP87524B,
Thermal warning threshold level:
LP87524J,
0 - 125°C
0 for
1 - 137°C.
LP87524P
*
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SNVSAW2B – APRIL 2017 – REVISED DECEMBER 2018
Table 30. CONFIG Register Field Descriptions (continued)
Bits
Field
Type
Default
2
EN2_PD
R/W
0*
Selects the pull down resistor on the EN2 (GPIO2) input pin:
0 - Pulldown resistor is disabled.
1 - Pull-down resistor is enabled.
Description
1
EN1_PD
R/W
1*
Selects the pull down resistor on the EN1 (GPIO1) input pin:
0 - Pulldown resistor is disabled.
1 - Pulldown resistor is enabled.
0
Reserved
R/W
0
7.6.1.22 INT_TOP1
Address: 0x1A
Figure 43. INT_TOP1 Register
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
INT_BUCK23
INT_BUCK01
NO_SYNC_CL
K
TDIE_SD
TDIE_WARN
INT_OVP
I_LOAD_
READY
Table 31. INT_TOP1 Register Field Descriptions
Bits
Field
Type
Default
7
Reserved
R/W
0
Description
6
INT_BUCK23
R
0
Interrupt indicating that output Buck3 and/or Buck2 have a pending interrupt. The
reason for the interrupt is indicated in INT_BUCK_2_3 register.
This bit is cleared automatically when INT_BUCK_2_3 register is cleared to 0x00.
5
INT_BUCK01
R
0
Interrupt indicating that output Buck1 and/or Buck0 have a pending interrupt. The
reason for the interrupt is indicated in INT_BUCK_0_1 register.
This bit is cleared automatically when INT_BUCK_0_1 register is cleared to 0x00.
4
NO_SYNC_CLK
R/W
0
Latched status bit indicating that the external clock is not valid.
Write 1 to clear interrupt.
3
TDIE_SD
R/W
0
Latched status bit indicating that the die junction temperature has exceeded the
thermal shutdown level. The regulators have been disabled if they were enabled. The
regulators cannot be enabled if this bit is active. The actual status of the thermal
warning is indicated by TDIE_SD_STAT bit in TOP_STAT register.
Write 1 to clear interrupt.
2
TDIE_WARN
R/W
0
Latched status bit indicating that the die junction temperature has exceeded the
thermal warning level. The actual status of the thermal warning is indicated by
TDIE_WARN_STAT bit in TOP_STAT register.
Write 1 to clear interrupt.
1
INT_OVP
R/W
0
Latched status bit indicating that the input voltage has exceeded the overvoltage
detection level. The actual status of the overvoltage is indicated by OVP_STAT bit in
TOP_STAT register.
Write 1 to clear interrupt.
0
I_LOAD_READY
R/W
0
Latched status bit indicating that the load current measurement result is available in
I_LOAD_1 and I_LOAD_2 registers.
Write 1 to clear interrupt.
7.6.1.23 INT_TOP2
Address: 0x1B
Figure 44. INT_TOP2 Register
D7
D6
D5
D4
D3
D2
D1
Reserved
Copyright © 2017–2018, Texas Instruments Incorporated
D0
RESET_REG
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Table 32. INT_TOP2 Register Field Descriptions
Bits
Field
Type
Default
7:1
Reserved
R/W
0x00
0
RESET_REG
R/W
0
Description
Latched status bit indicating that either start-up (NRST rising edge) is done, VANA
supply voltage has been below undervoltage threshold level, or the host has requested
a reset (SW_RESET bit in RESET register). The regulators have been disabled, and
registers are reset to default values and the normal start-up procedure is done.
Write 1 to clear interrupt.
7.6.1.24 INT_BUCK_0_1
Address: 0x1C
Figure 45. INT_BUCK_0_1 Register
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
BUCK1_PG
_INT
BUCK1_SC
_INT
BUCK1_ILIM
_INT
Reserved
BUCK0_PG
_INT
BUCK0_SC
_INT
BUCK0_ILIM
_INT
Table 33. INT_BUCK_0_1 Register Field Descriptions
Bits
Field
Type
Default
7
Reserved
R/W
0
Description
6
BUCK1_PG_INT
R/W
0
Latched status bit indicating that Buck1 output voltage has reached Power-Goodthreshold level.
Write 1 to clear.
5
BUCK1_SC_INT
R/W
0
Latched status bit indicating that the Buck1 output voltage has fallen below 0.35-V
level during operation or Buck1 output did not reach 0.35-V level in 1 ms from enable.
Write 1 to clear.
4
BUCK1_ILIM_INT
R/W
0
Latched status bit indicating that output current limit has been active.
Write 1 to clear.
3
Reserved
R/W
0
2
BUCK0_PG_INT
R/W
0
Latched status bit indicating that Buck0 output voltage has reached Power-Goodthreshold level.
Write 1 to clear.
1
BUCK0_SC_INT
R/W
0
Latched status bit indicating that the Buck0 output voltage has fallen below 0.35-V
level during operation or Buck0 output did not reach 0.35-V level in 1 ms from enable.
Write 1 to clear.
0
BUCK0_ILIM_INT
R/W
0
Latched status bit indicating that output current limit has been active.
Write 1 to clear.
7.6.1.25 INT_BUCK_2_3
Address: 0x1D
Figure 46. INT_BUCK_2_3 Register
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
BUCK3_PG
_INT
BUCK3_SC
_INT
BUCK3_ILIM
_INT
Reserved
BUCK2_PG
_INT
BUCK2_SC
_INT
BUCK2_ILIM
_INT
Table 34. INT_BUCK_2_3 Register Field Descriptions
Bits
50
Field
Type
Default
7
Reserved
R/W
0
6
BUCK3_PG_INT
R/W
0
Latched status bit indicating that Buck3 output voltage has reached Power-Goodthreshold level.
Write 1 to clear.
5
BUCK3_SC_INT
R/W
0
Latched status bit indicating that the Buck3 output voltage has fallen below 0.35-V
level during operation or Buck3 output did not reach 0.35-V level in 1 ms from enable.
Write 1 to clear.
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SNVSAW2B – APRIL 2017 – REVISED DECEMBER 2018
Table 34. INT_BUCK_2_3 Register Field Descriptions (continued)
Bits
Field
Type
Default
4
BUCK3_ILIM_INT
R/W
0
Description
3
Reserved
R/W
0
2
BUCK2_PG_INT
R/W
0
Latched status bit indicating that Buck2 output voltage has reached Power-Goodthreshold level.
Write 1 to clear.
1
BUCK2_SC_INT
R/W
0
Latched status bit indicating that the Buck2 output voltage has fallen below 0.35-V
level during operation or Buck2 output did not reach 0.35-V level in 1 ms from enable.
Write 1 to clear.
0
BUCK2_ILIM_INT
R/W
0
Latched status bit indicating that output current limit has been active.
Write 1 to clear.
Latched status bit indicating that output current limit has been active.
Write 1 to clear.
7.6.1.26 TOP_STAT
Address: 0x1E
Figure 47. TOP_STAT Register
D7
D6
D5
Reserved
D4
D3
D2
D1
D0
SYNC_CLK
_STAT
TDIE_SD
_STAT
TDIE_WARN
_STAT
OVP_STAT
Reserved
Table 35. TOP_STAT Register Field Descriptions
Bits
Field
Type
Default
7:5
Reserved
R
0x0
Description
4
SYNC_CLK_STAT
R
0
Status bit indicating the status of external clock (CLKIN):
0 - External clock frequency is valid
1 - External clock frequency is not valid
3
TDIE_SD_STAT
R
0
Status bit indicating the status of thermal shutdown:
0 - Die temperature below thermal shutdown level
1 - Die temperature above thermal shutdown level
2
TDIE_WARN
_STAT
R
0
Status bit indicating the status of thermal warning:
0 - Die temperature below thermal warning level
1 - Die temperature above thermal warning level
1
OVP_STAT
R
0
Status bit indicating the status of input overvoltage monitoring:
0 - Input voltage below overvoltage threshold level
1 - Input voltage above overvoltage threshold level
0
Reserved
R
0
7.6.1.27 BUCK_0_1_STAT
Address: 0x1F
Figure 48. BUCK_0_1_STAT Register
D7
D6
D5
D4
D3
D2
D1
D0
BUCK1_STAT
BUCK1_PG
_STAT
Reserved
BUCK1_ILIM
_STAT
BUCK0_STAT
BUCK0_PG
_STAT
Reserved
BUCK0_ILIM
_STAT
Table 36. BUCK_0_1_STAT Register Field Descriptions
Bits
Field
Type
Default
7
BUCK1_STAT
R
0
Status bit indicating the enable/disable status of Buck1:
0 - Buck1 regulator is disabled
1 - Buck1 regulator is enabled
6
BUCK1_PG_STAT
R
0
Status bit indicating Buck1 output voltage validity (raw status)
0 - Buck1 output is below Power-Good-threshold level
1 - Buck1 output is above Power-Good-threshold level
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Description
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Table 36. BUCK_0_1_STAT Register Field Descriptions (continued)
Bits
Field
Type
Default
5
Reserved
R
0
Description
4
BUCK1_ILIM
_STAT
R
0
Status bit indicating Buck1 current limit status (raw status)
0 - Buck1 output current is below current limit level
1 - Buck1 output current limit is active
3
BUCK0_STAT
R
0
Status bit indicating the enable/disable status of Buck0:
0 - Buck0 regulator is disabled
1 - Buck0 regulator is enabled
2
BUCK0_PG_STAT
R
0
Status bit indicating Buck0 output voltage validity (raw status):
0 - Buck0 output is below Power-Good-threshold level
1 - Buck0 output is above Power-Good-threshold level
1
Reserved
R
0
0
BUCK0_ILIM
_STAT
R
0
Status bit indicating Buck0 current limit status (raw status):
0 - Buck0 output current is below current limit level
1 - Buck0 output current limit is active
7.6.1.28 BUCK_2_3_STAT
Address: 0x20
Figure 49. BUCK_2_3_STAT Register
D7
D6
D5
D4
D3
D2
D1
D0
BUCK3_STAT
BUCK3_PG
_STAT
Reserved
BUCK3_ILIM
_STAT
BUCK2_STAT
BUCK2_PG
_STAT
Reserved
BUCK2_ILIM
_STAT
Table 37. BUCK_2_3_STAT Register Field Descriptions
Bits
Field
Type
Default
Description
7
BUCK3_STAT
R
0
Status bit indicating the enable/disable status of Buck3:
0 - Buck3 regulator is disabled
1 - Buck3 regulator is enabled
6
BUCK3_PG_STAT
R
0
Status bit indicating Buck3 output voltage validity (raw status):
0 - Buck3 output is below Power-Good-threshold level
1 - Buck3 output is above Power-Good-threshold level
5
Reserved
R
0
4
BUCK3_ILIM
_STAT
R
0
Status bit indicating Buck3 current limit status (raw status):
0 - Buck3 output current is below current limit level
1 - Buck3 output current limit is active
3
BUCK2_STAT
R
0
Status bit indicating the enable/disable status of Buck2:
0 - Buck2 regulator is disabled
1 - Buck2 regulator is enabled
2
BUCK2_PG_STAT
R
0
Status bit indicating Buck2 output voltage validity (raw status):
0 - Buck2 output is below Power-Good-threshold level
1 - Buck2 output is above Power-Good-threshold level
1
Reserved
R
0
0
BUCK2_ILIM
_STAT
R
0
Status bit indicating Buck2 current limit status (raw status):
0 - Buck2 output current is below current limit level
1 - Buck2 output current limit is active
7.6.1.29 TOP_MASK1
Address: 0x21
Figure 50. TOP_MASK1 Register
D7
Reserved
52
D6
D5
Reserved
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D4
D3
D2
D1
D0
SYNC_CLK
_MASK
Reserved
TDIE_WARN
_MASK
Reserved
I_LOAD_
READY_MASK
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Table 38. TOP_MASK1 Register Field Descriptions
Bits
Field
Type
Default
7
Reserved
R/W
1*
6:5
Reserved
R/W
0x0
4
SYNC_CLK
_MASK
R/W
0*
3
Reserved
R/W
0
2
TDIE_WARN
_MASK
R/W
0*
1
Reserved
R/W
0
0
I_LOAD_
READY_MASK
R/W
1*
Description
Masking for external clock detection interrupt (NO_SYNC_CLK in INT_TOP1 register):
0 - Interrupt generated
1 - Interrupt not generated
Masking for thermal warning interrupt (TDIE_WARN in INT_TOP1 register):
0 - Interrupt generated
1 - Interrupt not generated
This bit does not affect TDIE_WARN_STAT status bit in TOP_STAT register.
Masking for load current measurement ready interrupt (I_LOAD_READY in INT_TOP
register).
0 - Interrupt generated
1 - Interrupt not generated
7.6.1.30 TOP_MASK2
Address: 0x22
Figure 51. TOP_MASK2 Register
D7
D6
D5
D4
D3
D2
D1
Reserved
D0
RESET_REG
_MASK
Table 39. TOP_MASK2 Register Field Descriptions
Bits
Field
Type
Default
7:1
Reserved
R/W
0x00
0
RESET_REG
_MASK
R/W
1*
Description
Masking for register reset interrupt (RESET_REG in INT_TOP2 register):
0 - Interrupt generated
1 - Interrupt not generated
7.6.1.31 BUCK_0_1_MASK
Address: 0x23
Figure 52. BUCK_0_1_MASK Register
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
BUCK1_PG
_MASK
Reserved
BUCK1_ILIM
_MASK
Reserved
BUCK0_PG
_MASK
Reserved
BUCK0_ILIM
_MASK
Table 40. BUCK_0_1_MASK Register Field Descriptions
Bits
Field
Type
Default
7
Reserved
R/W
0
6
BUCK1_PG_MASK
R/W
1*
5
Reserved
R
0
4
BUCK1_ILIM
_MASK
R/W
1*
Copyright © 2017–2018, Texas Instruments Incorporated
Description
Masking for Buck1 Power-Good interrupt (BUCK1_PG_INT in INT_BUCK_0_1
register):
0 - Interrupt generated
1 - Interrupt not generated
This bit does not affect BUCK1_PG_STAT status bit in BUCK_0_1_STAT register.
Masking for Buck1 current-limit-detection interrupt (BUCK1_ILIM_INT in
INT_BUCK_0_1 register):
0 - Interrupt generated
1 - Interrupt not generated
This bit does not affect BUCK1_ILIM_STAT status bit in BUCK_0_1_STAT register.
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Table 40. BUCK_0_1_MASK Register Field Descriptions (continued)
Bits
Field
Type
Default
3
Reserved
R/W
0
2
BUCK0_PG_MASK
R/W
1*
1
Reserved
R
0
0
BUCK0_ILIM
_MASK
R/W
1*
Description
Masking for Buck0 Power-Good interrupt (BUCK0_PG_INT in INT_BUCK_0_1
register):
0 - Interrupt generated
1 - Interrupt not generated
This bit does not affect BUCK0_PG_STAT status bit in BUCK_0_1_STAT register.
Masking for Buck0 current-limit-detection interrupt (BUCK0_ILIM_INT in
INT_BUCK_0_1 register):
0 - Interrupt generated
1 - Interrupt not generated
This bit does not affect BUCK0_ILIM_STAT status bit in BUCK_0_1_STAT register.
7.6.1.32 BUCK_2_3_MASK
Address: 0x24
Figure 53. BUCK_2_3_MASK Register
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
BUCK3_PG
_MASK
Reserved
BUCK3_ILIM
_MASK
Reserved
BUCK2_PG
_MASK
Reserved
BUCK2_ILIM
_MASK
Table 41. BUCK_2_3_MASK Register Field Descriptions
Bits
Field
Type
Default
7
Reserved
R/W
0
6
BUCK3_PG_MASK
R/W
1*
5
Reserved
R
0
4
BUCK3_ILIM
_MASK
R/W
1*
3
Reserved
R/W
0
2
BUCK2_PG_MASK
R/W
1*
1
Reserved
R
0
0
BUCK2_ILIM
_MASK
R/W
1*
Description
Masking for Buck3 Power-Good interrupt (BUCK3_PG_INT in INT_BUCK_2_3
register):
0 - Interrupt generated
1 - Interrupt not generated
This bit does not affect BUCK3_PG_STAT status bit in BUCK_2_3_STAT register.
Masking for Buck3 current-limit-detection interrupt (BUCK3_ILIM_INT in
INT_BUCK_2_3 register):
0 - Interrupt generated
1 - Interrupt not generated
This bit does not affect BUCK3_ILIM_STAT status bit in BUCK_2_3_STAT register.
Masking for Buck2 Power-Good interrupt (BUCK2_PG_INT in INT_BUCK_2_3
register):
0 - Interrupt generated
1 - Interrupt not generated
This bit does not affect BUCK2_PG_STAT status bit in BUCK_2_3_STAT register.
Masking for Buck2 current limit-detection interrupt (BUCK2_ILIM_INT in
INT_BUCK_2_3 register):
0 - Interrupt generated
1 - Interrupt not generated
This bit does not affect BUCK2_ILIM_STAT status bit in BUCK_2_3_STAT register.
7.6.1.33 SEL_I_LOAD
Address: 0x25
Figure 54. SEL_I_LOAD Register
D7
D6
D5
D4
D3
D2
Reserved
54
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D1
D0
LOAD_CURRENT_BUCK
_SELECT[1:0]
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SNVSAW2B – APRIL 2017 – REVISED DECEMBER 2018
Table 42. SEL_I_LOAD Register Field Descriptions
Bits
Field
Type
Default
7:2
Reserved
R/W
0x00
1:0
LOAD_CURRENT_
BUCK_SELECT
[1:0]
R/W
0x0
Copyright © 2017–2018, Texas Instruments Incorporated
Description
Start the current measurement on the selected regulator:
0x0 - Buck0
0x1 - Buck1
0x2 - Buck2
0x3 - Buck3
A single measurement is started when register is written.
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7.6.1.34 I_LOAD_2
Address: 0x26
Figure 55. I_LOAD_2 Register
D7
D6
D5
D4
D3
D2
Reserved
D1
D0
BUCK_LOAD_CURRENT[9:8]
Table 43. I_LOAD_2 Register Field Descriptions
Bits
Field
Type
Default
7:2
Reserved
R
0x00
1:0
BUCK_LOAD_
CURRENT[9:8]
R
0x0
Description
This register describes 3 MSB bits of the average load current on selected regulator
with a resolution of 20 mA per LSB and max code corresponding to 20.47-A current.
7.6.1.35 I_LOAD_1
Address: 0x27
Figure 56. I_LOAD_1 Register
D7
D6
D5
D4
D3
D2
D1
D0
BUCK_LOAD_CURRENT[7:0]
Table 44. I_LOAD_1 Register Field Descriptions
Bits
Field
Type
Default
Description
7:0
BUCK_LOAD_
CURRENT[7:0]
R
0x00
This register describes 8 LSB bits of the average load current on selected regulator
with a resolution of 20 mA per LSB and max code corresponding to a 20.47-A current.
7.6.1.36 PGOOD_CTRL1
Address: 0x28
Figure 57. PGOOD_CTRL1 Register
D7
D6
D5
PG3_SEL[1:0]
D4
PG2_SEL[1:0]
D3
D2
PG1_SEL[1:0]
D1
D0
PG0_SEL[1:0]
Table 45. PGOOD_CTRL1 Register Field Descriptions
Bits
Field
Type
Default
7:6
PG3_SEL[1:0]
R/W
0x1*
PGOOD signal source control from Buck3
0x0 - Masked
0x1 - Power-Good-threshold voltage
0x2 - Reserved, do not use
0x3 - Power-Good-threshold voltage AND current limit
5:4
PG2_SEL[1:0]
R/W
0x1*
PGOOD signal source control from Buck2
0x0 - Masked
0x1 - Power-Good-threshold voltage
0x2 - Reserved, do not use
0x3 - Power-Good threshold voltage AND current limit
3:2
PG1_SEL[1:0]
R/W
0x1*
PGOOD signal source control from Buck1
0x0 - Masked
0x1 - Power-Good-threshold voltage
0x2 - Reserved, do not use
0x3 - Power-Good-threshold voltage AND current limit
1:0
PG0_SEL[1:0]
R/W
0x1*
PGOOD signal source control from Buck0
0x0 - Masked
0x1 - Power-Good-threshold voltage
0x2 - Reserved, do not use
0x3 - Power-Good-threshold voltage AND current limit
56
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7.6.1.37 PGOOD_CTRL2
Address: 0x29
Figure 58. PGOOD_CTRL2 Register
D7
D6
D5
D4
D3
D2
D1
D0
HALF_DELAY
EN_PG0
_NINT
PGOOD_SET
_DELAY
EN_PGFLT
_STAT
Reserved
PGOOD_
WINDOW
PGOOD_OD
PGOOD_POL
Table 46. PGOOD_CTRL2 Register Field Descriptions
Bits
Field
Type
Default
7
HALF_DELAY
R/W
0 for
LP87524B,
LP87524J,
1 for
LP87524P
*
Description
6
EN_PG0_NINT
R/W
0*
Combine Buck0 PGOOD signal to nINT signal:
0 - Buck0 PGOOD signal not included to nINT signal
1 - Buck0 PGOOD signal included to nINT signal. If nINT OR Buck0 PGOOD is low
then nINT signal is low.
5
PGOOD_SET_DEL
AY
R/W
1*
Debounce time of output voltage monitoring for PGOOD signal (only when PGOOD
signal goes valid):
0 - 4-10 µs
1 - 11 ms
4
EN_PGFLT_STAT
R/W
0*
Operation mode for PGOOD signal:
0 - Indicates live status of monitored voltage outputs.
1 - Indicates status of PGOOD_FLT register, inactive if at least one of PGx_FLT bit is
inactive.
3
Reserved
R/W
0
2
PGOOD_WINDOW
R/W
1*
Voltage monitoring method for PGOOD signal:
0 - Only undervoltage monitoring
1 - Overvoltage and undervoltage monitoring
1
PGOOD_OD
R/W
1*
PGOOD signal type:
0 - Push-pull output (VANA level)
1 - Open-drain output
0
PGOOD_POL
R/W
0*
PGOOD signal polarity:
0 - PGOOD signal high when monitored outputs are valid
1 - PGOOD signal low when monitored outputs are valid
Select the time step for start-up and shutdown delays:
0 - Start-up and shutdown delays have 0.5-ms or 1-ms time steps, based on
DOUBLE_DELAY bit in CONFIG register.
1 - Start-up and shutdown delays have 0.32-ms or 0.64-ms time steps, based on
DOUBLE_DELAY bit in CONFIG register.
7.6.1.38 PGOOD_FLT
Address: 0x2A
Figure 59. PGOOD_FLT Register
D7
D6
D5
D4
Reserved
D3
D2
D1
D0
PG3_FLT
PG2_FLT
PG1_FLT
PG0_FLT
Table 47. PGOOD_FLT Register Field Descriptions
Bits
Field
Type
Default
7:4
Reserved
R/W
0x0
3
PG3_FLT
R
0
Source for PGOOD inactive signal:
0 - Buck3 has not set PGOOD signal inactive.
1 - Buck3 has set PGOOD signal inactive. This bit can be cleared by reading this
register when Buck3 output is valid.
2
PG2_FLT
R
0
Source for PGOOD inactive signal:
0 - Buck2 has not set PGOOD signal inactive.
1 - Buck2 has set PGOOD signal inactive. This bit can be cleared by reading this
register when Buck2 output is valid.
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Table 47. PGOOD_FLT Register Field Descriptions (continued)
Bits
Field
Type
Default
1
PG1_FLT
R
0
Source for PGOOD inactive signal:
0 - Buck1 has not set PGOOD signal inactive.
1 - Buck1 has set PGOOD signal inactive. This bit can be cleared by reading this
register when Buck1 output is valid.
Description
0
PG0_FLT
R
0
Source for PGOOD inactive signal:
0 - Buck0 has not set PGOOD signal inactive.
1 - Buck0 has set PGOOD signal inactive. This bit can be cleared by reading this
register when Buck0 output is valid.
7.6.1.39 PLL_CTRL
Address: 0x2B
Figure 60. PLL_CTRL Register
D7
D6
D5
PLL_MODE[1:0]
D4
D3
Reserved
D2
D1
D0
EXT_CLK_FREQ[4:0]
Table 48. PLL_CTRL Register Field Descriptions
Bits
Field
Type
Default
7:6
PLL_MODE[1:0]
R/W
0x2*
5
Reserved
R/W
0
4:0
EXT_CLK_FREQ[4
:0]
R/W
0x01*
Description
Selection of external clock and PLL operation:
0x0 - Forced to internal RC oscillator — PLL disabled.
0x1 - PLL is enabled in STANDBY and ACTIVE modes. Automatic external clock use
when available, interrupt generated if external clock appears or disappears.
0x2 - PLL is enabled only in ACTIVE mode. Automatic external clock use when
available, interrupt generated if external clock appears or disappears.
0x3 - Reserved
Frequency of the external clock (CLKIN):
0x00 - 1 MHz
0x01 - 2 MHz
0x02 - 3 MHz
...
0x16 - 23 MHz
0x17 - 24 MHz
0x18...0x1F - Reserved
See Specifications for input clock frequency tolerance.
7.6.1.40 PIN_FUNCTION
Address: 0x2C
Figure 61. PIN_FUNCTION Register
D7
D6
D5
D4
D3
D2
D1
D0
EN_SPREAD_
SPEC
EN_PIN_CTRL
_GPIO3
EN_PIN_SELE
CT_GPIO3
EN_PIN_CTRL
_GPIO2
EN_PIN_SELE
CT_GPIO2
GPIO3_SEL
GPIO2_SEL
GPIO1_SEL
Table 49. PIN_FUNCTION Register Field Descriptions
Bits
Field
Type
Default
7
EN_SPREAD
_SPEC
R/W
0*
Enable spread-spectrum feature:
0 - Disabled
1 - Enabled
6
EN_PIN_CTRL_GP
IO3
R/W
1*
Enable EN1/2 pin control for GPIO3 (GPIO3_SEL=1 AND GPIO3_DIR=1):
0 - Only GPIO3_OUT bit controls GPIO3.
1 - GPIO3_OUT bit AND ENx pin control GPIO3
5
EN_PIN_SELECT_
GPIO3
R/W
0*
Enable EN1/2 pin control for GPIO3:
0 - GPIO3_SEL bit AND EN1 pin control GPIO3
1 - GPIO3_SEL bit AND EN2 pin control GPIO3
58
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SNVSAW2B – APRIL 2017 – REVISED DECEMBER 2018
Table 49. PIN_FUNCTION Register Field Descriptions (continued)
Bits
Field
Type
Default
4
EN_PIN_CTRL_GP
IO2
R/W
1*
Enable EN1/3 pin control for GPIO2 (GPIO2_SEL=1 AND GPIO2_DIR=1):
0 - Only GPIO2_OUT bit controls GPIO2.
1 - GPIO2_OUT bit AND ENx pin control GPIO2
Description
3
EN_PIN_SELECT_
GPIO2
R/W
0*
Enable EN1/3 pin control for GPIO2:
0 - GPIO2_SEL bit AND EN1 pin control GPIO2
1 - GPIO2_SEL bit AND EN3 pin control GPIO2
2
GPIO3_SEL
R/W
1*
EN3 pin function:
0 - EN3
1 - GPIO3
1
GPIO2_SEL
R/W
1*
EN2 pin function:
0 - EN2
1 - GPIO2
0
GPIO1_SEL
R/W
0*
EN1 pin function:
0 - EN1
1 - GPIO1
7.6.1.41 GPIO_CONFIG
Address: 0x2D
Figure 62. GPIO_CONFIG Register
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
GPIO3_OD
GPIO2_OD
GPIO1_OD
Reserved
GPIO3_DIR
GPIO2_DIR
GPIO1_DIR
Table 50. GPIO_CONFIG Register Field Descriptions
Bits
Field
Type
Default
Description
7
Reserved
R
0
6
GPIO3_OD
R/W
1*
GPIO3 signal type when configured to output:
0 - Push-pull output (VANA level)
1 - Open-drain output
5
GPIO2_OD
R/W
1*
GPIO2 signal type when configured to output:
0 - Push-pull output (VANA level)
1 - Open-drain output
4
GPIO1_OD
R/W
0*
GPIO1 signal type when configured to output:
0 - Push-pull output (VANA level)
1 - Open-drain output
3
Reserved
R
0
2
GPIO3_DIR
R/W
1*
GPIO3 signal direction:
0 - Input
1 - Output
1
GPIO2_DIR
R/W
1*
GPIO2 signal direction:
0 - Input
1 - Output
0
GPIO1_DIR
R/W
0*
GPIO1 signal direction:
0 - Input
1 - Output
7.6.1.42 GPIO_IN
Address: 0x2E
Figure 63. GPIO_IN Register
D7
D6
D5
Reserved
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D4
D3
D2
D1
D0
GPIO3_IN
GPIO2_IN
GPIO1_IN
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Table 51. GPIO_IN Register Field Descriptions
Bits
Field
Type
Default
7:3
Reserved
R
0x00
Description
2
GPIO3_IN
R
0
State of GPIO3 signal:
0 - Logic low level
1 - Logic high level
1
GPIO2_IN
R
0
State of GPIO2 signal:
0 - Logic low level
1 - Logic high level
0
GPIO1_IN
R
0
State of GPIO1 signal:
0 - Logic low level
1 - Logic high level
7.6.1.43 GPIO_OUT
Address: 0x2F
Figure 64. GPIO_OUT Register
D7
D6
D5
D4
Reserved
D3
D2
D1
D0
GPIO3_OUT
GPIO2_OUT
GPIO1_OUT
Table 52. GPIO_OUT Register Field Descriptions
Bits
Field
Type
Default
7:3
Reserved
R/W
0x00
2
GPIO3_OUT
R/W
1*
Control for GPIO3 signal when configured to GPIO Output:
0 - Logic low level
1 - Logic high level
1
GPIO2_OUT
R/W
1*
Control for GPIO2 signal when configured to GPIO Output:
0 - Logic low level
1 - Logic high level
0
GPIO1_OUT
R/W
0
Control for GPIO1 signal when configured to GPIO Output:
0 - Logic low level
1 - Logic high level
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Description
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LP87524B/J/P-Q1 is a multi-phase step-down converter with four switcher cores, which are configured to
four one-phase regulators configuration.
8.2 Typical Application
R0
VIN
VIN_B0
CIN0 CIN1 CIN2 CIN3
VIN_B1
SW_B0
FB_B0
C0
COUT0
VIN_B2
CVANA
CPOL0
LOAD
R1
VIN_B3
VANA
VOUT0
L0
SW_B1
FB_B1
C1
L1
VOUT1
COUT1
CPOL1
LOAD
R2
NRST
SDA
SCL
nINT
CLKIN
PGOOD
EN1 (GPIO1)
EN2 (GPIO2)
EN3 (GPIO3)
SW_B2
FB_B2
L2
C2
VOUT2
COUT2
CPOL2
LOAD
R3
SW_B3
FB_B3
C3
L3
VOUT3
COUT3
CPOL3
LOAD
GNDs
Copyright © 2017, Texas Instruments Incorporated
Figure 65. Four 1-Phase Configuration
8.2.1 Design Requirements
8.2.1.1 Inductor Selection
The inductors are L0, L1, L2, and L3 are shown in the Typical Application. The inductance and DCR of the
inductor affects the control loop of the buck regulator. TI recommends using inductors similar to those listed in
Table 53. Pay attention to the saturation current and temperature rise current of the inductor. Check that the
saturation current is higher than the peak current limit and the temperature rise current is higher than the
maximum expected rms output current. Minimum effective inductance to ensure good performance is 0.22 μH at
maximum peak output current over the operating temperature range. DC resistance of the inductor must be less
than 0.05 Ω for good efficiency at high-current condition. The inductor AC loss (resistance) also affects
conversion efficiency. Higher Q factor at switching frequency usually gives better efficiency at light load to middle
load. Shielded inductors are preferred as they radiate less noise.
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Typical Application (continued)
Table 53. Recommended Inductors
MANUFACTURER
PART NUMBER
VALUE
DIMENSIONS
L × W × H (mm)
RATED DC CURRENT,
ISAT maximum (typical) / ITEMP
maximum (typical) (A)
DCR typical /
maximum
(mΩ)
TOKO
DFE252012PD-R47M
0.47 µH (20%)
2.5 × 2 × 1.2
5.2 (–) / 4 (–) (1)
- / 27
Vishay
(1)
IHLP1616AB-1A
0.47 µH (20%)
4.1 × 4.5 × 1.2
– (6 ) / – (6 )
(1)
19 / 21
Operating temperature range is up to 125°C including self temperature rise.
8.2.1.2 Input Capacitor Selection
The input capacitors CIN0, CIN1, CIN2, and CIN3 are shown in the Typical Application. A ceramic input bypass
capacitor of 10 μF is required for each phase of the regulator. Place the input capacitor as close as possible to
the VIN_Bx pin and PGND_Bx pin of the device. A larger value or higher voltage rating improves the input
voltage filtering. Use X7R type of capacitors, not Y5V or F. DC bias characteristics capacitors must be
considered, minimum effective input capacitance to ensure good performance is 1.9 μF per buck input at
maximum input voltage including tolerances and ambient temperature range, assuming that there are at least 22
μF of additional capacitance common for all the power input pins on the system power rail. See Table 54.
The input filter capacitor supplies current to the high-side FET switch in the first half of each cycle and reduces
voltage ripple imposed on the input power source. A ceramic capacitor's low ESR provides the best noise filtering
of the input voltage spikes due to this rapidly changing current. Select an input filter capacitor with sufficient
ripple current rating. In addition ferrite can be used in front of the input capacitor to reduce the EMI.
Table 54. Recommended Input Capacitors (X7R Dielectric)
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
DIMENSIONS L × W × H
(mm)
VOLTAGE
RATING (V)
Murata
GCM21BR71A106KE22
10 µF (10%)
0805
2 × 1.25 × 1.25
10 V
8.2.1.3 Output Capacitor Selection
The output capacitors COUT0, COUT1, COUT2, and COUT3 are shown in Typical Application. A ceramic local output
capacitor of 22 μF is required per phase. Use ceramic capacitors, X7R or X7T types; do not use Y5V or F. DC
bias voltage characteristics of ceramic capacitors must be considered. The output filter capacitor smooths out
current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes
and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently
low ESR and ESL to perform these functions. Minimum effective output capacitance to ensure good performance
is 10 μF per phase including the DC voltage roll-off, tolerances, aging and temperature effects.
The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its
RESR. The RESR is frequency dependent (as well as temperature dependent); make sure the value used for
selection process is at the switching frequency of the part. See Table 55.
POL capacitors (CPOL0, CPOL1, CPOL2, CPOL3) can be used to improve load transient performance and to decrease
the ripple voltage. A higher output capacitance improves the load step behavior and reduces the output voltage
ripple as well as decreases the PFM switching frequency. However, output capacitance higher than 100 µF per
phase is not necessarily of any benefit. Note that the output capacitor may be the limiting factor in the output
voltage ramp and the maximum total output capacitance listed in electrical characteristics must not be exceeded.
At shutdown the output voltage is discharged to 0.6 V level using forced-PWM operation. This can increase the
input voltage if the load current is small and the output capacitor is large. Below 0.6 V level the output capacitor
is discharged by the internal discharge resistor and with large capacitor more time is required to settle VOUT down
as a consequence of the increased time constant.
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Table 55. Recommended Output Capacitors (X7R or X7T Dielectric)
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
DIMENSIONS L × W × H
(mm)
VOLTAGE
RATING (V)
Murata
GCM31CR71A226KE02
22 µF (10%)
1206
3.2 × 1.6 × 1.6
10
8.2.1.4 Snubber Components
If the input voltage for the regulators is above 4 V, snubber components are needed at the switching nodes to
decrease voltage spiking in the switching node and to improve EMI. The snubber capacitors C0, C1, C2, and C3
and the snubber resistors R0, R1, R2, and R3 are shown in Figure 65. The recommended components are shown
in Table 56 and these component values give good performance on LP87524B/J/P-Q1 EVM. The optimal
resistance and capacitance values finally depend on the PCB layout.
Table 56. Recommended Snubber Components
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
DIMENSIONS L × W x
H (mm)
VOLTAGE /
POWER RATING
Vishay-Dale
CRCW04023R90JNED
3.9 Ω (5%)
0402
1 × 0.5 × 0.4
62 mW
Murata
GCM1555C1H391JA16
390 pF (5%)
0402
1 × 0.5 × 0.5
50 V
8.2.1.5 Supply Filtering Components
The VANA input is used to supply analog and digital circuits in the device. See Table 57 for recommended
components for VANA input supply filtering.
Table 57. Recommended Supply Filtering Components
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
DIMENSIONS L × W ×
H (mm)
VOLTAGE RATING
(V)
Murata
GCM155R71C104KA55
100 nF (10%)
0402
1.0 × 0.5 × 0.5
16
Murata
GCM188R71C104KA37
100 nF (10%)
0603
1.6 × 0.8 × 0.8
16
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8.2.2 Current Limit vs. Maximum Output Current
The worst case inductor current ripple can be calculated using Equation 1 and Equation 2:
VOUT
D
VIN(max) u K
'IL
(VIN(max)
(1)
VOUT ) u D
fSW u L
(2)
Example using Equation 1 and Equation 2:
VIN(max) = 5.5 V
VOUT(max) = 1 V
η(min) = 0.75
fSW(min) = 1.8 MHz
L(min) = 0.38 µH
then D(max) = 0.242 and ΔIL(max) = 1.59 A
Peak current is half of the current ripple. If ILIM_FWD_SET_OTP is 4 A, the minimum forward current limit would be 3.8
A when VIN ≥ 3 V and when taking the tolerance into account. In the worst case situation difference between set
peak current and maximum load current = 0.795 A + 0.2 A = 0.995 A.
Inductor current =
Forward current
ILIM_FWD_MAX (+20%)
ILIM_FWD_TYP (+7.5%)
ILIM_FWD_SET_OTP (1.5...5 A, 0.5-A step)
ILIM_FWD_MIN (-5%)
Minimum 1A guard band
to take current ripple,
inductor inductance
variation into account
IL_AVG = IOUT
1 / fSW
IOUT_MAX < ILIM_FWD_SET_OTP ± 1 A
Figure 66. Current Limit vs Maximum Output Current
8.2.3 Detailed Design Procedure
The performance of the LP87524B/J/P-Q1 device depends greatly on the care taken in designing the printed
circuit board (PCB). The use of low-inductance and low serial-resistance ceramic capacitors is strongly
recommended, while proper grounding is crucial. Attention must be given to decoupling the power supplies.
Decoupling capacitors must be connected close to the device and between the power and ground pins to support
high peak currents being drawn from system power rail during turnon of the switching MOSFETs. Keep input and
output traces as short as possible, because trace inductance, resistance, and capacitance can easily become the
performance limiting items. The separate power pins VIN_Bx are not connected together internally. Connect the
VIN_Bx power connections together outside the package using power plane construction.
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8.2.4 Application Curves
Measurements are done using typical application set up with connections shown in Figure 65 (snubber
components included when VIN > 4 V). Graphs may not reflect the OTP default settings. Unless otherwise
specified: VIN = 3.7 V, VOUT = 1 V, V(NRST) = 1.8 V, TA = 25°C, ƒSW = 4 MHz, L = 0.47 µH (TOKO DFE252012PDR47M), COUT = 22 µF / phase, and CPOL = 22 µF / phase. Measurements are done using connections in the
Typical Application.
100
100
90
80
Efficiency (%)
Efficiency (%)
90
70
60
1PH, VIN=3.3V, AUTO
1PH, VIN=3.3V, FPWM
1PH, VIN=5.0V, AUTO
1PH, VIN=5.0V, FPWM
50
40
0.001
0.01
0.1
Output Current (A)
1
80
70
60
1PH, VOUT=1.0V, FPWM
1PH, VOUT=1.8V, FPWM
1PH, VOUT=2.5V, FPWM
50
0.01
5
0.1
Output Current (A)
D923
VOUT = 1.8 V
1
5
D924
VIN = 3.3 V
Figure 67. Efficiency in PFM/PWM Mode
Figure 68. Efficiency in Forced-PWM Mode
100
1.02
1.016
1.012
1.008
Output Voltage (V)
Efficiency (%)
90
80
70
60
1.004
1
0.996
0.992
0.988
1PH, VOUT=1.0V, FPWM
1PH, VOUT=1.8V, FPWM
1PH, VOUT=2.5V, FPWM
50
40
0.01
0.1
Output Current (A)
1
1PH, Vin=3.3V, FPWM
1PH, Vin=5.0V, FPWM
0.984
0.98
5
0
0.5
D925
1
1.5
2
2.5
Output Current (A)
3
3.5
D026
VIN = 5 V
Figure 70. Output Voltage vs Load Current in Forced-PWM
Mode
1.02
1.02
1.016
1.016
1.012
1.012
1.008
1.008
Output Voltage (V)
Output Voltage (V)
Figure 69. Efficiency in Forced-PWM Mode
1.004
1
0.996
0.992
1.004
1
0.996
0.992
1PH, BUCK0
1PH, BUCK1
1PH, BUCK2
1PH, BUCK3
0.988
0.988
0.984
1PH, Vin=3.3V, AUTO
1PH, Vin=5.0V, AUTO
0.984
0.98
0
0.2
0.4
0.6
Output Current (A)
0.8
1
D027
Figure 71. Output Voltage vs Load Current in PFM/PWM
Mode
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4
0.98
2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6
Input Voltage (V)
D028
VOUT = 1 V
Load = 1 A
Figure 72. Output Voltage vs Input Voltage in PWM Mode
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1.02
1.016
Output Voltage (V)
1.012
1.008
VOUT(200mV/div)
V(EN1)(500mV/div)
1.004
1
0.996
0.992
0.988
1PH, PWM
1PH, PFM
0.984
0.98
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
Load = 1 A (PWM) and 0.1 A (PFM)
V(SW)(2V/div)
140
D036
Time (100 µs/div)
IOUT = 0 A
Figure 73. Output Voltage vs Temperature
Figure 74. Start-Up With EN1, Forced PWM
VOUT(200mV/div)
V(EN1)(500mV/div)
VOUT(200mV/div)
V(EN1)(500m/div)
ILOAD(500mA/div)
ILOAD(500mA/div)
V(SW)(2V/div)
V(SW)(2V/div)
Time (100 µs/div)
Time (100 µs/div)
RLOAD = 1 Ω
RLOAD = 1 Ω
Figure 75. Start-Up With EN1, Forced PWM
(1-Phase Output)
Figure 76. Shutdown With EN1, Forced PWM
(1-Phase Output)
VOUT(10mV/div)
VOUT(10mV/div)
V(SW_B0)(1V/div)
V(SW_B0)(2V/div)
Time (100 ns/div)
Time (40 µs/div)
IOUT = 10 mA
IOUT = 200 mA
Figure 77. Output Voltage Ripple, PFM Mode
(1-Phase Output)
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Figure 78. Output Voltage Ripple, Forced-PWM Mode
(1-Phase Output)
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10000
Voltage (nV)
1000
VOUT(10mV/div)
100
10
VIN = 3.3V 4MHz
VIN = 5V 4MHz
1
0.1
1
Frequency (MHz)
VOUT = 1 V
No load
10
D300
V(SW_B0)(1V/div)
Time (2 µs/div)
RBW/VBW = 10 Hz
Figure 79. Output Voltage Ripple Spectrum, Forced-PWM
Mode. COUT = 22 µF, ferrite BLM18KG121TH1D, CPOL = 10
µF + 0.22 µF.
VOUT(10mV/div)
Figure 80. Transient from PFM-to-PWM Mode
(1-Phase Output)
VOUT(20mV/div)
I(LOAD(1A/div)
V(SW_B0)(1V/div)
Time (2 µs/div)
Time (40 µs/div)
IOUT = 0.1 A → 2 A → 0.1 A
Figure 81. Transient from PWM-to-PFM Mode
(1-Phase Output)
VOUT(20mV/div)
TR = TF = 1 µs
Figure 82. Transient Load Step Response, AUTO Mode
(1-Phase Output)
VOUT(200mV/div)
I(LOAD(1A/div)
Time (20 µs/div)
Time (40 µs/div)
IOUT = 0.1 A → 2 A → 0.1
A
TR = TF = 1 µs
Figure 84. VOUT Transition from 0.6 V to 1.4 V
Figure 83. Transient Load Step Response, Forced-PWM
Mode (1-Phase Output)
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V(EN1)(1V/div)
VOUT(200mV/div)
V(nINT)(1V/div)
VOUT(50mV/div)
IOUT(2A/div)
Time (20 µs/div)
Figure 85. VOUT Transition from 1.4 V to 0.6 V
Time (200 µs/div)
Figure 86. Start-up With Short on Output (1-Phase Output)
9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range from 2.8 V and 5.5 V. This input supply
must be well regulated and able to withstand maximum input current and maintain stable voltage without voltage
drop even at load transition condition. The resistance of the input supply rail must be low enough that the input
current transient does not cause too high drop in the LP87524B/J/P-Q1 supply voltage that can cause false
UVLO fault triggering. If the input supply is located more than a few inches from the LP87524B/J/P-Q1 additional
bulk capacitance may be required in addition to the ceramic bypass capacitors.
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10 Layout
10.1 Layout Guidelines
The high frequency and large switching currents of the LP87524B/J/P-Q1 make the choice of layout important.
Good power supply results only occur when care is given to proper design and layout. Layout affects noise
pickup and generation and can cause a good design to perform with less-than-expected results. With a range of
output currents from milliamps to 10 A, good power supply layout is much more difficult than most general PCB
design. Use the following steps as a reference to ensure the device is stable and maintains proper voltage and
current regulation across its intended operating voltage and current range.
1. Place CIN as close as possible to the VIN_Bx pin and the PGND_Bxx pin. Route the VIN trace wide and thick
to avoid IR drops. The trace between the positive node of the input capacitor and the VIN_Bx pin(s) of
LP87524B/J/P-Q1, as well as the trace between the negative node of the input capacitor and power
PGND_Bxx pin(s), must be kept as short as possible. The input capacitance provides a low-impedance
voltage source for the switching converter. The inductance of the connection is the most important parameter
of a local decoupling capacitor — parasitic inductance on these traces must be kept as small as possible for
proper device operation. The parasitic inductance can be reduced by using a ground plane as close as
possible to top layer by using thin dielectric layer between top layer and ground plane.
2. The output filter, consisting of COUT and L, converts the switching signal at SW_Bx to the noiseless output
voltage. It must be placed as close as possible to the device keeping the switch node small, for best EMI
behavior. Route the traces between the LP87524B/J/P-Q1 output capacitors and the load direct and wide to
avoid losses due to the IR drop.
3. Input for analog blocks (VANA and AGND) must be isolated from noisy signals. Connect VANA directly to a
quiet system voltage node and AGND to a quiet ground point where no IR drop occurs. Place the decoupling
capacitor as close as possible to the VANA pin.
4. If the processor load supports remote voltage sensing, connect the feedback pins FB_Bx of the
LP87524B/J/P-Q1 device to the respective sense pins on the processor. The sense lines are susceptible to
noise. They must be kept away from noisy signals such as PGND_Bxx, VIN_Bx, and SW_Bx, as well as high
bandwidth signals such as the I2C. Avoid both capacitive and inductive coupling by keeping the sense lines
short, direct, and close to each other. Run the lines in a quiet layer. Isolate them from noisy signals by a
voltage or ground plane if possible. If series resistors are used for load current measurement, place them
after connection of the voltage feedback.
5. PGND_Bxx, VIN_Bx and SW_Bx must be routed on thick layers. They must not surround inner signal layers,
which are not able to withstand interference from noisy PGND_Bxx, VIN_Bx and SW_Bx.
6. If the input voltage is above 4 V, place snubber components (capacitor and resistor) between SW_Bx and
ground on all four phases. The components can be also placed to the other side of the board if there are
area limitations and the routing traces can be kept short.
Due to the small package of this converter and the overall small solution size, the thermal performance of the
PCB layout is important. Many system-dependent parameters such as thermal coupling, airflow, added heat
sinks and convection surfaces, and the presence of other heat-generating components affect the power
dissipation limits of a given component. Proper PCB layout, focusing on thermal performance, results in lower die
temperatures. Wide and thick power traces come with the ability to sink dissipated heat. This can be improved
further on multi-layer PCB designs with vias to different planes. This results in reduced junction-to-ambient (RθJA)
and junction-to-board (RθJB) thermal resistances and thereby reduces the device junction temperature, TJ. TI
strongly recommends to perform of a careful system-level 2D or full 3D dynamic thermal analysis at the
beginning product design process, by using a thermal modeling analysis software.
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SNVSAW2B – APRIL 2017 – REVISED DECEMBER 2018
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10.2 Layout Example
Via to GND plane
Via to VIN plane
VOUT1
VOUT0
L1
L0
COUT0
COUT1
CIN1
CIN0
GND
VIN
VIN
VIN
19
nINT
20
NRST
21
FB_B3
SW_B0
VANA
VIN_B0
18
SW_B1
AGND
PGND_B01
17
AGND
GND
VIN_B2
CIN5
PGOOD
SW_B2
VIN
16
PGND_B23
CVANA
EN2
SW_B3
GND
FB_B1
15
VIN_B3
GND
14
VIN_B1
13 12 11 10 9
CIN4
FB_B0
8
EN1
7
SDA
6
SCL
5
AGND
4
CLKIN
3
EN3
2
FB_B2
1
GND
22 23 24 25 26
VIN
VIN
VIN
CIN3
CIN2
GND
L3
COUT3
COUT2
L2
VOUT3
VOUT2
Figure 87. LP87524B/J/P-Q1 Board Layout
The output voltage rails are shorted together based on the configuration as shown in Typical Application.
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LP87524B-Q1
LP87524J-Q1, LP87524P-Q1
www.ti.com
SNVSAW2B – APRIL 2017 – REVISED DECEMBER 2018
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 58. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LP87524B-Q1
Click here
Click here
Click here
Click here
Click here
LP87524J-Q1
Click here
Click here
Click here
Click here
Click here
LP87524P-Q1
Click here
Click here
Click here
Click here
Click here
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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SNVSAW2B – APRIL 2017 – REVISED DECEMBER 2018
www.ti.com
PACKAGE OUTLINE
RNF0026C
VQFN-HR - 0.9 mm max height
SCALE 2.800
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
B
A
PIN 1 INDEX AREA
4.6
4.4
0.1 MIN
(0.05)
SECTION A-A
A-A 25.000
TYPICAL
C
0.9 MAX
SEATING PLANE
0.05
0.00
0.08 C
2X 2
10X
0.3
0.2
8X 0.5
4X (0.35)
4X (0.575)
4X (0.625)
14
8
10X
7
A
2X
2.5
SYMM
10X 0.5
0.66 0.1
12X
21
1
26
SYMM
THERMAL PAD
1.72
1.52
A
27
PIN 1 ID
(0.2) TYP
4X (0.4)
13
9
22
12X
2.24 0.1
0.3
0.2
0.1
0.05
C A B
C
0.5
0.3
4223207/B 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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LP87524B-Q1
LP87524J-Q1, LP87524P-Q1
www.ti.com
SNVSAW2B – APRIL 2017 – REVISED DECEMBER 2018
EXAMPLE BOARD LAYOUT
RNF0026C
VQFN-HR - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
8X (0.5)
10X (0.25)
12X (0.6)
22
26
1
21
10X (1.82)
12X (0.25)
SYMM
(3.08)
27
(0.66)
2X (3.65)
10X (0.5)
( 0.2) TYP
VIA
4X (0.4)
8
14
4X (0.825)
13
9
(R0.05)
TYP
4X (0.35)
(0.87)
4X (0.775)
(2.24)
2X (3.2)
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.05 MAX
ALL AROUND
EXPOSED
METAL
0.05 MIN
ALL AROUND
EXPOSED
METAL
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAIL
NOT TO SCALE
4223207/B 04/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RNF0026C
VQFN-HR - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.575) TYP
10X
EXPOSED METAL
12X (0.6)
SYMM
(0.5)
TYP
26
22
21
1
12X (0.25)
(1.01) TYP
(1.775)
TYP
(1.035) TYP
10X (0.5)
27
2X (0.98)
SYMM
2X (0.66)
(0.59)
(R0.05) TYP
EXPOSED METAL
4X (0.3)
4X (0.825)
8
14
20X (0.81)
13
9
4X (0.3)
20X (0.25)
4X (0.775)
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PADS 1, 8, 14 & 21: 87% - PADS 9-13 & 22-26: 88% - THERMAL PAD 27: 87%
SCALE:25X
4223207/B 04/2018
NOTES: (continued)
6. For alternate stencil design recommendations, see IPC-7525 or board assembly site preference.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LP87524BRNFRQ1
ACTIVE
VQFN-HR
RNF
26
3000
RoHS-Exempt
& Green
SN
Level-1-260C-UNLIM
-40 to 125
LP8752
4B-Q1
LP87524BRNFTQ1
ACTIVE
VQFN-HR
RNF
26
250
RoHS-Exempt
& Green
SN
Level-1-260C-UNLIM
-40 to 125
LP8752
4B-Q1
LP87524JRNFRQ1
ACTIVE
VQFN-HR
RNF
26
3000
RoHS-Exempt
& Green
SN
Level-1-260C-UNLIM
-40 to 125
LP8752
4J-Q1
LP87524JRNFTQ1
ACTIVE
VQFN-HR
RNF
26
250
RoHS-Exempt
& Green
SN
Level-1-260C-UNLIM
-40 to 125
LP8752
4J-Q1
LP87524PRNFRQ1
ACTIVE
VQFN-HR
RNF
26
3000
RoHS-Exempt
& Green
SN
Level-1-260C-UNLIM
-40 to 125
LP8752
4P-Q1
LP87524PRNFTQ1
ACTIVE
VQFN-HR
RNF
26
250
RoHS-Exempt
& Green
SN
Level-1-260C-UNLIM
-40 to 125
LP8752
4P-Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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