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LP8755
SNVSA20A – NOVEMBER 2013 – REVISED FEBRUARY 2015
LP8755 Multi-Phase Six-Core Step-Down Converter
Check for Samples: LP8755
1 Features
3 Description
•
The LP8755 is designed to meet the power
management requirements of the latest applications
processors in mobile phones and similar portable
applications. The device contains six step-down DCDC converter cores, which are bundled together in a
6-phase buck converter. The device is fully controlled
by a SmartReflex™-compatible (DVS) interface or an
I2C-compatible serial interface.
1
•
•
•
•
•
•
•
Six High-Efficiency Step-Down DC-DC Converter
Cores:
– Max Output Current 15 A
– Cores Bundled to a 6-Phase Converter
– Load Current Reporting
– Programmable Overcurrent Protection (OCP)
– Auto PWM/PFM and Forced-PWM Operations
and Automatic Low Power-Mode Setting
– Automatic Phase Adding/Shedding
– Remote Differential Feedback Voltage Sensing
– Output Voltage Ramp Control
– VOUT Range = 0.6 V to 1.67 V
I2C-Compatible Interface which Supports Standard
(100 kHz), Fast (400 kHz), and High-Speed (3.4
MHz) Modes
Four Selectable I2C Addresses
Interrupt Function with Programmable Masking
Output Short-Circuit and Input Overvoltage
Protection (OVP)
Spread Spectrum and Phase Control for EMI
Reduction
Overtemperature Protection (OTP)
Undervoltage Lockout (UVLO)
2 Applications
•
•
•
Smart Phones, eBooks and Tablets
GSM, GPRS, EDGE, LTE, CDMA and WCDMA
Handsets
Gaming Devices
The automatic PWM/PFM operation together with the
automatic
phase
adding/shedding
maximizes
efficiency over a wide output current range. The
LP8755 supports remote differential voltage sensing
to compensate IR drop between the regulator output
and the point-of-load thus improving the accuracy of
the output voltage.
The protection features include short-circuit
protection, current limits, input OVP, UVLO,
temperature warning, and shutdown functions.
Several error flags are provided for status information
of the IC. In addition, I2C read-back includes total
load current and load current for each buck core: The
LP8755 has the ability to sense current being
delivered to the load without the addition of current
sense resistors. During start-up, the device controls
the output voltage slew rate to minimize overshoot
and the inrush current.
Device Information(1)
PART NUMBER
LP8755
PACKAGE
DSBGA (49)
BODY SIZE (MAX)
3.022 mm x 2.882 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Efficiency vs. Load Current
100
EFFICIENCY (%)
90
80
70
1650 mV
1400 mV
1150 mV
900 mV
650 mV
VIN = 3.8V
fSW = 4.0MHz
Inductor: TOKO
DFE252012C 470nH
60
50
0
2500
5000
7500
10000
12500
15000
OUTPUT CURRENT (mA)
C001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP8755
SNVSA20A – NOVEMBER 2013 – REVISED FEBRUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
7
1
1
1
2
3
5
Absolute Maximum Ratings ..................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions ...................... 5
Thermal Information .................................................. 6
General Electrical Characteristics............................. 7
6-Phase Buck Electrical Characteristics ................... 8
6-Phase Buck System Characteristics...................... 9
Protection Features Characteristics........................ 11
I2C Serial Bus Timing Parameters .......................... 12
Typical Characteristics ......................................... 14
Detailed Description ............................................ 15
7.1 Overview ................................................................. 15
7.2 Functional Block Diagram ....................................... 16
7.3
7.4
7.5
7.6
8
Features Descriptions .............................................
Device Functional Modes........................................
Programming ..........................................................
Register Maps .........................................................
16
25
27
29
Application and Implementation ........................ 38
8.1 Application Information............................................ 38
8.2 Typical Application .................................................. 38
9 Power Supply Recommendations...................... 47
10 Layout................................................................... 47
10.1 Layout Guidelines ................................................. 47
10.2 Layout Example .................................................... 48
11 Device and Documentation Support ................. 49
11.1
11.2
11.3
11.4
11.5
Device Support......................................................
Documentation Support .......................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
49
49
49
49
49
12 Mechanical, Packaging, and Orderable
Information ........................................................... 49
4 Revision History
Changes from Original (November 2013) to Revision A
•
2
Page
Changed formatting to match new TI datasheet guidelines; added Device Information and ESD Ratings tables,
Power Supply Recommendations, Layout, and Device and Documentation Support sections; moved some curves to
Application Curves section, reformatted Detailed Description and Application and Implementation sections, adding
additional content. ................................................................................................................................................................. 1
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SNVSA20A – NOVEMBER 2013 – REVISED FEBRUARY 2015
5 Pin Configuration and Functions
DSBGA (YFQ)
49 Pins
Top View
7
GND
B0
GND
B0
VLDO
GNDA
VIO
SYS
GND
B3
GND
B3
6
SW
B0
SW
B0
NSLP
FB
B0+/B0
INT
SW
B3
SW
B3
5
VIN
B0/B1
VIN
B0/B1
VIN
B0/B1
FB
B0-/B1
VIN
B3/B4
VIN
B3/B4
VIN
B3/B4
4
SW
B1
SW
B1
ADDR
FB
B2
NRST
SW
B4
SW
B4
3
GND
B1/B2
GND
B1/B2
GND
B1/B2
FB
B3+/B3
GND
B4/B5
GND
B4/B5
GND
B4/B5
2
SW
B2
SW
B2
SCL
SYS
FB
B3-/B4
SCL
SR
SW
B5
SW
B5
1
VIN
B2
VIN
B2
SDA
SYS
FB
B5
SDA
SR
VDDA
5V
VIN
B5
A
B
C
BUCK0
BUCK1
BUCK3
BUCK2
BUCK4
BUCK5
D
E
F
G
Pin Functions
PIN
TYPE
DESCRIPTION
NUMBER
NAME
A1, B1
VINB2
P
Input for Buck 2. The separate power pins VINBXX are not connected together internally VINBXX pins must be connected together in the application and be locally bypassed.
A2, B2
SWB2
A
Buck 2 switch node
A3, B3, C3
GNDB1/B2
G
Power Ground for Buck 1 and Buck 2
A4, B4
SWB1
A
Buck 1 switch node
A5, B5, C5
VINB0/B1
P
Input for Buck 0 and Buck 1. The separate power pins VINBXX are not connected together
internally - VINBXX pins must be connected together in the application and be locally bypassed.
A6, B6
SWB0
A
Buck 0 switch node
A7, B7
GNDB0
G
Power Ground for Buck 0
C1
SDASYS
D/I/O
C2
SCLSYS
D/I
Serial interface clock input for system access. Connect a pullup resistor.
C4
ADDR
D/I
Serial bus address selection. Connect to GND (addr = 60h), VIOSYS (addr = 61h), SDASYS
(addr = 62h) or SCLSYS (addr = 63h).
C6
NSLP
D/I
Full Power to Low Power state transition control signal (By default active LOW for Low-Power
PFM mode)
C7
VLDO
A
Internal supply voltage capacitor pin. A ceramic low ESR 1-µF capacitor should be connected
from this pin to GNDA. The LDO voltage is generated internally, do NOT supply or load this pin
externally.
D1
FBB5
A
Not used for six-phase converter. Connect to GND.
D2
FBB3−/B4
A
Not used for six-phase converter. Connect to GND.
D3
FBB3+/B3
A
Not used for six-phase converter. Connect to GND.
D4
FBB2
A
Not used for six-phase converter. Connect to GND.
Serial interface data input and output for system access. Connect a pullup resistor.
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Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NUMBER
NAME
D5
FBB0−/B1
A
Remote sensing (negative). Connect to the respective sense pin of the processor or to the
negative power supply trace of the processor as close as possible to the processor.
D6
FBB0+/B0
A
Remote sensing (positive). Connect to the respective sense pin of the processor or to the
positive power supply trace of the processor as close as possible to the processor.
D7
GNDA
G
Ground
E1
SDASR
D/I/O
Serial Interface data input and output for Dynamic Voltage Scaling (DVS). Connect a pullup
resistor / connect to GND if not used.
E2
SCLSR
D/I
Serial Interface clock input for DVS. Connect a pullup resistor / connect to GND if not used.
E3, F3, G3
GNDB4/B5
G
Power Ground for Buck 4 and Buck 5
E4
NRST
A
Voltage reference input for DVS interface. Setting NRST input HIGH triggers start-up sequence.
E5, F5, G5
VINB3/B4
P
Input for Buck 3 and Buck 4.The separate power pins VINBXX are not connected together
internally - VINBXX pins must be connected together in the application and be locally bypassed.
E6
INT
D/O
Open-drain interrupt output. Active LOW. Connect a pullup resistor to I/O supply.
E7
VIOSYS
A
This pin shall be tied to the system I/O-voltage. Bias supply voltage for the device. Enables the
I/O interface: All registers are accessible via serial bus interface when this pin is pulled high. An
internal power-on reset (POR) occurs when VIOSYS is toggled low/high. The I2C host should
allow at least 500 µs before sending data to the LP8755 after the rising edge of the VIOSYS line.
F1
VDDA5V
P
Input for Analog blocks
F2, G2
SWB5
A
Buck 5 switch node
F4, G4
SWB4
A
Buck 4 switch node
F6, G6
SWB3
A
Buck 3 switch node
F7, G7
GNDB3
G
Power Ground for Buck 3
G1
VINB5
P
Input for Buck 5. The separate power pins VINBXX are not connected together internally VINBXX pins must be connected together in the application and be locally bypassed.
A: Analog Pin, D: Digital Pin, G: Ground Pin, P: Power Pin, I: Input Pin, O: Output Pin
4
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SNVSA20A – NOVEMBER 2013 – REVISED FEBRUARY 2015
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
Voltage on power connections (VIOSYS, VDDA5V, VINBXX)
−0.3
6
Voltage on logic pins (input or output pins) (SCLSYS, SDASYS, NRST,
NSLP, ADDR, INT, SCLSR, SDASR)
−0.3
6
V
Buck switch nodes (SWBXX)
−0.3
(VVINBXX + 0.2 V) with 6 V max
V
VLDO, FBB0+/B0, FBB0−/B1, FBB2, FBB3+/B3, FBB3−/B4, FBB5
−0.3
2
All other analog pins
−0.3
6
INPUT VOLTAGE
V
TEMPERATURE
Junction temperature (TJ-MAX)
150
Maximum lead temperature (soldering, 10 s) (3)
260
−65
Storage temperature, Tstg
(1)
(2)
(3)
°C
150
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. If
Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
All voltage values are with respect to network ground pin.
For detailed soldering specifications and information, please refer to Texas Instruments AN-1112: DSBGA Wafer-Level Chip-Scale
Package (SNVA009).
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
INPUT VOLTAGE
Voltage on power connections (VDDA5V, VINBXX)
2.5
5
V
1.8
smaller of 3.3 V or
VVINBXX
V
SCLSYS, SDASYS, ADDR
0
VVIOSYS
V
SCLSR, SDASR, NSLP, INT
0
VNRST
V
NRST
0
1.8
V
Junction temperature (TJ)
−40
125
Ambient temperature (TA) (3)
−40
85
Voltage on VIOSYS
TEMPERATURE
(1)
(2)
(3)
°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. If
Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
All voltage values are with respect to network ground pin.
Junction-to-ambient thermal resistance value given is valid for High-K PCB, and is highly application and board-layout dependent. In
applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design.
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6.4 Thermal Information
LP8755
THERMAL METRIC (1)
YFQ
UNIT
49 PINS
RθJA
Junction-to-ambient thermal resistance (2)
(3)
49.2
RθJCtop
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance (4)
6.6
ψJT
Junction-to-top characterization parameter (5)
2.9
ψJB
Junction-to-board characterization parameter (6)
6.5
RθJCbot
Junction-to-case (bottom) thermal resistance (7)
n/a
(1)
(2)
(3)
(4)
(5)
(6)
(7)
6
0.2
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC standard
test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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6.5 General Electrical Characteristics
Minimum (MIN) and maximum (MAX) limits apply over the full ambient temperature range –40°C ≤ TA ≤ 85°C; typical (TYP)
values at TA = 25°C (unless otherwise noted). VVDDA5V = VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V, VOUT = 1.1 V (unless
otherwise noted). (1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.1
2
UNIT
CURRENTS
ISHDN
Shutdown supply current.
Total current into power
connections VDDA5V and
VINBXX
VVIOSYS = 0 V, VNRST = 0 V
ISTBY
Standby mode supply current.
Total current into power
connections VDDA5V and
VINBXX
VVIOSYS = 1.8 V, VNRST = 0 V
80
PFM Mode, no load, one core active
0.4
IActive
Active mode current
consumption. Total current
into power connections
VDDA5V and VINBXX
µA
Forced PWM Mode, no load, one core
active
mA
14.5
LOGIC AND CONTROL INPUTS SCLSYS, SDASYS, ADDR
VIL
Input low level
VVIOSYS = 1.8 V to 3.3 V
VIH
Input high level
VVIOSYS = 1.8 V to 3.3 V
Vhys
Hysteresis of Schmitt trigger
inputs (SCLSYS, SDASYS)
Ci
Capacitance of pins
0.3 x
VVIOSYS
0.7 x VVIOSYS
V
0.1 x VVIOSYS
See
(3)
4
pF
LOGIC AND CONTROL INPUTS SCLSR, SDASR, NSLP, NRST
VIL
Input low level
VNRST = 1.8 V
VIH
Input high level
VNRST = 1.8 V
Vhys
Hysteresis of Schmitt trigger
inputs (SCLSR, SDASR)
Ci
Capacitance of SCLSR and
SDASR pins
RIN
Input resistance
VIL_NRST
Input low level NRST
VIH_NRST
Input high level NRST
0.3 x VNRST
0.7 x VNRST
V
0.1 x VNRST
4
NRST pulldown resistor to GND
1200
pF
kΩ
0.54
1.3
V
LOGIC AND CONTROL OUTPUTS
Voltage on INT pin, ISINK = 3 mA,
VNRST = VVIOSYS = 1.8 V
VOL
Output low level
RP
0.4
V
Voltage on SDASYS, SDASR, ISINK = 3
mA,
VNRST = VVIOSYS = 1.8 V
0.36
External pullup resistor for INT To I/O Supply
10
kΩ
ALL LOGIC AND CONTROL INPUTS
ILEAK
(1)
(2)
(3)
Input current
All logic inputs over pin voltage range.
Note that NRST pin does have an 1.2-MΩ
internal pulldown resistor and current
through this resistor is not included into
ILEAK rating. TA = 25°C
−1
1
µA
All voltage values are with respect to network ground pin.
Minimum (Min) and Maximum (Max) limits are specified by design, test, or statistical analysis. Typical (Typ.) numbers are not ensured,
but do represent the most likely norm.
Maximum capacitance of SCLSYS or SDASYS line is 8 pF, if ADDR pin is connected to line for serial bus address selection.
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6.6 6-Phase Buck Electrical Characteristics
Minimum (MIN) and maximum (MAX) limits apply over the full ambient temperature range –40°C ≤ TA ≤ 85°C; typical (TYP)
values at TA = 25°C (unless otherwise noted) (1) (2). VVDDA5V = VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V, VOUT = 1.1 V (unless
otherwise noted).
PARAMETER
Differential feedback
voltage (3) (4)
VFB0+/B0 - VFB0-/B1
VFB
TYP
MAX
PWM Mode, VOUTSET = 0.6 V to 1.67 V,
IOUT ≤ 15 A (5)
TEST CONDITIONS
0.975 x
VOUTSET
VOUTSET
1.025 x
VOUTSET
PFM Mode, VOUTSET = 0.6 V to 1.67 V,
IOUT ≤ 375 mA
0.975 x
VOUTSET
VOUTSET
1.025 x
VOUTSET
Low-Power PFM Mode, VOUTSET = 0.6 V
to 1.67 V,
IOUT ≤ 30 mA
0.97 x
VOUTSET
VOUTSET
1.03 x
VOUTSET
ILIMITP
High side switch current limit 3-A register setting (4)
ILIMITN
Low side switch current limit
VOUT
Output voltage
fSW
Switching frequency
MIN
2700
3200
3700
Reverse current (4)
650
850
1050
Range, programmable by register setting
0.6
Step
1.67
10
2.5 V ≤ VVINBXX ≤ 5 V, 0.6 V ≤ VOUTSET <
0.8 V (4)
2.7
3
3.4
2.5 V ≤ VVINBXX ≤ 5 V, 0.8 V ≤ VOUTSET ≤
1.67 V (4)
3.6
4
4.5
Test current = 200 mA; Split FET
120
Test current = 200 mA; Full FET
60
IOUT = –200 mA
50
RDSON_N
Pin-pin resistance for NFET
ILK_HS
High-side leakage current
VSW = 0 V, Per Buck Core
2
ILK_LS
Low-side leakage current
VSW = 3.7 V = VVINBXX, per buck core
2
RPD
Pull-down resistor
Enabled via control register, Active only
when converter disabled, Per Buck Core
RIN_FB
Differential feedback Input
resistance (6)
TA = 25°C
(3)
(4)
(5)
(6)
8
mA
V
MHz
Pin-pin resistance for PFET
(2)
V
mV
RDSON_P
(1)
UNIT
mΩ
Ω
250
200
300
µA
400
kΩ
Junction-to-ambient thermal resistance value given is valid for High-K PCB, and is highly application and board-layout dependent. In
applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design.
Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics. The performance of the LP8755 device
depends greatly on the care taken in designing the Printed Wiring Board (PWB). The use of low inductance and low serial resistance
ceramic capacitors is strongly recommended, while proper grounding is crucial. Attention should be given to decoupling the power
supplies. Decoupling capacitors must be connected close to the IC and between the power and ground pins to support high peak
currents being drawn from System Power Rail during turn-on of the switching MOSFETs. Keep input and output traces as short as
possible, because trace inductance, resistance and capacitance can easily become the performance limiting items.
Due to the nature of the converter operating in PFM Mode/Low-Power Mode, the feedback voltage accuracy specification is for the lower
point of the ripple. Thus the converter will position the average output voltage typically slightly above the nominal PWM-Mode output
voltage.
Datasheet min/max specification limits are specified by design, test, or statistical analysis.
The power switches in the LP8755 are designed to operate continuously with currents up to the switch current limit thresholds. However,
when continuously operating at high current levels there will be significant heat generated within the IC and thus sustained total DC
current which the device can support is typically limited by thermal constraints. Thermal issues will become extremely important when
designing PCB and the thermal environment of the LP8755. PCB with high thermal efficiency is required to ensure the junction
temperature is kept below 125°C. Completing thermal analyses in early stages of the product design process is highly recommended to
predict thermal performance at board level. Under high current load conditions the serial bus master device must monitor the
temperature of the converter using the Thermal warning feature, see Protection Features Characteristics. If the 2nd thermal warning is
triggered at 120°C, the application must quickly decrease the load current to keep the converter within its recommended operating
temperature.
Datasheet min/max specification limits are specified by design.
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6.7 6-Phase Buck System Characteristics
Minimum (MIN) and maximum (MAX) limits apply over the full ambient temperature range –40°C ≤ TA ≤ 85°C; typical (TYP)
values at TA = 25°C (unless otherwise noted) (1) (2). VVDDA5V = VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V, VOUT = 1.1 V (unless
otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Programmable via control register (3)
RAMP_B0[2:0] = 000
KRAMP
Ramp timer
30
RAMP_B0[2:0] = 001
15
RAMP_B0[2:0] = 010
7.5
RAMP_B0[2:0] = 011
3.8
RAMP_B0[2:0] = 100
1.9
RAMP_B0[2:0] = 101
0.94
RAMP_B0[2:0] = 110
0.47
RAMP_B0[2:0] = 111
0.23
mV/µs
TSTART
Start-up time
Time from NRST-HIGH to start of switching
25
µs
TRAMP
VOUT rise time
Time to ramp from 5% to 95% of VOUT
20
µs
Average output current, programmable via
control register, VOUT = 1.1 V. (4)
IPFM–PWM
PFM-to-PWM switch–over
current threshold
PFM_EXIT_B0[2:0] = 000
100
PFM_EXIT_B0[2:0] = 001
125
PFM_EXIT_B0[2:0] = 010
150
PFM_EXIT_B0[2:0] = 011
175
PFM_EXIT_B0[2:0] = 100
225
PFM_EXIT_B0[2:0] = 101
275
PFM_EXIT_B0[2:0] = 110
325
PFM_EXIT_B0[2:0] = 111
375
mA
Average output current, programmable via
control register, VOUT = 1.1 V. (4)
PFM_ENTRY_B0[2:0] = 000
IPWM–PFM
IADD
(1)
(2)
(3)
(4)
PWM-to-PFM switchover current
threshold
Phase adding level
50
PFM_ENTRY_B0[2:0] = 001
75
PFM_ENTRY_B0[2:0] = 010
100
PFM_ENTRY_B0[2:0] = 011
125
PFM_ENTRY_B0[2:0] = 100
175
PFM_ENTRY_B0[2:0] = 101
225
PFM_ENTRY_B0[2:0] = 110
275
PFM_ENTRY_B0[2:0] = 111
325
ADD_PH_B0[2:0] = 001
400
ADD_PH_B0[2:0] = 010
500
ADD_PH_B0[2:0] = 011
600
ADD_PH_B0[2:0] = 100
700
ADD_PH_B0[2:0] = 101
800
ADD_PH_B0[2:0] = 110
900
ADD_PH_B0[2:0] = 111
1000
mA
mA
Junction-to-ambient thermal resistance value given is valid for High-K PCB, and is highly application and board-layout dependent. In
applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design.
Specifications listed in this table are for 6-phase configuration only. Besides the default 6-phase, single-output voltage rail configuration,
the 6 switcher cores can be bundled to a variety of different grouping configurations. For applications requiring other DC-DC converter
configuration(s), please contact the Texas Instruments Sales Office/Distributors for availability and specifications.
In the real application, achievable output voltage ramp profiles are influenced by a number of factors, including the amount of output
capacitance, the load current level, the load characteristic (either resistive or constant-current), and the voltage ramp amplitude. Typical
values are measured with typical conditions. The falling edge ramp rate can be limited by the negative current limit ILIMITN.
The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependant on the output voltage, input voltage, and
the inductor current level. Typical values are measured with typical conditions.
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6-Phase Buck System Characteristics (continued)
Minimum (MIN) and maximum (MAX) limits apply over the full ambient temperature range –40°C ≤ TA ≤ 85°C; typical (TYP)
values at TA = 25°C (unless otherwise noted)(1)(2). VVDDA5V = VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V, VOUT = 1.1 V (unless
otherwise noted).
PARAMETER
ISHED
MIN
TYP
MAX
UNIT
300
SHED_PH_B0[2:0] = 001
400
SHED_PH_B0[2:0] = 010
500
SHED_PH_B0[2:0] = 011
600
SHED_PH_B0[2:0] = 100
700
SHED_PH_B0[2:0] = 101
800
SHED_PH_B0[2:0] = 110
900
2.5 V ≤ VVINBXX ≤ 5 V
ILOAD = 1 A, forced PWM
0.05
%/V
Load regulation in PWM mode of 100 mA ≤ ILOAD ≤ 10 A, Differential sensing
operation
enabled
0.2
%/A
AUTO (no Low-Power PFM) mode, IOUT 0.5
mA → 500 mA → 0.5 mA, 100 ns load step
±30
mV
PWM mode, IOUT 0.6 A → 2 A → 0.6 A, 400-ns
load step
±20
mV
PWM mode, IOUT 1 A → 8 A → 1 A, 400-ns
load step
±60
mV
VVINBXX stepping 3.3 V 3.8 V, tr = tf = 10
µs,
IOUT = 2000 mA DC
±15
mV
Phase shedding level
Line regulation
ΔVOUT
TEST CONDITIONS
SHED_PH_B0[2:0] = 000
Transient load step response
Transient line response
DC load each phase
mA
2500
IOUT
Output current
COUT
Output capacitance (6)
Effective capacitance during operation, VOUT =
0.6 V to 1.67 V, Min value over TA –40°C to
85°C
30
50
µF
CIN
Input capacitance on each input
voltage rail (6) (7)
Effective capacitance during operation, 2.5 V ≤
VVINBXX ≤ 5 V
2.5
10
µF
L
Output inductance
Effective inductance during operation
IBALANCE
Current balancing accuracy
IOUT ≥ 1000 mA
VRIPPLE_PWM
Output voltage ripple PWM
mode, One phase active (8)
COUT ESR = 10 mΩ
PWM mode, IOUT = 200 mA
Switching frequency = 4 MHz
7
mVPP
VRIPPLE_PFM
Output voltage ripple PFM
mode (8)
COUT ESR = 10 mΩ
PFM mode
IOUT = 100 µA
8
mVPP
(5)
(6)
(7)
(8)
10
Six phases combined (5)
15000
0.25
0.47
1
mA
µH
< 10%
The power switches in the LP8755 are designed to operate continuously with currents up to the switch current limit thresholds. However,
when continuously operating at high current levels there will be significant heat generated within the IC and thus sustained total DC
current which the device can support is typically limited by thermal constraints. Thermal issues will become extremely important when
designing PCB and the thermal environment of the LP8755. PCB with high thermal efficiency is required to ensure the junction
temperature is kept below 125°C. Completing thermal analyses in early stages of the product design process is highly recommended to
predict thermal performance at board level. Under high current load conditions the serial bus master device must monitor the
temperature of the converter using the Thermal warning feature, see Protection Features Characteristics. If the 2nd thermal warning is
triggered at 120°C, the application must quickly decrease the load current to keep the converter within its recommended operating
temperature.
Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics. The performance of the LP8755 device
depends greatly on the care taken in designing the Printed Circuit Board (PCB). The use of low inductance and low serial resistance
ceramic capacitors is strongly recommended, while proper grounding is crucial. Attention should be given to decoupling the power
supplies. Decoupling capacitors must be connected close to the IC and between the power and ground pins to support high peak
currents being drawn from System Power Rail during turn-on of the switching MOSFETs. Keep input and output traces as short as
possible, because trace inductance, resistance and capacitance can easily become the performance limiting items.
In addition to these capacitors, at least one higher value capacitor (for example, 22 µF) should be placed close to the power pins. Note
that cores B0-B1 and B3-B4 do have combined power input pins.
Ripple voltage should be measured at COUT electrode on a well-designed PCB, using suggested inductors and capacitors and with a
high-quality scope probe.
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6-Phase Buck System Characteristics (continued)
Minimum (MIN) and maximum (MAX) limits apply over the full ambient temperature range –40°C ≤ TA ≤ 85°C; typical (TYP)
values at TA = 25°C (unless otherwise noted)(1)(2). VVDDA5V = VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V, VOUT = 1.1 V (unless
otherwise noted).
PARAMETER
VRIPPLE_LP
Output Voltage Ripple LowPower PFM mode (8)
TEST CONDITIONS
MIN
COUT ESR = 10 mΩ
Low-power PFM mode
IOUT = 100 µA
TYP
MAX
8
UNIT
mVPP
6.8 Protection Features Characteristics
Minimum (MIN) and maximum (MAX) limits apply over the full ambient temperature range –40°C ≤ TA ≤ 85°C; typical (TYP) at
TA = 25°C (unless otherwise noted) (1) (2). VVDDA5V = VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V, VOUT = 1.1 V (unless otherwise
noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOLTAGE MONITORING
VPG
Power good threshold voltage
Power good threshold for voltage
decreasing, % of setting, VOUT = 1.1 V
VOVP
Input overvoltage protection trigger
point (3) (4)
VIN rising. Voltage monitored on VDDA5V
pin
5.15
5.3
5.45
VUVLO
Input undervoltage lockout (UVLO)
turn-on threshold (3)
VIN falling. Voltage monitored on VDDA5V
pin
2.15
2.25
2.35
VSCP
Output short-circuit fault threshold
Detected by sensing the voltage on
converter output with respect to GND.
400
mV
tMASKSCP
SCP masking time
Triggered by converter start-up, specified by
design
400
µs
Triggered by converter start-up, specified by
design
400
µs
90%
V
Triggered by VSET transition, specified by
design
Slew Rate setting mV/µs
tMASKPG
(1)
(2)
(3)
(4)
Power Good masking time
30
50
15
100
7.5
200
3.8
400
1.9
800
0.94
1600
0.47
3200
0.23
6400
µs
Junction-to-ambient thermal resistance value given is valid for High-K PCB, and is highly application and board-layout dependent. In
applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design.
Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics. The performance of the LP8755 device
depends greatly on the care taken in designing the Printed Circuit Board (PCB). The use of low inductance and low serial resistance
ceramic capacitors is strongly recommended, while proper grounding is crucial. Attention should be given to decoupling the power
supplies. Decoupling capacitors must be connected close to the IC and between the power and ground pins to support high peak
currents being drawn from System Power Rail during turn-on of the switching MOSFETs. Keep input and output traces as short as
possible, because trace inductance, resistance and capacitance can easily become the performance limiting items.
Undervoltage lockout (UVLO) and overvoltage protection (OVP) circuits shut down the LP8755 when the system input voltage is outside
the desired operating range.
Limits for OVP trigger points apply when VVIOSYS is high. False OVP alarm may occur, if the input voltage rises close to 5 V while
VVIOSYS is low.
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Protection Features Characteristics (continued)
Minimum (MIN) and maximum (MAX) limits apply over the full ambient temperature range –40°C ≤ TA ≤ 85°C; typical (TYP) at
TA = 25°C (unless otherwise noted)(1)(2). VVDDA5V = VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V, VOUT = 1.1 V (unless otherwise
noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
THERMAL SHUTDOWN AND MONITORING
TSHUT
Thermal shutdown (TSD)
Threshold, Temperature rising
Thermal warning
TWARN
150
Hysteresis
25
Temperature rising, 1st warning, Interrupt
only
85
Hysteresis
10
Temperature rising, 2nd warning, Interrupt
and flag set
Thermal warning prior to TSD
°C
120
Hysteresis
10
6.9 I2C Serial Bus Timing Parameters
Serial bus address is selected by the ADDR pin. Connect the pin to GND (addr = 60h), VIOSYS (addr = 61h), SDASYS (addr
= 62h), or SCLSYS (addr = 63h). Both of the serial buses share the same address; that is, if addr = 60h is selected for the
System bus, the Dynamic Voltage Scaling bus will respond to the same address. Start conditions are used to secure the I2C
slave address. During the I2C bus start condition, it is detected whether the ADDR is connected to SDASYS, SCLSYS, GND,
or VIOSYS. The I2C host should allow at least 500 µs before sending data to the LP8755 after the rising edge of the VIOSYS
line.
These specifications are ensured by design. Limits apply over the full ambient temperature range –40°C ≤ TA ≤ 85°C, VVDDA5V
= VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V, VOUT = 1.1 V (unless otherwise noted) (See Figure 1) .
MIN
MAX
UNIT
Standard mode
100
kHz
Fast mode
400
kHz
High-speed mode, Cb = 100 pF (max)
3.4
MHz
1.7
MHz
DIGITAL TIMING SPECIFICATIONS (SCL, SDA)
fCLK
Serial clock frequency
High-speed mode, Cb = 400 pF (max) (4)
tLOW
SCL low time
Standard mode
4.7
Fast mode
1.3
High-speed mode, Cb = 100 pF (max)
160
High-speed mode, Cb = 400 pF (max) (4)
320
Standard mode
tHIGH
tSU;DAT
SCL high time
Data setup time
Fast mode
High-speed mode, Cb = 100 pF (max)
(1)
(2)
(3)
(4)
12
Data hold time
µs
ns
4
µs
0.6
60
High-speed mode, Cb = 400 pF (max) (4)
120
Standard mode
250
Fast mode
100
High-speed mode
tHD;DAT
NOM
(1) (2) (3)
ns
ns
10
Standard mode
0
3.45
Fast mode
0
0.9
High-speed mode, Cb = 100 pF (max)
0
70
High-speed mode, Cb = 400 pF (max) (4)
0
150
µs
ns
Unless otherwise stated, 'SDA' in this paragraph refers to both of the SDASR and SDASYS signals, and respectively 'SCL' refers to
SCLSR and SCLSYS signals.
Cb refers to the capacitance of one bus line. Cb is expressed in pF units. The specification table provided applies to both of the
interfaces; DVS and System interface.
The power-on default setting for the system bus and the DVS bus is High-speed-enabled, there is no handshaking required to initiate
high speed.
For bus line loads Cb between 100 pF and 400 pF the timing parameters must be linearly interpolated.
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I2C Serial Bus Timing Parameters (continued)
Serial bus address is selected by the ADDR pin. Connect the pin to GND (addr = 60h), VIOSYS (addr = 61h), SDASYS (addr
= 62h), or SCLSYS (addr = 63h). Both of the serial buses share the same address; that is, if addr = 60h is selected for the
System bus, the Dynamic Voltage Scaling bus will respond to the same address. Start conditions are used to secure the I2C
slave address. During the I2C bus start condition, it is detected whether the ADDR is connected to SDASYS, SCLSYS, GND,
or VIOSYS. The I2C host should allow at least 500 µs before sending data to the LP8755 after the rising edge of the VIOSYS
line.
These specifications are ensured by design. Limits apply over the full ambient temperature range –40°C ≤ TA ≤ 85°C, VVDDA5V
= VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V, VOUT = 1.1 V (unless otherwise noted) (See Figure 1) .
MIN
tSU;STA
tHD;STA
Set-up time for a repeated
start condition
Hold time for a start or a
repeated start condition
tBUF
Bus free time between a stop
and start condition
tSU;STO
Set-up time for a stop
condition
Standard mode
4.7
Fast mode
0.6
High-speed mode
160
Standard mode
4.0
Fast mode
0.6
High-speed mode
160
Standard mode
4.7
Fast mode
1.3
Standard mode
4.0
Fast mode
0.6
High-speed mode
160
Standard mode
trDA
Rise time of SDA signal
Fall time of SDA signal
Rise time of SCL signal
trCL1
Rise time of SCL signal after
a repeated start condition and
after acknowledge bit
Fall time of a SCL signal
Cb
Capacitive load for each bus
line (SCL and SDA)
tSP
Pulse width of spike
suppressed (5)
(5)
µs
ns
µs
ns
µs
µs
ns
1000
ns
300
ns
High-speed mode, Cb = 100 pF (max)
10
80
ns
High-speed mode, Cb = 400 pF (max) (4)
20
160
ns
300
ns
Fast Mode
6.5
300
ns
High-speed mode, Cb = 100 pF (max)
10
80
ns
High-speed mode, Cb = 400 pF (max) (4)
20
160
ns
1000
ns
Fast mode
20
300
ns
High-speed mode, Cb = 100 pF (max)
10
40
ns
High-speed mode, Cb = 400 pF (max) (4)
20
80
ns
High-speed mode, Cb = 100 pF (max)
10
80
ns
20
160
ns
High-speed mode, Cb = 400 pF (max)
(4)
Standard mode
tfCL
UNIT
20
Standard mode
trCL
MAX
Fast mode
Standard mode
tfDA
NOM
300
ns
Fast mode
6.5
300
ns
High-speed mode, Cb = 100 pF (max)
10
40
ns
High-speed mode, Cb = 400 pF (max) (4)
20
80
ns
400
pF
Fast mode
50
High-speed mode
10
ns
Spike suppression filtering on SCLSYS, SCLSR, SDASYS and SDASR will suppress spikes that are less than the indicated width.
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tBUF
SDA
tfDA
tHD;STA
trCL
tLOW
trDA
tfCL
tSP
SCL
tHD;STA
tSU;STA
tHIGH
tSU;STO
tHD;DAT
tSU;DAT
START
STOP
REPEATED
START
START
Figure 1. I2C Timing
6.10 Typical Characteristics
7
7
6
6
5
5
4
PHASES
PHASES
Unless otherwise specified: VVDDA5V = VVINBXX = 3.7 V
400mA
500mA
600mA
700mA
800mA
900mA
1000mA
3
2
1
0
1
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
C005
Figure 2. Phase Adding vs Load Current in Different
ADD_PH_B0 Settings
LOAD CURRENT (A)
18
VOUT = 1.1V, PFM Mode, no load, one core active
418
VOUT = 1.1V, PWM Mode, no load, one core active
17
416
16
414
CURRENT (mA)
CURRENT (uA)
C006
Figure 3. Phase Shedding vs Load Current in Different
SHED_PH_B0 Settings
420
412
410
408
406
15
14
13
12
404
11
402
Iin(uA)
Iin(mA)
400
10
2.5
3.0
3.5
4.0
INPUT VOLTAGE (V)
4.5
5.0
2.5
3.0
3.5
4.0
INPUT VOLTAGE (V)
C011
Figure 4. PFM Mode Current Consumption vs VIN
14
300mA
400mA
500mA
600mA
700mA
800mA
900mA
3
2
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
LOAD CURRENT (A)
4
4.5
5.0
C012
Figure 5. PWM Mode Current Consumption vs VIN
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7 Detailed Description
7.1 Overview
The LP8755 is a high-efficiency, high-performance power supply IC with six step-down DC-DC converter cores. It
delivers 0.6 V to 1.67 V regulated voltage rail from either a single Li-Ion or three cell NiMH/NiCd batteries to
portable devices such as cell phones and PDAs.
There are three modes of operation for the 6-phase converter, depending on the output current required: PWM
(Pulse Width Modulation), PFM (Pulse-Frequency Modulation), and Low-Power PFM. Converter operates in
PWM mode at high load currents of approximately 250 mA or higher, depending on register setting. Lighter
output current loads will cause the converter to automatically switch into PFM or Low-Power PFM mode for
reduced current consumption and a longer battery life. Forced PWM is also available for highest transient
performance.
Under no-load conditions the device can be set to Standby or Shutdown. Shutdown mode turns off the device,
offering the lowest current consumption (ISHDN = 0.1 µA typ.). Additional features include soft-start, undervoltage
lockout, input overvoltage protection, current overload protection, thermal warning, and thermal shutdown.
The modes and features can be programmed via control registers. All the registers can be accessed with both
I2C serial interfaces: System serial interface and Dynamic voltage scaling (DVS) interface. Using DVS interface
for dynamic voltage scaling prevents latencies if System serial interface is busy. Using DVS interface is optional;
System serial interface can also be used for dynamic voltage scaling.
7.1.1 Buck Information
The LP8755 has six integrated high-efficiency buck converter cores. The cores are designed for flexibility; most
of the functions are programmable, thus allowing optimization of the SMPS operation for each application. The
cores are bundled together to establish a multi-phase converter This is shown in Figure 23.
Operating Modes:
• OFF: Output is isolated from the input voltage rail in this mode. Output has an optional pulldown resistor.
• PWM: Converter operates in buck configuration. Average switching frequency is constant.
• PFM: Converter switches only when output voltage decreases below programmed threshold. Inductor current
is discontinuous.
• Low-Power PFM: This mode is similar to PFM mode, but used with lower load conditions. In this mode some
of the internal blocks are turned off between the PFM pulses. Load transient response is compromised due to
the wake-up time.
Features:
• DVS support; SmartReflex functionality
• Automatic mode control based on the loading
• Synchronous rectification
• Current mode loop with PI compensator
• Soft start
• Power good flag with maskable interrupt
• Overvoltage comparator
• Phase control and spread spectrum techniques for reducing EMI
• Average output current sensing (for PFM/PWM entry/exit, phase adding/shedding, and load current reporting)
• Current balancing between the phases of the converter
• Differential voltage sensing
• Dynamic phase adding/shedding, each output being phase shifted
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Overview (continued)
Programmability (The following parameters can be programmed via registers):
• Output voltage
• Forced PWM operation
• Switch current limits for high side FET
• PWM/PFM mode entry and exit (based on average output current)
• Phase adding and shedding levels
• Output voltage slew rate
7.2 Functional Block Diagram
LP8755
VLDO
INTERNAL
LDO
1 PF
FBB0+ / B0
FBB0- / B1
SYSTEM
POWER
POWER
INPUTS
Configurable
Feedback
Amplifiers
Logic Control
VIOSYS
FBB2
FBB3+ / B3
FBB3- / B4
FBB5
(chip EN)
SCLSYS
SDASYS
ADDR
SYS IO
Domain
EPROM
Buck 0 /
Master 0
Buck 1
Reference
Voltage
SCLSR
SDASR
INT
NSLP
Buck 2
SWB0
SWB1
SWB2
Oscillator
SR IO
Domain
Thermal
Monitoring
NRST
Internal
Pull-down
1.1 M:
Voltage
Monitoring
Buck 3
Buck 4
Buck 5
SWB3
SWB4
SWB5
POWER
GROUNDS
AGND
7.3 Features Descriptions
7.3.1 Multi-Phase DC-DC Converters
A multi-phase synchronous buck converter offers several advantages over a single power-stage converter. For
application processor power delivery, lower ripple on the input and output currents and faster transient response
to load steps are the most significant advantages. Also, since the load current is evenly shared among multiple
channels, the heat generated is greatly reduced for each channel due to the fact that power loss is proportional
to square of current. Physical size of the output inductor shrinks significantly for the similar reason. Interleaving
switching action of the converters and channels for a typical application (shown in Figure 23) is illustrated in
Figure 7.
16
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Features Descriptions (continued)
+
-
SLAVE
PHASE
CONTROL
RAMP
GENERATOR
VOUT
-
GATE
CONTROL
ERROR
AMP
+
VOLTAGE
SETTING
VDAC
SLEW RATE
CONTROL
PROGRAMMABLE
PARAMETERS
VIN
POS
CURRENT
LIMIT
+ -
FBP
FBN
PMOS
CURRENT
SENSE
DIFFERENTIAL TO
SINGLE-ENDED
LOOP
COMP
POWER
GOOD
+
-
CONTROL
BLOCK
MASTER
INTERFACE
SW
NEG
CURRENT
LIMIT
NMOS
CURRENT
SENSE
SLAVE
INTERFACE
ZERO
CROSS
DETECT
IADC
GND
Figure 6. Detailed Block Diagram Showing One Buck Core
7.3.1.1 Multi-Phase Operation and Phase-Shedding
Under heavy load conditions, the 6-phase converter switches each channel 60° apart. As a result, the 6-phase
converter has an effective ripple frequency six times greater than the switching frequency of any one phase.
However, the parallel operation decreases the efficiency at light load conditions. In order to overcome this
operational inefficiency, the LP8755 changes the number of active phases to optimize efficiency for the variations
of the load. This is called phase-shedding. The concept is illustrated in Figure 7.
6-PHASE
OPERATION
5-PHASE
OPERATION
4-PHASE
OPERATION
3-PHASE
OPERATION
2-PHASE
OPERATION
1-PHASE
OPERATION
BEST EFFICIENCY OBTAINED WITH
EFFICIENCY
N=1
N=2
N=3
N=6
N=4
N=5
LOAD CURRENT
Figure 7. Multi-phase Buck Converter Efficiency vs Number of Phases; All Converters in PWM Mode
(6)
(6)
Graph is not to scale and is for illustrative purposes only.
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Features Descriptions (continued)
IL_TOT
IL0
IL1
IL2
IL3
IL4
IL5
0
60
120
180
240
300
360
420
240
300
360
420
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
SWITCHING CYCLE 360°
0
60
120
180
PHASE, DEGREES
Figure 8. PWM Timings and Inductor Current Waveforms
(7)
18
(7)
Graph is not to scale and is for illustrative purposes only.
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Features Descriptions (continued)
7.3.1.2 Transitions Between Low-Power PFM, PFM, and PWM Modes
Normal PWM-mode operation with phase-shedding can optimize efficiency at mid-to-full load, but this is usually
at the expense of light-load efficiency. The LP8755 converter operates in PWM mode at a load current of 100 to
375 mA or higher; this mode transition trip-point is set by register. Lighter load current causes the device to
automatically switch into PFM mode for reduced current consumption. By combining PFM and PWM modes in
the same regulator and providing automatic switching, high efficiency can be achieved over a wide output load
current range.
Efficiency is further enhanced when the converter enters Low-Power PFM mode. The LP8755 includes LowPower mode function for low-current consumption. In this mode most of the internal blocks are disabled between
the inductor current ramp up and ramp down phases to reduce the operating current. However, as a result, the
transient performance of the converter is compromised. The Low-Power mode can be enabled by control register
setting. Also, the application processor or the PMIC may provide an HW signal (NSLP) to the LP8755 input to
indicate when the processor has entered a low-power state. When the signal is asserted, the LP8755 Low-Power
PFM function will be enabled, and the LP8755 will run with a reduced input current. The right timing of the NSLP
signal from the system is important for best load-transient performance. The NSLP signal should be asserted
only when load current is stable and below 30 mA. Before the load current increases above 30 mA, the NSLP
signal should be de-asserted 100 µs (minimum) prior to a load step to prepare the converter for the higher load
current.
7.3.1.3 Buck Converter Load Current
The buck load current can be monitored via I2C registers. Current of different buck converter cores or the total
load current of the master can be selected from register 0x21 (see SEL_I_LOAD). A write to this selection
register starts a current measurement sequence. The measurement sequence is a minimum of 50 µs long. When
a measurement sequence starts, the FLAGS_1.I_LOAD_READY bit in register 0x0E is set to '0'. After the
measurement sequence is finished, the FLAGS_1.I_LOAD_READY bit is set to '1'. (Note that by default this bit is
'0'.) The measurement result can be read from registers 0x22 (LOAD_CURR.BUCK_LOAD_CURR[7:0]) and
0x21 (SEL_I_LOAD.BUCK_LOAD_CURR[10:8]). The measurement result [10:0] LSB is 10 mA, and the
maximum value of the measurement is 20 A. The LP8755 can be configured to give out an interrupt after the
load current measurement sequence is finished. Load current measurement interrupt can be masked with
INT_MASKS_2.MASK_I_LOAD_READY bit.
7.3.1.4 Spread Spectrum Mode
Systems with periodic switching signals may generate a large amount of switching noise in a set of narrowband
frequencies (the switching frequency and its harmonics). The usual solution to reduce noise coupling is to add
EMI-filters and shields to the boards. The LP8755's register-selectable spread spectrum mode minimizes the
need for output filters, ferrite beads, or chokes. In spread spectrum mode, the switching frequency varies
randomly around the center frequency, reducing the EMI emissions radiated by the converter, associated passive
components, and PCB traces. See Figure 9.
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POWER SPECTRUM IS
SPREAD AND LOWERED
RADIADED ENERGY
Features Descriptions (continued)
FREQUENCY
Where a fixed-frequency converter exhibits large amounts of spectral energy at the switching frequency, the spread
spectrum architecture of the LP8755 spreads that energy over a large bandwidth.
Figure 9. Spread Spectrum Modulation
7.3.2 Power-Up and Output Voltage Sequencing
The power-up sequence for the LP8755 is as follows:
• VVINBXX and VVDDA5V reach min recommended levels.
• VVIOSYS set high. Enables the system I/O interface. For power-on-reset (POR), the I2C host should allow at
least 500 µs before sending data to the LP8755 after the rising edge of the VIOSYS line.
• VLDO voltage is raising. The LDO voltage is generated internally. The internal POR signal is activated.
• Internal POR deasserted, OTP read.
• Device enters standby mode.
• DC-DC enable, output voltage, voltage slew rate programmed over I2C as needed by the application.
• NRST set high.
VINBXX
VIOSYS
LDO
(internal)
t0
t1
t2
NRST
tI2CT
LP8755 receiving/sending data across the system I2C bus.
Figure 10. Timing Diagram for the Power-Up Sequence
20
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Features Descriptions (continued)
Table 1. Power-Up Sequence
CONDITION (1)
PARAMETER
(1)
t0
VVDDA5V to VVIOSYS assertion
t1
LDOON Delay Time
MIN
t2
LDOON to NRST HIGH
Device ready for I2C data transfer
MAX
150°C
Read FLAGS_0
Clear T_WARNING
E\ZULWLQJ¶0'
No
INT by change in
TEMP released
Yes
INT Requested
If THSD low then enable
power outputs
INT by T_WARNING
released
TEMP[1:0] = 0b10
Yes
INT Requested
T_WARNING Asserted
No
Tj < 110°C
Tj > 120°C
Read FLAGS_0
No
INT Released
Yes
INT Requested
TEMP[1:0] = 0b01
Yes
INT Requested
No
Tj < 75°C
Tj > 85°C
Read FLAGS_0
Yes
INT Requested
No
INT Released
TEMP[1:0] = 0b00
Note that INT is asserted whenever any of the thermal thresholds is crossed, if unmasked. Note also the 10°C
Hysteresis on the TJ Thresholds.
Figure 16. Thermal Warnings and Thermal Shutdown Flow
7.4 Device Functional Modes
SHUTDOWN: All switch, reference, control and bias circuitry of the LP8755 are turned off. The main battery
supply voltage is high enough to start the buck power-up sequence but VVIOSYS and NRST are
LOW.
STANDBY: Setting VVIOSYS HIGH enables standby-operation. All registers can be read or written by the system
master via the system serial interface. Recovery from UVLO, TSD, or OVP event also leads to
standby.
ACTIVE:
Regulated DC-DC converters are on or can be enabled with full current capability. In this mode, all
features and control registers are available via the system serial bus and via SmartReflex interface.
LOW-POWER: At light loads (less than approximately 30 mA), and when the load does not require highest level
of transient performance, the device enters automatically Low-Power mode. In this mode the part
operates at low IQ. Conditions entering and exiting Low-Power mode are shown in Figure 17.
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Device Functional Modes (continued)
FROM ANY
STATE
VVIOSYS
LOW
SHUTDOWN
VVIOSYS
HIGH
READ
OTP
REG
RESET ***
THERMAL
SHUTDOWN
or
UVLO/OVP
RELEASED
and
FLAG(s) CLEARED
STANDBY
NRST LOW
2
or
I C RESET
2
I C RESET
NRST HIGH
ACTIVE
FAULT CONDITION
DETECTED
**
*
FROM ANY STATE
EXCEPT SHUTDOWN
ACTIVE
LOW POWER
*) HIGH LOAD CURRENT OR ANY OF
THE FOLLOWING CONDITIONS:
NSLP (pin)
LP_B0 (bit)
LP_EN (bit)
FPWM_B0 (bit)
**) LOW LOAD CURRENT AND ALL
THE FOLLOWING CONDITIONS
NSLP (pin)
LP_B0 (bit)
LP_EN (bit)
FPWM_B0 (bit)
HIGH
µ0¶
µ0¶
µ1¶
LOW
µ1¶
µ1¶
µ0¶
***) 6((´5(6(76&(1$5,26´)25
DETAILS
Figure 17. Device Operation Modes
26
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7.5 Programming
7.5.1 I2C-Compatible Interface
The I2C-compatible synchronous serial interface provides access to the programmable functions and registers on
the device. This protocol uses a two-wire interface for bidirectional communications between the IC's connected
to the bus. The two interface lines are the Serial Data Line (SDA), and the Serial Clock Line (SCL). Every device
on the bus is assigned a unique address and acts as either a Master or a Slave depending on whether it
generates or receives the serial clock SCL. The SCL and SDA lines should each have a pullup resistor placed
somewhere on the line and remain HIGH even when the bus is idle. Note: CLK pin is not used for serial bus data
transfer. There are two buses implemented: the System I2C bus and the SmartReflex bus. In the following
paragraphs, SCL refers to both SCLSYS and SCLSR, and SDA refers to SDASYS and SDASR. The LP8755
supports standard mode (100 kHz), fast mode (400 kHz) and high-speed mode (3.4 MHz).
7.5.1.1 Data Validity
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of
the data line can only be changed when clock signal is LOW.
SCL
SDA
data
change
allowed
data
valid
data
change
allowed
data
valid
data
change
allowed
Figure 18. Data Validity Diagram
7.5.1.2 Start and Stop Conditions
The LP8755 is controlled via an I2C-compatible interface. START and STOP conditions classify the beginning
and end of the I2C session. A START condition is defined as SDA transitions from HIGH to LOW while SCL is
HIGH. A STOP condition is defined as SDA transition from LOW to HIGH while SCL is HIGH. The I2C master
always generates the START and STOP conditions.
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 19. Start and Stop Sequences
The I2C bus is considered busy after a START condition and free after a STOP condition. During data
transmission the I2C master can generate repeated START conditions. A START and a repeated START
condition are equivalent function-wise. The data on SDA must be stable during the HIGH period of the clock
signal (SCL). In other words, the state of SDA can only be changed when SCL is LOW. Figure 1 shows the SDA
and SCL signal timing for the I2C-Compatible Bus. See the I2C Serial Bus Timing Parameters for timing values.
7.5.1.3 Transferring Data
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated
by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LP8755 pulls
down the SDA line during the 9th clock pulse, signifying an acknowledge. The LP8755 generates an
acknowledge after each byte has been received.
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Programming (continued)
There is one exception to the “acknowledge after every byte” rule. When the master is the receiver, it must
indicate to the transmitter an end of data by not-acknowledging (“negative acknowledge”) the last byte clocked
out of the slave. This “negative acknowledge” still includes the acknowledge clock pulse (generated by the
master), but the SDA line is not pulled down.
After the START condition, the bus master sends a chip address. This address is seven bits long followed by an
eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a “0” indicates a WRITE and a “1”
indicates a READ. The second byte selects the register to which the data will be written. The third byte contains
data to write to the selected register.
ack from slave
ack from slave
ack from slave
start
MSB Chip Addr LSB
w
ack
MSB Register Addr LSB
ack
MSB
Data LSB
ack
stop
start
id = 60h
w
ack
addr = 40h
ack
address 40h data
ack
stop
SCL
SDA
Figure 20. Write Cycle (w = write; SDA = '0'), id = device address = 60Hex for LP8755.
ack from slave
start
MSB Chip Addr LSB
w
ack from slave
MSB Register Addr LSB
repeated start
ack from slave data from slave nack from master
rs
MSB Chip Address LSB
rs
id = 60h
r
MSB
Data
LSB
stop
address 3Fh data
nack stop
SCL
SDA
start
id =60h
w ack
address = 3Fh
ack
r ack
When READ function is to be accomplished, a WRITE function must precede the READ function as shown above.
Figure 21. Read Cycle ( r = read; SDA = '1'), id = device address = 60Hex for LP8755.
7.5.1.4 I2C-Compatible Chip Address
The device address for the LP8755 is 0x60 (ADDR pin tied to the GND). After the START condition, the I2C
master sends the 7-bit address followed by an eighth bit, read or write (R/W). R/W = 0 indicates a WRITE and
R/W = 1 indicates a READ. The second byte following the device address selects the register address to which
the data will be written. The third byte contains the data for the selected register.
MSB
1
Bit 7
LSB
1
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
R/W
Bit 0
2
I C Slave Address (chip address)
Here device address is 1100000Bin = 60 Hex.
Figure 22. Device Address
28
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Programming (continued)
7.5.1.5 Auto-Increment Feature
The auto-increment feature allows writing several consecutive registers within one transmission. Every time an 8bit word is sent to the LP8755, the internal address index counter will be incremented by one, and the next
register will be written. Table 4 shows writing sequence to two consecutive registers. Note: the auto-increment
feature does not work for read.
Table 4. Auto-Increment Example
Master
Action
Start
Device
Address
= 60H
Write
LP8755
Action
Register
Address
Data
ACK
Data
ACK
Stop
ACK
ACK
7.6 Register Maps
7.6.1 Register Descriptions
The LP8755 is controlled by a set of registers through the system serial interface port or through the
SmartReflex-compatible interface. Table 5 lists device registers, their addresses and their abbreviations. A more
detailed description is given in the sections VSET_B0 to INT_MASK_2.
Many registers contain bits, that are reserved for future use. When writing to a register, any reserved bits should
not be changed.
Table 5. Register Descriptions
Addr
Register
Read /
Write
D7
0x00
VSET_B0
R/W
EN_DIS_B
0
0x06
FPWM
R/W
0x07
BUCK0_CTRL
R/W
0x0D
FLAGS_0
R/W
D6
D5
D4
D3
D2
D1
D0
VSET_B0[6:0]
Reserved
OC_LEV_B0[1:0]
LP_B0
Reserved
I_LOAD_REA
DY
FPWM_B0
RDIS_B0
Reserved
UVLO
T_WARNIN
G
Reserved
RAMP_B0[2:0]
nPG_B0
TEMP[1:0]
0x0E
FLAGS_1
R/W
0x0F
INT_MASK_0
R/W
0x10
GENERAL
R/W
0x11
RESET
R/W
0x12
DELAY_BUCK0
R/W
0x18
CHIP_ID
R
0x19
PFM_LEV_B0
R/W
Reserved
PFM_ENTRY_B0[2:0]
Reserved
PFM_EXIT_B0[2:0]
0x1F
PHASE_LEV_B0
R/W
Reserved
ADD_PH_B0[2:0]
Reserved
SHED_PH_B0[2:0]
0x21
SEL_I_LOAD
R/W
Reserved
BUCK_LOAD_CURR[10:8]
Reserved
LOAD_CURRENT_SOURCE[2:0]
0x22
LOAD_CURR
R
0x2E
INT_MASK_2
R/W
Reserved
Reserved
EN_SS
Reserved
DIS_DIF_B0
THSD
OVP
SCP
MASK_nPG
_B0
MASK_OVP
MASK_SCP
Reserved
SLP_POL
Reserved
LP_EN
SW_RESET
DELAY_B0[7:0]
VENDOR[1:0]
ALL_LAYER[1:0]
METAL_LAYER[3:0]
BUCK_LOAD_CURR[7:0]
Reserved
MASK_ILOA
D_READY
MASK_UVL
O
MASK_TWA MASK_TEM
RNING
P
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7.6.2 VSET_B0
Address: 0x00
D7
EN_DIS_B0
D6
D5
D4
D3
VSET_B0[6:0]
D2
D1
D0
Bits
Field
Type
Default
Description
7
EN_DIS_B0
R/W
1
DC-DC converter Buck0 Enable/Disable. The Enable of the master Buck0 controls the
operation of the slave bucks.
0 = Converter disabled
1 = Converter enabled
Note: When a disable request is received the converter is disabled immediately.
6:0
VSET_B0[6:0]
R/W
011 1100
Sets the output voltage.
Defined by:
VOUT = 0.5 V + 10 mV * VSET_B0
VOUT range = 0.6 V to 1.67 V
NOTE: Do not use VSET_B0 values < 0001010 (10 dec) = 0.6 V.
NOTE: Register settings starting from 1110110 up to 1111111 are clamped to 1.67 V.
7.6.3 FPWM
Address: 0x06
D7
D6
D5
D4
Reserved
Bits
Field
Type
Default
7:1
Reserved
R/W
001 1111
0
FPWM_B0
R/W
1
D3
D2
D1
D0
FPWM_B0
Description
Forced PWM mode of operation, Buck regulator 0 (Master). The setting of the master
controls the operation of the slave bucks.
0 = PWM, PFM or Low-Power PFM operation mode.
1 = This will force the master converter and the slaves to operate always in the PWM
mode.
7.6.4 BUCK0_CTRL
Address: 0x07
D7
D6
OC_LEV_B0[1:0]
D5
LP_B0
D4
RDIS_B0
D3
Reserved
D2
D1
RAMP_B0[2:0]
D0
Bits
Field
Type
Default
7:6
OC_LEV_B0[1:0]
R/W
11
Inductor positive current limit on Buck 0. Note that OC_LEV_B0...B5 should have the
same value.
00 = 1.5 A
01 = 2.0 A
10 = 2.5 A
11 = 3.0 A
5
LP_B0
R/W
0
Allows converter to enter into Low-Power PFM mode.
1 = Entering to Low-Power PFM mode is allowed.
0 = Entering to Low-Power PFM more is not allowed.
4
RDIS_B0
R/W
1
Enables the output discharge resistors when the VOUT supply has been disabled.
1 = Enable pull-down
0 = Disable pull-down
3
Reserved
R/W
0
30
Description
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Bits
Field
Type
Default
2:0
RAMP_B0[2:0]
R/W
001
Description
This set the output voltage change ramp as follows:
000 = 30 mV/µs
001 = 15 mV/µs
010 = 7.5 mV/µs
011 = 3.8 mV/µs
100 = 1.9 mV/µs
101 = 0.94 mV/µs
110 = 0.47 mV/µs
111 = 0.23 mV/µs
7.6.5 BUCK1_CTRL
Address: 0x08
D7
D6
OC_LEV_B1[1:0]
D5
D4
D3
D2
D1
D0
Reserved
Bits
Field
Type
Default
7:6
OC_LEV_B1[1:0]
R/W
11
5:0
Reserved
R/W
01 0001
Description
Inductor positive current limit on Buck 1. Note that OC_LEV_B0...B5 should have the
same value.
00 = 1.5 A
01 = 2.0 A
10 = 2.5 A
11 = 3.0 A
7.6.6 BUCK2_CTRL
Address: 0x09
D7
D6
OC_LEV_B2[1:0]
D5
D4
D3
D2
D1
D0
Reserved
Bits
Field
Type
Default
7:6
OC_LEV_B2[1:0]
R/W
11
5:0
Reserved
R/W
01 0001
Description
Inductor positive current limit on Buck 2. Note that OC_LEV_B0...B5 should have the
same value.
00 = 1.5 A
01 = 2.0 A
10 = 2.5 A
11 = 3.0 A
7.6.7 BUCK3_CTRL
Address: 0x0A
D7
D6
OC_LEV_B3[1:0]
D5
D4
D3
D2
D1
D0
Reserved
Bits
Field
Type
Default
7:6
OC_LEV_B3[1:0]
R/W
11
5:0
Reserved
R/W
01 0001
Description
Inductor positive current limit on Buck 3. Note that OC_LEV_B0...B5 should have the
same value.
00 = 1.5 A
01 = 2.0 A
10 = 2.5 A
11 = 3.0 A
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7.6.8 BUCK4_CTRL
Address: 0x0B
D7
D6
OC_LEV_B4[1:0]
D5
D4
D3
D2
D1
D0
Reserved
Bits
Field
Type
Default
7:6
OC_LEV_B4[1:0]
R/W
11
5:0
Reserved
R/W
01 0001
Description
Inductor positive current limit on Buck 4. Note that OC_LEV_B0...B5 should have the
same value.
00 = 1.5 A
01 = 2.0 A
10 = 2.5 A
11 = 3.0 A
7.6.9 BUCK5_CTRL
Address: 0x0C
D7
D6
OC_LEV_B5[1:0]
D5
D4
D3
D2
D1
D0
Reserved
Bits
Field
Type
Default
7:6
OC_LEV_B5[1:0]
R/W
11
5:0
Reserved
R/W
01 0001
Description
Inductor positive current limit on Buck 5. Note that OC_LEV_B0...B5 should have the
same value.
00 = 1.5 A
01 = 2.0 A
10 = 2.5 A
11 = 3.0 A
7.6.10 FLAGS_0
Address: 0x0D
D7
D6
D5
Reserved
D4
D3
D2
nPG_B0
Bits
Field
Type
Default
7:3
Reserved
R/W
X XXXX
2
nPG_B0
R/W
0
Flag Bit (1)
Power good fault flag for VOUT rail
1 = Power fault detected
0 = Power good
1:0
TEMP[1:0]
R
00
indicates the die temperature as follows:
00: die temperature lower than 85ºC
01: 85ºC ≤ die temperature < 120ºC
10: 120ºC ≤ die temperature < 150ºC
11: die temperature 150ºC or higher
(1)
D1
D0
TEMP[1:0]
Description
The flag bit can be cleared only by writing a zero to the associated register bit or power cycling the device (VVIOSYS to LOW). Reading or
RESET does not clear the flag bits. After clearing, the nPG fault flag will be raised again '1' if the fault condition persists. Any unmasked
flag bit High will cause the interrupt to be asserted on the INT pin. The INT pin will be pulled Low until all the unmasked flags are clear
again.
7.6.11 FLAGS_1
Address: 0x0E
32
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D7
D6
D5
I_LOAD_READ
Y
Reserved
Bits
D4
UVLO
D3
T_WARNING
D2
THSD
D1
OVP
D0
SCP
Field
Type
Default
7:6
Reserved
R/W
00
5
I_LOAD_READY
R/W
0
Flag Bit (1)
1 = Buck load current measurement data ready
0 = Buck load current measurement data not ready
4
UVLO
R/W
0
Flag Bit (1)
1= Input undervoltage lockout (UVLO): Input voltage sagged below UVLO threshold.
0 = No UVLO
3
T_WARNING
R/W
0
Flag Bit (1)
1= Thermal warning: The IC temperature exceeds 120°C, in advance of the thermal
shutdown protection.
0 = No thermal warning
2
THSD
R/W
0
Flag Bit (1)
1 = Thermal shutdown event detected
0 = No thermal shutdown
1
OVP
R/W
0
Flag Bit (1)
1= Indicates overvoltage protection (OVP) circuit activation.
0 = No OVP event. The OVP circuitry monitors VDDA5V power input.
0
SCP
R/W
0
Flag Bit (1)
1= Indicates short-circuit protection (SCP) circuit activation. The bit is activated when a
short-circuit condition is detectedon output rail.
0 = No SCP event
(1)
Description
The flag bit(s) can be cleared only by writing a zero to the associated register bit(s) or power cycling the device (VVIOSYS to LOW).
Reading or RESET does not clear the flag bits. After clearing, the OVP, SCP fault flag(s) will be raised again '1' if the fault condition
persists. The THSD flag will remain '0' after clear, even though the fault condition persists. Any unmasked flag bit High will cause the
interrupt to be asserted on the INT pin. The INT pin will be pulled Low until all the unmasked flags are clear again.
7.6.12 INT_MASK_0
Address: 0x0F
D7
D6
D5
Reserved
D4
D3
D2
MASK_nPG_B
0
D1
MASK_OVP
Bits
Field
Type
Default
7:3
Reserved
R/W
1 1111
2
MASK_nPG_B0
R/W
0
Interrupt mask for power good fault flag
1 = nPG does not set interrupt.
0 = nPG sets interrupt, when triggered.
1
MASK_OVP
R/W
0
Interrupt mask for Overvoltage Protection (OVP) fault flag
1 = OVP does not set interrupt.
0 = OVP sets interrupt, when triggered.
0
MASK_SCP
R/W
0
Interrupt mask for short-circuit protection SCP fault flag
1 = SCP does not set interrupt.
0 = SCP sets interrupt, when triggered.
D0
MASK_SCP
Description
7.6.13 GENERAL
Address: 0x10
D7
D6
Reserved
D5
EN_SS
D4
Reserved
D3
DIS_DIF_B0
D2
D1
SLP_POL
D0
LP_EN
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Bits
Field
Type
Default
7:6
Reserved
R/W
00
5
EN_SS
R/W
0
4
Reserved
R/W
0
3
DIS_DIF_B0
R/W
0
R/W
0
2
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Description
Spread Spectrum
1 = Spread Spectrum enabled
0 = Spread Spectrum disabled
Disable Differential-to-single-ended amplifier
1 = Differential amplifier disabled
0 = Differential amplifier enabled
1
SLP_POL
R/W
0
Sets the polarity of the NSLP pin
1 = NSLP is active high
0 = NSLP is active low
0
LP_EN
R/W
1
1 = allows Low-Power PFM mode. In order to reduce power consumption under low
load conditions, the unit will automatically switch off unused internal blocks.
0 = Low-Power mode not allowed
7.6.14 RESET
Address: 0x11
D7
D6
D5
D4
Reserved
Bits
Field
Type
Default
7:1
Reserved
R/W
000 0000
0
SW_RESET
R/W
0
D3
D2
D1
D0
SW_RESET
Description
Writing this bit with '1' and '0', in this order, will reset the registers to the default values.
If NRST is still kept HIGH, the converter output(s) will be regulated to the programmed
register values. If a full POR reset is required VVIOSYS must be pulled low. The fault
flags are persistent over SW-reset.
7.6.15 DELAY_BUCK0
Address: 0x12
D7
D6
D5
D4
D3
D2
D1
D0
DELAY_B0
Bits
Field
Type
7:0
DELAY_B0
R/W
(1)
Default
Description
0000 0000 Master delay
Sets the delay time from when NRST is asserted to when the VOUT rail is enabled.
Sets the delay time from when NRST is de-asserted to when the VOUT rail is disabled.
DELAY = DELAY_B0 * 100 µs
If DELAY_B0 = FFh, supply is never enabled. (1)
If this register is set to FFh when the converter is already started, it will cause an immediate power down of the converter.
7.6.16 CHIP_ID
Address: 0x18
D7
DEVICE
D6
D5
D4
OTP_REV
Bits
Field
Type
Default
7
DEVICE
R
1
6:2
OTP_REV
R
0 0001
34
D3
D2
D1
D0
DIE_REV
Description
DEVICE
Contains Device ID
OTP_REV
Contains OTP Version ID
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Bits
Field
Type
Default
1:0
DIE_REV
R
00
Description
DIE_REV
Contains Revision ID
7.6.17 PFM_LEV_B0
Address: 0x19
D7
Reserved
D6
D5
PFM_ENTRY_B0[2:0]
Bits
Field
Type
Default
7
Reserved
R/W
0
6:4
PFM_ENTRY_B0
R/W
3
Reserved
R/W
0
2:0
PFM_EXIT_B0
R/W
101
(1)
D4
D3
Reserved
D2
D1
PFM_EXIT_B0[2:0]
D0
Description
PFM_ENTRY_B0 (1)
Sets the target PFM entry level for Buck 0. The final PWM-to-PFM switchover current
varies slightly and is dependant on the output voltage, input voltage and the inductor
current level.
000 = 50 mA
001 = 75 mA
010 = 100 mA
011 = 125 mA
100 = 175 mA
101 = 225 mA
110 = 275 mA
111 = 325 mA
PFM_EXIT_B0 (1)
Sets the target PFM exit level for Buck 0. The final PFM-to-PWM switchover current
varies slightly and is dependant on the output voltage, input voltage and the inductor
current level.
000 = 100 mA
001 = 125 mA
010 = 150 mA
011 = 175 mA
100 = 225 mA
101 = 275 mA
110 = 325 mA
111 = 375 mA
For proper operation, the PFM exit current level should be at least 50 mA higher than the PFM entry current level.
7.6.18 PHASE_LEV_B0
Address: 0x1F
D7
Reserved
D6
D5
ADD_PH_B0[2:0]
Bits
Field
Type
Default
7
Reserved
R/W
0
6:4
ADD_PH_B0
R/W
100
3
Reserved
R/W
0
(1)
D4
D3
Reserved
D2
D1
SHED_PH_B0[2:0]
D0
Description
ADD_PH_B0 (1)
Sets the level on which a phase is added.
000 = 0.3 A * No. of Active Phases
001 = 0.4 A * No. of Active Phases
010 = 0.5 A * No. of Active Phases
011 = 0.6 A * No. of Active Phases
100 = 0.7 A * No. of Active Phases
101 = 0.8 A * No. of Active Phases
110 = 0.9 A * No. of Active Phases
111 = 1.0 A * No. of Active Phases
ADD_PH_B0 and SHED_PH_B0 values must be chosen so that the resulting hysteresis is a minimum of 100 mA and ADD_PH_B0 >
SHED_PH_B0.
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Bits
Field
Type
Default
2:0
SHED_PH_B0
R/W
010
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Description
SHED_PH_B0 (1)
Sets the level of phase shedding.
000 = 0.3 A * No. of Active Phases
001 = 0.4 A * No. of Active Phases
010 = 0.5 A * No. of Active Phases
011 = 0.6 A * No. of Active Phases
100 = 0.7 A * No. of Active Phases
101 = 0.8 A * No. of Active Phases
110 = 0.9 A * No. of Active Phases
111 = 1.0 A * No. of Active Phases
7.6.19 SEL_I_LOAD
Address: 0x21
D7
Reserved
D6
D5
BUCK_LOAD_CURR[10:8]
Bits
Field
Type
Default
7
Reserved
R/W
0
6:4
BUCK_LOAD_
CURR[10:8]
R
000
3
Reserved
R/W
0
2:0
LOAD_CURRENT_
SOURCE[2:0]
R/W
000
D4
D3
Reserved
D2
D1
D0
LOAD_CURRENT_SOURCE[2:0]
Description
BUCK_LOAD_CURR
This register reports 3 MSB bits of the magnitude of the average load current of the
selected Buck Converter. See LOAD_CURR register.
LOAD_CURRENT_SOURCE
These bits are used for choosing the Buck Converter whose load current will be
measured.
000 = Converter 0 load current will be measured.
001 = Converter 1 load current will be measured.
010 = Converter 2 load current will be measured.
011 = Converter 3 load current will be measured.
100 = Converter 4 load current will be measured.
101 = Converter 5 load current will be measured.
110 = Master total load current will be measured.
7.6.20 LOAD_CURR
Address: 0x22
D7
D6
D5
Bits
Field
Type
7:0
BUCK_LOAD_
CURR[7:0]
R
D4
D3
BUCK_LOAD_CURR[7:0]
Default
D2
D1
D0
Description
0000 0000 BUCK_LOAD_CURR
This register reports 8 LSB bits of the magnitude of the average load current of the
selected Buck Converter. The value is reported with a resolution of 10 mA per LSB
and 20A max current. Three MSB bits are reported by
SEL_I_LOAD.BUCK_LOAD_CURR[10:8] bits, see SEL_I_LOAD.
The current reported is an average over the last 5 milliseconds. The host system has
read-only access to this register. This register is cleared to 0 on all resets.
000 0000 0000 Load current lower than 10 mA
000 0000 0001 10 mA ≤ Load current < 20 mA
...
111 1111 1110 20460 mA ≤ Load current < 20470 mA
111 1111 1111 Load current 20470 mA or higher.
Note: Not production tested. Typical values for reference only.
7.6.21 INT_MASK_2
Address: 0x2E
36
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D7
D6
D5
D4
Reserved
Bits
D3
MASK_ILOAD_
READY
D2
MASK_UVLO
D1
MASK_TWARN
ING
Field
Type
Default
7:4
Reserved
R/W
0000
3
MASK_ILOAD_
READY
R/W
1
Interrupt mask for load current measurement flag
1 = FLAGS_1.I_LOAD_READY does not set interrupt.
0 = FLAGS_1.I_LOAD_READY sets interrupt.
2
MASK_UVLO
R/W
0
Interrupt mask for undervoltage lock-out flag
1 = FLAGS_1.UVLO does not set interrupt.
0 = FLAGS_1.UVLO sets interrupt, when triggered.
1
MASK_
TWARNING
R/W
1
Interrupt mask for thermal warning flag
1 = FLAGS_1.T_WARNING does not set interrupt.
0 = FLAGS_1.T_WARNING sets interrupt, when triggered.
0
MASK_TEMP
R/W
1
Interrupt mask for die temperature flag bits
1 = FLAGS_0.TEMP[1:0] value change does not set interrupt.
0 = FLAGS_0.TEMP[1:0] value change sets interrupt.
D0
MASK_TEMP
Description
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LP8755 is a multi-phase step-down converter with 6 switcher cores bundled together.
8.2 Typical Application
SYSTEM VOLTAGE
LP8755: 6-PHASE
CONFIGURATION
2.5..5.0V
VINB0B1
OUTPUT
VOLTAGE
L1 0.47/1PH
SWB0
CIN1
10 PF
L2 0.47/1PH
VINB2
SWB1
APPLICATIONS
PROCESSOR
CIN2
10 PF
L3 0.47/1PH
SWB2
VINB3B4
CIN3
10 PF
COUT6PH
4 x 22 PF
L4 0.47/1PH
VINB5
CPU
LOAD
15A
MAX
SWB3
CIN4
10 PF
L5 0.47/1PH
SWB4
VDDA5V
L6 0.47/1PH
VIOSYS
SWB5
CPU SENSE
VIO1V8
CVDDA
100
nF
SDASR
FBB0+
SCLSR
FBB0VIO1V8
NSLP
VLDO
CLDO
1 PF
RP3
FBB2
SDASYS
RP4
FBB3+
SCLSYS
FBB3-
RP5
INT
ADDR
GNDs
FBB5
NRST
CPU POWER REQUEST
Figure 23. Six-Phase Configuration Scheme
38
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Typical Application (continued)
8.2.1 Design Requirements
Table 6 shows requirements for 6-phase configuration.
Table 6. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
2.5 V to 5 V
Output voltage
1.1 V
Converter operation mode
Forced PWM
Maximum load current
15 A
Inductor current limit
3A
8.2.2 Detailed Design Procedure
The performance of the LP8755 device depends greatly on the care taken in designing the Printed Circuit Board
(PCB). The use of low inductance and low serial resistance ceramic capacitors is strongly recommended, while
proper grounding is crucial. Attention should be given to decoupling the power supplies. Decoupling capacitors
must be connected close to the IC and between the power and ground pins to support high peak currents being
drawn from System Power Rail during turn-on of the switching MOSFETs. Keep input and output traces as short
as possible, because trace inductance, resistance and capacitance can easily become the performance limiting
items. The separate power pins VINBXX are not connected together internally. The VINBXX power connections
shall be connected together outside the package using power plane construction.
8.2.2.1 Inductor Selection
The DC bias current characteristics of inductors must be considered. Different manufacturers follow different
saturation current rating specifications, so attention must be given to details. (Please request DC bias curves
from the manufacturer as part of the inductor selection process.) Minimum effective value of inductance to
ensure good performance is 0.25 µH at 3.2 A (Default ILIMITP typical) bias current over the inductor's operating
temperature range. The inductor’s DC resistance should be less than 0.05 Ω for good efficiency at high-current
condition. The inductor AC loss (resistance) also affects conversion efficiency. Higher Q factor at switching
frequency usually gives better efficiency at light load to middle load. Table 7 lists suggested inductors and
suppliers. Shielded inductors radiate less noise and are preferable.
Table 7. Suggested Inductor Selection
ITEM
MODEL
VENDOR
DIMENSIONS LXWXH
(mm)
D.C.R (mΩ)
MAX
L1 to L6; Step-down
converter inductor 0.47 µH
XFL4015-471ME_ (1)
LQH32PNR47NN0 (2)
DFE252012 R47 (3)
DFE201612C R47N (4)
LQM2MPNR47MGH (4)
Coilcraft
Murata
TOKO
TOKO
Murata
4 .0 x 4.0 x 1.5
3.2 x 2.5 x 1.55
2.5 x 2 x 1.2
2.0 x 1.6 x 1.2
2.0 x 1.6 x 1.0
8.4
30 ± 20 %
39
50
46
L1 to L6; Step-down
converter inductor 0.68 µH
DFE322512 R68
TOKO
3.2 x 2.5 x 1.2
37
L1 to L6; Step-down
converter inductor
1 µH
DFE322512 1R0
TOKO
3.2 x 2.5 x 1.2
45
(1)
(2)
(3)
(4)
Best efficiency.
Good balance between size and efficiency.
Satisfactory compromise between size and efficiency.
Applications for which solution size is critical, efficiency compromised on very high loads.
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8.2.2.2 Input Capacitor Selection
A ceramic input capacitor of 10 µF, 10 V is sufficient for most applications. Place the input capacitor as close as
possible to the VINBXX pin and GND pin of the device. A larger value or higher voltage rating may be used to
improve input voltage filtering. Use X7R or X5R types, do not use Y5V. DC bias characteristics of ceramic
capacitors must be considered when selecting case sizes like 0402. Minimum effective input capacitance to
ensure good performance is 2.5 µF at maximum input voltage DC bias including tolerances and over ambient
temp range, assuming that there is at least 22 µF of additional capacitance common for all the power input pins
on the system power rail.
The input filter capacitor supplies current to the PFET (high-side) switch in the first half of each cycle and
reduces voltage ripple imposed on the input power source. A ceramic capacitor's low equivalent series resistance
(ESR) provides the best noise filtering of the input voltage spikes due to this rapidly changing current. Select an
input filter capacitor with sufficient ripple current rating.
For additional noise immunity, adding a high-frequency decoupling capacitor of 100 nF to 1 µF between VDDA5V
pin and GND is recommended.
Table 8. Suggested Input Capacitors (X5R Dielectric)
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
VOLTAGE RATING
Murata
GRM188R60J106ME84
10 µF (20%)
0603
6.3 V
TDK
C1608X5R1A106KT
10 µF (10%)
0603
10 V
Taiyo Yuden
LMK107BJ106MALTD
10 µF (20%)
0603
10 V
Samsung
CL10A226MP8NUNE
22 µF (20%)
0603
10 V
8.2.2.3 Output Capacitor Selection
Use ceramic capacitor, X7R or X5R types; do not use Y5V. DC bias voltage characteristics of ceramic capacitors
must be considered. DC bias characteristics vary from manufacturer to manufacturer, and DC bias curves should
be requested from them as part of the capacitor selection process. The output filter capacitor smooths out current
flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and
reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low
ESR to perform these functions. Minimum effective output capacitance to ensure good performance in 6-phase
configuration is 30 µF at the output voltage DC bias including tolerances and over ambient temp range.
The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its
RESR. The RESR is frequency dependent (as well as temperature dependent); make sure the value used for
selection process is at the switching frequency of the part.
A higher output capacitance improves the load step behavior and reduces the output voltage ripple as well as
decreasing the PFM switching frequency. For most 6-phase applications 4 x 22-µF 0603 capacitors for COUT is
suitable. Although the converter's loop compensation can be programmed to adapt to virtually several hundreds
of microfarads COUT, an effective COUT less than 120 µF is preferred -- there is not necessarily any benefit to
having a COUT higher than 120 µF. Note that the output capacitor may be the limiting factor in the output voltage
ramp, especially for very large (> 100 µF) output capacitors. For large output capacitors, the output voltage might
be slower than the programmed ramp rate at voltage transitions, because of the higher energy stored on the
output capacitance. Also at start-up, the time required to charge the output capacitor to target value might be
longer. At shutdown, if the output capacitor is discharged by the internal discharge resistor, more time is required
to settle VOUT down as a consequence of the increased time constant.
Table 9. Suggested Output Capacitor
40
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
VOLTAGE RATING
Samsung
CL10A226MP8NUNE
22 µF (20%)
0603
10 V
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8.2.2.4 LDO Capacitor Selection
A ceramic low ESR 1-μF capacitor should be connected between the VLDO and GNDA pins.
Table 10. Suggested LDO Capacitor
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
VOLTAGE RATING
Samsung
CL03A105MQ3CSNH
1 µF (20%)
0201
6.3 V
8.2.2.5 VIOSYS Capacitor Selection
Adding a ceramic low ESR 1-μF capacitor between the VIOSYS pin and GND is recommended. If VVIOSYS signal
is low noisy the capacitor is not required.
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8.2.3 Application Curves
100
100
90
90
EFFICIENCY (%)
EFFICIENCY (%)
Unless otherwise specified: VVDDA5V = VVINBXX = 3.7 V, VOUT = 1.1 V, TA = 25°C
80
70
1650 mV
1400 mV
1150 mV
900 mV
650 mV
VIN = 3.8V
fSW = 4.0MHz
Inductor: TOKO
DFE252012C 470nH
60
50
80
70
VIN = 2.8V
fSW = 4.0MHz
Inductor: TOKO
DFE252012C 470nH
60
2500
5000
7500
10000
12500
15000
1400 mV
1150 mV
900 mV
650 mV
50
0
1650 mV
0
2500
OUTPUT CURRENT (mA)
5000
7500
10000
12500
15000
OUTPUT CURRENT (mA)
C001
C002
Figure 24. Efficiency vs Load Current in PWM Mode; VOUT
Settings = 650 mV, 950 mV, 1150 mV, 1400 mV and 1650
mV
Figure 25. Efficiency vs Load Current in PWM Mode; VOUT
Settings = 650 mV, 950 mV, 1150 mV, 1400 mV and 1650
mV
100
100
VIN = 3.8V Inductor: TOKO
DFE252012C 470nH
OUTPUT CURRENT = 3A
fSW = 4.0MHz
Inductor: TOKO
DFE252012C 470nH
PFM to PWM transition
90
95
1650 mV
1400 mV
1150 mV
900 mV
650 mV
80
EFFICIENCY (%)
EFFICIENCY (%)
90
70
1650 mV
1400 mV
1150 mV
900 mV
650 mV
1650 mV Low Power
1400 mV Low Power
1150 mV Low Power
900 mV Low Power
650 mV Low Power
60
50
40
80
75
30
1
10
85
100
70
2500
1000
3000
OUTPUT CURRENT (mA)
3500
4000
4500
5000
INPUT VOLTAGE (mV)
C006
C003
Figure 26. Light Load Efficiency, PFM and Low Power
Mode Enabled; VOUT Settings = 650 mV, 950 mV, 1150 mV,
1400 mV and 1650 mV. PFM_EXIT_B0[2:0] = 100b (225 mA)
Figure 27. Efficiency vs Input Voltage in PWM Mode; VOUT
Settings = 650 mV, 950 mV, 1150 mV, 1400 mV and 1650
mV
100
100
1650 mV
OUTPUT CURRENT = 6A
fSW = 4.0MHz
Inductor: TOKO
DFE252012C 470nH
95
OUTPUT CURRENT = 10A
fSW = 4.0MHz
Inductor: TOKO
DFE252012C 470nH
1400 mV
1150 mV
95
900 mV
650 mV
1150 mV
900 mV
90
EFFICIENCY (%)
EFFICIENCY (%)
1400 mV
650 mV
90
85
85
80
80
75
75
70
2500
3000
3500
4000
4500
5000
70
2500
INPUT VOLTAGE (mV)
3000
3500
4000
4500
5000
INPUT VOLTAGE (mV)
C003
Figure 28. Efficiency vs Input Voltage in PWM Mode; VOUT
Settings = 650 mV, 950 mV, 1150 mV, 1400 mV and 1650
mV
42
1650 mV
C003
Figure 29. Efficiency vs Input Voltage in PWM Mode; VOUT
Settings = 650 mV, 950 mV, 1150 mV, 1400 mV and 1650
mV
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1160
1.110
VIN = 3.8V, VOUTSET = 1150mV
VIN = 3.7V, VOUTSET = 1100mV
1.108
1.106
1155
VOUT (V)
1150
1.102
1.100
1.098
1.096
1145
Auto LP/PFM/PWM Mode
1.094
Auto PFM/PWM Mode
Forced PWM Mode
1140
PFM, Iload = 100mA
1.092
PWM, Iload = 3A
1.090
1
10
100
1k
10k
LOAD CURRENT (mA)
±60
±20
0
20
40
60
80
100 120 140
T (C)
C004
Figure 30. Output Voltage vs Load Current in Different
Modes
2500
PHASE CURRENT (mA)
1149.5
1149.0
1148.5
C028
Figure 31. Output Voltage vs Temperature
1150.0
OUTPUT VOLTAGE (mV)
±40
10.0
Phase 0
Phase 1
Phase 2
Phase 3
Phase 4
Phase 5
Accuracy
2000
1500
9.0
8.0
7.0
6.0
5.0
4.0
1000
3.0
ACCURACY (%)
VOUT (mV)
1.104
2.0
500
1.0
0
3000
3500
4000
4500
0
5000
5000
7.0
6.0
1500
5.0
4.0
1000
3.0
2.0
500
1.0
0
0
2000
4000
6000
0.0
8000
TOTAL IOUT (mA)
IOUT MEASURED BY LP8755 (mA)
8.0
ACCURACY (%)
PHASE CURRENT (mA)
2000
16000
9.0
14000
12000
10000
8000
6000
4000
2000
0
0
2000
4000
6000
15.0
14.0
13.0
12.0
11.0
10.0
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
IOUT
1.0
Accuracy
0.0
8000 10000 12000 14000 16000
REAL IOUT (mA)
C008
Figure 34. Phase Currents and Current Balancing
Accuracy, 3 Phases Active (Currents measured by
LP8755)
C008
Figure 33. Phase Currents and Current Balancing
Accuracy, 6 Phases Active (Currents measured by
LP8755)
10.0
Phase 0
Phase 1
Phase 2
Accuracy
0.0
15000
TOTAL IOUT (mA)
INPUT VOLTAGE (mV)
Figure 32. Line Regulation; ILOAD = 1 A; VOUTSET = 1150 mV
2500
10000
ACCURACY (%)
1148.0
2500
C009
Figure 35. Load Current Measured by LP8755 vs Real Load
Current, 6 Phases Active
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7000
6000
5000
4000
3000
2000
1000
0
0
1000
2000
3000
4000
5000
15.0
14.0
13.0
12.0
11.0
10.0
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
IOUT
1.0
Accuracy
0.0
6000 7000 8000
REAL IOUT (mA)
VOUT AC COUPLED
20 mV/DIV
ACCURACY (%)
IOUT MEASURED BY LP8755 (mA)
8000
www.ti.com
lLOAD 2 A/DIV
TIME 10 Ps/DIV
C010
Figure 36. Load Current Measured by LP8755 vs Real Load
Current, 3 Phases Active
Figure 37. Transient Load Step Response; PWM mode,
IOUT 1 A → 8 A → 1 A, tRISE = tFALL= 400 ns
VOUT AC COUPLED
20 mV/DIV
VOUT AC COUPLED
20 mV/DIV
lLOAD 400 mA/DIV
lLOAD 200 mA/DIV
TIME 10 Ps/DIV
TIME 10 Ps/DIV
Figure 38. Transient Load Step Response; PWM mode,
IOUT 0.6 A → 2 A → 0.6 A, tRISE = tFALL= 400 ns
Figure 39. Transient Load Step Response; AUTO mode,
IOUT 0.5 mA → 500 mA → 0.5 mA, tRISE = tFALL= 100 ns
VIN 500 mV/DIV
VOUT AC COUPLED
10 mV/DIV
VOUT AC COUPLED
10 mV/DIV
SW 1 V/DIV
TIME 40 Ps/DIV
TIME 200 ns/DIV
Figure 40. Transient Line Response; IOUT = 2000 mA DC
44
Figure 41. Output Voltage Ripple, PWM Mode. IOUT = 200
mA; One Phase Active
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NRST 2 V/DIV
VOUT AC COUPLED
10 mV/DIV
VOUT 200 mV/DIV
SW 1 V/DIV
SW 5 V/DIV
TIME 400 Ps/DIV
TIME 20 Ps/DIV
Figure 42. Output Voltage Ripple, PFM Mode. IOUT = 100 µA
Figure 43. Start-up with NRST, No Load
NRST 2 V/DIV
VNRST 2V/DIV
VOUT 200 mV/DIV
LOAD 1 A/DIV
VOUT 500mV/DIV
SW 5 V/DIV
IL 500mA/DIV
TIME 10ms/DIV
TIME 20 Ps/DIV
Figure 44. Start-up with NRST, 3-A Load
Figure 45. Shutdown with NRST, VIN = 3.7 V, VOUT = 1.1 V,
No Load, Forced PWM
VIN 500mV/DIV
VOUT AC COUPLED 10mV/DIV
lL_B0 200mA/DIV
VOUT 200mV/DIV
lLOAD 1A/DIV
TIME 100ms/DIV
TIME 400us/DIV
Figure 46. Load ramp 4.5 A → 0 A → 4.5 A
Figure 47. VOUT Transition from 0.6 V to 1.4 V with
Different Ramp Settings, VIN = 3.7 V
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SW 2 V/DIV
VOUT 200 mV/DIV
INT 500 mV/DIV
VOUT 200 mV/DIV
LOAD 5 A/DIV
INT 500 mV/DIV
TIME 400 Ps/DIV
TIME 10 Ps/DIV
Figure 48. Interrupt Line Going Low with Not Power Good
Activation
46
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Figure 49. Metallic Short Applied at VOUT
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SNVSA20A – NOVEMBER 2013 – REVISED FEBRUARY 2015
9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 2.5 V and 5 V. This input supply
should be well regulated and able to withstand maximum input current and maintain stable voltage without
voltage drop even at load transition condition. The resistance of the input supply rail should be low enough that
the input current transient does not cause too high drop in the LP8755 supply voltage that can cause false UVLO
fault triggering. If the input supply is located more than a few inches from the LP8755 additional bulk capacitance
may be required in addition to the ceramic bypass capacitors.
10 Layout
10.1 Layout Guidelines
The high frequency and large switching currents of the LP8755 make the choice of layout important. Good power
supply results will only occur when care is given to proper design and layout. Bad layout will affect noise pickup
and generation and can cause a good design to perform with less-than-expected results. With a range of output
currents from milliamps to 10 A and over, good power-supply layout is more challenging than for most general
PCB design. The following steps should be used as a reference to ensure the device is stable and maintains
proper voltage and current regulation across its intended operating voltage and current range:
1. Place CIN as close as possible to the VINBXX pin and the GND pin. Route the VIN trace wide and thick to
avoid IR drops. The trace between the input capacitor's positive node and LP8755’s VINBXX pin(s) as well
as the trace between the input capacitor's negative node and power GND pin(s) must be kept as short as
possible. The input capacitance provides a low-impedance voltage source for the switching converter.
2. The output filter for each buck, consisting of COUT and L, converts the switching signal at SW to the noiseless
output voltage. For optimal EMI behavior, it should be placed as close as possible to the device, keeping the
switch node small. Route the traces between the LP8755's output capacitors and the load's input capacitors
direct and wide to avoid losses due to the IR drop.
3. Input for analog blocks (VDDA5V and GNDA) should be isolated from noisy signals. Connect VDDA5V
directly to a quiet system voltage node and GNDA to a quiet ground point where no IR drop occurs. For
additional noise immunity, adding a high-frequency decoupling capacitor of 100 nF to 1 µF is recommended.
Place the decoupling capacitor as close to the VDDA5V pin as possible. VDDA5V trace is low current, so the
trace width does not need to be optimized.
4. If the processor load supports voltage remote sensing, connect the LP8755 feedback pins FBBXX to the
respective sense pins on the processor. The sense lines are susceptible to noise. They must be kept away
from noisy signals such as GNDBXX, VIN, and SW, as well as high bandwidth signals such as the I2C. Avoid
both capacitive as well as inductive coupling by keeping the sense lines short, direct, and close to each
other. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane if possible.
Running the signal as a differential pair is recommended.
5. GNDBXX, VIN, and SW should be routed on thick layers. They must not surround inner signal layers which
are not able to withstand interference from noisy GNDBXX, VIN, and SW. This can create noise coupling to
inner signal layers.
Due to the small package of this converter and the overall small solution size, the thermal performance of the
PCB layout is important. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and
convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of
a given component. Proper PCB layout, focusing on thermal performance, results in lower die temperatures.
Wide power traces come with the ability to sink dissipated heat. This can be improved further on multi-layer PCB
designs with vias to different planes. This results in reduced junction-to-ambient (RθJA) and junction-to-board
(RθJB) thermal resistances, thereby reducing the device junction temperature, TJ. It's strongly recommended to
perform a careful system-level 2D or full 3D dynamic thermal analysis at the beginning of the product design
process, using a thermal modeling analysis software.
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SNVSA20A – NOVEMBER 2013 – REVISED FEBRUARY 2015
www.ti.com
10.2 Layout Example
Via to GND plane
Via to VIN plane
VOUT
L1
COUT1
L2
L0
COUT0
CIN5
CIN1
GND
VIN
Pin A1
GND
VIN
B2
VIN
CVDDA
SW
B2
GND
B1/
B2
SW
B1
VIN
B0/
B1
SW
B0
GND
B0
VIN
B2
SW
B2
GND
B1/
B2
SW
B1
VIN
B0/
B1
SW
B0
GND
B0
SDA
SYS
SCL
SYS
GND
B1/
B2
ADD
R
VIN
B0/
B1
NSLP
VLD
O
FB
B5
FB
B3-/
B4
FB
B3+/
B3
FB
B2
FB
B0-/
B1
FB
B0+/
B0
GND
A
SDA
SR
SCL
SR
GND
B4/
B5
NRS
T
VIN
B3/
B4
INT
VIO
SYS
VDD
A5V
SW
B5
GND
B4/
B5
SW
B4
VIN
B3/
B4
SW
B3
GND
B3
VIN
B5
SW
B5
GND
B4/
B5
SW
B4
VIN
B3/
B4
SW
B3
GND
B3
VIN
CIN7
CIN4
CIN0
VIN
GND
CIN3
GND
VIN
CIN2
CLDO
GND
CVIOSYS
CIN6
GND
COUT2
L5
L3
COUT3
L4
Figure 50. LP8755 Board Layout
48
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LP8755
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SNVSA20A – NOVEMBER 2013 – REVISED FEBRUARY 2015
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
Texas Instruments Application Note DSBGA Wafer-Level Chip-Scale Package (SNVA009).
11.3 Trademarks
SmartReflex is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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49
PACKAGE OPTION ADDENDUM
www.ti.com
4-Sep-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LP8755KME/NOPB
NRND
DSBGA
YFQ
49
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
8755
LP8755KMX/NOPB
NRND
DSBGA
YFQ
49
1000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
8755
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
4-Sep-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Aug-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
LP8755KME/NOPB
DSBGA
YFQ
49
250
180.0
13.0
LP8755KMX/NOPB
DSBGA
YFQ
49
1000
180.0
13.0
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.06
3.2
0.71
8.0
12.0
Q1
3.06
3.2
0.71
8.0
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Aug-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LP8755KME/NOPB
DSBGA
YFQ
LP8755KMX/NOPB
DSBGA
YFQ
49
250
200.0
230.0
25.0
49
1000
200.0
230.0
25.0
Pack Materials-Page 2
MECHANICAL DATA
YFQ0049xxx
D
0.600±0.075
E
TMD49XXX (Rev A)
4215087/A
NOTES:
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
www.ti.com
12/12
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