LP87702-Q1
SNVSAL1C – DECEMBER 2017 – REVISED JUNE 2021
LP87702-Q1 Dual Buck Converter and 5-V Boost With Diagnostic Functions
•
1 Features
•
•
•
•
•
•
•
•
AEC-Q100 Qualified for Automotive Applications:
– Device Temperature Grade 1: –40°C to
+125°C, TA
Functional Safety Quality-Managed
– Documentation Available to Aid Functional
Safety System Design
– Two Inputs for External Voltage Monitoring
– Two Programmable Power-Good Signals
– Dedicated Reference Voltage for Diagnostics
– Window Watchdog with Reset Output
– Output Short-Circuit and Overload Protection
– Overtemperature Warning and Protection
– Overvoltage Protection (OVP) and
Undervoltage Lockout (UVLO)
Two High-Efficiency Step-Down DC/DC
converters:
– Maximum Output Current 3.5 A
– 2-MHz, 3-MHz, or 4-MHz Switching Frequency
– Auto PWM/PFM and Forced-PWM Operations
– Output Voltage = 0.7 V to 3.36 V
5-V Boost Converter
– Maximum Output Current 600 mA
External Clock Input to Synchronize Switching
Spread-Spectrum Modulation
Programmable Start-up and Shutdown Delays and
Sequencing with Enable Signal
Configurable General Purpose Outputs (GPOs)
I2C-Compatible Interface Supporting Standard
(100 kHz), Fast (400 kHz), Fast+ (1 MHz), and
High-Speed (3.4 MHz) Modes
VIN
2 Applications
•
•
•
•
•
The LP87702-Q1 helps meet the power management
requirements of the latest platforms, particularly in
automotive radar and camera and industrial radar
applications. The device contains two step-down
DC/DC converters, and a 5-V boost converter
to support safety critical applications. The device
integrates two voltage monitoring inputs for external
power supplies and a window watchdog.
The automatic PWM/PFM (AUTO mode) operation
gives high efficiency over a wide output current range
for buck converters. The LP87702-Q1 uses remote
voltage sensing to compensate IR drop between the
converter output and the point-of-load, thus improving
the accuracy of the output voltage.
Device Information(1)
PART NUMBER
LP87702-Q1
(1)
SW_B0
VIN_B1
PACKAGE
BODY SIZE (NOM)
VQFN (32)
5.00 mm × 5.00 mm
See the orderable addendum at the end of the data sheet for
all available packages.
100
VOUT0
VIN_B0
Automotive Radar
Automotive Camera
Automotive Sensor Fusion
Industrial Radar
Building Automation
3 Description
LOAD
FB_B0
VANA
90
SW_BST
VOUT1
SW_B1
LOAD
NRST
FB_B1
SDA (EN3)
SCL (EN2)
nINT
VOUT2
EN1
VOUT_BST
Efficiency (%)
•
Interrupt Function with Programmable Masking
80
70
LOAD
CLKIN (GPO2/WD_DIS)
PG0
VMON1
PG1 (GPO1)
VMON2
GPO0
WDI
GNDs
60
VIN=3.3V, VOUT=1.2V
VIN=3.3V, VOUT=1.8V
VIN=3.3V, VOUT=2.3V
WD_RESET
50
1
Copyright © 2017, Texas Instruments Incorporated
Simplified Schematic
10
100
Output Current (mA)
1000
5000
Exce
Buck Efficiency vs Output Current
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP87702-Q1
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SNVSAL1C – DECEMBER 2017 – REVISED JUNE 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings............................................................... 6
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information....................................................7
7.5 Electrical Characteristics.............................................7
7.6 I2C Serial Bus Timing Parameters............................ 13
7.7 Typical Characteristics.............................................. 15
8 Detailed Description......................................................16
8.1 Overview................................................................... 16
8.2 Functional Block Diagram......................................... 17
8.3 Feature Descriptions.................................................17
8.4 Device Functional Modes..........................................40
8.5 Programming............................................................ 42
8.6 Register Maps...........................................................45
9 Application and Implementation.................................. 79
9.1 Application Information............................................. 79
9.2 Typical Application.................................................... 79
10 Power Supply Recommendations..............................88
11 Layout........................................................................... 88
11.1 Layout Guidelines................................................... 88
11.2 Layout Example...................................................... 89
12 Device and Documentation Support..........................90
12.1 Third-Party Products Disclaimer............................. 90
12.2 Receiving Notification of Documentation Updates..90
12.3 Support Resources................................................. 90
12.4 Trademarks............................................................. 90
12.5 Electrostatic Discharge Caution..............................90
12.6 Glossary..................................................................90
13 Mechanical, Packaging, and Orderable
Information.................................................................... 90
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (September 2019) to Revision C (June 2021)
Page
• Functional safety related features moved under Functional Safety Quality-Managed....................................... 1
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Changed multiple register bit descriptions........................................................................................................45
Changes from Revision A (July 2018) to Revision B (September 2019)
Page
• Added FMEDA and Functional Safety Manual support availability feature........................................................ 1
• Changed Description wording.............................................................................................................................1
• Added test condition .......................................................................................................................................... 7
• Changed from typical value to max value ..........................................................................................................7
• Added comment on VANAOVP setting and it's impact on device input voltage range ...................................... 16
• Added comment on minimum WDI pulse length...............................................................................................26
• Changed BOOST_SC_INT bit set delay from immediate to 1 ms ................................................................... 36
• Changed multiple register bit descriptions........................................................................................................45
Changes from Revision * (December 2017) to Revision A (July 2018)
Page
• First release of production-data data sheet ....................................................................................................... 1
2
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SNVSAL1C – DECEMBER 2017 – REVISED JUNE 2021
5 Description (continued)
Programmable start-up and shutdown sequences synchronized to the enable signal are supported, including
general purpose digital outputs.
During start-up and voltage change, the device controls the output slew rate for minimum output voltage
overshoot and inrush current. This device contains one-time-programmable (OTP) memory. Each orderable
part number has specific OTP settings for a given application. Details of the default OTP configuration for each
orderable part number can be found in the technical reference manual.
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SNVSAL1C – DECEMBER 2017 – REVISED JUNE 2021
6 Pin Configuration and Functions
24
23
22
21
20
19
18
17
PGND_B0
PGND_B0
CLK(GPO2)
SDA (EN3)
SCL (EN2)
EN1
PGND_B1
PGND_B1
25
SW_B0
SW_B1
16
26
SW_B0
SW_B1
15
27
VIN_B0
VIN_B1
14
28
VIN_B0
VIN_B1
13
THERMAL PAD
29
PG0
GPO0
12
30
VMON1
NRST
11
31
VMON2
PGND_BST
10
32
PG1 (GPO1)
SW_BST
nINT
FB_B0
FB_B1
AGND
VANA
WD_RESET
WDI
VOUT_BST
1
2
3
4
5
6
7
8
9
Figure 6-1. RHB Package 32-Pin VQFN With Thermal Pad Top View
Table 6-1. Pin Functions
PIN
4
TYPE
DESCRIPTION
NAME
NUMBER
AGND
4
G
CLKIN
22
D/I/O
EN1
19
D/I
FB_B0
2
A
Output voltage feedback for Buck0.
FB_B1
3
A
Output voltage feedback for Buck1.
GPO0
12
D/O
General purpose digital output 0.
nINT
1
D/O
Open-drain interrupt output. Active LOW.
Ground
External clock input. Alternative function is general purpose digital output 2 (GPO2). Second
alternative function is watchdog disable (WD_DIS)
Programmable Enable 1 signal.
NRST
11
D/I
Reset signal for the device.
PG0
29
D/O
Programmable power-good indication signal.
PG1
32
D/O
Programmable power-good indication signal. Alternative function is general purpose digital output
1 (GPO1).
PGND_B0
23, 24
P/G
Power ground for Buck0.
PGND_B1
17, 18
P/G
Power Ground for Buck1.
PGND_BST
10
P/G
Power ground for boost.
SCL
20
D/I
Serial interface clock input for I2C access. Connect a pullup resistor. Alternative function is
programmable to the enable 2 signal.
SDA
21
D/I/O
Serial interface data input and output for I2C access. Connect a pullup resistor. Alternative
function is programmable to the enable 3 signal.
SW_B0
25, 26
P/O
Buck0 switch node.
SW_B1
15, 16
P/O
Buck1 switch node.
SW_BST
9
P/I
Boost input. Bypass switch input when this mode is selected.
VANA
5
P
Supply voltage for analog and digital blocks. Must be connected to same node with VIN_Bx.
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Table 6-1. Pin Functions (continued)
PIN
NAME
NUMBER
TYPE
DESCRIPTION
VMON1
30
A/I
Voltage monitoring input 1.
VMON2
31
A/I
Voltage monitoring input 2.
VIN_B0
27, 28
P/I
Input for Buck0. The separate power pins VIN_Bx are not connected together internally – VIN_Bx
pins must be connected together in the application and be locally bypassed.
VIN_B1
13, 14
P/I
Input for Buck1. The separate power pins VIN_Bx are not connected together internally – VIN_Bx
pins must be connected together in the application and be locally bypassed.
VOUT_BST
8
P/O
Boost output. Bypass switch output when this mode is selected.
WD_RESET
6
D/O
Reset output from window watchdog
7
D/I
Digital input signal for window watchdog
N/A
G
WDI
Thermal pad
A: Analog Pin, D: Digital Pin, G: Ground Pin, P: Power Pin, I: Input Pin, O: Output Pin
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
MAX
–0.3
6
UNIT
VIN_B0,
VIN_B1, SW_BST,
VANA
Voltage on input power connections
SW_B0, SW_B1
Voltage on buck switch nodes
–0.3
(VIN_Bx + 0.3 V) with
6-V maximum
V
FB_B0, FB_B1
Voltage on buck voltage sense nodes
–0.3
(VANA + 0.3 V) with
6-V maximum
V
VOUT_BST
Voltage on boost output
–0.3
6
V
SCL (EN2), SDA (EN3), Voltage on voltage monitoring pins
VMON1, VMON2
–0.3
(VANA + 0.3 V) with
6-V maximum
V
NRST, EN1, nINT
V
Voltage on logic pins (input or output pins)
–0.3
6
V
PG0, PG1 (GPO1),
Voltage on logic pins (input or output pins)
GPO0, CLKIN (GPO2),
WDI, WD_RESET
–0.3
(VANA + 0.3 V) with
6-V maximum
V
TJ-MAX
Junction temperature
−40
150
°C
Tstg
Storage temperature
–65
150
°C
260
°C
Maximum lead temperature (soldering, 10 sec.)
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltage values are with respect to network ground.
7.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC
V(ESD)
(1)
Electrostatic discharge
Q100-002(1)
Charged-device model (CDM), per AEC
Q100-011
UNIT
±2000
All pins
±500
Corner pins (1, 8, 9, 16, 17,
24, 25, 32)
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
2.8
5.5
V
V
INPUT VOLTAGE
VIN_B0, VIN_B1, SW_BST, VANA
Voltage on input power connections
VMON1, VMON2
Voltage on voltage monitoring pins
0
5.5
NRST, EN1, EN2, EN3, nINT
Voltage on logic pins (input or output pins)
0
5.5
PG0, PG1 (GPO1), GPO0, CLKIN
(GPO2), WDI, WD_RESET
Voltage on logic pins (input or output pins)
0
VANA
V
Voltage on I2C interface, Standard (100 kHz), Fast
(400 kHz), Fast+ (1 MHz), and High-Speed (3.4
MHz) Modes
0
1.95
V
Voltage on I2C interface, Standard (100 kHz), Fast
(400 kHz), and Fast+ (1 MHz) Modes
0 VANA with 3.6-V
maximum
V
SCL, SDA
TEMPERATURE
Junction temperature, TJ
6
−40
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140
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over operating free-air temperature range (unless otherwise noted)
Ambient temperature, TA
MIN
MAX
UNIT
−40
125
°C
7.4 Thermal Information
RHB (VQFN)
THERMAL METRIC(1)
32 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
31.7
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
17.1
°C/W
RθJB
Junction-to-board thermal resistance
5.6
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
5.6
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
1.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
Limits apply over the junction temperature range –40°C ≤ TJ ≤ 140°C, specified VVANA, VVIN_Bx, VVOUT_Bx, VVOUT_BST, and
IOUT range, unless otherwise noted. Typical values are at TA = 25°C, VVANA = VVIN_Bx = 3.3 V, VOUT_BST = 5 V and VOUT_Bx =
1 V, unless otherwise noted. (1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
Input filtering capacitance Effective capacitance, connected from
for buck converters
VIN_Bx to PGND_Bx
1.9
10
Output filtering
capacitance for buck
converters
Effective total capacitance. Maximum
includes POL capacitance
15
22
Point-of-load (POL)
capacitance for buck
converters
Optional POL capacitance
MAX
UNIT
EXTERNAL COMPONENTS
CIN_BUCK
COUT_BUC
K
COUT_BUC
K_POL
Output filtering
COUT_BST capacitance for boost
converter
Effective capacitance
ESRC
Input and output
capacitor ESR
[1-10] MHz
LBUCK
Inductor for buck
converters
Inductance of the inductor
LBST
Inductor for boost
converters
DCRL
100
22
10
µF
µF
22
40
µF
2
10
mΩ
0.47
–30%
Inductance of the inductor, 2-MHz switching
30%
µH
1
Inductance of the inductor, 4-MHz switching
Inductance of the inductor
µF
µH
1
–30%
Inductor DCR
30%
25
mΩ
BUCK CONVERTERS
V(VIN_Bx),
V(VANA)
Input voltage range
2.8
Programmable voltage range
VOUT_Bx
IOUT_Bx
Output voltage
Output current
Step size, 0.7 V ≤ VOUT < 0.73 V
0.7
3.3
5.5
V
1
3.36
V
10
Step size, 0.73 V ≤ VOUT < 1.4 V
5
Step size, 1.4 V ≤ VOUT ≤ 3.36 V
20
Output current
mV
3.5 (3)
A
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Limits apply over the junction temperature range –40°C ≤ TJ ≤ 140°C, specified VVANA, VVIN_Bx, VVOUT_Bx, VVOUT_BST, and
IOUT range, unless otherwise noted. Typical values are at TA = 25°C, VVANA = VVIN_Bx = 3.3 V, VOUT_BST = 5 V and VOUT_Bx =
1 V, unless otherwise noted. (1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
V(VIN_Bx) – VOUT, IOUT_Bx ≤ 2 A
0.8
V(VIN_Bx) – VOUT, IOUT_Bx > 2 A
1
DC output voltage
accuracy, includes
voltage reference, DC
load and line regulations,
process and temperature
Force PWM mode, VOUT ˂ 1.0 V
–20
20
Force PWM mode, VOUT ≥ 1.0 V
–2%
2%
–20
40
–2%
2% + 20mV
PFM mode, VOUT ˂ 1.0 V, the average output
voltage level is increased by max. 20 mV
PFM mode, VOUT ≥ 1.0 V, the average output
voltage level is increased by max. 20 mV
Ripple voltage
UNIT
V
PWM mode, VOUT = 1.2 V, fSW = 4 MHz,
COUT = 22 + 22 µF (GCM31CR71A226KE02)
5
PFM mode, L = 0.47 µH, COUT = 22 + 22 µF
(GCM31CR71A226KE02)
25
mV
mV
mVp-p
DCLNR
DC line regulation
IOUT = IOUT(max)
±0.05
DCLDR
DC load regulation in
PWM mode
VOUT_Bx = 1.0 V, IOUT from 0 to IOUT(max)
0.3%
TLDSR
Transient load step
response
IOUT = 0 A to 3 A, TR = TF = 1 µs, PWM
mode, VVIN_Bx = 3.3V, VOUT_Bx = 1.2 V, COUT
= 22 + 22 µF, L = 0.47 µH, fSW = 4 MHz
±65
mV
TLNSR
Transient line response
V(VIN_Bx) stepping 3 V ↔ 3.5 V, TR = TF = 10
µs, IOUT = IOUT(max)
±20
mV
ILIM FWD
Forward current limit for
both bucks (peak for
every switching cycle)
ILIM NEG
Negative current limit
Programmable range
RDS(ON)
BUCK HS
FET
RDS(ON)
BUCK LS
FET
ƒSW
1.5
Step size
%/V
4.5
0.5
Accuracy, V(VIN_Bx) ≥ 3 V, ILIM = 4 A
Accuracy, 2.8 V ≤ V(VIN_Bx) < 3 V, ILIM = 4 A
–5%
7.5%
20%
–20%
7.5%
20%
1.6
2
3
A
A
On-resistance, high-side
FET
Each phase, between VIN_Bx and SW_Bx
pins (I = 1.0 A)
60
110
mΩ
On-resistance, low-side
FET
Each phase, between SW_Bx and PGND_Bx
pins (I = 1.0 A)
55
80
mΩ
Switching frequency,
PWM mode
OTP programmable
Start-up time (soft start)
2-MHz setting or VOUT_Bx < 0.8 V
1.8
2
2.2
3-MHz setting and VOUT_Bx ≥ 0.8 V
2.7
3
3.3
4-MHz setting and VOUT_Bx ≥ 1.1 V
3.6
4
4.4
From ENx to VOUT_Bx = 0.35 V (slew-rate
control begins)
120
Overshoot during start-up
8
MAX
Minimum voltage
difference between
V(VIN_Bx) and VOUT_Bx for
electrical characteristics
MHz
µs
50
mV
Output voltage slewrate(4)
SLEW_RATEx[2:0] = 010, VVOUT_Bx ≥ 0.7 V
–15%
10
15% mV/µs
Output voltage slewrate(4)
SLEW_RATEx[2:0] = 011, VVOUT_Bx ≥ 0.7 V
–15%
7.5
15% mV/µs
Output voltage slewrate(4)
SLEW_RATEx[2:0] = 100, VVOUT_Bx ≥ 0.7 V
–15%
3.8
15% mV/µs
Output voltage slewrate(4)
SLEW_RATEx[2:0] = 101, VVOUT_Bx ≥ 0.7 V
–15%
1.9
15% mV/µs
Output voltage slewrate(4)
SLEW_RATEx[2:0] = 110, VVOUT_Bx ≥ 0.7 V
–15%
0.94
15% mV/µs
Output voltage slewrate(4)
SLEW_RATEx[2:0] = 111, VVOUT_Bx ≥ 0.7 V
–15%
0.47
15% mV/µs
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Limits apply over the junction temperature range –40°C ≤ TJ ≤ 140°C, specified VVANA, VVIN_Bx, VVOUT_Bx, VVOUT_BST, and
IOUT range, unless otherwise noted. Typical values are at TA = 25°C, VVANA = VVIN_Bx = 3.3 V, VOUT_BST = 5 V and VOUT_Bx =
1 V, unless otherwise noted. (1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IPFM-PWM
PFM-to-PWM switch current threshold(5)
520
mA
IPWM-PFM
PWM-to-PFM switch current threshold(5)
240
mA
Output pull-down
resistance
Converter disabled
75
125
175
Ω
2.8
3.3
4
V
5.5
V
BOOST CONVERTER
Input voltage range for
boost power inputs
VIN_BST
VOUT_BST
Input voltage range when
bypass switch mode
selected
Output voltage, boost
mode
4.5
BOOST_VSET = 00
4.9
BOOST_VSET = 01
5.0
BOOST_VSET = 10
5.1
BOOST_VSET = 11
5.2
V
IOUT_BST
Output current
Both boost and bypass mode
0.6
A
ILIM_BST
Output current limit
BOOST_ILIM = 00, VIN_BST < 3.6 V
0.8
1
1.3
A
BOOST_ILIM = 01, VIN_BST < 3.6 V
1.1
1.4
1.9
BOOST_ILIM = 10, VIN_BST < 3.6 V
1.5
1.9
2.3
BOOST_ILIM = 11, VIN_BST < 3.6 V
2.2
2.8
3.4
VOUT_BST
_DC
VDROP
DC output voltage
accuracy, includes
voltage reference, DC
Default output voltage
load and line regulations,
process and temperature.
Boost mode
Voltage drop, bypass
mode,
Ripple voltage, boost
mode
–3%
3%
Iout = 250 mA
83
22 µF effective output capacitance
20
mV
mVp-p
DCLDR
DC load regulation, boost
IOUT = 1 mA to IOUT(max)
mode
TLDSR
Transient load step
response, boost mode
IOUT = 1 mA to 250 mA, TR = TF = 1 µs, 22
µF effective output capacitance, VIN > 3 V
ISHORT
Short circuit current
limitation
During start-up, both boost and bypass
mode. Short circuit current limit applies until
VOUT_BST = VIN_BST
625
On-resistance, high-side
FET
Pin-to-pin, between SW_BST and
VOUT_BST pins (I = 250 mA)
145
220
mΩ
On-resistance, low-side
FET
Pin-to-pin, between SW_BST and
PGND_BST pins (I = 250 mA)
90
175
mΩ
Switching frequency,
boost mode
2-MHz setting
1.8
2
2.2
MHz
4-MHz setting
3.6
4
4.4
MHz
RDS(ON)
BST HS FET
RDS(ON)
BST LS FET
ƒSW
0.3%
–220
220
mV
mA
From enable to boost VOUT within 3% of
Start-up time, boost mode
target value. COUT_BST = 22 µF
450
µs
Output pull-down
resistance
135
Ω
Converter disabled
EXTERNAL CLOCK AND PLL
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LP87702-Q1
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SNVSAL1C – DECEMBER 2017 – REVISED JUNE 2021
Limits apply over the junction temperature range –40°C ≤ TJ ≤ 140°C, specified VVANA, VVIN_Bx, VVOUT_Bx, VVOUT_BST, and
IOUT range, unless otherwise noted. Typical values are at TA = 25°C, VVANA = VVIN_Bx = 3.3 V, VOUT_BST = 5 V and VOUT_Bx =
1 V, unless otherwise noted. (1) (2)
PARAMETER
TEST CONDITIONS
Nominal frequency
External input clock(6)
TYP
1
Nominal frequency step size
Required accuracy from nominal frequency
External clock detection
MIN
MAX
24
1
–30%
UNIT
MHz
10%
Delay for detecting loss of external clock,
nominal internal clock, clock accuracy ±10%
1.8
Delay for detecting valid external clock,
nominal internal clock, clock accuracy ±10%
20
µs
Clock change delay
(internal to external)
Delay from valid clock detection to use of
external clock
600
µs
PLL output clock jitter
Cycle to cycle
300
ps, p-p
Voltage threshold, VANA_THRESHOLD = 0
3.3
Voltage threshold, VANA_THRESHOLD = 1
5.0
MONITORING FUNCTIONS
V
VANA Voltage Monitoring Voltage window, VANA_WINDOW = 00
±3%
±4%
±5%
Voltage window, VANA_WINDOW = 01
±4%
±5%
±6%
Voltage window, VANA_WINDOW = 10 or 11
±9%
±10%
±11%
VMON1 and VMON2
Voltage Monitoring
Thresholds
VMONx_THRESHOLD = 000
0.65
VMONx_THRESHOLD = 001
0.8
VMONx_THRESHOLD = 010
1.0
VMONx_THRESHOLD = 011
1.1
VMONx_THRESHOLD = 100
1.2
VMONx_THRESHOLD = 101
1.3
VMONx_THRESHOLD = 110
1.8
VMONx_THRESHOLD = 111
1.8
V
VMONx_WINDOW = 00,
VMONx_THRESHOLD from 000 to 111
±1%
±2%
±3%
VMONx_WINDOW = 01,
VMONx_THRESHOLD from 000 to 111
±2%
±3%
±4%
VMONx_WINDOW = 10,
VMONx_THRESHOLD from 000 to 111
±3%
±4%
±5%
±5%
±6%
±7%
BUCKx_WINDOW = 00
±20
±30
±40
Buck0 and Buck1 Voltage BUCKx_WINDOW = 01
Monitoring Windows
BUCKx_WINDOW = 10
±37
±50
±63
±57
±70
±83
VMON1 and VMON2
Voltage Monitoring
Windows
VMONx_WINDOW = 11,
VMONx_THRESHOLD from 000 to 111
Boost Voltage Monitoring
Deglitch time
BUCKx_WINDOW = 11
±77
±90
±103
BOOST_WINDOW = 00
±0.6%
±2%
±3.4%
BOOST_WINDOW = 01
±2.6%
±4%
±5.4%
BOOST_WINDOW = 10
±4.6%
±6%
±7.4%
BOOST_WINDOW = 11
±6.6%
±8%
±9.4%
VANA, VMONx and BOOST monitoring
BUCKx monitoring
12
17
6
9
mV
μs
PROTECTION FUNCTIONS
Thermal warning
Temperature rising, TDIE_WARN_LEVEL = 0
115
125
135
Temperature rising, TDIE_WARN_LEVEL = 1
130
140
150
Hysteresis
10
°C
20
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Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: LP87702-Q1
LP87702-Q1
www.ti.com
SNVSAL1C – DECEMBER 2017 – REVISED JUNE 2021
Limits apply over the junction temperature range –40°C ≤ TJ ≤ 140°C, specified VVANA, VVIN_Bx, VVOUT_Bx, VVOUT_BST, and
IOUT range, unless otherwise noted. Typical values are at TA = 25°C, VVANA = VVIN_Bx = 3.3 V, VOUT_BST = 5 V and VOUT_Bx =
1 V, unless otherwise noted. (1) (2)
PARAMETER
Thermal shutdown
VANAOVP VANA Overvoltage
TEST CONDITIONS
Temperature rising
BUCKx short circuit
detection
TYP
MAX
140
150
160
Hysteresis
20
Voltage rising, VANA_OVP_SEL = 0
5.6
5.8
6.1
Voltage falling, VANA_OVP_SEL = 0
5.45
5.73
5.96
Voltage rising, VANA_OVP_SEL = 1
4.1
4.3
4.6
Voltage falling, VANA_OVP_SEL = 1
3.95
4.23
4.46
Hysteresis
VANAUVL VANA Undervoltage
Lockout
O
MIN
40
200
UNIT
°C
V
mV
Voltage rising
2.51
2.63
2.75
Voltage falling
2.5
2.6
2.7
0.32
0.35
0.45
V
270
420
mA
Threshold
Bypass short circuit
current limit
V
LOAD CURRENT MEASUREMENT FOR BUCK CONVERTERS
Current measurement
range
Current corresponding to maximum output
code (note: maximum current for LP87702
buck is 3.5A)
Resolution
LSB
Measurement accuracy
IOUT > 1A
Measurement time
Auto mode (automatically changing to PWM
mode for the measurement)
10.22
20
A
mA
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