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Design
LP8860-Q1
SNVSA21G – MAY 2014 – REVISED OCTOBER 2017
LP8860-Q1 Low-EMI Automotive LED Driver With Four 150-mA Channels
1 Features
2 Applications
•
•
•
1
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Input Voltage Operating Range 3 V to 48 V
Four High-Precision Current Sinks
– Current Matching 0.5% (typical)
– LED String Current up to 150 mA per Channel
– Dimming Ratio > 13 000:1 With External PWM
Brightness Control
– 16-bit Dimming Control with SPI or I2C
– Supports Display Mode (Global Dimming) and
Cluster Mode (Independent Dimming)
Hybrid PWM and Current Dimming for Higher LED
Drive Optical Efficiency
Synchronization for LED PWM Frequency
Boost Controller With Programmable Switching
Frequency 100 kHz to 2.2 MHz and SpreadSpectrum Option for Lower EMI
Boost Synchronization Input
Power-Line FET Control for Inrush Current
Protection and Standby Energy Saving
Automatic LED Current Reduction With External
Temperature Sensor
Extensive Fault Diagnostics
Backlight for:
– Automotive Infotainment
– Automotive Instrument Clusters
– Smart Mirrors
– Heads-Up Displays (HUD)
– Central Information Displays (CID)
– Audio-Video Navigation (AVN)
3 Description
The LP8860-Q1 is an automotive high-efficiency LED
driver with boost controller. It has 4 high-precision
current sinks that can be controlled by a PWM input
signal, an SPI or I2C master, or both.
The boost converter has adaptive output voltage
control based on the headroom voltages of the LED
current sinks. This feature minimizes the power
consumption by adjusting the voltage to the lowest
sufficient level in all conditions. A wide-range
adjustable frequency allows the LP8860-Q1 to avoid
disturbance for AM radio band.
The LP8860-Q1 supports built-in hybrid PWM and
current dimming, which reduces EMI, extends the
LED lifetime, and increases the total optical
efficiency. Phase-shift PWM reduces audible noise
and output ripple.
Device Information(1)
PART NUMBER
Simplified Schematic
VIN
RISENSE
3...40 V
LP8860-Q1
D
L
Q2
Up to 48V
C2x
CIN
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
System Efficiency
Q1
C1N
95
GD
VSENSE_P
ISENSE
90
VDD 3.3V
RSENSE
VDD
Efficiency (%)
ISENSE_GND
CPUMP
FB
CVDD
SQW
FILTER
BOOST SYNC
Up to 150 mA/string
LP8860-Q1
SYNC
V/H SYNC
OUT1
VSYNC
BRIGHTNESS
PWM
OUT2
SCLK/SCL
OUT3
MOSI/SDA
VIN = 8 V
VIN = 12 V
VIN = 15 V
TSENSE
RT°
ISET
IF
FAULT
SGND
VIN = 6 V
75
65
VDDIO/EN
FAULT
VIN = 5 V
80
70
NSS
EN
85
OUT4
MISO
FAULT RESET
BODY SIZE (NOM)
7.00 mm × 7.00 mm
COUT
C1P
SD
VSENSE_N
CCPUMP
PACKAGE
HLQFP (32)
0
10
20
30
40
50
60
Brightness (%)
70
80
90
100
C001
NTC
PGND LGND
PAD
RISET
VDDIO
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP8860-Q1
SNVSA21G – MAY 2014 – REVISED OCTOBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
Electrical Characteristics .......................................... 7
Current Sinks Electrical Characteristics.................... 7
Boost Converter Characteristics ............................... 8
Logic Interface Characteristics.................................. 9
VIN Undervoltage Protection (VIN_UVLO) ................ 9
VDD Undervoltage Protection (VDD_UVLO) ......... 10
VIN Overvoltage Protection (VIN_OVP) ............... 10
VIN Overcurrent Protection (VIN_OCP) ............... 10
Power-Line FET Control Electrical
Characteristics ......................................................... 10
7.14 External Temp Sensor Control Electrical
Characteristics ......................................................... 10
7.15 I2C Serial Bus Timing Parameters (SDA, SCLK) . 12
7.16 SPI Timing Requirements ..................................... 12
7.17 Typical Characteristics .......................................... 13
8
Detailed Description ............................................ 14
8.1
8.2
8.3
8.4
8.5
8.6
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
14
17
18
48
49
55
Application and Implementation ........................ 85
9.1 Application Information............................................ 85
9.2 Typical Applications ................................................ 85
10 Power Supply Recommendations ..................... 99
11 Layout................................................................. 100
11.1 Layout Guidelines ............................................... 100
11.2 Layout Example .................................................. 101
12 Device and Documentation Support ............... 102
12.1 Device Support....................................................
12.2 Documentation Support ......................................
12.3 Receiving Notification of Documentation
Updates..................................................................
12.4 Community Resources........................................
12.5 Trademarks .........................................................
12.6 Electrostatic Discharge Caution ..........................
12.7 Glossary ..............................................................
102
102
102
102
102
102
102
13 Mechanical, Packaging, and Orderable
Information ......................................................... 102
4 Revision History
Changes from Revision F (July 2017) to Revision G
•
Page
Updated with more detailed package drawings ................................................................................................................. 102
Changes from Revision E (November 2016) to Revision F
Page
•
Changed placement of "7" data hold time in Figure 2 ......................................................................................................... 12
•
Deleted "The LP8860-Q1 doesn’t support incremental addressing." after Table 20 ........................................................... 51
•
Changed "short" to "open" in DRV_HEADER[2:0] row, EEPROM Register 4 ..................................................................... 70
Changes from Revision D (September 2016) to Revision E
Page
•
Deleted 4-A row from VOCP in VIN Overcurrent Protection (VIN_OCP) table........................................................................ 10
•
Changed "+ 150 mA" to "× 150 mA" in eq. 8 ...................................................................................................................... 41
•
Deleted "01/4A" row from Input voltage overcurrent protection in Table 16 ........................................................................ 43
•
Deleted duplicate of Figure 42 "State Diagram" .................................................................................................................. 48
•
Changed "open" to "short" in DRV_LED_FAULT_THR[1:0] row, EEPROM Register 4 ...................................................... 70
•
Changed "nit" to "not" - correct typo..................................................................................................................................... 71
•
Deleted "01 = 4 A" from PL_SD_LEVEL[1:0] in EEPROM Register 10 ............................................................................... 75
•
Updated orderable options in POA .................................................................................................................................... 102
•
Added pre-prod "R" orderable option in POA .................................................................................................................... 102
2
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LP8860-Q1
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SNVSA21G – MAY 2014 – REVISED OCTOBER 2017
Changes from Revision C (December 2015) to Revision D
Page
•
Changed title of data sheet ................................................................................................................................................... 1
•
Changed slight modification to wording of "Features" bullets ................................................................................................ 1
•
Deleted "Safety and" ............................................................................................................................................................. 1
•
Changed "Tolerance Features" to "Diagnostics" .................................................................................................................... 1
•
Deleted "SPI or I2C Interface"................................................................................................................................................. 1
•
Added additional Applications ............................................................................................................................................... 1
•
Changed "The high switching" to "A wide-range adjustable" ................................................................................................. 1
•
Deleted some wording in Description to make it more succinct; rewrite last sentence.......................................................... 1
•
Added Device Comparison table ............................................................................................................................................ 3
•
Deleted Table 19 "Default EEPROM Context" - this information now in SNVA757, available in mysecureSW only ......... 50
Changes from Revision B (March 2015) to Revision C
Page
•
Added Features bullets re: Automotive ................................................................................................................................. 1
•
Changed "safety" to "fault detection"...................................................................................................................................... 1
•
Changed "up to 40V" to "Up to 48V" in Simplified Schematic ............................................................................................... 1
•
Changed SPI Write Cycle and SPI Read Cycle diagrams .................................................................................................. 51
Changes from Revision A (June 2014) to Revision B
Page
•
Changed EXT_TEMP_MINUS[1:0] from "2, 6, 10, 14 μA" to "1, 5, 9, 13 µA"...................................................................... 41
•
Changed values for EXT_TEMP_MINUS from "2, 6, 10, 14 µA" to '1, 5, 9, 13 µA" ............................................................ 67
•
Added Documentation Support section ............................................................................................................................. 102
Changes from Original (May 2014) to Revision A
•
Page
Changed first sentence in paragraph beginning "EEPROM bits are intended to be set..." to 2 separate sentences ......... 50
5 Device Comparison Table
VIN range
Number of LED channels
LP8860-Q1
LP8862-Q1
LP8861-Q1
TPS61193-Q1
TPS61194-Q1
TPS61196-Q1
3 V to 48 V
4.5 V to 45 V
4.5 V to 45 V
4.5 V to 45 V
4.5 V to 45 V
8 V to 30 V
4
2
4
3
4
6
150 mA
160 mA
100 mA
100 mA
100 mA
200 mA
I2C/SPI support
Yes
No
No
No
No
No
SEPIC support
No
Yes
Yes
Yes
Yes
No
LED current / channel
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LP8860-Q1
SNVSA21G – MAY 2014 – REVISED OCTOBER 2017
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6 Pin Configuration and Functions
SD
CPUMP
GD
PGND
ISENSE
ISENSE_GND
FB
OUT1
32
31
30
29
28
27
26
25
VFP Package
32-Lead PowerPAD™ Quad Flatpack S-PQFP-G32
Top View
C1P
1
24
OUT2
C1N
2
23
LGND
VDD
3
22
OUT3
SQW
4
21
OUT4
VSENSE_N
5
20
IF
VSENSE_P
6
19
VDDIO/EN
ISET
7
18
PWM
17
NSS
EP*
9
10
11
12
13
14
15
16
SGND
FAULT
SYNC
VSYNC
MISO
MOSI/SDA
SCLK/SCL
8
FILTER
TSENSE
*EXPOSED PAD
4
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LP8860-Q1
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SNVSA21G – MAY 2014 – REVISED OCTOBER 2017
Pin Functions
PIN
NUMBER
NAME
TYPE (1)
DESCRIPTION
1
C1P
A
Positive pin for charge pump flying capacitor.
If feature is disabled, the pin may be left floating.
2
C1N
A
Negative pin for charge pump flying capacitor.
If feature is disabled, the pin may be left floating.
3
VDD
P
Input voltage pin for internal circuit.
4
SQW
A
Square wave output. Can be used for generating extra voltage rail.
If unused, the pin may be left floating.
5
VSENSE_N
A
Pin for input current sense.
6
VSENSE_P
A
Pin for OVP/UVLO protection and input current sense.
7
ISET
A
Optional resistor for setting LED maximum current.
If feature is disabled, the pin may be left floating.
8
TSENSE
A
External temperature sensor for LED current control.
If feature is disabled, the pin may be left floating.
9
FILTER
A
Low pass filter for PLL.
If feature is disabled, the pin may be left floating.
10
SGND
G
Signal ground.
11
FAULT
OD
12
SYNC
I
Input for synchronizing boost.
This pin must be connected to GND if not used.
13
VSYNC
I
Input for synchronizing PWM generation to display refresh.
This pin must be connected to GND if feature is disabled.
14
MISO
O
Slave data output (SPI). If unused, the pin may be left floating.
15
MOSI/SDA
I/O
Slave data input (SPI) or serial data (I2C).
This pin must be connected to GND if not used.
16
SCLK/SCL
I
Serial clock for SPI or I2C.
This pin must be connected to GND if not used.
17
NSS
I
Slave select (SPI mode) or fault reset (I2C or standalone mode).
This pin must be connected to GND if not used.
18
PWM
I
PWM dimming input.
This pin must be connected to GND if feature is disabled.
19
VDDIO/EN
I
Enable input pin and reference voltage for digital pins.
20
IF
I
Interface selection: low – I2C or standalone mode; high – SPI.
21
OUT4
A
LED current sink output.
If unused, the pin may be left floating.
22
OUT3
A
LED current sink output.
If unused, the pin may be left floating.
23
LGND
G
LED current ground.
24
OUT2
A
LED current sink output.
If unused, the pin may be left floating.
25
OUT1
A
LED current sink output.
If unused, the pin may be left floating.
26
FB
A
Boost feedback input.
27
ISENSE_GND
A
Boost controller’s current sense resistor GND.
28
ISENSE
A
Boost current sense pin.
29
PGND
G
Power ground.
30
GD
A
Gate driver output for boost FET.
31
CPUMP
P
Charge pump output pin.
32
SD
A
Power line FET control.
If unused, the pin may be left floating.
(1)
Fault signal output.
If unused, the pin may be left floating.
A: Analog pin, G: Ground pin, P: Power pin, I: Input pin, I/O: Input/Output pin, O: Output pin, OD: Open Drain pin
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SNVSA21G – MAY 2014 – REVISED OCTOBER 2017
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
Voltage on pins VSENSE_N, VSENSE_P, OUT1 to OUT4, FB, SD
–0.3
52
V
Voltage on pins VDD, FILTER, SYNC, VSYNC, PWM, SCLK/SCL, MOSI/SDA, MISO, NSS,
VDDIO/EN, IF, ISENSE, ISENSE_GND, FAULT, ISET, TSENSE, C1N
–0.3
6
V
Voltage on pins C1P, CPUMP, GD, SQW
–0.3
12
V
Continuous power dissipation
Ambient temperature, TA
(3)
Internally Limited
(4)
Junction temperature, TJ (4)
–40
125
°C
–40
150
°C
Maximum lead temperature (soldering)
See
Storage temperature, Tstg
(1)
(2)
(3)
(4)
(5)
–65
(5)
°C
150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to the potential at the GND pins.
Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 165°C (typical) and
disengages at TJ = 135°C (typical).
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =
150°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the
part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX ).
For detailed soldering specifications and information, refer to PowerPAD™ Thermally Enhanced Package Application Note .
7.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic discharge
Charged-device model (CDM), per AEC Q100-011
UNIT
±2000
All pins
±500
Corner pins
(1,8,9,16,17,24,25,32)
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Voltage on pins VSENSE_N, VSENSE_P
3
48
V
VDD input voltage
3
5.5
V
1.65
VDD
V
VDDIO/EN input voltage
Voltage on pins FILTER, ISENSE, ISENSE_GND, ISET, TSENSE, C1N
0
5.5
V
FAULT, PWM, SCLK/SCL, MOSI/SDA, NSS, IF, SYNC, MISO, VSYNC
0
VDDIO
V
Voltage on pins C1P, CPUMP, GD, SQW
0
11
V
Voltage on pins OUT1 to OUT4, FB, SD
0
48
V
(1)
6
All voltages are with respect to the potential at the GND pins.
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SNVSA21G – MAY 2014 – REVISED OCTOBER 2017
7.4 Thermal Information
LP8860
THERMAL METRIC (1)
HLQFP PowerPAD (VLP)
UNIT
32 PINS
RθJA
Junction-to-ambient thermal resistance (2)
36.0
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
23.3
°C/W
RθJB
Junction-to-board thermal resistance
15.5
°C/W
ψJT
Junction-to-top characterization parameter
3.2
°C/W
ψJB
Junction-to-board characterization parameter
15.5
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
1.6
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
7.5 Electrical Characteristics
TJ = −40°C to +125°C (unless otherwise noted). (1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
Shutdown supply current for VDD Device disabled, VDDIO/EN = 0 V
1
5
Backlight enabled (no load), boost
enabled, PLL and CP disabled,
DRV_LED_BIAS_CTRL[1:0] = 10 ,
boost ƒSW = 300 kHz
2.5
6
Backlight enabled (no load), boost
enabled, CP disabled, ƒPLL = 10
MHz, DRV_LED_BIAS_CTRL[1:0] =
11, boost ƒSW = 400 kHz
4.5
UNIT
POWER SUPPLIES
IQ
Active supply current for VDD,
VDD = 5 V
μA
mA
VVDD_POR_R
Power-on reset rising threshold
VVDD_POR_F
Power-on reset falling threshold
1.1
TTSD
Thermal shutdown threshold
150
TTSD_THR
Thermal shutdown hysteresis
15
2.2
165
V
180
°C
30
INTERNAL OSCILLATOR
ƒOSC
(1)
(2)
Frequency
10
Frequency accuracy
MHz
–7%
7%
All voltages are with respect to the potential at the GND pins.
Minimum (MIN) and Maximum (MAX) limits are specified by design, test, or statistical analysis.
7.6 Current Sinks Electrical Characteristics
Limits apply over the full ambient temperature range –40°C ≤ TA ≤ +125°C. Unless otherwise specified: VDD = 3.3 V, VIN = 12
V, EN/VDDIO = 3.3 V, L = 22 μH, CIN = 2 × 10 μF ceramic and 33 μF electrolytic, COUT = 2 × 10 μF ceramic and 33 μF
electrolytic, CVDD = 1 μF, CCPUMP = 10 μF, Q = IPD25N06S4L-30-ND, D = SS5P10-M3/86A.
TYP
MAX
ILEAKAGE
PARAMETER
Leakage current
Outputs OUT1 to OUT4, VOUT = 48 V
0.1
1
IMAX
Maximum source current
OUT1 to OUT4
150
IOUT
Output current accuracy
IOUT = 150 mA
IMATCH
Output current matching (1)
IOUT = 150 mA, 100% brightness
ƒLED_PWM
LED PWM output frequency
for display mode
PWM_FREQ[3:0] = 0000b
PWM_FREQ[3:0] = 1111b
(1)
TEST CONDITIONS
MIN
−3%
UNIT
µA
mA
3%
0.5%
2%
4883
39 063
Hz
Output Current Accuracy is the difference between the actual value of the output current and programmed value of this current.
Matching is the maximum difference from the average. For the constant current sinks on the part (OUT1 to OUT4), the following are
determined: the maximum output current (MAX), the minimum output current (MIN), and the average output current of all outputs (AVG).
Two matching numbers are calculated: (MAX-AVG)/AVG and (AVG-MIN)/AVG. The largest number of the two (worst case) is
considered the matching figure. The typical specification provided is the most likely norm of the matching figure for all parts. Note that
some manufacturers have different definitions in use.
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Current Sinks Electrical Characteristics (continued)
Limits apply over the full ambient temperature range –40°C ≤ TA ≤ +125°C. Unless otherwise specified: VDD = 3.3 V, VIN = 12
V, EN/VDDIO = 3.3 V, L = 22 μH, CIN = 2 × 10 μF ceramic and 33 μF electrolytic, COUT = 2 × 10 μF ceramic and 33 μF
electrolytic, CVDD = 1 μF, CCPUMP = 10 μF, Q = IPD25N06S4L-30-ND, D = SS5P10-M3/86A.
PARAMETER
TEST CONDITIONS
ƒPWM
PWM input frequency
tPWM MIN
Minimum on and off time for
PWM input
IDIM
Dimming ratio (input
resolution)
PWMRES
BRT_MODE[1:0] = 00, 01 and 10
MIN
16
bit
ƒLED_PWM = 5 kHz, ƒOSC = 5 MHz
10
ƒLED_PWM= 10 kHz, ƒOSC = 5 MHz
9
ƒLED_PWM = 20 kHz, ƒOSC = 5 MHz
8
13 000:1
13
ƒLED_PWM = 20 kHz, ƒOSC = 40 MHz
11
Saturation voltage
VSHORT_FAULT_THR LED short detection threshold
(2)
Hz
SPI or I2C control
7
bits
12
ƒLED_PWM = 40 kHz, ƒOSC = 40 MHz
VSAT
UNIT
500
ns
PWM output resolution, PWM
control for BRT_MODE[1:0] = ƒLED_PWM = 40 kHz, ƒOSC = 5 MHz
00, 01, and 10 (without
ƒLED_PWM = 5 kHz, ƒOSC = 40 MHz
dithering)
ƒLED_PWM = 10 kHz, ƒOSC = 40 MHz
(2)
MAX
400
External 100 Hz PWM
Individual output current
adjustment range
ΔIOUT
TYP
100
10
DRV_OUTx_CORR[3:0] = 1111
–7.4%
DRV_OUTx_CORR[3:0] = 0000
6.5%
IOUT = 150 mA
0.5
DRV_LED_FAULT_THR[1:0] = 00
3.6
DRV_LED_FAULT_THR[1:0] = 01
3.6
DRV_LED_FAULT_THR[1:0] = 10
6.9
DRV_LED_FAULT_THR[1:0] = 11
10.6
0.75
V
V
Saturation voltage is defined as the voltage when the LED current has dropped 10% from the value measured at 1 V.
7.7 Boost Converter Characteristics
Limits apply over the full ambient temperature range – 40°C ≤ TA ≤ +125°C. Unless otherwise specified: VDD = 3.3 V, VIN = 12
V, EN/VDDIO = 3.3 V, L = 22 μH, CIN = 2 × 10 μF ceramic and 33-μF electrolytic, COUT = 2 × 10 μF ceramic and 33-μF
electrolytic, CVDD = 1 μF, CCPUMP = 10 μF, Q = IPD25N06S4L-30-ND, D = SS5P10-M3/86A.
PARAMETER
Maximum continuous load
current
ILOAD
VOUT/VIN
TEST CONDITIONS
MIN
VIN = 6 V, VBOOST = 48 V (ƒSW = 303 kHz)
600
VIN = 3 V, VBOOST = 30 V (ƒSW = 1.1 MHz)
150
VIN = 3 V, VBOOST = 30 V (ƒSW = 2.2 MHz)
100
TYP
MAX
mA
Conversion ratio
ƒSW
Switching frequency (central
frequency if spread spectrum
is enabled)
tBOOST
Start-up time
UNIT
10
BOOST_FREQ
BOOST_FREQ
BOOST_FREQ
BOOST_FREQ
BOOST_FREQ
BOOST_FREQ
BOOST_FREQ
BOOST_FREQ
= 000
= 001
= 010
= 011
= 100
= 101
= 110
= 111
(1)
–7%
100
200
303
400
629
800
1100
2200
50
7%
kHz
ms
START-UP
(1)
8
Start-up time is measured from the moment the boost is activated until the VOUT crosses 90% of its initial voltage value.
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Boost Converter Characteristics (continued)
Limits apply over the full ambient temperature range – 40°C ≤ TA ≤ +125°C. Unless otherwise specified: VDD = 3.3 V, VIN = 12
V, EN/VDDIO = 3.3 V, L = 22 μH, CIN = 2 × 10 μF ceramic and 33-μF electrolytic, COUT = 2 × 10 μF ceramic and 33-μF
electrolytic, CVDD = 1 μF, CCPUMP = 10 μF, Q = IPD25N06S4L-30-ND, D = SS5P10-M3/86A.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RSENSE = 25 mΩ
IMAX
SW current limit
VGD
Gate driver output voltage
IGD_SOURCE_ Gate driver peak current,
sourcing
PEAK
IGD_SINK_PEA Gate driver peak current,
sinking
K
BOOST_IMAX_SEL=000
BOOST_IMAX_SEL=001
BOOST_IMAX_SEL=010
BOOST_IMAX_SEL=011
BOOST_IMAX_SEL=100
BOOST_IMAX_SEL=101
BOOST_IMAX_SEL=110
BOOST_IMAX_SEL=111
2
3
4
5
6
7
8
9
0
A
11
BOOST_DRIVER_SIZE[1:0] = 11
BOOST_GD_VOLT = 1
VDD= 5 V, VCPUMP = 10 V
FET SQ4850EY
V
1.7
A
1.5
7.8 Logic Interface Characteristics
VDDIO/EN = 1.65 V to VDD, VDD = 3.3 V unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC INPUT VDDIO/EN
VIL
Input low level
VIH
Input high level
1.2
0.4
II
Input current
−1
V
1
µA
0.2 ×
VDDIO/EN
V
1
μA
0.5
V
1
μA
LOGIC INPUT SYNC, VSYNC, PWM, SCLK/SCL, MOSI/SDA, NSS, IF
VIL
Input low level
VIH
Input high level
II
Input current
0.8 × VDDIO/EN
−1
LOGIC OUTPUT FAULT
VOL
Output low level
I = 3 mA
ILEAKAGE
Output leakage current
V = 5.5 V
0.3
LOGIC OUTPUT MISO
VOL
Output low level
IOUT = 3 mA
VOH
Output high level
IOUT = –2 mA
IL
Output leakage current
0.3
0.7 × VDDIO/EN
0.5
V
0.9 ×
VDDIO/EN
1
μA
LOGIC OUTPUTS SDA
VOL
Output low level
I = 3 mA
ILEAKAGE
Output leakage current
V = 5.5 V
0.3
0.5
V
1
μA
7.9 VIN Undervoltage Protection (VIN_UVLO)
PARAMETER
TEST CONDITIONS
MIN
UVLO[1:0] = 00
VUVLO
VIN UVLO threshold voltage
TYP
MAX
UNIT
Disabled
UVLO[1:0] = 01
2.64
3
3.36
UVLO[1:0] = 10
4.4
5
5.6
UVLO[1:0] = 11
7.04
8
8.96
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7.10 VDD Undervoltage Protection (VDD_UVLO)
PARAMETER
TEST CONDITIONS
VVDD_UVLO
VDD UVLO threshold voltage
VHYST
VDD UVLO hysteresis
MIN
TYP
VDD_UVLO_LEVEL = 0
2.5
VDD_UVLO_LEVEL = 1
3
MAX
UNIT
V
50
mV
7.11 VIN Overvoltage Protection (VIN_OVP)
PARAMETER
TEST CONDITIONS
MIN
OVP[1:0] = 00
VOVP
VIN OVP threshold voltage
TYP
MAX
UNIT
Disabled
OVP[1:0] = 01
6.16
7
7.84
OVP[1:0] = 10
9.68
11
12.32
OVP[1:0] = 11
19.8
22.5
25.2
MIN
TYP
MAX
V
7.12 VIN Overcurrent Protection (VIN_OCP)
PARAMETER
VOCP
(1)
TEST CONDITIONS
VIN current protection limit with
RISENSE = 20 mΩ, VIN = 12 V
See (1)
PL_SD_LEVEL[1:0] = 10
6
PL_SD_LEVEL[1:0] = 11
8
UNIT
A
Refer to Selecting Current Sensing Resistor for LP8860-Q1 Power Input application note.
7.13 Power-Line FET Control Electrical Characteristics
PARAMETER
TEST CONDITIONS
IL,VSENSE_P
VSENSE_P pin leakage current
VSENSE_P = 48 V
IL,VSENSE_N
VSENSE_N pin leakage current
VSENSE_N = 48 V
IL,SD
SD pin leakage current
VSD = 48 V
ISD
Pulldown current for power-line
p-FET, NMOS_PLFET_EN=0
PL_SD_SINK_LEVEL = 00
PL_SD_SINK_LEVEL = 01
PL_SD_SINK_LEVEL = 10
PL_SD_SINK_LEVEL = 11
PFET
MIN
TYP
MAX
0.1
3
55
110
220
440
UNIT
µA
µA
7.14 External Temp Sensor Control Electrical Characteristics
PARAMETER
RTEMP_HIGH
10
TSENSE high level
resistance value
TEST CONDITIONS
EXT_TEMP_LEVEL_HIGH[3:0]
EXT_TEMP_LEVEL_HIGH[3:0]
EXT_TEMP_LEVEL_HIGH[3:0]
EXT_TEMP_LEVEL_HIGH[3:0]
EXT_TEMP_LEVEL_HIGH[3:0]
EXT_TEMP_LEVEL_HIGH[3:0]
EXT_TEMP_LEVEL_HIGH[3:0]
EXT_TEMP_LEVEL_HIGH[3:0]
EXT_TEMP_LEVEL_HIGH[3:0]
EXT_TEMP_LEVEL_HIGH[3:0]
EXT_TEMP_LEVEL_HIGH[3:0]
EXT_TEMP_LEVEL_HIGH[3:0]
EXT_TEMP_LEVEL_HIGH[3:0]
EXT_TEMP_LEVEL_HIGH[3:0]
EXT_TEMP_LEVEL_HIGH[3:0]
EXT_TEMP_LEVEL_HIGH[3:0]
= 0000
= 0001
= 0010
= 0011
= 0100
= 0101
= 0110
= 0111
= 1000
= 1001
= 1010
= 1011
= 1100
= 1101
= 1110
= 1111
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MIN
TYP
79.67
43.35
29.77
22.67
18.30
15.34
13.21
11.60
10.34
9.32
8.49
7.79
7.20
6.69
6.25
5.87
MAX
UNIT
kΩ
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External Temp Sensor Control Electrical Characteristics (continued)
PARAMETER
RTEMP_LOW
TSENSE low-level
resistance value
RTS_FLOAT
TSENSE maximum
resistance (missing
resistor fault value)
TEST CONDITIONS
EXT_TEMP_LEVEL_LOW[3:0] = 0000
EXT_TEMP_LEVEL_LOW[3:0] = 0001
EXT_TEMP_LEVEL_LOW[3:0] = 0010
EXT_TEMP_LEVEL_LOW[3:0] = 0011
EXT_TEMP_LEVEL_LOW[3:0] = 0100
EXT_TEMP_LEVEL_LOW[3:0] = 0101
EXT_TEMP_LEVEL_LOW[3:0] = 0110
EXT_TEMP_LEVEL_LOW[3:0] = 0111
EXT_TEMP_LEVEL_LOW[3:0] = 1000
EXT_TEMP_LEVEL_LOW[3:0] = 1001
EXT_TEMP_LEVEL_LOW[3:0] = 1010
EXT_TEMP_LEVEL_LOW[3:0] = 1011
EXT_TEMP_LEVEL_LOW[3:0] = 1100
EXT_TEMP_LEVEL_LOW[3:0] = 1101
EXT_TEMP_LEVEL_LOW[3:0] = 1110
EXT_TEMP_LEVEL_LOW[3:0] = 1111
MIN
TYP
MAX
UNIT
79.67
43.35
29.77
22.67
18.30
15.34
13.21
11.60
10.34
9.32
8.49
7.79
7.20
6.69
6.25
5.87
kΩ
2
MΩ
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7.15 I2C Serial Bus Timing Parameters (SDA, SCLK)
See Figure 1.
MIN
NOM
MAX
UNIT
400
kHz
ƒSCLK
Clock frequency
1
Hold time (repeated) START Condition
0.6
2
Clock low time
1.3
3
Clock high time
600
ns
4
Set-up time for a repeated START condition
600
ns
5
Data hold time
50
ns
6
Data setup time
100
ns
7
Rise Time of SDA and SCL
20+0.1xCb
300
ns
8
Fall Time of SDA and SCL
15+0.1xCb
300
ns
9
Set-up time for STOP condition
600
ns
10
Bus free time between a STOP and a START Condition
1.3
µs
Cb
Capacitive load parameter for each bus line
load of 1 pF corresponds to 1 ns.
10
µs
25000
200
µs
ns
7.16 SPI Timing Requirements
See Figure 2.
MIN
NOM
MAX
UNIT
1
Cycle time
70
ns
2
Enable lead time
35
ns
3
Enable lag time
35
ns
4
Clock low time
35
ns
5
Clock high time
35
ns
6
Data setup time
20
ns
7
Data hold time
20
8
Disable time
10
ns
9
Data valid
29
ns
10
NSS inactive time
Cb
Bus capacitance
40
pF
ns
700
ns
5
Figure 1. I2C Timing
NSS
t2t
t1t
4
t10t
5
3
SCLK
7
6
MOSI
MISO
MSB IN
BIT 14
BIT 9
BIT 8
BIT 7
9
High
Impedance
Address
BIT 1
8
9
MSB OUT
R/W
LSB IN
BIT 1
LSB OUT
Data
Figure 2. SPI Timing Diagram
12
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7.17 Typical Characteristics
95
90
90
85
85
80
Efficiency (%)
Efficiency (%)
Unless otherwise specified: L= 22 µH (IHLP-5050FDER220M5A), CIN = 2 × 10-µF ceramic and 33 µF electrolytic, COUT = 2 ×
10-µF ceramic and 33-µF electrolytic, Q = IPD25N06S4L-30-ND, D = SS5P10-M3/86A, VDD = 5 V, charge pump disabled, T =
25°C
VIN = 5 V
80
VIN = 6 V
75
VIN = 8 V
VIN = 12 V
70
VIN = 5 V
75
VIN = 6 V
70
VIN = 8 V
VIN = 12 V
65
VIN = 15 V
VIN = 15 V
60
65
0
10
20
30
40
50
60
70
80
90
Brightness (%)
ƒSW = 303 kHz
4 strings
0
100
10
20
8 LEDs/string
40
50
60
70
80
90
100
Brightness (%)
150 mA/string
ƒSW = 2.2 MHz
4 strings
Figure 3. System Efficiency
C004
8 LEDs/string
100 mA/string
Figure 4. System Efficiency
160
4000
Vout = 26 V
3500
140
Vout = 33 V
Vout = 39 V
3000
Current (mA)
Maximum Boost Output Current (mA)
30
C001
Vout = 45 V
2500
2000
1500
25 mA
120
30 mA
100
50 mA
80
60 mA
60
80 mA
100 mA
40
1000
20
500
0
120 mA
150 mA
5
6
7
8
9
10
11
12
13
14
Input Voltage (V)
ƒSW = 303 kHz
0.0
15
0.2
0.3
0.4
0.5
0.6
0.7
Voltage (V)
0.8
C006
Adaptive voltage control off
Figure 5. Boost Maximum Output Current
Figure 6. LED Current vs Headroom Voltage
200
200
VIN = 5 V
180
VIN = 5 V
180
VIN = 6 V
VIN = 6 V
160
140
VIN = 8 V
120
VIN = 12 V
100
VIN = 15 V
Ripple, p-p (mV)
160
Ripple, p-p (mV)
0.1
C007
80
60
140
VIN = 8 V
120
VIN = 12 V
100
VIN = 15 V
80
60
40
40
20
20
0
0
0
10
20
30
40
50
60
70
Brightness (%)
ƒSW = 303 kHz
4 strings
8 LEDs/string
Phase shift 90º
80
90
100
0
10
20
150 mA/string
ƒLED_PWM = 4.9 kHz
30
40
50
60
70
80
90
Brightness (%)
C003
fSW = 2.2 MHz
4 strings
Figure 7. Boost Ripple
8 LEDs/string
Phase shift 90º
100
C005
100 mA/string
fLED_PWM= 4.9 kHz
Figure 8. Boost Ripple
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8 Detailed Description
8.1 Overview
The LP8860-Q1 is a high-voltage LED driver for automotive infotainment, LED clusters, and medium-sized LCD
backlight applications with a boost controller. The device can be used as a stand-alone device, with a simple
four-wire control:
• VDDIO/EN for enable
• PWM input for brightness control
• FAULT output to indicate fault condition
• NSS input for fault reset
Alternatively, the LP8860-Q1 can be controlled through I2C or SPI serial interface which allows wide range of
user-specific configurable features.
8.1.1 Boost Controller
The boost controller generates a 16-V to 48-V supply for LED strings. To optimize LED drive efficiency the boost
controller includes adaptive output voltage control which gets feedback from monitoring the internal LED current
sinks voltage circuit. This feature minimizes power consumption by adjusting the boost voltage to lowest
sufficient level in all conditions.
Boost switching frequency can be set in a wide range from 100 kHz to 2.2 MHz. This enables system
optimization for both high power applications, where efficiency is critical, and for lower power applications where
small solution size can be achieved with high boost switching frequency.
The LP8860-Q1 has several features for system EMI optimization:
• Boost switching frequency can be selected either below or above AM band.
• Spread spectrum can be enabled to reduce energy around the switching frequency and its harmonics.
• Boost switching can be synchronized to an external clock with a dedicated SYNC input.
• Gate drive strength for the external FET is controllable with EEPROM.
8.1.2 LED Output Configurations
The LP8860-Q1 has four high-precision current sinks with up to 150 mA per output capability. LED outputs can
be connected parallel to reach higher current levels.
LED outputs are highly configurable; for example, there are features such as brightness slope control, external
clock synchronization, phase shifting, adaptive headroom control, etc.
In general there are 2 main user modes:
• Display Mode (with full feature set) and/or
• Cluster Mode (with limited feature set)
These modes and features are detailed in later sections.
8.1.3 Display Mode
In Display Mode LED outputs are configured to power an LCD backlight. Maximum current per string is set by
RISET; alternatively, through a user-programmable EEPROM value.
Brightness is controlled with PWM input or I2C/SPI register writes. An optional sloper feature enables automatic
smooth transition between brightness levels. Sloper time can be programmed to EEPROM registers, and an
advanced slope feature allows smoother response to eye compared to traditional linear slope.
Outputs are controlled with a Phase Shift PWM (PSPWM) Scheme. Due to the phase shift between the outputs
they are not activated simultaneously which brings several benefits:
• Peak load current from the boost output is decreased, which reduces the voltage ripple seen at the boost
output and allows smaller output capacitors.
• Smaller ripple reduces the possible audible noise from the ceramic boost output capacitors.
• PSPWM scheme multiplies the effective load frequency seen at the boost output by number of active
channels. This further reduces the audible noise by transferring the output ripple frequency above human
14
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Overview (continued)
•
hearing.
Optical ripple through LCD panel is reduced, helping to reduce the “waterfall” effect which is caused by
asynchronous backlight ripple and LCD refresh.
PWM output frequency is set with EEPROM registers from 4.9 kHz to 39 kHz. Selecting output frequency
depends on the number of strings used, system requirements for the frequency, and desired dimming ratio.
Dimming resolution is a function of PWM output frequency — the higher the frequency, the lower the resolution.
User can choose to increase resolution by:
• enabling dithering function (optional through EEPROM), or
• increasing internal clock frequency.
Increasing internal clock frequency increases device current consumption.
In high-quality display systems an "anti-waterfall" feature may be required. The LP8860-Q1 supports this by
offering output synchronization to the LCD refresh signal through VSYNC input. VSYNC input is synchronized to
outputs through internal PLL; EEPROM and filtering are described in later sections.
8.1.4 Cluster Mode
In Cluster mode LED strings have independent control but fewer features enabled than in Display Mode.
Brightness (PWM and current) are independently controlled for all 4 outputs. When there is an unequal number
of LEDs per channel, the LP8860-Q1 adaptive voltage control is not used in Cluster mode; therefore, boost
output voltage is fixed (or externally controlled or powered).
In Cluster mode PWM frequency can be set through EEPROM, and Phase Shift PWM mode is enabled.
Cluster mode does not support the PWM input pin, hybrid dimming, slope control or dither mode.
8.1.5 Hybrid Dimming
Hybrid dimming combines both PWM and current-dimming benefits offering the best optical efficiency to drive
LEDs. At higher brightness levels only the LED constant current is controlled; at lower brightness levels LED
brightness is controlled by adding PWM on top of low constant current value.
Because LED optical efficacy declines with high forward current, reducing the current yields better system optical
efficiency compared with conventional PWM dimming. An additional benefit of current dimming is reduced EMI
compared to PWM switching. PWM dimming is used with lower brightness values to achieve a higher dimming
ratio. The optimum switch point between PWM and current dimming is programmable and depends on the LED
type.
8.1.6 Charge Pump and Square Waveform (SQW) Output
The gate driver for the external boost FET can be powered directly from the VDD input or from the charge pump
integrated into the LP8860-Q1. When a 5-V rail is available in the system for VDD supply, it is typically a high
enough voltage to drive the external FET, and the internal charge pump can be disabled. In this case, the VDD
and CPUMP pins must be shorted together, and the fly cap can be removed. When the system VDD is not high
enough to drive the gate of the boost FET (typical case is 3.3 V), the charge pump can be used to multiply the
gate drive voltage to 2× VDD.
The SQW output provides a 100-kHz square wave signal (1 mA maximum) with amplitude equal to the chargepump output voltage. When the charge pump is disabled, the amplitude of the SQW signal is equal to VDD. See
Charge Pump and High Output Voltage Application sections for usage examples.
8.1.7 Power-Line FET
Some automotive systems require a safety switch to disconnect the driver device from the battery. The LP8860Q1 offers a power-line FET control circuit, which limits inrush current from the power line during start-up and
reduces standby power consumption by disconnecting device from the power-line during an off state. This FET
disconnects the boost and LED strings from the input during fault conditions. For example, when the input
voltage is above the overvoltage protection (OVP) level, the power-line FET disconnects the LED strings from the
power-line to protect LED outputs against overheating.
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Overview (continued)
Depending on which fault has shut down the power-line FET, the device can enter automatic fault recovery state
where the power-line FET is turned on in 100-ms time periods to see if the fault condition has been removed. If
the fault was only short-term, and normal operation condition returns, the device turns back on automatically.
8.1.8 Protection Features
Extensive fault-detection and protection features of the LP8860-Q1 include:
• Open-string and shorted LED detections
– LED fault detection prevents system overheating in case of open in some of the LED strings
• Boost overcurrent
• Boost overvoltage
• VIN input overvoltage protection
– Threshold sensing from VSENSE_P pin
• VIN input undervoltage protection
– Threshold sensing from VSENSE_P pin
• VIN input overcurrent protection
– Threshold sensing across RISENSE resistor
• VDD input undervoltage lockout
• Thermal shutdown in case of die overtemperature (165°C nominal)
Fault protection thresholds are EEPROM programmable and some protection features can be disabled, or
masked, if necessary.
A fault condition is indicated through the FAULT pin. If an I2C/SPI interface is used, the fault reason can be read
from the register, and flags can be cleared with register write.
8.1.9 Advanced Thermal Protection Features
The LP8860-Q1 has a unique features for protecting against overheating:
1. Die temperature based Thermal de-rating function. Average LED current is automatically lowered when die
temperature increases above a predefined (90ºC, 100ºC, or 110ºC) level. Decreasing LED current reduces
thermal loading on the device and prevents overheating.
2. An external NTC sensor-based protection, where a sensor can be placed close to LEDs to protect them from
overheating. The sensor is connected to the TSENSE pin of the device. Two methods are available:
– Current de-rating, where the LED current is lowered proportionally to the temperature measured with the
external NTC sensor. This method is available only if LED max current is set with RISET resistor.
– Brightness limitation above a predefined temperature
16
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8.2 Functional Block Diagram
RISENSE
VIN
Q2
D
CIN
VSENSE_P
VSENSE_N
COUT
SD
POWER-LINE FET CONTROL
C1N
VDD
VDD
C2X
C1P
CHARGE PUMP
CPUMP
CCPUMP
CVDD
SQW
FB
Q1
GD
SYNC
BOOST
CONTROLLER
ISENSE
+
RSENSE
ISENSE_GND
PGND
FILTER
ISET
RISET
NTC
ANALOG BLOCKS
(CLOCK
GENERATOR, PLL,
VREF, ADC, DACs
etc.)
4 x LED
CURRENT
SINK
OUT1
OUT2
OUT3
TSENSE
tº
OUT4
PWM
VSYNC
FAULT
VDDIO/EN
LGND
DIGITAL BLOCKS
(FSM, PWM
DETECTOR,
BRIGTNESS
CONTROL,
SLOPER, HYBRID
DIMMING, SAFETY
LOGIC etc.)
SCLK/SCL
MOSI/SDA
MISO
SPI/I2C
INTERFACE
EEPROM
NSS
IF
SGND
EXPOSED PAD
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8.3 Feature Description
8.3.1 Clock Generation
The LP8860-Q1 has an internal 10-MHz oscillator which is used for clocking the PWM input duty cycle
measurement. The 10-MHz clock is divided by two, and the 5-MHz clock is used for clocking the state machine
and internal timings.
The internal 5-MHz clock can be used for generating the LED PWM output frequency directly or it can be
multiplied with an internal PLL to achieve higher resolution. The higher clock frequency for the PWM generation
block allows the higher resolution; however, the tradeoff is higher power consumption of the part. Clock
multiplication is set with EEPROM bits.
8.3.1.1 LED PWM Clock Generation With VSYNC
Unsynchronized LCD line scanning and LED backlight ripple may cause a “waterfall” effect. Synchronizating LED
output PWM frequency with video processor or timing controller VSYNC/HSYNC signal can reduce this effect.
The PLL can be used for generating required PWM generation clock from the VSYNC signal. This ensures that
the LED output PWM remains synchronized to the VSYNC signal, and there is no clock variation between the
LCD display video update and the LED backlight output frequency. If PWM_COUNTER_RESET = 1, the VSYNC
signal rising edge restartsthe PWM generation, ensuring there is no clock drifting. The slow divider is intended for
LED PWM frequency synchronization with an external VSYNC. An external filter connected to the FILTER pin
must be used only if a slow divider is enabled — otherwise the LP8860-Q1 uses internal compensation.
The ƒOUT of the PLL must be chosen in the 5-MHz to 40-MHz range. If VSYNC is enabled, the signal must be
active before VDDIO/EN is set high and present whenever VDDIO/EN is high.
VSYNC 50...150 Hz
or 50...150 kHz
SYNC_PRE_DIVIDER[3:0]
PWM_FREQ[3:0]
PWM_COUNTER_RESET
PWM_RESOLUTION[1:0]
LED_STRING_CONF[2:0]
EN_SYNC
Predivider
VBOOST
PLL
0
1
10 MHz Internal
Oscillator
Divider
f/2
5 MHz
0
Phase
Detector
Filter
VCO
PWM Generator
1
fOUT
EN_PLL
SEL_DIVIDER
PWM Input
State Machine,
PWM Input, Internal
Timings, Slope etc.
1
Divider
1/Nfast
0
Divider
R_SEL[1:0]
PWM_RESOLUTION[1:0]
0
Divider
1/Nslow
1
PWM_SYNC
SLOW_PLL_DIV[12:0]
Copyright © 2016, Texas Instruments Incorporated
Figure 9. PLL Clock Generation
8.3.1.2 LED PWM Frequency and Resolution
LED output PWM frequency is selected with EEPROM register when using a 5-MHz internal
oscillator for generating PWM output. bits define phase shift between LED outputs
as described later. EEPROM bits select the PLL output frequency and hence the
LED PWM resolution. PWM frequencies with = 0 are listed in Table 1.
18
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Feature Description (continued)
NOTE
If the VSYNC signal is used for generating PWM output frequency, it affects all clock
frequencies, as well as the LED PWM output frequency. The EEPROM Bit Explanations
section explains how all the dividers affect the output clocks.
VBOOST
PWM_FREQ[3:0]
LED_STRING_CONF[2:0]
5 MHz
PWM Generator
EN_PLL=0
PWM_RESOLUTION[1:0]=00
PWM_COUNTER_RESET=0
Copyright © 2016, Texas Instruments Incorporated
Figure 10. PWM Clocking With Internal Oscillator
VBOOST
PWM_FREQ[3:0]
PWM_RESOLUTION[1:0]
LED_STRING_CONF[2:0]
PLL
5 MHz
Phase
Detector
VCO
Filter
Divider
1/Nfast
PWM Generator
Fout=10, 20, 40 MHz
EN_PLL=1
EN_SYNC=0
SEL_DIVIDER =1
PWM_COUNTER_RESET=0
PWM_RESOLUTION[1:0]
Copyright © 2016, Texas Instruments Incorporated
Figure 11. PWM Clocking With PLL, Internal Oscillator as Reference
Table 1. Output PWM Frequency and Resolution With Internal Oscillator
00
OSC = 5 MHz
01
OSC = 10 MHz
10
OSC = 20 MHz
11
OSC = 40 MHz
PWM_FREQ[3:0]
PWM_RESOLUTION[1:0]
PWM FREQUENCY (Hz)
RESOLUTION (bit)
1111
39063
7
8
9
10
1110
34180
7
8
9
10
1101
30518
7
8
9
10
1100
29297
7
8
9
10
1011
28076
7
8
9
10
1010
26855
7
8
9
10
1001
25635
7
8
9
10
1000
24412
7
8
9
10
0111
23192
7
8
9
10
0110
21973
7
8
9
10
0101
20752
7
8
9
10
0100
19531
8
9
10
11
0011
17090
8
9
10
11
0010
13428
8
9
10
11
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Feature Description (continued)
Table 1. Output PWM Frequency and Resolution With Internal Oscillator (continued)
00
OSC = 5 MHz
01
OSC = 10 MHz
10
OSC = 20 MHz
11
OSC = 40 MHz
PWM_FREQ[3:0]
PWM_RESOLUTION[1:0]
PWM FREQUENCY (Hz)
RESOLUTION (bit)
0001
9766
9
10
11
12
0000
4883
10
11
12
13
VSYNC 50...150 Hz
or 50...150 kHz
PWM_FREQ[3:0]
PWM_COUNTER_RESET
PWM_RESOLUTION[1:0]
LED_STRING_CONF[2:0]
SYNC_PRE_DIVIDER[3:0]
PLL
Phase
Detector
Predivider
VCO
Filter
VBOOST
PWM generator
EN_PLL=1
SEL_DIVIDER=0
EN_SYNC=1
PWM_SYNC=1
Divider
1/Nslow
SLOW_PLL_DIV[12:0]
Copyright © 2016, Texas Instruments Incorporated
Figure 12. PWM Synchronization With External VSYNC Input
PWM clock frequencies with different , , and combinations are listed in
Table 2.
Table 2. PLL Clock and LED PWM Frequency
PWM_SYNC
SEL_DIVIDER
EN_PLL
EN_SYNC
PLL CLOCK
PWM FREQUENCY
0
X
0
0
1
1
0
5 MHz
See Table 1
0
5, 10, 20, 40 MHz
0
0
See Table 1
1
1
SYNC × R_SEL[1:0] ×
SLOW_PLL_DIV[12:0]/
SYNC_PRE_DIV[3:0]
PLL clock / GEN_DIV
1
0
1
1
SYNC × GEN_DIV ×
SLOW_PLL_DIV[12:0]/
SYNC_PRE_DIV[3:0]
PLL clock / GEN_DIV
GEN_DIV coefficients and resolution (bit) are listed on Table 3.
Table 3. GEN_DIV Coefficients and Resolution
PWM_RESOLUTION[1:0]
00
PWM_
STEP
FREQ[3:0]
20
01
10
11
GEN_DIV
RES
(bits)
STEP
GEN_DIV
RES
(bits)
STEP
GEN_DIV
RES
(bits)
STEP
GEN_DIV
RES
(bits)
0000
64
1024.00
10
32
2048.00
11
16
4096.00
12
8
8192.00
13
0001
128
512.00
9
64
1024.00
10
32
2048.00
11
16
4096.00
12
0010
176
372.36
8
88
744.73
9
44
1489.45
10
22
2978.91
11
0011
224
292.57
8
112
585.14
9
56
1170.29
10
28
2340.57
11
0100
256
256.00
8
128
512.00
9
64
1024.00
10
32
2048.00
11
0101
272
240.94
7
136
481.88
8
68
963.76
9
34
1927.53
10
0110
288
227.56
7
144
455.11
8
72
910.22
9
36
1820.44
10
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Table 3. GEN_DIV Coefficients and Resolution (continued)
PWM_RESOLUTION[1:0]
00
PWM_
STEP
FREQ[3:0]
01
10
11
GEN_DIV
RES
(bits)
STEP
GEN_DIV
RES
(bits)
STEP
GEN_DIV
RES
(bits)
STEP
GEN_DIV
RES
(bits)
0111
304
215.58
7
152
431.16
8
76
862.32
9
38
1724.63
10
1000
320
204.80
7
160
409.60
8
80
819.20
9
40
1638.40
10
1001
336
195.05
7
168
390.10
8
84
780.19
9
42
1560.38
10
1010
352
186.18
7
176
372.36
8
88
744.73
9
44
1489.45
10
1011
368
178.09
7
184
356.17
8
92
712.35
9
46
1424.70
10
1100
384
170.67
7
192
341.33
8
96
682.67
9
48
1365.33
10
1101
400
163.84
7
200
327.68
8
100
655.36
9
50
1310.72
10
1110
448
146.29
7
224
292.57
8
112
585.14
9
56
1170.29
10
1111
512
128.00
7
256
256.00
8
128
512.00
9
64
1024.00
10
Dithering allows increased resolution and smaller average steps size. Dithering can be programmed with
EEPROM bits 0 to 4 bits. Figure 13 shows 1-bit dithering. For 3-bit dithering, every 8th pulse is
made 1 LSB longer to increase the average value by 1/8th. Dither is available in steady state condition when
is high, otherwise during slope only.
PWM value 510 (10-bit)
+1LSB
PWM value 510 ½ (10-bit)
PWM value 511 (10-bit)
Figure 13. Example of the Dithering, 1-Bit Dither, 10-Bit Resolution
8.3.2 Brightness Control (Display Mode)
The LP8860-Q1 LED outputs can be configured to display or cluster mode. The following sections describe
display mode options. Cluster mode is a special mode with individually controlled LED outputs. See Cluster
Mode section for details.
The LP8860-Q1 controls the brightness of the display with conventional PWM or with Hybrid PWM and Current
dimming. Brightness control is received either from PWM input pin or from I2C/SPI register bits. The brightness
source is selected with bits as follows:
Table 4. Brightness Control Selection
BRT_MODE[1:0]
BRIGHTNESS CONTROL
00
PWM input duty cycle
01
PWM input duty cycle x Brightness register
10
Brightness register
11
PWM direct control (PWM in = PWM out)
8.3.2.1 PWM Input Duty Cycle Based Control
In this mode the LED brightness is controlled by the input PWM duty cycle. The PWM detector block measures
the duty cycle in the PWM pin and uses this 16-bit value to control the duty cycle of the LED output PWM. Input
PWM period is measured from rising edge to the next rising edge.
The ratio of input PWM frequency and 10-MHz sampling clock defines resolution reachable with external PWM.
PWM input block timeout is 24 ms after the last rising edge; it must be taken into account for 0% and 100%
brightness setting. For setting 100% brightness, a high-level PWM input signal must last at least 24 ms. The
minimum on and off time for the PWM input signal is 400 ns.
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8.3.2.2 Brightness Register Control
With brightness register control the LED output PWM is controlled with 16-bit resolution
register bits.
8.3.2.3 PWM Input Duty × Brightness Register
In this mode the PWM input duty cycle value is multiplied with the 16-bit register value
to achieve the LED output PWM.
8.3.2.4 PWM-Input Direct Control
With PWM-input direct control the output PWM directly follows the input PWM frequency and duty cycle. Due to
the internal logic structure the input is clocked with the 5-MHz clock or the PLL clock (if it is enabled). The output
PWM delay can be 5 to 6 clock cycles from input PWM.
In the direct control mode several of the advanced features are not available: Phase Shift PWM (PSPWM),
brightness slope, dither, Hybrid PWM and Current dimming, and LED current limitation with external NTC.
Dimming ratio can be calculated as the ratio between the brightness PWM input signal and sampling clock (5MHz or PLL clock) frequencies. In direct mode PWM duty cycle must be less than 100%. Boost adaptive mode
turns off at 100% duty cycle.
8.3.2.5
Brightness Slope
Sloper makes the smooth transition from one brightness value to another. Slope time can be programmed with
EEPROM bits from 0 to 511 ms. Slope time is used for sloping up and down. Advanced
slope makes brightness changes smooth for eye.
Table 5. Slope Time
22
PWM_SLOPE[2:0]
SLOPE TIME
000
disabled
001
1 ms
010
2 ms
011
52 ms
100
105 ms
101
210 ms
110
315 ms
111
511 ms
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Brightness (PWM)
Sloper Input
Brightness (PWM)
PWM Output
Time
Steady state with or
without dithering
Normal slope
If dither is enabled it will
be used during transition
to enable smooth effect
Advanced slope
Time
Slope Time
Figure 14. Sloper Operation
8.3.2.6 LED Dimming Methods
In additional to conventional PWM dimming control the LP8860-Q1 supports Hybrid PWM and Current dimming.
Hybrid dimming combines the PWM and current dimming methods. PWM dimming operates with a lower range
of light, and linear current dimming is used with higher brightness values. If the bit is set
to 1, the system enables hybrid dimming. Principles of PWM dimming and Hybrid PWM and Current dimming are
illustrated by Figure 15. Only 25% switch points and slope gain = 1 are shown for simplicity.
Max current can be set with EEPROM bits or
with RISET resistor
PWM DIMMING
CURRENT DIMMING
LED CURRENT
LED CURRENT
100%
75%
50%
I_SLOPE[2:0]=000
Slope gain = 1
25%
GAIN_CTRL[2:0]=011
Switch point = 25%
25%
50%
100%
BRIGHTNESS
25%
50%
100%
BRIGHTNESS
Figure 15. Principles of PWM Dimming and Hybrid PWM and Current Dimming
LED forward voltage increases and efficiency declines when forward current is increased. Use of constant
current with PWM dimming at lower brightness and current dimming at greater brightness (instead of PWM
dimming at full brightness range), yields better optical efficiency and resolution especially at lower brightness
values. The optimum switch point between PWM and current dimming modes and current slope depend on the
LED type.
PWM control ranges from 12.5% to 50% and the current slope can be selected using and
EEPROM bits, respectively (see Table 6 and Table 7).
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LED CURRENT
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25%
100%
OPTICAL EFFICIENCY
BRIGHTNESS
HYBRID DIMMING
~20%
PWM DIMMING
BRIGHTNESS
Figure 16. Optical Efficiency Improvement With PWM and Current Dimming
24
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Table 6. Gain Control Selections
GAIN_CTRL[2:0]
SWITCH POINT FROM PWM
TO CURRENT DIMMING
000
50.0%
001
40.6%
010
31.3%
011
25.0%
100
21.9%
101
18.8%
110
15.6%
111
12.5%
Table 7. Current Slope Control Selections
I_SLOPE[2:0]
SLOPE GAIN
000
1.000
001
1.023
010
1.047
011
1.070
100
1.094
101
1.117
110
1.141
111
1.164
The current setting for DISP_CL1_CURRENT[11:0] in Hybrid PWM and Current dimming mode can be defined
by the following formula (assuming individual LED sink current correction DRV_OUTx_CORR[3:0] is 0%):
IDISP _ CL1_ CURRENT[11:0]
IMAX DRV _LED _ CURRENT _ SCALE[2 : 0] u I_ SLOPE[2 : 0] u
(100% GAIN_ CTRL[2 : 0])
100%
(1)
Example of calculation for Hybrid PWM and Current dimming mode, 100-mA maximum output current:
Target maximum current 100 mA
Maximum scale 100 mA
(DRV_LED_CURRENT_SCALE[2:0]=101)
IDISP_CL1_CURRENT = 100 – 100 × 1 × ((100 – 25) / 100) = 25 mA
Slope = 1.000 (I_SLOPE[2:0]=000)
Switch point = 25% (GAIN_CTRL[2:0]=011)
Example of calculation for Hybrid PWM and Current dimming mode, 23-mA maximum output current:
Target maximum current 23 mA
Maximum scale 25 mA
(DRV_LED_CURRENT_SCALE[2:0]=000)
IDISP_CL1_CURRENT = 23 – 25 × 1.094 × ((100 – 25) / 100) = 2.49 mA
Slope = 1.094 (I_SLOPE[2:0]=100)
Switch point = 25% (GAIN_CTRL[2:0]=011)
NOTE
1. Formula is only approximation for the actual value.
2. DISP_CL1_CURRENT[11:0] value must be chosen to avoid current saturation before 100%
brightness is achieved.
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8.3.2.7 PWM Calculation Data Flow for Display Mode
Figure 17 shows the PWM calculation data flow for display mode. In PWM direct control mode most of the blocks
are bypassed, and this flow chart does not apply.
HYSTERESIS
[1:0]
10
MHz
Clock
External
Temp Sensor
BRT_MODE[1:0]
PWM_SLOPE[3:0]
I_SLOPE[2:0]
DITHER[2:0]
Current 12-bit
EN_BRT_ADV_SLOPE
PWM Input
Signal
00
PWM
Detector
01
16-bit
16-bit
10
11
Brightness
Register
16-bit
Temperature
Regulator
16-bit
16-bit
Sloper
11-bit
Advanced
Slope
16-bit
PWM &
Current
Control
16-bit
PWM
PWM
Comparator
...
16-bit
PWM
freq
EN_PWM_I
Internal
Temp Sensor
Dither
16-bit
PWM
Counter
GAIN_CTRL[2:0]
DISPLAY
MODE LED
CURRENT
SINKS
PWM_RESOLUTION
[1:0]
PWM_FREQ[3:0]
PLL Clock 5...40 MHz
Copyright © 2016, Texas Instruments Incorporated
Figure 17. PWM Data Flow Calculation
Table 8. PWM Calculation Blocks
BLOCK NAME
DESCRIPTION
PWM detector
PWM detector block measures the duty cycle of the input PWM signal. Resolution depends on the
input signal frequency. Hysteresis selection sets the minimum allowable change to the input.
Smaller changes are ignored.
Brightness register
16-bit register for brightness setting
Brightness mode control
Brightness control block gets 16-bit value from the PWM detector, and also 16-bit value from the
brightness register . selects whether to use PWM input
duty cycle value, the brightness register value or multiplication.
Temperature regulator
Temperature regulator reduces LED PWM duty cycle depending on internal and external
temperature sensor.
See LED Current Dimming With Internal Temperature Sensor and LED Current Limitation With
External NTC Sensor for details
External temperature sensor
External NTC temperature sensor
Internal temperature sensor
Internal die temperature sensor
Sloper
Sloper makes the smooth transition from one brightness value to another. Slope time can be
adjusted from 0 ms to 511 ms with EEPROM bits.
Advanced sloper
Advanced slope makes brightness changes smoother for eye; see Brightness Slope for details
PWM and Current Control
Hybrid PWM and Current dimming improves the optical efficiency of the LEDs by using PWM
control with lower brightness values and current control with greater values.
EEPROM bit enables Hybrid PWM and Current control. PWM dimming range can be set 12.5 to
50% of the brightness range with EEPROM bits. Current slope can be adjusted
by using the EEPROM bits. See LED Dimming Methods for details
Dither
With dithering the output resolution can be further increased. This way the brightness change steps
are not visible to eye. The amount of dithering is 0 to 4 bits, and is selected with
EEPROM bits.
PWM comparator
PWM comparator compares the PWM counter output to the value received from the dither block.
Output of the PWM comparator directly controls the LED current sinks. If Phase Shift PWM
(PSPWM) mode is used, the PWM counter values for each LED output are modified by summing an
offset value to create different phases.
PWM counter
Overflowing 16-bit PWM counter creates new PWM cycle. Step for incrementation is defined by
and bits, see Table 3.
26
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8.3.3 LED Output Modes and Phase Shift PWM (PSPWM) Scheme
The PSPWM scheme allows delaying the time when each LED output is active. When the LED outputs are not
activated simultaneously, the peak load current from the boost output is greatly decreased. This reduces the
ripple seen on the boost output and allows smaller output capacitors. Reduced ripple also reduces the output
ceramic capacitor audible ringing. The PSPWM scheme also increases the load frequency seen on boost output
up to 4 times, therefore transferring possible audible noise to a frequency above human hearing range. In
addition, “optical ripple” through the LCD panel is reduced helping in waterfall noise reduction.
Figure 18 shows the available LED output modes. The number of LED outputs used can be one to four; outputs
can be tied together to increase current for one string or all four strings can be independently controlled in the
cluster mode.
In = 000 the phase difference between channels is 90 degrees. This mode is
intended for application in Figure 53. When = 001 the phase difference between 3
channels in display mode is 120 degrees. This mode is intended for application shown in Figure 63. When
= 010 the phase difference between 2 channels in display mode is 180 degrees,
channels 3 and 4 in cluster mode, intended for application illustrated by Figure 60. LED strings not used in
Display mode can be used for Cluster mode, or not used. When = 111 all strings
are in cluster mode.
Phase shift
90 degrees
Cycle time
1/(fPWM)
Cycle time
1/(fPWM)
Phase shift
120 degrees
VBOOST
VBOOST
OUT1
DISPLAY
OUT1
DISPLAY
OUT2
DISPLAY
OUT2
DISPLAY
1
OUT3
DISPLAY
1
2
3
2
External
power
supply
3
4
OUT3
DISPLAY
4
Output 4 in
cluster mode
or not
connected
OUT4
CLUSTER
OUT4
DISPLAY
4-channel Phase Shift PWM (Mode 0)
3-channel Phase Shift PWM (Mode 1)
Cycle time
1/(fPWM)
Phase shift 120 degrees
Phase shift
180 degrees
Cycle time
1/(fPWM)
OUT1
DISPLAY
OUT1
DISPLAY
External
power
supply
VBOOST
OUT2
DISPLAY
1
2
3
4
OUT3
CLUSTER
Outputs 3 and
4 in cluster
mode or not
connected
External
power
supply
VBOOST
OUT2
CLUSTER
1
OUT3
CLUSTER
2
3
4
3
4
Outputs 2,3
and 4 in
cluster mode
or not
connected
OUT4
CLUSTER
OUT4
CLUSTER
Phase shift 120 degrees
2-channel Phase Shift PWM (Mode 2)
Phase shift
180 degrees
Cycle time
1/(fPWM)
Phase Shift PWM (Mode 3)
VBOOST
Cycle time
1/(fPWM)
OUT1
OUT2
DISPLAY
1
OUT3
OUT4
DISPLAY
2
3
OUT1
OUT2
OUT3
OUT4
DISPLAY
4
1
Mode 4
Cycle time
1/(fPWM)
External
power
supply
OUT1
OUT2
DISPLAY
1
OUT4
CLUSTER
Cycle time
1/(fPWM)
VBOOST
VBOOST
OUT3
CLUSTER
2
Mode 5
Phase shift
90 degrees
Phase shift
120 degrees
VBOOST
2
3
Outputs 3 and
4 in cluster
4 mode or not
connected
OUT1
CLUSTER
OUT2
CLUSTER
OUT3
CLUSTER
1
2
3
4
OUT4
CLUSTER
Phase shift
120 degrees
Mode 6
Mode 7
Figure 18. Phase Shift Modes
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Table 9. Description of the LED Output Modes
28
MODE
LED_STRING_CONF[2:0]
0
000
4 separate LED strings with 90° phase shift
DESCRIPTION
1
001
3 separate LED strings with 120° phase shift (String 4 in cluster mode or
not used)
2
010
2 separate LED strings with 180° phase shift (Strings 3 and 4 in cluster
mode or not used)
3
011
1 LED string. (Strings 2,3 and 4 in cluster mode or not used)
4
100
2 LED strings (1+2, 3+4) with 180° phase shift. Strings with same phase
can be connected together.
5
101
1 LED string (1+2+3+4). All strings with same phase (can be tied together).
6
110
1 LED string (1+2). 1st and 2nd strings tied with same phase, strings 3 and
4 are in cluster mode or not used
7
111
All strings are used in cluster mode with 90° phase shift
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Table 10. Output Mode Configuration
LED_STRING_CONF[2:0]
SETUP
000
001
010
011
100
101
110
111
No. of
Displ.
Strings
No. of
Cluster
Strings
No. of
Displ.
Strings
No. of
Cluster
Strings
No. of
Displ.
Strings
No. of
Cluster
Strings
No. of
Displ.
Strings
No. of
Cluster
Strings
No. of
Displ.
Strings
No. of
Cluster
Strings
No. of
Displ.
Strings
No. of
Cluster
Strings
No. of
Displ.
Strings
No. of
Cluster
Strings
No. of
Displ.
Strings
No. of
Cluster
Strings
4
0
3
1
2
1+1
1
1+1+1
2+2
0
same
phase/
4 tied
0
same
phase/
2 tied
1+1
0
1+1+1+1
Y
Y
N
Y
N
Y
N
Y
Y
N
N
Open LED string
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Short LED string
Y
Y
Y
Y
Y
N
Y
Y
Y/N
Y/N
Y
Y
Y
Y
N
Y
N
Y
N
Y
Y
Y
N
N
Y
Y
Brightness modes
All
All
Reg. only
All
Reg. only
All
Reg. only
All
All
All
Reg. only
Reg. only
PMW dimming
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Adaptive voltage control
Y
FAULT DETECTION
OPTIONS
Sloper
Dithering
Int. temp. current dimming
Ext. temp. current limit
Ext. temp. current dimming
Y
Hybrid PWM and Current Dimming
Y
N
Y
N
N
Y
Y
N
N
LED OUTPUT PARAMETERS (PLL Frequency 40 MHz)
ƒLED
PWM
min
Resolution at min ƒLED PWM
fLED
PWM max
4.9 kHz
4.9 kHz
4.9 kHz
4.9 kHz
13
13
13
13
13
39 kHz
39 kHz
39 kHz
39 kHz
4.9 kHz
Resolution at max ƒLED PWM
10
Additional Dither for Display
4
10
4
N
4
N
10
4
N
4
4
4.9 kHz
10
4
13
N
N
LED OUTPUT PARAMETERS (PLL Frequency 5 MHz/off
fLED
PWM
min
Resolution at min ƒLED PWM
ƒLED
PWM
Max
4.9 kHz
4.9 kHz
4.9 kHz
4.9 kHz
10
10
10
10
13
39 kHz
39 kHz
39 kHz
39 kHz
610 Hz
Resolution at max ƒLED PWM
7
Additional bits with dither
4
7
4
N
4
N
610 Hz
7
4
N
4
4
4
13
N
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8.3.4 LED Current Setting
EXT_TEMP_GAIN[3:0]
EXT_TEMP_MINUS[1:0]
EXT_TEMP_I_DIMMING_EN
TSENSE
TEMPERATURE
CURRENT
DIMMING
DRV_OUT1_CORR[3:0]
R1
DRV_EN_EXT_LED_CUR_CTRL
RISET
R2
NTC
RT
ISET
EXTERNAL
CURRENT
SETTING
1
LED CURRENT
SINK 1
OUT1
DAC
0
VREF
DRV_OUT2_CORR[3:0]
CL2_CURRENT[7:0]
DAC
LED CURRENT
SINK 2
OUT2
DRV_OUT3_CORR[3:0]
CL3_CURRENT[7:0]
DAC
LED CURRENT
SINK 3
OUT3
DRV_OUT4_CORR[3:0]
CL4_CURRENT[7:0]
DISP_CL1_CURRENT[11:0]
DAC
LED CURRENT
SIUNK 4
OUT4
DRV_LED_BIAS_CTRL[1:0]
DRV_EN_SPLIT_FET
DRV_LED_CURRENT_SCALE[2:0]
Copyright © 2016, Texas Instruments Incorporated
Figure 19. LED Current Setting
The output LED current can be set by a register. Maximum output LED current can be set by an external resistor
when that option is enabled. For strings in cluster mode current for every LED output can be set independently.
The maximum current for the LED outputs in display mode are controlled with
bits. Current for the outputs in the cluster mode are controlled separately by the register bits
, , , and
respectively. In the display mode resolution for current control is 12 bits. In the cluster mode resolution is 8 bits
for all outputs except OUT1. For OUT1 maximum current resolution is always 12 bits.
Additionally, current for every output current can be scaled with bits (see
Table 11) and can be corrected by EEPROM bits. The adjustment range is shown in
Table 12 Maximum current settings are effective for display and cluster modes.
Table 11. LED Current Scaling
30
DRV_LED_CURRENT_SCALE[2:0]
MAXIMUM CURRENT
000
25 mA
001
30 mA
010
50 mA
011
60 mA
100
80 mA
101
100 mA
110
120 mA
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Table 11. LED Current Scaling (continued)
DRV_LED_CURRENT_SCALE[2:0]
MAXIMUM CURRENT
111
150 mA
When maximum current is controlled by anexternal resistor RISET (=1),
current for outputs in display mode or for OUT1 in cluster mode can be calculated as follows:
ILED
3000 u VBG DISP _ CL1_ CURRENT[11: 0] DRV _LED_ CURRENT _ SCALE[2 : 0] (DRV _ OUTx _ CORR[3 : 0] 100)
u
u
u
RISET
4095
150
100
(2)
Where VBG = 1.2 V.
space
For example, if is 0xFFF, is 111, and a
24-kΩ RISET resistor is used, then the LED maximum current is 150 mA.
When current control with external resistor is disabled (=0) LED current for
outputs in display mode or for OUT1 in cluster mode can be calculated as follow:
ILED
DISP _ CL1_ CURRENT[11: 0]
(DRV _ OUTx _ CORR[3 : 0] 100)
u DRV _LED _ CURRENT _ SCALE[2 : 0] u
4095
100
(3)
When maximum current control with external resistor is enabled, LED current for OUT2…OUT4 outputs in cluster
mode is defined as:
ILED
3000 u VBG CLx _ CURRENT[7 : 0] DRV _ LED _ CURRENT _ SCALE[2 : 0] (DRV _ OUTx _ CORR[3 : 0] 100)
u
u
u
RISET
255
150
100
(4)
Otherwise, when current control with external resistor is disabled:
ILED
CLx _ CURRENT[7 : 0]
(DRV _ OUTx _ CORR[3 : 0] 100)
u DRV _LED _ CURRENT _ SCALE[2 : 0] u
255
100
(5)
Correction value is defined by shown in Table 12:
Table 12. Individual Current Correction
DRV_OUTx_CORR[3:0]
CORRECTION
0000
6.50%
0001
5.60%
0010
4.70%
0011
3.70%
0100
2.80%
0101
1.90%
0110
0.90%
0111
0.00%
1000
–0.9%
1001
–1.90%
1010
–2.80%
1011
–3.70%
1100
–4.70%
1101
–5.60%
1110
–6.50%
1111
–7.40%
NOTE
Formulas are only approximation for the actual current.
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The register is initialized during start-up by the
EEPROM bits. are initialized by the
EEPROM bits. Cluster mode current registers for outputs OUT2 and OUT3 are initialized by 0 during power on
reset.
Current register value must be not written to 0 if brightness is not zero – it may cause LED faults and adaptive
voltage control instability.
8.3.5 Cluster Mode
Cluster is a simplified mode which allows independent current and PWM control for every string in cluster mode.
In this mode brightness control is limited to conventional PWM through the SPI/I2C brightness registers. The
PWM input pin, Hybrid PWM and Current dimming mode, slope control, or dither are not available. Brightness for
different LED strings depends on , , and
registers. If OUT1 is in cluster mode, only 13 MSB are used. If all LED outputs are in the
cluster mode, LED output PWM resolution is always 13 bits, and frequency depends on
bits (see Table 13). If one or more of the LED outputs is in display mode, frequency,
and resolution for strings in the cluster mode is the same as for strings in the display mode (see Table 1).
CL#_CURRENT[7:0]
Cluster
Current
Register
CL#_BRT[12:0]
Cluster
Brightness
Register
...
PWM
Comparator
CLUSTER
MODE LED
CURRENT
SINKS
PWM_RESOLUTION[1:0]
PWM
Counter
PWM_FREQ[3:0]
PLL Clock 5...40 MHz
Copyright © 2016, Texas Instruments Incorporated
Figure 20. Cluster Mode Block Diagram
Table 13. Output PWM Frequency for Mode 7 (All Strings in Cluster Mode)
PWM_RESOLUTION[1:0]
00
01
10
11
OSC frequency (MHz)
5
10
20
40
ƒLED PWM (Hz)
610
1221
2442
4883
When the LP8860-Q1 is set in cluster mode, fault protection functionality is limited. Headroom for LED strings
must be between the high-voltage comparator level and low-voltage comparator
level (which depend upon saturation voltage); otherwise a fault is generated.
Adaptive boost control does not follow strings in cluster mode. Display mode strings and cluster mode strings
must not be connected to the same boost. When LED strings in display and cluster modes are connected to the
same boost, LED open or short faults may be generated if the LED forward-voltage mismatch is too high.
If all LED outputs are in cluster mode, boost output voltage is fixed and must be set by EEPROM
bits to a value high enough to ensure correct LED string operation in all
conditions.
=0 disables cluster LED fault detection, even if all LED strings are in the cluster mode.
The current de-rating (based on the internal temperature sensor) and LED current limitation (based on external
temperature sensor) are not functional in this mode, and analog current dimming based on the external sensor
functionality is limited (LED shutdown for high temperature is not operational).
32
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8.3.6 Boost Controller
The LP8860-Q1 boost controller generates a 16-V to 48-V supply voltage for the LEDs. Output voltage can be
increased by an external resistive voltage divider connected to the FB pin, but voltage lower than 16 V is not
supported.
The output voltage can be controlled either with EEPROM register bits , or
automatic adaptive boost control can be used. During start-up the output voltage is ramped to default start-up
voltage where it then adapts to the required voltage based on LED output
headroom voltage (if adaptive mode has been enabled in EEPROM). Initial voltage for adaptive voltage control
mode must be higher than LED string voltage — otherwise the system may generate a boost overvoltage fault
during VDDIO/EN pin toggling if the output boost capacitor is not discharged below the initial voltage before the
next boost start-up. A different option is to set bit high to prevent a boost
overvoltage fault.
The converter is a magnetic switching PWM mode DC-DC converter with a current limit. The topology of the
magnetic boost converter is called Current Programmed Mode (CPM) control, where the inductor current is
measured and controlled with the feedback. Switching frequency is selectable from 100 kHz and 2.2 MHz with
EEPROM bits . In most cases lower frequency has the highest system efficiency.
In adaptive mode the boost output voltage is adjusted automatically based on LED current sink headroom
voltage. Boost output voltage control step size is, in this case, 125 mV to ensure as small as possible current
sink headroom and high efficiency. The adaptive mode is enabled with the bit. If boost is
started with adaptive mode enabled, then the initial boost output voltage value is defined with the
EEPROM register bits in order to eliminate long output voltage iteration time
when boost is started after VDDIO/EN toggling or power-on reset.
Boost can be clocked by an external SYNC signal (100 kHz to 2.2 MHz); minimum pulse length for the signal is
200 ns. If an external SYNC disappears, boost uses internal frequency defined by
EEPROM bits. The boost frequency with external SYNC and EEPROM bits-defined frequency need to be close
to each other; maximum frequency mismatch is ±25%. The boost controller has optional spread-spectrum
switching operation (±3% from central frequency, 1.875-kHz modulation frequency) which reduces spectrum
spikes around the switching frequency and its harmonic frequencies.
Further EMI reduction can be achieved by limiting the rise and fall times of the FET with an additional external
resistor on the GD pin.
The boost gate driver is powered directly from VDD voltage or from the charge pump which multiplies VDD
voltage by 2. If the charge pump is disabled, the VDD and CPUMP pins must be tied together.
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BOOST_INIT_VOLTAGE[5:0]
OCP
BOOST_SEL_LLC[1:0]
FB
BOOST_SEL_I[1:0]
LIGHT
LOAD
BOOST_SEL_P[1:0]
OVP
BOOST_GD_VOLT
FB Divider
BLANK TIME
R
RC Filter
R
S
R
GD
-
GM
R
+
GATE DRIVER
BOOST_DRIVER_SIZE[1:0]
BOOST_SEL_JITTER_FILTER[1:0]
BOOST_EN_SPREAD_SPECTRUM
BOOST_FREQ_SEL[2:0]
CURRENT SENSE
CURRENT RAMP
GENERATOR
OFF/BLANK TIME
PULSE GENERATOR
ISENSE
ISENSE 25m
BOOST OSCILLATOR
GM
MUX
ISENCE_GND
SYNC
BOOST_EXT_CLK_SEL
BOOST_IMAX_SEL[2:0]
BOOST_SEL_IRAMP[1:0]
BOOST_BLANKTIME_SEL[1:0]
BOOST_EN_IRAMP_SU_DELAY
BOOST_OFFTIME_SEL[1:0]
Copyright © 2016, Texas Instruments Incorporated
Figure 21. Boost Converter Topology
8.3.7 Charge Pump
The boost switch FET gate driver is powered typically from VDD voltage. When the VDD voltage is not high
enough to drive the boost FET gate, the charge pump can be used to increase gate-driver voltage.
The charge pump effectively doubles the VDD voltage for gate driver. Maximum DC output current is 50 mA.
Boost driver voltage selection bit BOOST_GD_VOLT must be set to 1 before enabling the charge pump. If VDD
voltage is 5 V, the charge pump is not typically needed. In this case, a flying capacitor is not necessary, and the
charge pump output CPUMP pin must be connected to the VDD input pin.
GATE DRIVER
CP_2X_EN
CP_2X_CLK[1:0]
SQW_PULSE_GEN_EN
CPUMP
CP_2X_FAULT
CHARGE PUMP
SQW
VDD
C1P
C1N
Copyright © 2016, Texas Instruments Incorporated
Figure 22. Charge Pump
Table 14. Charge Pump Clock Frequency
34
CP_2X_CLK
FREQUENCY (kHz)
00
104
01
208
10
417
11
833
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Square-waveform (SQW) output provides a 100-kHz square wave signal (1 mA max) with amplitude equal to the
charge pump output voltage. When the charge pump is disabled, amplitude of this voltage is equal to VDD. This
signal can be used to generate low-current voltage rails; for example, a gate-reference voltage for output
protective FET (Figure 61) or for using nMOSFET as power-line FET (Figure 25). Figure 23 and Figure 24 show
examples of possible connections.
C1P
C1N
GD
SD
VSENSE_N
ISENSE
VSENSE_P
VRAIL
5V
~10V
SQW
VDD
CPUMP
LP8860
Copyright © 2016, Texas Instruments Incorporated
Figure 23. VRAIL Multiplied by 2
C1P
C1N
SD
VSENSE_N
GD
ISENSE
VSENSE_P
VRAIL
3.3V
~13.2V
VDD
SQW
CPUMP
LP8860
~6.6V
Copyright © 2016, Texas Instruments Incorporated
Figure 24. VRAIL Multiplied by 4
RISENSE
Q2
L1
Up to 40V
D1
C2x
CIN
Q1
C1P
C1N
SD
VSENSE_N
GD
ISENSE
VSENSE_P
VDD
RSENSE
ISENSE_GND
FB
CPUMP
LP8860
SQW
Copyright © 2016, Texas Instruments Incorporated
Figure 25. Using nFET for Power-Line Control
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8.3.8 Powerline Control FET
The power-line FET limits peak current from the power line during start-up and allows the boost and LED strings
to be disconnected during a fault condition, when device is in fault recovery state.
The power-line control block has VSENSE_P and VSENSE_N pins for sensing input current and a shutdown SD
pin for driving the gate of the power-line FET. The power-line FET is opened when the LP8860-Q1 is enabled by
VDDIO/EN signal and VIN is greater than VGS in steady state (when pFET is used as a power-line FET). A powerline pFET must be chosen with minimal VGS in steady state. Gate current is defined by the
EEPROM bits.
VIN
RISENSE
CIN
tVGSt
IG
SD
PL_SD_SINK_LEVEL[1:0]
VSENSE_N
NMOS_PLFET_EN
VSENSE_P
Copyright © 2016, Texas Instruments Incorporated
Figure 26. Power-line FET Control
During a shutdown state the LP8860-Q1 closes the power-line FET and prevents possible boost and LED
leakage. Sense pins are used to detect overcurrent. Power-line FET is closed when an OCP fault occurs. A VIN
OCP is indicated with PL_FET_FAULT bit. The power-line FET closes with all faults, followed by entering to a
recovery state.
When it is not possible to choose a pFET with the necessary characteristics, a schematic with nFET can be used
(see Charge Pump section, Figure 25); the bit must be set accordingly. In this
case the SD pin provides current to shut down the power-line nFET during fault condition.
8.3.9 Protection and Fault Detection Modes
The LP8860-Q1 has fault detection for LED outputs, low and high input voltage, power line overcurrent, boost
overcurrent, boost overvoltage, and charge pump overload. In addition, the device has thermal shutdown and
LED overtemperature protection with an external NTC thermistor.
Faults have dedicated fault flags in registers and . Mask bits can be used to disable
certain faults (see Table 17 for details). In addition the open-drain output pin FAULT can be used to indicate
occurred fault. Writing CLEAR_FAULTS or setting the NSS pin (I2C interface mode only) high resets the fault.
Setting the VDDIO/EN pin low, then high again, resets the faults as well.
8.3.9.1 LED Fault Comparators and Adaptive Boost Control
Every LED current sink has 3 comparators for adaptive boost control and fault detection. Each comparator
outputs is filtered. Filter control bits select how many PWM generator clock
cycles (5 MHz if PLL disabled or PLL clock) high/mid comparator is filtered before it is used to detect shorted
LEDs and boost voltage down-scaling. Usually 1 µs is sufficient; for 5-MHz frequency it means
= 0000b, 10 MHz = 0001b, 20 MHz = 0010b, and 40 MHz = 0011b.
Adaptive boost-control function adjusts the boost output voltage to the minimum sufficient voltage for proper LED
current sink operation. The output with the highest VF LED string is detected and the boost output voltage
adjusted accordingly. Current sink headroom can be adjusted with EEPROM bits . Boost
adaptive control voltage step size is 125 mV. Boost adaptive control operates similarly with and without PSPWM.
Additionally, when faster boost response is needed in larger brightness steps, the "jump" command can be used.
Jump allows increase of the boost voltage with greater steps. Jump is enabled with the EEPROM
bit. The threshold for the magnitude of brightness increase that requires use of jump can be set with the
EEPROM bits. EEPROM bits define when the
jump command is activated.
36
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VBOOST
Driver
headroom
OUT4 string VF
OUT3 string VF
OUT2 string VF
OUT1 string VF
VBOOST
Figure 27. Boost Voltage Adaptation
OUT#
DRV_LED_FAULT_THR[1:0]
HIGH_COMP
DRV_LED_COMP_HYST[1:0]
MID_COMP
DRV_HEADR[2:0]
LOW_COMP
DAC
Figure 28. Output Voltage Comparators
VOUT VOLTAGE
Figure 29 shows different cases which cause boost voltage increase, decrease, or generate faults.
Boost
decreases
voltage
No actions
No actions
Boost up level
reached for 1
output only
All outputs are
above boost up
level
HIGH_COMP
Boost
increases
voltage
Open LED fault
when
VBOOST=MAX
Boost down
level
reached
Open LED
fault
Short LED fault (at least
one output should be
between LOW_COMP
and MID_COMP)
Short LED
fault
MID_COMP
OUT4
OUT3
OUT1
OUT2
OUT4
OUT3
OUT1
OUT2
OUT4
OUT3
OUT2
OUT1
OUT4
OUT3
OUT2
OUT1
OUT4
OUT3
OUT1
OUT2
OUT4
OUT3
OUT1
OUT2
LOW_COMP
Figure 29. Protection and Boost Adaptation Algorithms
NOTE
In the Cluster mode, if voltage of one or more outputs is below LOW_COMP, it causes
open LED fault detection.
8.3.9.2 LED Current Dimming With Internal Temperature Sensor
The LP8860-Q1 can prevent thermal shutdown (TSD) by reducing the average LED strings current based on die
temperature.
When die temperature reaches EEPROM bits-defined threshold, the device automatically
lowers the brightness (2.25% / ºC typical). Depending on brightness control mode either PWM duty cycle or
current is used for average current reduction.
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BRIGHTNESS %
100%
50%
TSD
90
100
110
120
130
150
140
160
TEMPERATURE (ƒ&)
Figure 30. Thermal De-Rating Function
Example With 100% and 50% Brightness
Table 15. Thermal De-rating Function Temperature
Thresholds
INT_TEMP_LIM[1:0]
TEMPERATURE
00
disabled
01
90ºC
10
100ºC
11
110ºC
Table 16. Temperature ADC Output for Different Temperatures
TEMPERATURE (°C)
38
DECIMAL OUTPUT VALUE OF TEMP[10:0] REGISTER
VDD 3.6 (V)
VDD 5 (V)
–40
885
891
–35
901
907
–30
916
923
–25
932
939
–20
948
954
–15
964
970
-10
980
986
-5
994
1002
0
1010
1018
5
1026
1034
10
1041
1050
15
1057
1066
20
1073
1082
25
1089
1098
30
1105
1115
35
1121
1131
40
1137
1147
45
1154
1163
50
1170
1180
55
1186
1196
60
1202
1212
65
1219
1229
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Table 16. Temperature ADC Output for Different Temperatures (continued)
DECIMAL OUTPUT VALUE OF TEMP[10:0] REGISTER
TEMPERATURE (°C)
VDD 3.6 (V)
VDD 5 (V)
70
1235
1245
75
1252
1262
80
1268
1278
85
1285
1293
90
1301
1310
95
1318
1328
100
1332
1343
105
1349
1359
110
1365
1375
8.3.9.3 LED Current Limitation With External NTC Sensor
The EEPROM bit enables the LED current limitation mode. The principle of current
limitation is shown in Figure 31.
When LED temperature reaches level, the device automatically tries to reduce
LED average current step-by-step by 3.125% from maximum brightness value. Step time is defined by
EEPROM bits. If temperature continues to increase and reaches
level, the device shuts down the LEDs and generates a fault condition. The
LEDs are turned on automatically when the temperature is below the level.
Otherwise, if after one or more steps the temperature drops down below ,
brightness increases with the same step time until it reaches the original level. The LP8860-Q1 uses PWM duty
reduction to reduce LED current. The device detects external NTC resistor availability, and the
flag is set, if the NTC sensor is missing (resistance is 2 MΩ or more).
PWM
TEMPERATURE
HIGH LEVEL
PWM
Temperature
LOW LEVEL
TIME
Figure 31. LED Current Limitation With NTC
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TEMPERATURE
EXT_TEMP_LEVEL_LOW[3:0]
EXT_TEMP_FLAG_L
FAULT PIN
READ STATUS REGISTER
(EXT_TEMP_FLAG_L and
EXT_TEMP_FLAG_H bits)
WRITE CLEAR FAULTS
Figure 32. Timing Diagram for LED Current Limitation With NTC
8.3.9.4 LED Current Dimming With External NTC Sensor
When an external resistor for maximum current control is used, current dimming for LED current can be used
also. In this case LED current can be de-rated when ambient temperature is high. This option must be enabled
by and EEPROM bits.
Knee point and slope are defined by and EEPROM bits
respectively. LED shutdown temperature is defined by bits. Serial and parallel
resistors R1 and R2 affect the slope and knee point and can be used for the thermal curve adjustment and NTC
linearization.
100%
LED CURRENT
Knee Point
High Temperature Comparator Level
EXT_TEMP_LEVEL_HIGH[3:0]
I1
I2
AMBIENT TEMPERATURE T1
T2
Figure 33. Current Dimming for High Ambient Temperature
R1
R2
RT
NTC
Figure 34. NTC Linearization
Figure 35 and Figure 36 show the block diagrams for current dimming.
40
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Tsense BLOCK
I
ISET
CURRENT
MULTIPLIER
TSENSE
OUT
LED
CURRENT
SINKS
EXT_TEMP_GAIN[3:0]
OFFSET CURRENT
R2
Tsense
BLOCK
R1
I
NTC
EXT_TEMP_MINUS[1:0]
I
ILED
R2
RT
LIMIT
NTC
TSENSE
R1
T°
EXTERNAL
CURRENT
SETTING
RT
ISET
CURRENT
SUBTRACTOR
ITEMP
Copyright © 2016, Texas Instruments Incorporated
ISET - ITEMP
T°
T°
Copyright © 2016, Texas Instruments Incorporated
Figure 35. Temperature-Dependent NTC Current
(Subtracted from ISET Current)
Figure 36. NTC Current Processing —
Scaling, Shift, and Limitation
Current dimming by external NTC sensor for 150-mA scale can be defined by formulas:
VBG
ISET
u 1000
50 u RISET
ITEMP
ª§
·º
Ǭ
¸»
V
BG
Ǭ
u 1000 3.57PA ¸ »
R2 u RNTC
Ǭ
¸»
« ¨ R1 R2 R
¸»
NTC
¹»
«©
«
»
EXT_TEMP_GAIN[3:0]
«
»
«
»
«
»
«
»
¬
¼
(6)
EXT_TEMP_MINUS[1:0]
(7)
ITEMP cannot be negative; if ITEMP < 0, then ITEMP must be 0.
ILED = (ISET – ITEMP) × 150 mA
ILED cannot go below a 5-mA level; if calculated ILED < 5 mA, then ILED = 5 mA.
where
•
•
•
•
•
•
•
•
ISET: Maximum current setting with external resistor RISET, µA
ITEMP: Temperature compensation, µA
RISET: External resistor, kΩ
R1, R2: Resistors for adjustment, kΩ
ILED: Output current per channel, mA
EXT_TEMP_MINUS[1:0]: 1, 5, 9, 13 µA
EXT_TEMP_GAIN[[3:0]: 50/n, n = 16 to 1
VBG: 1.2 V
(8)
8.3.9.5 Protection Feature and Fault Summary
Table 17 summarizes protection features and related faults.
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Table 17. Overview of the Fault/Protection Schemes
FAULT/PROTECTION
Input overvoltage
protection
THRESHOLD
ACTION (1) (2)
OVP_LEVEL[1:0] (V)
VIN overvoltage monitored from soft start. Fault
causes entry to FAULT_RECOVERY state. If
device is restarted successfully with recovery
timer, the fault register bit is not automatically
cleared.
FAULT pin is pulled low.
MASK_OVP_FSM
Masks fault recovery, but
not status and fault pin
operations
Fault bit and FAULT pin:
1. POR or VDDIO/EN
2. Writing CLEAR_FAULTS bit
or toggling NSS pin
VIN undervoltage monitored from soft start.
Fault causes entry to FAULT_RECOVERY
state. If device is restarted successfully with
recovery timer, the fault register bit is not
automatically cleared.
FAULT pin is pulled low.
MASK_VIN_UVLO
Masks fault recovery,
status and fault pin
operations
Fault bit and FAULT pin:
1.POR or VDDIO/EN
2. Writing CLEAR_FAULTS bit
or toggling NSS pin
FAULT NAME
VIN_OVP
00
OFF
01
7
10
11
11
22.5
UVLO_LEVEL[1:0] (V)
Input undervoltage
protection
VIN_UVLO
00
OFF
01
3
10
5
11
8
VDD_UVLO_LEVEL
Threshold (V)
VDD undervoltage
protection
Boost overcurrent
protection
Boost overvoltage
protection
(1)
(2)
(3)
(4)
(5)
42
0
2.5
1
3
VDD_UVLO
MASK (3)
FAULT CLEARING (4) (5)
Device enters STANDBY state. Recovers when
fault disappears. All registers are cleared or
reloaded from EEPROM (if defined) with
exception registers 0x00, 0x01, 0x04…0x0C.
After recovery LP8860-Q1 provides the same
brightness as before fault detection, if
DISP_CL1_CURRENT[11:0] context stays
same as LED_CURRENT_CTRL[11:0]
EEPROM setting. If VDD voltage goes below
POR level, registers 0x00, 0x01, 0x04…0x0C
are cleared.
This fault does not have any flags and doesn’t
generate FAULT. Voltage hysteresis is 50 mV
(typical).
BOOST_OCP
VBOOST longer than 110 ms 5 V
(typical) below set value.
Set value is voltage value
defined by logic during
adaptation in adaptive mode or
initial boost voltage setting in
manual mode.
Fault monitoring started from boost start. Fault
causes entry to FAULT_RECOVERY state. If
device is restarted successfully with recovery
timer, the fault register bit is not automatically
cleared.
FAULT pin is pulled low.
MASK_BOOST_OCP_
FSM
Masks fault recovery, but
not status and fault pin
operations
Fault bit and FAULT pin:
1. POR or VDDIO/EN
2. Writing CLEAR_FAULTS bit
or toggling NSS pin
BOOST_OVP
VBOOST voltage 1.6 V (typical)
above set value
Set value is voltage value
defined by logic during
adaptation in adaptive mode or
initial boost voltage setting in
manual mode.
Boost OVP fault monitored during normal
operation
FAULT pin is pulled low.
MASK_BOOST_OVP_
STATUS
Fault bit and FAULT pin:
1. POR or VDDIO/EN
2. Writing CLEAR_FAULTS bit
or toggling NSS pin
Recovery time is 100 ms.
During fault recovery state the LED outputs and boost is shut down and power-line FET is turned off.
If fault recovery is masked, fault bit sets again after cleaning.
If fault is cleared during fault recovery state, FAULT pin is pulled low again after recovery state, if this fault still exists.
The NSS pin can be used for fault reset only for I2C interface mode. NSS is level sensitive; be aware NSS is set to low after fault reset.
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Table 17. Overview of the Fault/Protection Schemes (continued)
FAULT/PROTECTION
FAULT NAME
ACTION (1) (2)
THRESHOLD
PL_SD_LEVEL[1:0] (A)
10
Input voltage
overcurrent protection
6
PL_FET_FAULT
11
8
DRV_LED_FAULT_THR[1:0] (V)
Short LED fault
SHORT_LED
00
3.6
01
3.6
10
6.9
11
10.6
DRV_LED_COMP_HYST[1:0]
(mV)
00
1000
01
750
10
500
11
250
DRV_HEADR[2:0] (mV)
Open LED fault
LED faults
Charge pump fault
OPEN_LED
111
VSAT+50
110
VSAT+175
101
VSAT+300
100
VSAT+450
011
VSAT+575
010
VSAT+700
001
VSAT+875
000
VSAT+1000
MASK (3)
FAULT CLEARING (4) (5)
Fault is detected with 2 methods:
1. Detects overcurrent from soft start by
measuring RISENSE voltage.
2. Detects FB voltage at the end of soft start. If
voltage is below 1.2 V, fault is detected. Fault
causes entry to FAULT_RECOVERY state. If
device is restarted successfully with recovery
timer, the fault register bit is not automatically
cleared.
FAULT pin is pulled low.
Fault bit and FAULT pin:
1. POR or VDDIO/EN
2. Writing CLEAR_FAULTS bit
or toggling NSS pin
LED output in display mode: Triggered if one or
more outputs voltage is above
DRV_LED_FAULT_THR and at least one LED
output voltage is between DRV_HEADR and
DRV_HEADR + DRV_LED_COMP_HYST. Is
set only if LED faults are enabled in EEPROM.
Shorted string is removed from voltage control
loop and LED current sink n is disabled.
LED output in cluster mode: If one or more
outputs voltage above DRV_LED_FAULT_THR
fault is detected. Is pulled low only if LED faults
are enabled in EEPROM. Shorted string PWM
output is disabled.
FAULT pin is pulled low.
Fault bit and FAULT pin:
1. POR or VDDIO/EN
EN_DISPLAY_LED_
2. Writing CLEAR_FAULTS bit
FAULT for LEDs in display
or toggling NSS pin
mode
When fault is cleared it can be
EN_CL_LED_FAULT for
set again only during next POR
LEDs in cluster mode
or if there is another LED short
fault in different output.
LED output in display mode: Triggered if one or
more outputs voltage is below DRV_HEADR,
and boost adaptive control has reach the
maximum voltage. Is set only if led faults
enabled in EEPROM. Open string is removed
from voltage control loop and PWM generation
is disabled.
LED output in cluster mode: Triggered if one or
more outputs voltage is below DRV_HEADR. Is
set only if LED faults enabled in EEPROM.
Open string PWM generation is disabled.
FAULT pin is pulled low.
EN_DISPLAY_LED
_FAULT
for LEDs in display mode
EN_CL_LED_FAULT
for LEDs in cluster mode
Fault bit and FAULT pin:
1. POR or VDDIO/EN
2. Writing CLEAR_FAULTS bit
or toggling NSS pin
When open fault is cleared it can
set again only during next
power-up or if there is another
LED open fault.
LED_FAULT[4:1]
Defines which string has either open or short
fault. Cleared only during power down.
POR or VDDIO/EN
CP_2X_ FAULT
Charge pump voltage not high enough
condition. Fault causes entry to
FAULT_RECOVERY state. CP voltage
monitored from the boost soft start. If device is
restarted successfully with recovery timer, the
fault register bit is not automatically cleared.
FAULT pin is pulled low.
Fault bit and FAULT pin:
1. POR or VDDIO/EN
2. Writing CLEAR_FAULTS bit
or toggling NSS pin
VCPUMD < 0.85 × (2 × VDD)
(typical)
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Table 17. Overview of the Fault/Protection Schemes (continued)
FAULT/PROTECTION
FAULT NAME
THRESHOLD
INT_TEMP_LIM[1:0]
Thermal Current Limit
(LED Outputs)
No faults
00
01
10
11
disabled
90°C
100°C
110°C
ACTION (1) (2)
MASK (3)
FAULT CLEARING (4) (5)
When die temperature increases temperature
defined by INT_TEMP_LIM[1:0] the device
automatically lowers the PWM duty for outputs
2.25%/ºC (typical). For Hybrid PWM and
Current dimming mode current is used for
brightness reduction as well.
EXT_TEMP_LEVEL_LOW[3:0]
EXT_TEMP_
FLAG_L
Thermal LED Current
Limit with external
NTC sensor.
Level (kΩ)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
79.67
43.35
29.77
22.67
18.30
15.34
13.21
11.60
10.34
9.32
8.49
7.79
7.20
6.69
6.25
5.87
Fault is monitored during normal operation. If
EXT_TEMP_LEVEL_LOW[3:0] is exceeded,
LED current is reduced.
FAULT pin is pulled low when
EXT_TEMP_FLAG_L goes high.
Fault bit:
1. POR or VDDIO/EN
2. Writing CLEAR_FAULTS bit
or toggling NSS pin when fault
EXT_TEMP_COMP_EN=0
deasserted.
disables fault
Fault pin:
1. POR or VDDIO/EN
2. Writing CLEAR_FAULTS bit
or toggling NSS pin
Fault is monitored during normal operation. If
EXT_TEMP_LEVEL_HIGH[3:0] limit is
exceeded, the LED outputs are turned off.
FAULT pin is pulled low.
Fault bit:
1. POR or VDDIO/EN
2. Writing CLEAR_FAULTS bit
or toggling NSS pin when fault
EXT_TEMP_COMP_EN=0
deasserted.
disables fault
Fault pin:
1. POR or VDDIO/EN
2. Writing CLEAR_FAULTS bit
or toggling NSS pin
EXT_TEMP_LEVEL_HIGH[3:0]
EXT_TEMP_
FLAG_H
44
Setting
Setting
Level (kΩ)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
79.67
43.35
29.77
22.67
18.30
15.34
13.21
11.60
10.34
9.32
8.49
7.79
7.20
6.69
6.25
5.87
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Table 17. Overview of the Fault/Protection Schemes (continued)
THRESHOLD
ACTION (1) (2)
NTC missing
TEMP_RES_
MISSING
Resistance > 2 MΩ
NTC is missing. Fault is monitored during
normal operation. Not connected to FAULT
output pin. TEMP_RES_FAULT is monitored if
EXT_TEMP_COMP_EN EEPROM bit has been
enabled
Thermal shutdown
TSD
Rising temperature =165ºC
Falling temperature = 135ºC
Thermal shutdown is monitored from soft start.
Fault causes entry to the FAULT_RECOVERY
state.
FAULT pin is pulled low.
FAULT/PROTECTION
FAULT NAME
MASK (3)
FAULT CLEARING (4) (5)
1. POR or VDDIO/EN
EXT_TEMP_COMP_EN=0
2. Writing CLEAR_FAULTS bit
disables fault
or toggling NSS pin
Fault bit and FAULT pin:
1. POR or VDDIO/EN
2. Writing CLEAR_FAULTS bit
or toggling NSS pin
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Fault detection is digitally filtered — filtering time for different faults is shown in Table 18.
Table 18. Fault Filters
FAULT/PROTECTON
FAULT NAME
TIME
ENABLED
Boost Overcurrent Protection
BOOST_OCP
110 ms
From boost start
Boost Overvoltage Protection
BOOST_OVP
100 µs
In normal mode
Input Overvoltage Protection
VIN_OVP
100 µs
From soft start
Input Undervoltage Protection
VIN_UVLO
100 µs
From soft start
Input Overcurrent Protection
PL_FET_FAULT
100 µs
From soft start
VDD Undervoltage Protection
VDD_UVLO
5 µs
Always
Thermal Shutdown
TSD
100 µs
From soft start
Charge Pump fault
CP_2X_FAULT
10 µs
From boost start
Thermal LED Current Limit with
external NTC sensor.
EXT_TEMP_FLAG_H
10 µs
In normal mode
EXT_TEMP_FLAG_L
10 µs
In normal mode
NTC missing
TEMP_RES_FAULT
100 µs
In normal mode
OVP Threshold
VIN
OVP Threshold
FB
VSD
tsoftstart
ttRECOVERY = 100 mst
VIN_OVP
FLAG
ttRECOVERY = 100 mst
FAULT PIN
WRITE
CLEAR_FAULTS
Figure 37. Input OVP Triggering and Recovery
UVLO
Threshold
VIN
UVLO
Threshold
FB
VSD
ttRECOVERY = 100 mst
VIN_UVLO
FLAG
tsoftstart
ttRECOVERY = 100 mst
FAULT PIN
WRITE
CLEAR_FAULTS
Figure 38. Input UVLO Triggering and Recovery
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PL_SD_LEVEL[1:0]
IIN
FB
VSD
ttRECOVERY = 100 mst
PL_FET_FAULT
FLAG
tsoftstart
ttRECOVERY = 100 mst
FAULT PIN
WRITE
CLEAR_FAULTS
Figure 39. Input OVP Triggering and Recovery
OVERLOAD CONDITION
OVERLOAD REMOVED
VDDIO/EN
tFILTER = 110 ms
tRECOVERY = 100 ms
tFILTER = 110 ms
tRECOVERY = 100 ms
tFILTER = 110 ms
tRECOVERY = 100 ms
tFILTER = 110 ms
VBOOST SET ± 5 V
FB
VSD
ttshutdownt
ttsoftstartt
BOOST_OCP
FLAG
FAULT PIN
WRITE
CLEAR_FAULTS
Figure 40. Boost OCP Triggering and Recovery
FB
VBOOST SET +1.6 V
VBOOST SET
GD
BOOST_OVP
FLAG
FAULT PIN
WRITE
CLEAR_FAULTS
Figure 41. Boost OVP Triggering and Recovery
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8.4 Device Functional Modes
8.4.1 Standby Mode
The device is in standby mode when the EN/VDDIO pin is low. Current consumption from the VDD pin in this
mode is typically 1 µA.
8.4.2 Active Mode
The EN/VDDIO pin enables the logic and analog blocks. The device goes through the start-up sequence where
EEPROM context is loaded to the registers, the power-line FET is enabled during soft start, and boost starts
during boost start-time. In this mode I2C and SPI communication are available after soft start, and register
settings can be changed.
8.4.3 Fault Recovery State
Fault recovery state is special state which can be caused by faults. In this state power line FET is switched off,
boost and LED current sinks are disabled. I2C or SPI interfaces are available in this state — for example, fault
flags can be read.
POR=1
EEPROM:
SOFT_START_SEL[1:0]
00=5 ms
01=10 ms
10=20 ms
11=50 ms
STANDBY
VDDIO/EN=1
EEPROM READ
~300 s
FAULTS
100 ms
SOFT START
5...50 ms
FAULT RECOVERY
BOOST START
FAULTS or
BOOST_OCP
50 ms
VDDIO/EN=0
NORMAL
FAULTS or
BOOST_OCP
FAULTS:
- PL_FET_FAULT
- VIN_UVLO
- VIN_OVP
- TSD
- CP_2X_FAULT
VDDIO/EN=0
SHUTDOWN
VDD_UVLO=1
Figure 42. State Diagram
8.4.4 Start-Up and Shutdown Sequences
Depending on EEPROM settings the LP8860-Q1 can be started up or shut down differently. Typical startup/shutdown sequence is shown in Figure 43.
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Device Functional Modes (continued)
t>0
t>500 s
VIN
VDD
VDDIO/EN
PL pFET Drain
Headroom Adaptation
VOUT = VIN Level ± Diode Drop
VBOOST
PWM OUT
IQ
Active Mode
tSOFTt
tSTARTt
tBOOSTt
tSTARTt
Figure 43. Timing Diagram for the Typical Start-Up and Shutdown
8.5 Programming
8.5.1 EEPROM
EEPROM memory stores various parameters for chip control. The 200-bit EEPROM memory is organized as 25
× 8 bits. The EEPROM structure consists of a register front-end and the non-volatile memory (NVM). Register
data can be read and written through the I2C/SPI serial interface. EEPROM must be burned with the new data;
otherwise, data disappears after power-on reset or VDDIO/EN cycling. PWM outputs and PLL must be disabled
when writing to EEPROM registers or burning EEPROM ( = 0, = 0,
= 0, = 0, = 0). To read and program EEPROM NVM separate
commands need to be sent. Erase and program voltages are generated internally; no other voltages other than
the normal VDD voltage is required. A complete EEPROM memory map is shown in the Table 23.
The user must make sure that VDD power is on, and the VDDIO/EN pin is kept high, during the whole
programming/burn sequence to avoid memory corruption.
EE_PROG = 1
25 x 8 bits
Startup or
EE_READ=1
EEPROM
REGISTERS
Address 60h...78h
Device Control
I2C/SPI
EEPROM
NVM
User
REGISTERS
ADDRESS 00h...1Ah
Device Control
Figure 44. EEPROM and Register Configuration
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Programming (continued)
EEPROM has protection against accidental writes. EEPROM access can be unlocked by writing a pass code to
the EEPROM_UNLOCK register. It unlocks the EEPROM Control register EEPROM_CNTRL and all EEPROM
registers. Lock is enabled again by writing any other code to the EEPROM_UNLOCK register (for example, 0x00
enables the lock any time).
Table 19. EEPROM Pass Code Protection
PASS CODE TO EEPROM_UNLOCK REGISTER
0x08, 0xBA, 0xEF
EEPROM is used as fixed product-configuration storage, to be set or programmed during production before
normal operation. EEPROM can be reprogrammed for evaluation purposes up to 1000 cycles. Data-retention
lifetime for factory-programmed content is 10 years, minimum. For more details regarding EEPROM options, see
TI Application Note Selecting the Correct LP8860-Q1 EEPROM Version (SNVA757).
50
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8.5.2 Serial Interface
The LP8860-Q1 supports 2 different interface modes:
• SPI interface (4-wire serial)
• I2C-compatible (2-wire serial)
The user can define the interface mode by IF pin as shown in Table 20. The LP8860-Q1 detects interface mode
selection during start-up. When the device is in normal mode, the IF signal does not affect the interface selection.
Table 20. Interface Modes
IF PIN
INTERFACE
GND
I2C
VDDIO
SPI
8.5.2.1 SPI Interface
The LP8860-Q1 is compatible with SPI serial-bus specification, and it operates as a slave. The transmission
consists of 16-bit write and read cycles. One cycle consists of 7 address bits, 1 read/write (R/W) bit, and 8 data
bits. The R/W bit high state defines a write cycle and low defines a read cycle. MISO output is normally in a highimpedance state. When the slave select NSS for LP8680 is active (that is, low), MISO output is pulled low for
both read and write operations, except for the period when Data is sent out during a read cycle. The Address
and Data are transmitted MSB first. The Slave Select signal NSS must be low during the Cycle transmission.
NSS resets the interface when high, and it has to be taken high between successive cycles. Data is clocked in
on the rising edge of the SCLK clock signal, while data is clocked out on the falling edge of SCLK.
NSS
SCLK
MOSI
MISO
A6
A5
A4
A3
A2
A1
A0
1
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Hi-Z
Hi-Z
Figure 45. SPI Write Cycle
NSS
SCLK
MOSI
A6
A5
A4
A3
A2
A1
A0
R/W
0
tDon't Caret
MISO
Hi-Z
D7
D6
D5
D4
D3
D2
D1
D0
Hi-Z
Figure 46. SPI Read Cycle
8.5.2.2 I2C Serial Bus Interface
8.5.2.2.1 Interface Bus Overview
The I2C-compatible synchronous serial interface provides access to the programmable functions and registers on
the device. This protocol is using a two-wire interface for bi-directional communications between the devices
connected to the bus. The two interface lines are the Serial Data Line (SDA), and the Serial Clock Line (SCL).
These lines must be connected to a positive supply through a pullup resistor and remain HIGH even when the
bus is idle.
Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on
whether it generates or receives the SCL. The LP8860-Q1 is always a slave device.
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8.5.2.2.2 Data Transactions
One data bit is transferred during each clock pulse. Data is sampled during the high state of the SCL.
Consequently, throughout the clock high period, the data must remain stable. Any changes on the SDA line
during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New data must
be sent during the low SCL state. This protocol permits a single data line to transfer both command/control
information and data using the synchronous serial clock.
SDA
SCL
Data Line
Stable:
Data Valid
Change
of Data
Allowed
Figure 47. Bit Transfer
Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and a
Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is
transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following
sections provide further details of this process.
Data Output
by
Transmitter
Transmitter Stays Off the
Bus During the
Acknowledgment Clock
Data Output
by
Receiver
Acknowledgment
Signal From Receiver
SCL
1
2
3-6
7
8
9
S
Start
Condition
Figure 48. Start and Stop
The Master device on the bus always generates the Start and Stop Conditions (control codes). After a Start
Condition is generated, the bus is considered busy and it retains this status until a certain time after a Stop
Condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCL) is high indicates a
Start Condition. A low-to-high transition of the SDA line while the SCL is high indicates a Stop Condition.
SDA
SCL
S
P
Start
Condition
Stop
Condition
Figure 49. Stop and Start Conditions
In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a transaction.
This allows another device to be accessed, or a register read cycle.
8.5.2.2.3 Acknowledge Cycle
The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte
transferred, and the acknowledge signal sent by the receiving device.
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The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter
releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver
must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the
high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to
receive the next byte.
8.5.2.2.4 Acknowledge After Every Byte Rule
The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge
signal after every byte received.
There is one exception to the acknowledge after every byte rule. When the master is the receiver, it must
indicate to the transmitter an end of data by not-acknowledging (negative acknowledge”) the last byte clocked out
of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master),
but the SDA line is not pulled down.
8.5.2.2.5 Addressing Transfer Formats
Each device on the bus has a unique slave address. The LP8860-Q1 operates as a slave device with 7-bit
address combined with data direction bit. Default slave address is 2Dh as 7-bit or 5Ah for write and 5Bh for read
in 8-bit format.
Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device
sends an acknowledge signal on the SDA line, once it recognizes its address. The slave address is the first
seven bits after a Start Condition. The direction of the data transfer (R/W) depends on the bit sent after the slave
address — the eighth bit. When the slave address is sent, each device in the system compares this slave
address with its own. If there is a match, the device considers itself addressed and sends an acknowledge
signal. Depending upon the state of the R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver.
MSB
LSB
ADR6
Bit7
ADR5
bit6
ADR4
bit5
ADR3
bit4
ADR2
bit3
ADR1
bit2
ADR0
bit1
x
x
x
x
x
x
x
R/W
bit0
2
I C SLAVE address (chip address)
Figure 50. Address and Read/Write Bit
8.5.2.2.6 Control Register Write Cycle
1.
2.
3.
4.
5.
6.
7.
8.
Master device generates start condition.
Master device sends slave address (7 bits) and the data direction bit (r/w = “0”).
Slave device sends acknowledge signal if the slave address is correct.
Master sends control register address (8 bits).
Slave sends acknowledge signal.
Master sends data byte to be written to the address register.
Slave sends acknowledgement.
Write cycle ends when the master creates stop condition.
8.5.2.2.7 Control Register Read Cycle
1.
2.
3.
4.
5.
6.
7.
8.
9.
Master device generates start condition.
Master device sends slave address (7 bits) and the data direction bit (r/w = “0”).
Slave device sends acknowledge signal if the slave address is correct.
Master sends control register address (8 bits).
Slave sends acknowledge signal if slave address is correct.
Master generates repeated start condition
Master sends the slave address (7 bits) and the data direction bit (r/w = “1”)
Slave sends acknowledgment if the slave address is correct.
Read cycle ends when master does not generate acknowledge signal after data byte and generates stop
condition.
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Table 21. Data Read and Write Cycles
ACTION (1)
MODE
Data Read
[Ack]
[Ack]
[Ack]
[Register Data]
register address possible
Data Write
[Ack]
[Ack]
[Ack]
register address possible
(1)
S
Data from master; [] Data from slave
Slave Address
(7 bits)
'0'
A
Control Register Add.
(8 bits)
Register Data
(8 bits)
A
A
P
Data transfered,
byte + Ack
R/W
From Slave to Master
A - ACKNOWLEDGE (SDA Low)
S - START CONDITION
From Master to Slave
P - STOP CONDITION
Register Write Format
Figure 51. Register Write Format
S
Slave Address
(7 bits)
'0'
A
Control Register Add.
(8 bits)
A
Sr
Slave Address
(7 bits)
'1'
R/W
R/W
A
Data- Data
(8 bits)
A/
P
NA
Data transfered, byte +
Ack/NAck
Direction of the transfer will
change at this point
From Slave to Master
From Master to Slave
A - ACKNOWLEDGE (SDA Low)
NA - ACKNOWLEDGE (SDA High)
S - START CONDITION
Sr - REPEATED START CONDITION
P - STOP CONDITION
Register Read Format
Figure 52. Register Read Format
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8.6 Register Maps
Table 22. Register Map
ADDR
REGISTER
0x00
DISP_CL1_BRT
D7
D6
D5
D4
0x01
0x02
RESERVED
D1
D0
DISP_CL1_CURRENT[11:8]
DISP_CL1_CURRENT[7:0]
CL2_BRT
RESERVED
CL2_BRT[12:8]
0x05
CL2_BRT[7:0]
0x06
CL2_CURRENT
0x07
CL3_BRT
CL2_CURRENT[7:0]
RESERVED
CL3_BRT[12:8]
0x08
CL3_BRT[7:0]
0x09
CL3_CURRENT
0x0A
CL4_BRT
CL3_CURRENT[7:0]
RESERVED
CL4_BRT[12:8]
0x0B
CL4_BRT[7:0]
0x0C
CL4_CURRENT
0x0D
CONFIGURATION
0x0E
STATUS
0x0F
FAULT
0x10
LED FAULT
0x11
FAULT CLEAR
0x12
ID
0x13
TEMP MSB
0x14
TEMP LSB
0x15
DISP LED CURRENT
CL4_CURRENT[7:0]
RESERVED
DRV_LED_CURENT_SCALE[2:0]
EN_ADVANCED_
SLOPE
RESERVED
RESERVED
VIN_OVP
RESERVED
VIN_UVLO
TSD
OPEN_LED
SHORT_LED
PWM_SLOPE[2:0]
BRT_SLOPE_
DONE
TEMP_RES_
MISSING
EXT_TEMP_
FLAG_L
EXT_TEMP_
FLAG_H
BOOST_OCP
BOOST_OVP
PL_FET_
FAULT
CP_2X_
FAULT
LED_FAULT[4:1]
RESERVED
CLEAR_FAULTS
FULL_LAYER_REVISION
METAL_REVISION
RESERVED
TEMP[10:8]
TEMP[7:0]
RESERVED
0x16
0x17
D2
DISP_CL1_BRT[7:0]
DISP_CL1_CURRENT
0x03
0x04
D3
DISP_CL1_BRT[15:8]
LED_CURRENT[11:8]
LED_CURRENT[7:0]
DISP LED PWM
PWM[15:8]
0x18
PWM[7:0]
0x19
EEPROM_CNTRL
0x1A
EEPROM_UNLOCK
EE_READY
RESERVED
EE_PROG
EE_READ
EEPROM_UNLOCK_CODE[7:0]
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Table 23. EEPROM Register Map (1)
ADDR
REGISTER
0x60
EEPROM REG 0
0x61
EEPROM REG 1
D7
D6
EXT_TEMP_MINUS[1:0]
D5
D4
D3
D2
DRV_LED_BIAS_CTRL[1:0]
D1
D0
LED_CURRENT_CTRL[11:8]
LED_CURRENT_CTRL[7:0]
EN_STEADY_
DITHER
PWM_INPUT_HYSTERESIS[1:0]
EN_ADVANCED_
SLOPE
0x62
EEPROM REG 2
RESERVED
0x63
EEPROM REG 3
EN_DISPAY_LED_
FAULT
0x64
EEPROM REG 4
EN_CL_LED_
FAULT
0x65
EEPROM REG 5
0x66
EEPROM REG 6
0x67
EEPROM REG 7
DRV_OUT2_CORR[3:0]
0x68
EEPROM REG 8
DRV_OUT4_CORR[3:0]
DRV_OUT3_CORR[3:0]
0x69
EEPROM REG 9
EXT_TEMP_GAIN[3:0]
BL_COMP_FILTER_SEL[3:0]
0x6A
EEPROM REG
10
0x6B
EEPROM REG
11
0x6C
EEPROM REG
12
0x6D
EEPROM REG
13
0x6E
EEPROM REG
14
0x6F
EEPROM REG
15
0x70
EEPROM REG
16
0x71
EEPROM REG
17
0x72
EEPROM REG
18
BOOST_DRIVER_SIZE[1:0]
0x73
EEPROM REG
19
RESERVED
0x74
EEPROM REG
20
0x75
EEPROM REG
21
0x76
EEPROM REG
22
0x77
EEPROM REG
23
0x78
EEPROM REG
24
DRV_LED_CURRENT_SCALE[2:0]
DRV_LED_COMP_HYST[1:0]
I_SLOPE[2:0]
RESERVED
EXT_TEMP_I_
DIMMING_EN
LED_STRING_CONF[2:0]
DRV_LED_FAULT_THR[1:0]
EN-PWM_I
DRV_HEADR[2:0]
PWM_RESOLUTION[1:0]
DITHER[2:0]
DRV_EN_EXT_
LED_CUR_CTR
GAIN_CTRL[2:0]
NMOS_PLFET_
EN
PWM_SLOPE[2:0]
DRV_EN_SPLI
T_FET
BRT_MODE[1:0]
DRV_OUT1_CORR[3:0]
SOFT_START_SEL[1:0]
PL_SD_LEVEL[1:0]
PL_SD_SINK_LEVEL[1:0]
SLOW_PLL_DIV[12:5]
EN_SYNC
PWM_SYNC
R_SELL[1:0]
PWM_
COUNTER_
RESET
SEL_DIVIDER
RESERVED
MASK_BOOST_
OVP_FSM
MASK_BOOST_
OCP_FSM
RESERVED
BOOST_EN_
SPREAD_
SPECTRUM
SLOW_PLL_DIV[4:0]
EN_PLL
SYNC_PRE_DIVIDER[3:0]
SYNC_TYPE
PWM_FREQ[3:0]
MASK_OVP_
FSM
MASK_VIN_
UVLO
BOOST_EN_
IRAMP _SU_
DELAY
BOOST_EXT_
CLK_SEL
BOOST_SEL_IND[1:0]
EN_ADAP
UVLO_LEVEL[1:0]
BOOST_OFFTIME_SEL[1:0]
BOOST_BLANKTIME_SEL[1:0]
BOOST_SEL_I[1:0]
RESERVED
RESERVED
Unused bits data must not be changed.
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BOOST_SEL_P[1:0]
BOOST_VO_SLOPE_CTRL[2:0]
CP_2X_CLK[1:0]
EXT_TEMP_LEVEL_HIGH[3:0]
(1)
JUMP_STEP_SIZE[1:0]
BOOST_INITIAL_VOLTAGE[5:0]
BOOST_SEL_LLC[1:0]
INT_TEMP_LIM[1:0]
BOOST_FREQ_SEL[2:0]
BRIGHTNESS_JUMP_THRES[1:0]
BOOST_SEL_JITTER_FILTER[1:0
]
VDD_UVLO_LEVE
L
BOOST_GD_
VOLT
BOOST_IMAX_SEL[2:0]
BOOST_SEL_IRAMP[1:0]
EN_JUMP
OVP_LEVEL[1:0]
CP_2X_EN
SQW_PULSE_
GEN_EN
EXT_TEMP_LEVEL_LOW[3:0]
EXT_TEMP_PERIOD[4:0]
EXT_TEMP_
COMP_EN
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8.6.1 Register Bit Explanations
8.6.1.1 Display/Cluster1 Brightness Control MSB
Address 0x00
Reset value 0000 0000b
DISP_CL1_BRT MSB
7
6
5
4
3
2
1
0
1
0
DISP_CL1_BRT[15:8]
Name
Bit
Access
DISP_CL1_BRT[15:8]
7:0
R/W
Description
Backlight brightness control MSB
8.6.1.2 Display/Cluster1 Brightness Control LSB
Address 0x01
Reset value 0000 0000b
DISP_CL1_BRT LSB
7
6
5
4
3
2
DISP_CL1_BRT[7:0]
Name
Bit
Access
DISP_CL1_BRT LSB
7:0
R/W
Description
Backlight brightness control LSB
The DISP_CL1_BRT MSB register must be written first. New value is valid after writing DISP_CL1_BRT LSB. If
output 1 is used in display mode, the Brightness/Cluster Output 1 Brightness Control register is used for all
outputs in display mode (16-bits register). Otherwise it is the Brightness Control register for cluster output 1. For
cluster bit control is 13 bit, most significant bit are used.
8.6.1.3 Display/Cluster1 Output Current MSB
Address 0x02
Reset value loaded during start-up from EEPROM REG0
DISP_CL1_CURRENT MSB
7
6
5
4
3
RESERVED
2
1
0
DISP_CL1_CURRENT[11:8]
Name
Bit
Access
DISP_CL1_CURRENT[11:8]
3:0
R/W
Description
Display/Cluster current control MSB
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8.6.1.4 Display/Cluster1 Output Current LSB
Address 0x03
Reset value loaded during start-up from EEPROM REG1
DISP_CL1_CURRENT LSB
7
6
5
4
3
2
1
0
DISP_CL1_CURRENT[7:0]
Name
Bit
Access
DISP_CL1_CURRENT[7:0]
7:0
R/W
Description
Display/Cluster current control LSB
The DISP_CL1_CURRENT MSB register must be written first. New value is valid after writing
DISP_CL1_CURRENT LSB. If one of few outputs is used in display mode, the DISP_CL1_CURRENT register is
used for all outputs in display mode (12-bit), otherwise it is Cluster1 Output Current register.
Maximum current is defined by DRV_LED_CURRENT_SCALE[2:0] bits.
8.6.1.5 Cluster2 Brightness Control MSB
Address 0x04
Reset value 0000 0000b
CL2_BRT MSB
7
6
5
4
3
RESERVED
2
1
0
1
0
CL2_BRT[12:8]
Name
Bit
Access
CL2_BRT[12:8]
4:0
R/W
Description
Cluster output 2 brightness control MSB
8.6.1.6 Cluster2 Brightness Control LSB
Address 0x05
Reset value 0000 0000b
CL2_BRT LSB
7
6
5
4
3
2
CL2_BRT[7:0]
Name
Bit
Access
CL2_BRT[7:0]
7:0
R/W
Description
Cluster output 2 brightness control LSB
The CL2_BRT MSB register must be written first. New value is valid after writing CL2_BRT LSB.
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8.6.1.7 Cluster2 Output Current
Address 0x06
Reset value 0000 0000b
CL2_CURRENT
7
6
5
4
3
2
1
0
2
1
0
1
0
CL2_CURRENT[7:0]
Name
Bit
Access
CL2_CURRENT[7:0]
7:0
R/W
Description
Cluster output 2 current control
Maximum current is defined by DRV_LED_CURRENT_SCALE[2:0] bits.
8.6.1.8 Cluster3 Brightness Control MSB
Address 0x07
Reset value 0000 0000b
CL3_BRT MSB
7
6
5
4
3
RESERVED
CL3_BRT[12:8]
Name
Bit
Access
CL3_BRT[12:8]
4:0
R/W
Description
Cluster output 3 brightness control MSB
8.6.1.9 Cluster3 Brightness Control LSB
Address 0x08
Reset value 0000 0000b
CL3_BRT LSB
7
6
5
4
3
2
CL3_BRT[7:0]
Name
Bit
Access
CL3_BRT[7:0]
7:0
R/W
Description
Cluster output 3 brightness control LSB
The CL3_BRT MSB register must be written first. New value is valid after writing CL3_BRT LSB.
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8.6.1.10 Cluster3 Output Current
Address 0x09
Reset value 0000 0000b
CL3_CURRENT
7
6
5
4
3
2
1
0
2
1
0
1
0
CL3_CURRENT[7:0]
Name
Bit
Access
CL3_CURRENT[7:0]
7:0
R/W
Description
Cluster output 3 current control
Maximum current is defined by DRV_LED_CURRENT_SCALE[2:0] bits.
8.6.1.11 Cluster4 Brightness Control MSB
Address 0x0A
Reset value 0000 0000b
CL4_BRT MSB
7
6
5
4
3
RESERVED
CL4_BRT[12:8]
Name
Bit
Access
CL4_BRT[12:8]
4:0
R/W
Description
Cluster output 4 brightness control MSB
8.6.1.12 Cluster4 Brightness Control LSB
Address 0x0B
Reset value 0000 0000b
CL4_BRT LSB
7
6
5
4
3
2
CL4_BRT[7:0]
Name
Bit
Access
CL4_BRT[7:0]
7:0
R/W
Description
Cluster output 4 brightness control LSB
The CL4_BRT MSB register must be written first. New value is valid after writing CL4_BRT LSB.
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8.6.1.13 Cluster4 Output Current
Address 0x0C
Reset value 0000 0000b
CL4_CURRENT
7
6
5
4
3
2
1
0
1
0
CL4_CURRENT[7:0]
Name
Bit
Access
CL4_CURRENT[7:0]
7:0
R/W
Description
Cluster output 4 current control
Maximum current is defined by DRV_LED_CURRENT_SCALE[2:0] bits.
8.6.1.14 Configuration
Address 0x0D
Reset value loaded during start-up from EEPROM
CONFIGURATION
7
6
RESERVED
5
4
3
DRV_LED_CURRENT_SCALE[2:0]
2
EN_ADVANCED
_SLOPE
PWM_SLOPE[2:0]
Name
Bit
Access
DRV_LED_CURRENT_SCALE[2:0]
6:4
R/W
Description
Scales the maximum LED current when EN_EXT_LED_CUR_CTRL = 0
Effective for display and cluster mode.
000 = 25 mA
001 = 30 mA
010 = 50 mA
011 = 60 mA
100 = 80 mA
101 = 100 mA
110 = 120 mA
111 = 150 mA
EN_ADVANCED_SLOPE
3
R/W
Enable for advanced slope (smooth brightness change)
0 = Linear slope used only
1 = Advanced slope used
PWM_SLOPE[2:0]
2:0
R/W
Linear brightness sloping time (typical)
000 = 0 ms
001 = 1 ms
010 = 2 ms
011 = 52 ms
100 = 105 ms
101 = 210 ms
110 = 315 ms
111 = 511 ms
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8.6.1.15 Status
Address 0x0E
Reset value 0000 0000b
STATUS
7
6
5
4
RESERVED
3
2
1
0
BRT_SLOPE_DONE
TEMP_RES_MISSING
EXT_TEMP_FLAG_L
EXT_TEMP_FLAG_H
Name
Bit
Access
BRT_SLOPE_DONE
3
R
Description
Status bit for the brightness sloping
0 = Sloping ongoing
1 = Sloping done
TEMP_RES_MISSING
2
R
NTC sensor missing flag
0 = sensor OK
1 = NTC sensor missing
EXT_TEMP_FLAG_L
1
R
External temperature sensor low limit exceeded flag
0 = limit not detected
1 = low temperature limit detected
EXT_TEMP_FLAG_H
0
R
External temperature sensor high limit exceeded flaf
0 = limit not detected
1 = high temperature limit detected
8.6.1.16 Fault
Address 0x0F
Reset value 0000 0000b
STATUS
7
6
5
4
3
2
1
0
RESERVED
VIN_OVP
VIN_UVLO
TSD
BOOST_OCP
BOOST_OVP
PL_FET_FAULT
CP_2X_FAULT
62
Name
Bit
Access
VIN_OVP
6
R
Description
VIN overvoltage protection flag
0 = No fault
1 = Fault detected
VIN_UVLO
5
R
VIN undervoltage lockout flag
0 = No fault
1 = Fault detected
TSD
4
R
Thermal shutdown
0 = No flag
1 = Fault detected
BOOST_OCP
3
R
Boost overcurrent protection flag
0 = No flag
1 = Fault detected
BOOST_OVP
2
R
Boost output overvoltage protection flag
0 = No flag
1 = Fault detected
PL_FET_FAULT
1
R
VIN overcurrent protection flag
0 = No fault
1 = Fault detected
CP_2X_FAULT
0
R
Charge pump output voltage too low
0 = No fault
1 = Fault detected
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8.6.1.17 LED Fault
Address 0x10
Reset value 0000 0000b
LED FAULT
7
6
RESERVED
5
4
OPEN_LED
SHORT_LED
3
2
1
0
LED_FAULT[4:1]
Name
Bit
Access
OPEN_LED
5
R
Description
Open LED fault.
0 = No fault
1 = Fault detected
SHORT_LED
4
R
Short LED fault.
0 = No fault
1 = Fault detected
LED_FAULT[4:1]
3:0
R
Defines which string has either open or short fault.
0001 = LED OUT1
0010 = LED OUT2
0100 = LED OUT3
1000 = LED OUT4
8.6.1.18 Fault Clear
Address 0x11
Reset value 0000 0000b
FAULT CLEAR
7
6
5
4
3
2
1
RESERVED
Name
Bit
Access
CLEAR_FAULTS
0
W
0
CLEAR_FAULTS
Description
Write only bit, writing CLEAR_FAULTS high clears faults.
8.6.1.19 Identification
Address 0x12
ID
7
6
5
4
3
FULL_LAYER_REVISION[3:0]
2
1
0
METAL REVISIONS[3:0]
Name
Bit
Access
FULL_LAYER_REVISION
7:4
R
Description
Manufacturer ID code – full layer revision
METAL REVISIONS
3:0
R
Manufacturer ID code – metal mask revision
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8.6.1.20 Temp MSB
Address 0x13
TEMP MSB
7
6
5
4
3
2
RESERVED
Name
Bit
Access
TEMP[10:8]
2:0
R
1
0
TEMP[10:8]
Description
Device internal temperature sensor reading, first 3 MSB. MSB must be read before LSB,
because reading of MSB register latches the data.
8.6.1.21 Temp LSB
Address 0x14
TEMP LSB
7
6
5
4
3
2
1
0
TEMP[7:0]
Name
Bit
Access
TEMP[7:0]
7:0
R
Description
Device internal temperature sensor reading, last 8 LSB. MSB must be read before LSB,
because reading of MSB register latches the data.
8.6.1.22 Display LED Current MSB
Address 0x15
DISP LED CURRENT MSB
7
6
5
4
3
RESERVED
2
1
0
LED_CURRENT[11:8]
Name
Bit
Access
LED_CURRENT[11:8]
3:0
R
Description
Display LED current value reading, first 3 MSB. DISP LED CURRENT MSB must be
read before DISP LED CURRENT LSB, DISP LED PWM MSB, and DISP LED PWM
LSB because reading of the MSB register latches the data for current and PWM.
8.6.1.23 Display LED Current LSB
Address 0x16
DISP LED CURRENT LSB
7
6
5
4
3
2
1
0
LED_CURRENT[7:0]
Name
Bit
Access
LED_CURRENT[7:0]
7:0
R
64
Description
Display LED current value reading, last 8 LSB.
Note: DISP LED CURRENT MSB latches the data for current and PWM.
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8.6.1.24 Display LED PWM MSB
Address 0x17
Reset value 0000 0000b
DISP LED PWM MSB
7
6
5
4
3
2
1
0
PWM[15:8]
Name
Bit
Access
PWM[7:0]
7:0
R
Description
Display LED current value reading, first 8 MSB.
Note: DISP LED CURRENT MSB latches the data for current and PWM.
8.6.1.25 Display LED PWM LSB
Address 0x18
Reset value 0000 0000b
DISP LED PWM LSB
7
6
5
4
3
2
1
0
PWM[7:0]
Name
Bit
Access
PWM[7:0]
7:0
R
Description
Display LED PWM reading, last 8 LSB.
Note: DISP LED CURRENT MSB latches the data for current and PWM.
8.6.1.26 EEPROM Control
Address 0x19
Reset value 1000 0000b
EEPROM CTRL
7
6
5
4
EE_READY
3
2
RESERVED
1
0
EE_PROG
EE_READ
Name
Bit
Access
EE_READY
7
R
Description
EE_PROG
1
R/W
EEPROM programming
0 = Normal operation
1 = Start the EEPROM programming sequence. Programs data currently in the
EEPROM registers to non-volatile memory (NVM).
EE_READ
0
R/W
EEPROM read
0 = Normal operation
1 = Reads the data from NVM to the EEPROM registers. Can be used to restore
default values if EEPROM registers are changed during testing.
EEPROM ready
0 = EEPROM programming or read in progress
1 = EEPROM ready, not busy
Programming sequence (program data permanently from registers to NVM):
1. Turn on the chip by setting VDDIO/EN pin high.
2. Unlock EEPROM by writing the unlock codes to register 0x1A.
– Write 0x08 to address 0x1A
– Write 0xBA to address 0x1A
– Write 0xEF to address 0x1A
3. Write data to EEPROM registers (address 0x60…0x78).
4. Write EE_PROG to high in address 0x19. (0x02 to address 0x19).
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5. Wait 200 ms.
6. Write EE_PROG to low in address 0x19. (0x00 to address 0x19).
Read sequence (load data from NVM to registers):
1. Turn on the chip by writing setting VDDIO/EN pin high.
2. Unlock EEPROM by writing the unlock codes to register 0x1A.
– Write 0x08 to address 0x1A
– Write 0xBA to address 0x1A
– Write 0xEF to address 0x1A
3. Write EE_READ to high in address 0x19. (0x01 to address 0x19).
4. Wait 1 ms.
5. Write EE_READ to low in address 0x19. (0x00 to address 0x19).
NOTE
EEPROM bits are intended to be set/programmed before normal operation only once
during silicon production, but can be reprogrammed for evaluation purposes up to 1000
cycles.
8.6.1.27 EEPROM Unlock Code
Address 0x1A
Reset value 0000 0000b
EEPROM UNLOCK
7
6
5
4
3
2
1
0
EEPROM UNLOCK_CODE[7:0]
66
Name
Bit
Access
EEPROM_UNLOCK_CODE[7:0]
7:0
W
Description
Unlock EEPROM control register (0x19) and EEPROM registers.
Writing 0x08, 0xBA, 0xEF sequence unlocks EEPROM registers.
Lock is enabled again by writing any other code to the register.
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8.6.2 EEPROM Bit Explanations
8.6.2.1 EEPROM Register 0
Address 0x60
EEPROM REGISTER 0
7
6
5
EXT_TEMP_MINUS[1:0]
4
3
DRV_LED_BIAS_CTRL[1:0]
2
1
0
LED_CURRENT_CTRL[11:8]
Name
Bit
EXT_TEMP_MINUS[1:0]
7:6
Access Description
R/W
External temperature sensor current dimming knee point, see LED Current Dimming
With Internal Temperature Sensor for details.
00 = 1 μA
01 = 5 μA
10 = 9 μA
11 = 13 μA
DRV_LED_BIAS_CTRL[1:0]
5:4
R/W
Controls the LED current sink bias current. Effects LED current sink rise time and
current consumption. 150-mA LED current is suggested.
00 = slowest LED current sink setting and low Iq (typical 800-ns rise time / 200 μA
per sink)
01 = slow (typical 400-ns rise time / 400 μA per sink)
10 = fast (typical 200-ns rise time / 800 μA per sink)
11 = fastest LED current sink and higher current consumption (typical100-ns rise
time / 1.6 mA per sink)
LED_CURRENT_CTRL[11:8]
3:0
R/W
MSB bits for 12-bit LED current control. Step size is 150 mA / 4095 = 36.63 µA
(typical) when max current is set to 150 mA. Max current can be scaled with RISET
resistor or with DRV_LED_CURRENT_SCALE EEPROM bits.
000h = 0 mA
001h = 0.037 mA
002h = 0.073 mA
003h = 0.110 mA
…
FFEh = 149.963 mA
FFFh = 150.000 mA
8.6.2.2 EEPROM Register 1
Address 0x61
EEPROM REGISTER 1
7
6
5
4
3
2
1
0
LED_CURRENT_CTRL[7:0]
Name
Bit
LED_CURRENT_CTRL[7:0]
7:0
Access Description
R/W
LSB bits for 12-bit LED current control. Step size is 150 mA / 4095 = 36.63 µA when
max current is set to 150 mA. Max current can be scaled with RISET resistor or with
DRV_LED_CURRENT_SCALE EEPROM bits.
000h = 0 mA
001h = 0.037 mA
002h = 0.073 mA
003h = 0.110 mA
…
FFEh = 149.963 mA
FFFh = 150.000 mA
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8.6.2.3 EEPROM Register 2
Address 0x62
EEPROM REGISTER 2
7
6
RESERVED
EN_STEADY_DITHER
5
4
PWM_INPUT_HYSTERESIS[1:0]
3
EN_ADVANCED_SLOPE
2
1
0
PWM_SLOPE[2:0]
Name
Bit
Access
EN_STEADY_DITHER
6
R/W
Enable dithering in steady state condition
0 = Disabled, dithering used in sloping (brightness changes) only
1 = Enabled, dithering used in sloping as well as steady-state condition. Dithering
defined with DITHER[2:0] bits.
PWM_INPUT_HYSTERESIS[1:0]
5:4
R/W
PWM input hysteresis function. Defines how small changes in the PWM input are
ignored. Hysteresis used to remove constant switching between two values.
00 = ±1-step hysteresis with 16-bit resolution
01 = ±8-step hysteresis with 16-bit resolution
10 = ±16-step hysteresis with 16-bit resolution
11 = ±256-step hysteresis with 16-bit resolution
EN_ADVANCED_SLOPE
3
R/W
Advanced smooth slope for brightness changes
0 = Advanced slope is disabled
1 = Use advanced slope for brightness change to make brightness changes
smooth for eye
PWM_SLOPE[2:0]
2:0
R/W
Linear brightness sloping time (typical)
000 = Slope function disabled, immediate brightness change
001 = 1 ms
010 = 2 ms
011 = 52 ms
100 = 105 ms
101 = 210 ms
110 = 315 ms
111 = 511 ms
68
Description
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8.6.2.4 EEPROM Register 3
Address 0x63
EEPROM REGISTER 3
7
EN_DISPLAY_LED_FAULT
6
5
4
DRV_LED_CURRENT_SCALE[2:0]
3
2
LED_STRING_CONF[2:0]
1
0
EN_PWM_I
Name
Bit
Access
Description
EN_DISPLAY_LED_FAULT
7
R/W
0 = LED open/short faults disabled
1 = LED open/short faults enabled
DRV_LED_CURRENT_SCALE[2:0]
6:4
R/W
Scales the maximum LED current when EN_EXT_LED_CUR_CTRL = 0
Effective for both modes – display and cluster.
000 = 25 mA
001 = 30 mA
010 = 50 mA
011 = 60 mA
100 = 80 mA
101 = 100 mA
110 = 120 mA
111 = 150 mA
LED_STRING_CONF[2:0]
3:1
R/W
LED current sink configuration
000 = 4 separate LED strings with 90° phase shift
001 = 3 separate LED strings with 120° phase shift (String 4 in cluster mode or
not used)
010 = 2 separate LED strings with 180° phase shift (Strings 3 and 4 in cluster
mode or not used)
011 = 1 LED string. (Strings 2,3 and 4 in cluster mode or not used)
100 = 2 LED strings (1+2, 3+4) with 180° phase shift. Tied strings with same
phase.
101 = 1 LED string (1+2+3+4). Tied strings with same phase
110 = 1 LED string (1+2). 1st and 2nd strings tied with same phase, strings 3
and 4 are in cluster mode or not used
111 = All strings are used in cluster mode
EN_PWM_I
0
R/W
Enable Hybrid PWM and Current dimming mode
0 = Disabled, dimming only with PWM
1 = Enabled
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8.6.2.5 EEPROM Register 4
Address 0x64
EEPROM REGISTER 4
7
6
EN_CL_LED_FAULT
70
5
4
DRV_LED_COMP_HYST[1:0]
3
DRV_LED_FAULT_THR[1:0]
2
1
0
DRV_HEADER[2:0]
Name
Bit
Access
Description
EN_CL_LED_FAULT
7
R/W
Enable open/short LED fault for cluster strings
0 = LED fault in cluster mode disabled
1 = LED fault in cluster mode enabled
DRV_LED_COMP_HYST[1:0]
6:5
R/W
LED comparator hysteresis – difference between mid and low
comparator, used for boost adaptive voltage control (boost high
level)
00 = 1000 mV
01 = 750 mV
10 = 500 mV
11 = 250 mV
DRV_LED_FAULT_THR[1:0]
4:3
R/W
LED Fault thresholds, used for short LED detection.
00 = 3.6 V
01 = 3.6 V
10 = 6.9 V
11 = 10.6 V
DRV_HEADER[2:0]
2:0
R/W
LED current sink headroom control, used for boost adaptive voltage
control (boost low level) and open LED detection.
VSAT is the saturation voltage of the sink, typically 500 mV with 150mA current.
111 = VSAT + 50 mV
110 = VSAT + 175 mV
101 = VSAT + 300 mV
100 = VSAT + 450 mV
011 = VSAT + 575 mV
010 = VSAT + 700 mV
001 = VSAT + 875 mV
000 = VSAT + 1000 mV
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8.6.2.6 EEPROM Register 5
Address 0x65
EEPROM REGISTER 5
7
6
5
I_SLOPE[2:0]
4
3
2
PWM_RESOLUTION[1:0]
1
0
DITHER[2:0]
Name
Bit
Access
Description
I_SLOPE[2:0]
7:5
R/W
Slope gain adjusts the current slope for Hybrid PWM and Current
dimming mode
000 = 1.000
001 = 1.023
010 = 1.047
011 = 1.070
100 = 1.094
101 = 1.117
110 = 1.141
111 = 1.164
PWM_RESOLUTION[1:0]
4:3
R/W
For PWM clocking with internal oscillator (VSYNC is not used) these
bits control the PLL multiplier and hence the PWM output resolution
00 = 5-MHz clock used for generating PWM
01 = 10-MHz clock used for generating PWM
10 = 20-MHz clock used for generating PWM
11 = 40-MHz clock used for generating PWM
DITHER[2:0]
2:0
R/W
Dither function controls
000 = Dither function disabled
001 = 1-bit dither
010 = 2-bit dither
011 = 3-bit dither
1XX = 4-bit dither
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8.6.2.7 EEPROM Register 6
Address 0x66
EEPROM Register 6
7
6
RESERVED
5
4
GAIN_CTRL[2:0]
3
2
EN_EXT_LED_CUR_CTRL
DRV_EN_SPLIT_FET
1
0
BRT_MODE[1:0]
Name
Bit
Access
Description
GAIN_CTRL[2:0]
6:4
R/W
Switch point from PWM to current control for Hybrid PWM and
Current dimming mode
000 = 50.0%
001 = 40.6%
010 = 31.3%
011 = 25.0%
100 = 21.9%
101 = 18.8%
110 = 15.6%
111 = 12.5%
EN_EXT_LED_CUR_CTRL
3
R/W
Enable LED current set resistor
0 = Resistor is disabled and current is scaled with SCALE[2:0]
EEPROM register bits
1 = Enable LED current set resistor. LED current is scaled by the
RISET resistor
DRV_EN_SPLIT_FET
2
R/W
LED current sink FET control
0 = big size FET is driving LED current
1 = enable use of smaller FET for driving low LED output currents.
Smaller FET is selected automatically when current setting is below
1/16 of the scale. Automatic scaling improves accuracy for output
currents below 1/16 of the full current scale.
BRT_MODE[1:0]
1:0
R/W
Brightness control mode
00 = PWM input pin duty cycle control
01 = PWM input duty x Brightness register
10 = Brightness register
11 = Direct PWM control from PWM input pin
5
4
8.6.2.8 EEPROM Register 7
Address 0x67
EEPROM Register 7
7
6
3
DRV_OUT2_CORR[3:0]
72
2
1
0
DRV_OUT1_CORR[3:0]
Name
Bit
Access
DRV_OUT2_CORR[3:0]
7:4
R/W
Description
Current correction for OUT2 LED current sink
0000 = 6.5%
0001 = 5.6%
0010 = 4.7%
0011 = 3.7%
0100 = 2.8%
0101 = 1.9%
0110 = 0.9%
0111 = 0.0%
1000 = –0.9%
1001 = –1.9%
1010 = –2.8%
1011 = –3.7%
1100 = –4.7%
1101 = –5.6%
1110 = –6.5%
1111 = –7.4%
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Name
Bit
Access
DRV_OUT1_CORR[3:0]
3:0
R/W
5
4
Description
Current correction for OUT1 LED current sink
0000 = 6.5%
0001 = 5.6%
0010 = 4.7%
0011 = 3.7%
0100 = 2.8%
0101 = 1.9%
0110 = 0.9%
0111 = 0.0%
1000 = –0.9%
1001 = –1.9%
1010 = –2.8%
1011 = –3.7%
1100 = –4.7%
1101 = –5.6%
1110 = –6.5%
1111 = –7.4%
8.6.2.9 EEPROM Register 8
Address 0x68
EEPROM Register 8
7
6
3
DRV_OUT4_CORR[3:0]
2
1
0
DRV_OUT3_CORR[3:0]
Name
Bit
Access
DRV_OUT4_CORR[3:0]
7:4
R/W
Description
Current correction for OUT4 LED current sink
0000 = 6.5%
0001 = 5.6%
0010 = 4.7%
0011 = 3.7%
0100 = 2.8%
0101 = 1.9%
0110 = 0.9%
0111 = 0.0%
1000 = –0.9%
1001 = –1.9%
1010 = –2.8%
1011 = –3.7%
1100 = –4.7%
1101 = –5.6%
1110 = –6.5%
1111 = –7.4%
DRV_OUT3_CORR[3:0]
3:0
R/W
Current correction for OUT3 LED current sink
0000 = 6.5%
0001 = 5.6%
0010 = 4.7%
0011 = 3.7%
0100 = 2.8%
0101 = 1.9%
0110 = 0.9%
0111 = 0.0%
1000 = –0.9%
1001 = –1.9%
1010 = –2.8%
1011 = –3.7%
1100 = –4.7%
1101 = –5.6%
1110 = –6.5%
1111 = –7.4%
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8.6.2.10 EEPROM Register 9
Address 0x69
EEPROM Register 8
7
6
5
4
3
EXT_TEMP_GAIN[3:0]
74
2
1
0
BL_COMP_FILTER_SEL[3:0]
Name
Bit
Access
Description
EXT_TEMP_GAIN[3:0]
7:4
R/W
External temperature sensor current dimming gain control, see LED
Current Dimming With Internal Temperature Sensor for details.
BL_COMP_FILTER_SEL[3:0]
3:0
R/W
Filter selects how many PWM generator clock cycles high/mid
comparator is filtered before it is used to detect shorted LEDs and
boost voltage down scaling.
0000 = 5
0001 = 10
0010 = 20
0011 = 40
0100 = 60
0101 = 80
0110 = 100
0111 = 140
1000 = 180
1001 = 220
1010 = 260
1011 = 300
1100 = 340
1101 = 380
1110 = 420
1111 = 460
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8.6.2.11 EEPROM Register 10
Address 0x6A
EEPROM Register 9
7
6
EXT_TEMP_I_DIMMING_
EN
NMOS_PLFET_EN
5
4
3
SOFT_START_SEL[1:0]
2
1
PL_SD_LEVEL[1:0]
0
PL_SD_SINK_LEVEL[1:0]
Name
Bit
Access
EXT_TEMP_I_DIMMING_EN
7
R/W
Description
External temperature sensor current dimming enabled
0 = disabled
1 = enabled
NMOS_PLFET_EN
6
R/W
Powerline FET selection:
0 = pFET
1 = nFET
SOFT_START_SEL[1:0]
5:4
R/W
Soft-start time selection
00 = 5 ms
01 = 10 ms
10 = 20 ms
11 = 50 ms
PL_SD_LEVEL[1:0]
3:2
R/W
Power-line FET current limit selection VIN OCP (assumed RISENSE = 20 mΩ).
10 = 6 A
11 = 8 A
PL_SD_SINK_LEVEL[1:0]
1:0
R/W
Power-line FET gate current
NMOS_PLFET_EN = 0
(current for normal mode)
NMOS_PLFET_EN = 1
(current for fault recovery mode,
otherwise 0mA)
00
55 µA
0.3 mA
01
110 µA
0.5 mA
10
220 µA
1.0 mA
11
440 µA
2.2 mA
8.6.2.12 EEPROM Register 11
Address 0x6B
EEPROM Register 11
7
6
5
4
3
2
1
0
SLOW_PLL_DIV[12:5]
Name
Bit
Access
SLOW_PLL_DIV[12:5]
7:0
R/W
Description
Divider for VSYNC operation. 8 MSB bits
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8.6.2.13 EEPROM Register 12
Address 0x6C
EEPROM Register 12
7
6
5
EN_SYNC
PWM_SYNC
PWM_COUNTER_RESET
4
3
2
1
0
SLOW_PLL_DIV[4:0]
Name
Bit
Access
Description
EN_SYNC
7
R/W
VSYNC input enable
0 = VSYNC input disabled
1 = VSYNC input enabled
PWM_SYNC
6
R/W
Enable PWM generation synchronization to VSYNC signal
0 = Disabled
1 = Enabled. PWM output used for phase detector input after
dividing with SLOW_PLL_DIV divider
PWM_COUNTER_RESET
5
R/W
Enable PWM generator resetting on VSYNC signal rising edge
0 = Disabled
1 = Enabled
SLOW_PLL_DIV[4:0]
4:0
R/W
Divider for VSYNC operation. 5 LSB bits
8.6.2.14 EEPROM Register 13
Address 0x6D
EEPROM Register 13
7
6
R_SEL[1:0]
76
5
4
SEL_DIVIDER
EN_PLL
3
2
1
0
SYNC_PRE_DIVIDER[3:0]
Name
Bit
Access
Description
R_SEL[1:0]
7:6
R/W
Coefficient for the slow PLL divider
00 = 16
01 = 32
10 = 64
11 = 128
SEL_DIVIDER
5
R/W
PLL divider selection
0 = Slow PLL divider with external compensation (when using
VSYNC)
1 = Fast PLL divider with internal compensation (when using 5-MHz
internal clock)
EN_PLL
4
R/W
PLL enable
0 = PLL disabled and internal 5-MHz oscillator used for PWM
generation
1 = PLL is used for generating the PWM generation clock from the
internal oscillator or VSYNC signal
SYNC_PRE_DIVIDER[3:0]
3:0
R/W
VSYNC signal pre-divider from 1 to 16. Used when VSYNC
frequency is higher than PWM output frequency.
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8.6.2.15 EEPROM Register 14
Address 0x6E
EEPROM Register 14
7
6
5
RESERVED
4
3
SYNC_TYPE
2
1
0
PWM_FREQ[3:0]
Name
Bit
Access
Description
SYNC_TYPE
4
R/W
Type of the VSYNC input. Affects the PLL functionality.
0 = HSYNC (50 to 150 kHz)
1 = VSYNC (50 to 150 Hz)
PWM_FREQ[3:0]
3:0
R/W
PWM output frequency setting when internal oscillator is used. See
Brightness Control (Display Mode)
8.6.2.16 EEPROM Register 15
Address 0x6F
EEPROM Register 13
7
6
5
4
MASK_BOOST_OVP_
STATUS
MASK_BOOST_OCP
_FSM
MASK_OVP_FSM
MASK_VIN_UVLO
3
2
UVLO_LEVEL[1:0]
1
0
OVP_LEVEL[1:0]
Name
Bit
Access
MASK_BOOST_OVP_STATUS
7
R/W
Description
Boost overvoltage protection enable
0 = Enabled
1 = Fault bit and FAULT pin disabled.
MASK_BOOST_OCP_FSM
6
R/W
Boost overcurrent protection fault recovery state enable
0 = Enabled
1 = Entering fault recovery state disabled. Fault bit and FAULT pin
operate normally.
MASK_OVP_FSM
5
R/W
VIN overvoltage fault recovery state enable
0 = Enabled
1 = Entering fault recovery state disabled. Fault bit and FAULT pin
operate normally.
MASK_VIN_UVLO
4
R/W
VIN undervoltage lockout fault recovery state enable
0 = Enabled
1 = Entering fault recovery state disabled. Fault bit and FAULT pin
operate normally.
UVLO_LEVEL[1:0]
3:2
R/W
VIN Undervoltage protection thresholds (UVLO)
00 = disabled
01 = 3 V
10 = 5 V
11 = 8 V
OVP_LEVEL[1:0]
1:0
R/W
VIN Overvoltage protection thresholds (OVP)
00 = disabled
01 = 7 V
10 = 11 V
11 = 22.5 V
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8.6.2.17 EEPROM Register 16
Address 0x70
EEPROM Register 16
7
6
5
RESERVED
78
4
3
BOOST_EN_IRAMP_DELAY BOOST_EXT_CLK_SEL
2
1
BOOST_IMAX_SEL[2:0]
0
BOOST_GD_VOLT
Name
Bit
Access
Description
BOOST_EN_IRAMP_DELAY
5
R/W
Boost current ramp delay enable (for adjusting conversion
ratio/stability, 35% of period)
1 = Delay enabled
0 = Delay disabled
BOOST_EXT_CLK_SEL
4
R/W
Boost clock selection
0 = Internal clock
1 = External clock (SYNC pin)
If external clock selected and sync disappears for 1.5…2 periods,
boost automatically switches to using internal oscillator with
frequency defined by BOOST_FREQ_SEL[2:0]
BOOST_IMAX_SEL[2:0]
3:1
R/W
Maximum current limit for boost SW mode. Values below based on
25-mΩ sense resistor value.
000 = 2 A
001 = 3 A
010 = 4 A
011 = 5 A
100 = 6 A
101 = 7 A
110 = 8 A
111 = 9 A
BOOST_GD_VOLT
0
R/W
Boost gate driver voltage selection
1 = Charge pump output (VGATE DRIVER > 6 V)
0 = VDD
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8.6.2.18 EEPROM Register 17
Address 0x71
EEPROM Register 17
7
6
BOOST_EN_SPREAD_
SPECTRUM
5
4
BOOST_SEL_IND[1:0]
3
2
BOOST_SEL_IRAMP[1:0]
1
0
BOOST_FREQ_SEL[2:0]
Name
Bit
Access
BOOST_EN_SPREAD_
SPECTRUM
7
R/W
Description
Boost spread spectrum (±3% from central frequency, 1.875 kHz modulation
frequency) enable
0 = Spread spectrum disabled
1 = Spread spectrum enabled
BOOST_SEL_IND[1:0]
6:5
R/W
See BOOST_SEL_IRAMP for selecting BOOST_SEL_IND setting
BOOST_SEL_IRAMP[1:0]
4:3
R/W
Boost artificial current ramp peak value, A/s.
Select value higher than IRAMP_GAIN:
IRAMP_GAIN =1.2 x 0.5 x (VOUTmax - VINmin)/(0.7 x L x 60000), where VIN, VOUT are
boost input and output voltage, L - inductance, H. 25-mΩ RSENSE is suggested.
BOOST_SEL_IND[1:0]
BOOST_FREQ_SEL[2:0]
2:0
R/W
BOOST_SEL_IRAMP
[1:0]
00
01
10
11
00
130
65
34
29
01
88
43
23
20
10
56
28
15
13
11
37
18
10
8.5
BOOST_EXT_CLK_SEL=0
Boost output frequency selection (internal oscillator)
000= 100 kHz
001 = 200 kHz
010 = 303 kHz
011 = 400 kHz
100 = 629 kHz
101 = 800 kHz
110 = 1100 kHz
111 = 2200 kHz
BOOST_EXT_CLK_SEL=1
Boost output frequency selection (for external sync mode if external sync
disappears)
000= 100 kHz
001 = 200 kHz
010 = 303 kHz
011 = 400 kHz
100 = 625 kHz
101 = 833 kHz
110 = 1111 kHz
111 = 2500 kHz
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8.6.2.19 EEPROM Register 18
Address 0x72
EEPROM Register 16
7
6
BOOST_DRIVER_SIZE[1:0]
5
4
EN_ADAP
EN_JUMP
3
2
BRIGHTNESS_JUMP_THRES[1:0]
1
0
JUMP_STEP_SIZE[1:0]
Name
Bit
Access
BOOST_DRIVER_SIZE[1:0]
7:6
R/W
Boost gate driver scaling. Affects gate driver peak current and SW
node voltage rise/fall times
00 = 0.4/0.45 A (typical) peak sink/source current
01 = 0.75/0.87 A (typical) peak sink/source current
10 = 1.2/1.3 A (typical) peak sink/source current
11 = 1.5/1.7 A (typical) peak sink/source current
EN_ADAP
5
R/W
Enable boost converter adaptive mode
0 = adaptive mode disabled, boost converter output voltage is set with
BOOST_INITIAL_VOLTAGE EEPROM register bits.
1 = adaptive mode enabled. Boost converter start-up voltage is set
with BOOST_INITIAL_VOLTAGE EEPROM register bits. Further boost
voltage is adapted to the highest LED string VF.
If all LED outputs are in cluster mode, adaptive mode is disabled
automatically.
EN_JUMP
4
R/W
Enable large boost voltage jump command for the fast brightness
increase.
0 = Normal steps used for boost voltage control
1 = Jump command allowed in boost voltage control
BRIGHTNESS_JUMP_THRES[1:0]
3:2
R/W
Defines the magnitude of the input brightness change after which jump
command is given.
00 = Jump command after 10% brightness change
01 = Jump command after 30% brightness change
10 = Jump command after 50% brightness change
11 = Jump command after 70% brightness change
JUMP_STEP_SIZE[1:0]
1:0
R/W
Boost control step size that jump command increases backlight boost
output voltage
00: 8 steps (1.0 V typ)
01: 16 steps (2.0 V typ)
10: 32 steps (4.0 V typ)
11: 64 steps (8.0 V typ)
80
Description
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8.6.2.20 EEPROM Register 19
Address 0x73
EEPROM Register 19
7
6
5
4
3
RESERVED
2
1
0
BOOST_INITIAL_VOLTAGE[5:0]
Name
Bit
Access
BOOST_INITIAL_VOLTAGE[5:0]
5:0
R/W
Description
Boost voltage control from 16 V to 47.5 V with 0.5 V step (without
FB resistive divider). When resistive divider is used on the FB pin,
the voltages are scaled accordingly. If adaptive boost control is
enabled, this sets the initial start voltage for the boost converter. If
adaptive mode is disabled, this sets the output voltage of the boost
converter.
000000 = 16.0 V (typical)
000001 = 16.5 V (typical)
000010 = 17.0 V (typical)
000011 = 17.5 V (typical)
000100 = 18.0 V (typical)
...
111100 = 46.0 V (typical)
111101 = 46.5 V (typical)
111110 = 47.0 V (typical)
111111 = 47.5 V (typical)
8.6.2.21 EEPROM Register 20
Address 0x74
EEPROM Register 20
7
6
BOOST_SEL_LLC[1:0]
5
4
3
BOOST_SEL_JITTER_FILTER[1:0]
2
1
BOOST_SEL_I[1:0]
0
BOOST_SEL_P[1:0]
Name
Bit
Access
Description
BOOST_SEL_LLC[1:0]
7:6
R/W
Light load comparator control. Selects boost PFM entry threshold
(compensator current)
00 = 5 μA (boost switches from PFM to PWM early at light loads)
01 = 10 μA
10 = 15 μA
11 = 20 μA (boost operates in PFM mode to higher loads)
BOOST_SEL_JITTER_FILTER[1:0]
5:4
R/W
Boost jitter filter selection
00 = bypass
01 = 300 kHz
10 = 60 kHz
11 = 30 kHz
BOOST_SEL_I[1:0]
3:2
R/W
Boost PI compensator control: integral part
00 = 1
01 = 2
10 = 3
11 = 4
BOOST_SEL_P[1:0]
1:0
R/W
Boost PI compensator control: proportional part
00 = 1
01 = 2
10 = 3
11 = 4
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8.6.2.22 EEPROM Register 21
Address 0x75
EEPROM Register 21
7
6
BOOST_OFFTIME_SEL[1:0]
5
4
BOOST_BLANKTIME_SEL[1:0]
3
2
RESERVED
1
0
BOOST_VO_SLOPE_CTRL[2:0]
Name
Bit
Access
Description
BOOST_OFFTIME_SEL[1:0]
7:6
R/W
Boost time off selection
00 = 131 ns
01 = 68 ns
10 = 38 ns
11 = 24 ns
BOOST_BLANKTIME_SEL[1:0]
5:4
R/W
Boost blank time selection
00 = 162 ns
01 = 88 ns
10 = 63 ns
11 = 40 ns
BOOST_VO_SLOPE_CTRL[2:0]
2:0
R/W
Sets the speed for boost output voltage scaling up or down
000 = 1 (every PWM cycle)
001 = 2 (every other PWM cycle)
010 = 3 (every third PWM cycle)
011 = 4 (every 4th PWM cycle)
100 = 5 (every 5th PWM cycle)
101 = 6 (every 6th PWM cycle)
110 = 8 (every 8th PWM cycle)
111 = 16 (every 16th PWM cycle)
8.6.2.23 EEPROM Register 22
Address 0x76
EEPROM Register 20
7
6
VDD_UVLO_
LEVEL
82
5
4
RESERVED
3
2
CP_2X_CLK[1:0]
1
0
CP_2X_EN
SQW_PULSE_
GEN_EN
Name
Bit
Access
Description
VDD_UVLO_LEVEL
7
R/W
VDD UVLO protection level
0 = 2.5 V
1 = 3.0 V
Voltage hysteresis typically 50 mV.
2.5V level can be used if PLL frequency up to 20 MHz. With higher
PLL frequency logic is not specified to work down to 2.5 V VDD
CP_2X_CLK[1:0]
3:2
R/W
Charge pump clock frequency
00 = 104 kHz
01 = 208 kHz
10 = 417 kHz
11 = 833 kHz
CP_2X_EN
1
R/W
Charge pump enable. CP is enabled at soft start if CP_2X_EN
EEPROM bit asserted.
0 = disabled
1 = enabled
SQW_PULSE_GEN_EN
0
R/W
External charge pump clock enable (50% duty cycle 100 kHz).
Clock connected to SQW pin. SQW clock enabled at soft start.
0 = disabled
1 = enabled
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8.6.2.24 EEPROM Register 23
Address 0x77
EEPROM Register 23
7
6
5
4
3
EXT_TEMP_LEVEL_HIGH[3:0]
2
1
0
EXT_TEMP_LEVEL_LOW[3:0]
Name
Bit
Access
Description
EXT_TEMP_LEVEL_HIGH[3:0]
7:4
R/W
High external temperature sensor limit, kΩ
0000 = 79.67
0001 = 43.35
0010 = 29.77
0011 = 22.67
0100 = 18.30
0101 = 15.34
0110 = 13.21
0111 = 11.60
1000 = 10.34
1001 = 9.32
1010 = 8.49
1011 = 7.79
1100 = 7.20
1101 = 6.69
1110 = 6.25
1111 = 5.87
EXT_TEMP_LEVEL_LOW[3:0]
3:0
R/W
Low external temperature sensor limit, kΩ
0000 = 79.67
0001 = 43.35
0010 = 29.77
0011 = 22.67
0100 = 18.30
0101 = 15.34
0110 = 13.21
0111 = 11.60
1000 = 10.34
1001 = 9.32
1010 = 8.49
1011 = 7.79
1100 = 7.20
1101 = 6.69
1110 = 6.25
1111 = 5.87
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8.6.2.25 EEPROM Register 24
Address 0x78
EEPROM Register 24
7
6
5
4
INT_TEMP_LIM[1:0]
84
3
2
1
EXT_TEMP_PERIOD[4:0]
0
EXT_TEMP_COMP_EN
Name
Bit
Access
Description
INT_TEMP_LIM[1:0]
7:6
R/W
Internal temperature sensor brightness thermal de-rating starting
level.
Thermal de-rating function temperature threshold:
00 = thermal de-rating function disabled
01 = 90°C
10 = 100°C
11 = 110°C
EXT_TEMP_PERIOD[4:0]
5:1
R/W
Step time for temperature limitation with external sensor
00000 = 2 s
00001 = 4 s
00010 = 6 s
00011 = 8 s
00100 = 10 s
00101 = 12 s
00110 = 14 s
00111 = 16 s
01000 = 18 s
01001 = 20 s
01010 = 22 s
01011 = 24 s
01100 = 26 s
01101 = 28 s
01110 = 30 s
01111 = 32 s
…
11110 = 62 s
11111 = 64 s
EXT_TEMP_COMP_EN
0
R/W
External temperature sensor (NTC) enable
0 = disabled
1 = enabled
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LP8860-Q1 is designed for automotive applications, and an input voltage VIN is intended to be connected to
the car battery. The device is internally powered from the VDD pin, and voltage must be in 3-V to 5.5-V range.
The device has flexible configurability; outputs configuration are defined by EEPROM settings. If the VDD voltage
is not high enough to drive an external nMOSFET gate, an internal charge pump must be used to power the gate
driver. The charge pump is configured by EEPROM.
The LP8860-Q1 can be used as a stand-alone device, using only the VDDIO/EN pin and the PWM signal.
Alternatively, the device can be a part of system, connected to a microprocessor by an SPI or I2C interface.
NOTE
Maximum operating voltage for VIN is 48 V; the boost converter can achieve output voltage
up to 48 V (typical) without external feedback divider in adaptive voltage control mode.
However, VIN must be below output voltage, and the conversion ratio (max 10) must be
taken into account. If necessary, boost can provide higher output voltage with an external
resistive feedback voltage divider. For high output-voltage applications, outputs must be
protected by external components to prevent overvoltage.
9.2 Typical Applications
9.2.1 Typical Application for Display Backlight
Figure 53 shows the typical application for the LP8860-Q1 with factory-programmed settings. It supports 4 LED
strings in display mode with a 90° phase shift. Brightness control register is used for LED dimming by using
conventional PWM dimming method. VDD voltage is 5 V, charge pump is disabled, and boost switching
frequency is 303 kHz.
VIN
RISENSE
3...40 V
D
L
Q2
CIN
Up to 40 V
COUT
C1P
SD
VSENSE_N
Q1
C1N
GD
VSENSE_P
ISENSE
VDD 5 V
RSENSE
VDD
ISENSE_GND
CPUMP
CVDD
FB
CCPUMP
SQW
FILTER
LP8860-Q1
SYNC
OUT1
VSYNC
SCL
SDA
PWM
OUT2
SCLK/SCL
OUT3
MOSI/SDA
OUT4
MISO
MCU/GPU
FAULT RESET
NSS
EN
TSENSE
VDDIO/EN
ISET
IF
FAULT
FAULT
SGND
PGND LGND
PAD
VDDIO
Copyright © 2016, Texas Instruments Incorporated
Figure 53. VDD = 5 V, I2C, 4 LED Outputs in Display Mode
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Typical Applications (continued)
9.2.1.1 Design Requirements
Table 24. EEPROM Setting Example
ADDRESS (HEX)
DATA (HEX)
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
ED
DF
DC
F0
DF
E5
F2
77
77
71
3F
B7
17
EF
B0
87
CE
72
E5
DF
35
06
DC
FF
3E
DESIGN PARAMETER
VALUE
VIN voltage range
3 V to 40 V
VDD voltage
5V
Charge pump
Disabled
Brightness Control
I2C
Output configuration
Mode 1, OUT1 to OUT4 are in display mode (phase shift 90º)
LED string current
130 mA
External current set resistor
Disabled
Boost frequency
303 kHz
Inductor
22 μH to 33 μH, at least 9-A saturation current
Input/Output capacitors
10 μF ceramic and 33 μF electrolytic
RISENSE
20 mΩ
RSENSE
25 mΩ
Current dimming with external NTC
Disabled
86
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9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Inductor Selection
There are two main considerations when choosing an inductor; the inductor must not saturate, and the inductor
current ripple must be small enough to achieve the desired output voltage ripple. Different saturation current
rating specifications are followed by different manufacturers so attention must be given to details. Saturation
current ratings are typically specified at 25°C. However, ratings at the maximum ambient temperature of
application should be requested from the manufacturer. Shielded inductors radiate less noise and are preferable.
The saturation current must be greater than the sum of the maximum load current and the worst case averageto-peak inductor current. The equation below shows the worst case conditions.
IOUTMAX
+ IRIPPLE For Boost
'¶
(VOUT - VIN) VIN
x
Where IRIPPLE =
(2 x L x f)
VOUT
ISAT >
Where D =
•
•
•
•
•
•
•
•
(VOUT ± VIN)
(VOUT)
DQG '¶ = (1 - D)
IRIPPLE: peak inductor current
IOUTMAX: maximum load current
VIN: minimum input voltage in application
L: min inductor value including worst case tolerances
f: minimum switching frequency
VOUT: output voltage
D: Duty Cycle for CCM Operation
VOUT: Output Voltage
(9)
As a result the inductor must be selected according to the ISAT. A more conservative and recommended
approach is to choose an inductor that has a saturation current rating greater than the maximum switch current
limit defined by EEPROM bits. A 22-µH to 33-µH inductor with a saturation current
rating of at least 9 A is recommended for most applications. The inductor resistance must be less than 300 mΩ
for good efficiency. See detailed information in Texas Instruments Application Note Understanding Boost Power
Stages in Switch Mode Power Supplies (SLVA061). “Power Stage Designer™ Tools” can be used for the boost
calculation: http://www.ti.com/tool/powerstage-designer.
9.2.1.2.2 Output Capacitor Selection
A ceramic capacitor with a 100-V voltage rating is recommended for the output capacitor. The DC-bias effect can
reduce the effective capacitance by up to 80%, a consideration for capacitance value selection. Effectively the
capacitance must be 33 µF for 600-mA loads. A different option is to use an aluminum electrolytic capacitor with
low ESR and ceramic capacitor in parallel. Typically a 33-µF (ESR < 500 mΩ) with 10-µF (effective) ceramic
capacitor in parallel is sufficient. If ESR is lower, capacitance for ceramic capacitor can be decreased.
For higher switching frequency (2.2 MHz) and boost output current below 400 mA, two 10-µF ceramic capacitors
in parallel are sufficient.
9.2.1.2.3 Input Capacitor Selection
A ceramic capacitor with 50-V voltage rating is recommended for the input capacitor. The DC-bias effect can
reduce the effective capacitance by up to 80%, a consideration for capacitance value selection. Effectively the
capacitance must be 33 µF for 600-mA loads. A different option is to use an aluminum electrolytic capacitor with
low ESR and ceramic capacitor in parallel. Typically a 33-µF (ESR < 500 mΩ) with 10-µF (effective) ceramic
capacitor in parallel is sufficient. If ESR is lower, capacitance for ceramic capacitor can be decreased.
For higher switching frequency (2.2 MHz) and boost output current below 400 mA two 10-µF ceramic capacitors
in parallel are sufficient.
9.2.1.2.4 Charge Pump Output Capacitor
A ceramic capacitor with at least 16-V voltage rating is recommended for the output capacitor of the charge
pump. The DC-bias effect can reduce the effective capacitance by up to 80%, which needs to be considered in
capacitance value selection. Typically a 10-µF capacitor is sufficient.
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9.2.1.2.5 Charge Pump Flying Capacitor
A ceramic capacitor with at least 10-V voltage rating is recommended for the flying capacitor of the charge pump.
Typically 1-µF capacitor is sufficient.
9.2.1.2.6 Diode
A Schottky diode must be used for the boost output diode. Peak repetitive current must be greater than inductor
peak current (up to 9 A) to ensure reliable operation. Average current rating must be greater than the maximum
output current. Schottky diodes with a low forward drop and fast switching speeds are ideal for increasing
efficiency. Choose a reverse breakdown voltage of the Schottky diode significantly larger than the output voltage.
Do not use ordinary rectifier diodes because slow switching speeds and long recovery times cause the efficiency
and the load regulation to suffer.
9.2.1.2.7 Boost Converter Transistor
An nFET transistor with high enough voltage rating (VDS at least 5 V higher than maximum output voltage) must
be used. Current rating for the FET must be the same as the inductor peak current. Gate-drive voltage for the
FET is VDD or about 2 x VDD, if the charge pump is enabled (EEPROM selection).
9.2.1.2.8 Boost Sense Resistor
A high-power 25-mΩ resistor must be used for sensing the boost SW current. Power rating can be calculated
from the inductor current and sense resistor resistance value.
9.2.1.2.9 Power Line Transistor
A pFET transistor with necessary voltage rating (VDS at least 5 V higher than max input voltage) must be used.
Current rating for the FET must be the same as input peak current or greater. Transfer characteristic is very
important for pFET. VGS for open transistor must be less then VIN. A 20-kΩ resistor between the pFET gate and
source is sufficient.
If a pFET with high enough VDS and low VGS is not available, it is possible to use an nFET with extra external
components with the EEPROM bit NMOS_PLFET_EN set high. See Charge Pump section (Figure 25) for using
the nFET as a power-line FET.
9.2.1.2.10 Input Current Sense Resistor
A high-power 20-mΩ resistor must be used for sensing the boost input current. Power rating can be calculated
from the input current and sense resistor resistance value.
9.2.1.2.11 Filter Component Values
Table 25 shows recommended filter component values for the VSYNC PLL filter (phase margin 60°). An external
filter must be used only when external VSYNC is used; otherwise, the LP8860-Q1 uses internal compensation.
C1
FILTER
C2
R1
Figure 54. Filter Components
88
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Table 25. Filter Components Selection
V/H SYNC
PLL FREQUENCY (MHz)
C1
C2
R1
50 Hz
(BW3dB = 1 Hz)
5
100 nF
1.4 μF
85 kΩ
10
54 nF
0.7 μF
170 kΩ
20
27 nF
0.35 μF
338 kΩ
40
13.6 nF
0.175 μF
677 kΩ
5
10 nF
129 nF
14 kΩ
10
5 nF
65 nF
28 kΩ
20
2.5 nF
32 nF
56 kΩ
40
1.2 nF
16 nF
112 kΩ
20 kHz
(BW3dB = 330 Hz)
50 kHz
(BW3dB = 330 Hz)
5
22 nF
322 nF
5.6 kΩ
10
12 nF
161 nF
11.2 kΩ
20
6.2 nF
80 nF
22.3 kΩ
40
3.1 nF
40 nF
44,7 kΩ
9.2.1.2.11.1 Critical Components for Design
Schematic on Figure 55 shows the critical part of circuitry: boost components, the LP8860-Q1 internal charge
pump for gate driver powering and powering/grounding of LP8860-Q1 boost components. Layout example for
this is shown in Figure 67.
R1
+VBATT
D1
L1
Q1
C3
C5
C4
C8
1
R2
32
5
6
VDD 3.3V
3
31
C1
2
C1P
SD
VSENSE_N
GD
VSENSE_P
ISENSE
ISENSE_GND
FB
SQW
12
R3
28
R4
C2
9
30
VDD
CPUMP
C9
Q2
C1N
27
C6
R5
26
4
C7
FILTER
LP8860-Q1
SYNC
OUT1
25
13
VSYNC
18
PWM
OUT2
16
SCLK/SCL
OUT3
22
15
MOSI/SDA
MISO
OUT4
21
14
17
NSS
19
VDDIO/EN
TSENSE
ISET
20
IF
11
FAULT
SGND
10
PGND LGND
29
to LEDs
24
to LEDs
8
7
PAD
23
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Figure 55. Critical Components for Design
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Table 26. Bill of Materials for Design Example
REFERENCE DESIGNATOR
90
DESCRIPTION
NOTE
R1
20 mΩ 3 W
Input current sensing resistor
R2
20 kΩ 0.1 W
Power-line FET gate pullup resistor
R3
10 Ω 0.1 W
Gate resistor for boost FET
R4
10 Ω 0.1 W
Current sensing filter resistor
R5
25 mΩ 3 W
Boost current sensing resistor
C1
1 μF 10 V ceramic capacitor
VDD bypass capacitor
C2
10 μF 16 V ceramic capacitor
Charge pump output capacitor
C3
33 μF 50 V electrolytic capacitor
Boost input capacitor
C4
10 μF 50 V ceramic capacitor
Boost input capacitor
C5
1 μF 10 V ceramic capacitor
Flying capacitor
C6
1000 pF 10 V ceramic capacitor
Current sensing filter capacitor
C7
39 pF 50 V ceramic capacitor
High frequency bypass capacitor
C8
33 μF 50 V electrolytic capacitor
Boost output capacitor
C9
10 μF 100 V ceramic capacitor
Boost output capacitor
L1
22 μH saturation current 9 A
Boost inductor
D1
60 V 15 A Schottky diode
Boost Schottky diode
Q1
60 V 10 A pMOSFET
Power-line FET
Q2
60 V 15 A nMOSFET
Boost nMOSFET
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9.2.1.3 Application Performance Plots
VDDIO/EN 5V/div
10V/div
VD POWER-LINE pFET 10V/div
VBOOST 10 V/DIV
LED OUT 10 V/DIV
20ms/div
40—s/div
fLED_PWM = 4.9 kHz
Phase shift 90º
4 strings
ƒSW = 303 kHz
CIN = COUT= 33 µF(el) + 10 µF(cer)
130 mA/string
Figure 57. Typical Start-up
Figure 56. Voltage of LED Outputs Showing Phase-Shift
PWM Operation
BOOST CURRENT
100mA/DIV
BOOST CURRENT
100mA/DIV
BOOST VOLTAGE
1V/DIV
BOOST VOLTAGE
1V/DIV
OUT1 5V/DIV
OUT1 5V/DIV
40ms/DIV
40ms/DIV
PWM_SLOPE =
110
130 mA/string
Phase Shift = 90°
4 strings
10 LED/string
EN_ADVANCED_SLOPE = 0
Figure 58. Slope with Phase-Shift Mode
EN_PWM_I = 1
PWM_SLOPE = 101
I_SLOPE =000
GAIN_CTRL =
111
EN_ADVANCED_SLOPE = 0
130 mA/string
4 strings
Phase Shift = 90°
Figure 59. Slope With Hybrid Dimming and Phase Shift
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9.2.2 Low VDD Voltage and Combined Output Mode Application
Figure 60 shows the application for LED strings in Display mode (OUT1 and OUT2) and Cluster mode (OUT3
and OUT4). External powering must be used for Cluster-mode LED strings. VDD voltage is 3.3 V, and the charge
pump for gate driver powering is enabled.
VIN
RISENSE
3...40 V
D
L
Q2
Up to 40 V
C2x
CIN
COUT
C1P
SD
VSENSE_N
Q1
C1N
GD
VSENSE_P
ISENSE
VDD 3.3 V
RSENSE
VDD
ISENSE_GND
FB
CCPUMP
Display Group
CVDD
SQW
FILTER
LP8860-Q1
SYNC
OUT1
OUT2
VSYNC
SCLK
MCU/GPU
SCLK/SCL
MOSI
MOSI/SDA
MISO
MISO
NSS
Cluster Group
PWM
OUT3
OUT4
NSS
EN
VDDIO/EN
TSENSE
External
Powering
ISET
IF
VDDIO
FAULT
FAULT
SGND
PGND LGND
PAD
VDDIO
Copyright © 2016, Texas Instruments Incorporated
Figure 60. VDD = 3.3V, SPI, 2 Outputs in Display Mode,
2 in Cluster Mode Schematic
9.2.2.1 Design Requirements
Table 27. EEPROM Setting Example
92
ADDRESS (HEX)
DATA (HEX)
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
ED
DF
DC
F4
DF
E5
F2
77
77
71
3F
B7
17
EF
B0
87
CF
72
E5
DF
35
06
DE
FF
3E
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DESIGN PARAMETER
VALUE
VIN voltage range
3 V to 40 V
VDD voltage
3.3 V
Charge pump
Enabled
Brightness Control
SPI
Output configuration
Mode 2, OUT1 and OUT2 - display mode (phase shift 180º), OUT3 and OUT4 - cluster mode
LED string current
OUT1 and OUT2 - 130 mA; OUT3 - 30 mA; OUT4 - 33 mA
External current set resistor
Disabled
Boost frequency
303 kHz
Inductor
22 μH to 33 μH, at least 5-A saturation current
Input/Output capacitors
10 μF ceramic and 33 μF electrolytic
Current dimming with external NTC
Disabled
9.2.2.2 Detailed Design Procedure
See Detailed Design Procedure.
9.2.2.3 Application Performance Plots
See Application Performance Plots.
9.2.3 High Output Voltage Application
The LP8860-Q1 has ability to control up to 16 or 17 LEDs per string with additional external components for
output overvoltage protection. nFET transistors can protect outputs, and SQW output can be used to produce
extra rail voltage for the transistor gates, if necessary voltage is not available in the system.
VIN
8...48 V
RISENSE
Up to 60 V
L1
Q2
CIN
D1
Q1
C1P
C1N
SD
VSENSE_N
ISENSE
VSENSE_P
VDD 5 V
RSENSE
R2DIV
ISENSE_GND
VDD
CVDD
COUT
R1DIV
GD
FB
CPUMP
CCPUMP
SQW
VDD 5 V
FILTER
LP8860-Q1
SYNC
50 kHz
VSYNC
OUT1
OUT2
PWM
SCL
SCLK/SCL
SDA
OUT3
MOSI/SDA
MISO
MCU/GPU
OUT4
NSS
Protection
FETs
VDDIO/EN
10 V
IF
FAULT
SGND
TSENSE
PGND LGND
ISET
PAD
VDDIO
Copyright © 2016, Texas Instruments Incorporated
2
Figure 61. VDD = 5 V, I C, High-Voltage Output with Output Protection FETs Circuits
9.2.3.1 Design Requirements
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Table 28. EEPROM Setting Example
ADDRESS (HEX)
DATA (HEX)
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
ED
DF
DC
F4
DF
E5
F2
77
77
71
3F
B7
17
EF
B0
87
CF
72
E5
DF
35
06
DE
FF
3E
DESIGN PARAMETER
VALUE
VIN voltage range
3 V to 48 V
VDD voltage
5V
Charge pump
Disabled
Brightness Control
I2C
Output configuration
Mode 0, all outputs are in display mode, phase shift 90º, synchronized with VSYNC 50kHz,
10 LEDs per string, ƒLED_PWM= 10 kHz
LED string current
OUT1 to OUT4 - 120 mA
External current set resistor
Disabled
Boost frequency
303 kHz
Inductor
22 μH to 33 μH, at least 9-A saturation current
Input/Output capacitors
10 μF ceramic and 33 μF electrolytic
Current dimming with external NTC
Disabled
VSYNC
Enabled, 50 kHz
Feedback voltage divider
R1DIV = 30 kΩ, R2DIV = 150 kΩ
9.2.3.2 Detailed Design Procedure
See Detailed Design Procedure.
9.2.3.3 Application Performance Plots
See Application Performance Plots.
9.2.4 High Output Current Application
The LP8860-Q1 outputs can be tied together to drive LED with higher current. To drive a 300 mA/string, connect
2 outputs together. All 4 outputs connected together can drive up to a 600-mA LED string.
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VIN
RISENSE
3...40V
D
L
Q2
Up to 40V
C2x
CIN
COUT
C1P
SD
VSENSE_N
Q1
C1N
GD
VSENSE_P
ISENSE
VDD 3.3V
RSENSE
VDD
ISENSE_GND
CPUMP
FB
SQW
FILTER
Up to 300mA/string
BOOST SYNC 300 kHz
LP8860-Q1
SYNC
OUT1
VSYNC
SCLK
MOSI
OUT2
OUT3
MOSI/SDA
MISO
MCU/GPU
PWM
SCLK/SCL
MISO
NSS
OUT4
NSS
EN
VDDIO/EN
VDDIO
FAULT
FAULT
SGND
TSENSE
ISET
IF
PGND LGND
PAD
VDDIO
Copyright © 2016, Texas Instruments Incorporated
Figure 62. Two Channels at 300 mA/String, VDD = 3.3 V, SPI
9.2.4.1 Design Requirements
Table 29. EEPROM Setting Example
ADDRESS (HEX)
DATA (HEX)
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
EF
FF
DC
F8
DF
E5
F2
77
77
71
3F
B7
17
EF
B1
87
DF
72
E5
DF
35
06
DE
FF
3E
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DESIGN PARAMETER
VALUE
VIN voltage range
3 V to 40 V
VDD voltage
3.3 V
Charge pump
Enabled
Brightness Control
SPI
Output configuration
Mode 4, OUT1 to OUT4 in display mode, phase shift between tied groups 180º
LED string current
OUT1 and OUT2 - 300 mA; OUT3 and OUT4 - 300 mA
External current set resistor
Disabled
Boost frequency
300 kHz externally synchronized
Inductor
22 μH to 33 μH, at least 9-A saturation current
Input/Output capacitors
10-μF ceramic and 33-μF electrolytic
Current dimming with external NTC
Disabled
9.2.4.2 Detailed Design Procedure
See Detailed Design Procedure.
9.2.4.3 Application Performance Plots
See Application Performance Plots.
9.2.5 Three-Channel Configuration Without Serial Interface
Outputs which are not used can be left floating. In this example 3 outputs are in use. PSPWM mode for 3 outputs
is set to mode 1 = 001b, and the serial interface is not used. The device is enabled
with the EN/VDDIO pin, and brightness control is set with the PWM input. EEPROM settings must be preprogrammed for brightness dimming with external PWM.
LED current dimming with external NTC sensor is used in this application to protect LEDs against over-heating.
VIN
RISENSE
3...40 V
D
L
Q2
CIN
Up to 40 V
COUT
C1P
SD
VSENSE_N
Q1
C1N
GD
VSENSE_P
ISENSE
VDD 5 V
RSENSE
VDD
ISENSE_GND
CPUMP
FB
SQW
FILTER
Up to 150 mA/string
LP8860-Q1
SYNC
OUT1
VSYNC
BRIGHTNESS
PWM
OUT2
SCLK/SCL
OUT3
MOSI/SDA
MISO
FAULT RESET
OUT4
RT1
NSS
EN
VDDIO/EN
FAULT
SGND
RT°
ISET
IF
FAULT
TSENSE
RT2
PGND LGND
NTC
PAD
RISET
VDDIO
Copyright © 2016, Texas Instruments Incorporated
Figure 63. Three-Channel Configuration without Serial Interface
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9.2.5.1 Design Requirements
Table 30. EEPROM Setting Example
ADDRESS (HEX)
DATA (HEX)
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
6F
FF
DC
F2
DF
E5
F8
77
77
E1
BF
B7
17
EF
B1
87
CE
72
E5
DF
35
06
DC
CF
3F
DESIGN PARAMETER
VALUE
VIN voltage range
3 V to 40 V
VDD voltage
5V
Charge pump
Disabled
Brightness Control
PWM
Output configuration
Mode 1, OUT1 to OUT3 - display mode; OUT4 - not used
LED string current
OUT1 to OUT3 - 150 mA
External current set resistor
Enabled, RISET = 24 kΩ
Boost frequency
303 kHz
Inductor
22 μH to 33 μH, at least 6-A saturation current
Input/Output capacitors
10-μF ceramic and 33 μF electrolytic
Current dimming with external NTC
Enabled,RT°= NCP15XH103F03RC (Murata), see Figure 64, RT1 = 6.6 kΩ, RT2 not
assembled
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9.2.5.2 Detailed Design Procedure
4.0
100
3.5
90
80
3.0
LED current (%)
NTC Resistance (k )
LED current dimming with external NTC sensor is used in this application — see section LED Current Dimming
With External NTC Sensor for details. Figure 65 shows LED current de-rating versus temperature measured by
NTC sensor with characteristic shown in Figure 64.
2.5
2.0
1.5
1.0
70
60
50
40
30
EXT_TEMP_MINUS[1:0]=01b
EXT_TEMP_GAIN[3:0]=1110b
EXT_TEMP_LEVEL_HIGH[3:0]=1100b
20
0.5
10
0
0.0
40
50
60
70
80
90
100
110
Temperature (ž&
40
120
50
60
70
80
90
100
110
Temperature (ž&
C009
120
C008
Figure 65. LED Current De-rating vs Temperature
Figure 64. NTC Sensor Resistance vs Temperature
9.2.5.3 Application Performance Plots
See Application Performance Plots.
9.2.6 Solution With Minimum External Components
The LP8880-Q1 needs only a few external components for basic functionality if material cost and PCB area for a
LP8860-Q1-based solution need to be minimized. In this example the power-line FET is removed, as is input
current sensing. External synchronization functions are disabled.
VIN
3...40 V
L1
Up to 40 V
COUT
D
CIN
Q
C1P
C1N
GD
SD
VSENSE_N
ISENSE
VSENSE_P
VDD 5 V
RSENSE
ISENSE_GND
VDD
FB
CPUMP
SQW
FILTER
LP8860-Q1
SYNC
VSYNC
BRIGHTNESS
OUT1
OUT2
PWM
OUT3
SCLK/SCL
OUT4
MOSI/SDA
MISO
FAULT RESET
ENABLE
FAULT
TSENSE
NSS
VDDIO/EN
ISET
IF
FAULT
SGND
PGND LGND
PAD
VDDIO
Copyright © 2016, Texas Instruments Incorporated
Figure 66. Solution With Minimum External Components
98
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9.2.6.1 Design Requirements
Table 31. EEPROM Setting Example
ADDRESS (HEX)
DATA (HEX)
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
EF
FF
DC
D0
DF
E5
F0
77
77
71
3F
B7
17
EF
B0
87
CE
07
E5
DF
75
86
DC
FF
3E
DESIGN PARAMETER
VALUE
VIN voltage range
3 V to 40 V
VDD voltage
5V
Charge pump
Disabled
Brightness Control
PWM
Output configuration
Mode0, OUT1 to OUT4 in display mode, phase shift 90º
LED string current
OUT1 to OUT4 - 100 mA
External current set resistor
Disabled
Boost frequency
2.2 MHz
Inductor
4.7 µH to 22 µH, at least 6-A saturation current
Input/Output capacitors
2 × 10-μF ceramic
Current dimming with external NTC
Disabled
10 Power Supply Recommendations
The LP8860-Q1 is designed to operate from a car battery. VIN input must be protected from reversal voltage and
voltage dump over 48 Volts. The impedance of the input supply rail must be low enough that the input current
transient does not cause drop below VIN UVLO level. If the input supply is connected by using long wires,
additional bulk capacitance may be required in addition to normal input capacitor .
The voltage range for VDD is 3 V to 5.5 V. A ceramic capacitor must be placed as close as possible to the VDD
pin. The boost gate driver is powered from the VDD pin; this must be taken into account. For high boost
frequency and high internal PLL frequency (can be up to 40 MHz), power consumption from VDD pin can be
around 20 mA to 40 mA.
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11 Layout
11.1 Layout Guidelines
Figure 67 shows a layout recommendation for the LP8860-Q1. Figure 67 is used to show the principles of good
layout. This layout can be adapted to the actual application layout if and where possible. It is important that all
boost components are close to each other and to the device; the high-current traces must be wide enough. VDD
must be as noise-free as possible. Place a VDD bypass capacitor near the pin and ground it to a noise-free
ground. A charge-pump capacitor and boost input and output capacitors must be connected to PGND. Here are
some main points to help the PCB layout work:
• Current loops need to be minimized:
– For low frequency the minimal current loop can be achieved by placing the boost components as close to
each other as possible. Input and output capacitor grounds need to be close to each other to minimize
current loop size.
– Minimal current loops for high frequencies can be achieved by making sure that the ground plane is intact
under the current traces. High frequency return currents try to find route with minimum impedance, which
is the route with minimum loop area, not necessarily the shortest path. Minimum loop area is formed when
return current flows just under the positive current route in the ground plane, if the ground plane is intact
under the route.
– For high frequency the copper area capacitance must be taken into account. For example, the copper
area for the drain of boost nMOSFET is a tradeoff between capacitance and components cooling capacity.
• GND plane must be intact under the high current boost traces to provide shortest possible return path and
smallest possible current loops for high frequencies.
• Current loops when the boost switch is conducting and not conducting must be in the same direction in
optimal case.
• Inductors must be placed so that the current flows in the same direction as in the current loops. Rotating the
inductor 180° changes current direction.
• Use separate power and noise-free grounds. The power ground is used for boost converter return current and
noise-free ground for more sensitive signals, like VDD bypass capacitor grounding as well as grounding the
GND pins of the LP8860-Q1 itself.
• Boost output feedback voltage to LEDs need to be taken out after the output capacitors, not straight from the
diode cathode.
• A small (for example, 39-pF) bypass capacitor must be placed close to the FB pin to suppress high frequency
noise
• VDD line must be separated from the high current supply path to the boost converter to prevent high
frequency ripple affecting the chip behavior. A separate 1-µF bypass capacitor is used for the VDD pin, and it
is grounded to noise-free ground.
• Capacitor connected to charge pump output CPUMP must have 10-µF capacitance, grounded by shortest
way to boost switch current sensing resistor. This capacitor must be as close as possible to CPUMP pin. This
capacitor provides a greater peak current for gate driver and must be used even if the charge pump is
disabled. If the charge pump is disabled, the VDD and CPUMP pins must be tied together.
• Input and output capacitors need strong grounding (wide traces, many vias to PGND plane).
• If two or more output capacitors are used, symmetrical layout must be used to get all capacitors working
ideally.
• Input/output ceramic capacitors have DC-bias effect. If the output capacitance is too low, it can cause boost
to become unstable on some loads. DC bias characteristics need to be obtained from the component
manufacturer; it is not taken into account on component tolerance. TI recommends X5R/X7R capacitors.
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11.2 Layout Example
BATTERY
+VBATT -VBATT
R1
R2
Input capacitors
Q1
L1
C3
C4
D1
C8
Output capacitors
C9
3
VDD
OUT1 25
24
OUT2
LGND 23
8
17
NSS
FILTER
16
TSENSE
SCLK/SCL
PWM
15
18
MOSI/SDA
7
14
19 VDDIO/EN
ISET
13
VSENSE_P
MISO
IF
6
VSYNC
20
12
5
11
OUT4
VSENSE_N
SYNC
21
FAULT
OUT3
4
10 SGND
22
SQW
9
VDD
FB 26
ISENSE 28
GD 30
PGND 29
C1
ISENSE_GND 27
C1N
CPUMP 31
SD 32
C1P
C7
C6
C2
2
Ground wire for
current sensor
R4
R3
1
Connection
between PGND
and GND
R5
Q2
C5
Feedback line
VIA to GND plane
Figure 67. LP8860-Q1 Layout
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• PowerPAD™ Thermally Enhanced Package Application Note
• Understanding Boost Power Stages in Switch Mode Power Supplies
• Power Stage Designer™ Tools
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
PowerPAD is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
102
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LP8860AQVFPRQ1
ACTIVE
HLQFP
VFP
32
1000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LP8860AQ1
LP8860BQVFPRQ1
ACTIVE
HLQFP
VFP
32
1000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LP8860BQ1
LP8860CQVFPRQ1
ACTIVE
HLQFP
VFP
32
1000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LP8860CQ1
LP8860DQVFPRQ1
ACTIVE
HLQFP
VFP
32
1000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LP8860DQ1
LP8860HQVFPRQ1
ACTIVE
HLQFP
VFP
32
1000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LP8860HQ1
LP8860JQVFPRQ1
ACTIVE
HLQFP
VFP
32
1000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LP8860JQ1
LP8860LQVFPRQ1
ACTIVE
HLQFP
VFP
32
1000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LP8860LQ1
LP8860NQVFPRQ1
ACTIVE
HLQFP
VFP
32
1000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LP8860NQ1
LP8860RQVFPRQ1
ACTIVE
HLQFP
VFP
32
1000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LP8860RQ1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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