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LP8862-Q1
SNVSA75D – NOVEMBER 2015 – REVISED MAY 2017
LP8862-Q1 Low-EMI Automotive LED Driver With Two 160-mA Channels
1 Features
3 Description
•
•
The LP8862-Q1 is an automotive high-efficiency, lowEMI, easy-to-use LED driver with integrated DC-DC
converter. The DC-DC supports both boost and
SEPIC modes of operation. The device has two highprecision current sinks that can provide high dimming
ratio brightness control with a PWM input signal.
1
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Input Voltage Operating Range 4.5 V to 40 V
Two High-Precision Current Sinks
– Current Matching 1% (Typical)
– LED String Current up to 160 mA per Channel
– Dimming Ratio of 10 000:1 at 100 Hz
Integrated Boost/SEPIC Converter for LED String
Power
– Output Voltage up to 45 V
– Switching Frequency 300 kHz to 2.2 MHz
– Switching Synchronization Input
– Spread Spectrum for Lower EMI
Power-Line FET Control for Inrush Current
Protection and Standby Energy Saving
Extensive Fault Detection Features
– Fault Output
– Input Voltage OVP, UVLO, and OCP
– Open and Shorted LED Fault Detection
– Thermal Shutdown
Minimum Number of External Components
The boost/SEPIC converter has an adaptive output
voltage control based on the LED current sink
headroom voltages. This feature minimizes power
consumption by adjusting the voltage to the lowest
sufficient level in all conditions. DC-DC supports
spread spectrum for switching frequency and an
external synchronization with a dedicated pin. A widerange adjustable frequency allows the LP8862-Q1 to
avoid disturbance for AM radio band.
The input voltage range for the LP8862-Q1 is from
4.5 V to 40 V to support automotive stop/start and
load dump conditions. The device supports PWM
brightness dimming ratio of 10 000:1 for 100-Hz input
PWM frequency. The LP8862-Q1 integrates
extensive fault detection features. The device has an
option to drive an external p-FET to disconnect the
input supply from the system in the event of a fault.
This feature also reduces inrush current and standby
power consumption.
Device Information(1)
PART NUMBER
PACKAGE
LP8862-Q1
2 Applications
•
BODY SIZE (NOM)
HTSSOP (20)
6.50 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Backlight for:
– Automotive Infotainment
– Automotive Instrument Clusters
– Smart Mirrors
– Heads-Up Displays (HUD)
– Central Information Displays (CID)
– Audio-Video Navigation (AVN)
Simplified Schematic
VIN
RISENSE
4.5...40 V
L1
Q1
D1
CIN BOOST
VOUT up to 45 V
COUT
RGS
R2
SW
SD
VSENSE_N
FB
CFB
VIN
CIN
System Efficiency
CLDO
RFSET
LP8862-Q1
OUT1
FSET
OUT2
90
System Efficiency (%)
Up to 160 mA/string
LDO
95
R1
SYNC
85
BRIGHTNESS
80
EN
PWM
VDDIO/EN
FAULT
75
FAULT
ISET
70
PGND
GND
PAD
RISET
VDDIO
65
VIN=5V
VIN=8V
VIN=12V
VIN=16V
60
55
Copyright © 2016, Texas Instruments Incorporated
50
0
10
20
30
40
50
60
Brightness (%)
70
80
90
100
D001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP8862-Q1
SNVSA75D – NOVEMBER 2015 – REVISED MAY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
8
1
1
1
2
3
4
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
Electrical Characteristics .......................................... 7
Internal LDO Electrical Characteristics ..................... 7
Protection Electrical Characteristics ......................... 7
Power Line FET Control Electrical Characteristics ... 8
Current Sinks Electrical Characteristics.................... 8
PWM Brightness Control Electrical Characteristics 8
Boost or SEPIC Converter Characteristics ............. 8
Logic Interface Characteristics................................ 9
Typical Characteristics .......................................... 10
Detailed Description ............................................ 11
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
12
13
20
Application and Implementation ........................ 22
9.1 Application Information............................................ 22
9.2 Typical Applications ................................................ 22
10 Power Supply Recommendations ..................... 28
11 Layout................................................................... 29
11.1 Layout Guidelines ................................................. 29
11.2 Layout Example .................................................... 30
12 Device and Documentation Support ................. 31
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Third-Party Products Disclaimer ...........................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
31
31
31
31
31
31
31
13 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (April 2017) to Revision D
Page
•
Enhanced descriptions for pins 3, 10, and 16 in Pin Functions table .................................................................................... 5
•
Deleted last line of Brightness Control subsection ............................................................................................................... 15
Changes from Revision B (July 2016) to Revision C
Page
•
Deleted "IOUT = 100 mA" from tON/OFF row of Table 7.10 ........................................................................................................ 8
•
Changed "0.5" from MAX to TYP column in tON/OFF row of Table 7.10 ................................................................................. 8
•
Added table note 1 for Tables 7.10 and 7.11 ......................................................................................................................... 8
•
Deleted "Initial DC-DC voltage is about 88% of VMAX BOOST." from Integrated DC-DC Converter. ....................................... 13
•
Changed Equation 1; add "K" eq definitions for Equation 1 and paragraph after Figure 7 ................................................. 13
•
Added new paragraph before Internal LDO; changed Equation 3 ....................................................................................... 15
•
Changed "less then" to "less than" - correction of typo........................................................................................................ 24
2
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SNVSA75D – NOVEMBER 2015 – REVISED MAY 2017
Changes from Revision A (November 2015) to Revision B
Page
•
Changed "Output Current" to "LED String Current" .............................................................................................................. 1
•
Changed "Dimming Ratio of 10 000:1 at 200 Hz" to "Dimming Ratio of 10 000:1 at 100 Hz" .............................................. 1
•
Deleted some bullets from Features ..................................................................................................................................... 1
•
Added some bullets to Features and minor revisions to wording........................................................................................... 1
•
Added several new Applications ............................................................................................................................................ 1
•
Changed "The high switching frequency" to "A wide-range adjustable frequency" .............................................................. 1
•
Added table ........................................................................................................................................................................... 1
•
Added Device Comparison table ........................................................................................................................................... 3
Changes from Original (November 2015) to Revision A
•
Page
Changed device from product preview to production data .................................................................................................... 1
5 Device Comparison Table
VIN range
Number of LED channels
LED current / channel
LP8860-Q1
LP8862-Q1
LP8861-Q1
TPS61193-Q1
TPS61194-Q1
TPS61196-Q1
3 V to 48 V
4.5 V to 45 V
4.5 V to 45 V
4.5 V to 45 V
4.5 V to 45 V
8 V to 30 V
4
2
4
3
4
6
150 mA
160 mA
100 mA
100 mA
100 mA
200 mA
I2C/SPI support
Yes
No
No
No
No
No
SEPIC support
No
Yes
Yes
Yes
Yes
No
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SNVSA75D – NOVEMBER 2015 – REVISED MAY 2017
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6 Pin Configuration and Functions
PWP Package
20-Pin TSSOP
Top View
VIN
1
20
VSENSE_N
LDO
2
19
SD
FSET
3
18
SW
VDDIO/EN
4
17
PGND
FAULT
5
16
FB
SYNC
6
15
OUT1
PWM
7
14
OUT2
NC
8
13
NC
GND
9
12
NC
ISET
10
11
GND
EP*
*EXPOSED PAD
4
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Pin Functions
PIN
NUMBER
NAME
1
VIN
2
LDO
3
FSET
4
TYPE (1)
DESCRIPTION
A
Input power pin as well as the positive input for an optional current sense resistor.
A
Output of internal LDO; connect a 1-μF decoupling capacitor between this pin and
noise-free ground.
A
DC-DC (boost or SEPIC) switching-frequency-setting resistor; for normal operation,
resistor value from 24 kΩ to 219 kΩ must be connected between this pin and ground.
VDDIO/EN
I
Enable input for the device as well as supply input (VDDIO) for digital pins
5
FAULT
OD
6
SYNC
7
PWM
8
NC
9
GND
10
ISET
11
12
Fault signal output. If unused, this pin may be left floating.
I
Input for synchronizing boost.
If synchronization is not used, connect this pin to GND to disable spread spectrum or
to VDDIO/EN to enable spread spectrum.
I
PWM dimming input.
No internal connection
G
Ground.
A
LED current setting resistor; for normal operation, resistor value from 24 kΩ to 129 kΩ
must be connected between this pin and ground.
GND
G
Ground.
NC
—
No internal connection
13
NC
—
No internal connection
14
OUT2
A
Current sink output.
This pin must be connected to GND if not used.
15
OUT1
A
Current sink output.
This pin must be connected to GND if not used.
16
FB
A
DC-DC (boost or SEPIC) feedback input; for normal operation this pin must be
connected to the middle of a resistor divider between VOUT and ground using
feedback resistor values from 5 kΩ to 150 kΩ.
17
PGND
G
DC-DC (boost or SEPIC) power ground.
18
SW
A
DC-DC (boost or SEPIC) switch pin.
19
SD
A
Power-line FET control.
20
VSENSE_N
A
Input current sense pin.
(1)
A: Analog pin, G: Ground pin, P: Power pin, I: Input pin, I/O: Input/Output pin, O: Output pin, OD: Open Drain pin
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1) (2)
Voltage on pins
MIN
MAX
VIN, VSENSE_N, SD, SW, FB
–0.3
50
OUT1, OUT2
–0.3
45
LDO, SYNC, FSET, ISET, PWM, VDDIO/EN, FAULT
–0.3
5.5
Continuous power dissipation (3)
UNIT
V
Internally Limited
(4)
–40
125
ºC
Junction temperature range TJ (4)
–40
150
ºC
See (5)
ºC
150
°C
Ambient temperature range TA
Maximum lead temperature (soldering)
Storage temperature, Tstg
(1)
(2)
(3)
(4)
(5)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to the potential at the GND pins.
Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 165°C (typical) and
disengages at TJ = 145°C (typical).
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =
150°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the
part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX ).
For detailed soldering specifications and information, please refer to the PowerPAD™ Thermally Enhanced Package Application Note
(SLMA002).
7.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic discharge
Charged-device model (CDM), per AEC
Q100-011
UNIT
±2000
Corner pins (1, 10, 11,
20)
±750
Other pins
±500
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted) (1)
VIN
Voltage on pins
(1)
6
MIN
MAX
4.5
45
VSENSE_N, SD, SW
0
45
OUT1, OUT2
0
40
FB, FSET, LDO, ISET, VDDIO/EN, FAULT
0
5.25
SYNC, PWM
0
VDDIO/EN
UNIT
V
All voltages are with respect to the potential at the GND pins.
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7.4 Thermal Information
LP8862-Q1
THERMAL METRIC (1)
PWP (TSSOP)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance (2)
44.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
26.5
°C/W
RθJB
Junction-to-board thermal resistance
22.4
°C/W
ψJT
Junction-to-top characterization parameter
0.9
°C/W
ψJB
Junction-to-board characterization parameter
22.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.5
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
7.5 Electrical Characteristics
TJ = −40°C to 125°C (unless otherwise noted) (1) (2).
PARAMETER
TEST CONDITIONS
Standby supply current
Device disabled, VVDDIO/EN = 0 V,
VIN = 12 V
Active supply current
VIN = 12 V, VOUT = 26 V, output
current 160 mA/channel, converter
ƒSW = 300 kHz
Power-on reset rising threshold
LDO pin voltage. Output of the
internal LDO or an external supply
input (VDD).
VPOR_F
Power-on reset falling threshold
LDO pin voltage. Output of the
internal LDO or an external supply
input (VDD).
TTSD
Thermal shutdown threshold
TTSD_HYST
Thermal shutdown hysteresis
IQ
VPOR_R
(1)
(2)
MIN
TYP
MAX
UNIT
4.5
20
μA
5
12
mA
2.7
V
1.5
150
165
175
°C
20
All voltages are with respect to the potential at the GND pins.
Min and Max limits are specified by design, test, or statistical analysis.
7.6 Internal LDO Electrical Characteristics
TJ = −40°C to 125°C (unless otherwise noted).
PARAMETER
VLDO
Output voltage
VDR
Dropout voltage
ISHORT
Short circuit current
TEST CONDITIONS
VIN = 12 V
MIN
TYP
MAX
UNIT
4.15
4.3
4.45
V
120
220
430
mV
50
mA
7.7 Protection Electrical Characteristics
TJ = −40°C to 125°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
41
42
44
UNIT
V
2.7
3.2
3.7
A
VOVP
VIN OVP threshold voltage
IOCP
VIN OCP current
VUVLO
VIN UVLO
4.0
V
VUVLO_HYS
VIN UVLO hysteresis
100
mV
RSENSE = 50 mΩ
T
LED short detection threshold
5.6
6
7
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7.8 Power Line FET Control Electrical Characteristics
TJ = −40°C to 125°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VSENSE_N pin leakage current
VVSENSE_N = 45 V
0.1
3
µA
SD leakage current
VSD = 45 V
0.1
3
µA
230
283
µA
SD pulldown current
185
7.9 Current Sinks Electrical Characteristics
TJ = −40°C to 125°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.1
5
ILEAKAGE
Leakage current
Outputs OUT1 and OUT2, VOUT# =
45 V
IMAX
Maximum current
OUT1, OUT2
IOUT
Output current accuracy
IOUT = 160 mA
IMATCH
Output current matching (1)
IOUT = 160 mA, PWM duty =100%
1%
5%
VSAT
Saturation voltage (2)
IOUT = 160 mA , VLDO = 4.3 V
0.4
0.7
(1)
(2)
160
−5%
UNIT
µA
mA
5%
V
Output Current Accuracy is the difference between the actual value of the output current and programmed value of this current.
Matching is the maximum difference from the average. For the constant current sinks on the part (OUT1, OUT2), the following are
determined: the maximum output current (MAX), the minimum output current (MIN), and the average output current of all outputs (AVG).
Matching number is calculated: (MAX-MIN)/AVG. The typical specification provided is the most likely norm of the matching figure for all
parts. LED current sinks were characterized with 1-V headroom voltage. Note that some manufacturers have different definitions in use.
Saturation voltage is defined as the voltage when the LED current has dropped 10% from the value measured at 1 V.
7.10 PWM Brightness Control Electrical Characteristics
TJ = −40°C to 125°C (unless otherwise noted).
PARAMETER
ƒPWM
PWM input frequency
tON/OFF
Minimum on/off time (1)
(1)
TEST CONDITIONS
MIN
TYP
MAX
100
20 000
0.5
UNIT
Hz
µs
This specification is not ensured by ATE.
7.11 Boost or SEPIC Converter Characteristics
TJ = −40°C to 125°C (unless otherwise noted).
Unless otherwise specified: VIN = 12 V, EN/VDDIO = 3.3 V, L = 22 μH, CIN = 2 × 10 μF ceramic and 33 μF electrolytic,
COUT = 2 × 10-μF ceramic and 33-μF electrolytic, D = NRVB460MFS, ƒSW = 300 kHz.
PARAMETER
TEST CONDITIONS
VIN
Input voltage
VOUT
Output voltage
ƒSW_MIN
Minimum switching frequency
(central frequency if spread
spectrum is enabled)
ƒSW_MAX
Maximum switching frequency
(central frequency if spread
spectrum is enabled)
VOUT/VIN
Conversion ratio
MIN
TYP
MAX
UNIT
4.5
40
V
6
45
V
300
kHz
2 200
kHz
Defined by RFSET resistor
10
(1)
ƒSW ≥ 1.15 MHz
TOFF
Minimum switch OFF time
ISW_MAX
SW current limit
RDSON
FET RDSON
fSYNC
External SYNC frequency
tSYNC_ON_MIN
External SYNC minimum on
time (1)
150
ns
tSYNC_OFF_MIN
External SYNC minimum off
time (1)
150
ns
(1)
8
55
1.8
Pin-to-pin
ns
2
2.2
A
240
400
mΩ
2 200
kHz
300
This specification is not ensured by ATE.
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7.12 Logic Interface Characteristics
TJ = −40°C to 125°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC INPUT VDDIO/EN
VIL
Input low level
VIH
Input high level
II
Input current
0.4
1.65
−1
5
30
V
µA
LOGIC INPUT SYNC/FSET, PWM
VIL
Input low level
VIH
Input high level
II
Input current
0.2 × VDDIO/EN
0.8 × VDDIO/EN
−1
V
1
μA
0.5
V
1
μA
LOGIC OUTPUT FAULT
VOL
Output low level
Pullup current 3 mA
ILEAKAGE
Output leakage current
V = 5.5 V
0.3
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7.13 Typical Characteristics
Unless otherwise specified: D = NRVB460MFS, T = 25ºC
900
900
Boost Output Current (mA)
1000
Boost Output Crurrent (mA)
1000
800
700
600
500
Vboost = 22 V
400
Vboost = 30 V
300
800
700
600
500
Vboost = 22 V
400
Vboost = 30V
300
Vboost = 37 V
Vboost = 37 V
200
200
5
10
15
20
25
30
Input Voltage (V)
5
ƒSW = 300 kHz
L = 33 μH
DC load (PWM = 100%)
CIN and COUT = 33 µF + 2 × 10 µF (ceramic)
900
Boodt Output Current (mA)
900
800
700
600
500
Vboost = 22 V
Vboost = 30 V
C002
800
700
600
500
Vboost = 22 V
400
Vboost = 30 V
300
Vboost = 37 V
200
200
5
10
15
20
25
30
Input Voltage (V)
ƒSW = 1.5 MHz
L = 8.2 μH
CIN and COUT = 2 × 10 µF (ceramic)
5
10
DC load (PWM = 100%)
15
20
25
Input Voltage (V)
C003
ƒSW = 2.2 MHz
L = 4.7 μH
CIN and COUT = 2 × 10 µF (ceramic)
Figure 3. Maximum Boost Current
30
C004
DC load (PWM = 100%)
Figure 4. Maximum Boost Current
160
2200
140
1800
120
fSW (kHz)
LED Output Current (mA)
30
DC load (PWM = 100%)
Vboost = 37 V
100
80
60
20
20
1400
1000
600
40
200
20
40
60
80
100 120 140
RISET (k:)
160
180
200
60
100
140
180
RFSET (k )
220
220
C009
D001
Figure 5. LED Current vs RISET
10
25
Figure 2. Maximum Boost Current
1000
300
20
ƒSW = 800 kHz
L = 15 μH
CIN and COUT = 2 × 10 µF (ceramic)
Figure 1. Maximum Boost Current
400
15
Input Voltage (V)
1000
Boost Output Current (mA)
10
C001
Figure 6. Boost Switching Frequency fSW vs RFSET
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8 Detailed Description
8.1 Overview
The LP8862-Q1 is a highly integrated LED driver for automotive infotainment, lighting systems, and mediumsized LCD backlight applications. It includes a DC-DC with an integrated FET, supporting both boost and SEPIC
modes, an internal LDO enabling direct connection to battery without need for a pre-regulated supply, and two
LED current sinks. A VDDIO/EN pin provides the supply voltage for digital IOs (PWM and SYNC inputs) and at
the same time enables the device.
The switching frequency on the DC-DC regulator is set by a resistor connected to the FSET pin. The maximum
output voltage of the DC-DC is set by a resistive divider connected to the FB pin. For best efficiency the output
voltage is adapted automatically to the minimum necessary level needed to drive the LED strings. This is done
by monitoring LED output voltage drop in real time. For EMI reduction and control two optional features are
available:
• Spread spectrum, which reduces EMI noise around the switching frequency and its harmonic frequencies
• DC-DC can be synchronized to an external frequency connected to SYNC pin
The two constant current sinks OUT1 and OUT2 provide LED current up to 160 mA. Value for the current per
OUT pin is set with a resistor connected to ISET pin. Unused current sink must be connected to ground.
Grounded sink is disabled and excluded from adaptive output voltage control and LED string fault detection.
Brightness is controlled with the PWM input. Frequency range for the input PWM is from 100 Hz to 20 kHz. LED
output PWM follows the input PWM so the output frequency is equal to the input frequency.
The LP8862-Q1 has extensive fault detection features:
• Open-string and shorted LED detections
– LED fault detection prevents system overheating in case of open or short in some of the LED strings
• VIN input overvoltage protection
– Threshold sensing from VIN pin
• VIN input undervoltage protection
– Threshold sensing from VIN pin
• VIN input overcurrent protection
– Threshold sensing across RISENSE resistor
• Thermal shutdown in case of die overtemperature
Fault condition is indicated with the FAULT output pin. Additionally, the LP8862-Q1 supports control for an
optional power-line FET allowing further protection by disconnecting the device from power-line in fault condition.
With the power-line FET control it possible to protect device itself, DC-DC external components and LEDs in
case of shorted VOUT and too-high VIN voltage. Power-line FET control also features soft-start which reduces the
peak current from the power-line during start-up.
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8.2 Functional Block Diagram
RISENSE
VIN
L
Q
D
RGS
CIN
COUT
CIN BOOST
VIN
VSENSE_N
VOUT
SD
POWER-LINE FET CONTROL
LDO
LDO
CLDO
SW
SYNC
RFSET
PGND
BOOST
CONTROLLER
FSET
R1
FB
RISET
2 x LED
CURRENT
SINK
ISET
CURRENT
SETTING
R2
OUT1
OUT2
PWM
VDDIO/EN
FAULT
DIGITAL BLOCKS
(FSM, ADAPTIVE VOLTAGE
CONTROL, FAULT
DETECTION etc.)
VDDIO
GND
ANALOG BLOCKS
(CLOCK GENERATOR,
VREF, TSD etc.)
EXPOSED PAD
12
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8.3 Feature Description
8.3.1 Integrated DC-DC Converter
The LP8862-Q1 DC-DC converter generates supply voltage for the LEDs and can operate in boost mode or in
SEPIC mode. The maximum output voltage VOUT_MAX is defined by an external resistive divider (R1, R2).
VOUT_MAX must be chosen based on the maximum voltage required for LED strings. Recommended maximum
voltage is about 30% higher than maximum LED string voltage. DC-DC output voltage is adjusted automatically
based on LED current sink headroom voltage. Maximum, minimum, and initial boost voltages can be calculated
with Equation 1:
·
§V
VBOOST ¨ BG K u 0.0387 ¸ u R1 VBG
R2
©
¹
where
•
•
•
•
•
•
VBG = 1.2 V
R2 recommended value is 130 kΩ
Resistor values are in kΩ
K = 1 for maximum adaptive boost voltage (typical)
K = 0 for minimum adaptive boost voltage (typical)
K = 0.88 for initial boost voltage (typical)
(1)
45
Maximum Converter Output Voltage (V)
40
35
30
25
20
15
10
200
300
400
500
600
700
800
900
1000
R1 (k )
C008
Figure 7. Maximum Converter Output Voltage vs R1 Resistance
Alternatively, a T-divider can be used if resistance less than 100 kΩ is required for the external resistive divider.
Refer to Using the LP8862-Q1 Evaluation Module for details.
The converter is a current mode DC-DC converter, where the inductor current is measured and controlled with
the feedback. Switching frequency is adjustable between 300 kHz and 2.2 MHz with RFSET resistor as shown in
Equation 2:
ƒSW = 67600/ (RFSET + 6.4)
where
•
•
ƒSW is switching frequency, kHz
RFSET is frequency setting resistor, kΩ
(2)
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Feature Description (continued)
In most cases lower frequency has higher system efficiency. DC-DC parameters are chosen automatically
according to the selected switching frequency (see Table 2). In boost mode a 15-pF capacitor CFB must be
placed across resistor R1 when operating in 300-kHz to 500-kHz range (see Figure 19). When operating in 1.8MHz to 2.2-MHz range CFB = 4.7 pF.
D
VIN
VOUT
CIN
COUT
R1
SW
OCP
ADAPTIVE
VOLTAGE
CONTROL
RC
filter
FB
R2
LIGHT
LOAD
GM
S R
R
+
CURRENT
SENSE
OVP
R
R
PGND
SYNC
FSET
GM
FSET
CTRL
BOOST
OSCILLATOR
RFSET
OFF/BLANK
TIME
PULSE
GENERATOR
BLANK
TIME
CURRENT
RAMP
GENERATOR
Figure 8. Boost Block Diagram
DC-DC can be driven by an external SYNC signal between 300 kHz…2.2 MHz (Table 1). If the external
synchronization input disappears, DC-DC continues operation at the frequency defined by RFSET resistor. When
external frequency disappears and SYNC pin level is low, DC-DC continues operation without spread spectrum
immediately. If SYNC remains high, DC-DC continues switching with spread spectrum enabled after 256 µs.
External SYNC frequency must be 1.2…1.5 times higher than the frequency defined by RFSET resistor. Minimum
frequency setting with RFSET is 250 kHz to support a 300-kHz external clock.
The optional spread spectrum feature (±3% from central frequency, 1-kHz modulation frequency) reduces EMI
noise at the switching frequency and its harmonic frequencies. When external synchronization is used, internal
spread spectrum feature is not available.
Table 1. DC-DC Synchronization Mode
SYNC PIN INPUT
Spread spectrum disabled
High
Spread spectrum enabled
300...2200 kHz frequency
14
MODE
Low
Spread spectrum disabled, external synchronization mode
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Table 2. DC-DC Parameters (1)
RANGE
FREQUENCY
(kHz)
TYPICAL
INDUCTANCE
(µH)
TYPICAL INPUT
AND OUTPUT
CAPACITORS (µF)
MINIMUM SWITCH
OFF TIME (ns) (2)
BLANK
TIME (ns)
CURRENT
RAMP (A/s)
CURRENT
RAMP
DELAY (ns)
1
300...480
33
2 × 10 (ceramic) +
33 (electrolytic)
150
95
24
550
2
480...1150
15
10 (ceramic) +
33 (electrolytic)
60
95
43
300
3
1150...1650
10
3 × 10 (ceramic)
40
95
79
0
4
1650...2200
4.7
3 × 10 (ceramic)
40
70
145
0
(1)
(2)
Parameters are for reference only
Due to current-sensing comparator delay the actual minimum off time is 6 ns (typical) longer than in the table.
The converter SW pin DC current is limited to 2 A (typical). To support warm start transient condition the current
limit is automatically increased to 2.5 A for a short period of 1.5 seconds when a 2-A limit is reached.
NOTE
Application condition where the 2-A limit is exceeded continuously is not allowed. In this
case the current limit would be 2 A for 1.5 seconds followed by 2.5-A limit for 1.5 seconds,
and this 3-second period repeats.
To keep switching voltage within safe levels there is a 48-V limit comparator in the event that FB loop is broken.
8.3.2 Internal LDO
The internal LDO regulator converts the input voltage at VIN to a 4.3-V output voltage for internal use. Connect
LDO output with a minimum of 1-μF ceramic capacitor to ground as close to the LDO pin as possible. If an
external voltage higher than 4.5 V is connected to LDO pin, the internal LDO is disabled, and the internal circuitry
is powered from the external power supply. VIN and VSENSE_N pins must be connected to the same external
voltage as LDO pin. For an application example schematic refer to the LP8861-Q1 data sheet (SNVSA50).
8.3.3 LED Current Sinks
8.3.3.1 Current Sink Configuration
The LP8862-Q1 detects LED current sink configuration during start-up. A current sink connected to ground is
disabled and excluded from the adaptive DC-DC control and fault detection.
8.3.3.2 Current Setting
Maximum current for the LED current sinks is controlled with external RISET resistor. Resistor value for targeted
LED string current can be calculated using Equation 3:
RISET = 4000 × VBG / ILED
where
•
•
RISET is current setting resistor, kΩ
ILED is output current per output, mA
(3)
8.3.3.3 Brightness Control
The LP8862-Q1 controls the brightness of the display with conventional PWM. Output PWM directly follows the
input PWM. Input PWM frequency can be in the range of 100 Hz to 20 kHz.
8.3.4 Power Line FET Control
The LP8862-Q1 has a control pin (SD) for driving the gate of an external power-line FET. Power-line FET is an
optional feature. Power-line FET limits inrush current by turning on gradually when the device is enabled
(VDDIO/EN = high, VIN > VGS). Inrush current is controlled by increasing sink current for the FET gradually to 230
μA. In shutdown the LP8862-Q1 turns off the power-line FET and prevents possible DC-DC and LEDs leakage.
The power switch also turns off in case of any fault which causes the device to enter FAULT RECOVERY state.
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8.3.5 Fault Detections
The LP8862-Q1 has fault detection for LED open and short, VIN input overvoltage (VIN_OVP), VIN undervoltage
lockout (VIN_UVLO), power-line overcurrent (VIN_OCP), and thermal shutdown (TSD).
8.3.5.1 Adaptive DC-DC Voltage Control and Functionality of LED Fault Comparators
Adaptive voltage control function adjusts the DC-DC output voltage to the minimum sufficient voltage for proper
LED current sink operation. The current sink with highest VF LED string is detected and DC-DC output voltage
adjusted accordingly. DC-DC adaptive control voltage step size is defined by maximum voltage setting, VSTEP =
(VOUT_MAX – VOUT_MIN) /256. Periodic down pressure is applied to the target voltage to achieve better system
efficiency.
Every LED current sink has 3 comparators for the adaptive DC-DC control and LED-fault detections. Comparator
outputs are filtered; filtering time is 1 µs.
OUT#
SHORT STRING
DETECTION LEVEL
HIGH_COMP
VOLTAGE THRESHOLD
MID_COMP
LOWEST VOLTAGE
LOW_COMP
CURRENT/PWM
CONTROL
Figure 9. Comparators for Adaptive Voltage Control and LED Fault Detection
Figure 10 illustrates different cases which cause DC-DC voltage increase, decrease, or generate faults. In
normal operation, voltage at the OUT1 and OUT2 pins is between LOW_COMP and MID_COMP levels, and
VOUT voltage stays constant. LOW_COMP level is the minimum for proper LED current sink operation, 1.1 × VSAT
+ 0.2 V (typical). MID_COMP level is 1.1 × VSAT + 1.2 V (typical) so typical headroom window is 1 V.
When voltage at OUT1 and OUT2 pin increases above MID_COMP level, DC-DC voltage adapts downwards.
When voltage at OUT1 or OUT2 pin falls below LOW_COMP threshold, DC-DC voltage adapts upwards. In the
condition where VOUT reaches the maximum and there are one or more outputs still below LOW_COMP level, an
open LED fault is detected.
OUT# PIN
VOLTAGE
HIGH_COMP level, 6 V typical, is the threshold for shorted LED detection. When the voltage of OUT1 or OUT2
pin increases above HIGH_COMP level and the other output is within the normal headroom window, shorted
LED fault is detected.
No actions
No actions
DC-DC
decreases
voltage
Both outputs are
above headroom
window
HIGH_COMP
DC-DC
increases
voltage
Minimum
headroom
level
reached
Shorted LED fault (one
output should be
between LOW_COMP
Open LED fault when
and MID_COMP)
VOUT=VOUT_MAX
Shorted
LED fault
Open LED
fault
MID_COMP
HEADROOM
WINDOW
OUT2
OUT1
OUT2
OUT1
OUT2
OUT1
OUT2
OUT1
OUT2
OUT1
OUT2
OUT1
LOW_COMP
Figure 10. DC-DC Adaptation and LED Fault Detection Algorithms
16
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8.3.5.2 Overview of the Fault/Protection Schemes
Summary of LP8862-Q1 fault detection behavior is shown in Table 3. Detected faults (excluding LED open or
short) cause device to enter FAULT_RECOVERY state. In FAULT_RECOVERY the DC-DC and LED current
sinks of the device are disabled, power-line FET is turned off, and the FAULT pin is pulled low. The device
recovers automatically and enters normal operating mode (ACTIVE) after a recovery time of 100 ms if the fault
condition has disappeared. When recovery is succesful, FAULT pin is released.
In case a LED fault is detected, device continues normal operation and only the faulty string is disabled. Fault is
indicated via FAULT pin which can be released by toggling VDDIO/EN pin low for a short period of 2…20 µs.
LEDs are turned off for this period but device stays in ACTIVE mode. If VDDIO/EN is low longer, device goes to
STANDBY and restarts when EN goes high again.
Table 3. Fault Detections
FAULT/
PROTECTION
FAULT_
RECOVERY
STATE
ACTION
Yes
Yes
1. Overvoltage is monitored from the beginning of soft start. Fault is
detected if the duration of over-voltage condition is 100 µs minimum.
2. Overvoltage is monitored from the beginning of normal operation
(ACTIVE mode). Fault is detected if over-voltage condition duration is
560 ms minimum (tfilter). After the first fault detection filter time is
reduced to 50 ms for following recovery cycles. When device recovers
and has been in ACTIVE mode for 160 ms, filter time is increased
back to 560 ms .
Falling 3.9 V
Rising 4 V
Yes
Yes
Detects undervoltage condition at VIN pin. Sensed in all operating
modes. Fault is detected if undervoltage condition duration is 100 µs
minimum.
3 A (50-mΩ current
sensor resistor)
Yes
Yes
Detects over current by measuring voltage of the RISENSE resistor
connected between VIN and VSENSE_N pins. Sensed from the
beginning of soft start. Fault is detected if undervoltage condition
duration is 10 µs minimum.
No
Detected if the voltage of OUT1 pin or OUT2 pin is below threshold
level, and DC-DC adaptive control has reached maximum voltage.
Open string(s) is removed from the adaptive voltage control loop and
current sink is disabled.
Fault pin is released by toggling VDDIO/EN pin. If VDDIO/EN is low for
a period of 2…20 µs, LEDs are turned off for this period but device
stays ACTIVE. If VDDIO/EN is low longer, device goes to STANDBY
and restarts when EN goes high again.
Yes
No
Detected if the voltage of OUT1 pin or OUT2 pin is above shorted
string detection level, and the voltage of the other OUT pin is within
headroom window. Shorted string is removed from the adaptive
voltage control loop and current sink is disabled.
Fault pin is released by toggling the VDDIO/EN pin. If VDDIO/EN is
low for a period of 2…20 µs, LEDs are turned off for this period but
device stays ACTIVE. If VDDIO/EN is low longer, device goes to
STANDBY and restarts when EN goes high again.
Yes
Yes
Thermal shutdown is monitored from the beginning of soft start. Die
temperature must decrease by 20°C for device to recover.
FAULT
NAME
THRESHOLD
VIN
overvoltage
protection
VIN_OVP
1. VIN > 42 V
2. VOUT > VSET_DCDC +
6..10 V.
VSET_DCDC is voltage
value defined by logic
during adaptation
VIN
undervoltage
lockout
VIN_UVLO
VIN overcurrent
protection
VIN_OCP
Open LED fault
OPEN_LED
Shorted LED
fault
SHORT_LED
Thermal
protection
TSD
LOW_COMP
threshold
Shorted string
detection level 6 V
165ºC
Thermal Shutdown
Hysteresis 20ºC
FAULT
PIN
Yes
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Time is not enough to
discharge COUT
VIN OVERVOLTAGE
VIN OK
VIN
VOUT
VSET_DCDC +6...10 V
Powerline
FET state
ON
OFF
tFILTER = 560 ms
tRECOVERY =
100 ms
ON
OFF
tFILTER =
50 ms
tRECOVERY =
100 ms
OFF
ON
ON
IOUT
FAULT
tSOFTSTART +
tBOOST START
tSOFTSTART + tFILTER =
tRECOVERY =
tBOOST START 40 - 50 ms
100 ms
tSOFTSTART + tFILTER =
tBOOST START 50 ms
Figure 11. VIN Overvoltage Protection (DC-DC OVP)
VIN OVP threshold
VIN
DC-DC OVP threshold
FB
Powerline
FET state
ON
OFF
FAULT
ttRECOVERY = 100 mst
ON
ttSOFTSTART +t
ttBOOST STARTUPt
ttRECOVERY = 100 mst
Figure 12. VIN Overvoltage Protection (VIN OVP)
UVLO falling threshold
UVLO rising threshold
VIN
FB
Powerline
FET state
ON
FAULT
OFF
ttRECOVERY = 100 mst
ON
ttSOFTSTART +t
ttBOOST STARTUPt
ttRECOVERY = 100 mst
Figure 13. VIN Undervoltage Lockout
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3 A @ 50 m
IIN
FB
Powerline
FET state
ON
OFF
ON
ttRECOVERY = 100 mst
OFF
ttSOFTSTART +t
ttBOOST STARTUPt
ttRECOVERY = 100 mst
FAULT
Figure 14. Input Voltage Overcurrent Protection
VOUT_MAX
VOUT
OUT# pin
Other LEDs
OUT# pin
Open LED
LOW_COMP level
t = 2...20 µs
VDDIO/EN
FAULT
Figure 15. LED Open Fault
OUT# pin
Other LEDs
OUTT# pin
Shorted LED
MID_COMP level
LOW_COMP level
HIGH_COMP level
t = 2...20 µs
VDDIO/EN
FAULT
Figure 16. LED Short Fault
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8.4 Device Functional Modes
8.4.1 Device States
The LP8862-Q1 enters STANDBY mode when the internal LDO output rises above the power-on reset level,
VLDO > VPOR. In STANDBY mode the device is able to detect the VDDIO/EN signal. When VDDIO/EN is pulled
high, the device powers up. During soft start the external power-line FET is opened gradually to limit inrush
current. Soft start is followed by boost (SEPIC) start, during which time VOUT is ramped to the initial value. After
boost (SEPIC) start LED outputs are sensed to detect grounded outputs. Grounded outputs are disabled and
excluded from the adaptive boost (SEPIC) voltage control loop.
If a fault condition is detected, the LP8862-Q1 enters FAULT_RECOVERY state. In this state power line FET is
switched off and both the boost (SEPIC) and LED current sinks are disabled. Faults that cause the device to
enter FAULT_RECOVERY are shown in Figure 17. When LED open or short is detected, faulty string is disabled
but the device stays in ACTIVE mode.
POR = 1
STANDBY
VDDIO / EN = 1
100 ms
VIN_OCP
VIN_OVP
VIN_UVLO
TSD
SOFT START
65 ms
BOOST START
50 ms
FAULT RECOVERY
FAULTS
VDDIO / EN = 0
FAULT
RECOVERY?
FAULTS:
- VIN_OCP
- VIN_OVP
- VIN_UVLO
- TSD
NO
FAULTS
LED OUTPUT
CONFIGURATION
DETECTION
YES
ACTIVE
BOOST, LED CURRENT SINKS
AND POWER LINE FET ARE
DISABLED IN FAULT RECOVERY
STATE
VDDIO / EN = 0
SHUTDOWN
Figure 17. State Diagram
20
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Device Functional Modes (continued)
T = 50 s
t > 500 s
VIN
VLDO
VVDDIO/EN
SYNC
PL pFET drain
Headroom adaptation
VOUT = VIN level ± diode drop
VOUT
PWM OUT
IQ
Active mode
SOFT
tSTARTt
tBOOSTt
START
Figure 18. Timing Diagram for Typical Start-Up and Shutdown
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9 Application and Implementation
9.1 Application Information
The LP8862-Q1 is designed for automotive applications, and an input voltage VIN is intended to be connected to
the automotive battery. Device circuitry is powered from the internal LDO, which can alternatively be used as an
external VDD voltage — in this case external voltage should be in 4.5-V to 5.5-V range.
The LP8862-Q1 uses a simple four-wire control:
• VDDIO/EN for enable
• PWM input for brightness control
• SYNC pin for boost synchronisation (optional)
• FAULT output to indicate fault condition (optional)
9.2 Typical Applications
9.2.1 Typical Application for 2 LED Strings
Figure 19 shows typical application for the LP8862-Q1 which supports 2 LED strings with maximum current 160
mA per string. Boost switching frequency in this example is is 400 kHz.
VIN
RISENSE
4.5...28 V
L1
Q1
D1
CIN BOOST
Up to 37 V
COUT
RGS
R2
SW
SD
VSENSE_N
FB
CFB
VIN
CIN
R1
Up to 160 mA/string
LDO
CLDO
RFSET
LP8862-Q1
OUT1
FSET
OUT2
SYNC
BRIGHTNESS
PWM
EN
VDDIO/EN
FAULT
FAULT
R3
ISET
PGND
GND
PAD
RISET
VDDIO
Figure 19. LP8862-Q1 Boost Mode, Two Strings, 160-mA String Configuration
22
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Typical Applications (continued)
9.2.1.1 Design Requirements
Typical design parameters for a boost-mode two-string configuration are shown in Table 4:
Table 4. Boost Mode Design Parameters
DESIGN PARAMETER
VALUE
VIN voltage range
4.5…28 V
LED string
2 × 8 LEDs (30 V)
LED string current
160 mA
Max boost voltage
37 V
Boost switching frequency
400 kHz
External boost sync
not used
Boost spread spectrum
enabled
L1
22 μH
CIN
10 µF, 50 V
CIN BOOST
2 × (10-µF 50-V ceramic) + 33-µF 50-V electrolytic
COUT
2 × (10-µF 50-V ceramic) + 33-µF 50-V electrolytic
CFB
15 pF
CLDO
1 µF, 10 V
RISET
30 kΩ
RFSET
160 kΩ
RISENSE
50 mΩ
R1
750 kΩ
R2
130 kΩ
R3
10 kΩ
RGS
20 kΩ
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Inductor Selection
There are two main considerations when choosing an inductor; the inductor must not saturate, and the inductor
current ripple must be small enough to achieve the desired output voltage ripple. Different saturation current
rating specifications are followed by different manufacturers so attention must be given to details. Saturation
current ratings are typically specified at 25°C. However, ratings at the maximum ambient temperature of
application should be requested from the manufacturer. Shielded inductors radiate less noise and are preferred.
The saturation current must be greater than the sum of the maximum load current and the worst case averageto-peak inductor current. Equation 4 shows the worst-case conditions:
IOUTMAX
+ IRIPPLE For Boost
'¶
(VOUT - VIN) VIN
x
Where IRIPPLE =
(2 x L x f)
VOUT
ISAT >
Where D =
•
•
•
•
•
•
•
•
(VOUT ± VIN)
(VOUT)
DQG '¶ = (1 - D)
IRIPPLE - peak inductor current
IOUTMAX - maximum load current
VIN - minimum input voltage in application
L - min inductor value including worst case tolerances
f - minimum switching frequency
VOUT - output voltage
D - Duty Cycle for CCM Operation
VOUT - Output Voltage
(4)
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As a result the inductor must be selected according to the ISAT. A more conservative and recommended
approach is to choose an inductor that has a saturation current rating greater than the maximum current limit. A
saturation current rating of at least 3 A is recommended for most applications. See Table 2 for inductance
recommendations for the different switching frequency ranges. Resistance of the inductor must be less than 300
mΩ for good efficiency.
See detailed information in Understanding Boost Power Stages in Switch Mode Power Supplies. “Power Stage
Designer™ Tools” can be used for the boost calculation: http://www.ti.com/tool/powerstage-designer.
9.2.1.2.2 Output Capacitor Selection
A ceramic capacitor with 2 × VMAX BOOST or more voltage rating is recommended for the output capacitor. The
DC-bias effect can reduce the effective capacitance by up to 80%, which needs to be considered in capacitance
value selection. Capacitance recommendations for different boost switching frequencies are shown in Table 2.
To minimize audible noise of ceramic capacitors their geometric size must typically be minimized.
9.2.1.2.3 Input Capacitor Selection
A ceramic capacitor with 2 × VVIN MAX or more voltage rating is recommended for the input capacitor. The DCbias effect can reduce the effective capacitance by up to 80%, which needs to be considered in capacitance
value selection. Capacitance recommendations for different boost switching frequencies are shown in Table 2.
9.2.1.2.4 LDO Output Capacitor
A ceramic capacitor with at least 10-V voltage rating is recommended for the output capacitor of the LDO. The
DC-bias effect can reduce the effective capacitance by up to 80%, which needs to be considered in capacitance
value selection. Typically a 1-µF capacitor is sufficient.
9.2.1.2.5 Diode
A Schottky diode should be used for the boost output diode. Do not use ordinary rectifier diodes, since slow
switching speeds and long recovery times cause the efficiency and the load regulation to suffer. Diode rating for
peak repetitive current must be greater than inductor peak current (up to 3 A) to ensure reliable operation.
Average current rating must be greater than the maximum output current. Schottky diodes with a low forward
drop and fast switching speeds are ideal for increasing efficiency. Choose a reverse breakdown voltage of the
Schottky diode significantly larger than the output voltage.
9.2.1.2.6 Power Line Transistor
A pFET transistor with necessary voltage rating (VDS at least 5 V higher than max input voltage) must be used.
Current rating for the FET must be the same as input peak current or greater. Transfer characteristic is very
important for pFET. VGS for open transistor must be less than VIN. A 20-kΩ resistor between pFET gate and
source is sufficient.
9.2.1.2.7 Input Current Sense Resistor
A high-power 50 mΩ resistor must be used for sensing the boost input current. Power rating can be calculated
from the input current and sense resistor resistance value. Increasing RISENSE decreases VIN_OCP current
proportionally.
24
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9.2.1.3 Application Curves
SD 2V/div
VBOOST 10V/div
IBOOST 200mA/div
VDDIO/EN 5 V/div
40ms/div
ƒSW = 300 kHz
VIN = 10 V
Brightness PWM 50% 100 Hz
Open string connected to OUT1
Figure 21. Open LED Fault
95
95
90
90
85
85
System Efficiency (%)
Boost Efficiency (%)
Figure 20. Typical Start-Up
80
75
70
65
VIN=5V
VIN=8V
VIN=12V
VIN=16V
60
55
80
75
70
65
VIN=5V
VIN=8V
VIN=12V
VIN=16V
60
55
50
50
0
10
20
30
40
50
60
Brightness (%)
70
80
Two strings, 8 LEDs per string
160 mA/string for VIN = 12 V and VIN = 16 V
130 mA/string for VIN = 8 V
90 mA/string for VIN = 5 V
90
100
0
10
D001
ƒSW = 400 kHz
20
30
40
50
60
Brightness (%)
70
80
Two strings, 8 LEDs per string
160 mA/string for VIN = 12 V and VIN = 16 V
130 mA/string for VIN = 8 V
90 mA/string for VIN = 5 V
Figure 22. Boost Efficiency
90
100
D001
fSW = 400 kHz
Figure 23. System Efficiency
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9.2.2 SEPIC Mode Application
When LED string voltage can be above or below VIN voltage, SEPIC configuration can be used. In Figure 24 an
external frequency is used to synchronize SEPIC switching frequency. External frequency can be modulated to
spread switching frequency spectrum.
VIN
RISENSE
4.5...30 V
Q1
Up to 15 V
D1
L1
C1
COUT
CIN SEPIC
RGS
R2
SW
SD
VSENSE_N
CIN
CLDO
R1
FB
VIN
Up to 160 mA/string
LDO
RFSET
LP8862-Q1
OUT1
FSET
BOOST SYNC
OUT2
SYNC
BRIGHTNESS
PWM
EN
VDDIO/EN
FAULT
FAULT
ISET
R3
PGND
GND
PAD
VDDIO
RISET
Figure 24. SEPIC Mode, 2 Strings, 160-mA String Configuration
Typical design parameters for a SEPIC-mode two-string configuration are shown in Table 5:
Table 5. SEPIC Mode Design Parameters
DESIGN PARAMETER
26
VALUE
VIN voltage range
4.5…30 V
LED string
2 × 2 LEDs (9 V)
LED string current
160 mA
Max output voltage
15 V
SEPIC switching frequency
300 kHz
External boost sync
used
Spread spectrum
Internal spread spectrum not available, external frequency input can
be modulated
L1
22 μH
CIN
10 µF, 50 V
CIN SEPIC
2 × (10-µF 50-V ceramic) + 33-µF 50-V electrolytic
COUT
2 × (10-µF 50-V ceramic) + 33-µF 50-V electrolytic
CLDO
1 µF, 10 V
RISET
30 kΩ
RFSET
210 kΩ
RISENSE
50 mΩ
R1
300 kΩ
R2
130 kΩ
R3
10 kΩ
RGS
20 kΩ
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9.2.2.1 Detailed Design Procedure
In SEPIC mode the maximum voltage at the SW pin is equal to the sum of the input voltage and the output
voltage. Because of this, the maximum sum of input and output voltage must be limited below 50 V. See Detailed
Design Procedure for general external component guidelines. The main differences of SEPIC compared to boost
are described below.
Power Stage Designer™ Tool can be used for modeling SEPIC behavior: http://www.ti.com/tool/powerstagedesigner. For detailed explanation on SEPIC see Texas Instruments Analog Applications Journal Designing
DC/DC Converters Based on SEPIC Topology (SLYT309).
9.2.2.1.1 Inductor
In SEPIC mode, coupled coil saturation rating should be higher than input side inductor peak current. Current
values can be estimated using Power Stage Designer™ Tool or using equations in SLYT309.
9.2.2.1.2 Diode
In SEPIC mode diode peak current is equal to the sum of input and output currents. Diode rating for peak
repetitive current must be greater than SW pin current limit (up to 3 A for transients) to ensure reliable operation.
Average current rating must be greater than the maximum output current. Voltage rating must be higher than
sum of input and output voltages.
9.2.2.1.3 Capacitor C1
A ceramic capacitor with low ESR is recommended. Voltage rating must be higher than maximum input voltage.
9.2.2.2 Application Curves
95
90
SEPIC Efficiency (%)
85
80
75
70
65
VIN=5V
VIN=8V
VIN=12V
VIN=15V
60
55
50
0
10
20
30
40
50
60
Brightness (%)
70
80
Two strings, 2 LEDs per string
90
100
D001
ƒSW = 300 kHz
160 mA/string
Figure 25. SEPIC Efficiency
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95
System Efficiency (%)
90
85
80
75
70
65
VIN=5V
VIN=8V
VIN=12V
VIN=15V
60
55
50
0
10
20
30
40
50
60
Brightness (%)
70
80
Two strings, 2 LEDs per string
90
100
D001
fSW = 300 kHz
160 mA/string
Figure 26. System Efficiency
10 Power Supply Recommendations
The LP8862-Q1 device is designed to operate from an automotive battery. The device must be protected from
reversal voltage and voltage dump over 50 V. The resistance of the input supply rail must be low enough so that
the input current transient does not cause too-high drop at the LP8862-Q1 VIN pin. If the input supply is
connected by using long wires additional bulk capacitance may be required in addition to the ceramic bypass
capacitors in the VIN line.
28
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11 Layout
11.1 Layout Guidelines
Figure 27 shows a recommended layout for the LP8862-Q1 used to demonstrate the principles of a good layout.
This layout can be adapted to the actual application layout if or where possible. It is important that all boost
components are close to the chip, and the high current traces must be wide enough. By placing boost
components on one side of the chip it is easy to keep the ground plane intact below the high current paths. This
way other chip pins can be routed more easily without splitting the ground plane. Place LDO capacitor as close
to LDO pin as possible.
Here are some main points to help the PCB layout work:
• Current loops need to be minimized:
– For low frequency the minimal current loop can be achieved by placing the boost components as close as
possible to the SW and PGND pins. Input and output capacitor grounds need to be close to each other to
minimize current loop size.
– Minimal current loops for high frequencies can be achieved by making sure that the ground plane is intact
under the current traces. High frequency return currents try to find route with minimum impedance, which
is the route with minimum loop area, not necessarily the shortest path. Minimum loop area is formed when
return current flows just under the positive current route in the ground plane, if the ground plane is intact
under the route.
• The GND plane needs to be intact under the high current boost traces to provide shortest possible return path
and smallest possible current loops for high frequencies.
• Current loops when the boost switch is conducting and not conducting need to be on the same direction in
optimal case.
• Inductor placement should be so that the current flows in the same direction as in the current loops. Rotating
inductor 180° changes current direction.
• Use separate power and noise free grounds. The power ground is used for boost converter return current and
noise-free ground for more sensitive signals, like LDO bypass capacitor grounding as well as grounding the
GND pin of LP8862-Q1 device itself.
• Boost output feedback voltage to LEDs needs to be taken out after the output capacitors, not straight from the
diode cathode.
• Place LDO 1-µF bypass capacitor as close as possible to the LDO pin.
• Input and output capacitors need strong grounding (wide traces, many vias to GND plane).
• If two output capacitors are used they need symmetrical layout to get both capacitors working ideally.
• Output ceramic capacitors have DC-bias effect. If the output capacitance is too low, it can cause boost to
become unstable on some loads and this increases EMI. DC bias characteristics need to be obtained from
the component manufacturer; it is not taken into account on component tolerance. X5R/X7R capacitors are
recommended.
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11.2 Layout Example
RISENSE
VIN
VLDO
RFSET
RGS
VSENSE_N
20
LDO
SD
19
FSET
SW
18
PGND
17
1
VIN
2
3
VDDIO/EN
4
FAULT
5
FB
16
SYNC
6
OUT1
15
PWM
7
OUT2
14
8
NC
NC
13
9
GND
NC
12
10
ISET
GND
11
RISET
VOUT
LED
STRINGS
Figure 27. LP8862-Q1 Boost Layout
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12 Device and Documentation Support
12.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Using the LP8862-Q1EVM Evaluation Module
• PowerPAD™ Thermally Enhanced Package Application Note
• Understanding Boost Power Stages in Switch Mode Power Supplies
• Designing DC/DC Converters Based on SEPIC Topology
• Power Stage Designer™ Tool can be used for both boost and SEPIC: http://www.ti.com/tool/powerstagedesigner
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LP8862QPWPRQ1
ACTIVE
HTSSOP
PWP
20
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LP8862Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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