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LPV821
SNOSD36A – AUGUST 2017 – REVISED DECEMBER 2017
LPV821, 650nA, Precision, Nanopower, Zero-Drift Amplifier
1 Features
3 Description
•
•
•
•
•
•
•
•
•
The LPV821 is a single-channel, nanopower, zerodrift operational amplifier for “Always ON” sensing
applications in wireless and wired equipment where
low input offset is required. With the combination of
low initial offset, low offset drift, and 8 kHz of
bandwidth from 650 nA of quiescent current, the
LPV821 is the industry's lowest power zero-drift
amplifier that can be used for end equipment that
monitor current consumption, temperature, gas, or
strain gauges.
1
•
Quiescent Current: 650 nA
Low Offset Voltage: ±10 μV (Maximum)
Offset Voltage Drift: ±0.096 μV/°C (Maximum)
0.1-Hz to 10-Hz Noise: 3.9 μVPP
Input Bias Current: ±7 pA
Gain Bandwidth: 8 kHz
Supply Voltage: 1.7 V to 3.6 V
Rail-to-Rail Input/Output
Industry Standard Package
– Single in 5-pin SOT-23
EMI Hardened
The LPV821 zero-drift operational amplifier uses a
proprietary
auto-calibration
technique
to
simultaneously provide low offset voltage (10 μV,
maximum) and minimal drift over time and
temperature. In addition to having low offset and
ultra-low quiescent current, the LPV821 amplifier has
pico-amp bias currents which reduce errors
commonly introduced in applications monitoring
sensors with high output impedance and amplifier
configurations with megaohm feedback resistors.
2 Applications
•
•
•
•
•
•
•
Battery-Powered Instruments
Gas Detection
Process Analytics
Fault Monitoring
Current Sensing
– Shunt Resistor
– Current Transformer
Temperature Measurements
– High Impedance Thermistors
– RTD's, Thermocouples
Strain Gauges
– Electronic Scales
– Pressure Sensors
Device Information(1)
PART
NUMBER
CHAN
COUNT
PACKAGE
BODY SIZE (NOM)
LPV821
1
SOT-23 (5)
2.90 mm × 1.60 mm
2
WSON (8)
2.00 mm × 2.00 mm
LPV822
(2)
Precision Nano-Power Amplifier Family
FAMILY
CHAN
COUNT
IQ PER
CHAN
LPV821
1
LPV811
1
LPV812
OPA369
VOS (MAX)
VSUPPLY
650 nA
10 µV
1.7 to 3.6 V
450 nA
370 µV
1.6 to 5.5 V
2
425 nA
300 µV
1.6 to 5.5 V
1,2
800 nA
750 µV
1.8 to 5.5 V
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Planned for near-future release
Low-Side, Always-On Current Sense
VS
R4
LOAD
Load
Current
R3
+
Vshunt
Vcc
LPV821
Rshunt
R1
VOUT
+
Vbias
R2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LPV821
SNOSD36A – AUGUST 2017 – REVISED DECEMBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 13
9
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Applications ............................................... 15
10 Power Supply Recommendations ..................... 16
11 Layout................................................................... 17
11.1 Layout Guidelines ................................................. 17
11.2 Layout Example .................................................... 17
12 Device and Documentation Support ................. 18
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support......................................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
18
18
18
13 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
Changes from Original (August 2017) to Revision A
•
Page
Changed Advanced Information to Production Data Release................................................................................................ 1
5 Description (continued)
The LPV821 amplifier also features an input stage with rail-to-rail input common mode range and an output stage
that swings within 12 mV of the rails, maintaining the widest dynamic range possible. The device is EMI
hardened to reduce system sensitivity to unwanted RF signals from mobile phones, WiFi, radio transmitters, and
tag readers.
The LPV821 zero-drift amplifier operates with a single supply voltage as low as 1.7V, ensuring continuous
performance in low battery situations over the extended temperature range of -40ºC to 125ºC. The LPV821
(single) is available in industry standard 5-pin SOT-23.
2
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SNOSD36A – AUGUST 2017 – REVISED DECEMBER 2017
6 Pin Configuration and Functions
LPV821 5-Pin SOT-23
DBV Package
Top View
LPV822 8-Pin WSON
DSG Package
Top View
OUT A
1
±IN A
2
+IN A
3
V±
4
Exposed
Thermal
Die Pad
on
Underside
8
V+
7
OUT B
6
±IN B
5
+IN B
Pin Functions: LPV821 DBV
PIN
I/O
DESCRIPTION
NAME
NUMBER
OUT
1
O
Output
V–
2
P
Negative (lowest) power supply
+IN
3
I
Non-Inverting Input
–IN
4
I
Inverting Input
V+
5
P
Positive (highest) power supply
Pin Functions: LPV822 DSG (Preview)
PIN
I/O
DESCRIPTION
NAME
NUMBER
OUT A
1
O
Channel A Output
-IN A
2
I
Channel A Inverting Input
+IN A
3
I
Channel A Non-Inverting Input
V-
4
P
Negative (lowest) power supply
+IN B
5
I
Channel B Non-Inverting Input
-IN B
6
I
Channel B Inverting Input
OUT B
7
O
Channel B Output
V+
8
P
Positive (highest) power supply
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LPV821
SNOSD36A – AUGUST 2017 – REVISED DECEMBER 2017
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7 Specifications
7.1 Absolute Maximum Ratings
(1)
See
Supply, VS = (V+) - (V–)
Input/Output Pin Voltage (2)
Voltage
Current
(3)
MIN
MAX
-0.3
4
(V–) - 0.3
(V+) + 0.3
Differential Input Voltage +IN - (-IN) (2)
- 0.3
+ 0.3
Signal input terminals (2)
–10
10
Continuous
Continuous
Output short-circuit
(4)
Junction temperature
–40
125
Storage temperature, Tstg
–65
150
(2)
(3)
(4)
V
mA
150
Operating ambient temperature
(1)
UNIT
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under . Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should
be current limited to 10 mA or less.
Not to exceed -0.3V or +4.0V on ANY pin, referred to VShort-circuit to ground, one amplifier per package.
7.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply
voltage
VS = (V+) - (V–)
Specified
temperature
NOM
MAX
UNIT
1.7
3.6
V
–40
125
°C
7.4 Thermal Information
LPV821
THERMAL METRIC
DBV (SOT)
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance
218.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
101.3
°C/W
RθJB
Junction-to-board thermal resistance
52.9
°C/W
ψJT
Junction-to-top characterization parameter
18.9
°C/W
ψJB
Junction-to-board characterization parameter
52.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
4
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SNOSD36A – AUGUST 2017 – REVISED DECEMBER 2017
7.5 Electrical Characteristics
TA = 25°C, VS = 1.8 V to 3.3 V, VCM = VOUT = VS/2, and RL≥ 10 MΩ to VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
VS = 3.3 V
dVOS/dT
Input offset voltage drift
TA = –40°C to 125°C, VS = 3.3 V
PSRR
Power-supply rejection ratio
VS = 1.8 V to 3.3 V
±1.5
±10
±0.02
±0.096
μV/°C
0.4
4.5
μV/V
μV
INPUT
BIAS CURRENT
TA= 25°C
+IN
IB
Input bias current
-IN
IOS
7
TA= 125°C
7
TA= 25°C
-7
TA= 125°C
pA
-250
Input offset current
14
pA
NOISE
En
Input voltage noise
f = 0.1 Hz to 10 Hz
3.9
μVPP
en
Input voltage noise density
f = 100 Hz
215
nV/√Hz
in
Input current noise density
f = 100 Hz
1
fA/√Hz
INPUT
VOLTAGE
VCM
Common-mode voltage range
CMRR
Common-mode rejection ratio
(V–)
(V–) ≤ VCM ≤ (V+), VS = 3.3 V
100
(V+)
V
125
dB
Differential
3.3
pF
Common-mode
3.7
pF
135
dB
INPUT
CAPACITANCE
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
(V–) + 0.1 V ≤ VO ≤ (V+) – 0.1 V, RL = 100 kΩ to VS / 2
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
CL = 20 pF, RL = 10 MΩ
SR
Slew rate
G = +1, CL = 20 pF
8
kHz
3.3
V/ms
VOH
Voltage output swing from
positive rail
RL = 100 kΩ to V+/2, VS = 3.3 V
12
VOL
Voltage output swing from
negative rail
RL = 100 kΩ to V+/2, VS = 3.3 V
12
ISC
Short-circuit current
CL
Capacitive load drive
ZO
Open-loop output impedance
ƒ = 100 Hz, IO = 0 A
Quiescent current per channel
VCM = VS/2, IO = 0, VS = 3.3 V
OUTPUT
mV
Sourcing, VO to V–, VIN (diff) = 100 mV, VS = 3.3 V
21
Sinking, VO to V+, VIN (diff) = –100 mV, VS = 3.3 V
50
mA
See
Table 1
80
kΩ
POWER
SUPPLY
IQ
650
790
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SNOSD36A – AUGUST 2017 – REVISED DECEMBER 2017
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7.6 Typical Characteristics
At TA = 25°C, VS = 3.3 V, VCM = VOUT = VS/2, CL = 20 pF, and RL≥ 10 MΩ, unless otherwise noted.
30
25
20
Number of Amplifiers
20
15
10
15
10
Offset Voltage PV)
VS = 1.8 V
TA = -40°C
VS = 1.8 V
4
3
2
1
0
-1
-2
5
TA = 25°C
30
25
15
10
20
15
10
5
0
0
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7
8
5
Offset Voltage (PV)
Offset Voltage (PV)
VS = 1.8 V
Offs
N = 98 units
TA = 125°C
VS = 3.3 V
25
20
20
Number of Amplifiers
25
15
10
Offs
N = 98 units
TA = -40°C
Figure 4. Offset Voltage Distribution, Vs = 3.3 V
Figure 3. Offset Voltage Distribution, Vs = 1.8 V
15
10
Offset Voltage (PV)
VS = 3.3 V
N = 98 units
0
5
4
3
2
1
0
-1
-2
-3
-4
5
-5
5
0
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7
8
Number of Amplifiers
20
Number of Amplifiers
1.8V
N = 98 units
Figure 2. Offset Voltage Distribution, Vs = 1.8 V
25
Number of Amplifiers
-3
Offset Voltage (PV)
Ofss
N = 98 units
Figure 1. Offset Voltage Distribution, Vs = 1.8 V
Offset Voltage (PV)
3.3V
TA = 25°C
Figure 5. Offset Voltage Distribution, Vs = 3.3 V
6
-4
0
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7
8
0
-5
5
5
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7
8
Number of Amplifiers
25
VS = 3.3 V
N = 98 units
offs
TA = 125°C
Figure 6. Offset Voltage Distribution, Vs = 3.3 V
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Typical Characteristics (continued)
30
24
27
21
24
Absolute VOS Drift (nV/qC)
1.8V
N = 98 units
VS = 3.3 V
Figure 7. Offset Voltage Drift Distribution, Vs = 1.8 V
60
55
50
45
40
35
30
25
60
55
50
45
40
35
30
25
20
0
15
0
5
3
10
6
3
Absolute VOS Drift (nV/qC)
3.3V
N = 98 units
Figure 8. Offset Voltage Drift Distribution, Vs = 3.3 V
1.6
+3 V
-3 V
+6 V
-6 V
1.4
1.2
1
0.8
VOS(PV)
VOS (PV)
9
6
VS = 1.8 V
16
14
12
10
8
6
4
2
0
-2
-4
-6
-8
-10
-12
-14
-16
-40
12
20
9
15
15
12
18
5
15
21
10
18
0
Number of Amplifiers
27
0
Number of Amplifiers
At TA = 25°C, VS = 3.3 V, VCM = VOUT = VS/2, CL = 20 pF, and RL≥ 10 MΩ, unless otherwise noted.
-40qC
25qC
125qC
0.6
0.4
0.2
0
-0.2
-0.4
-25
-10
5
VS = 3.3 V
20
35 50
Temp(C)
65
80
95
-0.6
1.6
110 125
1.8
2
2.2
Rawo
N = 98 units
2.4
2.6 2.8
Vs (V)
3
3.2
3.4
3.6
VOSv
TA = –40, 25,
125°C
Figure 9. Offset Voltage vs Temperature, Vs = 3.3 V
Gain
125 °C
25 °C
-40 °C
10
VS = 1.8 V
100
1k
Frequency (Hz)
CL = 20 pF
10k
120
105
90
75
60
45
30
15
0
-15
-30
-45
-60
-75
Phase
Gain
125 °C
25 °C
-40 °C
10
SNOS
TA = –40, 25, 125°C
Figure 11. Open-Loop Gain and Phase vs Frequency
VS = 3.3 V
100
1k
Frequency (Hz)
CL = 20 pF
10k
120
105
90
75
60
45
30
15
0
-15
-30
-45
-60
-75
100k
Phase ( R )
AOL (dB)
Phase
120
105
90
75
60
45
30
15
0
-15
-30
-45
-60
-75
100k
Phase ( R )
AOL (dB)
Figure 10. Offset Voltage vs Supply Voltage
120
105
90
75
60
45
30
15
0
-15
-30
-45
-60
-75
SNOS
TA = –40, 25, 125°C
Figure 12. Open-Loop Gain and Phase vs Frequency
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Typical Characteristics (continued)
2.5
3
2
2.5
1.5
Input Offset Voltage (PV)
Input Offset Voltage (PV)
At TA = 25°C, VS = 3.3 V, VCM = VOUT = VS/2, CL = 20 pF, and RL≥ 10 MΩ, unless otherwise noted.
1
0.5
0
-0.5
-1
Vos (µV) at 125 °C
Vos (µV) at 25 °C
Vos (µV) at -40 °C
-1.5
2
1.5
1
0.5
0
-0.5
-1
Vos (µV) at 125 °C
Vos (µV) at 25 °C
Vos (µV) at -40 °C
-1.5
-2
-2
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Common Mode Voltage (V)
1.6
1.8
0
0.9 1.2 1.5 1.8 2.1 2.4
Common Mode Voltage (V)
2.7
3
3.3
SNOS
Figure 13. Input Offset Voltage vs Input Common Mode
Voltage
Figure 14. Input Offset Voltage vs Input Common Mode
Voltage
50
50
40
40
30
30
20
10
0
-10
-20
-30
20
10
0
-10
-20
-30
Ibias (pA) @ 125 °C
Ibias (pA) at 25 °C
Ibias (pA) @ -40 °C
-40
Ibias (pA) at 25 °C
Ibias (pA) at -40 °C
Ibias (pA) at 125 °C
-40
-50
-50
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Common Mode Voltage (V)
1.6
1.8
0
0.5
SNOS
VS = 1.8 V
1
1.5
2
2.5
Common Mode Voltage (V)
3
3.5
SNOS
VS = 3.3 V
Figure 15. Input Bias Current on +IN Input Pin vs Common
Mode Voltage
Figure 16. Input Bias Current on +IN Input Pin vs Common
Mode Voltage
600
6000
Ibias (pA) at 125 °C
Ibias (pA) at 25 °C
Ibias (pA) at -40 °C
500
400
Ibias at 125 °C (pA)
Ibias at 25 °C (pA)
Ibias at -40 °C (pA)
5000
4000
300
Input Bias Current (pA)
Input Bias Current (pA)
0.6
VS = 3.3 V
Input Bias Current (pA)
Input Bias Current (pA)
VS = 1.8 V
200
100
0
-100
-200
-300
3000
2000
1000
0
-1000
-2000
-3000
-400
-4000
-500
-5000
-600
-6000
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Common Mode Voltage (V)
1.6
1.8
0
0.5
SNOS
VS = 1.8 V
1
1.5
2
2.5
Common Mode Voltage (V)
3
3.5
SNOS
VS = 3.3 V
Figure 17. Input Bias Current on –IN Pin vs Common Mode
Voltage
8
0.3
SNOS
Figure 18. Input Bias Current on –IN Input Pin vs Common
Mode Voltage
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Typical Characteristics (continued)
10
40
9
0
8
-40
Input Bias Current (pA)
Input Bias Current (pA)
At TA = 25°C, VS = 3.3 V, VCM = VOUT = VS/2, CL = 20 pF, and RL≥ 10 MΩ, unless otherwise noted.
7
6
5
4
3
2
Ibias (pA) at Vs = 3.3V
Ibias (pA) at Vs = 1.8V
1
0
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
-80
-120
-160
-200
-240
-320
-40
140
0
20
40
60
80
Temperature (qC)
100
120
140
SNOS
VS = 3.3 V and 1.8 V
Figure 19. Input Bias Current ON +IN Input vs Temperature
Figure 20. Input Bias Current on –IN Input Pin vs
Temperature
130
CMRR (dB) at Vs = 3.3V
CMRR (dB) at Vs = 1.8V
120
110
PSRR (dB)
CMRR (dB)
-20
SNOS
VS = 3.3 V and 1.8 V
140
130
120
110
100
90
80
70
60
50
40
30
20
10
10
Ibias (pA) at Vs = 1.8V
Ibias (pA) at Vs = 3.3V
-280
100
90
80
PSRR (dB) Vs = 3.3V
PSRR (dB) Vs = 1.8V
100
1k
70
10
10k
Frequency (Hz)
100
1k
Frequency (Hz)
SNOS
10k
100k
SNOS
VS = 3.3 V and 1.8
V
VS = 3.3 V and 1.8 V
Figure 21. CMRR vs Frequency
Figure 22. PSRR vs Frequency
120
100
EMIRR (dB)
80
60
40
EMIRR at 0dBm
EMIRR at -10dBm
EMIRR at -20dBm
20
0
10
100
Frequency (MHz)
Quiecent Current per Channel (nA)
1100
1000
900
800
700
600
500
400
300
100
1.5
1k
IQ (nA) at 125 °C
IQ (nA) at 25 °C
IQ (nA) at -40 °C
200
1.75
2
2.25
SNOS
2.5 2.75 3 3.25
Supply Voltage (V)
3.5
3.75
4
SNOS
TA = –40, 25, 125°C
Figure 23. EMIRR Performance
Figure 24. Per Channel Quiescent Current vs Supply
Voltage
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Typical Characteristics (continued)
At TA = 25°C, VS = 3.3 V, VCM = VOUT = VS/2, CL = 20 pF, and RL≥ 10 MΩ, unless otherwise noted.
140
Voltage Noise Density (nV/?Hz)
130
120
Zo (k:
110
100
90
80
70
60
Zout (k:) at 1.8V
Zout (k:) at 3.3V
50
40
10
100
1k
Frequency (Hz)
10k
100k
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
100m
1
10
100
1k
Frequency (Hz)
10k
100k
SNOS
SNOS
VS = 3.3 V and 1.8 V
Figure 26. Voltage Noise Spectral Density vs Frequency
1 PV/div
1 PV/div
Figure 25. Open Loop Output Impedance
1 s/div
1 s/div
Nois
Nois
VS = 3.3 V
VS = 1.8 V
Figure 28. 0.1-Hz to 10-Hz Noise, Vs = 1.8 V
10
1
1
Output Swing from V- (V)
Output Swing from V- (V)
Figure 27. 0.1-Hz to 10-Hz Noise, Vs = 3.3 V
10
100m
10m
1m
Vout (V) at 125 °C
Vout (V) at 25 °C
Vout (V) at -40 °C
100P
1m
10m
VS = 1.8 V
100m
1
Output Sinking Current (mA)
10
100
10m
1m
Vout (V) at 125 °C
Vout (V) at 25 °C
Vout (V) at -40 °C
100P
1m
SNOS
TA = –40, 25, 125°C
10m
100m
1
Output Sinking Current (mA)
VS = 3.3 V
Figure 29. Output Swing vs. Sinking Current, 1.8 V
10
100m
10
100
SNOS
TA = –40, 25, 125°C
Figure 30. Output Swing vs. Sinking Current, 3.3 V
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Typical Characteristics (continued)
10
10
1
1
Output Swing from V+ (V)
Output Swing from V+ (V)
At TA = 25°C, VS = 3.3 V, VCM = VOUT = VS/2, CL = 20 pF, and RL≥ 10 MΩ, unless otherwise noted.
100m
10m
1m
100m
10m
1m
Vout (V) at 125 °C
Vout (V) at 25 °C
Vout (V) at -40 °C
100P
1m
10m
VS = 1.8 V
100m
1
10
Output Sourcing Current (mA)
100
Vout (V) at 125 °C
Vout (V) at 25 °C
Vout (V) at -40 °C
100P
1m
10m
SNOS
TA = –40, 25, 125°C
VS = 3.3 V
100
SNOS
TA = –40, 25, 125°C
Figure 32. Output Swing vs Sourcing Current, 3.3 V
Output Voltage (500mV/div)
Output Voltage (500mV/div)
Figure 31. Output Swing vs Sourcing Current, 1.8 V
100m
1
10
Output Sourcing Current (mA)
Time (500 Ps/div)
Time (1ms/div)
Larg
VIN = 2.64 VPP
G=1
Larg
RL = 1 MΩ
VIN = 1.44 VPP
RL = 1 MΩ
Figure 34. Large-Signal Response, 1.8V
Output Voltage (50mV/div)
Output Voltage (50mV/div)
Figure 33. Large-Signal Response, 3.3V
G=1
Time (200 Ps/div)
Smal
VIN = 0.2 VPP
G=1
Time (200 Ps/div)
RL = 1 MΩ
Figure 35. Small Signal Response, 3.3V
Smal
VIN = 0.2 VPP
G=1
RL = 1 MΩ
Figure 36. Small-Signal Response, 1.8V
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8 Detailed Description
8.1 Overview
The LPV821 is a zero-drift, nanopower, rail-to-rail input and output operational amplifier. The device operates
from 1.7 V to 3.7 V, is unity-gain stable, and is suitable for a wide range of general-purpose applications. The
zero-drift architecture provides ultra low offset voltage and near-zero offset voltage drift.
8.2 Functional Block Diagram
V+
(AVDD)
OSC & Freq.
Divider
Chop1
+IN
POR
Chop2
Bias
Notch FLT
AVDD
AVDD
gm1
gm2
OUT
gm3
-IN
AVSS
AVSS
gm4
V- (AVSS)
8.3 Feature Description
The LPV821 is unity-gain stable and uses an auto-calibration technique to provide low offset voltage and very
low drift over time and temperature. For lowest offset voltage and precision performance, optimize circuit layout
and mechanical conditions. Avoid temperature gradients that create thermoelectric (Seebeck) effects in the
thermocouple junctions formed from connecting dissimilar conductors. Cancel these thermally-generated
potentials by assuring they are equal on both input terminals. Other layout and design considerations include:
• Use low thermoelectric-coefficient conditions (avoid dissimilar metals).
• Thermally isolate components from power supplies or other heat sources.
• Shield operational amplifier and input circuitry from air currents, such as cooling fans.
Following these guidelines reduces the likelihood of junctions being at different temperatures, which can
cause thermoelectric voltages of 0.1 μV/°C or higher, depending on materials used.
8.3.1 Operating Voltage
The LPV821 operational amplifier operates over a power-supply range of 1.7 V to 3.6 V (±0.85 V to ± 1.8 V).
Parameters that vary over supply voltage or temperature are shown in the Typical Characteristics section.
CAUTION
Supply voltages higher than 4 V (absolute maximum) can permanently damage the
device.
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Feature Description (continued)
8.3.2 Input
The LPV821 input common-mode voltage range extends to the supply rails. Typically, the input bias current is
approximately 7 pA; however, input voltages that exceed the power supplies can cause excessive current to flow
into or out of the input pins. Momentary voltages greater than the power supply can be tolerated if the input
current is limited to 10 mA. This limitation is easily accomplished with adding a resistor in series with the input,
as shown in Figure 37.
Vcc
Current-limiting resistor
required if input voltage
exceeds supply rails by
• 0.3 V.
VOUT
R1
VIN
+
10 mA max
Figure 37. Input Current Protection
8.3.3 Internal Offset Correction
The LPV821 operational amplifier combines an auto-calibration technique with a time-continuous 8-kHz
operational amplifier in the signal path. The amplifier's offset is zero-corrected every 1 ms using a proprietary
technique. This design has no aliasing or flicker (1/f) noise.
8.3.4 Input Offset Voltage Drift
The LPV821 operational amplifier's input voltage offset drift is defined over the entire temperature range of
–40°C to 125°C. The maximum input voltage drift allows designers to calculate the worst-case input offset
change over this temperature range. The maximum input voltage drift over temperature is defined using
Equation 1:
dVOS/dT = ΔVOS / ΔT
where
•
•
•
ΔVOS = Change in input offset voltage
ΔT = Change in temperature (125°C - (-40°C) = 165°C)
dVOS/dT = Input offset voltage drift
(1)
The LPV821 datasheet maximum value for input offset voltage drift is specified for a sample size with a Cpk
(process capability index) of 2.0.
8.4 Device Functional Modes
The LPV821 has a single functional mode. The device is powered on as long as the power supply voltage is
between 1.7 V (±0.85 V) and 3.6 V (±1.8 V).
8.4.1 EMI Performance and Input Filtering
Operational amplifiers vary in susceptibility to EMI. If conducted EMI enters the operational amplifier, the dc
offset at the amplifier output can shift from its nominal value when EMI is present. This shift is a result of signal
rectification associated with the internal semiconductor junctions. Although all operational amplifier pin functions
can be affected by EMI, the input pins are likely to be the most susceptible. The LPV821 operational amplifier
incorporates an internal input low-pass filter that reduces the amplifier response to EMI. Both common mode and
differential-mode filtering are provided by the input filter.
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Device Functional Modes (continued)
8.4.2 Driving Capacitive Load
The LPV821 is internally compensated for stable unity-gain operation, with a 8-kHz typical gain bandwidth.
However, the unity-gain follower is the most sensitive configuration-to-capacitive load. The combination of a
capacitive load placed directly on the output of an amplifier along with the output impedance of the amplifier
creates a phase lag, which reduces the phase margin of the amplifier. If the phase margin is significantly
reduced, the response is under-damped, which causes peaking in the transfer and, when there is too much
peaking, the op amp might start oscillating.
Vcc
RISO
VOUT
VIN
+
CL
Figure 38. Resistive Isolation of Capacitive Load
In order to drive heavy (> 50 pF) capacitive loads, use an isolation resistor, RISO, as shown in Figure 38. The
value of the RISO to be used should be decided depending on the size of the CLand the level of performance
desired. Recommended minimum values for RISO are given in the following table, for 3.3V supply. Figure 39
shows the typical response obtained with the CL = 50 pF RISO = 160 kΩ. By using the isolation resistor, the
capacitive load is isolated from the output of the amplifier. The larger the value of RISO, the more stable the
amplifier will be. If the value of RISO is sufficiently large, the feedback loop is stable, independent of the value of
CL. However, larger values of RISO (e.g. 50 kΩ) result in reduced output swing and reduced output current drive.
Table 1. Capacitive Loads vs. Needed Isolation Resistors
CL
RISO
0 – 20 pF
not needed
50 pF
160 kΩ
100 pF
140 kΩ
500 pF
54.9 kΩ
1 nF
33 kΩ
5 nF
15 kΩ
10 nF
5.62 kΩ
VIN
VOUT
Figure 39. Typical Step Response
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LPV821 is a unity-gain stable, precision operational amplifier with very low offset voltage drift; the device is
also free from output phase reversal. Applications with noisy or high-impedance power supplies require
decoupling capacitors close to the device power-supply pins. In most cases, 0.1-μF capacitors are adequate.
9.2 Typical Applications
9.2.1
Low-Side Current Measurement
This single-supply, low-side, current-sensing solution shown in Figure 40 detects load currents up to 1 A. This
design uses the LPV821 because of its low offset voltage and rail-to-rail input and output. The LPV821 in the
main signal path is configured as a difference amplifier and a second LPV821 provides a buffered bias voltage to
allow transition of signal below and above the bias level for bi-direction current sensing. The low offset voltage
and offset drift of the LPV821 facilitate excellent dc accuracy for the circuit.
V Supply
load
Current
R4
LOAD
Vcc
R3
+
Vshunt
LPV821
Rshunt
Vbias
VOUT
+
Vcc
R1
R5
R2
Vcc
R6
To ADC REF
input
LPV821
+
Figure 40. Low-Side Current Measurement
9.2.1.1 Design Requirements
The design requirements are as follows:
• Supply Voltage: 3.3 V DC
• Input: 1 A (Max)
• Output: 1.65V ± 1.54 V ; (110 mV to 3.19 V)
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Typical Applications (continued)
9.2.1.2 Detailed Design Procedure
Referring to Figure 40, the load current passing though the shunt resistor (Rshunt) develops the shunt voltage,
Vshunt across the resistor. The shunt voltage is then amplified by the LPV821 by the ratio of R4 by R3 . The gain
of the difference amplifier is set by the ratio of R4 to R3 . To minimize errors, set R2 = R4 and R1 = R3 . The
bias voltage is supplied by buffering a resistor divider using a second LPV821 nanopower op amp. The circuit
equations are provided below.
Vout = Vshunt * Gain Diff + Vbias
Vshunt = Iload * Rshunt
GainDiff = R4 / R3
Vbias = [R6 / (R6 + R5)] * VCC
Rshunt = [Vshunt (max)] / [Iload (max)]
(2)
(3)
(4)
(5)
(6)
Because Vshunt is a low-side measurement, a maximum value 100 mV was selected.
Rshunt= Vshunt/ Iload= 100mV /1A =100mΩ
(7)
The tolerance of the shunt resistor, the ratio of R4 to R3 and the ratio of R2 to R1 are the main sources of gain
error in the signal path. To optimize the cost, a shut resistor with a tolerance of 0.5% was chosen. The main
sources of offset errors in the circuit are the voltage divider network comprise of R5, R6 and how closely the ratio
of R4 / R3 matches the ration of R2 / R1. The latter value affects the CMRR of the difference amplifier, ultimately
translating to an offset error.
The shunt voltage is scaled down by a divider network made of R1 and R2 before reaching the LPV821 amplifier
stage. The voltage present at the non-inverting node of the LPV821 should not exceed the common-mode range
of the device. The extremely low offset voltage and drift of the LPV821 ensures minimized offset error in the
measurement.
In case a bi-direction current sensing is required, for symmetric load current of –1 A to 1 A, the voltage divider
resistors R5 and R6 must be equal. To minimize power consumption, 100-kΩ resistors with a tolerance of 0.5%
were selected.
To set the gain of the difference amplifier, the common-mode range and output swing of the LPV821 must be
considered. The gain of the difference amplifier can now be calculated as shown below
Gain = [Vout (max) - Vout (min)] / [Rshunt * (Imax – Imin )] = [3.2 V - 100 mV] / [100 mΩ] * [1A – ( –1A)] = 15.5 V / V
(8)
10 Power Supply Recommendations
The LPV821 is specified for operation from 1.7 V to 3.6 (±0.85 V to ±1.8 V); many specifications apply from
–40°C to 125°C. The Typical Characteristics presents parameters that can exhibit significant variance with regard
to operating voltage or temperature.
CAUTION
Supply voltages larger than 4 V can permanently damage the device (see the Absolute
Maximum Ratings).
TI recommends placing 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in
from noisy or high-impedance power supplies. For more detailed information on bypass capacitor placement,
refer to the Layout section.
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11 Layout
11.1 Layout Guidelines
11.1.1 General Layout Guidelines
Pay attention to good layout practices. Keep traces short and when possible, use a printed-circuit-board (PCB)
ground plane with surface-mount components placed as close to the device pins as possible. Place a 0.1-μF
capacitor closely across the supply pins. Apply these guidelines throughout the analog circuit to improve
performance and provide benefits, such as reducing the electromagnetic interference (EMI) susceptibility.
Operational amplifiers vary in susceptibility to radio frequency interference (RFI). RFI can generally be identified
as a variation in offset voltage or DC signal levels with changes in the interfering RF signal. The LPV821 is
specifically designed to minimize susceptibility to RFI and demonstrates remarkably low sensitivity compared to
previous generation devices. Strong RF fields may still cause varying offset levels.
11.2 Layout Example
Figure 41. SOT-23 Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
TINA-TI SPICE-Based Analog Simulation Program
DIP Adapter Evaluation Module
TI Universal Operational Amplifier Evaluation Module
TI FilterPro Filter Design Software
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LPV821
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LPV821DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1CHF
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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