LSF0101, LSF0102, LSF0108
LSF0101,
LSF0102,
SDLS966K – DECEMBER
2013
– REVISEDLSF0108
MAY 2021
SDLS966K – DECEMBER 2013 – REVISED MAY 2021
www.ti.com
LSF010x 1/2/8 Channel Auto-Bidirectional Multi-Voltage Level Translator for OpenDrain and Push-Pull Applications
1 Features
3 Description
•
The LSF family of devices supports bidirectional
voltage translation without the need for DIR pin which
minimizes system effort (for PMBus, I2C, SMBus,
etc.). The LSF family of devices supports up to 100MHz up translation and greater than 100-MHz down
translation at ≤ 30pF cap load and up to 40-MHz
up/down translation at 50pF cap load which allows
the LSF family to support more consumer or telecom
interfaces (MDIO or SDIO).
Device Information
2 Applications
•
•
•
•
•
GPIO, MDIO, PMBus, SMBus, SDIO, UART, I2C,
and other interfaces in telecom infrastructure
Enterprise systems
Communications equipment
Personal electronics
Industrial applications
LSF0101DRY
SON (6)
1.45 mm × 1.00 mm
X2SON (6)
1.00 mm x 0.80 mm
LSF0102DQE
X2SON (8)
1.40 mm × 1.00 mm
LSF0102YZT
DSBGA (8)
1.90 mm × 1.00 mm
LSF0102DCT
SM8 (8)
2.80 mm × 2.95 mm
LSF0102DCU
VSSOP (8)
2.30 mm × 2.00 mm
LSF0108RKS
VQFN (20)
4.50 mm × 2.50 mm
LSF0108PW
TSSOP (20)
4.40 mm × 6.50 mm
(1)
Vref_A
6
2
Vref_B
5
3
4
A1
B1
YZT Package
8-Pin DSBGA
Bottom View
LSF0108
DQE Package
8-Pin X2SON
Transparent Top View
RKS Package
20-Pin VQFN
Transparent Top View
GND EN
GND EN
1
For all available packages, see the orderable addendum at
the end of the data sheet.
LSF0102
DRY Package
6-Pin SON
Transparent Top View
BODY SIZE (NOM)
LSF0101DTQ
LSF0101
DTQ Package
6-Pin X2SON
Transparent Top View
PACKAGE(PINS)(1)
PART NUMBER
GND
1
6
EN
A2
D1
D2
B2
Vref_A
2
5
Vref_B
A1
C1
C2
B1
A1
3
4
B1
Vref_A
A1
B2
A2
Vref_B
1
8
2
7
3
6
4
5
EN
EN
Vref_B
B1
B2
Vref_A
2
19
Vref_B
A1
3
18
B1
A2
4
17
B2
A3
5
16
B3
A4
6
15
B4
A5
7
14
B5
A6
8
13
B6
A7
9
12
B7
Thermal
Pad
10
GND
B1
GND
Vref_A
A1
A2
1
•
•
•
•
•
•
•
LSF family supports 5-V tolerance on I/O port which
makes it compatible with TTL levels in industrial and
telecom applications. The LSF family is able to set
up different voltage translation levels on each channel
which makes it very flexible.
20
•
11
•
Provides bidirectional voltage translation with no
direction pin
Supports up to 100-MHz up translation and greater
than 100-MHz down translation at
≤ 30pF cap load and up To 40-MHz up/down
translation at 50pF cap load
Allows bidirectional voltage-level translation
between
– 0.95 V ↔ 1.8/2.5/3.3/5 V
– 1.2 V ↔ 1.8/2.5/3.3/5 V
– 1.8 V ↔ 2.5/3.3/5 V
– 2.5 V ↔ 3.3/5 V
– 3.3 V ↔ 5 V
Low standby current
5-V tolerance I/O port to support TTL
Low RON provides less signal distortion
High-impedance I/O pins for EN = Low
Flow-through pinout for easy PCB trace routing
Latch-up performance >100 mA per JESD 17
–40°C to 125°C Operating temperature range
A8 B8
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2021 Texas Instruments
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intellectual property matters and other important disclaimers. PRODUCTION DATA.
Product Folder Links: LSF0101 LSF0102 LSF0108
1
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SDLS966K – DECEMBER 2013 – REVISED MAY 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information: LSF0101, LSF0108...................6
6.5 Thermal Information: LSF0102................................... 6
6.6 Electrical Characteristics.............................................6
6.7 LSF0101/02 AC Performance (Translating
Down) Switching Characteristics , VGATE = 3.3 V..........7
6.8 LSF0108 AC Performance (Translating Down)
Switching Characteristics, VGATE = 3.3 V...................... 7
6.9 LSF0101/02 AC Performance (Translating
Down) Switching Characteristics, VGATE = 2.5 V...........7
6.10 LSF0108 AC Performance (Translating Down)
Switching Characteristics, VGATE = 2.5 V...................... 7
6.11 LSF0101/02 AC Performance (Translating Up)
Switching Characteristics, VGATE = 3.3 V...................... 7
6.12 LSF0108 AC Performance (Translating Up)
Switching Characteristics, VGATE = 3.3 V...................... 7
6.13 LSF0101/02 AC Performance (Translating Up)
Switching Characteristics, VGATE = 2.5 V...................... 8
6.14 LSF0108 AC Performance (Translating Up)
Switching Characteristics, VGATE = 2.5 V...................... 8
6.15 Typical Characteristics.............................................. 8
7 Parameter Measurement Information............................ 9
8 Detailed Description......................................................10
8.1 Overview................................................................... 10
8.2 Functional Block Diagrams....................................... 10
8.3 Feature Description...................................................11
8.4 Device Functional Modes..........................................12
9 Application and Implementation.................................. 12
9.1 Application Information............................................. 12
9.2 Typical Applications.................................................. 13
10 Power Supply Recommendations..............................17
11 Layout........................................................................... 17
11.1 Layout Guidelines................................................... 17
11.2 Layout Example...................................................... 17
12 Device and Documentation Support..........................18
12.1 Related Links.......................................................... 18
12.2 Receiving Notification of Documentation Updates..18
12.3 Support Resources................................................. 18
12.4 Trademarks............................................................. 18
12.5 Electrostatic Discharge Caution..............................18
12.6 Glossary..................................................................18
13 Mechanical, Packaging, and Orderable
Information.................................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision J (April 2020) to Revision K (May 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document .................1
• Updated the Bidirectional Translation section to include inclusive terminology................................................13
Changes from Revision I (June 2019) to Revision J (April 2020)
Page
• Added section Voltage Translation for Vref_B < Vref_A + 0.8 V ......................................................................16
Changes from Revision H (June 2019) to Revision I (July 2019)
Page
• Changed product status from Advance Information mix to Production Data ..................................................... 1
• Deleted Advance Information note from the DTQ package in the Device Information table. ............................ 1
• Deleted Advance Information note from DTQ package in the Pin Configuration and Functions section. ..........4
• Deleted Advance Information note for the DTQ package in the Thermal Information table. ............................. 6
Changes from Revision G (February 2016) to Revision H (June 2019)
Page
• Added Advance Information note to Device Information table for DTQ package .............................................. 1
• Added DTQ6 pinout drawing to Pin Configurations and Functions section (Advance Information)....................4
• Added Advance Information note to LSF0101 Thermal Information table. ........................................................6
• General improvements to Application and Implementation section for clarity. ................................................ 12
Changes from Revision F (October 2015) to Revision G (October 2015)
Page
• Added all available package dimensions in Device Information and changed the pin diagram description....... 1
2
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SDLS966K – DECEMBER 2013 – REVISED MAY 2021
Changes from Revision E (July 2015) to Revision F (October 2015)
Page
• Changed Features from "Supports High Speed Translation, Greater Than 100 MHz" to "Supports Up to 100
MHz Up Translation and Greater Than 100 MHz Down Translation at ≤ 30pF Cap Load and Up To 40 MHz
Up/Down Translation at 50 pF Cap Load." ........................................................................................................ 1
• Updated all propagation delay tables changed from generic to specific LSF devices. ......................................7
Changes from Revision D (October 2014) to Revision E (July 2015)
Page
• Deleted "Less Than 1.5 ns Max Propagation Delay" from Features. ................................................................ 1
• Updated ESD Ratings table. ..............................................................................................................................5
• Increased MAX value for TA, Operating free-air temperature, from 85°C to 125°C............................................5
Changes from Revision C (May 2014) to Revision D (August 2014)
Page
• Changed bidirectional voltage level translation from 1.0 to 0.95 ....................................................................... 1
• Changed YZT package to fix view error. ............................................................................................................1
• Changed YZT package to fix view error. ............................................................................................................4
• Added Vref_A footnote......................................................................................................................................13
Changes from Revision B (May 2014) to Revision C (May 2014)
Page
• Changed LSF0108 status from preview to production........................................................................................1
• Updated document title. .....................................................................................................................................1
• Updated Handling Ratings table. ....................................................................................................................... 5
Changes from Revision A (January 2014) to Revision B (February 2014)
Page
• Added LSF0108 to data sheet. .......................................................................................................................... 1
Changes from Revision * (December 2013) to Revision A (January 2014)
Page
• Updated part number.......................................................................................................................................... 1
• Updated Electrical Characteristics table............................................................................................................. 6
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SDLS966K – DECEMBER 2013 – REVISED MAY 2021
5 Pin Configuration and Functions
Pinout drawings are not to scale.
GND
1
GND
1
6
EN
Vref_A
2
5
Vref_B
3
4
B1
2
Vref_A
A1
Vref_B
4
B1
Figure 5-2. LSF0101 DTQ Package 6-Pin X2SON
Transparent Top View
EN
GND
1
8
Vref_A
2
7
Vref_B
B1
A1
3
6
B1
B2
A2
4
5
B2
EN
Vref_B
A2
5
3
A1
Figure 5-1. LSF0101 DRY Package 6-Pin SON
Transparent Top View
GND
Vref_A
A1
EN
6
Figure 5-4. LSF0102 DQE Package 8-Pin X2SON
Transparent Top View
Figure 5-3. LSF0102 DCT or DCU Package 8-Pin
SM8 or VSSOP Top View
A2
A1
Vref_A
GND
D1
4
5
D2
C1
3
6
C2
B1
2
7
B2
A1
1
8
A2
B2
B1
Vref_B
EN
Figure 5-5. LSF0102 YZT Package 8-Pin DSBGA Bottom View
GND EN
20 EN
19 Vref_B
2
19
Vref_B
A1
3
18
B1
A2 4
A3 5
17 B2
16 B3
A2
4
17
B2
A3
5
16
B3
A4 6
A5 7
A6 8
A7 9
15 B4
14 B5
A4
6
15
B4
A5
7
14
B5
13 B6
A6
8
13
B6
12 B7
11 B8
A7
9
12
B7
11
Thermal
Pad
10
A8 10
1
Vref_A
18 B1
20
GND 1
Vref_A 2
A1 3
A8 B8
Figure 5-6. LSF0108 PW Package 20-Pin TSSOP
Top View
Figure 5-7. LSF0108 RKS Package 20-Pin VQFN
Transparent Top View
Pin Functions
PIN
4
I/O
DESCRIPTION
DCT, DCU, DQE,
YZT NO.
DRY, DTQ
NO.
An
3, 4
3
3 to 10
I/O
Bn
6, 5
4
18 to 11
I/O
EN
8
6
20
I
GND
1
1
1
—
Ground
Vref_A
2
2
2
—
Vref_B
7
5
19
—
Reference supply voltage.
For proper device biasing, see Section 9 and Understanding the
Bias Circuit for the LSF Family.
NAME
PW or RKS NO.
Auto-Bidirectional Data port
Enable input; connect to Vref_B and pull-up through a high resistor
(200 kΩ). See Using the Enable Pin with the LSF Family
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SDLS966K – DECEMBER 2013 – REVISED MAY 2021
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted)(1)
Input voltage(2)
VI
VI/O
Input/output
voltage(2)
MIN
MAX
UNIT
–0.5
7
V
–0.5
Continuous channel current
IIK
Input clamp current
TJ
Junction Temperature
Tstg
Storage temperature range
(1)
(2)
VI < 0
–65
7
V
128
mA
–50
mA
150
°C
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and input/output negative-voltage ratings may be exceeded if the input and input/output clamp-current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VI/O
Input/output voltage
0
5
V
Vref_A/B/EN
Reference voltage
0
5
V
IPASS
Pass transistor current
64
mA
TA
Operating free-air temperature
–40
125
°C
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SDLS966K – DECEMBER 2013 – REVISED MAY 2021
6.4 Thermal Information: LSF0101, LSF0108
LSF0101
THERMAL METRIC(1)
LSF0108
DTQ (X2SON)
DRY (SON)
RKS (VQFN)
PW (TSSOP)
UNIT
6 PINS
6 PINS
20 PINS
20 PINS
RθJA
Junction-to-ambient thermal resistance
294.4
407.0
49.3
106.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
188.9
285.2
45.9
41.0
°C/W
RθJB
Junction-to-board thermal resistance
216.8
271.6
20.6
57.6
°C/W
ψJT
Junction-to-top characterization parameter
26.5
113.5
2.5
4.2
°C/W
ψJB
Junction-to-board characterization parameter
216.0
271.0
20.6
47.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
3.4
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Thermal Information: LSF0102
LSF0102
THERMAL
METRIC(1)
DCU (US8)
DCT (SM8)
DQE (X2SON)
YZT (DSBGA)
8 PINS
8 PINS
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
210.1
189.6
246.5
125.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
89.1
119.6
149.1
1.0
°C/W
RθJB
Junction-to-board thermal resistance
88.8
102.1
100.0
62.7
°C/W
ψJT
Junction-to-top characterization parameter
8.3
44.5
17.1
3.4
°C/W
ψJB
Junction-to-board characterization parameter
88.4
101.0
99.8
62.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.6 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
TEST CONDITIONS
II = –18 mA,
VEN = 0
IIH
VI = 5 V
VEN = 0
ICC
Vref_B = VEN = 5.5 V, Vref_A = 4.5 V or 1 V, IO = 0, VI = VCC or GND
CI(ref_A/B/EN)
VI = 3 V or 0
Cio(off)
VO = 3 V or 0,
VEN = 0
Cio(on)
VO = 3 V or 0,
VEN = 3 V
VI = 0,
ron (2)
MIN
TYP(1)
MAX
UNIT
–1.2
V
5.0
µA
1
µA
11
IO = 64 mA
VI = 0,
IO = 32 mA
VI = 1.8 V,
IO = 15 mA
pF
4.0
6.0
pF
10.5
12.5
pF
Vref_A = 3.3 V; Vref_B = VEN = 5 V
8.0
Vref_A = 1.8 V; Vref_B = VEN = 5 V
9.0
Ω
Vref_A = 1.0 V; Vref_B = VEN = 5 V
10
Vref_A = 1.8 V; Vref_B = VEN = 5 V
10
Vref_A = 2.5 V; Vref_B = VEN = 5 V
15
Vref_A = 3.3 V; Vref_B = VEN = 5 V
9.0
Ω
Ω
VI = 1.0 V,
IO = 10 mA
Vref_A = 1.8 V; Vref_B = VEN = 3.3 V
18
Ω
VI = 0 V,
IO = 10 mA
Vref_A = 1.0 V; Vref_B = VEN = 3.3 V
20
Ω
VI = 0 V,
IO = 10 mA
Vref_A = 1.0 V; Vref_B = VEN = 1.8 V
30
Ω
(1)
All typical values are at TA = 25°C.
(2)
Measured by the voltage drop between the A and B pins at the indicated current through the switch. On-state resistance is determined
by the lowest voltage of the two (A or B) pins.
6
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6.7 LSF0101/02 AC Performance (Translating Down) Switching Characteristics , VGATE = 3.3 V
over recommended operating free-air temperature range, VGATE = 3.3 V, VIH = 3.3 V, VIL = 0, and VM = 1.15 V (unless
otherwise noted) (see Figure 7-1)
PARAMETER
tPLH
tPHL
FROM (INPUT)
TO (OUTPUT)
A or B
B or A
CL = 50 pF
TYP
MAX
CL = 30 pF
CL = 15 pF
TYP
TYP
MAX
1.1
0.7
0.3
1.2
0.8
0.4
MAX
UNIT
ns
6.8 LSF0108 AC Performance (Translating Down) Switching Characteristics, VGATE = 3.3 V
over recommended operating free-air temperature range, VGATE = 3.3 V, VIH = 3.3 V, VIL = 0, and VM = 1.15 V (unless
otherwise noted) (see Figure 7-1)
PARAMETER
tPLH
tPHL
FROM (INPUT)
TO (OUTPUT)
A or B
B or A
CL = 50 pF
TYP
MAX
CL = 30 pF
CL = 15 pF
TYP
TYP
MAX
1.9
1.4
0.75
2
1.5
0.85
MAX
UNIT
ns
6.9 LSF0101/02 AC Performance (Translating Down) Switching Characteristics, VGATE = 2.5 V
over recommended operating free-air temperature range, VGATE = 2.5 V, VIH = 2.5 V, VIL = 0, and VM = 0.75 V (unless
otherwise noted) (see Figure 7-1)
PARAMETER
tPLH
tPHL
FROM (INPUT)
TO (OUTPUT)
A or B
B or A
CL = 50 pF
TYP
MAX
CL = 30 pF
CL = 15 pF
TYP
TYP
MAX
1.2
0.8
0.35
1.3
1
0.5
MAX
UNIT
ns
6.10 LSF0108 AC Performance (Translating Down) Switching Characteristics, VGATE = 2.5 V
over recommended operating free-air temperature range, VGATE = 2.5 V, VIH = 2.5 V, VIL = 0, and VM = 0.75 V (unless
otherwise noted) (see Figure 7-1)
PARAMETER
tPLH
tPHL
FROM (INPUT)
TO (OUTPUT)
A or B
B or A
CL = 50 pF
TYP
MAX
CL = 30 pF
CL = 15 pF
TYP
TYP
MAX
2
1.45
0.8
2.1
1.55
0.9
MAX
UNIT
ns
6.11 LSF0101/02 AC Performance (Translating Up) Switching Characteristics, VGATE = 3.3 V
over recommended operating free-air temperature range, VGATE = 3.3 V, VIH = 2.3 V, VIL = 0, VT = 3.3 V, VM = 1.15 V and RL
= 300 (unless otherwise noted) (see Figure 7-1)
PARAMETER
tPLH
tPHL
FROM (INPUT)
TO (OUTPUT)
A or B
B or A
CL = 50 pF
TYP
MAX
CL = 30 pF
CL = 15 pF
TYP
TYP
MAX
1
0.8
0.4
1
0.9
0.4
MAX
UNIT
ns
6.12 LSF0108 AC Performance (Translating Up) Switching Characteristics, VGATE = 3.3 V
over recommended operating free-air temperature range, VGATE = 3.3 V, VIH = 2.3 V, VIL = 0, VT = 3.3 V, VM = 1.15 V and RL
= 300 (unless otherwise noted) (see Figure 7-1)
PARAMETER
tPLH
tPHL
FROM (INPUT)
TO (OUTPUT)
A or B
B or A
CL = 50 pF
TYP
MAX
CL = 30 pF
CL = 15 pF
TYP
TYP
MAX
2.1
1.55
0.9
2.2
1.65
1
MAX
UNIT
ns
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6.13 LSF0101/02 AC Performance (Translating Up) Switching Characteristics, VGATE = 2.5 V
over recommended operating free-air temperature range, VGATE = 2.5 V, VIH = 1.5 V, VIL = 0, VT = 2.5 V, VM = 0.75 V and RL
= 300 (unless otherwise noted) (see Figure 7-1)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
A or B
B or A
tPLH
tPHL
CL = 50 pF
TYP
MAX
CL = 30 pF
CL = 15 pF
TYP
TYP
MAX
1.1
0.9
0.45
1.3
1.1
0.6
MAX
UNIT
ns
6.14 LSF0108 AC Performance (Translating Up) Switching Characteristics, VGATE = 2.5 V
over recommended operating free-air temperature range, VGATE = 2.5 V, VIH = 1.5 V, VIL = 0, VT = 2.5 V, VM = 0.75 V and RL
= 300 (unless otherwise noted) (see Figure 7-1)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
A or B
B or A
tPLH
tPHL
CL = 50 pF
TYP
MAX
CL = 30 pF
CL = 15 pF
TYP
TYP
MAX
1.8
1.35
0.8
1.9
1.45
0.9
MAX
UNIT
ns
6.15 Typical Characteristics
4.0
Input
Output
3.5
3.0
Voltage (V)
2.5
2.0
1.5
1.0
0.5
0.0
±0.5
0
5
10
15
20
Time (ns)
C005
Figure 6-1. Signal Integrity (1.8 to 3.3 V Up Translation at 50 MHz)
8
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7 Parameter Measurement Information
VT
RL
USAGE
SWITCH
Translating up
Translating down
S1
S2
S1
Open
From Output
Under Test
S2
3.3 V
Input
VM
VM
VIL
CL
(see Note A)
5V
Output
VM
VM
LOAD CIRCUIT
VOL
TRANSLATING UP
5V
Input
VM
VM
VIL
2V
Output
VM
VM
VOL
TRANSLATING DOWN
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
C. The outputs are measured one at a time, with one transition per measurement.
Figure 7-1. Load Circuit for Outputs
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8 Detailed Description
8.1 Overview
The LSF family can be used in level-translation applications for interfacing devices or systems operating with
one another, that operate at different interface voltages. The LSF family is ideal for use in applications where an
open-drain driver is connected to the data I/Os. With appropriate pull-up resistors and layout, LSF can achieve
100 MHz. The LSF family can also be used in applications where a push-pull driver is connected to the data
I/Os. For an overview of device setup and operation, see The Logic Minute training series on Understanding the
LSF Family of Bidirectional, Multi-Voltage Level Translators.
8.2 Functional Block Diagrams
Vref_A
2
A1 3
Vref_B
LSF0101
5
6 EN
4 B1
SW
1
GND
Figure 8-1. LSF0101 Functional Block Diagram
Vref_A
2
A1 3
A2 4
Vref_B
LSF0102
7
SW
SW
8 EN
6 B1
5 B2
1
GND
Figure 8-2. LSF0102 Functional Block Diagram
10
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Vref_B
Vref_A
19
2
LSF0108
B1
SW
4
A2
17
B2
SW
5
A3
16
B3
SW
6
A4
15
B4
SW
14
7
A5
B5
SW
8
A6
13
B6
SW
9
A7
12
B7
SW
10
A8
EN
18
3
A1
20
11
SW
B8
1
GND
Figure 8-3. LSF0108 Functional Block Diagram
8.3 Feature Description
8.3.1 Auto Bidirectional Voltage Translation
All devices in the LSF family are auto bidirectional voltage level translators that are operational from 0.95 to 4.5
V on the Vref_A supply and from 1.8 to 5.5 V on the Vref_B supply. This allows bidirectional voltage translation
between 0.95 V and 5.5 V without the need for a direction pin in open-drain or push-pull applications. LSF family
supports level translation applications with transmission speeds greater than 100 Mbps for open-drain systems
using a 30-pF capacitance and 250-Ω pullup resistor. For additional details on the recommended setup and
operation of the LSF family of devices, see the Understanding the LSF Family of Bidirectional, Multi-Voltage
Level Translators training series.
8.3.2 Output Enable
To enable the I/O pins, the EN input should be tied directly to Vref_B during operation. To ensure the high
impedance state during power-up, power-down, or during operation, the EN pin must be LOW. The EN pin
should always be tied directly to the Vref_B pin and is recommended to be disabled by an open-drain driver
without a pullup resistor. For additional details on how to use the enable pin, see the Using the Enable Pin with
the LSF Family video.
Table 8-1. Enable Pin Function Table
(1)
INPUT EN(1) PIN
Data Port State
Tied directly to Vref_B
An = Bn
L
Hi-Z
EN is controlled by Vref_B logic levels.
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8.4 Device Functional Modes
For each channel (n), when either the An or Bn port is LOW, the switch provides a low impedance path between
the An and Bn ports; the corresponding Bn or An port will be pulled LOW. The low RON of the switch allows
connections to be made with minimal propagation delay and signal distortion.
When the signal is being driven from Bn to An and the Bn port is driven HIGH, the switch will be OFF, clamping
the voltage on the An port to the voltage set by Vref_A. When the signal is being driven from A to B and the An
port is HIGH, the switch will be OFF and the Bn port will then driven to a voltage higher than Vref_A by the pullup
resistor that is connected to the pull-up supply voltage (Vpu#). This functionality allows seamless translation
between higher and lower voltages selected by the user, without the need for directional control.
Refer to Table 8-1 for a summary of device operation. For additional details on the functional operation of the
LSF family of devices, see the Down Translation with the LSF Family and Up Translation with the LSF Family
videos.
Table 8-2. Device Functionality
Signal Direction(1)
Input State
Switch State
Functionality
B = LOW
ON
(Low Impedance)
A-side voltage is pulled low through the switch to the B-side voltage
B = HIGH
OFF
(High Impedance)
A-side voltage is clamped at Vref_A (2)
A = LOW
ON
(Low Impedance)
B-side voltage is pulled low through the switch to the A-side voltage
A = HIGH
OFF
(High Impedance)
B-side voltage is clamped at Vref_A and then pulled up to the Vpu#
supply voltage
B to A (Down Translation)
A to B (Up Translation)
(1)
(2)
The downstream channel should not be actively driven through a low impedance driver, or else there may be bus contention.
The A-side can have a pullup to Vref_A for additional current drive capability or may also be pulled above Vref_A with a pullup resistor.
Specifications in the Section 6.3 should always be followed.
9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The LSF devices are able to perform voltage translation for open-drain or push-pull interfaces. Table 9-1
provides common interfaces and the corresponding device recommendation from the LSF family which supports
the corresponding bit count.
Table 9-1. Voltage Translator for Common Interfaces
12
Part Name
Channel Number
LSF0101
1
GPIO
Interface
LSF0102
2
GPIO, MDIO, SMBus, PMBus, I2C
LSF0108
8
GPIO, MDIO, SDIO, SVID, UART, SMBus, PMBus, I2C, SPI
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9.2 Typical Applications
9.2.1 Open-Drain Interface (I2C, PMBus, SMBus, GPIO)
3.3V enable signal
ON
Vref(A) = 1.8V
Off
Vref_A
2
Rpu
Rpu
Vcc
A1 3
MDIO
A2 4
MDC
Vpu = 3.3V
200KΩ
Vref_B
LSF0102
7
SW
SW
8 EN
Rpu
Rpu
Vcc
6 B1
MDIO
5 B2
MDC
1
GND
GND
GND
Figure 9-1. Typical Application Circuit for Open-Drain Translation (MDIO shown as an example)
9.2.1.1 Design Requirements
9.2.1.1.1 Enable, Disable, and Reference Voltage Guidelines
The LSF family has an EN input that is used to disable the device by setting EN LOW, placing all I/Os
in the high-impedance state. Since the LSF family of devices are switch-type voltage translators, the power
consumption is very low. TI recommends always enabling the LSF family for bidirectional applications (I2C,
SMBus, PMBus, or MDIO).
Table 9-2. Application Operating Condition
PARAMETER
MIN
TYP
MAX
UNIT
Vref_A(1)
reference voltage (A)
0.95
4.5
V
Vref_B
reference voltage (B)
Vref_A + 0.8
5.5
V
VI(EN)
input voltage on EN pin
Vref_A + 0.8
5.5
V
Vpu
pull-up supply voltage
0
Vref_B
V
(1)
Vref_A is required to be the lowest voltage level across all inputs and outputs.
The 200 kΩ, pull-up resistor is required to allow Vref_B to regulate the EN input and properly bias the
device for translation. For additional details on device biasing, see the Understanding the Bias Circuit for the
LSF Family video. A filter capacitor on Vref_B is recommended. Also Vref_B and VI(EN) are recommended to be
1.0 V higher than Vref_A for best signal integrity.
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Bidirectional Translation
For the bidirectional translation configuration (higher voltage to lower voltage or lower voltage to higher voltage),
the EN input must be connected to Vref_B and both pins must be pulled up to the HIGH side Vpu through a
pull-up resistor (typically 200 kΩ). This allows Vref_B to regulate the EN input and bias the channels for proper
translation. A filter capacitor on Vref_B is recommended for a stable supply at the device. The controller output
driver can be push-pull or open-drain (pull-up resistors may be required) and the peripheral device output can be
push-pull or open-drain (pull-up resistors are required to pull the Bn outputs to Vpu).
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If either output is push-pull, data must be unidirectional or the outputs must be tri-state and be
controlled by some direction-control mechanism to prevent HIGH-to-LOW bus contention in either
direction. If both outputs are open-drain, no direction control is needed.
When Vref_B is connected through a 200-kΩ resistor to a 3.3-V Vpu power supply and Vref_A is set 1.8 V, as
shown in Figure 9-1, the A1 and A2 channels have a maximum output voltage equal to Vref_A, and the B1 and
B2 channels have has a maximum output voltage equal to Vpu.
9.2.1.2.2 Pull-up Resistor Sizing
The pull-up resistor value needs to limit the current through the pass transistor when it is in the ON state to
about 15 mA. This ensures a voltage drop of 260 mV to 350 mV to have a valid LOW signal on the downstream
channel. If the current through the pass transistor is higher than 15 mA, the voltage drop is also higher in the
ON state. To set the current through each pass transistor at 15 mA, calculate the pull-up resistor value using the
following equation:
Rpu = (Vpu – 0.35 V) / 0.015 A
(1)
Table 9-3 summarizes resistor values, reference voltages, and currents at 15 mA, 10 mA, and 3 mA. The resistor
value shown in the +10% column (or a larger value) should be used to ensure that the voltage drop across the
transistor is 350 mV or less. The external driver must be able to sink the total current from the resistors on both
sides of the LSF family device at 0.175 V, although the 15 mA applies only to current flowing through the LSF
family device.
Table 9-3. Pull-up Resistor Values
15 mA
VDPU (1) (2)
(1)
(2)
(3)
10 mA
3 mA
NOMINAL (Ω)
+10%(3) (Ω)
NOMINAL (Ω)
+10%(3) (Ω)
NOMINAL (Ω)
+10%(3) (Ω)
5V
310
341
465
512
1550
1705
3.3 V
197
217
295
325
983
1082
2.5 V
143
158
215
237
717
788
1.8 V
97
106
145
160
483
532
1.5 V
77
85
115
127
383
422
1.2 V
57
63
85
94
283
312
Calculated for VOL = 0.35 V
Assumes output driver VOL = 0.175 V at stated current
+10% to compensate for VDD range and resistor tolerance
9.2.1.3 Application Curve
4
Input
Output
3
Voltage (V)
2
1
0
-1
0
50
100
150
200
250
300
350
400
450
500
Time (ns)
Figure 9-2. Open Drain Translation (1.8 V to 3.3 V at 2.5 MHz)
14
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9.2.2 Mixed-Mode Voltage Translation
The supply voltage (Vpu#) for each channel can be individually set with a pull-up resistor. An example of this
mixed-mode multi-voltage translation is shown in Figure 9-3. For additional details on multi-voltage translation,
see the Multi-voltage Translation with the LSF Family video.
With the Vref_B pulled up to 5V and Vref_A connected to 1.8V, all channels will be clamped to 1.8V at which
point a pullup can be used to define the high level voltage for a given channel.
• Push-Pull Down Translation (5V to 1.8V): Channel 1 is an example of this setup. When B1 is 5V, A1 is
clamped to 1.8V, and when B1 is LOW, A1 is driven LOW through the switch.
• Push-Pull Up Translation (1.8V to 5V): Channel 2 is an example of this setup. When A2 is 1.8V, the switch
is high impedance and the B2 channel is pulled up to 5V. When A2 is LOW, B2 is driven LOW through the
switch.
• Push-Pull Down Translation (3.3V to 1.8V): Channels 3 and 4 are examples of this setup. When either B3
or B4 are driven to 3.3V, A3 or A4 are clamped to 1.8V, and when either B3 or B4 are LOW, A3 or A4 are
driven LOW through the switch.
• Open-Drain Bidirectional Translation (3.3V ↔ 1.8V): Channels 5 through 8 are examples of this setup.
These channels are for bidirectional operation for I2C and MDIO to translate between 1.8V and 3.3V with
open-drain drivers.
Vpu= 5.0V
Vref(A) = 1.8V
Vref_A
LSF0108
1.8V
Vcc
GPIO
GPIO
Vref_B
A1
A2
A3
GPIO
A4
GPIO
A5
SCL
A6
SDA
SW
SW
SW
SW
SW
SW
200KΩ
EN
Rpu
Vcc
B1
GPIO
B2
GPIO
Vcc
B3
GPIO
B4
B5
Vpu= 3.3V
GPIO
Rpu
Rpu
SCL
B6
SDA
Rpu
Rpu
MDIO
SW
MDIO
MDC
SW
MDC
Figure 9-3. Multi-Voltage Translation with the LSF0108
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9.2.3 Voltage Translation for Vref_B < Vref_A + 0.8 V
As described in Table 9-2, it is generally recommended that Vref_B > Vref_A + 0.8 V; however, the device can
still be operated in the condition where Vref_B < Vref_A + 0.8 V as long as additional considerations are made
for the design.
Typical Operation (Vref_B > Vref_A + 0.8 V): In this scenario, pullup resistors are not required on the A-side for
proper down-translation as is shown for channels 1 and 2 of Figure 9-3. The typical operating mode of the device
ensures that when down translating from B to A, the A-side I/O ports will clamp at Vref_A to provide proper
voltage translation. For further explanation of device operation, see the Down Translation with the LSF Family
video.
Requirements for Vref_B < Vref_A + 0.8 V Operation: In this scenario, there is not a large enough voltage
difference between Vref_A and Vref_B to ensure that the A side I/O ports will be clamped at Vref_A, but rather at
a voltage approximately equal to Vref_B - 0.8V. For example, if Vref_B = 1.8V and Vref_A = 1.2V, the A-side I/Os
will clamp to a voltage around 1.0V. Therefore, to operate in such a condition, the following additional design
considerations must be met:
•
•
Vref_B must be greater than Vref_A during operation (Vref_B > Vref_A)
Pullup resistors should be populated on A-side I/O ports to ensure the line will be fully pulled up to the
desired voltage
An example of this setup is shown in Figure 9-4, where 1.2V ↔ 1.8V translation is achieved with the LSF0102.
This type of setup also applies for other voltage nodes such as 1.8V ↔ 2.5V, 1.05V ↔ 1.5V, and others as long
as the Section 6.3 table is followed.
1.8 V
1.2 V
200k
Vref_A
Vref_B
2 LSF0102 7
RPU(A2)
RPU(A1)
A1 3
A2 4
SW
SW
8 EN
0.1 F
RPU(B1)
RPU(B2)
6 B1
5 B2
1
1.2 V Device
1.8 V Device
GND
Figure 9-4. 1.2 to 1.8V Level Translation with LSF0102
16
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10 Power Supply Recommendations
There are no power sequence requirements for the LSF family. For recommended operating voltages for all
supply and input pins, see Table 10-1.
Table 10-1. Recommended Operating Voltages
PARAMETER
MIN
TYP
MAX
UNIT
Vref_A(1)
reference voltage (A)
0.95
4.5
V
Vref_B
reference voltage (B)
Vref_A + 0.8
5.5
V
VI(EN)
input voltage on EN pin
Vref_A + 0.8
5.5
V
Vpu
pull-up supply voltage
0
Vref_B
V
11 Layout
11.1 Layout Guidelines
Because the LSF family is a switch-type level translator, the signal integrity is highly related with a pull-up
resistor and PCB capacitance condition.
•
•
•
Short signal trace as possible to reduce capacitance and minimize stub from pull-up resistor.
Place LSF close to high voltage side.
Select the appropriate pull-up resistor that applies to translation levels and driving capability of transmitter.
11.2 Layout Example
LSF0102
GND
Vref_A
A1
A2
1
2
3
4
8
7
6
5
EN
Short Signal Trace as possible
Vref_B
B1
B2
Minimize Stub as possible
Figure 11-1. Short Trace Layout
TP1
SD Controller
(1.8V IO)
LSF0108
SDIO level translator
SDIO Connector
(3.3V IO)
Device PCB
TP2
Figure 11-2. Device Placement
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12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 12-1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LSF0101
Click here
Click here
Click here
Click here
Click here
LSF0102
Click here
Click here
Click here
Click here
Click here
LSF0108
Click here
Click here
Click here
Click here
Click here
1. LSF Translator Family Evaluation Module
2. The Logic Minute Video Training Series on Understanding the LSF Family of Devices
• Introduction - Voltage Level Translation with the LSF Family
• Understanding the Bias Circuit for the LSF Family
• Using the Enable Pin with the LSF Family
• Translation Basics with the LSF Family
• Down Translation with the LSF Family
• Up Translation with the LSF Family
• Multi-Voltage Translation with the LSF Family
• Single Supply Translation with the LSF Family
3. Voltage Level Translation with the LSF Family Application Note
4. Biasing Requirements for TXS, TXB, and LSF Auto-Bidirectional Translators Application Note
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
18
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
26-May-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
LSF0101DRYR
ACTIVE
SON
DRY
6
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
VD
Samples
LSF0101DTQR
ACTIVE
X2SON
DTQ
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
FC
Samples
LSF0102DCTR
ACTIVE
SM8
DCT
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
NG2
(S, Y)
Samples
LSF0102DCUR
ACTIVE
VSSOP
DCU
8
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(G2, NG2J, NG2P, N
G2S)
NY
LSF0102DQER
ACTIVE
X2SON
DQE
8
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
RV
Samples
LSF0102YZTR
ACTIVE
DSBGA
YZT
8
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
RV
Samples
LSF0108PWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LSF0108
Samples
LSF0108RKSR
ACTIVE
VQFN
RKS
20
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
LSF0108
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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