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LSF0101, LSF0102, LSF0108
ZHCSBY4G – DECEMBER 2013 – REVISED FEBRUAURY 2016
LSF010x 适用于开漏和推挽应用的 1/2/8 通道双向多电压电平转换器
1 特性
•
•
1
•
•
•
•
•
•
•
•
•
•
2 应用
用无方向引脚提供双向电压转换
容性负载
≤ 30pF 时，最高支持 100MHz 的升压转换和
100MHz 以上的降压转换；容性负载为 50pF 时，
最高支持 40MHz 的升压/降压转换
支持热插入
可实现以下电压之间的双向电压电平转换
– 0.95V ↔ 1.8/2.5/3.3/5 V
– 1.2V ↔ 1.8/2.5/3.3/5V
– 1.8V ↔ 2.5/3.3/5V
– 2.5V ↔ 3.3/5V
– 3.3V ↔ 5V
低待机电流
支持 TTL 的 5V 耐受 I/O 端口
低导通电阻 (Ron) 提供较少的信号失真
针对 EN 为低电平的高阻抗 I/O 引脚
直通引脚分配以简化印刷电路板 (PCB) 走线路由
锁断性能超过了 100mA，符合 JESD 17 规范
-40°C 至 125°C 工作温度范围
静电放电 (ESD) 性能测试符合 JESD 22 规范
– 2000V 人体放电模式（A114-B，II 类）
– 200V 机器放电模式 (A115-A)
– 1000V 组件充电模式 (C101)
•
G
P
I
O
，
MDIO，PMBus，SMBus，SDIO，UART，I2C，
和其他电信基础设施中的接口
工业用
汽车用
个人计算
•
•
•
3 说明
LSF 系列在容性负载 ≤ 30pF 时最高支持 100MHz 的
升压转换和 100MHz 以上的降压转换；在容性负载为
50pF 时最高支持 40MHz 的升压/降压转换，因此可支
持更多的消费类或电信接口（MDIO 或 SDIO）。LSF
系列支持双向电压转换，而且无需使用 DIR 引脚，最
大限度降低了系统工作量（PMBus、I2C 或
SMbus）。
LSF 系列的 IO 端口能够耐受 5V 电压，因此与工业和
电信应用中的 TTL 电平 兼容。LSF 系列极具灵活性，
能够为每条通道设置不同电压转换电平。
器件信息(1)
器件型号
封装（引脚）
LSF0101
LSF0102
LSF0108
封装尺寸（标称值）
小外形尺寸无引线
(SON) (6)
1.45mm x 1.00mm
X2SON (8)
1.40mm x 1.00mm
DSBGA (8)
1.90mm x 1.00mm
SM8 (8)
2.80mm x 2.95mm
超薄小外形尺寸封装
(VSSOP)(8)
2.30mm x 2.00mm
超薄四方扁平无引线
封装 (VQFN) (20)
4.50mm x 2.50mm
TSSOP (20)
4.40mm x 6.50mm
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
LSF0102
LSF0101
A2
7
Vref_B
A1
3
6
B1
A2
4
5
B2
2
B2
8
8
3
7
1
1
2
A1
2
A1
EN
GND
Vref_A
Vref_A
B1
B2
B1
Vref_B
EN
4
C2
5
D2
6
A2
GND
5
3
A3
B1
4
C1
6
4
D1
7
3
A1
A2
A1
Vref_A
A4
Vref_B
A5
EN
8
6
5
9
1
2
DQE Package
8-Pin X2SON
(Top View)
A6
GND
Vref_A
YZT Package
8-Pin DSBGA
(Bottom View)
A7
DRY Package
6-Pin SON
(Top View)
LSF0108
RKS Package
20-Pin VQFN
(Top View)
A8
10
1
B8
11
20
GND
EN
18
B1
Vref_B
B3
B2
19
16
B5
B4
17
14
B7
B6
15
12
13
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SDLS966
LSF0101, LSF0102, LSF0108
ZHCSBY4G – DECEMBER 2013 – REVISED FEBRUAURY 2016
www.ti.com.cn
目录
1
2
3
4
5
6
特性 ..........................................................................
应用 ..........................................................................
说明 ..........................................................................
修订历史记录 ...........................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
5
5
5
6
6
6
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information: LSF0101, LSF0108.................
Thermal Information: LSF0102 .................................
Electrical Characteristics...........................................
LSF0101/02 AC Performance (Translating Down)
Switching Characteristics , VGATE = 3.3 V .................
6.8 LSF0108 AC Performance (Translating Down)
Switching Characteristics, VGATE = 3.3 V ..................
6.9 LSF0101/02 AC Performance (Translating Down)
Switching Characteristics, VGATE = 2.5 V ..................
6.10 LSF0108 AC Performance (Translating Down)
Switching Characteristics, VGATE = 2.5 V ..................
6.11 LSF0101/02 AC Performance (Translating Up)
Switching Characteristics, VGATE = 3.3 V ..................
6.12 LSF0108 AC Performance (Translating Up)
Switching Characteristics, VGATE = 3.3 V ..................
6.13 LSF0101/02 AC Performance (Translating Up)
Switching Characteristics, VGATE = 2.5 V .................. 8
6.14 LSF0108 AC Performance (Translating Up)
Switching Characteristics, VGATE = 2.5 V .................. 8
6.15 Typical Characteristics ............................................ 8
7
8
Parameter Measurement Information .................. 9
Detailed Description ............................................ 10
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagrams .....................................
Feature Description.................................................
Device Functional Modes........................................
10
10
11
11
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application .................................................. 12
7
10 Power Supply Recommendations ..................... 19
11 Layout................................................................... 19
7
11.1 Layout Guidelines ................................................. 19
11.2 Layout Example .................................................... 19
7
12 器件和文档支持 ..................................................... 21
7
7
7
12.1
12.2
12.3
12.4
12.5
相关链接................................................................
社区资源................................................................
商标 .......................................................................
静电放电警告.........................................................
Glossary ................................................................
21
21
21
21
21
13 机械、封装和可订购信息 ....................................... 21
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision F (October 2015) to Revision G
•
Page
已在“器件信息”表中添加所有可用封装尺寸并已更改引脚图 说明。........................................................................................ 1
Changes from Revision E (July 2015) to Revision F
Page
•
已更改 特性 从“支持 100MHz 以上的高速转换”改为“容性负载 ≤ 30pF 时，支持最高 100MHz 的升压转换和 100MHz
以上的降压转换；容性负载为 50pF 时，支持最高 40MHz 的升压/降压转换。”..................................................................... 1
•
Updated all propagation delay tables changed from generic to specific LSF devices. ......................................................... 7
Changes from Revision D (October 2014) to Revision E
Page
•
已删除 特性中的“最大传播延迟低于 1.5ns”。 ......................................................................................................................... 1
•
Updated ESD Ratings table. .................................................................................................................................................. 5
•
Increased MAX value for TA, Operating free-air temperature, from 85°C to 125°C. .............................................................. 5
Changes from Revision C (May 2014) to Revision D
Page
•
已将双向电压电平转换从 1.0 改为 0.95 ................................................................................................................................. 1
•
已更改 已更改 YZT 封装以修正视图错误。 ............................................................................................................................ 1
•
Changed YZT package to fix view error. ............................................................................................................................... 3
•
Added pin numbers to Pin Functions table............................................................................................................................. 4
•
Added Vref_A footnote. ........................................................................................................................................................ 13
2
版权 © 2013–2016, Texas Instruments Incorporated
LSF0101, LSF0102, LSF0108
www.ti.com.cn
ZHCSBY4G – DECEMBER 2013 – REVISED FEBRUAURY 2016
Changes from Revision B (May 2014) to Revision C
Page
•
已将 LSF0108 状态由“产品预览”改为“量产数据”。................................................................................................................. 1
•
已更新文档标题....................................................................................................................................................................... 1
•
Updated Handling Ratings table. ........................................................................................................................................... 5
Changes from Revision A (January 2014) to Revision B
•
Page
在数据表中添加了 LSF0108。................................................................................................................................................ 1
Changes from Original (December 2013) to Revision A
Page
•
已更新产品型号。 ................................................................................................................................................................... 1
•
Updated Electrical Characteristics table................................................................................................................................. 6
5 Pin Configuration and Functions
LSF0102 DCT or DCU Package
8-Pin SM8 or VSSOP
Top View
GND
Vref_A
A1
A2
LSF0102 DQE Package
8-Pin X2SON
Top View
GND
EN
1
8
Vref_A
2
7
Vref_B
B1
A1
3
6
B1
B2
A2
4
5
B2
EN
Vref_B
LSF0102 YZT Package
8-Pin DSBGA
Bottom View
A2
A1
Vref_A
GND
D1
4
5
D2
C1
3
6
C2
B1
2
7
B2
A1
1
8
A2
B2
B1
Vref_B
EN
LSF0101 DRY Package
6-Pin SON
Top View
GND
1
6
EN
Vref_A
2
5
Vref_B
3
4
B1
A1
Copyright © 2013–2016, Texas Instruments Incorporated
3
LSF0101, LSF0102, LSF0108
ZHCSBY4G – DECEMBER 2013 – REVISED FEBRUAURY 2016
www.ti.com.cn
LSF0108 PW Package
20-Pin TSSOP
Top View
20 EN
19 Vref_B
GND 1
Vref_A 2
A1 3
18 B1
A2 4
A3 5
17 B2
16 B3
A4 6
A5 7
A6 8
A7 9
15 B4
14 B5
13 B6
12 B7
11 B8
A8 10
LSF0108 RKS Package
20-Pin VQFN
Top View
1
20
GND EN
19
Vref_B
A1
3
18
B1
A2
4
17
B2
A3
5
16
B3
A4
6
15
B4
A5
7
14
B5
A6
8
13
B6
A7
9
12
B7
11
2
10
Vref_A
A8 B8
Pin Functions
PIN
DESCRIPTION
DCT, DCU,
DQE, YZT NO.
DRY
NO.
An
3, 4
3
3 to 10
Bn
6, 5
4
18 to 11
EN
8
6
20
Switch enable input; connect to Vref_B and pull-up through a high resistor (200 kΩ).
GND
1
1
1
Ground
Vref_A
2
2
2
Reference supply voltage; see Application and Implementation.
Vref_B
7
5
19
Reference supply voltage; see Application and Implementation.
NAME
4
PW or RKS
NO.
Data port
Copyright © 2013–2016, Texas Instruments Incorporated
LSF0101, LSF0102, LSF0108
www.ti.com.cn
ZHCSBY4G – DECEMBER 2013 – REVISED FEBRUAURY 2016
6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature (unless otherwise noted)
Input voltage (2)
VI
VI/O
Input/output voltage
(2)
MIN
MAX
UNIT
–0.5
7
V
–0.5
7
V
128
mA
VI < 0
–50
mA
DCT package
220
DCU package
227
Continuous channel current
IIK
Input clamp current
RθJA
Package thermal impedance (3)
Tstg
Storage temperature range
(1)
(2)
(3)
–65
°C/W
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and input/output negative-voltage ratings may be exceeded if the input and input/output clamp-current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VI/O
Input/output voltage
0
5
V
Vref_A/B/EN
Reference voltage
0
5
V
IPASS
Pass transistor current
64
mA
TA
Operating free-air temperature
–40
125
°C
Copyright © 2013–2016, Texas Instruments Incorporated
UNIT
5
LSF0101, LSF0102, LSF0108
ZHCSBY4G – DECEMBER 2013 – REVISED FEBRUAURY 2016
www.ti.com.cn
6.4 Thermal Information: LSF0101, LSF0108
THERMAL METRIC (1)
LSF0101
LSF0108
LSF0108
DRY (SON)
RKS (VQFN)
PW (TSSOP)
6 PINS
20 PINS
20 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
407.0
49.3
106.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
285.2
45.9
41.0
°C/W
RθJB
Junction-to-board thermal resistance
271.6
20.6
57.6
°C/W
ψJT
Junction-to-top characterization parameter
113.5
2.5
4.2
°C/W
ψJB
Junction-to-board characterization parameter
271.0
20.6
47.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
3.4
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Thermal Information: LSF0102
THERMAL METRIC (1)
LSF0102
LSF0102
LSF0102
LSF0102
DCU (US8)
DCT (SM8)
DQE (X2SON)
YZT (DSBGA)
8 PINS
8 PINS
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
210.1
189.6
246.5
125.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
89.1
119.6
149.1
1.0
°C/W
RθJB
Junction-to-board thermal resistance
88.8
102.1
100.0
62.7
°C/W
ψJT
Junction-to-top characterization parameter
8.3
44.5
17.1
3.4
°C/W
ψJB
Junction-to-board characterization parameter
88.4
101.0
99.8
62.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.6 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN TYP (1)
TEST CONDITIONS
MAX
UNIT
VIK
II = –18 mA,
VEN = 0
–1.2
V
IIH
VI = 5 V
VEN = 0
5.0
µA
ICC
Vref_B = VEN = 5.5 V, Vref_A = 4.5 V or 1 V, IO = 0, VI = VCC or GND
CI(ref_A/B/EN)
VI = 3 V or 0
Cio(off)
VO = 3 V or 0,
VEN = 0
Cio(on)
VO = 3 V or 0,
VEN = 3 V
VI = 0,
ron (2)
(1)
(2)
6
1
µA
11
IO = 64 mA
pF
4.0
6.0
pF
10.5
12.5
pF
Vref_A = 3.3 V; Vref_B = VEN = 5 V
8.0
Vref_A = 1.8 V; Vref_B = VEN = 5 V
9.0
Vref_A = 1.0 V; Vref_B = VEN = 5 V
10
Vref_A = 1.8 V; Vref_B = VEN = 5 V
10
Vref_A = 2.5 V; Vref_B = VEN = 5 V
15
Ω
Ω
VI = 0,
IO = 32 mA
VI = 1.8 V,
IO = 15 mA
Vref_A = 3.3 V; Vref_B = VEN = 5 V
9.0
Ω
VI = 1.0 V,
IO = 10 mA
Vref_A = 1.8 V; Vref_B = VEN = 3.3 V
18
Ω
VI = 0 V,
IO = 10 mA
Vref_A = 1.0 V; Vref_B = VEN = 3.3 V
20
Ω
VI = 0 V,
IO = 10 mA
Vref_A = 1.0 V; Vref_B = VEN = 1.8 V
30
Ω
All typical values are at TA = 25°C.
Measured by the voltage drop between the A and B pins at the indicated current through the switch. On-state resistance is determined
by the lowest voltage of the two (A or B) pins.
Copyright © 2013–2016, Texas Instruments Incorporated
LSF0101, LSF0102, LSF0108
www.ti.com.cn
ZHCSBY4G – DECEMBER 2013 – REVISED FEBRUAURY 2016
6.7 LSF0101/02 AC Performance (Translating Down) Switching Characteristics , VGATE = 3.3 V
over recommended operating free-air temperature range, VGATE = 3.3 V, VIH = 3.3 V, VIL = 0, and VM = 1.15 V (unless
otherwise noted) (see Figure 2)
PARAMETER
tPLH
tPHL
FROM (INPUT)
TO (OUTPUT)
A or B
B or A
CL = 50 pF
CL = 30 pF
CL = 15 pF
TYP
TYP
TYP
MAX
MAX
1.1
0.7
0.3
1.2
0.8
0.4
MAX
UNIT
ns
6.8 LSF0108 AC Performance (Translating Down) Switching Characteristics, VGATE = 3.3 V
over recommended operating free-air temperature range, VGATE = 3.3 V, VIH = 3.3 V, VIL = 0, and VM = 1.15 V (unless
otherwise noted) (see Figure 2)
PARAMETER
tPLH
tPHL
FROM (INPUT)
TO (OUTPUT)
A or B
B or A
CL = 50 pF
CL = 30 pF
CL = 15 pF
TYP
TYP
TYP
MAX
MAX
1.9
1.4
0.75
2
1.5
0.85
MAX
UNIT
ns
6.9 LSF0101/02 AC Performance (Translating Down) Switching Characteristics, VGATE = 2.5 V
over recommended operating free-air temperature range, VGATE = 2.5 V, VIH = 2.5 V, VIL = 0, and VM = 0.75 V (unless
otherwise noted) (see Figure 2)
PARAMETER
tPLH
tPHL
FROM (INPUT)
TO (OUTPUT)
A or B
B or A
CL = 50 pF
CL = 30 pF
CL = 15 pF
TYP
TYP
TYP
MAX
MAX
1.2
0.8
0.35
1.3
1
0.5
MAX
UNIT
ns
6.10 LSF0108 AC Performance (Translating Down) Switching Characteristics, VGATE = 2.5 V
over recommended operating free-air temperature range, VGATE = 2.5 V, VIH = 2.5 V, VIL = 0, and VM = 0.75 V (unless
otherwise noted) (see Figure 2)
PARAMETER
tPLH
tPHL
FROM (INPUT)
TO (OUTPUT)
A or B
B or A
CL = 50 pF
CL = 30 pF
CL = 15 pF
TYP
TYP
TYP
MAX
MAX
2
1.45
0.8
2.1
1.55
0.9
MAX
UNIT
ns
6.11 LSF0101/02 AC Performance (Translating Up) Switching Characteristics, VGATE = 3.3 V
over recommended operating free-air temperature range, VGATE = 3.3 V, VIH = 2.3 V, VIL = 0, VT = 3.3 V, VM = 1.15 V and RL
= 300 (unless otherwise noted) (see Figure 2)
PARAMETER
tPLH
tPHL
FROM (INPUT)
TO (OUTPUT)
A or B
B or A
CL = 50 pF
CL = 30 pF
CL = 15 pF
TYP
TYP
TYP
MAX
MAX
1
0.8
0.4
1
0.9
0.4
MAX
UNIT
ns
6.12 LSF0108 AC Performance (Translating Up) Switching Characteristics, VGATE = 3.3 V
over recommended operating free-air temperature range, VGATE = 3.3 V, VIH = 2.3 V, VIL = 0, VT = 3.3 V, VM = 1.15 V and RL
= 300 (unless otherwise noted) (see Figure 2)
PARAMETER
tPLH
tPHL
FROM (INPUT)
TO (OUTPUT)
A or B
B or A
Copyright © 2013–2016, Texas Instruments Incorporated
CL = 50 pF
CL = 30 pF
CL = 15 pF
TYP
TYP
TYP
MAX
MAX
2.1
1.55
0.9
2.2
1.65
1
MAX
UNIT
ns
7
LSF0101, LSF0102, LSF0108
ZHCSBY4G – DECEMBER 2013 – REVISED FEBRUAURY 2016
www.ti.com.cn
6.13 LSF0101/02 AC Performance (Translating Up) Switching Characteristics, VGATE = 2.5 V
over recommended operating free-air temperature range, VGATE = 2.5 V, VIH = 1.5 V, VIL = 0, VT = 2.5 V, VM = 0.75 V and RL
= 300 (unless otherwise noted) (see Figure 2)
PARAMETER
tPLH
tPHL
FROM (INPUT)
TO (OUTPUT)
A or B
B or A
CL = 50 pF
CL = 30 pF
CL = 15 pF
TYP
TYP
TYP
MAX
MAX
1.1
0.9
0.45
1.3
1.1
0.6
MAX
UNIT
ns
6.14 LSF0108 AC Performance (Translating Up) Switching Characteristics, VGATE = 2.5 V
over recommended operating free-air temperature range, VGATE = 2.5 V, VIH = 1.5 V, VIL = 0, VT = 2.5 V, VM = 0.75 V and RL
= 300 (unless otherwise noted) (see Figure 2)
PARAMETER
tPLH
tPHL
FROM (INPUT)
TO (OUTPUT)
A or B
B or A
CL = 50 pF
CL = 30 pF
CL = 15 pF
TYP
TYP
TYP
MAX
MAX
1.8
1.35
0.8
1.9
1.45
0.9
MAX
UNIT
ns
6.15 Typical Characteristics
4.0
Input
Output
3.5
3.0
Voltage (V)
2.5
2.0
1.5
1.0
0.5
0.0
±0.5
0
5
10
15
20
Time (ns)
C005
Figure 1. Signal Integrity (1.8 to 3.3 V Translation Up at 50 MHz)
8
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7 Parameter Measurement Information
VT
RL
USAGE
SWITCH
Translating up
Translating down
S1
S2
S1
Open
From Output
Under Test
S2
3.3 V
Input
VM
VM
VIL
CL
(see Note A)
5V
Output
VM
VM
LOAD CIRCUIT
VOL
TRANSLATING UP
5V
Input
VM
VM
VIL
2V
Output
VM
VM
VOL
TRANSLATING DOWN
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
C. The outputs are measured one at a time, with one transition per measurement.
Figure 2. Load Circuit for Outputs
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8 Detailed Description
8.1 Overview
The LSF family can be used in level translation applications for interfacing devices or systems operating at
different interface voltages with one another. The LSF family is ideal for use in applications where an open-drain
driver is connected to the data I/Os. With appropriate pull-up resistors and layout, LSF can achieve 100 MHz.
The LSF family can also be used in applications where a push-pull driver is connected to the data I/Os.
8.2 Functional Block Diagrams
Vref_A
2
A1 3
Vref_B
LSF0101
5
6 EN
4 B1
SW
1
GND
Figure 3. LSF0101 Functional Block Diagram
Vref_A
2
A1 3
A2 4
Vref_B
LSF0102
7
SW
SW
8 EN
6 B1
5 B2
1
GND
Figure 4. LSF0102 Functional Block Diagram
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Functional Block Diagrams (continued)
Vref_B
Vref_A
19
2
LSF0108
B1
SW
4
A2
17
B2
SW
5
A3
16
B3
SW
6
A4
15
B4
SW
14
7
A5
B5
SW
8
A6
13
B6
SW
9
A7
12
B7
SW
10
A8
EN
18
3
A1
20
11
SW
B8
1
GND
Figure 5. LSF0108 Functional Block Diagram
8.3 Feature Description
The LSF family are bidirectional voltage level translators operational from 0.95 to 4.5 V (Vref_A) and 1.8 to 5.5 V
(Vref_B). This allows bidirectional voltage translations between 1 V and 5 V without the need for a direction pin in
open-drain or push-pull applications. LSF family supports level translation applications with transmission speeds
greater than 100 Mbps for open-drain systems using a 30-pF capacitance and 250-Ω pullup resistor.
When the An or Bn port is LOW, the switch is in the ON-state and a low resistance connection exists between
the An and Bn ports. The low Ron of the switch allows connections to be made with minimal propagation delay
and signal distortion. Assuming the higher voltage is on the Bn port when the Bn port is HIGH, the voltage on the
An port is limited to the voltage set by Vref_A. When the An port is HIGH, the Bn port is pulled to the drain pullup supply voltage (Vpu#) by the pull-up resistors. This functionality allows a seamless translation between higher
and lower voltages selected by the user without the need for directional control.
The supply voltage (Vpu#) for each channel can be individually set up with a pull-up resistor. For example, CH1
can be used in up-translation mode (1.2 V ↔ 3.3 V) and CH2 in down-translation mode (2.5 V ↔ 1.8 V).
When EN is HIGH, the translator switch is on, and the An I/O is connected to the Bn I/O, respectively, allowing
bidirectional data flow between ports. When EN is LOW, the translator switch is off, and a high-impedance state
exists between ports. The EN input circuit is designed to be supplied by Vref_B. To ensure the high-impedance
state during power-up or power-down, EN must be LOW.
8.4 Device Functional Modes
Table 1 expresses the functional modes of the LSF devices.
Table 1. Function Table
INPUT EN
(1)
(1)
PIN
FUNCTION
H
An = Bn
L
H-Z
EN is controlled by Vref_B logic levels and should be at least 1 V
higher than Vref_A for best translator.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LSF devices are able to perform voltage translation for open-drain or push-pull interface. Table 2 provides
some consumer/telecom interfaces as reference in regards to the different channel numbers that are supported
by the LSF family.
Table 2. Voltage Translator for Consumer/Telecom Interface
Part Name
Channel Number
LSF0101
1
GPIO
Interface
LSF0102
2
GPIO, MDIO, SMBus, PMBus, I2C
LSF0108
8
GPIO, MDIO, SDIO, SVID, UART, SMBus, PMBus, I2C, SPI
9.2 Typical Application
9.2.1 I2C PMBus, SMBus, GPIO
3.3V enable signal
ON
Off
Vref(A) = 1.2V
Vpu1 = 3.3V
200KΩ
Vref_A
2
Rpu
Vpu3 = 2.5V
Vcc
Rpu
A1 3
GPIO3
Vcc
A2 4
GPIO4
GND
Vref_B
LSF0102
7
8 EN
Rpu Rpu
6 B1
SW
5 B2
SW
Vcc
GPIO1
GPIO2
GND
1
GND
Figure 6. Bidirectional Translation to Multiple Voltage Levels
9.2.1.1 Design Requirements
9.2.1.1.1 Enable, Disable, and Reference Voltage Guidelines
The LSF family has an EN input that is used to disable the device by setting EN LOW, which places all I/Os in
the high-impedance state. Since LSF family is switch-type voltage translator, the power consumption is very low.
It is recommended to always enable LSF family for bidirectional application (I2C, SMBus, PMBus, or MDIO).
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Typical Application (continued)
Table 3. Application Operating Condition
PARAMETER
MIN
TYP
MAX
UNIT
Vref_A (1)
reference voltage (A)
0.95
4.5
V
Vref_B
reference voltage (B)
Vref_A + 0.8
5.5
V
VI(EN)
input voltage on EN pin
Vref_A + 0.8
5.5
V
Vpu
pull-up supply voltage
0
Vref_B
V
(1)
Vref_A have to be the lowest voltage level across all of inputs and outputs.
The 200 kΩ, pull-up resistor is required to allow Vref_B to regulate the EN input. A filter capacitor on
Vref_B is recommended. Also Vref_B and VI(EN) are recommended to be at 1.0 V higher than Vref_A for best
signal integrity.
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Bidirectional Translation
For the bidirectional clamping configuration (higher voltage to lower voltage or lower voltage to higher voltage),
the EN input must be connected to Vref_B and both pins pulled to HIGH side Vpu through a pull-up resistor
(typically 200 kΩ). This allows Vref_B to regulate the EN input. A filter capacitor on Vref_B is recommended. The
master output driver can be push-pull or open-drain (pull-up resistors may be required) and the slave device
output can be push-pull or open-drain (pull-up resistors are required to pull the Bn outputs to Vpu).
If either output is push-pull, data must be unidirectional or the outputs must be tri-state and be
controlled by some direction-control mechanism to prevent HIGH-to-LOW contentions in either direction.
If both outputs are open-drain, no direction control is needed.
In Figure 6, the reference supply voltage (Vref_A) is connected to the processor core power supply voltage.
When Vref_B is connected through a 200 kΩ resistor to a 3.3 V Vpu power supply, and Vref_A is set 1.0 V. The
output of A3 and B4 has a maximum output voltage equal to Vref_A, and the bidirectional interface (Ch1/2,
MDIO) has a maximum output voltage equal to Vpu.
9.2.1.2.2 Pull-up Resistor Sizing
The pull-up resistor value needs to limit the current through the pass transistor when it is in the ON state to about
15 mA. This ensures a pass voltage of 260 mV to 350 mV. If the current through the pass transistor is higher
than 15 mA, the pass voltage also is higher in the ON state. To set the current through each pass transistor at 15
mA, to calculate the pull-up resistor value use the following equation:
Rpu = (Vpu – 0.35 V) / 0.015 A
(1)
Table 4 summarizes resistor values, reference voltages, and currents at 15 mA, 10 mA, and 3 mA. The resistor
value shown in the +10% column (or a larger value) should be used to ensure that the pass voltage of the
transistor is 350 mV or less. The external driver must be able to sink the total current from the resistors on both
sides of the LSF family device at 0.175 V, although the 15 mA applies only to current flowing through the LSF
family device.
Table 4. Pull-up Resistor Values (1) (2)
VDPU
(1)
(2)
(3)
15 mA
NOMINAL (Ω)
10 mA
+10%
(3)
(Ω)
NOMINAL (Ω)
3 mA
+10%
(3)
(Ω)
NOMINAL (Ω)
+10% (3) (Ω)
5V
310
341
465
512
1550
1705
3.3 V
197
217
295
325
983
1082
2.5 V
143
158
215
237
717
788
1.8 V
97
106
145
160
483
532
1.5 V
77
85
115
127
383
422
1.2 V
57
63
85
94
283
312
Calculated for VOL = 0.35 V
Assumes output driver VOL = 0.175 V at stated current
+10% to compensate for VDD range and resistor tolerance
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9.2.1.2.3 LSF Family Bandwidth
The maximum frequency of the LSF family is dependent on the application. The device can operate at speeds of
>100 MHz gave the correct conditions. The maximum frequency is dependent upon the loading of the
application. The LSF family behaves like a standard switch where the bandwidth of the device is dictated by the
on resistance and on capacitance of the device.
Figure 7 shows a bandwidth measurement of the LSF family using a two-port network analyzer.
0
–1
–2
Gain (dB)
–3
–4
–5
–6
–7
–8
–9
0.1
1
10
100
Frequency (MHz)
1000
Figure 7. 3-dB Bandwidth
The 3-dB point of the LSF family is ≈ 600 MHz; however, this measurement is an analog type of measurement.
For digital applications the signal should not degrade up to the fifth harmonic of the digital signal. The frequency
bandwidth should be at least five times the maximum digital clock rate. This component of the signal is very
important in determining the overall shape of the digital signal. In the case of the LSF family, a digital clock
frequency of greater than 100 MHz can be achieved.
The LSF family does not provide any drive capability. Therefore higher frequency applications will require higher
drive strength from the host side. No pull-up resistor is needed on the host side (3.3 V) if the LSF family is being
driven by standard CMOS totem pole output driver. Ideally, it is best to minimize the trace length from the LSF
family on the sink side (1.8 V) to minimize signal degradation.
All fast edges have an infinite spectrum of frequency components; however, there is an inflection (or knee) in the
frequency spectrum of fast edges where frequency components higher than ƒknee are insignificant in determining
the shape of the signal.
To calculate the maximum practical frequency component, or the knee frequency (fknee), use the following
equations:
ƒknee = 0.5 / RT (10 – 80%)
ƒknee = 0.4 / RT (20 – 80%)
(2)
(3)
For signals with rise time characteristics based on 10% to 90% thresholds, fknee is equal to 0.5 divided by the rise
time of the signal. For signals with rise time characteristics based on 20% to 80% thresholds, which is very
common in many of today's device specifications, ƒknee is equal to 0.4 divided by the rise time of the signal.
Some guidelines to follow that will help maximize the performance of the device:
• Keep trace length to a minimum by placing the LSF family close to the I2C output of the processor.
• The trace length should be less than half the time of flight to reduce ringing and line reflections or nonmonotonic behavior in the switching region.
• To reduce overshoots, a pull-up resistor can be added on the 1.8 V side; be aware that a slower fall time is to
be expected.
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9.2.1.3 Application Curve
4
Input
Output
3
Voltage (V)
2
1
0
-1
0
50
100
150
200
250
300
350
400
450
500
Time (ns)
2
Figure 8. Captured Waveform From Above I C Set-Up (1.8 V to 3.3 V at 2.5 MHz)
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9.2.2 MDIO
3.3V enable signal
ON
Vref(A) = 1.8V
Off
Vref_A
2
Rpu
Rpu
Vcc
A1 3
MDIO
A2 4
MDC
Vpu = 3.3V
200KΩ
Vref_B
LSF0102
7
SW
SW
8 EN
Rpu
Rpu
Vcc
6 B1
MDIO
5 B2
MDC
1
GND
GND
GND
Figure 9. Typical Application Circuit (MDIO/Bidirectional Interface)
9.2.2.1 Design Requirements
Refer to Design Requirements.
9.2.2.2 Detailed Design Procedure
Refer to Detailed Design Procedure.
9.2.2.3 Application Curve
Input (3.3V)
Output (1.0V)
Figure 10. Captured Waveform From Above MDIO Setup
16
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9.2.3 Multiple Voltage Translation in Single Device
Vpu= 5.0V
Vref(A) = 1.8V
Vref_B
Vref_A
LSF0108
1.8V
Vcc
GPIO
GPIO
A1
A2
A3
GPIO
A4
GPIO
A5
SCL
A6
SDA
SW
SW
SW
SW
SW
SW
200KΩ
EN
Rpu
Vcc
B1
GPIO
B2
GPIO
Vcc
B3
GPIO
B4
B5
Vpu= 3.3V
GPIO
Rpu
Rpu
SCL
B6
SDA
Rpu
Rpu
MDIO
SW
MDIO
MDC
SW
MDC
9.2.3.1 Design Requirements
Refer to Design Requirements.
9.2.3.2 Detailed Design Procedure
Refer to Detailed Design Procedure.
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9.2.3.3 Application Curve
3.5
Input
Output
3
Voltage (V)
2.5
2
1.5
1
0.5
0
-0.5
0
2
4
6
8
10 12
Time (ns)
14
16
18
20
22
D012
Figure 11. Translation Down (3.3 to 1.8 V) at 150 MHz
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10 Power Supply Recommendations
There are no power sequence requirements for the LSF family. For enable and reference voltage guidelines,
please refer to the Enable, Disable, and Reference Voltage Guidelines.
11 Layout
11.1 Layout Guidelines
Because the LSF family is a switch-type level translator, the signal integrity is highly related with a pull-up
resistor and PCB capacitance condition.
• Short signal trace as possible to reduce capacitance and minimize stub from pull-up resistor.
• Place LSF close to high voltage side.
• Select the appropriate pull-up resistor that applies to translation levels and driving capability of transmitter.
11.2 Layout Example
LSF0102
GND
Vref_A
A1
A2
1
2
3
4
8
7
6
5
EN
Short Signal Trace as possible
Vref_B
B1
B2
Minimize Stub as possible
Figure 12. Short Trace Layout
TP1
SD Controller
(1.8V IO)
LSF0108
SDIO level translator
SDIO Connector
(3.3V IO)
Device PCB
TP2
Figure 13. Device Placement
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Layout Example (接
接下页)
3.5
3.5
Input
Output
3
2.5
2.5
2
Voltage (V)
Voltage (V)
Input
Output
3
1.5
1
2
1.5
1
0.5
0.5
0
0
-0.5
0
2.5
5
7.5
10
12.5 15
Time (ns)
17.5
20
22.5
25
D011
Figure 14. Waveform From TP1 (Pull-up Resistor: 160-Ω
and 50-pF Capacitance 3.3 V to 1.8 V at 100 MHz)
20
-0.5
0
3
6
9
12
15
18
Time (ns)
21
24
27
30
D010
Figure 15. Waveform From TP2 (Pull-up Resistor: 160-Ω
and 50-pF Capacitance 1.8 V to 3.3 V at 100 MHz)
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12 器件和文档支持
12.1 相关链接
下面的表格列出了快速访问链接。范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购
买链接。
表 5. 相关链接
器件
产品文件夹
样片与购买
技术文档
工具与软件
支持与社区
LSF0101
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
LSF0102
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
LSF0108
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
12.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
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21
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对 TI 及其代理造成的任何损失。
在某些场合中，为了推进安全相关应用有可能对 TI 组件进行特别的促销。TI 的目标是利用此类组件帮助客户设计和创立其特 有的可满足适用
的功能安全性标准和要求的终端产品解决方案。尽管如此，此类组件仍然服从这些条款。
TI 组件未获得用于 FDA Class III（或类似的生命攸关医疗设备）的授权许可，除非各方授权官员已经达成了专门管控此类使 用的特别协议。
只有那些 TI 特别注明属于军用等级或“增强型塑料”的 TI 组件才是设计或专门用于军事/航空应用或环境的。购买者认可并同 意，对并非指定面
向军事或航空航天用途的 TI 组件进行军事或航空航天方面的应用，其风险由客户单独承担，并且由客户独 力负责满足与此类使用相关的所有
法律和法规要求。
TI 已明确指定符合 ISO/TS16949 要求的产品，这些产品主要用于汽车。在任何情况下，因使用非指定产品而无法达到 ISO/TS16949 要
求，TI不承担任何责任。
产品
应用
数字音频
www.ti.com.cn/audio
通信与电信
www.ti.com.cn/telecom
放大器和线性器件
www.ti.com.cn/amplifiers
计算机及周边
www.ti.com.cn/computer
数据转换器
www.ti.com.cn/dataconverters
消费电子
www.ti.com/consumer-apps
DLP® 产品
www.dlp.com
能源
www.ti.com/energy
DSP - 数字信号处理器
www.ti.com.cn/dsp
工业应用
www.ti.com.cn/industrial
时钟和计时器
www.ti.com.cn/clockandtimers
医疗电子
www.ti.com.cn/medical
接口
www.ti.com.cn/interface
安防应用
www.ti.com.cn/security
逻辑
www.ti.com.cn/logic
汽车电子
www.ti.com.cn/automotive
电源管理
www.ti.com.cn/power
视频和影像
www.ti.com.cn/video
微控制器 (MCU)
www.ti.com.cn/microcontrollers
RFID 系统
www.ti.com.cn/rfidsys
OMAP应用处理器
www.ti.com/omap
无线连通性
www.ti.com.cn/wirelessconnectivity
德州仪器在线技术支持社区
www.deyisupport.com
IMPORTANT NOTICE
邮寄地址： 上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122
Copyright © 2016, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
3-Jul-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LSF0101DRYR
ACTIVE
SON
DRY
6
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VD
LSF0102DCTR
ACTIVE
SM8
DCT
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
NG2
(S ~ Y)
LSF0102DCUR
ACTIVE
VSSOP
DCU
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(G2 ~ NG2P ~ NG2S)
NY
LSF0102DQER
ACTIVE
X2SON
DQE
8
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
RV
LSF0102YZTR
ACTIVE
DSBGA
YZT
8
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
RV
LSF0108PWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LSF0108
LSF0108RKSR
ACTIVE
VQFN
RKS
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LSF0108
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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