LSF0204, LSF0204D
SLVSCP5H – JULY 2014 – REVISED APRIL 2021
LSF0204x 4-Bits Bidirectional Multi-Voltage Level Translator for Open-Drain and
Push-Pull Application
1 Features
3 Description
•
The LSF family consists of bidirectional voltage
level translators that operate from 0.8 V to 4.5 V
(Vref_A) and 1.8 V to 5.5 V (Vref_B). This range
allows for bidirectional voltage translations between
0.8 V and 5.0 V without the need for a direction
terminal in open-drain or push-pull applications. The
LSF family supports level translation applications with
transmission speeds greater than 100 MHz for opendrain systems that utilize a 15-pF capacitance and
165-Ω pull-up resistor.
•
•
•
•
•
•
•
•
•
•
•
Provides bidirectional voltage translation with no
direction terminal
Supports up to 100-MHz up translation and greater
than 100-MHz down translation
at ≤ 30-pF capacitor load and up to 40-MHz up/
down translation at 50-pF capacitor load
Supports Ioff, partial power-down mode (refer to
Feature Description)
Allows bidirectional voltage level translation
between
– 0.8 V ↔ 1.8, 2.5, 3.3, 5 V
– 1.2 V ↔ 1.8, 2.5, 3.3, 5 V
– 1.8 V ↔ 2.5, 3.3, 5 V
– 2.5 V ↔ 3.3, 5 V
– 3.3 V ↔ 5 V
Low standby current
5 V Tolerance I/O port to support TTL
Low Ron provides less signal distortion
High-impedance I/O terminals for EN = Low
Flow-through pinout for easy PCB trace routing
Latch-up performance exceeds 100 mA per
JESD17
–40°C to 125°C operating temperature range
ESD performance tested per JESD 22
– 2000-V human-body model (A114-B, Class II)
– 200-V machine model (A115-A)
– 1000-V charged-device model (C101)
2 Applications
•
•
•
•
GPIO, MDIO, PMBus, SMBus, SDIO, UART, I2C,
and other interfaces in telecom infrastructure
Industrial
Automotive
Personal computing
When the An or Bn port is LOW, the switch is in
the ON-state and a low resistance connection exists
between the An and Bn ports. The low Ron of the
switch allows connections to be made with minimal
propagation delay and signal distortion. The voltage
on the A or B side will be limited to Vref_A and
can be pulled up to any level between Vref_A and
5 V. This functionality allows a seamless translation
between higher and lower voltages selected by the
user without the need for directional control.
Device Information(1)
PART NUMBER
PACKAGE
LSF0204x
(1)
BODY SIZE (NOM)
TSSOP (14)
5.00 mm × 4.40 mm
UQFN (12)
2.00 mm × 1.70 mm
VQFN (14)
3.50 mm × 3.50 mm
DSBGA (12)
1.90 mm × 1.40 mm
For all available packages, see the orderable addendum at
the end of the datasheet.
Vref_B
Vref_A
LSF0204
EN
A1
SW
B1
A2
SW
B2
A3
SW
B3
A4
SW
B4
GND
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LSF0204, LSF0204D
www.ti.com
SLVSCP5H – JULY 2014 – REVISED APRIL 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 4
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings............................................................... 6
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics.............................................7
7.6 Switching Characteristics: AC Performance
(Translating Down, 3.3 V to 1.8 V)................................ 7
7.7 Switching Characteristics: AC Performance
(Translating Down, 3.3 V to 1.2 V)................................ 8
7.8 Switching Characteristics: AC Performance
(Translating Up, 1.8 V to 3.3 V)..................................... 8
7.9 Switching Characteristics: AC Performance
(Translating Up, 1.2 V to 1.8 V)..................................... 8
7.10 Typical Characteristics.............................................. 8
8 Parameter Measurement Information............................ 9
8.1 Load Circuit AC Waveform for Outputs.....................10
9 Detailed Description...................................................... 11
9.1 Overview................................................................... 11
9.2 Functional Block Diagram......................................... 11
9.3 Feature Description...................................................12
9.4 Device Functional Modes..........................................12
10 Application and Implementation................................ 13
10.1 Application Information........................................... 13
10.2 Typical Applications................................................ 13
11 Power Supply Recommendations..............................19
12 Layout...........................................................................19
12.1 Layout Guidelines................................................... 19
12.2 Layout Example...................................................... 19
13 Device and Documentation Support..........................21
13.1 Receiving Notification of Documentation Updates..21
13.2 Support Resources................................................. 21
13.3 Trademarks............................................................. 21
13.4 Electrostatic Discharge Caution..............................21
13.5 Glossary..................................................................21
14 Mechanical, Packaging, and Orderable
Information.................................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (November 2019) to Revision H (April 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Updated the Bidirectional Translation section to include inclusive terminology................................................14
Changes from Revision F (January 2019) to Revision G (November 2019)
Page
• Changed Vref_A/B/EN max voltage to 5.5 V in the Recommended Operating Conditions table............................6
Changes from Revision E (December 2018) to Revision F (January 2019)
Page
• Changed location of YZP-package indicator dot to A3 position. ........................................................................4
• Added YZP package to Thermal Information table.............................................................................................6
Changes from Revision D (December 2015) to Revision E (December 2018)
Page
• Changed location of YZP-package A1-pin indicator dot. View is looking through the device, as in an X-ray. ....
4
Changes from Revision C (August 2015) to Revision D (December 2015)
Page
• Added Type Column to Pin Functions table........................................................................................................4
• Added Junction Temperatures to Thermal Information table.............................................................................. 6
Changes from Revision B (April 2015) to Revision C (August 2015)
Page
• Removed bullet "Less than 1.5 ns max propagation delay" from Features........................................................ 1
• Updated "Supports High Speed Translation, Greater Than 100 MHz" bullet in Features.................................. 1
Changes from Revision A (December 2014) to Revision B (April 2015)
Page
• Added YZP package to device. ......................................................................................................................... 1
2
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LSF0204 LSF0204D
LSF0204, LSF0204D
www.ti.com
SLVSCP5H – JULY 2014 – REVISED APRIL 2021
Changes from Revision * (November 2014) to Revision A (December 2014)
Page
• Changed From a first page Product Preview To a full datasheet .......................................................................1
• Changed text in the Section 3 From: "transmission speeds greater than 100 Mbps" To: "transmission speeds
greater than 100 MHz" .......................................................................................................................................1
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LSF0204 LSF0204D
3
LSF0204, LSF0204D
www.ti.com
SLVSCP5H – JULY 2014 – REVISED APRIL 2021
5 Description (continued)
The supply voltage (Vpu#) for each channel may be individually set up with a pull up resistor. For example, CH1
may be used in up-translation mode (1.2 V ↔ 3.3 V) and CH2 in down-translation mode (2.5 V ↔ 1.8 V).
When EN is HIGH, the translator switch is on, and the An I/O is connected to the Bn I/O, respectively, allowing
bidirectional data flow between ports. When EN is LOW, the translator switch is off, and a high-impedance state
exists between ports. The EN input circuit is designed to be supplied by Vref_A. EN must be LOW to ensure the
high-impedance state during power-up or power-down.
Device Comparison Table
PART
NUMBER
EN
An
Bn
DESCRIPTION
H
Place all data pins in 3 state mode
(Hi-Z)
Place all data pins in 3 state mode (Hi-Z)
LSF0204D
L
Input or output
Input or output
LSF0204
H
Input or output
Input or output
LSF0204
L
Place all data pins in 3 state mode
(Hi-Z)
Place all data pins in 3 state mode (Hi-Z)
LSF0204D
3-state output mode enable
(active Low; referenced to Vref_A)
3-state output mode enable
(active High, referenced to Vref_A)
6 Pin Configuration and Functions
Vref_A 1
14 Vref_B
13 B1
A1 2
Vref_A
Vref_B
1
14
12 B2
A1
A3 4
11 B3
A2
3
A4 5
10 B4
A3
4
11
NC 6
9 NC
A4
5
10
B4
GND 7
8 EN
NC
6
9
NC
A2 3
Figure 6-1. PW Package,
14-Pin TSSOP
(Top View)
2
13
B1
12
B2
B3
7
8
GND
EN
Figure 6-2. RGY Package,
14-Pin VQFN
(Transparent Top View)
EN
Vref_A
11
Vref_B
A1
2
10
B1
A2
A3
A4
3
9
B2
4
8
B3
B4
1
12
6
5
7
GND
Figure 6-3. RUT Package,
12-Pin UQFN
(Transparent Top View)
4
Figure 6-4. YZP Package,
12-Pin DSBGA
(Transparent Top View)
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LSF0204 LSF0204D
LSF0204, LSF0204D
www.ti.com
SLVSCP5H – JULY 2014 – REVISED APRIL 2021
Table 6-1. Pin Functions
PIN
NAME
NO.
TYPE(1)
DESCRIPTION
PW, RGY
RUT
YZP
Vref_A
1
1
B2
—
Reference supply voltage; see Application and Implementation section
A1
2
2
A3
I/O
Input/output 1.
A2
3
3
B3
I/O
Input/output 2.
A3
4
4
C3
I/O
Input/output 3.
A4
5
5
D3
I/O
Input/output 4.
NC
6
–
—
—
No connection. Not internally connected.
GND
7
6
D2
—
Ground
EN
8
12
C2
I
NC
9
–
—
—
No connection. Not internally connected.
B4
10
7
D1
I/O
Input/output 4.
B3
11
8
C1
I/O
Input/output 3.
B2
12
9
B1
I/O
Input/output 2.
B1
13
10
A1
I/O
Input/output 1.
Vref_B
14
11
A2
—
Reference supply voltage; see Application and Implementation section
(1)
Switch enable input; LSF0204: EN is high-active; LSF0204D: EN is
low-active
I = input, O = output
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LSF0204 LSF0204D
5
LSF0204, LSF0204D
www.ti.com
SLVSCP5H – JULY 2014 – REVISED APRIL 2021
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Input voltage (2)
VI
VI/O
Input/output voltage
MAX
–0.5
(2)
–0.5
7
Continuous channel current
IIK
Input clamp current
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
UNIT
7
VI < 0
–65
V
V
128
mA
–50
mA
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
The input and input/output negative-voltage ratings may be exceeded if the input and input/output clamp-current ratings are observed.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101(2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VI/O
Input/output voltage
0
5.5
V
Vref_A/B/EN
Reference voltage
0
5.5
V
IPASS
Pass transistor current
64
mA
TA
Operating free-air temperature
–40
125
°C
7.4 Thermal Information
LSF0204
THERMAL METRIC(1)
RθJA
RUT (UQFN)
PW (TSSOP)
YZP (DSBGA)
14 PINS
12 PINS
14 PINS
12 BALLS
83.2
195.8
157.9
83.7
°C
RθJC(top) Junction-to-case (top) thermal resistance
98.2
98.7
82.3
0.6
°C
RθJB
Junction-to-board thermal resistance
59.2
122.6
100.0
23.7
°C
ψJT
Junction-to-top characterization parameter
17.4
6.2
22.9
0.4
°C
ψJB
Junction-to-board characterization parameter
59.4
122.6
99.0
23.7
°C
RθJC(bot) Junction-to-case (bottom) thermal resistance
38.7
N/A
N/A
N/A
°C
(1)
6
Junction-to-ambient thermal resistance
UNIT
RGY (VQFN)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LSF0204 LSF0204D
LSF0204, LSF0204D
www.ti.com
SLVSCP5H – JULY 2014 – REVISED APRIL 2021
7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
II = -18 mA, VEN = 0
IIH
MIN
TYP(1)
MAX
UNIT
–1.2
V
VI = 5 V, VEN = 0
5.0
µA
3.5
µA
ICCBA
Leakage from
Vref_B to Vref_A
Vref_B = 3.3 V, Vref_A = 1.8 V, VEN = Vref_A IO = 0, VI = 3.3 V or GND
ICCA + ICCB (4)
Total Current
through GND
Vref_B = 3.3 V, Vref_A = 1.8 V, VEN = Vref_A IO = 0, VI = 3.3 V or GND
IIN
Control pin current Vref_B = 5.5 V, Vref_A = 4.5 V, VEN = 0 to Vref_A IO = 0
±1
µA
Ioff
Power Off
Leakage Current
±1
µA
VI = 3 V or 0
Cio(off)
VO = 3 V or 0, VEN = 0
Cio(on)
VO = 3 V or 0, VEN = Vref_A
7
(3)V
High-level input
voltage
Vref_A = 1.5 V to 4.5 V
VIL (EN pin)
Low-level input
voltage
Vref_A = 1.5 V to 4.5 V
VIH (EN pin)
High-level input
voltage
Vref_A= 1.0 V to 1.5 V
VIL (EN pin)
Low-level input
voltage
Vref_A = 1.0 V to 1.5 V
VI = 0, IO = 32 mA
(3)
(4)
6.0
pF
10.5
13
pF
V
0.3×Vref_A
0.8×Vref_A
0.3×Vref_A
Vref_A = VEN = 3.3 V; Vref_B = 5 V
3
Vref_A = VEN = 1.8 V; Vref_B = 5 V
4
Vref_A = VEN = 1.0 V; Vref_B = 5 V
9
Vref_A = VEN = 1.8 V; Vref_B = 5 V
4
VI = 0, IO = 32 mA , Vref_A = VEN = 2.5 V; Vref_B = 5 V
V
V
10
VI = 0, IO = 64 mA
(1)
(2)
pF
5.0
0.7×Vref_A
Input transition rise
∆t/∆v (EN pin) or fall rate for EN
pin
ron (2)
µA
Vref_B = Vref_A = 0 V, VEN = GND IO = 0, VI = 5 V or GND
CI(ref_A/B/EN)
IH (EN pin)
0.2
V
ns/V
Ω
Ω
10
Ω
VI = 1.8 V, IO = 15 mA, Vref_A = VEN = 3.3 V; Vref_B = 5 V
5
Ω
VI = 1.0 V, IO = 10 mA, Vref_A = VEN = 1.8 V; Vref_B = 3.3 V
8
Ω
VI = 0 V, IO = 10 mA, Vref_A = VEN = 1.0 V; Vref_B = 3.3 V
6
Ω
VI = 0 V, IO = 10 mA, Vref_A = VEN = 1.0 V; Vref_B = 1.8 V
6
Ω
All typical values are at TA = 25°C.
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is
determined by the lowest voltage of the two (A or B) terminals.
Enable pin test conditions are for the LSF0204. The enable pin test conditions for LSF0204D are oppositely set.
The actual supply current for LSF0204 is ICCA + ICCB; the leakage from Vref_B to Vref_A can be measured on Vref_A and Vref_B pin
7.6 Switching Characteristics: AC Performance (Translating Down, 3.3 V to 1.8 V)
over recommended operating free-air temperature range, Vrev-A = 1.8 V, Vrev-B = 3.3 V, VEN = 1.8 V, Vpu_1 = 3.3 V,
Vpu_2 = 1.8 V, RL = NA, VIH = 3.3 V, VIL = 0 VM = 1.15 V (unless otherwise noted)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
CL = 50 pF
CL = 30 pF
CL = 15 pF
UNIT
TYP
MAX
TYP
MAX
TYP
MAX
0.7
5.49
0.5
5.29
0.3
5.19
ns
0.9
4.9
0.7
4.7
0.5
4.5
ns
13
18
12
16.5
11
15
ns
tPZL
33
45
30
40
23
37
fMAX
50
tPLH
tPHL
tPLZ
A or B
B or A
100
100
ns
MHz
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LSF0204 LSF0204D
7
LSF0204, LSF0204D
www.ti.com
SLVSCP5H – JULY 2014 – REVISED APRIL 2021
7.7 Switching Characteristics: AC Performance (Translating Down, 3.3 V to 1.2 V)
over recommended operating free-air temperature range Vrev-A = 1.2 V, Vrev-B = 3.3 V, VEN = 1.2 V, Vpu_1 = 3.3 V,
Vpu_2 = 1.2 V, RL = NA, VIH = 3.3 V, VIL = 0 VM = 0.85 V (unless otherwise noted)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
A or B
B or A
CL = 50 pF
tPLH
tPHL
fMAX
CL = 30 pF
CL = 15 pF
UNIT
TYP
MAX
TYP
MAX
TYP
MAX
0.8
4.1
0.5
3.9
0.3
3.8
ns
0.9
4.7
0.7
4.5
0.6
4.3
ns
50
100
100
MHz
7.8 Switching Characteristics: AC Performance (Translating Up, 1.8 V to 3.3 V)
over recommended operating free-air temperature range Vrev-A = 1.8 V, Vrev-B = 3.3 V, VEN = 1.8 V, Vpu_1 = 3.3 V, Vpu_2 =
1.8 V, RL = 500 Ω, VIH = 1.8 V,VIL = 0 VM = 0.9 V (unless otherwise noted)
PARAMETER
FROM (INPUT)
CL = 50 pF
TO (OUTPUT)
CL = 30 pF
CL = 15 pF
UNIT
TYP
MAX
TYP
MAX
TYP
MAX
0.6
5.7
0.4
5.3
0.2
5.13
ns
1.3
6.7
1
6.4
0.7
5.3
ns
13
18
12
16.5
11
15
ns
tPZL
33
45
30
40
23
37
fMAX
50
tPLH
tPHL
tPLZ
A or B
B or A
100
100
ns
MHz
7.9 Switching Characteristics: AC Performance (Translating Up, 1.2 V to 1.8 V)
over recommended operating free-air temperature range, Vrev-A = 1.2 V, Vrev-B = 1.8 V, VEN = 1.2 V, Vpu_1 = 1.8 V,
Vpu_2 = 1.2 V, RL = 500 Ω, VIH = 1.2 V, VIL = 0 VM = 0.6 V (unless otherwise noted)
PARAMETER
FROM (INPUT)
CL = 50 pF
TO (OUTPUT)
tPLH
tPHL
A or B
B or A
fMAX
CL = 30 pF
CL = 15 pF
TYP
MAX
TYP
MAX
TYP
MAX
0.65
7.25
0.4
7.05
0.2
6.85
1.6
7.03
1.3
6.5
1
5.4
50
100
100
UNIT
ns
ns
MHz
7.10 Typical Characteristics
4
Input
Output
3.5
3
Voltage (V)
2.5
2
1.5
1
0.5
0
-0.5
0
5
10
Time (ns)
15
20
Figure 7-1. Signal Integrity (1.8 V to 3.3 V Translation Up at 50 MHz)
8
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LSF0204 LSF0204D
LSF0204, LSF0204D
www.ti.com
SLVSCP5H – JULY 2014 – REVISED APRIL 2021
8 Parameter Measurement Information
VT
RL
USAGE
SWITCH
Translating up
Translating down
S1
S2
S1
Open
From Output
Under Test
S2
3.3 V
Input
VM
VM
VIL
CL
(see Note A)
5V
Output
VM
VM
LOAD CIRCUIT
VOL
TRANSLATING UP
5V
Input
VM
VM
VIL
2V
Output
VM
VM
VOL
TRANSLATING DOWN
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
C. The outputs are measured one at a time, with one transition per measurement.
Figure 8-1. Load Circuit for Outputs
Vref_B
S1
500 Ω
Open
From Output
Under Test
15 pF
TEST
S1
tPZL/tPLZ
Vref_B
Figure 8-2. Load Circuit for Enable/Disable Time Measurement
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LSF0204 LSF0204D
9
LSF0204, LSF0204D
www.ti.com
SLVSCP5H – JULY 2014 – REVISED APRIL 2021
8.1 Load Circuit AC Waveform for Outputs
tr 2.0 ns
tf 2.0 ns
VCCA
90%
Input
(An, Bn)
50%
10%
GND
VOH
Output
(Bn, An)
VOL
tpLH
tpHL
Figure 8-3. tPLH, tPHL
tr 2.0 ns
tf 2.0 ns
VCCA
90%
Output Enabled
Control OE, OE
50%
10%
GND
tpLZ
tpZL
VOH
Output (An or Bn)
Low to off to Low
50%
10%
Outputs
enabled
Outputs
disabled
Outputs
enabled
Figure 8-4. tPLZ, tPZL
10
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LSF0204 LSF0204D
LSF0204, LSF0204D
www.ti.com
SLVSCP5H – JULY 2014 – REVISED APRIL 2021
9 Detailed Description
9.1 Overview
The LSF Family may be used in level translation applications for interfacing devices or systems operating at
different interface voltages with one another. The LSF Family is ideal for use in applications where an open-drain
driver is connected to the data I/Os. LSF can achieve 100 MHz with the appropriate pull-up resistors and layout.
The LSF Family may also be used in applications where a push-pull driver is connected to the data I/Os.
9.2 Functional Block Diagram
LSF0204
200 KΩ
Vref_B
Vref_A
Level Converter
EN
A1
B1
A2
B2
A3
B3
A4
B4
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LSF0204 LSF0204D
11
LSF0204, LSF0204D
www.ti.com
SLVSCP5H – JULY 2014 – REVISED APRIL 2021
9.3 Feature Description
9.3.1 Support High Speed Translation, Greater than 100 MHz
Allows the LSF family to support more consumer or telecom interfaces (MDIO or SDIO).
9.3.2 Bidirectional Voltage Translation Without DIR Terminal
Minimizes system effort to develop voltage translation for bidirectional interface (PMBus, I2C, or SMbus).
9.3.3 5-V Tolerance on IO Port and 125°C Support
The LSF family, with 5-V tolerance and 125°C support, is flexible and compliant with TTL levels in industrial and
telecom applications.
9.3.4 Channel Specific Translation
The LSF family is able to set up different voltage translation levels on each channel.
9.3.5 Ioff, Partial Power Down Mode
When Vref_A, Vref_B = 0, all of data pins and EN pin are Hi-Z.
EN logic circuit is supplied by Vref_A, once Vref_A power up first and all of data pins are unknown state until Vref_B
and EN ready. No power sequence is required to enable LSF0204 and operate function normally.
9.4 Device Functional Modes
Table 9-1 lists the device functional modes of the LSF0204x family of devices.
Table 9-1. Function Table
(1)
12
INPUT EN(1) TERMINAL
FUNCTION
H
An = Bn
L
Hi-Z
EN is controlled by Vref_A logic levels.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LSF0204 LSF0204D
LSF0204, LSF0204D
www.ti.com
SLVSCP5H – JULY 2014 – REVISED APRIL 2021
10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
LSF performs voltage translation for open-drain or push-pull interface. Table 10-1 provides some consumer/
telecom interfaces as reference in regards to the different channel numbers that are supported by the LSF
family.
Table 10-1. Voltage Translator for Consumer/Telecom Interface
PART NAME
CH#
INTERFACE
LSF0101
1
GPIO
LSF0102
2
GPIO, MDIO, SMBus, PMBus, I2C
LSF0204
4
GPIO, SPI. MDIO, SMBus, PMBus, I2C, UART, SVID
LSF0108
8
GPIO, MDIO, SDIO, SVID, UART, SMBus, PMBus, I2C, SPI
10.2 Typical Applications
10.2.1 I2C PMBus, SMBus, GPIO, Application
Vpu_1 = 3.3 V
Vpu_2 = 1.8 V
Vrev_A = 1.8 V Vrev_B = 3.3 V
1.8 V
enable signal
ON
LSF0204
Rpu
SDA
SCL
A2
A3
A4
Rpu
Rpu
EN
Rpu
A1
Vcc
Off
SW
SW
SW
SW
B1
B2
Vcc
SDA
SCL
B3
B4
GND
Figure 10-1. Bidirectional Translation to Multiple Voltage Levels
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LSF0204 LSF0204D
13
LSF0204, LSF0204D
www.ti.com
SLVSCP5H – JULY 2014 – REVISED APRIL 2021
10.2.1.1 Design Requirements
10.2.1.1.1 Enable, Disable, and Reference Voltage Guidelines
The LSF family has an EN input that is used to disable the device by setting EN LOW, which places all I/Os in
the high-impedance state. Since LSF family is switch-type voltage translator, the power consumption is very low.
It is recommended to always enable LSF family for bidirectional application (I2C, SMBus, PMBus, or MDIO).
Table 10-2. Application Operating Condition
SYMBOL
MIN
TYP
MAX
UNIT
Vref_A
Reference voltage (A)
0.8
4.5
V
Vref_B
Reference voltage (B)
Vref_A + 0.8
5.5
V
Input voltage on EN terminal
0
Vref_A
V
Pull-up supply voltage
0
Vref_B
V
VI(EN)
(1)
Vpu
(1)
PARAMETER
Refer VIH and VIL for VI(EN)
Also Vref_B is recommended to be at 1.0 V higher than Vref_A for best signal integrity.
The LSF Family is able to set different voltage translation level on each channel.
Note
Vref_A must be set as lowest voltage level.
10.2.1.2 Detailed Design Procedure
10.2.1.2.1 Bidirectional Translation
The controller output driver may be push-pull or open-drain (pull-up resistors may be required) and the
peripheral device output can be push-pull or open-drain (pull-up resistors are required to pull the Bn outputs
to Vpu).
Note
However, if either output is push-pull, data must be unidirectional or the outputs must be 3-state and
be controlled by some direction-control mechanism to prevent HIGH-to-LOW contentions in either
direction. If both outputs are open-drain, no direction control is needed.
In Figure 10-1, the reference supply voltage (Vref_A) is connected to the processor core power supply voltage.
When Vref_B is connected through to a 3.3 V Vpu power supply, and Vref_A is set 1.0V. The output of A3
and B4 has a maximum output voltage equal to Vref_A, and the bidirectional interface (Ch1/2, MDIO) has a
maximum output voltage equal to Vpu.
10.2.1.2.1.1 Pull-Up Resistor Sizing
The pull-up resistor value needs to limit the current through the pass transistor when it is in the ON state to about
15 mA. This ensures a pass voltage of 260 mV to 350 mV. If the current through the pass transistor is higher
than 15 mA, the pass voltage also is higher in the ON state. To set the current through each pass transistor at 15
mA, to calculate the pull-up resistor value use Equation 1.
Rpu = (Vpu – 0.35 V) / 0.015 A
(1)
Table 10-3 summarizes resistor values, reference voltages, and currents at 15 mA, 10 mA, and 3 mA. The
resistor value shown in the +10% column (or a larger value) should be used to ensure that the pass voltage of
the transistor is 350 mV or less. The external driver must be able to sink the total current from the resistors on
both sides of the LSF family device at 0.175 V, although the 15 mA applies only to current flowing through the
LSF family device.
14
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LSF0204 LSF0204D
LSF0204, LSF0204D
www.ti.com
SLVSCP5H – JULY 2014 – REVISED APRIL 2021
Table 10-3. Pullup Resistor Values
PULLUP RESISTOR VALUE (Ω)
15 mA
10 mA
3 mA
NOMINAL
+10%(1)
NOMINAL
+10%(1)
NOMINAL
+10%(1)
5V
310
341
465
512
1550
1705
3.3 V
197
217
295
325
983
1082
2.5 V
143
158
215
237
717
788
1.8 V
97
106
145
160
483
532
1.5 V
77
85
115
127
383
422
1.2 V
57
63
85
94
283
312
VDPU
(1)
+10% to compensate for VDD range and resistor tolerance
10.2.1.2.2 LS Family Bandwidth
The maximum frequency of the LSF family is dependent on the application. The device may operate at speeds
of >100 MHz gave the correct conditions. The maximum frequency is dependent upon the loading of the
application. The LSF family behaves like a standard switch where the bandwidth of the device is dictated by the
on resistance and on capacitance of the device.
Figure 10-2 shows a bandwidth measurement of the LSF family using a two-port network analyzer.
0
–1
–2
Gain (dB)
–3
–4
–5
–6
–7
–8
–9
0.1
1
10
100
Frequency (MHz)
1000
Figure 10-2. 3-dB Bandwidth
The 3-dB point of the LSF family is ≈600 MHz; however, this measurement is an analog type of measurement.
For digital applications, the signal should not degrade up to the fifth harmonic of the digital signal. The frequency
bandwidth should be at least five times the maximum digital clock rate. This component of the signal is important
in determining the overall shape of the digital signal. In the case of the LSF family, a digital clock frequency of
greater than 100 MHz may be achieved.
The LSF family does not provide any drive capability. Therefore higher frequency applications will require higher
drive strength from the host side. No pullup resistor is needed on the host side (3.3 V) if the LSF family is being
driven by standard CMOS totem pole output driver. Best practice is to minimize the trace length from the LSF
family on the sink side (1.8 V) to minimize signal degradation.
All fast edges have an infinite spectrum of frequency components; however, there is an inflection (or knee) in the
frequency spectrum of fast edges where frequency components higher than fknee are insignificant in determining
the shape of the signal.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LSF0204 LSF0204D
15
LSF0204, LSF0204D
www.ti.com
SLVSCP5H – JULY 2014 – REVISED APRIL 2021
To calculate the maximum practical frequency component, or the knee frequency (fknee), use the following
equations:
fknee = 0.5/RT (10–80%)
(2)
fknee = 0.4/RT (20–80%)
(3)
For signals with rise time characteristics based on 10- to 90-percent thresholds, fknee is equal to 0.5 divided by
the rise time of the signal. For signals with rise time characteristics based on 20% to 80% thresholds, which is
very common in many of today's device specifications, fknee is equal to 0.4 divided by the rise time of the signal.
Some guidelines to follow that will help maximize the performance of the device:
•
•
•
Keep trace length to a minimum by placing the LSF family close to the I2C output of the processor.
The trace length should be less than half the time of flight to reduce ringing and line reflections or nonmonotonic behavior in the switching region.
To reduce overshoots, a pullup resistor can be added on the 1.8 V side; be aware that a slower fall time is to
be expected.
10.2.1.3 Application Curve
4
Input
Output
Voltage (V)
3
2
1
0
±1
0
50
100
150
200 250 300 350
Time (ns)
400 450
500
Figure 10-3. Captured Waveform From Above I2C Set-Up (1.8 V to 3.3 V at 2.5 MHz)
16
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LSF0204 LSF0204D
LSF0204, LSF0204D
www.ti.com
SLVSCP5H – JULY 2014 – REVISED APRIL 2021
10.2.2 MDIO Application
Vpu_1 = 3.3 V
Vpu_2 = 1.0 V
Vrev_A = 1.0 V Vrev_B = 3.3 V
1.0 V
enable signal
ON
LSF0204
Rpu
MDC
MDIO
A2
A3
A4
Rpu
Rpu
EN
Rpu
A1
Vcc
Off
SW
SW
SW
SW
B1
B2
Vcc
MDC
MDIO
B3
B4
GND
Figure 10-4. Typical Application Circuit (MDIO/Bidirectional Interface)
10.2.2.1 Design Requirements
Refer to Design Requirements.
10.2.2.2 Detailed Design Procedure
Refer to Detailed Design Procedure
10.2.2.3 Application Curve
Input (3.3V)
Output (1.0V)
Figure 10-5. Captured Waveform From Above MDIO Setup
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LSF0204 LSF0204D
17
LSF0204, LSF0204D
www.ti.com
SLVSCP5H – JULY 2014 – REVISED APRIL 2021
10.2.3 Multiple Voltage Translation in Single Device, Application
Vrev_A = 1.8 V
Vrev_B = 3.3 V
Vpu_1 = 3.3 V
Vpu_2 = 1.8 V
1.8 V
enable signal
ON
LSF0204
Rpu Rpu
Off
A1
Vcc
Rpu
A2
Vpu = 1.0 V
MDIO
Vcc
GPIO
B3
SW
A4
MDC
B2
SW
A3
Vcc
B1
SW
MDC
MDIO
Rpu
EN
Rpu
B4
SW
GPIO
GND
10.2.3.1 Design Requirements
Refer to Design Requirements.
10.2.3.2 Detailed Design Procedure
Refer to Detailed Design Procedure
10.2.3.3 Application Curve
3.5
Input
Output
3
2.5
Voltage (V)
2
1.5
1
0.5
2.16E+1
1.92E+1
1.68E+1
1.44E+1
9.6E+0
7.2E+0
4.8E+0
0
2.4E+0
-0.5
1.2E+1
0
Time (ns)
Figure 10-6. Translation Down (3.3 V to 1.8 V) at 150 MHz
18
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LSF0204 LSF0204D
LSF0204, LSF0204D
www.ti.com
SLVSCP5H – JULY 2014 – REVISED APRIL 2021
11 Power Supply Recommendations
There are no power sequence requirements for the LSF Family. Refer to Section 10.2.1.1.1 for enabling and
reference voltage guidelines.
12 Layout
12.1 Layout Guidelines
The signal integrity is highly related with pull-up resistor and PCB capacitance condition because LSF Family is
switch-type level translator
•
•
•
Short signal trace as possible to reduce capacitance and minimize stub from pull-up resistor.
Place LSF close to high voltage side.
Select the appropriate pull-up resistor that applies to translation levels and driving capability of transmitter.
12.2 Layout Example
LSF0102
GND
Vref_A
A1
A2
1
2
3
4
8
7
6
5
EN
Short Signal Trace as possible
Vref_B
B1
B2
Minimize Stub as possible
Figure 12-1. Short Trace Layout
TP1
SD Controller
(1.8V IO)
LSF0108
SDIO level translator
SDIO Connector
(3.3V IO)
Device PCB
TP2
Figure 12-2. Device Placement
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LSF0204 LSF0204D
19
LSF0204, LSF0204D
www.ti.com
SLVSCP5H – JULY 2014 – REVISED APRIL 2021
3.5E+0
3E+0
Output
Input
3
2.5E+0
2.5
2E+0
2
Voltage (V)
1.5E+0
1E+0
5E-1
1.5
1
0.5
0
Time (ns)
3E+1
2.7E+1
2.4E+1
2.1E+1
1.8E+1
1.5E+1
Time (ns)
Figure 12-3. Waveform From TP1 (Pullup Resistor:
160-Ω and 50-pF Capacitance 3.3 to 1.8 V at 100
MHz)
20
1.2E+1
0
9E+0
-0.5
6E+0
2.5E+1
2.25E+1
2E+1
1.75E+1
1.5E+1
1.25E+1
7.5E+0
5E+0
2.5E+0
0
1E+1
0
-5E-1
3E+0
Voltage (V)
3.5
Intput
Output
Figure 12-4. Waveform From TP2 (Pullup Resistor:
160-Ω and 50-pF Capacitance 1.8 to 3.3 V at 100
MHz)
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LSF0204 LSF0204D
LSF0204, LSF0204D
www.ti.com
SLVSCP5H – JULY 2014 – REVISED APRIL 2021
13 Device and Documentation Support
13.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LSF0204 LSF0204D
21
LSF0204, LSF0204D
www.ti.com
SLVSCP5H – JULY 2014 – REVISED APRIL 2021
PACKAGE OUTLINE
LSF0204/LSF0204D
YZP0012-C01
DSBGA - 0.5 mm max height
SCALE 8.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A3
INDEX
AREA
D
C
0.5 MAX
SEATING PLANE
BALL TYP
0.19
0.15
0.05 C
1 TYP
SYMM
D
C
SYMM
1.5
TYP
D: Max = 1.972 mm, Min = 1.912 mm
B
0.5
TYP
E: Max = 1.472 mm, Min = 1.412 mm
A
12X
0.015
1
0.25
0.21
2
3
0.5 TYP
C A B
4224761/A 01/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
22
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LSF0204 LSF0204D
LSF0204, LSF0204D
www.ti.com
SLVSCP5H – JULY 2014 – REVISED APRIL 2021
EXAMPLE BOARD LAYOUT
LSF0204/LSF0204D
YZP0012-C01
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
12X (
0.225)
A
(0.5) TYP
B
SYMM
C
D
1
2
3
SYMM
LAND PATTERN EXAMPLE
SCALE:30X
0.05 MAX
( 0.225)
METAL
METAL
UNDER
MASK
0.05 MIN
( 0.225)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4224761/A 01/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017).
www.ti.com
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LSF0204 LSF0204D
23
LSF0204, LSF0204D
www.ti.com
SLVSCP5H – JULY 2014 – REVISED APRIL 2021
EXAMPLE STENCIL DESIGN
LSF0204/LSF0204D
YZP0012-C01
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
(R0.05) TYP
12X ( 0.25)
A
(0.5)
TYP
B
SYMM
METAL
TYP
C
D
1
3
2
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4224761/A 01/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
24
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LSF0204 LSF0204D
PACKAGE OPTION ADDENDUM
www.ti.com
1-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LSF0204DPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LSF204D
LSF0204DRGYR
ACTIVE
VQFN
RGY
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LSF24D
LSF0204DRUTR
ACTIVE
UQFN
RUT
12
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
SIO
LSF0204DYZPR
ACTIVE
DSBGA
YZP
12
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
G6
LSF0204PWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LSF204
LSF0204RGYR
ACTIVE
VQFN
RGY
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LSF24
LSF0204RUTR
ACTIVE
UQFN
RUT
12
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
SIN
LSF0204YZPR
ACTIVE
DSBGA
YZP
12
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
G5
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
