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LSF0204, LSF0204D
ZHCSD68A – JULY 2014 – REVISED DECEMBER 2014
LSF0204x 适用于漏极开路和推挽应用的 4 位双向多电压电平转换器
1 特性
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1
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•
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用无方向端子提供双向电压转换
最大传播延迟少于 1.5ns
支持高速转换，大于 100MHz
支持 Ioff，局部断电模式（请参见Feature
Description）
可实现以下电压之间的双向电压电平转换
– 1.0V ↔ 1.8/2.5/3.3/5V
– 1.2V ↔ 1.8/2.5/3.3/5V
– 1.8V ↔ 2.5/3.3/5V
– 2.5V ↔ 3.3/5V
– 3.3V ↔ 5V
低待机电流
支持 TTL 的 5V 耐受 I/O 端口
低导通电阻 Ron 提供较少的信号失真
针对 EN 为低电平的高阻抗 I/O 端子
直通引脚分配以简化印刷电路板 (PCB) 走线路由
锁断性能超过 100mA，符合 JESD17 规范
-40°C 至 125°C 工作温度范围
静电放电 (ESD) 性能测试符合 JESD 22 规范
– 2000V 人体模型（A114-B，II 类）
– 200V 机器模型 (A115-A)
– 1000V 充电器件模型 (C101)
3 说明
LSF 系列是工作电压介于 1.0V 至 4.5V (Vref_A) 和
1.8V 至 5.5V (Vref_B) 之间的双向电压电平转换器。
此器件在无需方向端子的条件下便可在开漏或推挽应用
中实现 1.0V 至 5.0V 的双向电压转换。 对于采用
15pF 电容器和 165Ω 上拉电阻器的开漏系统，LSF 系
列支持传输速度大于 100MHz 电平转换应用。
当 An 或 Bn 端口为低电平时，此开关处于接通状态，
并且在 An 和 Bn 端口之间存在一个低电阻连接。 开关
的低 Ron 可用最小传播延迟和信号失真来实现连接。
A 端或 B 端的电压将限制为 Vref_A，且可上拉至
Vref_A 到 5V 之间的任何电压水平。利用此功能，可
在无需方向控制的情况下实现用户选择的较高和较低电
压间的无缝转换。
器件信息(1)
器件型号
封装
LSF0204x
封装尺寸（标称值）
薄型小外形尺寸封装
(TSSOP) (14)
5.00mm x 4.40mm
UQFN (12)
2.00mm × 1.70mm
VQFN (14)
3.50mm x 3.50mm
DSBGA (12)
1.90mm × 1.40mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
简化电路原理图
2 应用
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•
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•
GPIO，MDIO，PMBus，SMBus，SDIO，UART
，I2C，和其他电信基础设施中的接口
工业用
汽车用
个人计算
Vref_B
Vref_A
LSF0204
EN
A1
SW
B1
A2
SW
B2
A3
SW
B3
A4
SW
B4
GND
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLVSCP5
LSF0204, LSF0204D
ZHCSD68A – JULY 2014 – REVISED DECEMBER 2014
www.ti.com.cn
目录
1
2
3
4
5
6
7
8
特性 ..........................................................................
应用 ..........................................................................
说明 ..........................................................................
修订历史记录 ...........................................................
Description (Continued) ........................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
3
4
8.1
8.2
8.3
8.4
8.5
8.6
4
4
4
4
5
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics...........................................
Switching Characteristics: AC Performance
(Translating Down, 3.3 V to 1.8 V) ...........................
8.7 Switching Characteristics: AC Performance
(Translating Down, 3.3 V to 1.2 V) ...........................
8.8 Switching Characteristics: AC Performance
(Translating Up, 1.8 V to 3.3 V) ................................
8.9 Switching Characteristics: AC Performance
(Translating Up, 1.2 V to 1.8 V) ................................
5
8.10 Typical Characteristics ............................................ 6
9
Parameter Measurement Information .................. 7
9.1 Load Circuit AC Waveform for Outputs .................... 8
10 Detailed Description ............................................. 9
10.1
10.2
10.3
10.4
Overview ................................................................. 9
Functional Block Diagram ....................................... 9
Feature Description............................................... 10
Device Functional Modes...................................... 10
11 Application and Implementation........................ 11
11.1 Application Information.......................................... 11
11.2 I2C PMBus, SMBus, GPIO, Application................ 11
12 Power Supply Recommendations ..................... 17
13 Layout................................................................... 17
13.1 Layout Guidelines ................................................. 17
13.2 Layout Example .................................................... 17
14 器件和文档支持 ..................................................... 19
6
6
6
14.1
14.2
14.3
14.4
相关链接................................................................
商标 .......................................................................
静电放电警告.........................................................
术语表 ...................................................................
19
19
19
19
15 机械封装和可订购信息 .......................................... 19
4 修订历史记录
Changes from Original (November 2014) to Revision A
Page
•
从首页产品预览更改为完整数据表 .......................................................................................................................................... 1
•
已将说明中的文本从“传输速度大于 100Mbps”改为“传输速度大于 100MHz” .......................................................................... 1
2
Copyright © 2014, Texas Instruments Incorporated
LSF0204, LSF0204D
www.ti.com.cn
ZHCSD68A – JULY 2014 – REVISED DECEMBER 2014
5 Description (Continued)
The supply voltage (Vpu#) for each channel can be individually set up with a pull up resistor. For example, CH1
can be used in up-translation mode (1.2 V ↔ 3.3 V) and CH2 in down-translation mode (2.5 V ↔ 1.8 V).
When EN is HIGH, the translator switch is on, and the An I/O is connected to the Bn I/O, respectively, allowing
bidirectional data flow between ports. When EN is LOW, the translator switch is off, and a high-impedance state
exists between ports. The EN input circuit is designed to be supplied by Vref_A. To ensure the high-impedance
state during power-up or power-down, EN must be LOW.
6 Device Comparison Table
PART
NUMBER
EN
An
Bn
DESCRIPTION
LSF0204D
H
Place all data pins in 3 state mode
(Hi-Z)
Place all data pins in 3 state mode (Hi-Z)
LSF0204D
L
Input or output
Input or output
LSF0204
H
Input or output
Input or output
L
Place all data pins in 3 state mode
(Hi-Z)
Place all data pins in 3 state mode (Hi-Z)
LSF0204
3-state output mode enable
(active Low; referenced to Vref_A)
3-state output mode enable
(active High, referenced to Vref_A)
7 Pin Configuration and Functions
PW Package
(TOP VIEW)
RGY Package
(TOP VIEW)
RUT Package
(TOP VIEW)
EN
Vref_A 1
A1 2
A2 3
14 Vref_B
Vref_A
1
12
11
Vref_B
B1
13 B1
A1
2
10
12 B2
A2
A3
A4
3
9
B2
A1
4
8
B3
B4
Vref_A
Vref_B
1
14
2
13
B1
A2
3
12
A3
4
11
B2
B3
A3 4
11 B3
A4 5
10 B4
NC 6
9 NC
A4
5
10
B4
GND 7
8 EN
NC
6
9
NC
5
6
7
GND
7
8
GND
EN
Pin Functions
PIN
DESCRIPTION
An/Bn
Data Port
EN
Switch enable input;
LSF0204: EN is high-active
LSF0204D: EN is low-active
Vref_A
Reference supply voltage; see Application and Implementation section
Vref_B
Reference supply voltage; see Application and Implementation section.
Copyright © 2014, Texas Instruments Incorporated
3
LSF0204, LSF0204D
ZHCSD68A – JULY 2014 – REVISED DECEMBER 2014
www.ti.com.cn
8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
Input voltage range (2)
VI
VI/O
Input/output voltage range
MAX
–0.5
(2)
–0.5
7
Continuous channel current
IIK
Input clamp current
Tstg
Storage temperature range
(1)
(2)
UNIT
7
VI < 0
–65
V
V
128
mA
–50
mA
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and input/output negative-voltage ratings may be exceeded if the input and input/output clamp-current ratings are observed.
8.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VI/O
Input/output voltage
0
5
Vref_A/B/EN
Reference voltage
0
IPASS
Pass transistor current
TA
Operating free-air temperature
–40
UNIT
V
5
V
64
mA
125
°C
8.4 Thermal Information
THERMAL METRIC (1)
LSF0204
RGY (14 Pins)
RUT (12 Pins)
PW (14 PIns)
157.9
RθJA
Junction-to-ambient thermal resistance
83.2
195.8
RθJC(top)
Junction-to-case (top) thermal resistance
98.2
98.7
82.3
RθJB
Junction-to-board thermal resistance
59.2
122.6
100.0
ψJT
Junction-to-top characterization parameter
17.4
6.2
22.9
ψJB
Junction-to-board characterization parameter
59.4
122.6
99.0
RθJC(bot)
Junction-to-case (bottom) thermal resistance
38.7
N/A
N/A
(1)
4
UNIT
°C
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2014, Texas Instruments Incorporated
LSF0204, LSF0204D
www.ti.com.cn
ZHCSD68A – JULY 2014 – REVISED DECEMBER 2014
8.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
VIK
II = -18 mA,
VEN = 0
–1.2
V
IIH
VI = 5 V
VEN = 0
5.0
µA
ICCBA
Leakage from
Vref_B to
Vref_A
Vref_B = 3.3 V, Vref_A = 1.8 V, VEN = Vref_A IO = 0, VI = 3.3 V or
GND
3.5
µA
ICCA + ICCB (2)
Total Current
through GND
Vref_B = 3.3 V, Vref_A = 1.8 V, VEN = Vref_A IO = 0, VI = 3.3 V or
GND
IIN
Control pin
current
Vref_B = 5.5 V, Vref_A = 4.5 V, VEN = 0 to Vref_A IO = 0
±1
µA
Ioff
Power Off
Leakage
Current
Vref_B = Vref_A = 0 V, VEN = GND IO = 0, VI = 5 V or GND
±1
µA
CI(ref_A/B/EN)
VI = 3 V or 0
Cio(off)
VO = 3 V or 0,
VEN = 0
Cio(on)
VO = 3 V or 0,
VEN = Vref_A
VIH (EN pin)
High-level input voltage (3)
Vref_A = 1.5 V to 4.5 V
VIL (EN pin)
Low-level input voltage
Vref_A = 1.5 V to 4.5 V
VIH (EN pin)
High-level input voltage
Vref_A= 1.0 V to 1.5 V
VIL (EN pin)
Low-level input voltage
Vref_A = 1.0 V to 1.5 V
∆t/∆v (EN pin)
Input transition rise or fall rate for EN pin
ron
(1)
(2)
(3)
(4)
(4)
0.2
µA
7
pF
5.0
6.0
pF
10.5
13
pF
0.7×Vref_A
V
0.3×Vref_A
0.8×Vref_A
V
V
0.3×Vref_A
10
V
ns/V
Vref_A = VEN = 3.3 V; Vref_B = 5 V
3
Vref_A = VEN = 1.8 V; Vref_B = 5 V
4
Vref_A = VEN = 1.0 V; Vref_B = 5 V
9
Vref_A = VEN = 1.8 V; Vref_B = 5 V
4
IO = 32 mA
Vref_A = VEN = 2.5 V; Vref_B = 5 V
10
Ω
IO = 15 mA
Vref_A = VEN = 3.3 V; Vref_B = 5 V
5
Ω
VI = 1.0 V,
IO = 10 mA
Vref_A = VEN = 1.8 V; Vref_B = 3.3 V
8
Ω
VI = 0 V,
IO = 10 mA
Vref_A = VEN = 1.0 V; Vref_B = 3.3 V
6
Ω
VI = 0 V,
IO = 10 mA
Vref_A = VEN = 1.0 V; Vref_B = 1.8 V
6
Ω
VI = 0,
IO = 64 mA
VI = 0,
IO = 32 mA
VI = 0,
VI = 1.8 V,
Ω
Ω
All typical values are at TA = 25°C.
The actual supply current for LSF0204 is ICCA + ICCB; the leakage from Vref_B to Vref_A can be measured on Vref_A and Vref_B pin
Enable pin test conditions are for the LSF0204. The enable pin test conditions for LSF0204D are oppositely set.
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is
determined by the lowest voltage of the two (A or B) terminals.
8.6 Switching Characteristics: AC Performance (Translating Down, 3.3 V to 1.8 V)
over recommended operating free-air temperature range, Vrev-A = 1.8 V, Vrev-B = 3.3 V, VEN = 1.8 V, Vpu_1 = 3.3 V,
Vpu_2 = 1.8 V, RL = NA, VIH = 3.3 V, VIL = 0 VM = 1.15 V (unless otherwise noted)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
CL = 50 pF
CL = 30 pF
CL = 15 pF
UNIT
TYP
MAX
TYP
MAX
TYP
MAX
0.7
5.49
0.5
5.29
0.3
5.19
ns
0.9
4.9
0.7
4.7
0.5
4.5
ns
13
18
12
16.5
11
15
ns
tPZL
33
45
30
40
23
37
fMAX
50
tPLH
tPHL
tPLZ
A or B
B or A
Copyright © 2014, Texas Instruments Incorporated
100
100
ns
MHz
5
LSF0204, LSF0204D
ZHCSD68A – JULY 2014 – REVISED DECEMBER 2014
www.ti.com.cn
8.7 Switching Characteristics: AC Performance (Translating Down, 3.3 V to 1.2 V)
over recommended operating free-air temperature range Vrev-A = 1.2 V, Vrev-B = 3.3 V, VEN = 1.2 V, Vpu_1 = 3.3 V,
Vpu_2 = 1.2 V, RL = NA, VIH = 3.3V, VIL = 0 VM = 0.85 V (unless otherwise noted)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
A or B
B or A
tPLH
tPHL
fMAX
CL = 50 pF
CL = 30 pF
CL = 15 pF
TYP
MAX
TYP
MAX
TYP
MAX
0.8
4.1
0.5
3.9
0.3
3.8
0.9
4.7
0.7
4.5
0.6
4.3
50
100
100
UNIT
ns
ns
MHz
8.8 Switching Characteristics: AC Performance (Translating Up, 1.8 V to 3.3 V)
over recommended operating free-air temperature range Vrev-A = 1.8 V, Vrev-B = 3.3 V, VEN = 1.8 V, Vpu_1 = 3.3 V,
Vpu_2 = 1.8V, RL = 500 Ω, VIH = 1.8V, VIL = 0 VM = 0.9V (unless otherwise noted)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
CL = 50 pF
CL = 30 pF
CL = 15 pF
UNIT
TYP
MAX
TYP
MAX
TYP
MAX
tPLH
0.6
5.7
0.4
5.3
0.2
5.13
ns
tPHL
1.3
6.7
1
6.4
0.7
5.3
ns
13
18
12
16.5
11
15
ns
tPZL
33
45
30
40
23
37
ns
fMAX
50
tPLZ
A or B
B or A
100
100
MHz
8.9 Switching Characteristics: AC Performance (Translating Up, 1.2 V to 1.8 V)
over recommended operating free-air temperature range, Vrev-A = 1.2 V, Vrev-B = 1.8 V, VEN = 1.2 V, Vpu_1 = 1.8 V,
Vpu_2 = 1.2 V, RL = 500 Ω, VIH = 1.2V, VIL = 0 VM = 0.6 V (unless otherwise noted)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
A or B
B or A
tPLH
tPHL
fMAX
CL = 50 pF
CL = 30 pF
CL = 15 pF
UNIT
TYP
MAX
TYP
MAX
TYP
MAX
0.65
7.25
0.4
7.05
0.2
6.85
ns
1.6
7.03
1.3
6.5
1
5.4
ns
50
100
100
MHz
8.10 Typical Characteristics
4
Input
Output
3.5
3
Voltage (V)
2.5
2
1.5
1
0.5
0
-0.5
0
5
10
Time (ns)
15
20
Figure 1. Signal Integrity (1.8 V to 3.3 V Translation Up at 50 MHz)
6
Copyright © 2014, Texas Instruments Incorporated
LSF0204, LSF0204D
www.ti.com.cn
ZHCSD68A – JULY 2014 – REVISED DECEMBER 2014
9 Parameter Measurement Information
VT
RL
USAGE
SWITCH
Translating up
Translating down
S1
S2
S1
Open
From Output
Under Test
S2
3.3 V
Input
VM
VM
VIL
CL
(see Note A)
5V
Output
VM
VM
LOAD CIRCUIT
VOL
TRANSLATING UP
5V
Input
VM
VM
VIL
2V
Output
VM
VM
VOL
TRANSLATING DOWN
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
C. The outputs are measured one at a time, with one transition per measurement.
Figure 2. Load Circuit for Outputs
Vref_B
S1
500 Ω
Open
From Output
Under Test
15 pF
TEST
S1
tPZL/tPLZ
Vref_B
Figure 3. Load Circuit for Enable/Disable Time Measurement
Copyright © 2014, Texas Instruments Incorporated
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LSF0204, LSF0204D
ZHCSD68A – JULY 2014 – REVISED DECEMBER 2014
www.ti.com.cn
9.1 Load Circuit AC Waveform for Outputs
tr 2.0 ns
tf 2.0 ns
VCCA
90%
Input
(An, Bn)
50%
10%
GND
VOH
Output
(Bn, An)
VOL
tpLH
tpHL
Figure 4. tPLH, tPHL
tr 2.0 ns
tf 2.0 ns
VCCA
90%
Output Enabled
Control OE, OE
50%
10%
GND
tpLZ
tpZL
VOH
Output (An or Bn)
Low to off to Low
50%
10%
Outputs
enabled
Outputs
disabled
Outputs
enabled
Figure 5. tPLZ, tPZL
8
Copyright © 2014, Texas Instruments Incorporated
LSF0204, LSF0204D
www.ti.com.cn
ZHCSD68A – JULY 2014 – REVISED DECEMBER 2014
10 Detailed Description
10.1 Overview
The LSF Family can be used in level translation applications for interfacing devices or systems operating at
different interface voltages with one another. The LSF Family is ideal for use in applications where an open-drain
driver is connected to the data I/Os. With appropriate pull-up resistors and layout, LSF can achieve 100 MHz.
The LSF Family can also be used in applications where a push-pull driver is connected to the data I/Os.
10.2 Functional Block Diagram
LSF0204
200 KΩ
Vref_B
Vref_A
Level Converter
EN
A1
B1
A2
B2
A3
B3
A4
B4
Copyright © 2014, Texas Instruments Incorporated
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LSF0204, LSF0204D
ZHCSD68A – JULY 2014 – REVISED DECEMBER 2014
www.ti.com.cn
10.3 Feature Description
10.3.1 Support High Speed Translation, Greater than 100 MHz
Allows the LSF family to support more consumer or telecom interfaces (MDIO or SDIO).
10.3.2 Bidirectional Voltage Translation Without DIR Terminal
Minimizes system effort to develop voltage translation for bidirectional interface (PMBus, I2C, or SMbus).
10.3.3 5V Tolerance on IO Port and 125°C Support
With 5 V tolerance and 125°C support, the LSF family is flexible and compliant with TTL levels in industrial and
telecom applications.
10.3.4 Channel Specific Translation
The LSF family is able to set up different voltage translation levels on each channel.
10.3.5 Ioff, Partial Power Down Mode
When Vref_A, Vref_B = 0, all of data pins and EN pin are Hi-Z.
Since EN logic circuit is supplied by Vref_A, once Vref_A power up first, all of data pins are unknown state until
Vref_B and EN ready. No power sequence requirement to enable LSF0204 and operate function normally.
10.4 Device Functional Modes
Function Table
(1)
10
INPUT EN (1) TERMINAL
FUNCTION
H
An = Bn
L
Hi-Z
EN is controlled by Vref_A logic levels.
Copyright © 2014, Texas Instruments Incorporated
LSF0204, LSF0204D
www.ti.com.cn
ZHCSD68A – JULY 2014 – REVISED DECEMBER 2014
11 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
11.1 Application Information
LSF is able to perform voltage translation for open-drain or push-pull interface. Table 1 provides some
consumer/telecom interfaces as reference in regards to the different channel numbers that are supported by the
LSF family.
Table 1. Voltage Translator for Consumer/Telecom Interface
PART NAME
CH#
INTERFACE
LSF0101
1
GPIO
LSF0102
2
GPIO, MDIO, SMBus, PMBus, I2C
LSF0204
4
SPI. MDIO, SMBus, PMBus, I2C, UART, SVID
LSF0108
8
GPIO, MDIO, SDIO, SVID, UART, SMBus, PMBus, I2C, SPI
11.2 I2C PMBus, SMBus, GPIO, Application
Vpu_1 = 3.3 V
Vpu_2 = 1.8 V
Vrev_A = 1.8 V Vrev_B = 3.3 V
1.8 V
enable signal
ON
LSF0204
Rpu
SDA
SCL
A2
A3
A4
Rpu
Rpu
EN
Rpu
A1
Vcc
Off
SW
SW
SW
SW
B1
B2
Vcc
SDA
SCL
B3
B4
GND
Figure 6. Bidirectional Translation to Multiple Voltage Levels
11.2.1 Design Requirements
11.2.1.1 Enable, Disable, and Reference Voltage Guidelines
The LSF family has an EN input that is used to disable the device by setting EN LOW, which places all I/Os in
the high-impedance state. Since LSF family is switch-type voltage translator, the power consumption is very low.
It is recommended to always enable LSF family for bidirectional application (I2C, SMBus, PMBus, or MDIO).
Copyright © 2014, Texas Instruments Incorporated
11
LSF0204, LSF0204D
ZHCSD68A – JULY 2014 – REVISED DECEMBER 2014
www.ti.com.cn
I2C PMBus, SMBus, GPIO, Application (continued)
Table 2. Application Operating Condition
SYMBOL
MAX
UNIT
Vref_A
Reference voltage (A)
1
4.5
V
Vref_B
Reference voltage (B)
Vref_A + 0.8
5.5
V
Input voltage on EN terminal
0
Vref_A
V
Pull-up supply voltage
0
Vref_B
V
VI(EN)
(1)
Vpu
(1)
PARAMETER
MIN
TYP
Refer VIH and VIL for VI(EN)
Also Vref_B is recommended to be at 1.0 V higher than Vref_A for best signal integrity.
LSF Family is able to set different voltage translation level on each channel
NOTE
Vref_A must be set as lowest voltage level.
11.2.2 Detailed Design Procedure
11.2.2.1 Bidirectional Translation
The master output driver can be push-pull or open-drain (pull-up resistors may be required) and the slave device
output can be push-pull or open-drain (pull-up resistors are required to pull the Bn outputs to Vpu).
However, if either output is push-pull, data must be unidirectional or the outputs must be 3-state and be
controlled by some direction-control mechanism to prevent HIGH-to-LOW contentions in either direction.
If both outputs are open-drain, no direction control is needed.
In Figure 6, the reference supply voltage (Vref_A) is connected to the processor core power supply voltage.
When Vref_B is connected through to a 3.3 V Vpu power supply, and Vref_A is set 1.0V. The output of A3 and
B4 has a maximum output voltage equal to Vref_A, and the bidirectional interface (Ch1/2, MDIO) has a maximum
output voltage equal to Vpu.
11.2.2.1.1 Pull-up Resistor Sizing
The pull-up resistor value needs to limit the current through the pass transistor when it is in the ON state to about
15 mA. This ensures a pass voltage of 260 mV to 350 mV. If the current through the pass transistor is higher
than 15 mA, the pass voltage also is higher in the ON state. To set the current through each pass transistor at 15
mA, to calculate the pull-up resistor value use Equation 1.
Rpu = (Vpu – 0.35 V) / 0.015 A
(1)
Table 3 summarizes resistor values, reference voltages, and currents at 15 mA, 10 mA, and 3 mA. The resistor
value shown in the +10% column (or a larger value) should be used to ensure that the pass voltage of the
transistor is 350 mV or less. The external driver must be able to sink the total current from the resistors on both
sides of the LSF family device at 0.175 V, although the 15 mA applies only to current flowing through the LSF
family device.
12
Copyright © 2014, Texas Instruments Incorporated
LSF0204, LSF0204D
www.ti.com.cn
ZHCSD68A – JULY 2014 – REVISED DECEMBER 2014
Table 3. Pull-up Resistor Values (1) (2)
PULL-UP RESISTOR VALUE (Ω)
VDPU
(1)
(2)
(3)
15 mA
10 mA
NOMINAL
+10%
(3)
3 mA
NOMINAL
+10% (3)
NOMINAL
+10% (3)
5V
310
341
465
512
1550
1705
3.3 V
197
217
295
325
983
1082
2.5 V
143
158
215
237
717
788
1.8 V
97
106
145
160
483
532
1.5 V
77
85
115
127
383
422
1.2 V
57
63
85
94
283
312
Calculated for VOL = 0.35 V
Assumes output driver VOL = 0.175 V at stated current
+10% to compensate for VDD range and resistor tolerance
11.2.2.2 LS Family Bandwidth
The maximum frequency of the LSF family is dependent on the application. The device can operate at speeds of
>100MHz gave the correct conditions. The maximum frequency is dependent upon the loading of the application.
The LSF family behaves like a standard switch where the bandwidth of the device is dictated by the on
resistance and on capacitance of the device.
Figure 7 shows a bandwidth measurement of the LSF family using a two-port network analyzer.
0
–1
–2
Gain (dB)
–3
–4
–5
–6
–7
–8
–9
0.1
1
10
100
Frequency (MHz)
1000
Figure 7. 3-dB Bandwidth
The 3-dB point of the LSF family is ≈600MHz; however, this measurement is an analog type of measurement.
For digital applications the signal should not degrade up to the fifth harmonic of the digital signal. The frequency
bandwidth should be at least five times the maximum digital clock rate. This component of the signal is very
important in determining the overall shape of the digital signal. In the case of the LSF family, a digital clock
frequency of greater than 100 MHz can be achieved.
The LSF family does not provide any drive capability. Therefore higher frequency applications will require higher
drive strength from the host side. No pull-up resistor is needed on the host side (3.3 V) if the LSF family is being
driven by standard CMOS totem pole output driver. Ideally, it is best to minimize the trace length from the LSF
family on the sink side (1.8 V) to minimize signal degradation.
All fast edges have an infinite spectrum of frequency components; however, there is an inflection (or "knee") in
the frequency spectrum of fast edges where frequency components higher than fknee are insignificant in
determining the shape of the signal.
Copyright © 2014, Texas Instruments Incorporated
13
LSF0204, LSF0204D
ZHCSD68A – JULY 2014 – REVISED DECEMBER 2014
www.ti.com.cn
To calculate the maximum "practical" frequency component, or the "knee" frequency (fknee), use the following
equations:
fknee = 0.5/RT (10–80%)
fknee = 0.4/RT (20–80%)
(2)
(3)
For signals with rise time characteristics based on 10- to 90-percent thresholds, fknee is equal to 0.5 divided by
the rise time of the signal. For signals with rise time characteristics based on 20% to 80% thresholds, which is
very common in many of today's device specifications, fknee is equal to 0.4 divided by the rise time of the signal.
Some guidelines to follow that will help maximize the performance of the device:
• Keep trace length to a minimum by placing the LSF family close to the I2C output of the processor.
• The trace length should be less than half the time of flight to reduce ringing and line reflections or nonmonotonic behavior in the switching region.
• To reduce overshoots, a pull-up resistor can be added on the 1.8 V side; be aware that a slower fall time is to
be expected.
11.2.3 Application Curve
4
Input
Output
Voltage (V)
3
2
1
0
±1
0
50
100
150
200 250 300 350
Time (ns)
400 450
500
Figure 8. Captured Waveform From Above I2C Set-Up (1.8 to 3.3 V at 2.5 MHz)
14
Copyright © 2014, Texas Instruments Incorporated
LSF0204, LSF0204D
www.ti.com.cn
ZHCSD68A – JULY 2014 – REVISED DECEMBER 2014
11.2.4 MDIO Application
Vpu_1 = 3.3 V
Vpu_2 = 1.0 V
Vrev_A = 1.0 V Vrev_B = 3.3 V
1.0 V
enable signal
ON
LSF0204
Rpu
MDC
MDIO
A2
A3
A4
Rpu
Rpu
EN
Rpu
A1
Vcc
Off
SW
SW
SW
SW
B1
B2
Vcc
MDC
MDIO
B3
B4
GND
Figure 9. Typical Application Circuit (MDIO/Bidirectional Interface)
11.2.4.1 Design Requirements
Refer to Design Requirements.
11.2.4.2 Detailed Design Procedure
Refer to Detailed Design Procedure
11.2.4.3 Application Curve
Input (3.3V)
Output (1.0V)
Figure 10. Captured Waveform From Above MDIO Setup
Copyright © 2014, Texas Instruments Incorporated
15
LSF0204, LSF0204D
ZHCSD68A – JULY 2014 – REVISED DECEMBER 2014
www.ti.com.cn
11.2.5 Multiple Voltage Translation in Single Device, Application
Vrev_A = 1.8 V
Vrev_B = 3.3 V
Vpu_1 = 3.3 V
Vpu_2 = 1.8 V
1.8 V
enable signal
ON
LSF0204
Rpu Rpu
Off
A1
Vcc
Rpu
A2
Vpu = 1.0 V
MDIO
Vcc
GPIO
B3
SW
A4
MDC
B2
SW
A3
Vcc
B1
SW
MDC
MDIO
Rpu
EN
Rpu
B4
SW
GPIO
GND
11.2.5.1 Design Requirements
Refer to Design Requirements.
11.2.5.2 Detailed Design Procedure
Refer to Detailed Design Procedure
11.2.5.3 Application Curves
3.5
Input
Output
3
2.5
Voltage (V)
2
1.5
1
0.5
2.16E+1
1.92E+1
1.68E+1
1.44E+1
9.6E+0
7.2E+0
4.8E+0
0
2.4E+0
-0.5
1.2E+1
0
Time (ns)
Figure 11. Translation Down (3.3 to 1.8 V) at 150 MHz
16
Copyright © 2014, Texas Instruments Incorporated
LSF0204, LSF0204D
www.ti.com.cn
ZHCSD68A – JULY 2014 – REVISED DECEMBER 2014
12 Power Supply Recommendations
There are no power sequence requirements for the LSF Family. For enable and reference voltage guidelines,
refer to the Enable, Disable, and Reference Voltage Guidelines.
13 Layout
13.1 Layout Guidelines
Since LSF Family is switch-type level translator, the signal integrity is highly related with pull-up resistor and PCB
capacitance condition.
• Short signal trace as possible to reduce capacitance and minimize stub from pull-up resistor.
• Place LSF close to high voltage side.
• Select the appropriate pull-up resistor that applies to translation levels and driving capability of transmitter.
13.2 Layout Example
LSF0102
GND
Vref_A
A1
A2
1
2
3
4
EN
8
7
6
5
Short Signal Trace as possible
Vref_B
B1
B2
Minimize Stub as possible
Figure 12. Short Trace Layout
TP1
SD Controller
(1.8V IO)
LSF0108
SDIO level translator
SDIO Connector
(3.3V IO)
Device PCB
TP2
Figure 13. Device Placement
版权 © 2014, Texas Instruments Incorporated
17
LSF0204, LSF0204D
ZHCSD68A – JULY 2014 – REVISED DECEMBER 2014
www.ti.com.cn
Layout Example (接
接下页)
2
Time (ns)
Figure 14. Waveform From TP1 (Pullup Resistor: 160 Ω
and 50-pF Capacitance 3.3 to 1.8 V at 100 MHz)
3E+1
2.7E+1
2.4E+1
2.1E+1
0
1.8E+1
-0.5
1.5E+1
2.5E+1
2.25E+1
7.5E+0
5E+0
0
2.5E+0
-5E-1
2E+1
0
1.75E+1
0
1.5E+1
0.5
1.25E+1
5E-1
1.2E+1
1
9E+0
1E+0
1.5
6E+0
Voltage (V)
2.5
2E+0
1.5E+0
Output
Input
3
2.5E+0
1E+1
Voltage (V)
3E+0
18
3.5
Intput
Output
3E+0
3.5E+0
Time (ns)
Figure 15. Waveform From TP2 (Pullup Resistor: 160 Ω
and 50-pF Capacitance 1.8 to 3.3 V at 100 MHz)
版权 © 2014, Texas Instruments Incorporated
LSF0204, LSF0204D
www.ti.com.cn
ZHCSD68A – JULY 2014 – REVISED DECEMBER 2014
14 器件和文档支持
14.1 相关链接
以下表格列出了快速访问链接。 范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购买
链接。
表 4. 相关链接
器件
产品文件夹
样片与购买
技术文档
工具与软件
支持与社区
LSF0204
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
LSF0204D
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
14.2 商标
All trademarks are the property of their respective owners.
14.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
14.4 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
15 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2014, Texas Instruments Incorporated
19
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IMPORTANT NOTICE
邮寄地址： 上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122
Copyright © 2014, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
21-Apr-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LSF0204DPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LSF204D
LSF0204DRGYR
ACTIVE
VQFN
RGY
14
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LSF24D
LSF0204DRUTR
ACTIVE
UQFN
RUT
12
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
SIO
LSF0204DYZPR
ACTIVE
DSBGA
YZP
12
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
G6
LSF0204PWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LSF204
LSF0204RGYR
ACTIVE
VQFN
RGY
14
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LSF24
LSF0204RUTR
ACTIVE
UQFN
RUT
12
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
SIN
LSF0204YZPR
ACTIVE
DSBGA
YZP
12
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
G5
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
21-Apr-2015
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jun-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LSF0204DPWR
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
LSF0204DRGYR
VQFN
RGY
14
3000
330.0
12.4
3.75
3.75
1.15
8.0
12.0
Q1
LSF0204DRUTR
UQFN
RUT
12
3000
180.0
9.5
1.9
2.3
0.75
4.0
8.0
Q1
LSF0204DYZPR
DSBGA
YZP
12
3000
180.0
8.4
1.63
2.08
0.69
4.0
8.0
Q2
LSF0204PWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
LSF0204RGYR
VQFN
RGY
14
3000
330.0
12.4
3.75
3.75
1.15
8.0
12.0
Q1
LSF0204RUTR
UQFN
RUT
12
3000
180.0
9.5
1.9
2.3
0.75
4.0
8.0
Q1
LSF0204YZPR
DSBGA
YZP
12
3000
180.0
8.4
1.63
2.08
0.69
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jun-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LSF0204DPWR
LSF0204DRGYR
TSSOP
PW
14
2000
364.0
364.0
27.0
VQFN
RGY
14
3000
367.0
367.0
35.0
LSF0204DRUTR
UQFN
RUT
12
3000
184.0
184.0
19.0
LSF0204DYZPR
DSBGA
YZP
12
3000
182.0
182.0
20.0
LSF0204PWR
TSSOP
PW
14
2000
364.0
364.0
27.0
LSF0204RGYR
VQFN
RGY
14
3000
367.0
367.0
35.0
LSF0204RUTR
UQFN
RUT
12
3000
184.0
184.0
19.0
LSF0204YZPR
DSBGA
YZP
12
3000
182.0
182.0
20.0
Pack Materials-Page 2
D: Max = 1.972 mm, Min =1.912 mm
E: Max = 1.472 mm, Min =1.412 mm
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