MAX207IDBG4

 
          ±    SLLS592B − OCTOBER 2003 − REVISED JANUARY 2004 D ESD Protection for RS-232 I/O Pins D D D D D D DB OR DW PACKAGE (TOP VIEW) − ±15 kV − Human-Body Model Meets or Exceeds the Requirements of TIA/EIA-232-F and ITU v.28 Standards Operates at 5-V VCC Supply Operates Up To 120 kbit/s External Capacitors . . . 4 × 0.1 µF Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II Applications − Battery-Powered Systems, PDAs, Notebooks, Laptops, Palmtop PCs, and Hand-Held Equipment DOUT3 DOUT1 DOUT2 RIN1 ROUT1 DIN2 DIN1 GND VCC C1+ V+ C1− 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 DOUT4 RIN2 ROUT2 DIN5 DOUT5 DIN4 DIN3 ROUT3 RIN3 V− C2− C2+ description/ordering information The MAX207 consists of five line drivers, three line receivers, and a dual charge-pump circuit with ±15-kV ESD protection pin to pin (serial-port connection pins, including GND). The device meets the requirements of TIA/EIA-232-F and provides the electrical interface between an asynchronous communication controller and the serial-port connector. The charge pump and four small external capacitors allow operation from a single 5-V supply. The devices operate at data signaling rates up to 120 kbit/s and a maximum of 30-V/µs driver output slew rate. ORDERING INFORMATION PACKAGE† TA 0°C 0 C to 70 70°C C SOIC (DW) SSOP (DB) −40°C −40 C to 85 85°C C SOIC (DW) ORDERABLE PART NUMBER Tube of 25 MAX207CDW Reel of 2000 MAX207CDWR Reel of 2000 MAX207CDBR Tube of 25 MAX207IDW Reel of 2000 MAX207IDWR TOP-SIDE MARKING MAX207C MA207C MAX207I SSOP (DB) Reel of 2000 MAX207IDBR MB207I † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2004, Texas Instruments Incorporated     !"#$ % &'!!($ #%  )'*+&#$ ,#$(!,'&$% &!" $ %)(&&#$% )(! $.( $(!"%  (/#% %$!'"($% %$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',( $(%$2  #++ )#!#"($(!%- POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 
 
          ±    SLLS592B − OCTOBER 2003 − REVISED JANUARY 2004 Function Tables EACH DRIVER INPUT DIN OUTPUT DOUT L H H L H = high level, L = low level EACH RECEIVER INPUT RIN OUTPUT ROUT L H H L Open H H = high level, L = low level, Open = input disconnected or connected driver off logic diagram (positive logic) 7 2 DIN1 DOUT1 6 3 DIN2 TTL/CMOS Inputs DOUT2 18 1 DIN3 DOUT3 19 24 DIN4 DOUT4 21 20 DIN5 DOUT5 5 4 ROUT1 TTL/CMOS Outputs RIN1 22 23 ROUT2 RIN2 17 ROUT3 2 RS-232 Outputs POST OFFICE BOX 655303 16 RIN3 • DALLAS, TEXAS 75265 RS-232 Inputs 
 
          ±    SLLS592B − OCTOBER 2003 − REVISED JANUARY 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V Positive charge pump voltage range, V+ (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC − 0.3 V to 14 V Negative charge pump voltage range, V− (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −14 V to 0.3 V Input voltage range, VI: Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V+ + 0.3 V Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 V Output voltage range, VO: Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V− − 0.3 V to V+ + 0.3 V Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC + 0.3 V Short-circuit duration: DOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous Package thermal impedance, θJA (see Notes 2 and 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W Operating virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to network GND. 2. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 4 and Figure 4) Supply voltage VIH VIL Driver high-level input voltage DIN Driver low-level input voltage DIN Driver input voltage DIN VI Receiver input voltage TA Operating free-air temperature MAX207C MAX207I MIN NOM MAX 4.5 5 5.5 2 UNIT V V 0.8 0 5.5 −30 30 0 70 −40 85 V V °C NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 5 V ± 0.5 V. electrical characteristics over recommended ranges of supply voltage (unless otherwise noted) (see Note 4 and Figure 4) PARAMETER ICC Supply current TEST CONDITIONS No load, VCC = 5 V, TA = 25°C MIN TYP MAX 11 20 UNIT mA NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 5 V ± 0.5 V. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 
 
          ±    SLLS592B − OCTOBER 2003 − REVISED JANUARY 2004 DRIVER SECTION electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note 4 and Figure 4) PARAMETER TEST CONDITIONS MIN TYP† VOH VOL High-level output voltage DOUT at RL = 3 kΩ to GND, DIN = GND 5 9 Low-level output voltage DOUT at RL = 3 kΩ to GND, DIN = VCC −5 −9 IIH IIL High-level input current Low-level input current VI = VCC VI at 0 V IOS‡ Short-circuit output current VCC = 5.5 V, VO = 0 V MAX UNIT V V µA 15 200 −15 −200 µA ±10 ±60 mA ro Output resistance VCC, V+, and V− = 0 V, VO = ±2 V 300 W † All typical values are at VCC = 5 V, and TA = 25°C. ‡ Short-circuit durations should be controlled to prevent exceeding the device absolute power-dissipation ratings, and not more than one output should be shorted at a time. NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 5 V ± 0.5 V. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note 4 and Figure 4) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT Maximum data rate CL = 50 to 1000 pF, One DOUT switching, RL = 3 kΩ to 7 kΩ, See Figure 1 tPLH (D) Propagation delay time, low- to high-level output CL = 2500 pF, all drivers loaded, RL = 3 kΩ, See Figure 1 2 µs tPHL (D) Propagation delay time, high- to low-level output CL = 2500 pF, all drivers loaded, RL = 3 kΩ, See Figure 1 2 µs tsk(p) Pulse skew§ CL = 150 pF to 2500 pF, RL = 3 kΩ to 7 kΩ, See Figure 2 300 ns SR(tr) Slew rate, transition region (see Figure 1) CL = 50 pF to 1000 pF VCC = 5 V RL = 3 kΩ to 7 kΩ, 120 3 kbit/s 6 30 V/µs TYP UNIT ±15 kV † All typical values are at VCC = 5 V, and TA = 25°C. § Pulse skew is defined as |tPLH − tPHL| of each channel of the same device. NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 5 V ± 0.5 V. ESD protection PIN DOUT, RIN 4 TEST CONDITIONS Human-Body Model POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
 
          ±    SLLS592B − OCTOBER 2003 − REVISED JANUARY 2004 RECEIVER SECTION electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note 4 and Figure 4) PARAMETER TEST CONDITIONS VOH VOL High-level output voltage VIT+ VIT− Positive-going input threshold voltage Vhys ri Input hysteresis (VIT+ − VIT−) MIN TYP† 3.5 VCC−0.4 V IOH = −1 mA IOL = 1.6 mA Low-level output voltage VCC = 5 V, VCC = 5 V, Negative-going input threshold voltage TA = 25°C TA = 25°C VI = ±3 V to ±25 V Input resistance MAX UNIT V 1.7 0.4 V 2.4 V 0.8 1.2 0.2 0.5 1 V V 3 5 7 kW † All typical values are at VCC = 5 V, and TA = 25°C. NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 5 V ± 0.5 V. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note 4 and Figure 3) PARAMETER TEST CONDITIONS tPLH tPHL Propagation delay time, low- to high-level output tsk(p) Pulse skew‡ CL= 150 pF Propagation delay time, high- to low-level output MIN TYP† MAX 0.5 10 µs 0.5 10 µs 300 UNIT ns † All typical values are at VCC = 5 V, and TA = 25°C. ‡ Pulse skew is defined as |tPLH − tPHL| of each channel of the same device. NOTE 4: Test conditions are C1−C4 = 0.1 µF, at VCC = 5 V ± 0.5 V. PARAMETER MEASUREMENT INFORMATION 3V Input Generator (see Note B) 1.5 V RS-232 Output 50 Ω RL 1.5 V 0V tPHL (D) CL (see Note A) Output tPLH (D) 3V −3 V TEST CIRCUIT SR(tr) + t PHL (D) 6V or t 3V −3 V VOH VOL VOLTAGE WAVEFORMS PLH (D) NOTES: A. CL includes probe and jig capacitance. B. The pulse generator has the following characteristics: PRR = 120 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns. Figure 1. Driver Slew Rate POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 
 
          ±    SLLS592B − OCTOBER 2003 − REVISED JANUARY 2004 PARAMETER MEASUREMENT INFORMATION 3V Generator (see Note B) RS-232 Output 50 Ω RL 1.5 V Input 1.5 V 0V CL (see Note A) tPHL (D) tPLH (D) VOH 50% 50% Output VOL TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The pulse generator has the following characteristics: PRR = 120 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns. Figure 2. Driver Pulse Skew Input 3V 1.5 V 1.5 V −3 V Output Generator (see Note B) 50 Ω CL (see Note A) tPHL (R) tPLH (R) VOH 50% Output 50% VOL TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns. Figure 3. Receiver Propagation Delay Times 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
 
          ±    SLLS592B − OCTOBER 2003 − REVISED JANUARY 2004 APPLICATION INFORMATION DOUT3 DOUT1 1 24 2 23 DOUT4 RIN2 5 kΩ 22 3 DOUT2 4 RIN1 ROUT2 5V 5 kΩ 400 kΩ 21 5 ROUT1 20 5V 400 kΩ 400 kΩ 19 5V GND 400 kΩ 7 18 8 17 + CBYPASS − = 0.1µF DIN4 5V 400 kΩ DIN1 DOUT5 5V 6 DIN2 DIN5 16 DIN3 ROUT3 RIN3 C4 = 0.1 µF 16 V 5 kΩ 9 C3 † = 0.1 µF 6.3 V VCC V− − + 10 11 C1 = 0.1 µF 6.3 V C1+ C2− 15 − 14 V+ − + + − 12 C2+ C1− + 13 C2 = 0.1 µF 16 V † C3 can be connected to VCC or GND. NOTES: A. Resistor values shown are nominal. B. Nonpolarized ceramic capacitors are acceptable. If polarized tantalum or electrolytic capacitors are used, they should be connected as shown. Figure 4. Typical Operating Circuit and Capacitor Values POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 
 
          ±    SLLS592B − OCTOBER 2003 − REVISED JANUARY 2004 APPLICATION INFORMATION capacitor selection The capacitor type used for C1−C4 is not critical for proper operation. The MAX207 requires 0.1-µF capacitors, although capacitors up to 10 µF can be used without harm. Ceramic dielectrics are suggested for the 0.1-µF capacitors. When using the minimum recommended capacitor values, make sure the capacitance value does not degrade excessively as the operating temperature varies. If in doubt, use capacitors with a larger (e.g., 2×) nominal value. The capacitors’ effective series resistance (ESR), which usually rises at low temperatures, influences the amount of ripple on V+ and V−. Use larger capacitors (up to 10 µF) to reduce the output impedance at V+ and V−. Bypass VCC to ground with at least 0.1 µF. In applications sensitive to power-supply noise generated by the charge pumps, decouple VCC to ground with a capacitor the same size as (or larger than) the charge-pump capacitors (C1−C4). ESD protection TI MAX207 devices have standard ESD protection structures incorporated on the pins to protect against electrostatic discharges encountered during assembly and handling. In addition, the RS232 bus pins (driver outputs and receiver inputs) of these devices have an extra level of ESD protection. Advanced ESD structures were designed to successfully protect these bus pins against ESD discharge of ±15-kV when powered down. ESD test conditions ESD testing is stringently performed by TI, based on various conditions and procedures. Please contact TI for a reliability report that documents test setup, methodology, and results. Human-Body Model The Human-Body Model (HBM) of ESD testing is shown in Figure 5, while Figure 6 shows the current waveform that is generated during a discharge into a low impedance. The model consists of a 100-pF capacitor, charged to the ESD voltage of concern, and subsequently discharged into the device under test (DUT) through a 1.5-kΩ resistor. RD 1.5 kΩ VHBM + − CS 100 pF DUT Figure 5. HBM ESD Test Circuit 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
 
          ±    SLLS592B − OCTOBER 2003 − REVISED JANUARY 2004 APPLICATION INFORMATION 1.5 VHBM = 2 kV DUT = 10-V, 1-Ω Zener Diode I DUT − A 1.0 0.5 0.0 0 50 100 150 200 Time − ns Figure 6. Typical HBM Current Waveform Machine Model The Machine Model (MM) ESD test applies to all pins using a 200-pF capacitor with no discharge resistance. The purpose of the MM test is to simulate possible ESD conditions that can occur during the handling and assembly processes of manufacturing. In this case, ESD protection is required for all pins, not just RS-232 pins. However, after PC board assembly, the MM test no longer is as pertinent to the RS-232 pins. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) MAX207CDB ACTIVE SSOP DB 24 60 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 MA207C MAX207CDBR ACTIVE SSOP DB 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 MA207C MAX207CDW ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 MAX207C MAX207CDWR ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 MAX207C MAX207IDB ACTIVE SSOP DB 24 60 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MB207I MAX207IDBR ACTIVE SSOP DB 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MB207I MAX207IDW ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MAX207I MAX207IDWR ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MAX207I (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of