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MAX3222
SLLS408H – JANUARY 2000 – REVISED OCTOBER 2016
MAX3222 3-V to 5.5-V Multichannel RS-232 Line Driver and Receiver With ±15-kV ESD
Protection
1 Features
3 Description
•
The MAX3222 consists of two line drivers, two line
receivers, and a dual charge-pump circuit with ±15-kV
ESD protection pin to pin (serial-port connection pins,
including GND). The device meets the requirements
of TIA/EIA-232-F and provides the electrical interface
between an asynchronous communication controller
and the serial-port connector. The charge pump and
four small external capacitors allow operation from a
single 3-V to 5.5-V supply. The device operates at
data signaling rates up to 250 kbit/s and a maximum
of 30-V/μs driver output slew rate.
1
•
•
•
•
•
•
•
•
RS-232 Bus-Pin ESD Protection Exceeds ±15 kV
Using Human-Body Model (HBM)
Meets or Exceeds the Requirements of
TIA/EIA-232-F and ITU v.28 Standards
Operates With 3-V to 5.5-V VCC Supply
Operates Up to 250 kbps
Two Drivers and Two Receivers
Low Standby Current: 1 µA Typical
External Capacitors: 4 × 0.1 µF
Accepts 5-V Logic Input With 3.3-V Supply
Alternative High-Speed Pin-Compatible Device
(1 Mbps)
– SNx5C3222
2 Applications
•
•
•
•
•
•
Battery-Powered Systems
PDAs
Notebooks
Laptops
Palmtop PCs
Hand-held Equipment
The MAX3222 can be placed in the power-down
mode by setting PWRDOWN low, which draws only 1
μA from the power supply. When the device is
powered down, the receivers remain active while the
drivers are placed in the high-impedance state.
Receiver outputs also can be placed in the highimpedance state by setting EN high.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
MAX3222CDW,
MAX322IDW
SOIC (20)
12.80 mm × 7.50 mm
MAX3222CDB,
MAX322IDB
SSOP (20)
7.20 mm × 5.30 mm
MAX3222CPW,
MAX322IPW
TSSOP (20)
6.50 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Block Diagram
DIN1
DIN2
PWRDOWN
EN
ROUT1
ROUT2
13
17
DOUT1
12
8
DOUT2
20
Powerdown
1
15
16
10
9
RIN1
RIN2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MAX3222
SLLS408H – JANUARY 2000 – REVISED OCTOBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
4
4
4
5
5
5
6
6
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics: Device..............................
Electrical Characteristics: Driver ...............................
Electrical Characteristics: Receiver ..........................
Switching Characteristics: Driver ..............................
Switching Characteristics: Receiver..........................
Typical Characteristics ............................................
Parameter Measurement Information .................. 8
Detailed Description ............................................ 10
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
11
11
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application ................................................. 12
10 Power Supply Recommendations ..................... 13
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 14
12 Device and Documentation Support ................. 15
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
15
15
15
15
15
13 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (March 2004) to Revision H
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Deleted ODERING INFORMATION table; see POA at the end of the datasheet. ................................................................ 3
•
Changed RθJA for DB, DW and PW package from: 70 °C/W to 84.4°C/W (DB), 58 °C/W to 70.2 °C/W (DW) and 83
°C/W to 94.3 °C/W (PW) in the Thermal Information table. ................................................................................................... 5
2
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5 Pin Configuration and Functions
DB, DW, or PW Package
20-Pin SOIC, SSOP, TSSOP
Top View
EN
C1+
V+
C1−
C2+
C2−
V−
DOUT2
RIN2
ROUT2
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
PWRDOWN
VCC
GND
DOUT1
RIN1
ROUT1
NC
DIN1
DIN2
NC
NC − No internal connection
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
C1+
2
—
Charge pump capacitor pin
C1-
4
—
Charge pump capacitor pin
C2+
5
—
Charge pump capacitor pin
C2-
6
—
Charge pump capacitor pin
DIN1
13
I
Driver logic input
DIN2
12
I
Driver logic input
DOUT1
17
O
RS-232 driver output
DOUT2
8
O
RS-232 driver output
Receiver enable, active low
EN
1
I
GND
18
—
Ground
11,14
—
No internal connection
PWRDOWN
20
I
Driver disable, active low
RIN1
16
I
RS-232 receiver input
RIN2
9
I
RS-232 receiver input
ROUT1
15
O
Receiver logic output
ROUT2
10
O
Receiver logic output
VCC
19
—
Power Supply
V+
3
—
Charge pump capacitor pin
V-
7
—
Charge pump capacitor pin
NC
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage, VCC (2)
Positive output supply voltage, V+
(2)
Negative output supply voltage, V– (2)
MIN
MAX
UNIT
–0.3
6
V
–0.3
7
V
0.3
-7
V
13
V
Supply voltage difference, V+ – V–
Input voltage, VI
Output voltage, VO
Drivers, EN, PWRDOWN
–0.3
6
Receiver
–25
25
Drivers
–13.2
13.2
Receivers
–0.3
VCC + 0.3
Operating virtual junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
–65
V
V
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to network GND.
6.2 ESD Ratings
VALUE
V(ESD)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
RIN, DOUT, and GND pins (1)
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
(1)
(2)
Pins 8, 9, 16, 17
and 18
±15000
All other pins
±3000
All pins
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1). See Figure 8.
Supply voltage
VCC = 3.3 V
VCC = 5 V
VIH
Driver and control high-level
input voltage
DIR, EN, PWRDOWN
VIL
Driver and control low-level
input voltage
DIR, EN, PWRDOWN
VI
Driver and control input voltage
DIR, EN, PWRDOWN
VI
Receiver input voltage
TA
(1)
4
Operating free-air temperature
VCC = 3.3 V
VCC = 5 V
MAX3222C
MAX3222I
MIN
NOM
MAX
3
3.3
3.6
4.5
5
5.5
2
UNIT
V
V
2.4
0.8
V
0
5.5
V
–25
25
V
0
70
–40
85
ºC
Test conditions are C1−C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2−C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
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6.4 Thermal Information
MAX3222
THERMAL METRIC (1) (2) (3)
DB (SSOP)
DW (SOIC)
PW (TSSOP)
UNIT
20 PINS
20 PINS
20 PINS
RθJA
Junction-to-ambient thermal resistance
84.4
70.2
94.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
44.1
36.2
29.9
°C/W
RθJB
Junction-to-board thermal resistance
40
37.9
45.1
°C/W
ψJT
Junction-to-top characterization parameter
11
11.1
1.4
°C/W
ψJB
Junction-to-board characterization parameter
39.5
37.5
44.6
°C/W
(1)
(2)
(3)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
The package thermal impedance is calculated in accordance with JESD 51-7.
6.5 Electrical Characteristics: Device
over operating free-air temperature range (unless otherwise noted) (1). See Figure 8.
PARAMETER
II
ICC
(1)
(2)
TEST CONDITIONS
MIN
Input leakage current (EN,
PWRDOWN)
Supply current
No load, PWRDOWN at VCC
Supply current (powered off)
No load, PWRDOWN at GND
TYP (2)
MAX
±0.01
±1
µA
0.3
1
mA
1
10
µA
UNIT
Test conditions are C1−C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2−C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
6.6 Electrical Characteristics: Driver
over operating free-air temperature range (unless otherwise noted) (1). See Figure 8.
PARAMETER
TEST CONDITIONS
MIN
TYP (2)
MAX
UNIT
VOH
High-level output voltage
DOUT at RL = 3 kΩ to GND, DIN =
GND
5
5.4
V
VOL
Low-level output voltage
DOUT at RL = 3 kΩ to GND, DIN =
VCC
–5
–5.4
V
IIH
High-level input current
VI = VCC
±0.01
±1
µA
IIL
Low-level input current
VI at GND
±0.01
±1
µA
±35
±60
mA
IOS
Short-circuit output current
ro
Output resistance
Ioff
(1)
(2)
Output leakage current
VCC = 3.6 V, VO = 0 V
VCC = 5.5 V, VO = 0 V
VCC, V+, and V– = 0 V, VO = ±2 V
300
10M
Ω
PWRDOWN = GND, VO = ±12 V,
VCC = 3 V to 3.6 V
±25
PWRDOWN = GND, VO = ±10 V,
VCC = 4.5 V to 5.5 V
±25
µA
Test conditions are C1−C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2−C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
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6.7 Electrical Characteristics: Receiver
over operating free-air temperature range (unless otherwise noted) (1). See Figure 8.
PARAMETER
MIN
TYP (2)
VCC – 0.6
VCC – 0.1
TEST CONDITIONS
MAX
VOH
High-level output voltage
IOH = –1 mA
VOL
Low-level output voltage
IOL = 1.6 mA
VIT+
Positive-going input threshold
voltage
VCC = 3.3 V
1.5
2.4
VCC = 5 V
1.8
2.4
VIT–
Negative-going input threshold
voltage
VCC = 3.3 V
0.6
1.2
VCC = 5 V
0.8
1.5
Vhys
Input hysteresis (VIT+ – VIT–)
Ioff
Output leakage current
EN = VCC
ri
Input resistance
VI = ±3 V to ±25 V
(1)
(2)
V
0.4
V
V
V
0.3
3
UNIT
V
±0.05
±10
µA
5
7
kΩ
Test conditions are C1−C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2−C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
6.8 Switching Characteristics: Driver
over operating free-air temperature range (unless otherwise noted) (1). See Figure 8.
PARAMETER
TEST CONDITIONS
MIN
TYP (2)
Maximum data rate
CL = 1000 pF, RL = 3 kΩ, One DOUT switching, see
Figure 3
150
250
kbps
tsk(p)
Pulse skew (3)
CL = 150 pF to 2500 pF, RL = 3 kΩ to 7 kΩ, see
Figure 4
300
ns
SR(tr)
Slew rate, transition region
(see Figure 3)
RL = 3 kΩ to 7 kΩ, VCC = 3.3
V
(1)
(2)
(3)
MAX
CL = 150 pF to 1000
pF
6
30
CL = 150 pF to 2500
pF
4
30
UNIT
V/µs
Test conditions are C1−C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2−C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
Pulse skew is defined as |tPLH − tPHL| of each channel of the same device.
6.9 Switching Characteristics: Receiver
over operating free-air temperature range (unless otherwise noted) (1). See Figure 8.
PARAMETER
TEST CONDITIONS
MIN
TYP (2)
MAX
UNIT
tPLH
Propagation delay time, low- to highCL = 150 pF, see Figure 5
level output
300
ns
tPHL
Propagation delay time, high- to lowCL = 150 pF, see Figure 5
level output
300
ns
ten
Output enable time
CL = 150 pF, RL = 3 kΩ, see
Figure 6
200
ns
tdis
Output disable time
CL = 150 pF, RL = 3 kΩ, see
Figure 6
200
ns
tsk(p)
Pulse skew (3)
See Figure 5
300
ns
(1)
(2)
(3)
6
Test conditions are C1−C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2−C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
Pulse skew is defined as |tPLH − tPHL| of each channel of the same device.
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6.10 Typical Characteristics
6
0
5
-1
4
-2
DOUT (V)
DOUT (V)
TA = 25° C; VCC = 3.3V
3
-3
2
-4
1
-5
0
-6
0
2
4
6
8
10
12
14
16
DOUT VOH vs. DOUT Current
18
20
0
2
D001
Figure 1. Driver VOH vs Load Current
4
6
8
10
12
14
16
DOUT VOL vs. DOUT Current
18
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D002
Figure 2. Driver VOL vs Load Current
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7 Parameter Measurement Information
3V
Input
Generator
(see Note B)
1.5 V
RS-232
Output
50 Ω
RL
1.5 V
0V
CL
(see Note A)
tTHL
3V
PWRDOWN
tTLH
VOH
3V
3V
Output
−3 V
−3 V
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
SR(tr)
t
THL
6V
or t
TLH
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
Figure 3. Driver Slew Rate
3V
Generator
(see Note B)
RS-232
Output
50 Ω
RL
Input
1.5 V
1.5 V
0V
CL
(see Note A)
tPHL
tPLH
VOH
3V
PWRDOWN
50%
50%
Output
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
Figure 4. Driver Pulse Skew
EN
0V
3V
Input
1.5 V
1.5 V
−3 V
Output
Generator
(see Note B)
50 Ω
tPHL
CL
(see Note A)
tPLH
VOH
50%
Output
50%
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
Figure 5. Receiver Propagation Delay Times
8
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Parameter Measurement Information (continued)
VCC
S1
GND
RL
Output
3 V or 0 V
CL
(see Note A)
EN
3V
Input
1.5 V
0V
tPZH
(S1 at GND)
tPHZ
S1 at GND)
VOH
Output
50%
0.3 V
Generator
(see Note B)
1.5 V
50 Ω
tPLZ
(S1 at VCC)
0.3 V
Output
50%
VOL
tPZL
(S1 at VCC)
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
Figure 6. Receiver Enable and Disable Times
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8 Detailed Description
8.1 Overview
The MAX3222 consists of two line drivers, two line receivers, and a dual charge-pump circuit with ±15-kV ESD
protection pin to pin (serial-port connection pins, including GND). The device meets the requirements of TIA/EIA232-F and provides the electrical interface between an asynchronous communication controller and the serialport connector. The charge pump and four small external capacitors allow operation from a single 3-V to 5.5-V
supply. The device operates at data signaling rates up to 250 kbit/s and a maximum of 30-V/μs driver output slew
rate.
The MAX3222 can be placed in the power-down mode by setting PWRDOWN low, which draws only 1 μA from
the power supply. When the device is powered down, the receivers remain active while the drivers are placed in
the high-impedance state. Also, during power down, the onboard charge pump is disabled; V+ is lowered to VCC,
and V− is raised toward GND. Receiver outputs also can be placed in the high-impedance state by setting EN
high.
8.2 Functional Block Diagram
DIN1
DIN2
PWRDOWN
EN
ROUT1
ROUT2
13
17
DOUT1
12
8
DOUT2
20
Powerdown
1
15
16
10
9
RIN1
RIN2
Figure 7. Logic Diagram (Positive Logic)
10
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8.3 Feature Description
8.3.1 Power
The power block increases, inverts, and regulates voltage at V+ and V- pins using a charge pump that requires
four external capacitors.
8.3.2 RS232 Driver
Two drivers interface standard logic level to RS232 levels. PWRDOWN input low turns driver off and
PWRDOWN input high turns driver on. Both DIN inputs and PWRDOWN input must be valid high or low. Do not
float logic input pins.
8.3.3 RS232 Receiver
Two receivers interface RS232 levels to standard logic levels. An open input will result in a high output on ROUT.
Each RIN input includes an internal standard RS232 load. EN input low turns on both ROUT pins. EN input high
puts both ROUT pins into high impedance state, output off. EN input must be valid high or low. Do not float logic
input pins.
8.4 Device Functional Modes
Driver and receiver outputs are controlled by the functional truth tables.
Table 1. Functional Table - Each Driver (1)
INPUTS
DIN
(1)
PWRDOWN
OUTPUT DOUT
X
L
Z
L
H
H
H
H
L
H = high level, L = low level, X = irrelevant, Z = high impedance
Table 2. Functional Table - Each Receiver (1)
INPUTS
(1)
RIN
EN
OUTPUT ROUT
L
L
H
L
H
L
X
H
Z
Open
L
H
H = high level, L = low level, X = irrelevant, Z = high impedance (off), Open = input disconnected or
connected driver off
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The MAX3222 interfaces a universal asynchronous receiver / transmitter (UART) to RS-232 port voltage levels.
External capacitors are used to generate RS-232 compliant voltages. For proper operation, add capacitors as
shown in Figure 8.
9.2 Typical Application
ROUT and DIN connect to UART or general purpose logic lines. RIN and DOUT lines connect to a RS232
connector or cable.
1
EN
Powerdown
2
VCC
C1+
+
C1
−
3
PWRDOWN
19
18
V+
+
20
+ C
BYPASS
− = 0.1 µF
GND
C3
−
17
4
DOUT1
C1−
5
16
C2+
RIN1
+
C2
−
6
7
−
C4
DOUT2
RIN2
ROUT2
15
C2−
ROUT1
14
V−
NC
+
8
13
9
12
10
11
DIN1
DIN2
NC
C3 can be connected to VCC or GND.
Resistor values shown are nominal.
NC − No internal connection
Nonpolarized ceramic capacitors are acceptable. If polarized tantalum or electrolytic capacitors are used, they should
be connected as shown.
Figure 8. Recommended Application Schematic
9.2.1 Design Requirements
•
•
Recommended VCC is 3.3 V or 5 V. 3 V to 5.5 V is also possible
Maximum recommended bit rate is 250 kbit/s.
Table 3. VCC vs Capacitor Values
12
VCC
C1
C2, C3, and C4
3.3 V ± 0.3 V
0.1 µF
0.1 µF
5 V ± 0.5 V
0.047 µF
0.33 µF
3 V ± 5.5 V
0.1 µF
0.47 µF
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9.2.2 Detailed Design Procedure
•
•
All DIN, PWRDOWN and EN inputs must be connected to valid low or high logic levels.
Select capacitor values based on VCC level for best performance.
8
8
6
6
4
4
Voltage (V)
Voltage (V)
9.2.3 Application Curves
2
0
-2
2
0
-2
DIN
DOUT
ROUT
-4
DIN
DOUT
ROUT
-4
-6
-6
0
1
2
3
4
5
6
Time (us)
7
8
9
10
0
1
D004
Figure 9. Loopback Waveforms
VCC = 3.3 V, Data Rate 250 kbit/s
2
3
4
5
6
Time (us)
7
8
9
10
D003
Figure 10. Loopback Waveforms with 1-nF load
VCC = 3.3 V, Data Rate 250 kbit/s
10 Power Supply Recommendations
VCC should be between 3 V and 5.5 V. Charge pump capacitors should be chosen using table in Table 3.
11 Layout
11.1 Layout Guidelines
Keep the external capacitor traces short. This is more important on C1 and C2 nodes that have the fastest rise
and fall times. Make the impedance from MAX3222 ground pin and circuit board's ground plane as low as
possible for best ESD performance. Use wide metal and multiple vias on both sides of ground pin
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13
MAX3222
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www.ti.com
11.2 Layout Example
1 EN
Ground
C3
PWRDOWN 20
2 C1+
VCC 19
VCC
PF
C1
3 V+
GND 18
4 C1-
DOUT1 17
5 C2+
RIN1 16
6 C2-
ROUT1 15
Ground
C2
7 V-
Ground
NC 14
C4
8 DOUT2
DIN1 13
9 RIN2
DIN2 12
10 ROUT2
NC 11
Figure 11. MAX3222 Layout
14
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Product Folder Links: MAX3222
MAX3222
www.ti.com
SLLS408H – JANUARY 2000 – REVISED OCTOBER 2016
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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15
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
MAX3222CDB
ACTIVE
SSOP
DB
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
MA3222C
Samples
MAX3222CDBR
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
MA3222C
Samples
MAX3222CDBRE4
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
MA3222C
Samples
MAX3222CDBRG4
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
MA3222C
Samples
MAX3222CDW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
MAX3222C
Samples
MAX3222CDWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
MAX3222C
Samples
MAX3222CPWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
MA3222C
Samples
MAX3222IDB
ACTIVE
SSOP
DB
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
MB3222I
Samples
MAX3222IDBR
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
MB3222I
Samples
MAX3222IDBRE4
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
MB3222I
Samples
MAX3222IDW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
MAX3222I
Samples
MAX3222IDWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
MAX3222I
Samples
MAX3222IPWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
MB3222I
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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