MCT8315A
SLLSFP7A – DECEMBER 2022 – REVISED APRIL 2023
MCT8315A High Speed Sensorless Trapezoidal Control Integrated FET BLDC Driver
1 Features
3 Description
•
The MCT8315A provides a single-chip, codefree sensorless trapezoidal solution for customers
requiring high speed operation (up to 3 kHz electrical)
or very fast start-up time (< 50 ms) for 12- to 24-V
brushless-DC motors requiring up to 4-A peak current.
The MCT8315A integrates three ½-bridges with 40V absolute maximum capability and a low RDS(ON)
of 240 mΩ (high-side + low-side FETs). MCT8315A
integrates power management circuits including an
voltage-adjustable buck regulator (3.3 V / 5 V, 170mA) and LDO (3.3 V, 20 mA) that can be used to
power external circuits.
•
•
•
•
•
•
•
•
•
•
2 Applications
•
•
•
•
•
•
Brushless-DC (BLDC) Motor Modules
Robotic Vacuum Suction Motors
Motor Cycle Fuel Pumps
Appliance Fans and Pumps
Automotive Fan and Blowers
CPAP Machines
Sensorless trapezoidal control is highly configurable
(motor start-up/stop behavior, fault handling, closed
loop operation) through register settings in a nonvolatile EEPROM, which allows the device to operate
stand-alone once it has been configured. The
MCT8315A receives a speed command through
a PWM signal, analog voltage, variable frequency
square wave or I2C instruction. There are a large
number of protection features integrated into the
MCT8315A to protect the device, motor, and system
against fault events.
Device Information(1)
PART NUMBER
MCT8315A1V
(1)
PACKAGE
BODY SIZE (NOM)
VQFN (40)
7.00 mm × 5.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
Documentation for reference:
• Refer MCT8315A tuning guide
• Refer to the MCT8315A EVM GUI
LDO out
3.3 V, up to 20 mA
Buck out
3.3 or 5.0 V, up to 170 mA
4.5 to 35 V (40 V abs max)
MCT8315A
SPEED
PWM, analog, frequency or
commanded over I2C
A
DIRECTION
BRAKE
FG
Speed feecback
B
Sensorless
Trap
EEPROM
A
C
nFAULT
I2C
Optional during operation for
I2C speed, diagnostics, or onthe-fly configuration
B
MOSFETs
•
•
•
Three-phase BLDC motor driver with integrated
sensorless motor control algorithm
– Code-free high speed Trapezoidal Control
– Supports up to 3 kHz (electrical frequency)
– Very fast start-up time (< 50 ms)
– Fast Deceleration (< 150 ms)
– Supports 120° or 150° modulation to improve
acoustic performance
– Windmilling support through forward
resynchronization and reverse drive
– Analog, PWM, freq. or I2C based speed input
– Active Demagnetization to reduce power losses
– Configurable motor start-up and stop options
– Closed speed/power loop options
– Anti-voltage surge (AVS) protection prevents
DC bus voltage spike during motor deceleration
4.5- to 35-V operating voltage (40-V abs max)
High output current capability: 4-A peak
Low MOSFET on-state resistance
– RDS(ON) (HS + LS) at TA = 25°C : 240-mΩ (typ.)
Low power sleep mode
– 5-µA (maximum) at VVM = 24-V, TA = 25°C
Speed loop accuracy: 3% with internal clock and
1% with external clock reference
Customer-configurable non-volatile memory
(EEPROM) to store device configuration
Supports up to 100-kHz PWM frequency for low
inductance motor support
Does not require external current sense resistors;
uses built-in current sensing
Built-in 3.3-V, 20-mA LDO regulator
Built-in 3.3-V/5-V, 170-mA buck regulator
Dedicated DRVOFF pin to disable (Hi-Z) outputs
Spread spectrum and slew rate for EMI mitigation
Suite of integrated protection features
– Supply under voltage lockout (UVLO)
– Supply over voltage protection (OVP)
– Motor lock detection (5 different types)
– Over current protection (OCP)
– Thermal warning and shutdown (OTW/TSD)
– Fault condition indication pin (nFAULT)
– Optional fault diagnostics over I2C interface
C
Buck/LDO Regulator
Integrated Current Sensing
DACOUTx
4-A peak output current,
typically 12 to 24 V
Optional real-time variable
monitoring, 12-bit DAC
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MCT8315A
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SLLSFP7A – DECEMBER 2022 – REVISED APRIL 2023
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................6
6.6 Characteristics of the SDA and SCL bus for
Standard and Fast mode.............................................12
6.7 Typical Characteristics.............................................. 14
7 Detailed Description......................................................15
7.1 Overview................................................................... 15
7.2 Functional Block Diagram......................................... 16
7.3 Feature Description...................................................17
7.4 Device Functional Modes..........................................70
7.5 External Interface......................................................70
7.6 EEPROM access and I2C interface.......................... 73
7.7 EEPROM (Non-Volatile) Register Map..................... 79
7.8 RAM (Volatile) Register Map...................................129
8 Application and Implementation................................ 146
8.1 Application Information........................................... 146
8.2 Typical Applications................................................ 146
9 Power Supply Recommendations..............................154
9.1 Bulk Capacitance.................................................... 154
10 Layout.........................................................................155
10.1 Layout Guidelines................................................. 155
10.2 Layout Example.................................................... 156
10.3 Thermal Considerations........................................157
11 Device and Documentation Support........................158
11.1 Support Resources............................................... 158
11.2 Trademarks........................................................... 158
11.3 Electrostatic Discharge Caution............................ 158
11.4 Glossary................................................................ 158
12 Mechanical, Packaging, and Orderable
Information.................................................................. 158
12.1 Tape and Reel Information....................................158
4 Revision History
Changes from Revision * (December 2022) to Revision A (April 2023)
Page
• Updated I2C Data Word section to clarify default I2C Target ID........................................................................74
• Updated CRC Byte Calculation section with CRC initial value......................................................................... 78
2
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5 Pin Configuration and Functions
nFAULT
ALARM
DACOUT1
DACOUT2
DACOUT2/SOX
BRAKE
DIR
EXT_CLK
40
39
38
37
36
35
34
33
DVDD 1
32
EXT_WD
DGND 2
31
SCL
FB_BK
3
30
SDA
GND_BK
4
29
FG
SW_BK
5
28
SPEED/WAKE
CPL
6
27
AVDD
CPH
7
26
AGND
CP
8
25
NC
VM
9
24
NC
VM 10
23
NC
22
NC
21
DRVOFF
VM
11
Thermal Pad
PGND 12
17
18
19
20
OUT B
PGND
OUT C
OUT C
PGND
16 OUT B
15
OUT A
OUT A
14
13
Figure 5-1. MCT8315A, 40-Pin VQFN With Exposed Thermal Pad, Top View
Table 5-1. Pin Functions
PIN
40-pin
Package
NAME
MCT8315A
TYPE(1)
DESCRIPTION
AGND
26
GND
Device analog ground. Refer Layout Guidelines for connection recommendation.
ALARM
39
O
Alarm signal : push-pull output. Pulled logic high during fault condition, if enabled.
If ALARM pin is not used, leave it floating.
AVDD
27
PWR O
3.3-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between
the AVDD and AGND pins. This regulator can source up to 20 mA for external circuits.
High → brake the motor
Low → normal operation
If BRAKE pin is not used, connect to AGND directly.
If BRAKE pin is used to brake the motor, use an external 100-kΩ pull-down resistor (to
AGND).
BRAKE
35
I
CP
8
PWR
CPH
7
PWR
CPL
6
PWR
DACOUT1
38
O
DAC output DACOUT1
DACOUT2
37
O
DAC output DACOUT2
DACOUT2/S
OX
36
O
Multi-purpose pin:
DAC output when configured as DACOUT2
CSA output when configured as SOX
Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the CP
and VM pins.
Charge pump switching node. Connect a X5R or X7R, 47-nF, ceramic capacitor between
the CPH and CPL pins. TI recommends a capacitor voltage rating at least twice the normal
operating voltage of the device.
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Table 5-1. Pin Functions (continued)
PIN
40-pin
Package
NAME
MCT8315A
DGND
TYPE(1)
2
GND
Device digital ground. Refer Layout Guidelines for connection recommendation.
DIR
34
I
Direction of motor spinning;
When low, phase driving sequence is OUT A → OUT B → OUT C
When high, phase driving sequence is OUT A → OUT C → OUT B
If DIR pin is not used, connect to AGND or AVDD directly (depending on phase driving
sequence needed).
If DIR pin is used for changing motor spin direction, use an external 100-kΩ pull-down resistor
(to AGND).
DRVOFF
21
I
Coast (Hi-Z) all six MOSFETs.
DVDD
1
PWR
EXT_CLK
33
I
External clock reference input in external clock reference mode.
EXT_WD
32
I
External watchdog input.
FB_BK
3
PWR I/O
Feedback for buck regulator. Connect to buck regulator output after the inductor/resistor.
FG
29
O
Motor speed indicator : open-drain output; requires an external pull-up resistor to 1.8-V to
5.0-V.
GND_BK
1.5-V internal regulator output. Connect a X5R or X7R, 2.2-µF, 6.3-V ceramic capacitor
between the DVDD and DGND pins.
4
GND
22, 23, 24, 25
-
No connection. Leave these pins floating.
40
O
Fault indicator: open drain output. Pulled logic low during fault condition; requires an external
pull-up resistor to 1.8-V to 5.0-V.
OUTA
13, 14
PWR O
Half-bridge output A
OUTB
16, 17
PWR O
Half-bridge output B
OUTC
19, 20
PWR O
Half-bridge output C
PGND
12, 15, 18
GND
SCL
31
I
SDA
30
I/O
SPEED/
WAKE
28
I
SW_BK
5
PWR
Buck switch node. Connect this pin to an inductor or resistor.
9, 10, 11
PWR I
Device and motor power supply. Connect to motor supply voltage; bypass to PGND with a
0.1-µF capacitor plus one bulk capacitor. TI recommends a capacitor voltage rating at least
twice the normal operating voltage of the device.
NC
nFAULT
VM
Thermal pad
(1)
4
DESCRIPTION
GND
Buck regulator ground. Refer Layout Guidelines for connection recommendation.
Device power ground. Refer Layout Guidelines for connection recommendation.
I2C clock input
I2C data line
Device speed input; supports analog, frequency or PWM signals. The speed pin input can be
configured through SPD_CTRL_MODE.
Connect to AGND
I = input, O = output, GND = ground, PWR = power, NC = no connect
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6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Power supply pin voltage (VM)
–0.3
40
V
Voltage difference between ground pins (GND_BK, DGND, PGND, AGND)
–0.3
0.3
V
Charge pump voltage (CPH, CP)
–0.3
VVM + 6
V
Charge pump negative switching pin voltage (CPL)
–0.3
VVM +0.3
V
Switching node pin voltage (SW_BK)
–0.3
VVM +0.3
V
Analog regulators pin voltage (AVDD)
–0.3
4
V
Analog regulators pin voltage (DVDD)
–0.3
1.7
V
Logic pin input voltage (BRAKE, DRVOFF, DIR, EXT_CLK, EXT_WD, SCL, SDA, SPEED)
–0.3
6
V
Open drain pin output voltage (nFAULT, FG)
–0.3
6
V
–1
VVM + 1
V
Ambient temperature, TA
–40
125
°C
Junction temperature, TJ
–40
150
°C
Storage tempertaure, Tstg
–65
150
°C
Output pin voltage (OUTA, OUTB, OUTC)
(1)
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
UNIT
±2000
Charged device model (CDM), per JEDEC specification JS-002((2))
V
±750
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
VVM
MIN
NOM
MAX
4.5
24
35
V
4
A
–0.1
5.5
V
–0.1
5.5
V
5
mA
Operating ambient temperature
–40
125
°C
Operating junction temperature
–40
150
°C
Power supply voltage
VVM
Peak output winding current
OUTA, OUTB, OUTC
VIN_LOGIC
Logic input voltage
BRAKE, DRVOFF, DIR, EXT_CLK,
EXT_WD, SPEED, SDA, SCL
VOD
Open drain pullup voltage
nFAULT, FG
IOD
Open drain output current capability
nFAULT, FG
TA
TJ
IOUT
(1)
(1)
UNIT
Power dissipation and thermal limits must be observed
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6.4 Thermal Information
MCT8315A
THERMAL
METRIC(1)
UNIT
RGF (VQFN)
40 Pins
RθJA
Junction-to-ambient thermal resistance
28
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
16.7
°C/W
RθJB
Junction-to-board thermal resistance
8.9
°C/W
ΨJT
Junction-to-top characterization parameter
1.8
°C/W
ΨJB
Junction-to-board characterization parameter
8.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES
IVMQ
VM sleep mode current
IVMS
VM standby mode current
IVM
6
VM operating mode current
VAVDD
Analog regulator voltage
IAVDD
External analog regulator load
VDVDD
Digital regulator voltage
VVCP
Charge pump regulator voltage
VVM > 6 V, VSPEED = 0, TA = 25 °C
3
5
µA
3.5
7
µA
VVM ≥ 12 V, Standby Mode, DRVOFF =
High, TA = 25 °C, LBK = 47 uH, CBK = 22
µF
8
16
mA
VVM > 6 V, Standby Mode, DRVOFF =
High, TA = 25 °C, RBK = 22 Ω, CBK = 22
µF
25
29
mA
VVM ≥ 12 V, Standby Mode, DRVOFF =
High, LBK = 47 uH, CBK = 22 µF
8
16.5
mA
VVM > 6 V, Standby Mode, DRVOFF =
High, RBK = 22 Ω, CBK = 22 µF
25
29
mA
VVM > 6 V, VSPEED > VEX_SL,
PWM_FREQ_OUT = 10000b (25 kHz),
TA = 25 °C, LBK = 47 uH, CBK = 22 µF,
No Motor Connected
11
18
mA
VVM > 6 V, VSPEED > VEX_SL,
PWM_FREQ_OUT = 10000b (25 kHz),
TA = 25 °C, RBK = 22 Ω, CBK = 22 µF, No
Motor Connected
27
30.5
mA
VVM > 6 V, VSPEED > VEX_SL,
PWM_FREQ_OUT = 10000b (25 kHz),
LBK = 47 uH, CBK = 22 µF, No Motor
Connected
11
17
mA
VVM > 6 V, VSPEED > VEX_SL,
PWM_FREQ_OUT = 10000b (25 kHz),
RBK = 22 Ω, CBK = 22 µF, No Motor
Connected
28
30.5
mA
3.3
3.465
VSPEED = 0, TA = 125 °C
0 mA ≤ IAVDD ≤ 20 mA
3.125
20
VCP with respect to VM
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V
mA
1.4
1.55
1.65
V
4.0
4.7
5.5
V
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TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VVM > 6 V, 0 mA ≤ IBK ≤ 170 mA,
BUCK_SEL = 00b
3.1
3.3
3.5
V
VVM > 6 V, 0 mA ≤ IBK ≤ 170 mA,
BUCK_SEL = 01b
4.6
5.0
5.4
V
VVM > 6 V, 0 mA ≤ IBK ≤ 170 mA,
BUCK_SEL = 10b
3.7
4.0
4.3
V
VVM > 6.7 V, 0 mA ≤ IBK ≤ 170 mA,
BUCK_SEL = 11b
5.2
5.7
6.2
V
BUCK REGULATOR
VBK
Buck regulator average voltage
(LBK = 47 µH, CBK = 22 µF)
VVM–
IBK*(RLBK
+2) (1)
VVM < 6.0 V (BUCK_SEL = 00b, 01b,
10b, 11b), 0 mA ≤ IBK ≤ 170 mA
VBK
Buck regulator average voltage
(LBK = 22 µH, CBK = 22 µF)
VVM > 6 V, 0 mA ≤ IBK ≤ 20 mA,
BUCK_SEL = 00b
3.1
3.3
3.5
V
VVM > 6 V, 0 mA ≤ IBK ≤ 20 mA,
BUCK_SEL = 01b
4.6
5.0
5.4
V
VVM > 6 V, 0 mA ≤ IBK ≤ 20 mA,
BUCK_SEL = 10b
3.7
4.0
4.3
V
VVM > 6.7 V, 0 mA ≤ IBK ≤ 20 mA,
BUCK_SEL = 11b
5.2
5.7
6.2
V
VVM–
IBK*(RLBK
+2)(1)
VVM < 6.0 V (BUCK_SEL = 00b, 01b,
10b, 11b), 0 mA ≤ IBK ≤ 20 mA
VBK
Buck regulator average voltage
(RBK = 22 Ω, CBK = 22 µF)
IBK
Buck regulator ripple voltage
External buck regulator load
V
VVM > 6 V, 0 mA ≤ IBK ≤ 10 mA,
BUCK_SEL = 00b
3.1
3.3
3.5
V
VVM > 6 V, 0 mA ≤ IBK ≤ 10 mA,
BUCK_SEL = 01b
4.6
5.0
5.4
V
VVM > 6 V, 0 mA ≤ IBK ≤ 10 mA,
BUCK_SEL = 10b
3.7
4.0
4.3
V
VVM > 6.7 V, 0 mA ≤ IBK ≤ 10 mA,
BUCK_SEL = 11b
5.2
5.7
6.2
V
VVM–
IBK*(RBK
+2)
VVM < 6.0 V (BUCK_SEL = 00b, 01b,
10b, 11b), 0 mA ≤ IBK ≤ 10 mA
VBK_RIP
V
V
VVM > 6 V, 0 mA ≤ IBK ≤ 170 mA, Buck
regulator with inductor, LBK = 47 uH, CBK
= 22 µF
–100
100
mV
VVM > 6 V, 0 mA ≤ IBK ≤ 20 mA, Buck
regulator with inductor, LBK = 22 uH, CBK
= 22 µF
–100
100
mV
VVM > 6 V, 0 mA ≤ IBK ≤ 10 mA, Buck
regulator with resistor; RBK = 22 Ω, CBK
= 22 µF
–100
100
mV
LBK = 47 uH, CBK = 22 µF,
BUCK_PS_DIS = 1b
170
mA
LBK = 47 uH, CBK = 22 µF,
BUCK_PS_DIS = 0b
170 –
IAVDD
mA
LBK = 22 uH, CBK = 22 µF,
BUCK_PS_DIS = 1b
20
mA
LBK = 22 uH, CBK = 22 µF,
BUCK_PS_DIS = 0b
20 –
IAVDD
mA
RBK = 22 Ω, CBK = 22 µF,
BUCK_PS_DIS = 1b
10
mA
RBK = 22 Ω, CBK = 22 µF,
BUCK_PS_DIS = 0b
10 –
IAVDD
mA
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TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER
fSW_BK
VBK_UV
VBK_UV_HYS
IBK_CL
TEST CONDITIONS
Regulation Mode
Buck regulator switching frequency
Buck regulator undervoltage lockout
Buck regulator undervoltage lockout
hysteresis
Buck regulator current limit threshold
IBK_OCP
Buck regulator over current protection
trip point
tBK_RETRY
Over current protection retry time
MIN
TYP
20
Linear Mode
20
VBK rising, BUCK_SEL = 00b
2.7
2.8
VBK falling, BUCK_SEL = 00b
2.5
VBK rising, BUCK_SEL = 01b
4.3
VBK falling, BUCK_SEL = 01b
MAX
UNIT
535
kHz
535
kHz
2.95
V
2.6
2.7
V
4.4
4.55
V
4.1
4.2
4.36
V
VBK rising, BUCK_SEL = 10b
2.7
2.8
2.95
V
VBK falling, BUCK_SEL = 10b
2.5
2.6
2.7
V
VBK rising, BUCK_SEL = 11b
4.3
4.4
4.55
V
VBK falling, BUCK_SEL = 11b
4.1
4.2
4.36
V
Rising to falling threshold, BUCK_SEL =
00b
90
200
400
mV
Rising to falling threshold, BUCK_SEL =
01b
90
200
400
mV
Rising to falling threshold, BUCK_SEL =
10b
90
200
400
mV
Rising to falling threshold, BUCK_SEL
=11b
90
200
400
mV
BUCK_CL = 0b
360
600
910
mA
BUCK_CL = 1b
80
150
250
mA
2
3
4
0.7
1
1.3
ms
VVM > 6 V, IOUT = 1 A, TA = 25°C
240
260
mΩ
VVM < 6 V, IOUT = 1 A, TA = 25°C
250
270
mΩ
VVM > 6 V, IOUT = 1 A, TJ = 150 °C
360
400
mΩ
370
415
mΩ
25
45
V/µs
A
DRIVER OUTPUTS
RDS(ON)
Total MOSFET on resistance (High-side
+ Low-side)
VVM < 6 V, IOUT = 1 A, TJ = 150 °C
SR
SR
tDEAD
VVM = 24 V, SLEW_RATE = 00b
13
Phase pin slew rate switching low to high VVM = 24 V, SLEW_RATE = 01b
(Rising from 20 % to 80 %)
VVM = 24 V, SLEW_RATE = 10b
30
50
80
V/µs
80
125
185
V/µs
VVM = 24 V, SLEW_RATE = 11b
130
200
280
V/µs
VVM = 24 V, SLEW_RATE = 00b
14
25
45
V/µs
Phase pin slew rate switching high to low VVM = 24 V, SLEW_RATE = 01b
(Falling from 80 % to 20 %)
VVM = 24 V, SLEW_RATE = 10b
30
50
80
V/µs
80
125
185
V/µs
VVM = 24 V, SLEW_RATE = 11b
110
Output dead time (high to low / low to
high)
200
280
V/µs
VVM = 24 V, SR = 25 V/µs
1800
3000
ns
VVM = 24 V, SR = 50 V/µs
1100
1400
ns
VVM = 24 V, SR = 125 V/µs
650
850
ns
VVM = 24 V, SR = 200 V/µs
500
550
ns
100
kHz
SPEED INPUT - PWM MODE
ƒPWM
8
PWM input frequency
0.01
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TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER
ResPWM
TEST CONDITIONS
PWM input resolution
MIN
TYP
MAX
fPWM = 0.01 to 0.35 kHz
11
12
13
UNIT
bits
fPWM = 0.35 to 2 kHz
11
13
14
bits
fPWM = 2 to 3.5 kHz
11
11.5
12
bits
fPWM = 3.5 to 7 kHz
12
13
13.5
bits
fPWM = 7 to 14 kHz
11
12
12.5
bits
fPWM = 14 to 29.2 kHz
10
11.5
12
bits
fPWM = 29.3 to 60 kHz
9
10.5
11
bits
fPWM = 60 to 100 kHz
8
9
10
bits
2.95
3
3.05
SPEED INPUT - ANALOG MODE
VANA_FS
Analog full-speed voltage
VANA_RES
Analog voltage resolution
732
V
μV
SPEED INPUT - FREQUENCY MODE
ƒPWM_FREQ
PWM input frequency range
Duty cycle = 50%
3
32767
Hz
40
mV
SLEEP MODE
VEN_SL
Analog voltage to enter sleep mode
SPD_CTRL_MODE = 00b (analog
mode)
VEX_SL
Analog voltage to exit sleep mode
SPD_CTRL_MODE = 00b (analog
mode)
2.2
tDET_ANA
SPD_CTRL_MODE = 00b (analog
Time needed to detect wake up signal on
mode)
SPEED pin
VSPEED > VEX_SL
0.5
tWAKE
Wakeup time from sleep mode
VSPEED > VEX_SL to DVDD voltage
available, SPD_CTRL_MODE = 00b
(analog mode)
tEX_SL_DR_A
Time taken to drive motor after exiting
from sleep state
SPD_CTRL_MODE = 00b (analog
mode)
VSPEED > VEX_SL, ISD detection disabled
NA
tDET_PWM
Time needed to detect wake up signal on SPD_CTRL_MODE = 01b (PWM
SPEED pin
mode), VSPEED > VIH
tWAKE_PWM
Wakeup time from sleep mode
VSPEED > VIH to DVDD voltage available,
SPD_CTRL_MODE = 01b (PWM mode)
or 11b (Frequency mode)
tEX_SL_DR_P
Time taken to drive motor after wakeup
from sleep state
SPD_CTRL_MODE = 01b (PWM mode)
VSPEED > VIH, ISD detection disabled
WM
tDET_SL_ANA
Time needed to detect sleep command,
analog mode
0.5
V
1
1.5
μs
3
5
ms
30
ms
1
1.5
μs
3
5
ms
30
ms
SPD_CTRL_MODE = 00b (analog
mode) VSPEED < VEN_SL, SLEEP_TIME
= 00b or 01b
0.5
1
2
ms
SPD_CTRL_MODE = 00b (analog
mode) VSPEED < VEN_SL, SLEEP_TIME
= 10b
14
20
26
ms
SPD_CTRL_MODE = 00b (analog
mode) VSPEED < VEN_SL, SLEEP_TIME
= 11b
140
200
260
ms
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TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER
tDET_SL_PWM
tEN_SL
TEST CONDITIONS
Time needed to detect sleep command,
PWM or frequency mode
Time needed to stop driving motor after
detecting sleep command
MIN
TYP
MAX
UNIT
SPD_CTRL_MODE = 01b (PWM mode)
or 11b (Frequency mode),
VSPEED < VIL, SLEEP_TIME = 00b
0.035
0.05
0.065
ms
SPD_CTRL_MODE = 01b (PWM mode)
or 11b (Frequency mode),
VSPEED < VIL, SLEEP_TIME = 01b
0.14
0.2
0.26
ms
SPD_CTRL_MODE = 01b (PWM mode)
or 11b (Frequency mode),
VSPEED < VIL, SLEEP_TIME = 10b
14
20
26
ms
SPD_CTRL_MODE = 01b (PWM mode)
or 11b (Frequency mode),
VSPEED < VIL, SLEEP_TIME = 11b
140
200
260
ms
1
2
ms
VSPEED < VEN_SL (analog
mode) or VSPEED < VIL (PWM mode)
(and SPEED_CTRL = 0 (I2C mode))
STANDBY MODE
tEX_SB_DR_A Time taken to drive motor after exiting
standby mode, analog mode
NA
SPD_CTRL_MODE = 00b (analog
mode), VSPEED > VEX_SB, ISD detection
disabled
6
ms
tEX_SB_DR_P Time taken to drive motor after exiting
standby mode, PWM mode
SPD_CTRL_MODE = 01b (PWM mode)
VSPEED > VIH, ISD detection disabled
6
ms
WM
tDET_SB_ANA
tDET_SB_PWM
Time needed to detect standby mode,
analog mode
SPD_CTRL_MODE = 00b (analog
mode), VSPEED < VEN_SB
Time needed to detect standby
command, PWM/ mode
0.5
1
2
ms
SPD_CTRL_MODE = 01b (PWM mode),
VSPEED < VIL, SLEEP_TIME = 00b
0.035
0.05
0.065
ms
SPD_CTRL_MODE = 01b (PWM mode),
VSPEED < VIL, SLEEP_TIME = 01b
0.14
0.2
0.26
ms
SPD_CTRL_MODE = 01b (PWM mode),
VSPEED < VIL, SLEEP_TIME = 10b
14
20
26
ms
SPD_CTRL_MODE = 01b (PWM mode),
VSPEED < VIL, SLEEP_TIME = 11b
140
200
260
ms
tDET_SB_FRE Time needed to detect standby mode,
Frequency mode
SPD_CTRL_MODE = 11b (Frequency
mode), VSPEED < VIL
4000
tDET_SB_DIG
Time needed to detect standby mode,
I2C mode
SPD_CTRL_MODE = 10b (I2C mode),
SPEED_CTRL = 0b
1
2
ms
tEN_SB
Time needed to stop driving motor after
detecting standby command
All speed input modes
1
2
ms
Q
ms
LOGIC-LEVEL INPUTS (BRAKE, DIR, EXT_CLK, EXT_WD, SPEED)
0.25*AV
DD
VIL
Input logic low voltage
AVDD = 3 to 3.6 V
VIH
Input logic high voltage
AVDD = 3 to 3.6 V
0.65*AV
DD
VHYS
Input hysteresis
800
mV
IIL
Input logic low current
AVDD = 3 to 3.6 V
-0.15
0.15
µA
IIH
Input logic high current
AVDD = 3 to 3.6 V
-0.3
0
µA
RPD_SPEED
Input pulldown resistance
SPEED pin To GND
0.6
1.4
MΩ
50
V
V
500
1
OPEN-DRAIN OUTPUTS (nFAULT, FG)
VOL
Output logic low voltage
IOD = -5 mA
IOZ
Output logic high current
VOD = 3.3 V
0.4
V
0
0.5
µA
-0.5
0.3*AVD
D
V
I2C Serial Interface
VI2C_L
10
Input logic low voltage
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TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER
TEST CONDITIONS
MIN
VI2C_H
Input logic high voltage
0.7*AVD
D
VI2C_HYS
Hysteresis
0.05*AV
DD
VI2C_OL
Output logic low voltage
Open-drain at 2mA sink current
II2C_OL
Output logic low current
VI2C_OL = 0.6V
II2C_IL
Input current on SDA and SCL
Ci
Capacitance for SDA and SCL
tof
Output fall time from VI2C_H(min) to
VI2C_L(max)
tSP
Pulse width of spikes that must be
suppressed by the input filter
TYP
MAX
UNIT
5.5
V
V
0
0.4
V
6
mA
10(2)
µA
10
pF
Standard Mode
250(3)
ns
Fast Mode
250(3)
ns
50(4)
ns
-10(2)
Fast Mode
0
OSCILLATOR
fOSCREF
External clock reference
EXT_CLK_CONFIG = 000b
8
kHz
EXT_CLK_CONFIG = 001b
16
kHz
EXT_CLK_CONFIG = 010b
32
kHz
EXT_CLK_CONFIG = 011b
64
kHz
EXT_CLK_CONFIG = 100b
128
kHz
EXT_CLK_CONFIG = 101b
256
kHz
EXT_CLK_CONFIG = 110b
512
kHz
EXT_CLK_CONFIG = 111b
1024
kHz
EEPROM
EEProg
Programming voltage
EERET
Retention
EEEND
Endurance
1.35
TA = 25 ℃
TJ = -40 to 150 ℃
1.5
1.65
100
V
Years
10
Years
TJ = -40 to 150 ℃
1000
Cycles
TJ = -40 to 85 ℃
20000
Cycles
PROTECTION CIRCUITS
VM rising
VUVLO
Supply under voltage lockout (UVLO)
VUVLO_HYS
Supply under voltage lockout hysteresis
tUVLO
Supply under voltage deglitch time
VOVP
Supply over voltage protection (OVP)
threshold
VOVP_HYS
Supply over voltage protection
hysteresis
tOVP
Supply over voltage deglitch time
4.3
4.4
4.51
V
VM falling
4.1
4.2
4.3
V
Rising to falling threshold
110
200
350
mV
3
5
7
µs
Supply rising, OVP_EN = 1, OVP_SEL =
0
32.5
34
35
V
Supply falling, OVP_EN = 1, OVP_SEL
=0
31.8
33
34.3
V
Supply rising, OVP_EN = 1, OVP_SEL =
1
20
22
23
V
Supply falling, OVP_EN = 1, OVP_SEL
=1
19
21
22
V
Rising to falling threshold, OVP_SEL = 1
0.9
1
1.1
V
Rising to falling threshold, OVP_SEL = 0
0.7
0.8
0.9
V
2.5
5
7
µs
2.25
2.5
2.75
V
VCPUV
Charge pump under voltage lockout
(above VM)
Supply rising
Supply falling
2.2
2.4
2.6
V
VCPUV_HYS
Charge pump UVLO hysteresis
Rising to falling threshold
65
100
150
mV
VAVDD_UV
Analog regulator (AVDD) under voltage
lockout
Supply rising
2.7
2.85
3
V
Supply falling
2.5
2.65
2.8
V
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TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER
VAVDD_
TEST CONDITIONS
UV_HYS
Analog regulator under voltage lockout
hysteresis
IOCP
Over current protection trip point
tOCP
Over current protection deglitch time
MIN
TYP
MAX
UNIT
Rising to falling threshold
180
200
240
mV
OCP_LVL = 0b
5.5
9
12
A
OCP_LVL = 1b
9
13
18
A
OCP_DEG = 00b
0.02
0.2
0.4
µs
OCP_DEG = 01b
0.2
0.6
1.2
µs
OCP_DEG = 10b
0.5
1.2
1.8
µs
OCP_DEG = 11b
0.9
1.6
2.5
µs
OCP_RETRY = 0
4
5
6
ms
OCP_RETRY = 1
425
500
575
ms
Thermal warning temperature
Die temperature (TJ)
135
145
155
°C
Thermal warning hysteresis
Die temperature (TJ)
20
25
30
°C
TTSD_BUCK
Thermal shutdown temperature (Buck)
Die temperature (TJ)
170
180
190
°C
TTSD_BUCK_
Thermal shutdown hysteresis (Buck)
Die temperature (TJ)
20
25
30
°C
TTSD
Thermal shutdown temperature (FET)
Die temperature (TJ)
165
175
185
°C
TTSD_HYS
Thermal shutdown hysteresis (FET)
Die temperature (TJ)
20
25
30
°C
tRETRY
Over current protection retry time
TOTW
TOTW_HYS
HYS
(1)
(2)
(3)
(4)
RLBK is resistance of inductor LBK.
If AVDD is switched off, I/O pins must not obstruct the SDA and SCL lines.
The maximum tf for the SDA and SCL bus lines (300 ns) is longer than the specified maximum tof for the output stages (250 ns). This
allows series protection resistors (Rs) to be connected between the SDA/SCL pins and the SDA/SCL bus lines without exceeding the
maximum specified tf.
Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.
6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
100
kHz
Standard-mode
fSCL
SCL clock frequency
0
tHD_STA
Hold time (repeated) START condition
tLOW
After this period, the first clock pulse is
generated
4
µs
LOW period of the SCL clock
4.7
µs
tHIGH
HIGH period of the SCL clock
4
µs
tSU_STA
Set-up time for a repeated START
condition
4.7
µs
tHD_DAT
Data hold time (2)
tSU_DAT
Data set-up time
tr
Rise time for both SDA and SCL signals
I2C bus devices
Fall time of both SDA and SCL signals
(3)
(6) (7) (8)
tSU_STO
Set-up time for STOP condition
tBUF
Bus free time between STOP and START
condition
Cb
Capacitive load for each bus line (9)
tVD_DAT
Data valid time (10)
VnL
12
Data valid acknowledge time
(4)
250
tf
tVD_ACK
0 (3)
Noise margin at the LOW level
ns
1000
ns
300
ns
4
µs
4.7
µs
(11)
400
pF
3.45 (4)
µs
(4)
µs
3.45
For each connected device (including
hysteresis)
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0.1*AVD
D
V
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over operating free-air temperature range (unless otherwise noted)
PARAMETER
Vnh
TEST CONDITIONS
Noise margin at the HIGHlevel
For each connected device (including
hysteresis)
MIN
NOM
MAX
UNIT
0.2*AVD
D
V
Fast-mode
fSCL
SCL clock frequency
0
tHD_STA
Hold time (repeated) START condition
tLOW
tHIGH
After this period, the first clock pulse is
generated
400
KHz
0.6
µs
LOW period of the SCL clock
1.3
µs
HIGH period of the SCL clock
0.6
µs
tSU_STA
Set-up time for a repeated START
condition
0.6
µs
tHD_DAT
Data hold time (2)
0 (3)
tSU_DAT
Data set-up time
100
tr
Rise time for both SDA and SCL signals
Fall time of both SDA and SCL signals (3)
(4)
(5)
µs
ns
20
300
ns
20 x
(AVDD/
5.5V)
300
ns
tf
(6) (7) (8)
tSU_STO
Set-up time for STOP condition
0.6
µs
tBUF
Bus free time between STOP and START
condition
1.3
µs
Cb
Capacitive load for each bus line (9)
tVD_DAT
Data valid time (10)
tVD_ACK
Data valid acknowledge time
(11)
400
pF
0.9 (4)
µs
(4)
µs
0.9
VnL
Noise margin at the LOW level
For each connected device (including
hysteresis)
Vnh
Noise margin at the HIGHlevel
For each connected device (including
hysteresis)
0.1*AVD
D
V
0.2*AVD
D
V
(1)
(2)
(3)
All values referred to VIH(min) (0.3VDD) and VIL(max) levels
tHD_DAT is the data hold time that is measured from the falling edge of SCL, applies to data in transmission and the acknowledge.
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
(4) The maximum tHD_DAT could be 3.45 µs and .9 µs for Standard-mode and Fast-mode, but must be less than the maximum of tVD_DAT or
tVD_ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If
the clock stretched the SCL, the data must be valid by the set-up time before it releases the clock.
(5) A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU_DAT 250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU_DAT = 1000 + 250 = 1250 ns (according to
the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
(6) If mixed with HS-mode devices, faster fall times according to Table 10 are allowed.
(7) The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified
at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified tf.
(8) In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should
allow for this when considering bus timing.
(9) The maximum bus capacitance allowable may vary from the value depending on the actual operating voltage and frequency of the
application.
(10) tVD_DAT = time for data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
(11) tVD_ACK = time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, dependging on which one is worse).
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6.7 Typical Characteristics
30
100
TJ = -40 C
TJ = 25 C
TJ = -150 C
97.5
28
Active Current (mA)
24
22
Buck
Buck
Buck
Buck
20
18
with
with
with
with
Inductor (25C)
Inductor (125C)
Resistor (25C)
Resistor (125C)
92.5
90
87.5
85
82.5
80
77.5
16
75
14
4
12
8
12
16
20
24
Supply Voltage (V)
28
32
36
Figure 6-2. Buck regulator efficiency over supply
voltage
10
8
10
Buck Efficiency (%)
95
26
12.5
15
17.5
20 22.5 25 27.5
Supply Voltage (V)
30
32.5
35
Figure 6-1. Supply current over supply voltage
5.75
5.5
Buck Output Voltage (V)
5.25
5
4.75
BUCK_SEL
BUCK_SEL
BUCK_SEL
BUCK_SEL
4.5
4.25
4
=
=
=
=
00b
01b
10b
11b
3.75
3.5
3.25
3
0
0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18
Buck Output Load Current (A)
0.2
Figure 6-3. Buck regulator output voltage over load current
14
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7 Detailed Description
7.1 Overview
The MCT8315A provides a single-chip, code-free sensorless trapezoidal solution for customers requiring high
speed operation (up to 3 kHz electrical speed) or very fast start-up time (< 50ms) for 12- to 24-V brushless-DC
motors requiring up to 4-A peak phase currents.
The MCT8315A integrates three ½-bridges with 40-V absolute maximum capability and a low RDS(ON) of 240-mΩ
(high-side + low-side FETs) to enable high power drive capability. Current is sensed using integrated current
sensing circuits which eliminate the need for external current sense resistors. Power management features
including an output voltage-adjustable buck regulator and 3.3-V LDO generate the necessary voltage rails for the
device and can also be used to power external circuits.
Sensorless trapezoidal control is highly configurable through register settings ranging from motor start-up
behavior to closed loop operation. Register settings can be stored in non-volatile EEPROM, which allows the
device to operate stand-alone once it has been configured. MCT8315A allows for a high level of monitoring;
variables like duty cycle, motor speed, DC bus power can be displayed and observed as an analog output via
two 12-bit DACs. This feature provides an effective method to tune speed loops as well as motor acceleration.
The device can receive a speed command through a PWM signal, analog voltage, frequency input or I2C
instruction.
In-built protection features include power-supply under voltage lockout (UVLO), charge-pump under voltage
lockout (CPUV), over current protection (OCP), AVDD under voltage lockout (AVDD_UV), buck regulator UVLO,
motor lock detection and over temperature warning and shutdown (OTW and TSD). Fault events are indicated
by the nFAULT pin with detailed fault information available in the registers.
The MCT8315A device is available in a 0.5-mm pin pitch, VQFN surface-mount package. The VQFN package
size is 7 mm × 5 mm with a height of 1 mm.
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7.2 Functional Block Diagram
CAVDD 1µF
LBK
Buck
Out
CFLY 47nF
VM
AVDD
Out
- or -
SW_BK
AVDD AGND
CPL
CPH
CP
CCP
1µF
RBK
CBK
VM
GND_BK
Buck/LDO
Regulator
FB_BK
DVDD
LDO
Regulator
DGND
VM
VM
Protection
CVM1
0.1µF
+ CVM2
>10µF
DRVOFF
VM
VCP
EEPROM
OUTA
SPEED/WAKE
PWM, Freq or
Analog Input
BRAKE
AVDD
Charge Pump
Input VM or
Buck/LDO
DVDD
CDVDD
2.2µF
AVDD LDO
Regulator
Sensorless Trap
Control
VGLS
OUTA
Integrated
current
sensing
IO Interface
DIR
PGND
AVDD
ALARM
A
Protection
Protection
FG
PGND
VM
ISENA
PGND
DRVOFF
VCP
nFAULT
OUTB
AVDD
Speed/power loop
AVDD
2
IC
SDA
Optional external
clock reference
VGLS
OUTB
SCL
2
Fast accel & decel
PGND
120° & 150°
commutation
EXT_WD
Built-in 60-MHz
Oscillator
EXT_CLK
DACOUT1
Oponal external
clock reference
Integrated
current
sensing
Protection
PGND
Protection
VM
ISENB
PGND
DRVOFF
VCP
12-bit
DAC
12-bit
ADC
OUTC
VGLS
DACOUT2
DACOUT2/SOX
Variable
monitoring on
DACOUT1 &
DACOUT2 pins,
SOX output
OUTC
Integrated
current
sensing
ISENA
ISENB
ISENC
VM
OUTA
OUTB
OUTC
PGND
Protection
PGND
ISENC
PGND
Figure 7-1. MCT8315A Functional Block Diagram
16
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7.3 Feature Description
7.3.1 Output Stage
The MCT8315A consists of integrated 240-mΩ (combined high-side and low-side FETs' on-state resistance)
NMOS FETs connected in a three-phase bridge configuration. A doubler charge pump provides the proper
gate-bias voltage to the high-side NMOS FETs across a wide operating voltage range in addition to providing
100% duty-cycle support. An internal linear regulator provides the gate-bias voltage for the low-side MOSFETs.
7.3.2 Device Interface
MCT8315A supports I2C interface to provide end application design with adequate flexibility. MCT8315A allows
controlling the motor operation and system through BRAKE, DIR, DRVOFF, EXT_CLK, EXT_WD and SPEED/
WAKE pins. MCT8315A also provides different signals for monitoring internal variables, speed, fault and phase
current feedback through DACOUT1, DACOUT2, FG, nFAULT, ALARM and SOX pins.
7.3.2.1 Interface - Control and Monitoring
Motor Control Signals
•
•
•
•
When BRAKE pin is driven 'High', MCT8315A enters brake state. Low-side braking (see Low-Side
Braking) is implemented during this brake state. MCT8315A decreases output speed to value defined by
BRAKE_DUTY_THRESHOLD before entering brake state. As long as BRAKE is driven 'High', MCT8315A
stays in brake state. Brake pin input can be overwritten by configuring BRAKE_INPUT over the I2C interface.
The DIR pin decides the direction of motor spin; when driven 'High', the sequence is OUT A → OUT C →
OUT B, and when driven 'Low', the sequence is OUT A → OUT B → OUT C. DIR pin input can be overwritten
by configuring DIR_INPUT over the I2C interface.
When DRVOFF pin is driven 'High', MCT8315A stops driving the motor by turning OFF all MOSFETs (coast
state). When DRVOFF is driven 'Low', MCT8315A returns to normal state of operation, as if it was restarting
the motor (see DRVOFF Functionality). DRVOFF does not cause the device to go to sleep or standby mode;
the digital core is still active. Entry and exit from sleep or standby condition is controlled by SPEED pin.
SPEED/WAKE pin is used to control motor speed and to wake up MCT8315A from sleep mode. SPEED pin
can be configured to accept PWM, frequency or analog input signals. It is used to enter and exit from sleep
and standby mode (see Table 7-3).
External Oscillator and Watchdog Signals
• EXT_CLK pin can be used to provide an external clock reference (see External Clock Source).
• EXT_WD pin can be used to provide an external watchdog signal (see External Watchdog).
Output Signals
• DACOUT1 outputs internal variable defined by address in register DACOUT1_VAR_ADDR. DACOUT1 is
refreshed every PWM cycle (see DAC outputs).
• DACOUT2 outputs internal variable defined by address in register DACOUT2_VAR_ADDR. DACOUT2 is
refreshed every PWM cycle (see DAC outputs).
• FG pin provides pulses which are proportional to motor speed (see FG Configuration).
• nFAULT (active low) pin provides fault status in device or motor operation.
• ALARM pin, if enabled using ALARM_PIN_EN, provides fault status in device or motor operation. When
ALARM pin is enabled, report only faults are reported only on ALARM pin (as logic high) and not reported
on nFAULT pin (as logic low). When ALARM pin is enabled, actionable faults are reported on ALARM pin (as
logic high) as well as on nFAULT pin (as logic low). When ALARM pin is disabled, it is in Hi-Z state and all
faults (actionable and report only) are reported on nFAULT as logic low. ALARM pin should be left floating
when unused/disabled.
• SOX pin provides the output of one of the current sense amplifiers.
7.3.2.2 I2C Interface
The MCT8315A supports an I2C serial communication interface that allows an external controller to send and
receive data. This I2C interface lets the external controller to configure the EEPROM and read detailed fault and
motor state information. The I2C bus is a two-wire interface using the SCL and SDA pins which are described as
follows :
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•
•
The SCL pin is the clock signal input.
The SDA pin is the data input and output.
7.3.3 Step-Down Mixed-Mode Buck Regulator
The MCT8315A has an integrated mixed-mode buck regulator to supply regulated 3.3-V or 5-V power for an
external controller or system voltage rail. Additionally, the buck output can also be configured to 4-V or 5.7-V for
supporting the extra headroom for an external LDO for generating a 3.3-V or 5-V supplies. The output voltage of
the buck is set by BUCK_SEL.
The buck regulator has a low quiescent current of ~1-2 mA during light loads to prolong battery life. The device
improves performance during line and load transients by implementing a pulse-frequency current-mode control
scheme which requires less output capacitance and simplifies frequency compensation design.
Table 7-1. Recommended settings for Buck Regulator
Buck Mode
Buck output voltage Max output
current from AVDD
(IAVDD_MAX)
Max output current
from Buck (IBK_MAX)
Buck current limit
AVDD power
sequencing
Inductor - 47 μH
3.3-V or 4-V
20 mA
170 mA - IAVDD
600 mA (BUCK_CL = Not supported
0b)
(BUCK_PS_DIS = 1b)
Inductor - 47 μH
5-V or 5.7-V
20 mA
170 mA - IAVDD
600 mA (BUCK_CL = Supported
0b)
(BUCK_PS_DIS = 0b)
Inductor - 22 μH
5-V or 5.7-V
20 mA
20 mA - IAVDD
150 mA (BUCK_CL = Not supported
1b)
(BUCK_PS_DIS = 1b)
Inductor - 22 μH
3.3-V or 4-V
20 mA
20 mA - IAVDD
150 mA (BUCK_CL = Supported
1b)
(BUCK_PS_DIS = 0b)
Resistor - 22 Ω
5-V or 5.7-V
20 mA
10 mA - IAVDD
150 mA (BUCK_CL = Not supported
1b)
(BUCK_PS_DIS = 1b)
Resistor - 22 Ω
3.3-V or 4-V
20 mA
10 mA - IAVDD
150 mA (BUCK_CL = Supported
1b)
(BUCK_PS_DIS = 0b)
7.3.3.1 Buck in Inductor Mode
The buck regulator in MCT8315A is primarily designed to support low inductance of 47-µH and 22-µH. A 47-µH
inductor allows the buck regulator to operate up to 170-mA load current support, whereas applications requiring
current up to 20-mA can use a 22-µH inductor which saves component size.
Figure 7-2 shows the connection of buck regulator in inductor mode.
VM
SW_BK
Control
Ext. Load
VBK
LBK
CBK
GND_BK
FB_BK
Figure 7-2. Buck (Inductor Mode)
18
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7.3.3.2 Buck in Resistor mode
If the external load requirement is less than 10-mA, the inductor can be replaced with a resistor. In resistor mode
the power is dissipated across the external resistor and the efficiency is lower than buck in inductor mode.
Figure 7-3 shows the connection of buck in resistor mode.
VM
SW_BK
Ext. Load
VBK
RBK
Control
CBK
GND_BK
FB_BK
Figure 7-3. Buck (Resistor Mode)
7.3.3.3 Buck Regulator with External LDO
The buck regulator also supports the voltage requirement to supply an external LDO to generate standard 3.3-V
or 5-V output rail with higher accuracies. The buck output voltage should be configured to 4-V or 5.7-V to provide
extra headroom to support the external LDO for generating 3.3-V or 5-V rail as shown in Figure 7-4. This allows
for a lower-voltage LDO design to save cost and better thermal management due to low drop-out voltage.
VM
VBK
(4V / 5.7V)
SW_BK
VLDO
(3.3V / 5V)
VIN
VLDO
LBK
Control
CBK
3.3V / 5V
LDO
Ext. Load
CLDO
GND_BK
GND
FB_BK
GND
External LDO
Figure 7-4. Buck Regulator with External LDO
7.3.3.4 AVDD Power Sequencing from Buck Regulator
The AVDD LDO has an option of using the power supply from mixed mode buck regulator to reduce the
device power dissipation. The power sequencing mode allows on-the-fly changeover of AVDD LDO input from
DC mains (VM) to buck output (VBK) as shown in Figure 7-5. This sequencing can be configured through the
BUCK_PS_DIS bit . Power sequencing is supported only when buck output voltage is set to 5-V or 5.7-V.
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VM
SW_BK
Ext. Load
VBK
LBK
Control
CBK
GND_BK
FB_BK
BUCK_PS_DIS
VBK
VM
AVDD LDO
REF
+
–
AVDD
External Load
CAVDD
AGND
Figure 7-5. AVDD Power Sequencing from Mixed Mode Buck Regulator
7.3.3.5 Mixed Mode Buck Operation and Control
The buck regulator implements a pulse frequency modulation (PFM) architecture with peak current mode control.
The output voltage of the buck regulator is compared with the internal reference voltage (VBK_REF) which is
internally generated depending on the buck output voltage setting (BUCK_SEL) which constitutes an outer
voltage control loop. Depending on the comparator output going high (VBK < VBK_REF) or low (VBK > VBK_REF),
the high-side power FET of the buck turns on and off respectively. An independent current control loop monitors
the current in high-side power FET (IBK) and turns off the high-side FET when the current becomes higher than
the buck current limit (IBK_CL set by BUCK_CL) - this implements a current limit control for the buck regulator.
Figure 7-6 shows the architecture of the buck and various control/protection loops.
20
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SW_BK
IBK
VM
Ext. Load
VBK
LBK
PWM Control
and Driver
CBK
GND_BK
+
Current Limit
_
+
OC Protection
_
+
UV Protection
_
VM
+
Voltage Control
IBK
IBK_CL
IBK
IBK_OCP
FB_BK
VBK
VBK_UVLO
VBK
VBK_REF
_
Buck
Reference
Voltage
Generator
Buck Control
BUCK_SEL
Figure 7-6. Buck Operation and Control Loops
7.3.3.6 Buck Under Voltage Protection
If at any time the voltage on the FB_BK pin (buck regulator output) falls lower than the VBK_UV threshold,
both the high-side and low-side MOSFETs of the buck regulator are disabled. MCT8315A goes into reset state
whenever buck UV event occurs, since the internal circuitry in MCT8315A is powered from the buck regulator
output.
7.3.3.7 Buck Over Current Protection
The buck over current event is sensed by monitoring the current flowing through high-side MOSFET of the buck
regulator. If the current through the high-side MOSFET exceeds the IBK_OCP threshold for a time longer than
the deglitch time (tOCP_DEG), a buck OCP event is recognized and both the high-side and low-side MOSFETs of
the buck regulator are disabled. MCT8315A goes into reset state whenever buck OCP event occurs, since the
internal circuitry in MCT8315A is powered from the buck regulator output.
7.3.4 AVDD Linear Voltage Regulator
A 3.3-V linear regulator is integrated into MCT8315A and is available for use by external circuitry. This AVDD
LDO regulator is used for powering up the internal circuitry of the device and additionally, this regulator can also
provide the supply voltage for a low-power MCU or other external circuitry supporting up to 20-mA. The output
of the AVDD regulator should be bypassed near the AVDD pin with a X5R or X7R, 1-µF, 6.3-V ceramic capacitor
routed directly back to the adjacent AGND ground pin.
The AVDD nominal, no-load output voltage is 3.3-V.
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FB_BK
BUCK_PS_DIS
VBK
VM
REF
+
–
AVDD
External Load
CAVDD
AGND
Figure 7-7. AVDD Linear Regulator Block Diagram
Use Equation 1 to calculate the power dissipated in the device by the AVDD linear regulator with VM as supply
(BUCK_PS_DIS = 1b)
2 = (88/ F 8#8&& ) × +#8&&
(1)
For example, at a VVM of 24-V, drawing 20-mA out of AVDD results in a power dissipation as shown in Equation
2.
P
24 V 3.3 V u 20 mA
414 mW
(2)
Use Equation 3 to calculate the power dissipated in the device by the AVDD linear regulator with buck output as
supply (BUCK_PS_DIS = 0b)
P = VFB_BK − VAVDD × IAVDD
(3)
7.3.5 Charge Pump
Since the output stages use N-channel FETs, the device requires a gate-drive voltage higher than the VM power
supply to turn-on the high-side FETs. The MCT8315A integrates a charge-pump circuit that generates a voltage
above the VM supply for this purpose.
The charge pump requires two external capacitors (CCP, CFLY) for operation. See Figure 7-1 and Table 5-1 for
details on these capacitors (value, connection, and so forth).
22
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VM
VM
CCP
CP
CPH
VM
Charge
Pump
Control
CFLY
CPL
Figure 7-8. Charge Pump
7.3.6 Slew Rate Control
An adjustable gate-drive current control is provided for the output stage MOSFETs to achieve configurable slew
rate for EMI mitigation. The MOSFET VDS slew rate is a critical factor for optimizing radiated emissions, total
energy and duration of diode recovery spikes and switching voltage transients related to parasitic elements of
the PCB. This slew rate is predominantly determined by the control of the internal MOSFET gate current as
shown in Figure 7-9.
VCP (Internal)
VM
Slew Rate
Control
VCP (Internal)
OUTx
Slew Rate
Control
GND
Figure 7-9. Slew Rate Circuit Implementation
The slew rate of each half-bridge can be adjusted through SLEW_RATE settings. Slew rate can be configured as
25-V/µs, 50-V/µs, 125-V/µs or 200-V/µs. The slew rate is calculated by the rise-time and fall-time of the voltage
on OUTx pin as shown in Figure 7-10.
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VOUTx
VM
VM
80%
80%
20%
20%
0
Time
tfall
trise
Figure 7-10. Slew Rate Timings
7.3.7 Cross Conduction (Dead Time)
The device is fully protected against any cross conduction of MOSFETs - during the switching of high-side
and low-side MOSFETs, MCT8315A avoids shoot-through events by inserting a dead time (tdead). This is
implemented by sensing the gate-source voltage (VGS) of the high-side and low-side MOSFETs and ensuring
that VGS of high-side MOSFET has dropped below turn-off level before switching on the low-side MOSFET of
same half-bridge (or vice-versa) as shown in Figure 7-11and Figure 7-12. The VGS of the high-side and low-side
MOSFETs (VGS_HS and VGS_LS) shown in Figure 7-12 are internal signals.
VM
HS Gate
Control
+
VGS_HS
OUTx
–
LS Gate
Control
+
VGS_LS
GND
–
Figure 7-11. Cross Conduction Protection
24
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VGS_HS
10%
tDEAD
VGS_LS
10%
Time
Figure 7-12. Dead Time
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7.3.8 Speed Control
The MCT8315A offers four methods of directly controlling the speed of the motor. The speed control method is
configured by SPD_CTRL_MODE. The speed command can be controlled in one of the following four ways.
•
•
•
•
PWM input on SPEED pin by varying duty cycle of input signal
Frequency input on SPEED pin by varying frequency of input signal
Analog input on SPEED pin by varying amplitude of input signal
Over I2C by configuring SPEED_CTRL
The speed can also be indirectly controlled by varying the supply voltage (VM).
The signal path from SPEED pin input (or I2C based speed input) to output duty cycle (DUTY_OUT) applied to
FETs is shown in Figure 7-13.
TARGET_DUTY
SPEED Pin
Freq
Freq based
Duty
PWM
PWM Duty
Analog
ADC
DUTY_
CMD
SPEED_
Optional
Transfer
REF /
Speed Loop /
Function POWER_
Power Loop
REF
FETs
AVS, CL_ACC
DUTY_OUT
PWM
2
IC
Figure 7-13. Multiplexing the Speed Command
Figure 7-14 shows the transfer function between DUTY_CMD and SPEED_REF / POWER_REF /
TARGET_DUTY.
SPEED_REF /
POWER_REF/
TARGET_DUTY
MAX_SPEED /
MAX_POWER/
100%
MIN_DUTY x MAX_SPEED /
MIN_DUTY x MAX_POWER /
MIN_DUTY
DUTY_CMD
0
ZERO_
DUTY_
THR
MIN_DUTY
100%
Figure 7-14. Speed Input Transfer Function
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When speed/power loop is disabled (CLOSED_LOOP_MODE = 00b), DUTY_CMD sets the TARGET_DUTY in
% - TARGET_DUTY is 100% when DUTY_CMD is 100% and TARGET_DUTY is equal to MIN_DUTY when
DUTY_CMD is set to MIN_DUTY. TARGET_DUTY stays clamped at MIN DUTY for ZERO_DUTY_THR ≤
DUTY_CMD ≤ MIN_DUTY.
When speed loop is enabled (CLOSED_LOOP_MODE = 01b), DUTY_CMD sets the SPEED_REF
in Hz. MAX_SPEED sets the SPEED_REF at DUTY_CMD of 100%. MIN_DUTY sets the minimum
SPEED_REF (MIN_DUTY x MAX_SPEED). SPEED_REF stays clamped at (MIN_DUTY x MAX_SPEED) for
ZERO_DUTY_THR ≤ DUTY_CMD ≤ MIN_DUTY.
When power loop is enabled (CLOSED_LOOP_MODE = 10b), DUTY_CMD sets the POWER_REF
in W. MAX_POWER sets the POWER_REF at DUTY_CMD of 100%. MIN_DUTY sets the minimum
POWER_REF (MIN_DUTY x MAX_POWER). POWER_REF stays clamped at (MIN_DUTY x POWER_REF)
for ZERO_DUTY_THR ≤ DUTY_CMD ≤ MIN_DUTY.
ZERO_DUTY_THR sets the DUTY_CMD below which SPEED_REF / POWER_REF / TARGET_DUTY is set to
zero and motor is in stopped state. AVS, CL_ACC configure the transient characteristics of DUTY_OUT; the
steady state value of DUTY_OUT is directly configured in % through TARGET_DUTY (when speed/power loop is
disabled) or through SPEED_REF/POWER_REF (when speed/power loop is enabled).
7.3.8.1 Analog Mode Speed Control
Analog input based speed control can be configured by setting SPD_CTRL_MODE to 00b. In this mode, the
duty command (DUTY_CMD) varies with the analog voltage input on the SPEED pin (VSPEED). When 0 ≤
VSPEED ≤ VEN_SB, DUTY_CMD is set to zero and the motor is stopped. When VEX_SB ≤ VSPEED ≤ VANA_FS,
DUTY_CMD varies linearly with VSPEED as shown in Figure 7-15. VEX_SB and VEN_SB are the standby entry and
exit thresholds - refer Section 7.4.1.2 for more information on VEX_SB and VEN_SB. When VSPEED > VANA_FS,
DUTY_CMD is clamped to 100%.
DUTY_CMD
100%
0
VANA_FS
VEN_SB VEX_SB
SPEED pin voltage
Figure 7-15. Analog Mode Speed Control
7.3.8.2 PWM Mode Speed Control
PWM based speed control can be configured by setting SPD_CTRL_MODE to 01b. In this mode, the PWM
duty cycle applied to the SPEED pin can be varied from 0 to 100% and duty command (DUTY_CMD) varies
linearly with the applied PWM duty cycle. When 0 ≤ DutySPEED ≤ DutyEN_SB, DUTY_CMD is set to zero and the
motor is stopped. When DutyEX_SB ≤ DutySPEED ≤ 100%, DUTY_CMD varies linearly with DutySPEED as shown in
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Figure 7-16. DutyEX_SB and DutyEN_SB are the standby entry and exit thresholds - refer Section 7.4.1.2 for more
information on DutyEX_SB and DutyEN_SB. The frequency of the PWM input signal applied to the SPEED pin is
defined as fPWM and the range for this frequency can be configured through SPD_PWM_RANGE_SELECT.
Note
1. fPWM is the frequency of the PWM signal the device can accept at SPEED pin to control motor
speed. It does not correspond to the PWM output frequency that is applied to the motor phases.
The PWM output frequency can be configured through PWM_FREQ_OUT (see Section 7.3.15).
2. SLEEP_TIME should be set longer than the off time in PWM signal (VSPEED < VIL) at lowest duty
input. For example, if fPWM is 10 kHz and lowest duty input is 2%, SLEEP_TIME should be more
than 98 µs to ensure there is no unintended sleep entry.
DUTY_CMD
100%
0
DutyEN_SB DutyEX_SB
100%
PWM Duty at SPEED pin
Figure 7-16. PWM Mode Speed Control
7.3.8.3 I2C based Speed Control
I2C based serial interface can be used for speed control by setting SPD_CTRL_MODE to 10b. In this mode,
the speed command can be written directly into SPEED_CTRL. The SPEED pin can be used to control
the sleep entry and exit - if SPEED pin input is set to a value lower than VEN_SL after SPEED_CTRL has
been set to 0b for a time longer than SLEEP_TIME, MCT8315A enters sleep state. When SPEED pin >
VEX_SL, MCT8315A exits sleep state and speed is controlled through SPEED_CTRL. If 0 ≤ SPEED_CTRL
≤ SPEED_CTRLEN_SB and SPEED pin > VEX_SL, MCT8315A is in standby state. The relationship between
DUTY_CMD and SPEED_CTRL is shown in Figure 7-17. Refer Section 7.4.1.2 for more information on
SPEED_CTRLEN_SB EX_SB and SPEED_CTRLEN_SB EN_SB.
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DUTY_CMD
100%
0
SPEED_CTRLEX_SB
32767
SPEED_CTRL
SPEED_CTRLEN_SB
Figure 7-17. I2C Mode Speed Control
7.3.8.4 Frequency Mode Speed Control
Frequency based speed control is configured by setting SPD_CTRL_MODE to 11b. In this mode, duty
command varies linearly as a function of the frequency of the square wave input at SPEED pin. When 0 ≤
FreqSPEED ≤ FreqEN_SB, DUTY_CMD is set to zero and the motor is stopped. When FreqEX_SB ≤ FreqSPEED ≤
INPUT_MAX_FREQUENCY, DUTY_CMD varies linearly with FreqSPEED as shown in Figure 7-18. FreqEX_SB
and FreqEN_SB are the standby entry and exit thresholds - refer Section 7.4.1.2 for more information on
FreqEX_SB and FreqEN_SB. Input frequency greater than INPUT_MAX_FREQUENCY clamps the DUTY_CMD
to 100%.
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DUTY_CMD
100%
0
INPUT_MAX_FREQUENCY
FreqEN_SB FreqEX_SB
Frequency at SPEED pin
Figure 7-18. Frequency Mode Speed Control
7.3.9 Starting the Motor Under Different Initial Conditions
The motor can be in one of three states when MCT8315A begins the start-up process. The motor may be
stationary, spinning in the forward direction, or spinning in the reverse direction. The MCT8315A includes a
number of features to allow for reliable motor start-up under all of these conditions. Figure 7-19 shows the motor
start-up flow for each of the three initial motor states.
Brake
Align
Double Align
Staonary
IPD
Slow rst cycle
Spinning in forward
direc on
Closed Loop
Coast (Hi-Z)
Brake
Spinning in reverse
direcon
Reverse Drive
Figure 7-19. Starting the motor under different initial conditions
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Note
"Forward" means "spinning in the same direction as the commanded direction", and "Reverse" means
"spinning in the opposite direction as the commanded direction".
7.3.9.1 Case 1 – Motor is Stationary
If the motor is stationary, the commutation must be initialized to be in phase with the position of the motor. The
MCT8315A provides various options to initialize the commutation logic to the motor position and reliably start the
motor.
•
•
•
The align and double align techniques force the motor into alignment by applying a voltage across particular
motor phases to force the motor to rotate in alignment with this phase.
Initial position detect (IPD) determines the position of the motor based on the deterministic inductance
variation, which is often present in BLDC motors.
The slow first cycle method starts the motor by applying a low frequency cycle to align the rotor position to
the applied commutation by the end of one electrical rotation.
MCT8315A also provides a configurable brake option to ensure the motor is stationary before initiating one of
the above start-up methods. Device enters open loop acceleration after going through the configured start-up
method.
7.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
If the motor is spinning forward (same direction as the commanded direction) with sufficient speed (BEMF),
the MCT8315A resynchronizes with the spinning motor and continues commutation by going directly to closed
loop operation. By resynchronizing to the spinning motor, the user achieves the fastest possible start-up time
for this initial condition. This resynchronization feature can be enabled or disabled through RESYNC_EN. If
resynchronization is disabled, the MCT8315A can be configured to wait for the motor to coast to a stop and/or
apply a brake. After the motor has stopped spinning, the motor start-up sequence proceeds as in Case 1,
considering the motor is stationary.
7.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
If the motor is spinning in the reverse direction (the opposite direction as the commanded direction), the
MCT8315A provides several methods to change the direction and drive the motor to the target speed reference
in the commanded direction.
The reverse drive method allows the motor to be driven so that it decelerates through zero speed. The motor
achieves the shortest possible spin-up time when spinning in the reverse direction.
If reverse drive is not enabled, then the MCT8315A can be configured to wait for the motor to coast to a stop
and/or apply a brake. After the motor has stopped spinning, the motor start-up sequence proceeds as in Case 1,
considering the motor is stationary.
Note
Take care when using the reverse drive or brake feature to ensure that the current is limited to an
acceptable level and that the supply voltage does not surge as a result of energy being returned to the
power supply.
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7.3.10 Motor Start Sequence (MSS)
Figure 7-20 shows the motor-start sequence implemented in the MCT8315A device.
Power On
Sleep/Standby
(SPEED_REF/
TARGET_DUTY = 0)
SPEED_REF/
TARGET_DUTY > 0
N
Y
0b
ISD_EN
1b
BEMF <
STAT_DETECT_THR ||
BEMF <
FG_BEMF_THR
Y
N
Reverse
Direcon
of spin
Forward
0b
RVS_DR_EN
0b
1b
RESYNC_EN
1b
0b
HIZ_EN
N
N
1b
Speed
Y>
MIN_DUTY
BEMF <
STAT_DETECT_THR
Hi-Z
Reverse Closed
Loop
Decelera on
Time >
HIZ_TIME
N
N
Motor
coast
meout
Y
Y
STAT_BRK_
EN
0b
1b
Brake
Y
BRAKE_EN
0b
1b
Brake_Roune
Direcon Reversal :
Zero Speed
Crossover
Y
N
Y
Reverse
Open Loop
Deceleraon
BEMF >
RESYNC_MIN_TH
RESHOLD
N
Time >
STARTUP_BRK
_TIME
Y
Motor Start-up
Open loop
Closed Loop
Figure 7-20. Motor Start Sequence
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Brake_Roune
Brake
Time >
BRK_TIME
N
Y
Brake_Rou ne_End
Figure 7-21. Brake Routine
Power-On State
This is the initial state of the Motor Start Sequence (MSS) when MCT8315A
is powered on. In this state, MCT8315A configures the peripherals,
initializes the algorithm parameters from EEPROM and prepares for driving
the motor.
Sleep/Standby
In this state, SPEED_REF/POWER_REF/TARGET_DUTY is set to zero and
MCT8315A is either in sleep or standby mode depending on DEV_MODE
and SPEED/WAKE pin voltage.
SPEED_REF/POWER_REF/
TARGET_DUTY > 0 Judgement
When SPEED_REF/POWER_REF/TARGET_DUTY is set to greater than
zero, MCT8315A exits the sleep/standby state and proceeds to ISD_EN
judgement. As long as SPEED_REF is set to zero, MCT8315A stays in
sleep/standby state.
ISD_EN Judgement
MCT8315A checks to see if the initial speed detect (ISD) function is
enabled (ISD_EN = 1b). If ISD is enabled, MSS proceeds to the BEMF
< STAT_DETECT_THR judgement. Instead, if ISD is disabled, the MSS
proceeds directly to the BRAKE_EN judgement.
BEMF < STAT_DETECT_THR
or BEMF < FG_BEMF_THR
Judgement
ISD determines the initial condition (speed, angle, direction of spin) of the
motor (see Section 7.3.10.1). If motor is deemed to be stationary (BEMF
< STAT_DETECT_THR or BEMF < FG_BEMF_THR), the MSS proceeds
to second BEMF < STAT_DETECT_THR judgement. If the motor is not
stationary, MSS proceeds to verify the direction of spin.
Direction of spin Judgement
The MSS determines whether the motor is spinning in the forward or
the reverse direction. If the motor is spinning in the forward direction,
the MCT8315A proceeds to the RESYNC_EN judgement. If the motor is
spinning in the reverse direction, the MSS proceeds to the RVS_DR_EN
judgement.
RESYNC_EN Judgement
If RESYNC_EN is set to 1b, MCT8315A proceeds to BEMF >
RESYNC_MIN_THRESHOLD judgement. If RESYNC_EN is set to 0b, MSS
proceeds to HIZ_EN judgement.
BEMF >
RESYNC_MIN_THRESHOLD
Judgement
If motor speed is such that BEMF > RESYNC_MIN_THRESHOLD,
MCT8315A uses the speed and position information from ISD to transition
to the closed loop state (see Motor Resynchronization ) directly. If
BEMF < RESYNC_MIN_THRESHOLD, MCT8315A proceeds to BEMF <
STAT_DETECT_THR judgement.
BEMF < STAT_DETECT_THR
Judgement
If motor speed is such that BEMF > STAT_DETECT_THR, MCT8315A
proceeds to motor coast timeout. If BEMF < STAT_DETECT_THR,
MCT8315A proceeds to STAT_BRK_EN judgement.
Motor Coast Timeout
MCT8315A waits for 200000 PWM cycles for the motor to coast down to
a speed where BEMF < STAT_DETECT_THR; after 200000 PWM cycles
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lapse in the motor coast state, MCT8315A proceeds to STAT_BRK_EN
judgement irrespective of BEMF. If BEMF < STAT_DETECT_THR during
motor coast before the 200000 cycle timeout, MCT8315A proceeds to
STAT_BRK_EN judgement immediately.
STAT_BRK_EN Judgement
The MSS checks if the stationary brake function is enabled (STAT_BRK_EN
=1b). If the stationary brake function is enabled, the MSS advances to the
stationary brake routine. If the stationary brake function is disabled, the
MSS advances to motor start-up state (see Section 7.3.10.4).
Stationary Brake Routine
The stationary brake routine can be used to ensure the motor is completely
stationary before attempting to start the motor. The stationary brake is
applied by turning on all three low-side driver MOSFETs for a time
configured by STARTUP_BRK_TIME.
RVS_DR_EN Judgement
The MSS checks to see if the reverse drive function is enabled
(RVS_DR_EN = 1b). If it is enabled, the MSS transitions to check speed
of the motor in reverse direction. If the reverse drive function is not enabled
(RVS_DR_EN = 0b), the MSS advances to the HIZ_EN judgement.
Speed > MIN_DUTY Judgement The MSS checks if the speed (in reverse direction) is higher than the
speed at MIN_DUTY - till the speed (in reverse direction) is higher than
the speed at MIN_DUTY, MSS stays in reverse closed loop deceleration.
When speed (in reverse direction) drops below the speed at MIN_DUTY, the
MSS transitions to reverse open loop deceleration.
Reverse Open Loop
Deceleration and Zero Speed
Crossover
In reverse open loop deceleration, the MCT8315A decelerates the motor
in open-loop till speed reaches zero. At zero speed, direction changes and
MCT8315A begins open loop acceleration.
HIZ_EN Judgement
The MSS checks to determine whether the coast (Hi-Z) function is enabled
(HIZ_EN = 1b). If the coast function is enabled (HIZ_EN = 1b), the MSS
advances to the coast routine. If the coast function is disabled (HIZ_EN =
0b), the MSS advances to the BRAKE_EN judgement.
Coast (Hi-Z) Routine
The device coasts the motor by turning OFF all six MOSFETs for a certain
time configured by HIZ_TIME.
BRAKE_EN Judgement
The MSS checks to determine whether the brake function is enabled
(BRAKE_EN = 1b). If the brake function is enabled (BRAKE_EN = 1b),
the MSS advances to the brake routine. If the brake function is disabled
(BRAKE_EN = 0b), the MSS advances to the motor start-up state (see
Section 7.3.10.4).
Brake Routine
MCT8315A implements a brake by turning on all three (high-side or lowside) MOSFETS for BRK_TIME. Brake is applied either using high-side or
low-side MOSFETs based on BRK_MODE configuration.
Closed Loop
In this state, the MCT8315A drives the motor with sensorless trapezoidal
commutation based on either zero cross detection or BEMF integration.
7.3.10.1 Initial Speed Detect (ISD)
The ISD function is used to identify the initial condition of the motor and is enabled by setting ISD_EN to 1b. The
initial speed, position and direction is determined by sensing the three phase voltages. ISD can be disabled by
setting ISD_EN to 0b. If the function is disabled (ISD_EN set to 0b), the MCT8315A does not perform the initial
speed detect function and proceeds to check if the brake routine (BRAKE_EN) is enabled.
7.3.10.2 Motor Resynchronization
The motor resynchronization function works when the ISD and resynchronization functions are both enabled and
the device determines that the initial state of the motor is spinning in the forward direction (same direction as
the commanded direction). The speed and position information measured during ISD are used to initialize the
34
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drive state of the MCT8315A, which can transition directly into closed loop state without needing to stop the
motor. In the MCT8315A, motor resynchronization can be enabled/disabled through RESYNC_EN bit. If motor
resynchronization is disabled, the device proceeds to check if the motor coast (Hi-Z) routine is enabled.
7.3.10.3 Reverse Drive
The MCT8315A uses the reverse drive function to change the direction of the motor rotation when ISD_EN
and RVS_DR_EN are both set to 1b and the ISD determines the motor spin direction to be opposite to
that of the commanded direction. Reverse drive includes synchronizing with the motor speed in the reverse
direction, reverse decelerating the motor through zero speed, changing direction, and accelerating in open
loop in forward (or commanded) direction until the device transitions into closed loop in forward direction
(see Figure 7-22). MCT8315A uses the same parameter values for open to closed loop handoff threshold
(OPN_CL_HANDOFF_THR), open loop acceleration rates (OL_ACC_A1, OL_ACC_A2) and open loop current
limit (OL_ILIMIT) in the reverse direction as in the forward direction..
Speed
Close loop
Handoff to close loop
Open loop
Time
Handoff to open loop
Open Loop
Reverse Deceleration
Figure 7-22. Reverse Drive Function
7.3.10.4 Motor Start-up
There are different options available for motor start-up from a stationary position and these options can be
configured by MTR_STARTUP. In align and double align mode, the motor is aligned to a known position by
injecting a DC current. In IPD mode, the rotor position is estimated by applying 6 different high-frequency pulses.
In slow first cycle mode, the motor is started by applying a low frequency cycle.
7.3.10.4.1 Align
Align is enabled by configuring MTR_STARTUP to 00b. The MCT8315A aligns the motor by injecting a DC
current using a particular phase pattern (phase-C high-side FET and phase-B low-side FET are ON) - current
flowing into phase-B and flowing out from phase-C for a certain time configured by ALIGN_TIME.
The duty cycle during align is defined by ALIGN_DUTY. In MCT8315A, current limit during align is configured by
ALIGN_CURR_THR.
A fast change in the phase current during align may result in a sudden change in the driving torque and this
could result in acoustic noise. To avoid this, the MCT8315A ramps up duty cycle from 0 to until it reaches
ALIGN_DUTY at a configurable rate set by ALIGN_RAMP_RATE. At the end of align routine, the motor will be
aligned at the known position.
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7.3.10.4.2 Double Align
Double align is enabled by configuring MTR_STARTUP to 01b. Single align is not reliable when the initial
position of the rotor is 180o out of phase with the applied phase pattern. In this case, it is possible to have
start-up failures using single align. In order to improve the reliabilty of align based start-up, the MCT8315A
provides the option of double align start-up. In double align start-up, MCT8315A uses a phase pattern for the
second align that is 60o out of phase with the first align phase pattern in the commanded direction. In double
align, relevant parameters like align time, current limit, ramp rate are the same as in the case of single align two different phase patterns are applied in succession with the same parameters to ensure that the motor will be
aligned to a known position irrespective of initial rotor position.
7.3.10.4.3 Initial Position Detection (IPD)
Initial Position Detection (IPD) can be enabled by configuring MTR_STARTUP to 10b. In IPD, inductive sense
method is used to determine the initial position of the motor using the spatial variation in the motor inductance.
Align or double align may result in the motor spinning in the reverse direction before starting open loop
acceleration. IPD can be used in such applications where reverse rotation of the motor is unacceptable. IPD
does not wait for the motor to align with the commutation and therefore can allow for a faster motor start-up
sequence. IPD works well when the inductance of the motor varies as a function of position. IPD works by
pulsing current in to the motor and hence can generate acoustics which must be taken into account when
determining the best start-up method for a particular application.
7.3.10.4.3.1 IPD Operation
IPD operates by sequentially applying six different phase patterns according to the following sequence:
BC-> CB-> AB-> BA-> CA-> AC (see Figure 7-23). When the current reaches the threshold configured by
IPD_CURR_THR, the MCT8315A stops driving the particular phase pattern and measures the time taken to
reach the current threshold from when the particular phase pattern was applied. Thus, the time taken to reach
IPD_CURR_THR is measured for all six phase patterns - this time varies as a function of the inductance in
the motor windings. The state with the shortest time represents the state with the minimum inductance. The
minimum inductance is because of the alignment of the north pole of the motor with this particular driving state.
A
IPD_CLK
B
Clock
C
Drive
BC
CB
AB
BA
CA
AC
IPD_CURR_THR
Current
Search the Minimum Time
Minimum
Time
Smallest
Inductance
Saturation Position of
the Magnetic Field
Permanent
Magnet Position
Figure 7-23. IPD Function
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7.3.10.4.3.2 IPD Release Mode
Two modes are available for configuring the way the MCT8315A stops driving the motor when the current
threshold is reached. The recirculate (or brake) mode is selected if IPD_RLS_MODE = 0b. In this configuration,
the low-side (LSC) MOSFET remains ON to allow the current to recirculate between the MOSFET (LSC) and
body diode (LSA) (see Figure 7-24). Hi-Z mode is selected if IPD_RLS_MODE = 1b. In Hi-Z mode, both the
high-side (HSA) and low-side (LSC) MOSFETs are turned OFF and the current recirculates through the body
diodes back to the power supply (see Figure 7-25).
In the Hi-Z mode, the phase current has a faster settle-down time, but that can result in a voltage increase on
VM. The user must manage this with an appropriate selection of either a clamp circuit or by providing sufficient
capacitance between VM and PGND to absorb the energy. If the voltage surge cannot be contained or if it is
unacceptable for the application, recirculate mode must be used. When using the recirculate mode, select the
IPD_CLK_FREQ appropriately to give the current in the motor windings enough time to decay to 0-A before the
next IPD phase pattern is applied.
HSA
HSB
HSC
M
VM
LSA
HSA
LSB
LSC
HSB
HSC
M
VM
LSA
Driving
LSB
LSC
Brake (Recirculate)
Figure 7-24. IPD Release Mode - Brake (0b)
HSA
HSB
HSC
M
VM
LSA
HSA
LSB
LSC
HSB
HSC
M
VM
LSA
Driving
LSB
LSC
Hi-Z (Tri-State)
Figure 7-25. IPD Release Mode - Tristate (1b)
7.3.10.4.3.3 IPD Advance Angle
After the initial position is detected, the MCT8315A begins driving the motor in open loop at an angle specified
by IPD_ADV_ANGLE.
Advancing the drive angle anywhere from 0° to 180° results in positive torque. Advancing the drive angle by
90° results in maximum initial torque. Applying maximum initial torque could result in uneven acceleration to the
rotor. Select the IPD_ADV_ANGLE to allow for smooth acceleration in the application (see Figure 7-26).
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Motor spinning direction
A
B
C
B
A
A
B
C
C
30 advance
60 advance
A
B
C
90 advance
A
B
C
120 advance
Figure 7-26. IPD Advance Angle
7.3.10.4.4 Slow First Cycle Startup
Slow First Cycle start-up is enabled by configuring MTR_STARTUP to 11b. In slow first cycle start-up, the
MCT8315A starts motor commutation at a frequency defined by SLOW_FIRST_CYCLE_FREQ. The frequency
configured is used only for first cycle, and then the motor commutation follows acceleration profile configured by
open loop acceleration coefficients A1 and A2. The slow first cycle frequency has to be configured to be slow
enough to allow motor to synchronize with the commutation sequence. This mode is useful when fast startup is
desired as it significantly reduces the align time.
7.3.10.4.5 Open loop
Upon completing the motor position initialization with either align, double align, IPD or slow first cycle, the
MCT8315A begins to accelerate the motor in open loop. During open loop, fixed duty cycle is applied and the
cycle by cycle current limit functionality is used to regulate the current.
In MCT8315A, open loop current limit threshold is selected through OL_ILIMIT_CONFIG and is set either
by CBC_ILIMIT or OL_ILIMIT based on the configuration of OL_ILIMIT_CONFIG. Open loop duty cycle
is configured through OL_DUTY. While the motor is in open loop, speed (and commutation instants) is
determined by Equation 4. In MCT8315A, open loop acceleration coefficients, A1 and A2 are configured through
OL_ACC_A1 and OL_ACC_A2 respectively. The function of the open-loop operation is to drive the motor to
a speed at which the motor generates sufficient BEMF to allow the BEMF zero-crossing based commutation
control to accurately drive the motor.
Speed (t) = A1 * t + 0.5 * A2 * t2
(4)
7.3.10.4.6 Transition from Open to Closed Loop
MCT8315A has an internal mechanism to determine the motor speed for transition from open loop commutation
to BEMF zero crossing based closed loop commutation. This feature of automatically deciding the open to
closed handoff speed can be enabled by configuring AUTO_HANDOFF to 1b. If AUTO_HANDOFF is set to 0b,
the open to closed loop handoff speed needs to be configured by OPN_CL_HANDOFF_THR. The closed loop in
this section does not refer to closed speed loop - it refers to the commutation control changing from open loop
(equation based) to closed loop (BEMF zero crossing based).
7.3.11 Closed Loop Operation
In closed loop operation, the MCT8315A drives the motor using trapezoidal commutation. The commutation
instant is determined by the BEMF zero crossing on the phase which is not driven (Hi-Z). The duty cycle of the
applied motor voltage is determined by DUTY OUT (see Speed Control).
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7.3.11.1 120o Commutation
In 120o commutation, each phase is driven for 120o and is Hi-Z for 60o within each half electrical cycle as
shown in Figure 7-27. In 120o commutation there are six different commutation states. 120o commutation can
be configured by setting COMM_CONTROL to 00b. MCT8315A supports different modulation modes with 120o
commutation which can be configured through PWM_MODUL.
©
©
ZC
©
ZC
©
ZC
©
©
ZC
ZC
©
ZC
ZC
© Commutaon point
ZC Back-EMF zero crossings
Phase
A
PHASE CURRENT
PHASE VOLTAGE
Phase
B
Phase
C
Figure 7-27. 120o commutation
7.3.11.1.1 High-Side Modulation
High-side modulation can be configured by setting PWM_MODUL to 00b. In high-side modulation, for a given
commutation state, one of the high-side FETs is switching with the commanded duty cycle DUTY_OUT, while the
low-side FET is ON with 100% duty cycle (see Figure 7-28).
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ZC
ZC
ZC
ZC
ZC
ZC
ZC
ZC
ZC
ZC
Phase
Voltage A
Phase
Voltage B
Phase
Voltage C
Figure 7-28. 120o commutation in High Side Modulation Mode
7.3.11.1.2 Low-Side Modulation
Low-side modulation can be configured by setting PWM_MODUL to 01b. In low-side modulation, for a given
commutation state, one of the low-side FETs is switching with the commanded duty cycle DUTY_OUT, while the
high-side FET is ON with 100% duty cycle (see Figure 7-29).
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ZC
ZC
ZC
ZC
ZC
ZC
ZC
ZC
ZC
ZC
Phase
Voltage A
Phase
Voltage B
Phase
Voltage C
Figure 7-29. 120 o commutation in Low Side Modulation Mode
7.3.11.1.3 Mixed Modulation
Mixed modulation can be configured by setting PWM_MODUL to 10b. In mixed modulation, MCT8315A
dynamically switches between high and low-side modulation (see Figure 7-30). The switching losses are
distributed evenly amongst the high and low-side MOSFETs in mixed modulation mode.
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ZC
ZC
ZC
ZC
ZC
ZC
ZC
ZC
ZC
ZC
Phase
Voltage A
Phase
Voltage B
Phase
Voltage C
Figure 7-30. 120o commutation in Mixed Modulation Mode
7.3.11.2 Variable Commutation
Variable commutation can be configured by setting COMM_CONTROL to 01b. 120o commutation may result in
acoustic noise due to the long Hi-Z period causing some torque ripple in the motor. In order to reduce this torque
ripple and acoustic noise, the MCT8315A uses variable commutation to reduce the phase current ripple at
commutation by extending 120o driving time and gradually decreasing duty cycle prior to entering Hi-Z state. In
this mode, the phase is Hi-Z between 30o and 60o and this window size is dynamically adjusted based on speed.
A smaller window size will typically give better acoustic performance. Figure 7-31 shows 150o commutation with
30o window size.
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©
©
ZC
©
ZC
©
ZC
©
ZC
©
ZC
©
ZC
ZC
© Commutaon point
Phase
A
ZC Back-EMF zero crossings
PHASE CURRENT
PHASE VOLTAGE
Phase
B
15 deg
30 deg 15 deg
Phase
C
Figure 7-31. 150o commutation
Note
Different modulation modes are supported only with 120o commutation; variable commutation uses
mixed modulation mode only.
7.3.11.3 Lead Angle Control
To achieve the best efficiency, it is often desirable to control the drive state of the motor so that the motor
phase current is aligned with the motor BEMF voltage. MCT8315A provides the option to advance or delay the
phase voltage from the commutation point by adjusting the lead angle. The lead angle can be adjusted to obtain
optimal efficiency. This can be accomplished by operating the motor at constant speed and load conditions and
adjusting the lead angle (LD_ANGLE) until the minimum current is achieved. The MCT8315A has the capability
to apply both positive and negative lead angle (by configuring LD_ANGLE_POLARITY) as shown in Figure 7-32
Lead angle can be calculated by {LD_ANGLE x 0.12}o; for example, if the LD_ANGLE is 0x1E and
LD_ANGLE_POLARITY is 1b, then a lead angle of +3.6o(advance) is applied. If LD_ANGLE_POLARITY is
0b, then a lead angle of -3.6o(delay) is applied.
Note
For 120o commutation, the negative lead angle is limited to -20o; any lead angle lower than that will be
clamped to -20o.
For variable commutation, negative lead angle is not supported and positive lead angle is limited
to +15o. Anything configured higher than +15o or lower than 00 will be clamped to 15o and 0o
respectively.
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(a)
Phase
Voltage
}POS
Phase
BEMF
(b)
Phase
Voltage
}NEG
Phase
BEMF
Figure 7-32. Positive and Negative Lead Angle Definition
7.3.11.4 Closed loop accelerate
To prevent sudden changes in the torque applied to the motor which could result in acoustic noise, the
MCT8315A device provides the option of limiting the maximum rate at which the speed command can change.
The closed loop acceleration rate parameter sets the maximum rate at which the speed command changes
(shown in Figure 7-33). In the MCT8315A, closed loop acceleration rate is configured through CL_ACC.
y%
Speed command
input
x%
y%
Speed command
after closed loop
accelerate buffer
x%
Closed loop
accelerate settings
Figure 7-33. Closed loop accelerate
7.3.12 Speed Loop
MCT8315A has a speed loop option which can be used to maintain constant speed under varying operating
conditions. Speed loop is enabled by setting CLOSED_LOOP_MODE to 01b. Kp and Ki coefficients are
configured through SPD_POWER_KP and SPD_POWER_KI. The output of speed loop (SPEED_PI_OUT) is
used to generate the DUTY_OUT (see Figure 7-13). The PI controller output upper (VMAX) and lower bound
(VMIN) saturation limits are configured through SPD_POWER_V_MAX and SPD_POWER_V_MIN respectively.
When output of the speed loop saturates, the integrator is disabled to prevent integral wind-up. The speed loop
PI controller is as in Figure 7-34.
SPEED_REF is derived from duty command input and maximum motor speed (MAX_SPEED) configured by
user (see Equation 5). In speed loop mode, minimum SPEED_REF is set by MIN_DUTY * MAX_SPEED.
SPEED_REF = DUTY_CMD * MAX_SPEED
44
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MAX_SPEED
VMAX
SPEED_REF
+
DUTY CMD
Kp
-
+
SPEED_PI_OUT
OUT
+
VMIN
SPEED_MEAS
Ki
+
+
Z-1
Switch Close
If VMIN slower retry time fault > faster retry time fault
> report only fault. For example, if a latched and retry fault happen simultaneously, the device
stays latched in fault mode until user issues clear fault command by writing 1b to CLR_FLT. If two
retry faults with different retry times happen simultaneously, the device retries only after the longer
(slower) retry time lapses.
5. Recovery refers only to state of FETs (Hi-Z or active) after the fault condition is removed.
Automatic indicates that the device automatically recovers (and FETs are active) when retry time
lapses after the fault condition is removed. Latched indicates that the device waits for clearing of
fault condition (by writing 1b to CLR_FLT bit) to make the FETs active again.
6. Actionable (latched or retry) faults can take up to 200-ms after fault response (FETs in Hi-Z) to be
reported on nFAULT pin (as logic low), ALARM pin (as logic high) and fault status registers.
7. Latched faults can take up to 200-ms after CLR_FLT command is issued (over I2C) to be cleared.
Table 7-2. Fault Action and Response
FAULT
CONDITION
CONFIGURATION
REPORT
FETs
DIGITAL
RECOVERY
VM undervoltage
VVM < VUVLO
—
—
Hi-Z
Disabled
Automatic:
VVM > VUVLO
AVDD undervoltage
VAVDD < VAVDD_UV
—
—
Hi-Z
Disabled
Automatic:
VAVDD > VAVDD_UV
Buck undervoltage
(BUCK_UV)
VFB_BK < VBK_UV
—
—
Active/Hi-Z
Active/Disabled
Automatic:
VFB_BK > VBK_UV
Charge pump
undervoltage
(VCP_UV)
VCP < VCPUV
—
nFAULT and
GATE_DRIVER_FA
ULT_STATUS
register
Hi-Z
Active
Automatic:
VVCP > VCPUV
OVP_EN = 0b
None
Active
Active
No action
OVP_EN = 1b
nFAULT and
GATE_DRIVER_FA
ULT_STATUS
register
Hi-Z
Active
Automatic:
VVM < VOVP
OCP_MODE = 00b
nFAULT and
GATE_DRIVER_FA
ULT_STATUS
register
Hi-Z
Active
Latched:
CLR_FLT
OCP_MODE = 01b
nFAULT and
GATE_DRIVER_FA
ULT_STATUS
register
Hi-Z
Active
Retry:
tRETRY
OCP_MODE = 10b
nFAULT and
GATE_DRIVER_FA
ULT_STATUS
register
Active
Active
No action
OCP_MODE = 11b
None
Active
Active
No action
—
—
Hi-Z
Disabled
Automatic
Over Voltage
Protection
(OVP)
Over Current
Protection
(OCP)
Buck Overcurrent
Protection
(BUCK_OCP)
VVM > VOVP
IPHASE > IOCP
IBK > IBK_OCP
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Table 7-2. Fault Action and Response (continued)
FAULT
Motor Lock
(MTR_LCK )
Cycle by Cycle
Current Limit
(CBC_ILIMIT)
60
CONDITION
Motor lock: Abnormal
Speed; No Motor Lock;
Loss of Sync
VSOX > CBC_ILIMIT
CONFIGURATION
REPORT
FETs
DIGITAL
RECOVERY
MTR_LCK_MODE =
0000b or 0001b
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
Hi-Z
Active
Latched:
CLR_FLT
MTR_LCK_MODE =
0010b
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
High side brake
Active
Latched:
CLR_FLT
MTR_LCK_MODE =
0011b
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
Low side brake
Active
Latched:
CLR_FLT
MTR_LCK_MODE =
0100b or 0101b
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
Hi-Z
Active
Retry:
tLCK_RETRY
MTR_LCK_MODE =
0110b
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
High side brake
Active
Retry:
tLCK_RETRY
MTR_LCK_MODE =
0111b
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
Low side brake
Active
Retry:
tLCK_RETRY
MTR_LCK_MODE =
1000b
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
Active
Active
No action
MTR_LCK_MODE =
1xx1b
None
Active
Active
No action
CBC_ILIMIT_MODE =
0000b
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
Recirculation
Active
Automatic:
Next PWM cycle
CBC_ILIMIT_MODE =
0001b
None
Recirculation
Active
Automatic:
Next PWM cycle
CBC_ILIMIT_MODE =
0010b
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
Recirculation
Active
Automatic:
VSOX < CBC_ILIMIT
CBC_ILIMIT_MODE =
0011b
None
Recirculation
Active
Automatic:
VSOX < CBC_ILIMIT
CBC_ILIMIT_MODE =
0100b
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
Recirculation
Active
Automatic:
PWM cycle > CBC_RETRY_PWM_CYC
CBC_ILIMIT_MODE =
0101b
None
Recirculation
Active
Automatic:
PWM cycle > CBC_RETRY_PWM_CYC
CBC_ILIMIT_MODE=
0110b
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
Active
Active
No action
CBC_ILIMIT_MODE =
0111b, 1xxxb
None
Active
Active
No action
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Table 7-2. Fault Action and Response (continued)
FAULT
Lock-Detection
Current Limit
(LOCK_ILIMIT)
CONDITION
VSOX > LOCK_ILIMIT
IPD Timeout Fault
(IPD_T1_FAULT
and
IPD_T2_FAULT)
IPD TIME > 500ms
(approx.), during IPD
current ramp up or ramp
down
IPD Timeout Fault
(IPD_T1_FAULT
and
IPD_T2_FAULT)
IPD TIME > 500ms
(approx.), during IPD
current ramp up or ramp
down
IPD Frequency
Fault
(IPD_FREQ_FAULT
)
IPD pulse before the
current decay in previous
IPD pulse
IPD Frequency
Fault
(IPD_FREQ_FAULT
)
IPD pulse before the
current decay in previous
IPD pulse
Maximum VM
(overvoltage) fault
Minimum VM
(undervoltage) fault
CONFIGURATION
REPORT
FETs
DIGITAL
RECOVERY
LOCK_ILIMIT_MODE =
0000b
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
Hi-Z
Active
Latched:
CLR_FLT
LOCK_ILIMIT_MODE =
0001b
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
Recirculation
Active
Latched:
CLR_FLT
LOCK_ILIMIT_MODE =
0010b
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
High-side brake
Active
Latched:
CLR_FLT
LOCK_ILIMIT_MODE =
0011b
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
Low-side brake
Active
Latched:
CLR_FLT
LOCK_ILIMIT_MODE =
0100b
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
Hi-Z
Active
Retry:
tLCK_RETRY
LOCK_ILIMIT_MODE =
0101b
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
Recirculation
Active
Retry:
tLCK_RETRY
LOCK_ILIMIT_MODE =
0110b
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
High-side brake
Active
Retry:
tLCK_RETRY
LOCK_ILIMIT_MODE =
0111b
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
Low-side brake
Active
Retry:
tLCK_RETRY
LOCK_ILIMIT_MODE=
1000b
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
Active
Active
No action
LOCK_ILIMIT_MODE =
1xx1b
None
Active
Active
No action
IPD_TIMEOUT_FAULT_E
N = 0b
—
Active
Active
No action
IPD_TIMEOUT_FAULT_E
N = 1b
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
Hi-Z
Active
Retry: tLCK_RETRY
—
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
Hi-Z
Active
Latched: CLR_FLT
IPD_FREQ_FAULT_EN =
0b
—
Active
Active
No action
IPD_FREQ_FAULT_EN =
1b
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
Hi-Z
Active
Retry: tLCK_RETRY
—
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
Hi-Z
Active
Latched: CLR_FLT
MAX_VM_MODE = 0b
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
Hi-Z
Active
Latched:
CLR_FLT
MAX_VM_MODE = 1b
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
Hi-Z
Active
Automatic:
(VVM < MAX_VM_MOTOR - 1)-V
MIN_VM_MODE = 0b
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
Hi-Z
Active
Latched:
CLR_FLT
MIN_VM_MODE = 1b
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
Hi-Z
Active
Automatic:
(VVM > MIN_VM_MOTOR + 0.5)-V
VVM > MAX_VM_MOTOR,
if MAX_VM_MOTOR ≠
000b
VVM < MIN_VM_MOTOR,
if MIN_VM_MOTOR ≠
000b
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Table 7-2. Fault Action and Response (continued)
FAULT
External Watchdog
CONDITION
Watchdog tickle does not
arrive before configured
time interval when
EXT_WDT_EN =1b. Refer
Section 7.5.5
CONFIGURATION
REPORT
FETs
DIGITAL
RECOVERY
EXT_WDT_FAULT_MOD
E = 0b
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
Active
Active
No action
EXT_WDT_FAULT_MOD
E = 1b
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
Hi-Z
Active
Latched:
CLR_FLT
Bus Current Limit
IVM >
BUS_CURRENT_LIMIT.
Refer
nFAULT and
Active; motor speed
BUS_CURRENT_LIMIT_E CONTROLLER_FA
will be restricted to
NABLE = 1b
ULT_STATUS
limit DC bus current
register
Active
Automatic: Speed restriction is removed
when IVM < BUS_CURRENT_LIMIT
Current Loop
Saturation
Indication of current loop
saturation due to lower
VVM
SATURATION_FLAGS_E
N = 1b
nFAULT and
Active; motor speed
CONTROLLER_FA
may not reach
ULT_STATUS
speed reference
register
Active
Automatic: motor will reach reference
operating point upon exiting saturation
Speed Loop
Saturation
Indication of speed loop
saturation due to lower
VVM, lower ILIMIT setting
etc.,
SATURATION_FLAGS_E
N = 1b
nFAULT and
Active; motor speed
CONTROLLER_FA
may not reach
ULT_STATUS
speed reference
register
Active
Automatic: motor will reach reference
operating point upon exiting saturation
Thermal warning
(OTW)
TJ > TOTW
Thermal shutdown
(TSD)
TJ > TTSD
62
OTW_REP = 0b
—
Active
Active
No action
OTW_REP = 1b
nFAULT and
GATE_DRIVER_FA
ULT_STATUS
register
Active
Active
Automatic:
TJ < TOTW – TOTW_HYS
—
nFAULT and
GATE_DRIVER_FA
ULT_STATUS
register
Hi-Z
Active
Automatic:
TJ < TTSD – TTSD_HYS
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7.3.21.1 VM Supply Undervoltage Lockout
If at any time the input supply voltage on the VM pin falls lower than the VUVLO threshold (VM UVLO falling
threshold), all the integrated FETs, driver charge-pump and digital logic are disabled as shown in Figure 7-49.
MCT8315A goes into reset state whenever VM UVLO event occurs.
VUVLO (max) rising
VUVLO (min) rising
VUVLO (max) falling
VUVLO (min) falling
VVM
DEVICE OFF
DEVICE ON
DEVICE ON
Time
Figure 7-49. VM Supply Undervoltage Lockout
7.3.21.2 AVDD Undervoltage Lockout (AVDD_UV)
If at any time the voltage on the AVDD pin falls lower than the VAVDD_UV threshold, all the integrated FETs, driver
charge-pump and digital logic controller are disabled. Since internal circuitry in MCT8315A is powered through
the AVDD regulator, MCT8315A goes into reset state whenever AVDD UV event occurs.
7.3.21.3 BUCK Undervoltage Lockout (BUCK_UV)
If at any time the input supply voltage on the FB_BK pin falls lower than the VBK_UVLO threshold, both the
high-side and low-side MOSFETs of the buck regulator are disabled . Since internal circuitry in MCT8315A is
powered through the buck regulator, MCT8315A goes into reset state whenever buck UV event occurs.
7.3.21.4 VCP Charge Pump Undervoltage Lockout (CPUV)
If at any time the voltage on the VCP pin (charge pump) falls lower than the VCPUV threshold, all the integrated
FETs are disabled and the nFAULT pin is driven low. The DRIVER_FAULT and VCP_UV bits are set to 1b in
the status registers. Normal operation resumes (driver operation and the nFAULT pin is released) when the VCP
undervoltage condition clears. The VCP_UV bit stays set until cleared through the CLR_FLT bit.
7.3.21.5 Overvoltage Protection (OVP)
If at any time input supply voltage on the VM pins rises higher than VOVP, all the integrated FETs are disabled
and the nFAULT pin is driven low. The DRIVER_FAULT and OVP bits are set to 1b in the status registers.
Normal operation resumes (driver operation and the nFAULT pin is released) when the OVP condition clears.
The OVP bit stays set until cleared through the CLR_FLT bit. Setting the OVP_EN to 0b disables this protection
feature.
The OVP threshold can be set to 22-V or 34-V based on the OVP_SEL bit.
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VVM
VOVP (max) rising
VOVP (min) rising
VOVP (max) falling
VOVP (min) falling
DEVICE ON
DEVICE OFF
DEVICE ON
nFAULT
Time
Figure 7-50. Over Voltage Protection
7.3.21.6 Overcurrent Protection (OCP)
MOSFET overcurrent event is sensed by monitoring the current flowing through the FETs. If the current across a
FET exceeds the IOCP threshold for longer than the deglitch time tOCP, an OCP event is recognized and action is
taken according to OCP_MODE. The IOCP threshold is set through the OCP_LVL, tOCP is set through OCP_DEG
and the OCP_MODE can be configured in four different modes: latched shutdown, automatic retry, report only
and disabled.
7.3.21.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
When an OCP event happens in this mode, all MOSFETs are disabled and the nFAULT pin is driven low. The
DRIVER_FAULT, OCP and corresponding FET's OCP bits are set to 1b in the status registers. Normal operation
resumes (driver operation and the nFAULT pin is released) when the OCP condition clears and a clear fault
command is issued through the CLR_FLT bit.
Peak Current due
to deglitch time
IOCP
IOUTx
tOCP
nFAULT Pulled High
nFAULT Released
Fault Condition
nFAULT
Time
Clear Fault
Figure 7-51. Overcurrent Protection - Latched Shutdown Mode
7.3.21.6.2 OCP Automatic Retry (OCP_MODE = 01b)
When an OCP event happens in this mode, all the FETs are disabled and the nFAULT pin is driven low.
The DRIVER_FAULT, OCP and corresponding FET's OCP bits are set to 1b in the fault status registers.
64
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Normal operation resumes automatically (gate driver operation and the nFAULT pin is released) after the tRETRY
(OCP_RETRY) time elapses. The DRIVER_FAULT bit is reset to 0b after the tRETRY period expires. The OCP
and corresponding FET's OCP bits are set to 1b until cleared through the CLR_FLT bit.
Peak Current due
to deglitch time
IOCP
IOUTx
tRETRY
tOCP
nFAULT Pulled High
nFAULT Released
Fault Condition
nFAULT
Time
Figure 7-52. Overcurrent Protection - Automatic Retry Mode
7.3.21.6.3 OCP Report Only (OCP_MODE = 10b)
No protective action is taken when an OCP event happens in this mode. The overcurrent event is reported
by setting the DRIVER_FAULT, OCP, and corresponding FET's OCP bits to 1b in the fault status registers.
The device continues to operate as usual. The external controller manages the overcurrent condition by acting
appropriately. The reporting clears when the OCP condition clears and a clear fault command is issued through
the CLR_FLT bit.
7.3.21.6.4 OCP Disabled (OCP_MODE = 11b)
No action is taken when an OCP event happens in this mode.
7.3.21.7 Buck Overcurrent Protection
The buck overcurrent event is sensed by monitoring the current flowing through high-side MOSFET of the buck
regulator. If the current through the high-side MOSFET exceeds the IBK_OCP threshold for a time longer than
the deglitch time (tOCP), a buck OCP event is recognized and the buck regulator MOSFETs are disabled (Hi-Z).
MCT8315A goes into reset state whenever buck OCP event occurs, since the internal circuitry in MCT8315A is
powered from the buck regulator output.
7.3.21.8 Cycle-by-Cycle (CBC) Current Limit (CBC_ILIMIT)
Cycle-by-cycle (CBC) current limit provides a means of controlling the amount of current delivered to the
motor. This is useful when the system must limit the amount of current pulled from the power supply during
motor operation. The CBC current limit limits the current applied to the motor from exceeding the configured
threshold. CBC current limit functionality is achieved by connecting the output of current sense amplifier VSOX to
a hardware comparator. If the voltage at output of current sense amplifier exceeds the CBC_ILIMIT threshold,
a CBC_ILIMIT event is recognized and action is taken according to CBC_ILIMIT_MODE. Total delay in reaction
to this event is dependent on the current sense amplifier gain and the comparator delay. CBC current limit in
closed loop is set through CBC_ILIMIT while configuration of OL_ILIMIT_CONFIG sets the CBC current limit in
open loop operation. Different modes can be configured through CBC_ILIMIT_MODE: CBC_ILIMIT automatic
recovery next PWM cycle, CBC_ILIMIT automatic recovery threshold based, CBC_ILIMIT automatic recovery
number of PWM cycles based, CBC_ILIMIT report only, CBC_ILIMIT disabled.
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7.3.21.8.1 CBC_ILIMIT Automatic Recovery next PWM Cycle (CBC_ILIMIT_MODE = 000xb)
When a CBC_ILIMIT event happens in this mode, MCT8315A stops driving the FETs using recirculation mode
to prevent the inductive energy from entering the DC input supply. The CBC_ILIMIT bit is set to 1b in the fault
status registers. Normal operation resumes at the start of next PWM cycle and CBC_ILIMIT bit is reset to 0b.
The status of CONTROLLER_FAULT bit and nFAULT pin will be determined by CBC_ILIMIT_MODE. When
CBC_ILIMIT_MODE is 0000b, CONTROLLER_FAULT bit is set to 1b and nFAULT pin driven low until next PWM
cycle. When CBC_ILIMIT_MODE is 0001b, CONTROLLER_FAULT bit is not set to 1b and nFAULT is not driven
low.
7.3.21.8.2 CBC_ILIMIT Automatic Recovery Threshold Based (CBC_ILIMIT_MODE = 001xb)
When a CBC_ILIMIT event happens in this mode, MCT8315A stops driving the FETs using recirculation mode
to prevent the inductive energy from entering the DC input supply. The CBC_ILIMIT bit is set to 1b in the status
registers. Normal operation resumes after VSOX falls below CBC_ILIMIT threshold and CBC_ILIMIT bit is set to
0b. The status of CONTROLLER_FAULT bit and nFAULT pin will be determined by CBC_ILIMIT_MODE. When
CBC_ILIMIT_MODE is 0010b, CONTROLLER_FAULT bit is set to 1b and nFAULT pin driven low until VSOX falls
below CBC_ILIMIT threshold. When CBC_ILIMIT_MODE is 0011b, CONTROLLER_FAULT bit is not set to 1b
and nFAULT is not driven low.
7.3.21.8.3 CBC_ILIMIT Automatic Recovery after 'n' PWM Cycles (CBC_ILIMIT_MODE = 010xb)
When a CBC_ILIMIT event happens in this mode, MCT8315A stops driving the FETs using recirculation
mode to prevent the inductive energy from entering the DC input supply. The CBC_ILIMIT bit is set to 1b
in the fault status registers. Normal operation resumes after (CBC_RETRY_PWM_CYC +1) PWM cycles and
CBC_ILIMIT bit is set to 0b. The status of CONTROLLER_FAULT bit and nFAULT pin will be determined by
CBC_ILIMIT_MODE. When CBC_ILIMIT_MODE is 0100b, CONTROLLER_FAULT bit is set to1b and nFAULT
pin driven low until (CBC_RETRY_PWM_CYC +1) PWM cycles lapse. When CBC_ILIMIT_MODE is 0101b,
CONTROLLER_FAULT bit is not set to 1b and nFAULT is not driven low.
7.3.21.8.4 CBC_ILIMIT Report Only (CBC_ILIMIT_MODE = 0110b)
No protective action is taken when a CBC_ILIMIT event happens in this mode. The CBC current limit event is
reported by setting the CONTROLLER_FAULT and CBC_ILIMIT bits to 1b in the fault status registers. The gate
drivers continue to operate. The external controller manages the overcurrent condition by acting appropriately.
The reporting clears when the CBC_ILIMIT condition clears and a clear fault command is issued through the
CLR_FLT bit.
7.3.21.8.5 CBC_ILIMIT Disabled (CBC_ILIMIT_MODE = 0111b or 1xxxb)
No action is taken when a CBC_ILIMIT event happens in this mode.
7.3.21.9 Lock Detection Current Limit (LOCK_ILIMIT)
The lock detection current limit function provides a configurable threshold for limiting the current to prevent
damage to the system. The MCT8315A continuously monitors the output of the current sense amplifier (CSA)
through the ADC. If at any time, the voltage on the output of CSA exceeds LOCK_ILIMIT for a time longer
than tLCK_ILIMIT, a LOCK_ILIMIT event is recognized and action is taken according to LOCK_ILIMIT_MODE. The
threshold is set through LOCK_ILIMIT, the tLCK_ILIMIT is set through LOCK_ILIMIT_DEG. LOCK_ILIMIT_MODE
can be set to four different modes: LOCK_ILIMIT latched shutdown, LOCK_ILIMIT automatic retry, LOCK_ILIMIT
report only and LOCK_ILIMIT disabled.
7.3.21.9.1 LOCK_ILIMIT Latched Shutdown (LOCK_ILIMIT_MODE = 00xxb)
When a LOCK_ILIMIT event happens in this mode, the status of MOSFETs will be configured by
LOCK_ILIMIT_MODE and nFAULT is driven low. Status of MOSFETs during LOCK_ILIMIT:
• LOCK_ILIMIT_MODE = 0000b: All MOSFETs are turned OFF.
• LOCK_ILIMIT_MODE = 0001b: MOSFET which was switching is turned OFF while the one which was
conducting stays ON till inductive energy is completely recirculated.
• LOCK_ILIMIT_MODE = 0010b: All high-side MOSFETs are turned ON.
• LOCK_ILIMIT_MODE = 0011b: All low-side MOSFETs are turned ON.
66
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The CONTROLLER_FAULT and LOCK_ILIMIT bits are set to 1b in the fault status registers. Normal operation
resumes (gate driver operation and the nFAULT pin is released) when the LOCK_ILIMIT condition clears and a
clear fault command is issued through the CLR_FLT bit.
7.3.21.9.2 LOCK_ILIMIT Automatic Recovery (LOCK_ILIMIT_MODE = 01xxb)
When a LOCK_ILIMIT event happens in this mode, the status of MOSFETs will be configured by
LOCK_ILIMIT_MODE and nFAULT is driven low. Status of MOSFETs during LOCK_ILIMIT:
• LOCK_ILIMIT_MODE = 0100b: All MOSFETs are turned OFF.
• LOCK_ILIMIT_MODE = 0101b: MOSFET which was switching is turned OFF while the one which was
conducting stays ON till inductive energy is completely recirculated.
• LOCK_ILIMIT_MODE = 0110b: All high-side MOSFETs are turned ON
• LOCK_ILIMIT_MODE = 0111b: All low-side MOSFETs are turned ON
The CONTROLLER_FAULT and LOCK_ILIMIT bits are set to 1b in the fault status registers. Normal operation
resumes automatically (gate driver operation and the nFAULT pin is released) after the tLCK_RETRY (configured
by LCK_RETRY) time lapses. The CONTROLLER_FAULT and LOCK_ILIMIT bits are reset to 0b after the
tLCK_RETRY period expires.
7.3.21.9.3 LOCK_ILIMIT Report Only (LOCK_ILIMIT_MODE = 1000b)
No protective action is taken when a LOCK_ILIMIT event happens in this mode. The lock detection current limit
event is reported by setting the CONTROLLER_FAULT and LOCK_ILIMIT bits to 1b in the fault status registers.
The gate drivers continue to operate. The external controller manages this condition by acting appropriately.
The reporting clears when the LOCK_ILIMIT condition clears and a clear fault command is issued through the
CLR_FLT bit.
7.3.21.9.4 LOCK_ILIMIT Disabled (LOCK_ILIMIT_MODE = 1xx1b)
No action is taken when a LOCK_ILIMIT event happens in this mode.
7.3.21.10 Thermal Warning (OTW)
If the die temperature exceeds the thermal warning limit (TOTW), nFAULT is pulled low and the OT and OTW bits
in the gate driver status register are set to 1b. The reporting of OTW (on nFAULT and status bits) can be enabled
by setting OTW_REP to 1b. The device performs no additional action and continues to function. In this case, the
nFAULT pin is released when the die temperature decreases below the hysteresis point of the thermal warning
limit (TOTW - TOTW_HYS). The OTW bit remains set until cleared through the CLR_FLT bit and the die temperature
is lower than thermal warning limit. (TOTW - TOTW_HYS).
7.3.21.11 Thermal Shutdown (TSD)
If the die temperature exceeds the thermal shutdown limit (TTSD), all the FETs are disabled, the charge pump
is shut down, and the nFAULT pin is driven low. In addition, the DRIVER_FAULT, OT and TSD bit in the status
register are set to 1b. Normal operation resumes (driver operation and the nFAULT pin is released) when the
die temperature decreases below the hysteresis point of the thermal shutdown limit (TTSD - TTSD_HYS). The TSD
bit stays latched high indicating that a thermal event occurred until a clear fault command is issued through the
CLR_FLT bit. This protection feature cannot be disabled.
7.3.21.12 Motor Lock (MTR_LCK)
The MCT8315A continuously checks for different motor lock conditions (see Motor Lock Detection) during motor
operation. When one of the enabled lock condition happens, a MTR_LCK event is recognized and action is
taken according to the MTR_LCK_MODE.
In MCT8315A, all locks can be enabled or disabled individually and retry times can be configured through
LCK_RETRY. MTR_LCK_MODE bit can operate in four different modes: MTR_LCK latched shutdown,
MTR_LCK automatic retry, MTR_LCK report only and MTR_LCK disabled.
7.3.21.12.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
When a MTR_LCK event happens in this mode, the status of MOSFETs will be configured by MTR_LCK_MODE
and nFAULT is driven low. Status of MOSFETs during MTR_LCK:
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•
•
•
•
MTR_LCK_MODE = 0000b: All MOSFETs are turned OFF.
MTR_LCK_MODE = 0001b: MOSFET which was switching is turned OFF while the one which was
conducting stays ON till inductive energy is completely recirculated.
MTR_LCK_MODE = 0010b: All high-side MOSFETs are turned ON.
MTR_LCK_MODE = 0011b: All low-side MOSFETs are turned ON.
The CONTROLLER_FAULT, MTR_LCK and respective motor lock condition bits are set to 1b in the fault status
registers. Normal operation resumes (gate driver operation and the nFAULT pin is released) when the MTR_LCK
condition clears and a clear fault command is issued through the CLR_FLT bit.
7.3.21.12.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
When a MTR_LCK event happens in this mode, the status of MOSFETs will be configured by MTR_LCK_MODE
and nFAULT is driven low. Status of MOSFETs during MTR_LCK:
• MTR_LCK_MODE = 0100b: All MOSFETs are turned OFF.
• MTR_LCK_MODE = 0101b: MOSFET which was switching is turned OFF while the one which was
conducting stays ON till inductive energy is completely recirculated.
• MTR_LCK_MODE = 0110b: All high-side MOSFETs are turned ON.
• MTR_LCK_MODE = 0111b: All low-side MOSFETs are turned ON.
The CONTROLLER_FAULT, MTR_LCK and respective motor lock condition bits are set to 1b in the fault status
registers. Normal operation resumes automatically (gate driver operation and the nFAULT pin is released) after
the tLCK_RETRY (configured by LCK_RETRY) time lapses. The CONTROLLER_FAULT, MTR_LCK and respective
motor lock condition bits are reset to 0b after the tLCK_RETRY period expires.
7.3.21.12.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
No protective action is taken when a MTR_LCK event happens in this mode. The motor lock event is reported
by setting the CONTROLLER_FAULT, MTR_LCK and respective motor lock condition bits to 1b in the fault
status registers. The gate drivers continue to operate. The external controller manages this condition by acting
appropriately. The reporting clears when the MTR_LCK condition clears and a clear fault command is issued
through the CLR_FLT bit.
7.3.21.12.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
No action is taken when a MTR_LCK event happens in this mode.
7.3.21.13 Motor Lock Detection
The MCT8315A provides different lock detect mechanisms to determine if the motor is in a locked state. Multiple
detection mechanisms work together to ensure the lock condition is detected quickly and reliably. In addition to
detecting if there is a locked motor condition, the MCT8315A can also identify and take action if there is no motor
connected to the system. Each of the lock detect mechanisms and the no-motor detection can be disabled by
their respective register bits (LOCK1/2/3_EN).
7.3.21.13.1 Lock 1: Abnormal Speed (ABN_SPEED)
MCT8315A monitors the speed continuously and at any time the speed exceeds LOCK_ABN_SPEED, an
ABN_SPEED lock event is recognized and action is taken according to the MTR_LCK_MODE. In MCT8315A,
the threshold is set through the LOCK_ABN_SPEED register. ABN_SPEED lock can be enabled/disabled by
LOCK1_EN.
7.3.21.13.2 Lock 2: Loss of Sync (LOSS_OF_SYNC)
The motor is commutated by detecting the zero crossing on the phase which is in Hi-Z state. If the motor is
locked, the back-EMF will disappear and MCT8315A will be not able to detect the zero crossing. If MCT8315A
is not able to detect zero crossing for LOSS_SYNC_TIMES number of times, LOSS_OF_SYNC event is
recognized and action is taken according to the MTR_LCK_MODE. LOSS_OF_SYNC lock can be enabled/
disabled by LOCK2_EN.
68
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7.3.21.13.3 Lock3: No-Motor Fault (NO_MTR)
The MCT8315A continuously monitors the relevant phase current (low-side phase in the present phase pattern);
if the relevant phase current stays below NO_MTR_THR for a time longer than NO_MTR_DEG_TIME, a
NO_MTR event is recognized. The response to the NO_MTR event is configured through MTR_LCK_MODE .
NO_MTR lock can be enabled/disabled by LOCK3_EN.
7.3.21.14 SW VM Undervoltage Protection
MCT8315A provides the option of a software based VM undervoltage protection. The VM level at which the
software triggers the undervoltage fault is set by MIN_VM_MOTOR and the fault response to VM undervoltage is
set by MIN_VM_MODE. If MIN_VM_MODE is set to 0b, VM undervoltage fault (at MIN_VM_MOTOR) is latched
and the FETs are in Hi-Z until the fault condition is cleared by writing 1b to CLR_FIT bit. If MIN_VM_MODE is set
to 1b, VM undervoltage fault (at MIN_VM_MOTOR) automatically clears and the device starts motor operation
once VM > MIN_VM_MODE.
7.3.21.15 SW VM Overvoltage Protection
MCT8315A provides the option of a software based VM overvoltage protection. The VM level at which the
software triggers the overvoltage fault is set by MAX_VM_MOTOR and the fault response to VM overvoltage is
set by MAX_VM_MODE. If MAX_VM_MODE is set to 0b, VM overvoltage fault (at MAX_VM_MOTOR) is latched
and the FETs are in Hi-Z until the fault condition is cleared by writing 1b to CLR_FIT bit. If MAX_VM_MODE
is set to 1b, VM overvoltage fault (at MAX_VM_MOTOR) automatically clears and the device starts motor
operation once VM < MAX_VM_MODE.
7.3.21.16 IPD Faults
The MCT8315A uses 12-bit timers to estimate the time during the current ramp up and ramp down during IPD,
when the motor start-up is configured as IPD (MTR_STARTUP is set to 10b). During IPD, the algorithm checks
for a successful current ramp-up to IPD_CURR_THR, starting with an IPD clock of 10MHz; if unsuccessful
(timer overflow before current reaches IPD_CURR_THR), IPD is repeated with lower frequency clocks of 1MHz,
100kHz, and 10kHz sequentially. If the IPD timer overflows (current does not reach IPD_CURR_THR) with
all the four clock frequencies, then the IPD_T1_FAULT gets triggered. Similarly the algorithm checks for a
successful current decay to zero during IPD current ramp down using all the mentioned IPD clock frequencies. If
the IPD timer overflows (current does not ramp down to zero) in all the four attempts, then the IPD_T2_FAULT
gets triggered.
IPD gives incorrect results if the next IPD pulse is commanded before the complete decay of current due to
present IPD pulse. The MCT8315A can generate a fault called IPD_FREQ_FAULT during such a scenario . The
IPD_FREQ_FAULT maybe triggered if the IPD frequency is too high for the IPD current limit and the IPD release
mode or if the motor inductance is too high for the IPD frequency, IPD current limit and IPD release mode.
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7.4 Device Functional Modes
7.4.1 Functional Modes
7.4.1.1 Sleep Mode
In sleep mode, the MOSFETs, sense amplifiers, buck regulator, charge pump, AVDD LDO regulator and the
I2C bus are disabled. The device can be configured to enter sleep (instead of standby) mode by configuring
DEV_MODE to 1b. SPEED pin and I2C speed command determine entry and exit from sleep state as described
in Table 7-3.
7.4.1.2 Standby Mode
The device can be configured to operate as a standby device by setting DEV_MODE to 0b. In standby mode, the
charge pump, AVDD LDO, buck regulator and I2C bus are active while the motor is in stopped state waiting for
a suitable non-zero speed command. SPEED pin (analog, PWM or frequency based speed input) or I2C speed
command (I2C based speed input) determines entry and exit from standby state as described in Table 7-3.
The thresholds for entering and exiting standby mode in different speed input modes are as follows,
1. Analog : VEN_SB = (ZERO_DUTY_THR x VANA_FS), VEX_SB = ((ZERO_DUTY_THR + ZERO_DUTY_HYST) x
VANA_FS)
2. PWM : DutyEN_SB = ZERO_DUTY_THR, DutyEX_SB = (ZERO_DUTY_THR + ZERO_DUTY_HYST)
3. I2C : SPEED_CTRLEN_SB = ZERO_DUTY_THR x 32767, SPEED_CTRLEX_SB = (ZERO_DUTY_THR +
ZERO_DUTY_HYST) x 32767
4. Frequency : FreqEN_SB = ZERO_DUTY_THR x INPUT_MAX_FREQUENCY, FreqEX_SB =
(ZERO_DUTY_THR + ZERO_DUTY_HYST) x INPUT_MAX_FREQUENCY
Table 7-3. Conditions to Enter or Exit Sleep or Standby Modes
SPEED
COMMAND
MODE
ENTER STANDBY
CONDITION
EXIT FROM STANDBY
CONDITION
ENTER SLEEP CONDITION
EXIT FROM SLEEP
CONDITION
Analog
VSPEED < VEN_SB
VSPEED > VEX_SB
VSPEED < VEN_SL for
tDET_SL_ANA
PWM
DutySPEED < DutyEN_SB
DutySPEED > DutyEX_SB
VSPEED < VIL for tDET_SL_PWM VSPEED > VIH for tDET_PWM
I2C
SPEED_CTRL <
SPEED_CTRLEN_SB
SPEED_CTRL >
SPEED_CTRLEX_SB
SPEED_CTRL is set to
0b for SLEEP_TIME and
VSPEED < VIL
Frequency
FreqSPEED < FreqEN_SB
FreqSPEED > FreqEX_SB
VSPEED < VIL for tDET_SL_PWM VSPEED > VIH for tDET_PWM
VSPEED > VEX_SL for tDET_ANA
VSPEED > VIH for tDET_PWM
Note
VSPEED : SPEED pin input voltage, DutySPEED : SPEED pin input PWM duty, FreqSPEED : SPEED pin
input frequency
7.4.1.3 Fault Reset (CLR_FLT)
In the case of latched faults, the device goes into a partial shutdown state to help protect the power MOSFETs
and system. When the fault condition clears, the device can go to the operating state again by setting the
CLR_FLT to 1b.
7.5 External Interface
7.5.1 DRVOFF Functionality
When DRVOFF pin is driven high, all six MOSFETs are put in Hi-Z state, irrespective of speed command. If
motor speed command is non-zero when DRVOFF is driven high, device may encounter a fault like no motor or
abnormal BEMF.
7.5.2 DAC outputs
MCT8315A has two 12-bit DACs which output analog voltage equivalent of digital variables on the DACOUT1
and DACOUT2 pins. The maximum DAC output voltage is 3-V. Signals available on DACOUT pins are
70
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useful in tracking internal variables in real-time and can be used for tuning speed controller or motor
acceleration time. The address for variables to be tracked on DACOUT1 and DACOUT2 are configured
using DACOUT1_VAR_ADDR and DACOUT2_VAR_ADDR respectively. DACOUT1 is available on pin 38 and
DACOUT2 can be configured on pin 36 by setting DAC_SOX_CONFIG to 00b. DACOUT2 is also available on
pin 37. DAC_CONFIG should be configured to 1b for pins 37, 38 to function as DAC outputs.
7.5.3 Current Sense Output
MCT8315A can provide the built-in current sense amplifiers' output on the SOX pin. SOX output is available on
pin 36 and can be configured by DAC_SOX_CONFIG.
7.5.4 Oscillator Source
MCT8315A has a built-in oscillator that is used as the clock source for all digital peripherals and timing
measurements. Default configuration for MCT8315A is to use the internal oscillator and it is sufficient to drive the
motor without need for any external crystal or clock sources.
In case MCT8315A does not meet accuracy requirements of timing measurement or speed loop, then
MCT8315A has an option to support an external clock reference.
In order to improve EMI performance, MCT8315A provides the option of modulating the clock frequency by
enabling Spread Spectrum Modulation (SSM) through SSM_CONFIG.
7.5.4.1 External Clock Source
Speed loop accuracy of MCT8315A over the operating temperature range can be improved by providing a more
accurate clock reference on EXT_CLK pin as shown in Figure 7-53. EXT_CLK will be used to calibrate the
internal clock oscillator - this will help match the accuracy of the internal clock oscillator to that of the external
clock. External clock source can be selected by configuring CLK_SEL to 11b and setting EXT_CLK_EN to 1b.
The external clock source frequency can be configured through EXT_CLK_CONFIG.
EXT_CLK
Calibrate
Internal
Oscillator
(60 MHz)
Figure 7-53. External Clock Reference
Note
External clock is optional and can be used when higher clock accuracy is needed. MCT8315A will
always power up using the internal oscillator in all modes.
7.5.5 External Watchdog
MCT8315A provides an external watchdog feature - EXT_WD_EN bit should be set to 1b to enable the external
watchdog. When this feature is enabled, the device waits for a tickle (low to high transition in EXT_WD pin,
EXT_WD_STATUS_SET set to 1b in I2C mode) from the external watchdog input for a configured time interval;
if the time interval between two consecutive tickles is higher than the configured time, a watchdog fault is
triggered. This fault can be configured using EXT_WD_FAULT either as a report only fault or as a latched fault
with outputs in Hi-Z state. The latched fault can be cleared by writing 1b to CLR_FLT. When a watchdog timeout
occurs, EXT_WD_TIMEOUT bit is set to 1b. In case, the next tickle arrives before the configured time interval
elapses, the watchdog timer is reset and it begins to wait for the next tickle. This can be used to continuously
monitor the health of an external MCU (which is the external watchdog input) and put the MCT8315A outputs in
Hi-Z in case the external MCU is in an erroneous state.
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The external watchdog input is selected using EXT_WD_INPUT and can either be the EXT_WD pin or the I2C
interface. The time interval between two tickles to trigger a watchdog fault is configured by EXT_WD_FREQ;
there are 4 time (frequency) settings - 100ms (10Hz), 200ms (5Hz), 500ms (2Hz) and 1000ms (1Hz).
Note
Watchdog should be disabled by setting EXT_WD_EN to 0b before changing EXT_WD_FREQ
configuration.
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7.6 EEPROM access and I2C interface
7.6.1 EEPROM Access
MCT8315A has 1024 bits (16 rows of 64 bits each) of EEPROM, which are used to store the motor configuration
parameters. Erase operations are row-wise (all 64 bits are erased in a single erase operation), but 32-bit write
and read operations are supported. EEPROM can be written and read using the I2C serial interface but erase
cannot be performed using I2C serial interface. The shadow registers corresponding to the EEPROM are located
at addresses 0x000080-0x0000AE.
Note
MCT8315A allows EEPROM write and read operations only when the motor is not spinning.
7.6.1.1 EEPROM Write
In MCT8315A, EEPROM write procedure is as follows,
1. Write register 0x000080 (ISD_CONFIG) with ISD configuration like resync enable, reverse drive enable,
stationary detect threshold etc.,
2. Write register 0x000082 (MOTOR_STARTUP1) with motor start-up configuration like start-up method, first
cycle frequency, IPD parameters, align parameters etc.,
3. Write register 0x000084 (MOTOR_STARTUP2) with motor start-up configuration like open loop acceleration,
minimum duty cycle etc.,
4. Write register 0x000086 (CLOSED_LOOP1) with motor control configuration like closed loop acceleration,
PWM frequency, PWM modulation etc.,
5. Write register 0x000088 (CLOSED_LOOP2) with motor control configuration like FG signal parameters,
motor stop options etc.,
6. Write register 0x00008A (CLOSED_LOOP3) with motor control configuration like fast start-up and dynamic
degauss parameters including BEMF thresholds, duty cycle thresholds etc.,
7. Write register 0x00008C (CLOSED_LOOP4) with motor control configuration like fast deceleration
parameters including fast deceleration duty threshold, window, current limits etc.,
8. Write register 0x00008E (CONST_SPEED) with motor control configuration like speed loop parameters
including closed loop mode, saturation limits, Kp, Ki etc.,
9. Write register 0x000090 (CONST_PWR) with motor control configuration like input power regulation
parameters including maximum power, constant power mode, power level hysteresis, maximum speed etc.,
10. Write register 0x000092 (FAULT_CONFIG1) with fault control configuration like CBC, lock current limits and
actions, retry times etc.,
11. Write register 0x000094 (FAULT_CONFIG2) with fault control configuration like OV, UV limits and actions,
abnormal speed level, motor lock setting etc.,
12. Write registers 0x000096 and 0x000098 (150_DEG_TWO_PH_PROFILE,
150_DEG_THREE_PH_PROFILE) with PWM duty cycle configurations for 150o modulation.
13. Write registers 0x00009A and 0x00009C (TRAP_CONFIG1 and TRAP_CONFIG2) with algorithm
parameters like ISD BEMF threshold, blanking time, AVS current limits etc.,
14. Write registers 0x0000A4 and 0x0000A6 (PIN_CONFIG1 and PIN_CONFIG2) with pin configuration for DIR,
BRAKE, DACOUT1 and DACOUT2, SOX, external watchdog etc.,
15. Write register 0x0000A8 (DEVICE_CONFIG) with device configuration like device mode, external clock
enable, clock source, speed input PWM frequency range etc.,
16. Write registers 0x0000AC and 0x0000AE (GD_CONFIG1 and GD_CONFIG2) with gate driver configuration
like slew rate, CSA gain, OCP level, mode, OVP enable etc.,
17. Write 0x8A500000 into register 0x0000E6 to write the shadow register (0x000080-0x0000AE) values into the
EEPROM.
18. Wait for 300ms for the EEPROM write operation to complete.
Steps 1-16 can be selectively executed based on registers/parameters that need to be modified. After all shadow
registers have been updated with the required values, step 17 should be executed to copy the contents of the
shadow registers into the EEPROM.
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7.6.1.2 EEPROM Read
In MCT8315A, EEPROM read procedure is as follows,
1. Write 0x40000000 into register 0x0000E6 to read the EEPROM data into the shadow registers
(0x000080-0x0000AE).
2. Wait for 100ms for the EEPROM read operation to complete.
3. Read the shadow register values, 1 or 2 registers at a time, using the I2C read command as explained
in Section 7.6.2. Shadow register addresses are in the range of 0x000080-0x0000AE. Register address
increases in steps of 2 for 32-bit read operation (since each address is a 16-bit location).
7.6.2 I2C Serial Interface
MCT8315A interfaces with an external MCU over an I2C serial interface. MCT8315A is an I2C target to be
interfaced with a controller. External MCU can use this interface to read/write from/to any non-reserved register
in MCT8315A
Note
For reliable communication, a 100-µs delay should be used between every byte transferred over the
I2C bus.
7.6.2.1 I2C Data Word
The I2C data word format is shown in Table 7-4.
Table 7-4. I2C Data Word Format
TARGET_ID
R/W
CONTROL WORD
DATA
CRC-8
A6 - A0
W0
CW23 - CW0
D15 / D31/ D63 - D0
C7 - C0
Target ID and R/W Bit: The first byte includes the 7-bit I2C target ID (default 0x00, but can be modified
by setting I2C_TARGET_ADDR), followed by the read/write command bit. Every packet in MCT8315A the
communication protocol starts with writing a 24-bit control word and hence the R/W bit is always 0.
24-bit Control Word: The Target Address is followed by a 24-bit control bit. The control word format is shown in
Table 7-5.
Table 7-5. 24-bit Control Word Format
OP_R/W
CRC_EN
DLEN
MEM_SEC
CW23
CW22
CW21- CW20
CW19 - CW16
MEM_PAGE
CW15 - CW12
MEM_ADDR
CW11 - CW0
Each field in the control word is explained in detail below.
OP_R/W – Read/Write: R/W bit gives information on whether this is a read (1b) operation or write (0b)
operation. For write operation, MCT8315A will expect data bytes to be sent after the 24-bit control word. For
read operation, MCT8315A will expect an I2C read request with repeated start or normal start after the 24-bit
control word.
CRC_EN – Cyclic Redundancy Check(CRC) Enable: MCT8315A supports CRC to verify the data integrity.
This bit controls whether the CRC feature is enabled or not.
DLEN – Data Length: DLEN field determines the length of the data that will be sent by external MCU to
MCT8315A. MCT8315A protocol supports three data lengths: 16-bit, 32-bit and 64-bit.
Table 7-6. Data Length Configuration
74
DLEN Value
Data Length
00b
16-bit
01b
32-bit
10b
64-bit
11b
Reserved
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MEM_SEC – Memory Section: Each memory location in MCT8315A is addressed using three separate entities
in the control word – Memory Section, Memory Page, Memory Address. Memory Section is a 4-bit field which
denotes the memory section to which the memory location belongs like RAM, ROM etc.
MEM_PAGE – Memory Page: Memory page is a 4-bit field which denotes the memory page to which the
memory location belongs.
MEM_ADDR – Memory Address: Memory address is the last 12-bits of the address. The complete 22-bit
address is constructed internally by MCT8315A using all three fields – Memory Section, Memory Page, Memory
Address. For memory locations 0x000000-0x000800, memory section is 0x0, memory page is 0x0 and memory
address is the lowest 12 bits(0x000 for 0x000000, 0x080 for 0x000080 and 0x800 for 0x000800). All relevant
memory locations (EEPROM and RAM variables) have MEM_SEC and MEM_PAGE values both corresponding
to 0x0. All other MEM_SEC, MEM_PAGE values are reserved and not for external use.
Data Bytes: For a write operation to MCT8315A, the 24-bit control word is followed by data bytes. The DLEN
field in the control word should correspond with the number of bytes sent in this section. In case of mismatch
between number of data bytes and DLEN, the write operation is discarded.
CRC Byte: If the CRC feature is enabled in the control word, CRC byte has to be sent at the end of a write
transaction. Refer to Section 7.6.2.6 for detailed information on CRC byte calculation.
7.6.2.2 I2C Write Transaction
MCT8315A write transaction over I2C involves the following sequence (see Figure 7-54).
1. I2C start condition.
2. Start is followed by the I2C target ID byte, made up of 7-bit target ID along with the R/W bit set to 0b. ACK
in yellow box indicates that MCT8315A has processed the received target ID which has matched with it's I2C
target ID and therefore will proceed with this transaction. If target ID received does not match with the I2C ID
of MCT8315A, then the transaction is ignored. and no ACK is sent by MCT8315A.
3. The target ID byte is followed by the 24-bit control word sent one byte at a time. Bit 23 in the control word
is 0b as it is a write transaction. ACK in blue boxes correspond to acknowledgements sent by MCT8315A to
the controller that the previous byte (of control word) has been received and next byte can be sent.
4. The 24-bit control word is then followed by the data bytes. The number of data bytes sent by the controller
depends on the DLEN field in the control word.
a. While sending data bytes, the LSB byte is sent first. Refer to Section 7.6.2.4 for more details.
b. 16-bit/32-bit write – The data sent is written to the address mentioned in control word.
c. 64-bit Write – 64-bit is treated as two successive 32-bit writes. The address mentioned in control word is
taken as Addr_1. Addr_2 is internally calculated by MCT8315A by incrementing Addr_1 by 0x2. A total
of 8 data bytes are sent. The first 4 bytes (sent in LSB first) are written to Addr_1 and the next 4 bytes
are written to Addr_2.
d. ACK in blue boxes (after every data byte) correspond to the acknowledgement sent by MCT8315A to the
controller that the previous data byte has been received and next data byte can be sent.
5. If CRC is enabled, the packet ends with a CRC byte. CRC is calculated for the entire packet (Target ID + W
bit, Control Word, Data Bytes). MCT8315A will send an ACK on receiving the CRC byte.
6. I2C Stop condition from the controller to terminate the transaction.
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2 / 4 / 8 DATA BYTES
Write – without CRC
S
TARGET
ID [6:0]
0
ACK
CONTROL
ACK
WORD [23:16]
CONTROL
WORD [15:8]
ACK
CONTROL
WORD [7:0]
ACK
DATA
BYTE
TARGET
ID [6:0]
0
DATA
BYTE
ACK
P
2 / 4 / 8 DATA BYTES
Write – with CRC
S
ACK
ACK
CONTROL
ACK
WORD [23:16]
CONTROL
WORD [15:8]
ACK
CONTROL
WORD [7:0]
ACK
DATA
BYTE
ACK
DATA
BYTE
ACK
CRC
ACK
P
CRC includes {TARGET ID,0}, CONTROL WORD[23:0], DATA BYTES
Figure 7-54. I2C Write Transaction Sequence
7.6.2.3 I2C Read Transaction
MCT8315A read transaction over I2C involves the following sequence (see Figure 7-55).
1. I2C Start condition from the controller to initiate the transaction.
2. Start is followed by the I2C target ID byte, made up of 7-bit target ID along with the R/W bit set to 0b. ACK (in
yellow box) indicates that MCT8315A has processed the received target ID which has matched with it's I2C
target ID and therefore will proceed with this transaction. If target ID received does not match with the I2C ID
of MCT8315A, then the transaction is ignored and no ACK is sent by MCT8315A.
3. The target ID byte is followed by the 24-bit control word sent one byte at a time. Bit 23 in the control
word is set to 1b as it is a read transaction. ACK (in blue boxes) correspond to acknowledgements sent by
MCT8315A to the controller that the previous byte (of control word) has been received and next byte can be
sent.
4. The control word is followed by a Repeated Start (RS, start without a preceding stop) or normal Start (P
followed by S) to initiate the data (to be read back) transfer from MCT8315A to I2C controller. RS or S is
followed by the 7-bit target ID along with R/W bit set to 1b to initiate the read transaction. MCT8315A sends
an ACK (in grey box after RS) to the controller to acknowledge the receipt of read transaction request.
5. Post acknowledgement of read transaction request, MCT8315A sends the data bytes on SDA one byte at a
time. The number of data bytes sent by MCT8315A depends on the DLEN field in the control word.
a. While sending data bytes, the LSB byte is sent first. Refer the examples in Section 7.6.2.4 for more
details.
b. 16-bit/32-bit Read – The data from the address mentioned in control word is sent back to the controller.
c. 64-bit Read – 64-bit is treated as two successive 32-bit reads. The address mentioned in control word is
taken as Addr_1. Addr_2 is internally calculated by MCT8315A by incrementing Addr_1 by 0x2. A total
of 8 data bytes are sent by MCT8315A. The first 4 bytes (sent in LSB first) are read from Addr_1 and the
next 4 bytes are read from Addr_2.
d. ACK in orange boxes correspond to acknowledgements sent by the controller to MCT8315A that the
previous byte has been received and next byte can be sent.
6. If CRC is enabled in the control word, then MCT8315A sends an additional CRC byte at the end. Controller
has to read the CRC byte and then send the last ACK (in orange). CRC is calculated for the entire packet
(Target ID + W bit, Control Word, Target ID + R bit, Data Bytes).
7. I2C Stop condition from the controller to terminate the transaction.
76
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Read – without CRC
S
TARGET
ID [6:0]
0
2 / 4 / 8 DATA BYTES
CONTROL
ACK
WORD [23:16]
ACK
CONTROL
WORD [15:8]
ACK
CONTROL
WORD [7:0]
ACK
RS
TARGET
ID [6:0]
1
ACK
DATA
BYTE
Read – with CRC
S
TARGET
ID [6:0]
0
DATA
BYTE
ACK
ACK
P
2 / 4 / 8 DATA BYTES
CONTROL
ACK
WORD [23:16]
ACK
CONTROL
WORD [15:8]
ACK
CONTROL
WORD [7:0]
ACK
RS
TARGET
ID [6:0]
1
ACK
DATA
BYTE
DATA
BYTE
ACK
ACK
CRC
ACK
P
CRC includes {TARGET ID,0}, CONTROL WORD[23:0], {TARGET ID,1}, DATA BYTES
Figure 7-55. I2C Read Transaction Sequence
7.6.2.4 I2C Communication Protocol Packet Examples
All values used in this example section are in hex format. I2C target ID used in the examples is 0x60.
Example for 32-bit Write Operation: Address – 0x00000080, Data – 0x1234ABCD, CRC Byte – 0x45 (Sample
value; does not match with the actual CRC calculation)
Table 7-7. Example for 32-bit Write Operation Packet
Start Byte
Control Word 0
Control Word 1
Control
Word 2
Data Bytes
CRC
Target
ID
I2C
Write
OP_R/
W
CRC_E
N
DLEN
MEM_S MEM_P MEM_A MEM_A DB0
EC
AGE
DDR
DDR
DB1
DB2
DB3
CRC
Byte
A6-A0
W0
CW23
CW22
CW21CW20
CW19CW16
CW15CW12
CW11CW8
CW7CW0
D7-D0
D7-D0
D7-D0
D7-D0
C7-C0
0x60
0x0
0x0
0x1
0x1
0x0
0x0
0x0
0x80
0xCD
0xAB
0x34
0x12
0x45
0x80
0xCD
0xAB
0x34
0x12
0x45
0xC0
0x50
0x00
Example for 64-bit Write Operation: Address - 0x00000080, Data Address 0x00000080 - Data 0x01234567,
Data Address 0x00000082 – Data 0x89ABCDEF, CRC Byte – 0x45 (Sample value; does not match with the
actual CRC calculation)
Table 7-8. Example for 64-bit Write Operation Packet
Start Byte
Control Word 0
Control Word 1
Control Word Data Bytes
2
CRC
MEM_SEC MEM_PAGE MEM_ADDR
MEM_ADDR DB0 - DB7
CRC
Byte
Target
ID
I2C
Write
OP_R/W CRC_EN DLEN
A6-A0
W0
CW23
CW22
CW21- CW19CW20 CW16
CW15CW12
CW11-CW8
CW7-CW0
[D7-D0] x 8
C7-C0
0x60
0x0
0x0
0x1
0x2
0x0
0x0
0x80
0x67452301EFCDAB89
0x45
0x80
0x67452301EFCDAB89
0x45
0xC0
0x0
0x60
0x00
Example for 32-bit Read Operation: Address – 0x00000080, Data – 0x1234ABCD, CRC Byte – 0x56 (Sample
value; does not match with the actual CRC calculation)
Table 7-9. Example for 32-bit Read Operation Packet
Start Byte
Control Word 0
Target
ID
I2C
Write
R/W
CRC_
EN
DLEN
A6-A0
W0
CW23
CW22
0x60
0x0
0x1
0x1
0xC0
Control Word 1
Control Start Byte
Word 2
MEM_
PAGE
MEM_
ADDR
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Target
ID
I2C
Read
DB0
DB1
DB2
DB3
CRC
Byte
CW21- CW19- CW15- CW11- CW7CW20 CW16 CW12 CW8
CW0
A6-A0
W0
D7-D0
D7-D0
D7-D0
D7-D0
C7-C0
0x1
0x80
0x60
0x1
0xCD
0xAB
0x34
0x12
0x56
0x80
0xC1
0xCD
0xAB
0x34
0x12
0x56
0xD0
MEM_
SEC
0x0
0x0
0x00
MEM_
ADDR
0x0
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7.6.2.5 I2C Clock Stretching
The I2C peripheral in MCT8315A implements clock stretching under certain conditions when there are pending
I2C interrupts waiting to be processed. During clock stretching, MCT8315A pulls SCL low and the I2C bus is
unavailable for use by other devices. The following is a list of conditions under which clock stretching can occur:
1. Start interrupt pending: There are two scenarios when a start interrupt can result in clock stretching,
a. When target ID is a match, I2C peripheral in MCT8315A raises a start interrupt request. Until this start
interrupt request is processed, clock is stretched. Upon processing this request, clock is released and an
ACK (marked in yellow or grey in Figure 7-54 and Figure 7-55) is sent to the controller for continuing with
the transaction.
b. If Start (followed by target ID match) for a new transaction is received when a receive interrupt from
previous transaction is yet to be processed, clock is stretched until both the receive interrupt and
start interrupt are processed in chronological order. This process ensures that previous transaction is
executed correctly before initiating the next transaction.
2. Receive interrupt pending: When a receive interrupt is waiting to be processed and the receive register is
full which occurs when two successive bytes (data or control) have been received by MCT8315A (separated
by one ACK shown as blue boxes in Figure 7-54 and Figure 7-55) without the receive interrupt generated
by the first byte being processed. Upon receive of second byte, clock is stretched until receive interrupt
generated by the first byte is processed.
3. Transmit buffer is empty: In case of a transmit interrupt pending (to send data back to controller), if the
transmit buffer is waiting to be populated with data to be read back to the controller, clock stretching is done
until the transmit buffer is populated with requested data. After the buffer is populated, clock is released and
data is sent to controller.
Note
I2C clock stretching is timed out after 5 ms by MCT8315A to allow I2C bus access for other devices on
the same bus.
7.6.2.6 CRC Byte Calculation
An 8-bit CCIT polynomial (x8 + x2+ x + 1) and CRC initial value 0xFF is used for CRC computation.
CRC Calculation in Write Operation: When the external MCU writes to MCT8315A, if the CRC is enabled, the
external MCU has to compute an 8-bit CRC byte and add the CRC byte at the end of the data. MCT8315A will
compute CRC using the same polynomial internally and if there is a mismatch, the write request is discarded.
Input data for CRC calculation by external MCU for write operation are listed below:
1. Target ID + write bit.
2. Control word – 3 bytes
3. Data bytes – 2/4/8 bytes
CRC Calculation in Read Operation: When the external MCU reads from MCT8315A, if the CRC is enabled,
MCT8315A sends the CRC byte at the end of the data. The CRC computation in read operation involves the
start byte, control words sent by external MCU along with data bytes sent by MCT8315A. Input data for CRC
calculation by external MCU to verify the data sent by MCT8315A are listed below :
1. Target ID + write bit
2. Control word – 3 bytes
3. Target ID + read bit
4. Data bytes – 2/4/8 bytes
78
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7.7 EEPROM (Non-Volatile) Register Map
7.7.1 Algorithm_Configuration Registers
Table 7-10 lists the memory-mapped registers for the Algorithm_Configuration registers. All register offset
addresses not listed in Table 7-10 should be considered as reserved locations and the register contents should
not be modified.
Table 7-10. ALGORITHM_CONFIGURATION Registers
Offset
Acronym
Register Name
80h
ISD_CONFIG
ISD configuration
ISD_CONFIG Register (Offset = 80h) [Reset
= 00000000h]
Section
82h
MOTOR_STARTUP1
Motor start-up configuration 1
MOTOR_STARTUP1 Register (Offset = 82h)
[Reset = 00000000h]
84h
MOTOR_STARTUP2
Motor start-up configuration 2
MOTOR_STARTUP2 Register (Offset = 84h)
[Reset = X]
86h
CLOSED_LOOP1
Closed loop configuration 1
CLOSED_LOOP1 Register (Offset = 86h)
[Reset = 00000000h]
88h
CLOSED_LOOP2
Closed loop configuration 2
CLOSED_LOOP2 Register (Offset = 88h)
[Reset = 00000000h]
8Ah
CLOSED_LOOP3
Closed loop configuration 3
CLOSED_LOOP3 Register (Offset = 8Ah)
[Reset = 14000000h]
8Ch
CLOSED_LOOP4
Closed loop configuration 4
CLOSED_LOOP4 Register (Offset = 8Ch)
[Reset = 00000000h]
8Eh
CONST_SPEED
Constant speed configuration
CONST_SPEED Register (Offset = 8Eh)
[Reset = 00000000h]
90h
CONST_PWR
Constant power configuration
CONST_PWR Register (Offset = 90h) [Reset
= 00000000h]
96h
150_DEG_TWO_PH_PROFILE
150° Two-ph profile
98h
150_DEG_THREE_PH_PROFIL
E
150° Three-ph profile
150_DEG_THREE_PH_PROFILE Register
(Offset = 98h) [Reset = 00000000h]
9Ah
TRAP_CONFIG1
Trap configuration 1
TRAP_CONFIG1 Register (Offset = 9Ah)
[Reset = 00000000h]
9Ch
TRAP_CONFIG2
Trap configuration 2
TRAP_CONFIG2 Register (Offset = 9Ch)
[Reset = 00200000h]
150_DEG_TWO_PH_PROFILE Register
(Offset = 96h) [Reset = 00000000h]
Complex bit access types are encoded to fit into small table cells. Table 7-11 shows the codes that are used for
access types in this section.
Table 7-11. Algorithm_Configuration Access Type
Codes
Access Type
Code
Description
R
Read
W
Write
Read Type
R
Write Type
W
Reset or Default Value
-n
Value after reset or the default
value
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7.7.1.1 ISD_CONFIG Register (Offset = 80h) [Reset = 00000000h]
ISD_CONFIG is shown in Figure 7-56 and described in Table 7-12.
Return to the Summary Table.
Register to configure initial speed detect settings
Figure 7-56. ISD_CONFIG Register
31
30
29
28
27
26
PARITY
ISD_EN
BRAKE_EN
HIZ_EN
RVS_DR_EN
RESYNC_EN
25
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
23
22
19
18
17
24
STAT_BRK_EN STAT_DETECT
_THR
R/W-0h
21
20
STAT_DETECT_THR
BRK_MODE
RESERVED
RESERVED
BRK_TIME
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
13
12
15
14
11
10
9
16
8
BRK_TIME
HIZ_TIME
STARTUP_BRK
_TIME
R/W-0h
R/W-0h
R/W-0h
7
6
5
4
3
2
1
STARTUP_BRK_TIME
RESYNC_MIN_THRESHOLD
RESERVED
R/W-0h
R/W-0h
R/W-0h
0
Table 7-12. ISD_CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
31
PARITY
R/W
0h
Parity bit
30
ISD_EN
R/W
0h
ISD enable
0h = Disable
1h = Enable
29
BRAKE_EN
R/W
0h
Brake enable
0h = Disable
1h = Enable
28
HIZ_EN
R/W
0h
Hi-Z enable
0h = Disable
1h = Enable
27
RVS_DR_EN
R/W
0h
Reverse drive enable
0h = Disable
1h = Enable
26
RESYNC_EN
R/W
0h
Resynchronization enable
0h = Disable
1h = Enable
25
STAT_BRK_EN
R/W
0h
Enable or disable brake during stationary
0h = Disable
1h = Enable
STAT_DETECT_THR
R/W
0h
Stationary BEMF detect threshold
0h = 5 mV
1h = 10 mV
2h = 15 mV
3h = 20 mV
4h = 25 mV
5h = 30 mV
6h = 50 mV
7h = 100 mV
BRK_MODE
R/W
0h
Brake mode
0h = All three low-side FETs turned ON
1h = All three high-side FETs turned ON
24-22
21
80
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Table 7-12. ISD_CONFIG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
20
RESERVED
R/W
0h
Reserved
19-17
RESERVED
R/W
0h
Reserved
16-13
BRK_TIME
R/W
0h
Brake time
0h = 10 ms
1h = 50 ms
2h = 100 ms
3h = 200 ms
4h = 300 ms
5h = 400 ms
6h = 500 ms
7h = 750 ms
8h = 1 s
9h = 2 s
Ah = 3 s
Bh = 4 s
Ch = 5 s
Dh = 7.5 s
Eh = 10 s
Fh = 15 s
12-9
HIZ_TIME
R/W
0h
Hi-Z time
0h = 10 ms
1h = 50 ms
2h = 100 ms
3h = 200 ms
4h = 300 ms
5h = 400 ms
6h = 500 ms
7h = 750 ms
8h = 1 s
9h = 2 s
Ah = 3 s
Bh = 4 s
Ch = 5 s
Dh = 7.5 s
Eh = 10 s
Fh = 15 s
8-6
STARTUP_BRK_TIME
R/W
0h
Brake time when motor is stationary
0h = 1 ms
1h = 10 ms
2h = 25 ms
3h = 50 ms
4h = 100 ms
5h = 250 ms
6h = 500 ms
7h = 1000 ms
5-3
RESYNC_MIN_THRESH
OLD
R/W
0h
Minimum phase BEMF below which the motor is coasted instead of
resync
0h = computed based on MIN_DUTY
1h = 300 mV
2h = 400 mV
3h = 500 mV
4h = 600 mV
5h = 800 mV
6h = 1000 mV
7h = 1250 mV
2-0
RESERVED
R/W
0h
Reserved
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7.7.1.2 MOTOR_STARTUP1 Register (Offset = 82h) [Reset = 00000000h]
MOTOR_STARTUP1 is shown in Figure 7-57 and described in Table 7-13.
Return to the Summary Table.
Register to configure motor startup settings1
Figure 7-57. MOTOR_STARTUP1 Register
31
30
29
28
27
26
25
24
PARITY
MTR_STARTUP
ALIGN_RAMP_RATE
ALIGN_TIME
R/W-0h
R/W-0h
R/W-0h
R/W-0h
23
22
21
20
19
18
17
16
ALIGN_TIME
ALIGN_CURR_THR
IPD_CLK_FRE
Q
R/W-0h
R/W-0h
R/W-0h
15
14
13
12
11
10
9
8
IPD_CLK_FREQ
IPD_CURR_THR
IPD_RLS_MODE
R/W-0h
R/W-0h
R/W-0h
7
6
5
4
3
2
1
IPD_ADV_ANGLE
IPD_REPEAT
SLOW_FIRST_CYC_FREQ
R/W-0h
R/W-0h
R/W-0h
0
Table 7-13. MOTOR_STARTUP1 Register Field Descriptions
82
Bit
Field
Type
Reset
Description
31
PARITY
R/W
0h
Parity bit
30-29
MTR_STARTUP
R/W
0h
Motor start-up method
0h = Align
1h = Double Align
2h = IPD
3h = Slow first cycle
28-25
ALIGN_RAMP_RATE
R/W
0h
Align voltage ramp rate
0h = 0.1 V/s
1h = 0.2 V/s
2h = 0.5 V/s
3h = 1 V/s
4h = 2.5 V/s
5h = 5 V/s
6h = 7.5 V/s
7h = 10 V/s
8h = 25 V/s
9h = 50 V/s
Ah = 75 V/s
Bh = 100 V/s
Ch = 250 V/s
Dh = 500 V/s
Eh = 750 V/s
Fh = 1000 V/s
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Table 7-13. MOTOR_STARTUP1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
24-21
ALIGN_TIME
R/W
0h
Align time
0h = 5 ms
1h = 10 ms
2h = 25 ms
3h = 50 ms
4h = 75 ms
5h = 100 ms
6h = 200 ms
7h = 400 ms
8h = 600 ms
9h = 800 ms
Ah = 1 s
Bh = 2 s
Ch = 4 s
Dh = 6 s
Eh = 8 s
Fh = 10 s
20-17
ALIGN_CURR_THR
R/W
0h
Align current threshold (Align current threshold (A) =
ALIGN_CURR_THR / CSA_GAIN)
0h = Reserved
1h = 0.1V
2h = 0.2 V
3h = 0.3 V
4h = 0.4 V
5h = 0.5 V
6h = 0.6 V
7h = 0.7 V
8h = 0.8 V
9h = 0.9 V
Ah = 1 V
Bh = 1.1 V
Ch = 1.2 V
Dh = 1.3 V
Eh = 1.4 V
Fh = 1.5 V
16-14
IPD_CLK_FREQ
R/W
0h
IPD clock frequency
0h = 50 Hz
1h = 100 Hz
2h = 250 Hz
3h = 500 Hz
4h = 1000 Hz
5h = 2000 Hz
6h = 5000 Hz
7h = 10000 Hz
13-10
IPD_CURR_THR
R/W
0h
IPD current threshold (IPD current threshold (A) = IPD_CURR_THR /
CSA_GAIN)
0h = Reserved
1h = Reserved
2h = 0.2 V
3h = 0.3 V
4h = 0.4 V
5h = 0.5 V
6h = 0.6 V
7h = 0.7 V
8h = 0.8 V
9h = 0.9 V
Ah = 1 V
Bh = 1.1 V
Ch = 1.2 V
Dh = 1.3 V
Eh = 1.4 V
Fh = 1.5 V
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Table 7-13. MOTOR_STARTUP1 Register Field Descriptions (continued)
84
Bit
Field
Type
Reset
Description
9-8
IPD_RLS_MODE
R/W
0h
IPD release mode
0h = Brake
1h = Tristate
2h = Reserved
3h = Reserved
7-6
IPD_ADV_ANGLE
R/W
0h
IPD advance angle
0h = 0°
1h = 30°
2h = 60°
3h = 90°
5-4
IPD_REPEAT
R/W
0h
Number of times IPD is executed
0h = one
1h = average of 2 times
2h = average of 3 times
3h = average of 4 times
3-0
SLOW_FIRST_CYC_FRE R/W
Q
0h
Frequency of first cycle
0h = 0.05 Hz
1h = 0.1 Hz
2h = 0.25 Hz
3h = 0.5 Hz
4h = 1 Hz
5h = 2 Hz
6h = 3 Hz
7h = 5 Hz
8h = 10 Hz
9h = 15 Hz
Bh = 25 Hz
Ch = 50 Hz
Dh = 100 Hz
Eh = 150 Hz
Fh = 200 Hz
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SLLSFP7A – DECEMBER 2022 – REVISED APRIL 2023
7.7.1.3 MOTOR_STARTUP2 Register (Offset = 84h) [Reset = X]
MOTOR_STARTUP2 is shown in Figure 7-58 and described in Table 7-14.
Return to the Summary Table.
Register to configure motor startup settings2
Figure 7-58. MOTOR_STARTUP2 Register
31
30
PARITY
OL_ILIMIT_CO
NFIG
29
OL_DUTY
28
OL_ILIMIT
R/W-0h
R/W-0h
R/W-0h
R/W-0h
23
22
21
27
20
26
19
25
18
24
17
16
OL_ILIMIT
OL_ACC_A1
OL_ACC_A2
R/W-0h
R/W-0h
R/W-0h
15
14
13
12
11
10
9
OL_ACC_A2
OPN_CL_HANDOFF_THR
R/W-0h
R/W-0h
7
6
5
4
AUTO_HANDO FIRST_CYCLE
FF
_FREQ_SEL
R/W-0h
R/W-0h
3
2
8
1
0
MIN_DUTY
RESERVED
R/W-0h
R-X
Table 7-14. MOTOR_STARTUP2 Register Field Descriptions
Bit
Field
Type
Reset
Description
31
PARITY
R/W
0h
Parity bit
30
OL_ILIMIT_CONFIG
R/W
0h
Open loop current limit configuration
0h = Open loop current limit defined by OL_ILIMIT
1h = Open loop current limit defined by ILIMIT
29-27
OL_DUTY
R/W
0h
Duty cycle limit during open loop
0h = 10%
1h = 15%
2h = 20%
3h = 25%
4h = 30%
5h = 40%
6h = 50%
7h = 100%
26-23
OL_ILIMIT
R/W
0h
Open loop current limit (OL current threshold (A) = OL_CURR_THR /
CSA_GAIN)
0h = Reserved
1h = 0.1V
2h = 0.2 V
3h = 0.3 V
4h = 0.4 V
5h = 0.5 V
6h = 0.6 V
7h = 0.7 V
8h = 0.8 V
9h = 0.9 V
Ah = 1 V
Bh = 1.1 V
Ch = 1.2 V
Dh = 1.3 V
Eh = 1.4 V
Fh = 1.5 V
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Table 7-14. MOTOR_STARTUP2 Register Field Descriptions (continued)
Bit
22-18
86
Field
Type
Reset
Description
OL_ACC_A1
R/W
0h
Open loop acceleration A1
0h = 0.005 Hz/s
1h = 0.01 Hz/s
2h = 0.025 Hz/s
3h = 0.05 Hz/s
4h = 0.1 Hz/s
5h = 0.25 Hz/s
6h = 0.5 Hz/s
7h = 1 Hz/s
8h = 2.5 Hz/s
9h = 5 Hz/s
Ah = 7.5 Hz/s
Bh = 10 Hz/s
Ch = 12.5 Hz/s
Dh = 15 Hz/s
Eh = 20 Hz/s
Fh = 30 Hz/s
10h = 40 Hz/s
11h = 50 Hz/s
12h = 60 Hz/s
13h = 75 Hz/s
14h = 100 Hz/s
15h = 125 Hz/s
16h = 150 Hz/s
17h = 175 Hz/s
18h = 200 Hz/s
19h = 250 Hz/s
1Ah = 300 Hz/s
1Bh = 400 Hz/s
1Ch = 500 Hz/s
1Dh = 750 Hz/s
1Eh = 1000 Hz/s
1Fh = No Limit (32767) Hz/s
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Table 7-14. MOTOR_STARTUP2 Register Field Descriptions (continued)
Bit
17-13
Field
Type
Reset
Description
OL_ACC_A2
R/W
0h
Open loop acceleration A2
0h = 0.005 Hz/s2
1h = 0.01 Hz/s2
2h = 0.025 Hz/s2
3h = 0.05 Hz/s2
4h = 0.1 Hz/s2
5h = 0.25 Hz/s2
6h = 0.5 Hz/s2
7h = 1 Hz/s2
8h = 2.5 Hz/s2
9h = 5 Hz/s2
Ah = 7.5 Hz/s2
Bh = 10 Hz/s2
Ch = 12.5 Hz/s2
Dh = 15 Hz/s2
Eh = 20 Hz/s2
Fh = 30 Hz/s2
10h = 40 Hz/s2
11h = 50 Hz/s2
12h = 60 Hz/s2
13h = 75 Hz/s2
14h = 100 Hz/s2
15h = 125 Hz/s2
16h = 150 Hz/s2
17h = 175 Hz/s2
18h = 200 Hz/s2
19h = 250 Hz/s2
1Ah = 300 Hz/s2
1Bh = 400 Hz/s2
1Ch = 500 Hz/s2
1Dh = 750 Hz/s2
1Eh = 1000 Hz/s2
1Fh = No Limit (32767) Hz/s2
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Table 7-14. MOTOR_STARTUP2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
OPN_CL_HANDOFF_TH
R
R/W
0h
Open to closed loop handoff threshold
0h = 1 Hz
1h = 4 Hz
2h = 8 Hz
3h = 12 Hz
4h = 16 Hz
5h = 20 Hz
6h = 24 Hz
7h = 28 Hz
8h = 32 Hz
9h = 36 Hz
Ah = 40 Hz
Bh = 45 Hz
Ch = 50 Hz
Dh = 55 Hz
Eh = 60 Hz
Fh = 65 Hz
10h = 70 Hz
11h = 75 Hz
12h = 80 Hz
13h = 85 Hz
14h = 90 Hz
15h = 100 Hz
16h = 150 Hz
17h = 200 Hz
18h = 250 Hz
19h = 300 Hz
1Ah = 350 Hz
1Bh = 400 Hz
1Ch = 450 Hz
1Dh = 500 Hz
1Eh = 550 Hz
1Fh = 600 Hz
7
AUTO_HANDOFF
R/W
0h
Auto handoff enable
0h = Disable Auto Handoff (and use OPN_CL_HANDOFF_THR)
1h = Enable Auto Handoff
6
FIRST_CYCLE_FREQ_S
EL
R/W
0h
First cycle frequency select
0h = Defined by SLOW_FIRST_CYC_FREQ
1h = 0 Hz
5-2
MIN_DUTY
R/W
0h
Min operational duty cycle
0h = 1.5 %
1h = 2 %
2h = 3 %
3h = 4 %
4h = 5 %
5h = 6 %
6h = 7 %
7h = 8 %
8h = 9 %
9h = 10 %
Ah = 12 %
Bh = 15 %
Ch = 17.5 %
Dh = 20 %
Eh = 25 %
Fh = 30 %
1-0
RESERVED
R
X
Reserved
12-8
88
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7.7.1.4 CLOSED_LOOP1 Register (Offset = 86h) [Reset = 00000000h]
CLOSED_LOOP1 is shown in Figure 7-59 and described in Table 7-15.
Return to the Summary Table.
Register to configure close loop settings1
Figure 7-59. CLOSED_LOOP1 Register
31
30
29
28
27
26
PARITY
COMM_CONTROL
CL_ACC
R/W-0h
R/W-0h
R/W-0h
23
22
21
20
19
18
25
24
17
16
CL_DEC_CON
FIG
CL_DEC
PWM_FREQ_OUT
R/W-0h
R/W-0h
R/W-0h
15
14
13
12
11
10
9
8
PWM_FREQ_OUT
PWM_MODUL
PWM_MODE
LD_ANGLE_PO
LARITY
LD_ANGLE
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
2
1
0
7
6
5
4
3
LD_ANGLE
RESERVED
R/W-0h
R/W-0h
Table 7-15. CLOSED_LOOP1 Register Field Descriptions
Bit
Field
Type
Reset
Description
31
PARITY
R/W
0h
Parity bit
COMM_CONTROL
R/W
0h
Trapezoidal commutation mode
0h = 120° Commutation
1h = Variable commutation between 120° and 150°
2h = Reserved
3h = Reserved
30-29
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Table 7-15. CLOSED_LOOP1 Register Field Descriptions (continued)
Bit
28-24
23
90
Field
Type
Reset
Description
CL_ACC
R/W
0h
Closed loop acceleration rate
0h = 0.005 V/s
1h = 0.01 V/s
2h = 0.025 V/s
3h = 0.05 V/s
4h = 0.1 V/s
5h = 0.25 V/s
6h = 0.5 V/s
7h = 1 V/s
8h = 2.5 V/s
9h = 5 V/s
Ah = 7.5 V/s
Bh = 10 V/s
Ch = 12.5 V/s
Dh = 15 V/s
Eh = 20 V/s
Fh = 30 V/s
10h = 40 V/s
11h = 50 V/s
12h = 60 V/s
13h = 75 V/s
14h = 100 V/s
15h = 125 V/s
16h = 150 V/s
17h = 175 V/s
18h = 200 V/s
19h = 250 V/s
1Ah = 300 V/s
1Bh = 400 V/s
1Ch = 500 V/s
1Dh = 750 V/s
1Eh = 1000 V/s
1Fh = 32767 V/s
CL_DEC_CONFIG
R/W
0h
Closed loop decel configuration
0h = Close loop deceleration defined by CL_DEC
1h = Close loop deceleration defined by CL_ACC
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Table 7-15. CLOSED_LOOP1 Register Field Descriptions (continued)
Bit
22-18
Field
Type
Reset
Description
CL_DEC
R/W
0h
Closed loop deceleration rate
0h = 0.005 V/s
1h = 0.01 V/s
2h = 0.025 V/s
3h = 0.05 V/s
4h = 0.1 V/s
5h = 0.25 V/s
6h = 0.5 V/s
7h = 1 V/s
8h = 2.5 V/s
9h = 5 V/s
Ah = 7.5 V/s
Bh = 10 V/s
Ch = 12.5 V/s
Dh = 15 V/s
Eh = 20 V/s
Fh = 30 V/s
10h = 40 V/s
11h = 50 V/s
12h = 60 V/s
13h = 75 V/s
14h = 100 V/s
15h = 125 V/s
16h = 150 V/s
17h = 175 V/s
18h = 200 V/s
19h = 250 V/s
1Ah = 300 V/s
1Bh = 400 V/s
1Ch = 500 V/s
1Dh = 750 V/s
1Eh = 1000 V/s
1Fh = 32767 V/s
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Table 7-15. CLOSED_LOOP1 Register Field Descriptions (continued)
Bit
92
Field
Type
Reset
Description
17-13
PWM_FREQ_OUT
R/W
0h
Output PWM switching frequency
0h = 5 kHz
1h = 6 kHz
2h = 7 kHz
3h = 8 kHz
4h = 9 kHz
5h = 10 kHz
6h = 11 kHz
7h = 12 kHz
8h = 13 kHz
9h = 14 kHz
Ah = 15 kHz
Bh = 16 kHz
Ch = 17 kHz
Dh = 18 kHz
Eh = 19 kHz
Fh = 20 kHz
10h = 25 kHz
11h = 30 kHz
12h = 35 kHz
13h = 40 kHz
14h = 45 kHz
15h = 50 kHz
16h = 55 kHz
17h = 60 kHz
18h = 65 kHz
19h = 70 kHz
1Ah = 75 kHz
1Bh = 80 kHz
1Ch = 85 kHz
1Dh = 90 kHz
1Eh = 95 kHz
1Fh = 100 kHz
12-11
PWM_MODUL
R/W
0h
PWM modulation.
0h = High-Side Modulation
1h = Low-Side Modulation
2h = Mixed Modulation
3h = Reserved
10
PWM_MODE
R/W
0h
PWM mode
0h = Single Ended Mode
1h = Complementary Mode
9
LD_ANGLE_POLARITY
R/W
0h
Polarity of applied lead angle
0h = Negative
1h = Positive
8-1
LD_ANGLE
R/W
0h
Lead Angle {Lead Angle (deg) = LD_ANGLE * 0.12}
0
RESERVED
R/W
0h
Reserved
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SLLSFP7A – DECEMBER 2022 – REVISED APRIL 2023
7.7.1.5 CLOSED_LOOP2 Register (Offset = 88h) [Reset = 00000000h]
CLOSED_LOOP2 is shown in Figure 7-60 and described in Table 7-16.
Return to the Summary Table.
Register to configure close loop settings2
Figure 7-60. CLOSED_LOOP2 Register
31
30
29
28
27
26
25
24
PARITY
FG_SEL
FG_DIV_FACTOR
RESERVED
R/W-0h
R/W-0h
R/W-0h
R/W-0h
23
22
21
20
19
18
17
16
FG_BEMF_THR
MTR_STOP
MTR_STOP_BRK_TIME
R/W-0h
R/W-0h
R/W-0h
15
14
13
12
11
10
9
MTR_STOP_BRK_TIME
ACT_SPIN_BRK_THR
BRAKE_DUTY_THRESHOLD
R/W-0h
R/W-0h
R/W-0h
7
6
5
4
3
2
1
AVS_EN
CBC_ILIMIT
RESERVED
R/W-0h
R/W-0h
R/W-0h
8
0
Table 7-16. CLOSED_LOOP2 Register Field Descriptions
Bit
Field
Type
Reset
Description
31
PARITY
R/W
0h
Parity bit
30-29
FG_SEL
R/W
0h
FG mode select
0h = Output FG in open loop and closed loop
1h = Output FG in only closed loop
2h = Output FG in open loop for the first try.
3h = Reserved
28-25
FG_DIV_FACTOR
R/W
0h
FG division factor
0h = Divide by 3 (2-pole motor mechanical speed/3)
1h = Divide by 1 (2-pole motor mechanical speed)
2h = Divide by 2 (4-pole motor mechanical speed)
3h = Divide by 3 (6-pole motor mechanical speed)
4h = Divide by 4 (8-pole motor mechanical speed)
5h = Divide by 5 (10-pole motor mechanical speed)
6h = Divide by 6 (12-pole motor mechanical speed)
7h = Divide by 7 (14-pole motor mechanical speed)
8h = Divide by 8 (16-pole motor mechanical speed)
9h = Divide by 9 (18-pole motor mechanical speed)
Ah = Divide by 10 (20-pole motor mechanical speed)
Bh = Divide by 11 (22-pole motor mechanical speed)
Ch = Divide by 12 (24-pole motor mechanical speed)
Dh = Divide by 13 (26-pole motor mechanical speed)
Eh = Divide by 14 (28-pole motor mechanical speed)
Fh = Divide by 15 (30-pole motor mechanical speed)
RESERVED
R/W
0h
Reserved
FG_BEMF_THR
R/W
0h
FG output BEMF threshold
0h = +/- 1mV
1h = +/- 2mV
2h = +/- 5mV
3h = +/- 10mV
4h = +/- 20mV
5h = +/- 30mV
6h = Reserved
7h = Reserved
24
23-21
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Table 7-16. CLOSED_LOOP2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
20-18
MTR_STOP
R/W
0h
Motor stop method
0h = Hi-z
1h = Recirculation
2h = Low-side braking
3h = High-side braking
4h = Active spin down
5h = Reserved
6h = Reserved
7h = Reserved
17-14
MTR_STOP_BRK_TIME
R/W
0h
Brake time during motor stop
0h = 1 ms
1h = 2 ms
2h = 5 ms
3h = 10 ms
4h = 15 ms
5h = 25 ms
6h = 50 ms
7h = 75 ms
8h = 100 ms
9h = 250 ms
Ah = 500 ms
Bh = 1000 ms
Ch = 2500 ms
Dh = 5000 ms
Eh = 10000 ms
Fh = 15000 ms
13-11
ACT_SPIN_BRK_THR
R/W
0h
Duty cycle threshold for motor stop using active spin down, low- and
high-side braking
0h = Immediate
1h = 50 %
2h = 25 %
3h = 15 %
4h = 10 %
5h = 7.5 %
6h = 5 %
7h = 2.5 %
10-8
BRAKE_DUTY_THRESH
OLD
R/W
0h
Duty cycle threshold for BRAKE pin based low-side braking
0h = Immediate
1h = 50 %
2h = 25 %
3h = 15 %
4h = 10 %
5h = 7.5 %
6h = 5 %
7h = 2.5 %
AVS_EN
R/W
0h
AVS enable
0h = Disable
1h = Enable
7
94
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Table 7-16. CLOSED_LOOP2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
6-3
CBC_ILIMIT
R/W
0h
Cycle by Cycle (CBC) current limit (CBC current limit (A) =
CBC_ILIMIT / CSA_GAIN)
0h = Reserved
1h = 0.1 V
2h = 0.2 V
3h = 0.3 V
4h = 0.4 V
5h = 0.5 V
6h = 0.6 V
7h = 0.7 V
8h = 0.8 V
9h = 0.9 V
Ah = 1 V
Bh = 1.1 V
Ch = 1.2 V
Dh = 1.3 V
Eh = 1.4 V
Fh = 1.5 V
2-0
RESERVED
R/W
0h
Reserved
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SLLSFP7A – DECEMBER 2022 – REVISED APRIL 2023
7.7.1.6 CLOSED_LOOP3 Register (Offset = 8Ah) [Reset = 14000000h]
CLOSED_LOOP3 is shown in Figure 7-61 and described in Table 7-17.
Return to the Summary Table.
Register to configure close loop settings3
Figure 7-61. CLOSED_LOOP3 Register
31
30
29
28
27
26
25
24
PARITY
DYN_DGS_FILT_COUNT
DYN_DGS_UPPER_LIM
DYN_DGS_LOWER_LIM
INTEG_CYCL_
THR_LOW
R/W-0h
R/W-0h
R/W-2h
R/W-2h
R/W-0h
23
22
21
20
19
18
17
16
INTEG_CYCL_
THR_LOW
INTEG_CYCL_THR_HIGH
INTEG_DUTY_THR_LOW
INTEG_DUTY_THR_HIGH
BEMF_THRES
HOLD2
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
15
14
7
13
12
11
10
9
8
BEMF_THRESHOLD2
BEMF_THRESHOLD1
R/W-0h
R/W-0h
6
5
4
3
2
1
0
BEMF_THRESHOLD1
INTEG_ZC_ME
THOD
DEGAUSS_MAX_WIN
DYN_DEGAUS
S_EN
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 7-17. CLOSED_LOOP3 Register Field Descriptions
96
Bit
Field
Type
Reset
Description
31
PARITY
R/W
0h
Parity bit
30-29
DYN_DGS_FILT_COUNT R/W
0h
Number of samples needed for dynamic degauss check
0h = 15
1h = 20
2h = 30
3h = 12
28-27
DYN_DGS_UPPER_LIM
R/W
2h
Dynamic degauss voltage upper bound
0h = (VM - 0.09) V
1h = (VM - 0.12) V
2h = (VM - 0.15) V
3h = (VM - 0.18) V
26-25
DYN_DGS_LOWER_LIM
R/W
2h
Dynamic degauss voltage lower bound
0h = 0.03 V
1h = 0.06 V
2h = 0.09 V
3h = 0.12 V
24-23
INTEG_CYCL_THR_LOW R/W
0h
Number of BEMF samples per 30° below which commutation method
switches from integration to ZC
0h = 3
1h = 4
2h = 6
3h = 8
22-21
INTEG_CYCL_THR_HIG
H
0h
Number of BEMF samples per 30° above which commutation
method switches from ZC to integration
0h = 4
1h = 6
2h = 8
3h = 10
R/W
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Table 7-17. CLOSED_LOOP3 Register Field Descriptions (continued)
Bit
Field
Reset
Description
20-19
INTEG_DUTY_THR_LOW R/W
Type
0h
Duty cycle below which commutation method switches from
integration to ZC
0h = 12 %
1h = 15 %
2h = 18 %
3h = 20 %
18-17
INTEG_DUTY_THR_HIG
H
0h
Duty cycle above which commutation method switches from ZC to
integration
0h = 12 %
1h = 15 %
2h = 18 %
3h = 20 %
R/W
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Table 7-17. CLOSED_LOOP3 Register Field Descriptions (continued)
Bit
16-11
98
Field
Type
Reset
Description
BEMF_THRESHOLD2
R/W
0h
BEMF threshold for integration based commutation during falling
floating phase voltage
0h = 0
1h = 25
2h = 50
3h = 75
4h = 100
5h = 125
6h = 150
7h = 175
8h = 200
9h = 225
Ah = 250
Bh = 275
Ch = 300
Dh = 325
Eh = 350
Fh = 375
10h = 400
11h = 425
12h = 450
13h = 475
14h = 500
15h = 525
16h = 550
17h = 575
18h = 600
19h = 625
1Ah = 650
1Bh = 675
1Ch = 700
1Dh = 725
1Eh = 750
1Fh = 775
20h = 800
21h = 850
22h = 900
23h = 950
24h = 1000
25h = 1050
26h = 1100
27h = 1150
28h = 1200
29h = 1250
2Ah = 1300
2Bh = 1350
2Ch = 1400
2Dh = 1450
2Eh = 1500
2Fh = 1550
30h = 1600
31h = 1700
32h = 1800
33h = 1900
34h = 2000
35h = 2100
36h = 2200
37h = 2300
38h = 2400
39h = 2600
3Ah = 2800
3Bh = 3000
3Ch = 3200
3Dh = 3400
3Eh = 3600
3Fh = 3800
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Table 7-17. CLOSED_LOOP3 Register Field Descriptions (continued)
Bit
10-5
Field
Type
Reset
Description
BEMF_THRESHOLD1
R/W
0h
BEMF threshold for integration based commutation during rising
floating phase voltage
0h = 0
1h = 25
2h = 50
3h = 75
4h = 100
5h = 125
6h = 150
7h = 175
8h = 200
9h = 225
Ah = 250
Bh = 275
Ch = 300
Dh = 325
Eh = 350
Fh = 375
10h = 400
11h = 425
12h = 450
13h = 475
14h = 500
15h = 525
16h = 550
17h = 575
18h = 600
19h = 625
1Ah = 650
1Bh = 675
1Ch = 700
1Dh = 725
1Eh = 750
1Fh = 775
20h = 800
21h = 850
22h = 900
23h = 950
24h = 1000
25h = 1050
26h = 1100
27h = 1150
28h = 1200
29h = 1250
2Ah = 1300
2Bh = 1350
2Ch = 1400
2Dh = 1450
2Eh = 1500
2Fh = 1550
30h = 1600
31h = 1700
32h = 1800
33h = 1900
34h = 2000
35h = 2100
36h = 2200
37h = 2300
38h = 2400
39h = 2600
3Ah = 2800
3Bh = 3000
3Ch = 3200
3Dh = 3400
3Eh = 3600
3Fh = 3800
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SLLSFP7A – DECEMBER 2022 – REVISED APRIL 2023
Table 7-17. CLOSED_LOOP3 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
4
INTEG_ZC_METHOD
R/W
0h
Commutation method select
0h = ZC based
1h = Integration based
3-1
DEGAUSS_MAX_WIN
R/W
0h
Maximum degauss window
0h = 22.5°
1h = 10°
2h = 15°
3h = 18°
4h = 30°
5h = 37.5°
6h = 45°
7h = 60°
DYN_DEGAUSS_EN
R/W
0h
Dynamic degauss detection
0h = Disable
1h = Enable
0
100
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SLLSFP7A – DECEMBER 2022 – REVISED APRIL 2023
7.7.1.7 CLOSED_LOOP4 Register (Offset = 8Ch) [Reset = 00000000h]
CLOSED_LOOP4 is shown in Figure 7-62 and described in Table 7-18.
Return to the Summary Table.
Register to configure close loop settings4
Figure 7-62. CLOSED_LOOP4 Register
31
30
29
28
27
PARITY
RESERVED
R/W-0h
R/W-0h
23
22
15
21
20
19
26
25
24
18
17
16
RESERVED
WCOMP_BLAN
K_EN
FAST_DEC_DUTY_WIN
R/W-0h
R/W-0h
R/W-0h
14
13
12
11
10
9
8
FAST_DEC_DUTY_THR
DYN_BRK_CURR_LOW_LIM
DYNAMIC_BRK
_CURR
R/W-0h
R/W-0h
R/W-0h
7
6
5
4
3
2
1
FAST_DECEL_
EN
FAST_DECEL_CURR_LIM
FAST_BRK_DELTA
R/W-0h
R/W-0h
R/W-0h
0
Table 7-18. CLOSED_LOOP4 Register Field Descriptions
Bit
Field
Type
Reset
Description
31
PARITY
R/W
0h
Parity bit
RESERVED
R/W
0h
Reserved
WCOMP_BLANK_EN
R/W
0h
Enable WCOMP blanking during fast deceleration
0h = Disable
1h = Enable
18-16
FAST_DEC_DUTY_WIN
R/W
0h
Fast deceleration duty window
0h = 0 %
1h = 2.5 %
2h = 5 %
3h = 7.5 %
4h = 10 %
5h = 15 %
6h = 20 %
7h = 25 %
15-13
FAST_DEC_DUTY_THR
R/W
0h
Fast deceleration duty threshold
0h = 100 %
1h = 95 %
2h = 90 %
3h = 85 %
4h = 80 %
5h = 75 %
6h = 70%
7h = 65 %
30-20
19
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Table 7-18. CLOSED_LOOP4 Register Field Descriptions (continued)
Bit
Reset
Description
DYN_BRK_CURR_LOW_ R/W
LIM
0h
Fast deceleration dynamic current limit lower threshold (Deceleration
current lower threshold (A) = DYN_BRK_CURR_LOW_LIM /
CSA_GAIN)
0h = Reserved
1h = 0.1V
2h = 0.2 V
3h = 0.3 V
4h = 0.4 V
5h = 0.5 V
6h = 0.6 V
7h = 0.7 V
8h = 0.8 V
9h = 0.9 V
Ah = 1 V
Bh = 1.1 V
Ch = 1.2 V
Dh = 1.3 V
Eh = 1.4 V
Fh = 1.5 V
8
DYNAMIC_BRK_CURR
R/W
0h
Enable dynamic decrease in current limit during fast deceleration
0h = Disable
1h = Enable
7
FAST_DECEL_EN
R/W
0h
Fast deceleration enable
0h = Disable
1h = Enable
6-3
FAST_DECEL_CURR_LI
M
R/W
0h
Deceleration current threshold (Fast Deceleration current limit upper
threshold (A) = FAST_DECEL_CURR_LIM / CSA_GAIN)
0h = Reserved
1h = 0.1V
2h = 0.2 V
3h = 0.3 V
4h = 0.4 V
5h = 0.5 V
6h = 0.6 V
7h = 0.7 V
8h = 0.8 V
9h = 0.9 V
Ah = 1 V
Bh = 1.1 V
Ch = 1.2 V
Dh = 1.3 V
Eh = 1.4 V
Fh = 1.5 V
2-0
FAST_BRK_DELTA
R/W
0h
Fast deceleration exit speed delta
0h = 0.5 %
1h = 1 %
2h = 1.5 %
3h = 2 %
4h = 2.5 %
5h = 3 %
6h = 4 %
7h = 5 %
12-9
102
Field
Type
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SLLSFP7A – DECEMBER 2022 – REVISED APRIL 2023
7.7.1.8 CONST_SPEED Register (Offset = 8Eh) [Reset = 00000000h]
CONST_SPEED is shown in Figure 7-63 and described in Table 7-19.
Return to the Summary Table.
Register to configure Constant speed mode settings
Figure 7-63. CONST_SPEED Register
31
30
PARITY
RESERVED
SPD_POWER_KP
R/W-0h
R/W-0h
R/W-0h
23
22
15
29
28
21
27
20
26
19
18
25
24
17
16
SPD_POWER_KP
SPD_POWER_KI
R/W-0h
R/W-0h
14
13
12
11
10
9
8
2
1
0
SPD_POWER_KI
R/W-0h
7
6
5
4
3
SPD_POWER_V_MAX
SPD_POWER_V_MIN
CLOSED_LOOP_MODE
R/W-0h
R/W-0h
R/W-0h
Table 7-19. CONST_SPEED Register Field Descriptions
Bit
Field
Type
Reset
Description
31
PARITY
R/W
0h
Parity bit
30
RESERVED
R/W
0h
Reserved
29-20
SPD_POWER_KP
R/W
0h
Speed/ Power loop Kp (Kp = SPD_LOOP_KP / 10000)
19-8
SPD_POWER_KI
R/W
0h
Speed/ Power loop Ki (Ki = SPD_LOOP_KI / 1000000)
7-5
SPD_POWER_V_MAX
R/W
0h
Upper saturation limit for speed/ power loop
0h = 100 %
1h = 95 %
2h = 90 %
3h = 85 %
4h = 80 %
5h = 75 %
6h = 70%
7h = 65 %
4-2
SPD_POWER_V_MIN
R/W
0h
Lower saturation limit for speed/power loop
0h = 0 %
1h = 2.5 %
2h = 5 %
3h = 7.5 %
4h = 10 %
5h = 15 %
6h = 20 %
7h = 25 %
1-0
CLOSED_LOOP_MODE
R/W
0h
Closed loop mode
0h = Disabled
1h = Speed Loop
2h = Power Loop
3h = Reserved
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SLLSFP7A – DECEMBER 2022 – REVISED APRIL 2023
7.7.1.9 CONST_PWR Register (Offset = 90h) [Reset = 00000000h]
CONST_PWR is shown in Figure 7-64 and described in Table 7-20.
Return to the Summary Table.
Register to configure Constant power mode settings
Figure 7-64. CONST_PWR Register
31
30
29
28
27
PARITY
MAX_SPEED
R/W-0h
R/W-0h
23
22
21
20
19
26
25
24
18
17
16
10
9
8
1
0
MAX_SPEED
R/W-0h
15
14
MAX_SPEED
DEADTIME_CO
MP_EN
13
12
MAX_POWER
R/W-0h
R/W-0h
R/W-0h
7
6
5
4
11
3
2
MAX_POWER
CONST_POWER_LIMIT_HYST
CONST_POWER_MODE
R/W-0h
R/W-0h
R/W-0h
Table 7-20. CONST_PWR Register Field Descriptions
Bit
Field
Type
Reset
Description
31
PARITY
R/W
0h
Parity bit
MAX_SPEED
R/W
0h
Maximum Speed (Maximum Speed (Hz) = MAX_SPEED / 16)
DEADTIME_COMP_EN
R/W
0h
Enable dead time compensation
0h = Disable
1h = Enable
13-4
MAX_POWER
R/W
0h
Maximum power (Maximum power (W) = MAX_POWER / 4)
3-2
CONST_POWER_LIMIT_ R/W
HYST
0h
Hysteresis for input power regulation
0h = 5 %
1h = 7.5 %
2h = 10 %
3h = 12.5 %
1-0
CONST_POWER_MODE
0h
Input power regulation mode
0h = Disabled
1h = Closed Loop Power Control
2h = Power Limit Control
3h = Reserved
30-15
14
104
R/W
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SLLSFP7A – DECEMBER 2022 – REVISED APRIL 2023
7.7.1.10 150_DEG_TWO_PH_PROFILE Register (Offset = 96h) [Reset = 00000000h]
150_DEG_TWO_PH_PROFILE is shown in Figure 7-65 and described in Table 7-21.
Return to the Summary Table.
Register to configure 150 degree modulation TWO phase duty
Figure 7-65. 150_DEG_TWO_PH_PROFILE Register
31
30
29
28
27
26
25
24
PARITY
TWOPH_STEP0
TWOPH_STEP1
TWOPH_STEP
2
R/W-0h
R/W-0h
R/W-0h
R/W-0h
23
22
21
20
19
18
17
16
TWOPH_STEP2
TWOPH_STEP3
TWOPH_STEP4
R/W-0h
R/W-0h
R/W-0h
15
14
13
12
11
10
9
8
TWOPH_STEP5
TWOPH_STEP6
TWOPH_STEP7
R/W-0h
R/W-0h
R/W-0h
7
6
5
4
3
TWOPH_STEP
7
RESERVED
R/W-0h
R/W-0h
2
1
0
Table 7-21. 150_DEG_TWO_PH_PROFILE Register Field Descriptions
Bit
Field
Type
Reset
Description
31
PARITY
R/W
0h
Parity bit
30-28
TWOPH_STEP0
R/W
0h
150° modulation , Two ph - step duty - 0
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
27-25
TWOPH_STEP1
R/W
0h
150° modulation , Two ph - step duty - 1
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
24-22
TWOPH_STEP2
R/W
0h
150° modulation, Two ph - step duty - 2
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
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Table 7-21. 150_DEG_TWO_PH_PROFILE Register Field Descriptions (continued)
Bit
106
Field
Type
Reset
Description
21-19
TWOPH_STEP3
R/W
0h
150° modulation, Two ph - step duty - 3
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
18-16
TWOPH_STEP4
R/W
0h
150° modulation, Two ph - step duty - 4
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
15-13
TWOPH_STEP5
R/W
0h
150° modulation, Two ph - step duty - 5
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
12-10
TWOPH_STEP6
R/W
0h
150° modulation, Two ph - step duty - 6
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
9-7
TWOPH_STEP7
R/W
0h
150° modulation, Two ph - step duty - 7
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
6-0
RESERVED
R/W
0h
reserved bits for algo parameter update
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7.7.1.11 150_DEG_THREE_PH_PROFILE Register (Offset = 98h) [Reset = 00000000h]
150_DEG_THREE_PH_PROFILE is shown in Figure 7-66 and described in Table 7-22.
Return to the Summary Table.
Register to configure 150 degree modulation Three phase duty
Figure 7-66. 150_DEG_THREE_PH_PROFILE Register
31
30
29
28
27
26
25
24
PARITY
THREEPH_STEP0
THREEPH_STEP1
THREEPH_ST
EP2
R/W-0h
R/W-0h
R/W-0h
R/W-0h
23
22
21
20
19
18
17
16
THREEPH_STEP2
THREEPH_STEP3
THREEPH_STEP4
R/W-0h
R/W-0h
R/W-0h
15
14
13
12
11
10
9
8
THREEPH_STEP5
THREEPH_STEP6
THREEPH_STEP7
R/W-0h
R/W-0h
R/W-0h
7
6
5
4
3
2
THREEPH_ST
EP7
LEAD_ANGLE_150DEG_ADV
RESERVED
R/W-0h
R/W-0h
R/W-0h
1
0
Table 7-22. 150_DEG_THREE_PH_PROFILE Register Field Descriptions
Bit
Field
Type
Reset
Description
31
PARITY
R/W
0h
Parity bit
30-28
THREEPH_STEP0
R/W
0h
150° modulation, Three ph - step duty - 0
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
27-25
THREEPH_STEP1
R/W
0h
150° modulation, Three ph - step duty - 1
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
24-22
THREEPH_STEP2
R/W
0h
150° modulation, Three ph - step duty - 2
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
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Table 7-22. 150_DEG_THREE_PH_PROFILE Register Field Descriptions (continued)
Bit
108
Field
Type
Reset
Description
21-19
THREEPH_STEP3
R/W
0h
150° modulation, Three ph - step duty - 3
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
18-16
THREEPH_STEP4
R/W
0h
150° modulation, Three ph - step duty - 4
0h = 0.0 %
1h = 0.5 %
2h = 0.75 %
3h = 0.8375 %
4h = 0.875 %
5h = 0.9375 %
6h = 0.975 %
7h = 0.99 %
15-13
THREEPH_STEP5
R/W
0h
150° modulation, Three ph - step duty - 5
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
12-10
THREEPH_STEP6
R/W
0h
150° modulation, Three ph - step duty - 6
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
9-7
THREEPH_STEP7
R/W
0h
150° modulation, Three ph - step duty - 7
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
6-5
LEAD_ANGLE_150DEG_ R/W
ADV
0h
Angle advance for 150° modulation
0h = 0°
1h = 5°
2h = 10°
3h = 15°
4-0
RESERVED
0h
Reserved
R/W
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7.7.1.12 TRAP_CONFIG1 Register (Offset = 9Ah) [Reset = 00000000h]
TRAP_CONFIG1 is shown in Figure 7-67 and described in Table 7-23.
Return to the Summary Table.
Register to configure internal Algorithm Variables
Figure 7-67. TRAP_CONFIG1 Register
31
30
29
28
27
26
25
24
PARITY
RESERVED
RESERVED
RESERVED
R/W-0h
R/W-0h
R/W-0h
R/W-0h
23
22
21
20
19
18
17
16
OL_HANDOFF_CYCLES
RESERVED
AVS_NEG_CURR_LIMIT
R/W-0h
R/W-0h
R/W-0h
15
14
13
12
11
10
9
8
AVS_LIMIT_HY
ST
ISD_BEMF_THR
ISD_CYCLE_THR
R/W-0h
R/W-0h
R/W-0h
7
6
ISD_CYCLE_T
HR
RESERVED
5
RESERVED
4
ZC_ANGLE_OL_THR
3
2
FAST_STARTUP_DIV_FACTOR
1
0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 7-23. TRAP_CONFIG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
31
PARITY
R/W
0h
Parity bit
30-29
RESERVED
R/W
0h
Reserved
28-26
RESERVED
R/W
0h
Reserved
25-24
RESERVED
R/W
0h
Reserved
23-22
OL_HANDOFF_CYCLES
R/W
0h
Open loop handoff cycles
0h = 3
1h = 6
2h = 12
3h = 24
21-19
RESERVED
R/W
0h
Reserved
18-16
AVS_NEG_CURR_LIMIT
R/W
0h
AVS negative current limit (AVS negative current limit (A) =
(AVS_NEG_CURRENT_LIMIT * 3 /4095) / CSA_GAIN)
0h = 0
1h = -40
2h = -30
3h = -20
4h = -10
5h = 10
6h = 20
7h = 30
AVS_LIMIT_HYST
R/W
0h
AVS current hysteresis (AVS positive current limit (A) =
((AVS_LIMIT_HYST + AVS_NEG_CURR_LIMIT) * 3 /4095) /
CSA_GAIN)
0h = 20
1h = 10
15
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Table 7-23. TRAP_CONFIG1 Register Field Descriptions (continued)
Bit
110
Field
Type
Reset
Description
14-10
ISD_BEMF_THR
R/W
0h
ISD BEMF threshold (ISD BEMF threshold = 200 * ISD_BEMF_THR)
0h = 0
1h = 200
2h = 400
3h = 600
4h = 800
5h = 1000
6h = 1200
7h = 1400
8h = 1600
9h = 1800
Ah = 2000
Bh = 2200
Ch = 2400
Dh = 2600
Eh = 2800
Fh = 3000
10h = 3200
11h = 3400
12h = 3600
13h = 3800
14h = 4000
15h = 4200
16h = 4400
17h = 4600
18h = 4800
19h = 5000
1Ah = 5200
1Bh = 5400
1Ch = 5600
1Dh = 5800
1Eh = 6000
1Fh = 6200
9-7
ISD_CYCLE_THR
R/W
0h
ISD cycle threshold
0h = 2,
1h = 5,
2h = 8,
3h = 11,
4h = 14,
5h = 17,
6h = 20,
7h = 23
6
RESERVED
R/W
0h
Reserved
5-4
RESERVED
R/W
0h
Reserved
3-2
ZC_ANGLE_OL_THR
R/W
0h
Angle above which the ZC detection is done during OL
0h = 5°
1h = 8°
2h = 12°
3h = 15°
1-0
FAST_STARTUP_DIV_FA R/W
CTOR
0h
Dynamic A1, A2 change rate
0h = 1
1h = 2
2h = 4
3h = 8
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7.7.1.13 TRAP_CONFIG2 Register (Offset = 9Ch) [Reset = 00200000h]
TRAP_CONFIG2 is shown in Figure 7-68 and described in Table 7-24.
Return to the Summary Table.
Register to configure internal Algorithm Variables
Figure 7-68. TRAP_CONFIG2 Register
31
30
29
28
27
26
25
PARITY
TBLANK
TPWDTH
R/W-0h
R/W-0h
R/W-0h
20
19
23
22
21
RESERVED
DGS_HIGH_IN
D_EN
RESERVED
ALIGN_DUTY
ZERO_DUTY_HYST
R/W-0h
R/W-0h
R/W-1h
R/W-0h
R/W-0h
15
14
13
12
18
24
17
16
11
10
9
8
3
2
1
0
RESERVED
R/W-0h
7
6
5
4
RESERVED
R/W-0h
Table 7-24. TRAP_CONFIG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
31
PARITY
R/W
0h
Parity bit
30-27
TBLANK
R/W
0h
Blanking time after PWM edge
0h = 0 µs
1h = 1 µs
2h = 2 µs
3h = 3 µs
4h = 4 µs
5h = 5 µs
6h = 6 µs
7h = 7 µs
8h = 8 µs
9h = 9 µs
Ah = 10 µs
Bh = 11 µs
Ch = 12 µs
Dh = 13 µs
Eh = 14 µs
Fh = 15 µs
26-24
TPWDTH
R/W
0h
Comparator deglitch time
0h = 0 µs
1h = 1 µs
2h = 2 µs
3h = 3 µs
4h = 4 µs
5h = 5 µs
6h = 6 µs
7h = 7 µs
23
RESERVED
R/W
0h
Reserved
22
DGS_HIGH_IND_EN
R/W
0h
Degauss Filter for High Inductance Enable
0h = Disable
1h = Enable
21
RESERVED
R/W
1h
Reserved
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Table 7-24. TRAP_CONFIG2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
20-18
ALIGN_DUTY
R/W
0h
Duty cycle limit during align
0h = 10 %
1h = 15 %
2h = 20 %
3h = 25 %
4h = 30 %
5h = 40 %
6h = 50 %
7h = 100 %
17-16
ZERO_DUTY_HYST
R/W
0h
Duty cycle hysteresis to exit standby
0h = 0 %
1h = 1 %
2h = 2 %
3h = 3 %
15-0
RESERVED
R/W
0h
Reserved
7.7.2 Fault_Configuration Registers
Table 7-25 lists the memory-mapped registers for the Fault_Configuration registers. All register offset addresses
not listed in Table 7-25 should be considered as reserved locations and the register contents should not be
modified.
Table 7-25. FAULT_CONFIGURATION Registers
Offset
Acronym
Register Name
92h
FAULT_CONFIG1
Fault configuration 1
FAULT_CONFIG1 Register (Offset = 92h)
[Reset = 00000000h]
Section
94h
FAULT_CONFIG2
Fault configuration 2
FAULT_CONFIG2 Register (Offset = 94h)
[Reset = 00000000h]
Complex bit access types are encoded to fit into small table cells. Table 7-26 shows the codes that are used for
access types in this section.
Table 7-26. Fault_Configuration Access Type Codes
Access Type
Code
Description
R
Read
W
Write
Read Type
R
Write Type
W
Reset or Default Value
-n
112
Value after reset or the default
value
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7.7.2.1 FAULT_CONFIG1 Register (Offset = 92h) [Reset = 00000000h]
FAULT_CONFIG1 is shown in Figure 7-69 and described in Table 7-27.
Return to the Summary Table.
Register to configure fault settings1
Figure 7-69. FAULT_CONFIG1 Register
31
30
29
PARITY
RESERVED
NO_MTR_DEG_TIME
28
CBC_ILIMIT_MODE
R/W-0h
R/W-0h
R/W-0h
R/W-0h
23
22
21
20
27
19
26
25
18
17
CBC_ILIMIT_M
ODE
LOCK_ILIMIT
LOCK_ILIMIT_MODE
R/W-0h
R/W-0h
R/W-0h
15
14
13
12
11
10
9
LOCK_ILIMIT_
MODE
LOCK_ILIMIT_DEG
CBC_RETRY_PWM_CYC
R/W-0h
R/W-0h
R/W-0h
7
6
5
4
3
2
1
RESERVED
MTR_LCK_MODE
LCK_RETRY
R/W-0h
R/W-0h
R/W-0h
24
16
8
0
Table 7-27. FAULT_CONFIG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
31
PARITY
R/W
0h
Parity bit
30
RESERVED
R/W
0h
Reserved
NO_MTR_DEG_TIME
R/W
0h
No motor detect deglitch time
0h = 1 ms
1h = 10 ms
2h = 25 ms
3h = 50 ms
4h = 100 ms
5h = 250 ms
6h = 500 ms
7h = 1000 ms
29-27
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Table 7-27. FAULT_CONFIG1 Register Field Descriptions (continued)
Bit
114
Field
Type
Reset
Description
26-23
CBC_ILIMIT_MODE
R/W
0h
Cycle by cycle current limit
0h = Automatic recovery next PWM cycle; nFAULT active; driver is in
recirculation mode
1h = Automatic recovery next PWM cycle; nFAULT inactive; driver is
in recirculation mode
2h = Automatic recovery if VSOX < CBC_ILIMIT; nFAULT active;
driver is in recirculation mode (Only available with high-side
modulation)
3h = Automatic recovery if VSOX < CBC_ILIMIT; nFAULT inactive;
driver is in recirculation mode (Only available with high-side
modulation)
4h = Automatic recovery after CBC_RETRY_PWM_CYC; nFAULT
active; driver is in recirculation mode
5h = Automatic recovery after CBC_RETRY_PWM_CYC; nFAULT
inactive; driver is in recirculation mode
6h = VSOX > CBC_ILIMIT is report only but no action is taken
7h = Cycle by Cycle limit is disabled
8h = Cycle by Cycle limit is disabled
9h = Cycle by Cycle limit is disabled
Ah = Cycle by Cycle limit is disabled
Bh = Cycle by Cycle limit is disabled
Ch = Cycle by Cycle limit is disabled
Dh = Cycle by Cycle limit is disabled
Eh = Cycle by Cycle limit is disabled
Fh = Cycle by Cycle limit is disabled
22-19
LOCK_ILIMIT
R/W
0h
Lock detection current limit (Lock detection current limit (A) =
LOCK_ILIMIT / CSA_GAIN)
0h = Reserved
1h = 0.1 V
2h = 0.2 V
3h = 0.3 V
4h = 0.4 V
5h = 0.5 V
6h = 0.6 V
7h = 0.7 V
8h = 0.8 V
9h = 0.9 V
Ah = 1 V
Bh = 1.1 V
Ch = 1.2 V
Dh = 1.3 V
Eh = 1.4 V
Fh = 1.5 V
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Table 7-27. FAULT_CONFIG1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
18-15
LOCK_ILIMIT_MODE
R/W
0h
Lock detection current limit mode
0h = Ilimit lock detection causes latched fault; nFAULT active; Gate
driver is tristated
1h = Ilimit lock detection causes latched fault; nFAULT active; Gate
driver is in recirculation mode
2h = Ilimit lock detection causes latched fault; nFAULT active; Gate
driver is in high-side brake mode (All high-side FETs are turned ON)
3h = Ilimit lock detection causes latched fault; nFAULT active; Gate
driver is in low-side brake mode (All low-side FETs are turned ON)
4h = Automatic recovery after tLCK_RETRY; Gate driver is tristated
5h = Automatic recovery after tLCK_RETRY; Gate driver is in
recirculation mode
6h = Automatic recovery after tLCK_RETRY; Gate driver is in highside brake mode (All high-side FETs are turned ON)
7h = Automatic recovery after tLCK_RETRY; Gate driver is in lowside brake mode (All low-side FETs are turned ON)
8h = Ilimit lock detection is in report only but no action is taken
9h = Ilimit lock detection is disabled
Ah = Ilimit lock detection is disabled
Bh = Ilimit lock detection is disabled
Ch = Ilimit lock detection is disabled
Dh = Ilimit lock detection is disabled
Eh = Ilimit lock detection is disabled
Fh = Ilimit lock detection is disabled
14-11
LOCK_ILIMIT_DEG
R/W
0h
Lock detection current limit deglitch time
0h = 1 ms
1h = 2 ms
2h = 5 ms
3h = 10 ms
4h = 25 ms
5h = 50 ms
6h = 75 ms
7h = 100 ms
8h = 250 ms
9h = 500 ms
Ah = 1 s
Bh = 2.5 s
Ch = 5 s
Dh = 10 s
Eh = 25 s
Fh = 50 s
10-8
CBC_RETRY_PWM_CYC R/W
0h
Number of PWM cycles for CBC current limit to retry
0h = 0
1h = 1
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6
7h = 7
RESERVED
0h
Reserved
7
R/W
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Table 7-27. FAULT_CONFIG1 Register Field Descriptions (continued)
116
Bit
Field
Type
Reset
Description
6-3
MTR_LCK_MODE
R/W
0h
Motor lock mode
0h = Motor lock detection causes latched fault; nFAULT active; Gate
driver is tristated
1h = Motor lock detection causes latched fault; nFAULT active; Gate
driver is in recirculation mode
2h = Motor lock detection causes latched fault; nFAULT active; Gate
driver is in high-side brake mode (All high-side FETs are turned ON)
3h = Motor lock detection causes latched fault; nFAULT active; Gate
driver is in low-side brake mode (All low-side FETs are turned ON)
4h = Automatic recovery after tLCK_RETRY; Gate driver is tristated
5h = Automatic recovery after tLCK_RETRY; Gate driver is in
recirculation mode
6h = Automatic recovery after tLCK_RETRY; Gate driver is in highside brake mode (All high-side FETs are turned ON)
7h = Automatic recovery after tLCK_RETRY; Gate driver is in lowside brake mode (All low-side FETs are turned ON)
8h = Motor lock detection is in report only but no action is taken
9h = Motor lock detection is disabled
Bh = Motor lock detection is disabled
Ch = Motor lock detection is disabled
Dh = Motor lock detection is disabled
Eh = Motor lock detection is disabled
Fh = Motor lock detection is disabled
2-0
LCK_RETRY
R/W
0h
Lock retry time
0h = 100 ms
1h = 500 ms
2h = 1000 ms
3h = 2000 ms
4h = 3000 ms
5h = 5000 ms
6h = 7500 ms
7h = 10000 ms
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7.7.2.2 FAULT_CONFIG2 Register (Offset = 94h) [Reset = 00000000h]
FAULT_CONFIG2 is shown in Figure 7-70 and described in Table 7-28.
Return to the Summary Table.
Register to configure fault settings2
Figure 7-70. FAULT_CONFIG2 Register
31
30
29
28
PARITY
LOCK1_EN
LOCK2_EN
LOCK3_EN
27
LOCK_ABN_SPEED
26
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
23
22
21
20
19
18
LOSS_SYNC_TIMES
NO_MTR_THR
R/W-0h
R/W-0h
15
14
13
12
25
11
24
17
16
MAX_VM_MOD MAX_VM_MOT
E
OR
10
R/W-0h
R/W-0h
9
8
MAX_VM_MOTOR
MIN_VM_MOD
E
MIN_VM_MOTOR
AUTO_RETRY_TIMES
R/W-0h
R/W-0h
R/W-0h
R/W-0h
7
6
5
4
3
2
1
0
AUTO_RETRY_
TIMES
LOCK_MIN_SPEED
ABN_LOCK_SPD_RATIO
ZERO_DUTY_THR
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 7-28. FAULT_CONFIG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
31
PARITY
R/W
0h
Parity bit
30
LOCK1_EN
R/W
0h
Lock 1 (Abnormal Speed) Enable
0h = Disable
1h = Enable
29
LOCK2_EN
R/W
0h
Lock 2 (Loss of Sync) Enable
0h = Disable
1h = Enable
28
LOCK3_EN
R/W
0h
Lock 3 (No Motor) Enable
0h = Disable
1h = Enable
LOCK_ABN_SPEED
R/W
0h
Abnormal speed lock threshold
0h = 250 Hz
1h = 500 Hz
2h = 750 Hz
3h = 1000 Hz
4h = 1250 Hz
5h = 1500 Hz
6h = 1750 Hz
7h = 2000 Hz
8h = 2250 Hz
9h = 2500 Hz
Ah = 2750 Hz
Bh = 3000 Hz
Ch = 3250 Hz
Dh = 3500 Hz
Eh = 3750 Hz
Fh = 4000 Hz
27-24
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Table 7-28. FAULT_CONFIG2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
23-21
LOSS_SYNC_TIMES
R/W
0h
Number of times sync lost for loss of sync lock fault
0h = Trigger after losing sync 2 times
1h = Trigger after losing sync 3 times
2h = Trigger after losing sync 4 times
3h = Trigger after losing sync 5 times
4h = Trigger after losing sync 6 times
5h = Trigger after losing sync 7 times
6h = Trigger after losing sync 8 times
7h = Trigger after losing sync 9 times
20-18
NO_MTR_THR
R/W
0h
No motor lock current threshold (No motor lock current threshold (A)
= NO_MTR_THR / CSA_GAIN)
0h = 0.005 V
1h = 0.0075 V
2h = 0.010 V
3h = 0.0125 V
4h = 0.020 V
5h = 0.025 V
6h = 0.030 V
7h = 0.04 V
MAX_VM_MODE
R/W
0h
0h = Latch on Overvoltage
1h = Automatic clear if voltage in bounds
MAX_VM_MOTOR
R/W
0h
Maximum voltage for running motor
0h = No Limit
1h = 20.0 V
2h = 25.0 V
3h = 30.0 V
4h = 35.0 V
5h = 40.0 V
6h = Unused
7h = Unused
MIN_VM_MODE
R/W
0h
0h = Latch on Undervoltage
1h = Automatic clear if voltage in bounds
MIN_VM_MOTOR
R/W
0h
Minimum voltage for running motor
0h = No Limit
1h = 6.0 V
2h = 7.0 V
3h = 8.0 V
4h = 9.0 V
5h = 10.0 V
6h = 12.0 V
7h = 15.0 V
9-7
AUTO_RETRY_TIMES
R/W
0h
Number of automatic retry attempts
0h = No Limit
1h = 2
2h = 3
3h = 5
4h = 7
5h = 10
6h = 15
7h = 20
6-4
LOCK_MIN_SPEED
R/W
0h
Speed below which lock fault is triggered
0h = 0.5 Hz
1h = 1 Hz
2h = 2 Hz
3h = 3 Hz
4h = 5 Hz
5h = 10 Hz
6h = 15 Hz
7h = 25 Hz
17
16-14
13
12-10
118
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Table 7-28. FAULT_CONFIG2 Register Field Descriptions (continued)
Bit
Field
Reset
Description
3-2
ABN_LOCK_SPD_RATIO R/W
Type
0h
Ratio of electrical speed between two consecutive cycles above
which abnormal speed lock fault is triggered
0h = 2
1h = 4
2h = 6
3h = 8
1-0
ZERO_DUTY_THR
0h
Duty cycle below which target speed is zero
0h = 1%
1h = 1.5%
2h = 2.0%
3h = 2.5%
R/W
7.7.3 Hardware_Configuration Registers
Table 7-29 lists the memory-mapped registers for the Hardware_Configuration registers. All register offset
addresses not listed in Table 7-29 should be considered as reserved locations and the register contents should
not be modified.
Table 7-29. HARDWARE_CONFIGURATION Registers
Offset
Acronym
Register Name
A4h
PIN_CONFIG1
Hardware pin configuration
PIN_CONFIG1 Register (Offset = A4h)
[Reset = 00000000h]
Section
A6h
PIN_CONFIG2
Hardware pin configuration
PIN_CONFIG2 Register (Offset = A6h)
[Reset = 00000000h]
A8h
DEVICE_CONFIG
Device configuration
DEVICE_CONFIG Register (Offset = A8h)
[Reset = 00000000h]
Complex bit access types are encoded to fit into small table cells. Table 7-30 shows the codes that are used for
access types in this section.
Table 7-30. Hardware_Configuration Access Type
Codes
Access Type
Code
Description
R
Read
W
Write
Read Type
R
Write Type
W
Reset or Default Value
-n
Value after reset or the default
value
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7.7.3.1 PIN_CONFIG1 Register (Offset = A4h) [Reset = 00000000h]
PIN_CONFIG1 is shown in Figure 7-71 and described in Table 7-31.
Return to the Summary Table.
Register to configure hardware pins
Figure 7-71. PIN_CONFIG1 Register
31
30
29
28
27
PARITY
DACOUT1_VAR_ADDR
R/W-0h
R/W-0h
23
22
15
21
20
19
26
25
24
18
17
16
DACOUT1_VAR_ADDR
DACOUT2_VAR_ADDR
R/W-0h
R/W-0h
14
13
12
11
10
9
8
2
1
0
DACOUT2_VAR_ADDR
R/W-0h
7
6
5
4
3
DACOUT2_VA
R_ADDR
BRAKE_INPUT
DIR_INPUT
SPD_CTRL_MODE
ALARM_PIN_E
N
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 7-31. PIN_CONFIG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
31
PARITY
R/W
0h
Parity bit
30-19
DACOUT1_VAR_ADDR
R/W
0h
12-bit address of variable to be monitored
18-7
DACOUT2_VAR_ADDR
R/W
0h
12-bit address of variable to be monitored
6-5
BRAKE_INPUT
R/W
0h
Brake input configuration
0h = Hardware Pin BRAKE
1h = Overwrite Hardware pin with Active Brake
2h = Overwrite Hardware pin with brake functionality disabled
3h = Reserved
4-3
DIR_INPUT
R/W
0h
Direction input configuration
0h = Hardware Pin DIR
1h = Overwrite Hardware pin with clockwise rotation OUTA-OUTBOUTC
3h = Reserved
2-1
SPD_CTRL_MODE
R/W
0h
Speed input configuration
0h = Analog mode
1h = PWM mode
2h = 0x2
3h = Frequency mode
ALARM_PIN_EN
R/W
0h
Alarm Pin GPIO configuration
0h = Disabled (Hi-Z)
1h = Enabled
0
120
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7.7.3.2 PIN_CONFIG2 Register (Offset = A6h) [Reset = 00000000h]
PIN_CONFIG2 is shown in Figure 7-72 and described in Table 7-32.
Return to the Summary Table.
Register to configure hardware pins
Figure 7-72. PIN_CONFIG2 Register
31
30
28
27
PARITY
DAC_SOX_CONFIG
RESERVED
DAC_CONFIG
I2C_TARGET_ADDR
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
20
19
23
29
22
15
21
26
25
18
17
16
I2C_TARGET_ADDR
SLEEP_TIME
EXT_WD_EN
EXT_WD_INPU
T
R/W-0h
R/W-0h
R/W-0h
R/W-0h
9
8
14
13
12
11
10
EXT_WD_FAUL
T
EXT_WD_FREQ
FG_PIN_FAULT_CONFIG
RESERVED
R/W-0h
R/W-0h
R/W-0h
R/W-0h
7
24
6
5
4
3
2
1
0
RESERVED
R/W-0h
Table 7-32. PIN_CONFIG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
31
PARITY
R/W
0h
Parity bit
DAC_SOX_CONFIG
R/W
0h
Pin 36 configuration
0h = DACOUT2
1h = SOA
2h = SOB
3h = SOC
28
RESERVED
R/W
0h
Reserved
27
DAC_CONFIG
R/W
0h
Pin 37 and pin 38 configuration
0h = Reserved
1h = Pin 37 as DACOUT2 and pin 38 as DACOUT1
26-20
I2C_TARGET_ADDR
R/W
0h
I2C target address
19-18
SLEEP_TIME
R/W
0h
Sleep Time
0h = Check low for 50 µs
1h = Check low for 200 µs
2h = Check low for 20 ms
3h = Check low for 200 ms
17
EXT_WD_EN
R/W
0h
Enable external watchdog
0h = Disable
1h = Enable
16
EXT_WD_INPUT
R/W
0h
External watchdog source
0h = I2C
1h = GPIO
15
EXT_WD_FAULT
R/W
0h
External watchdog fault mode
0h = Report only
1h = Latched fault with Hi-Z outputs
14-13
EXT_WD_FREQ
R/W
0h
External watchdog frequency
0h = 10Hz
1h = 5Hz
2h = 2Hz
3h = 1Hz
30-29
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Table 7-32. PIN_CONFIG2 Register Field Descriptions (continued)
Bit
122
Field
Reset
Description
12-11
FG_PIN_FAULT_CONFIG R/W
Type
0h
Fault on FG Pin Configuration
0h = FG continues to toggle till motor stops
1h = FG in Hi-Z state, pulled up externally
2h = FG pulled Low
3h = Reserved
10-0
RESERVED
0h
Reserved
R/W
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7.7.3.3 DEVICE_CONFIG Register (Offset = A8h) [Reset = 00000000h]
DEVICE_CONFIG is shown in Figure 7-73 and described in Table 7-33.
Return to the Summary Table.
Register to configure device
Figure 7-73. DEVICE_CONFIG Register
31
30
29
28
27
PARITY
INPUT_MAX_FREQUENCY
R/W-0h
R/W-0h
23
22
21
20
19
26
25
24
18
17
16
9
INPUT_MAX_FREQUENCY
R/W-0h
15
14
11
10
RESERVED
SSM_CONFIG
13
RESERVED
12
DEV_MODE
SPD_PWM_RA
NGE_SELECT
CLK_SEL
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
3
2
5
4
8
7
6
RESERVED
EXT_CLK_EN
EXT_CLK_CONFIG
RESERVED
1
R/W-0h
R/W-0h
R/W-0h
R/W-0h
0
Table 7-33. DEVICE_CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
31
PARITY
R/W
0h
Parity bit
INPUT_MAX_FREQUENC R/W
Y
0h
Maximum frequency (in Hz) for frequency based speed input
15
RESERVED
R/W
0h
Reserved
14
SSM_CONFIG
R/W
0h
SSM enable
0h = Enable
1h = Disable
13-12
RESERVED
R/W
0h
Reserved
11
DEV_MODE
R/W
0h
Device mode select
0h = Standby mode
1h = Sleep mode
10
SPD_PWM_RANGE_SEL R/W
ECT
0h
PWM frequency range select
0h = 325 Hz to 100 kHz speed PWM input
1h = 10 Hz to 325 Hz speed PWM input
9-8
CLK_SEL
R/W
0h
Clock source
0h = Internal Oscillator
1h = Reserved
2h = Reserved
3h = External Clock input
7
RESERVED
R/W
0h
Reserved
6
EXT_CLK_EN
R/W
0h
External clock enable
0h = Disable
1h = Enable
30-16
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Table 7-33. DEVICE_CONFIG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5-3
EXT_CLK_CONFIG
R/W
0h
External clock frequency
0h = 8 kHz
1h = 16 kHz
2h = 32 kHz
3h = 64 kHz
4h = 128 kHz
5h = 256 kHz
6h = 512 kHz
7h = 1024 kHz
2-0
RESERVED
R/W
0h
Reserved
7.7.4 Gate_Driver_Configuration Registers
Table 7-34 lists the memory-mapped registers for the Gate_Driver_Configuration registers. All register offset
addresses not listed in Table 7-34 should be considered as reserved locations and the register contents should
not be modified.
Table 7-34. GATE_DRIVER_CONFIGURATION Registers
Offset
Acronym
Register Name
ACh
GD_CONFIG1
Gate driver configuration 1
GD_CONFIG1 Register (Offset = ACh)
[Reset = 00228000h]
Section
AEh
GD_CONFIG2
Gate driver configuration 2
GD_CONFIG2 Register (Offset = AEh)
[Reset = 01200000h]
Complex bit access types are encoded to fit into small table cells. Table 7-35 shows the codes that are used for
access types in this section.
Table 7-35. Gate_Driver_Configuration Access Type
Codes
Access Type
Code
Description
R
Read
W
Write
Read Type
R
Write Type
W
Reset or Default Value
-n
124
Value after reset or the default
value
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7.7.4.1 GD_CONFIG1 Register (Offset = ACh) [Reset = 00228000h]
GD_CONFIG1 is shown in Figure 7-74 and described in Table 7-36.
Return to the Summary Table.
Register to configure gated driver settings1
Figure 7-74. GD_CONFIG1 Register
31
30
29
28
27
26
25
24
PARITY
RESERVED
RESERVED
SLEW_RATE
RESERVED
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
23
22
21
20
19
18
17
16
CLR_FLT
RESERVED
RESERVED
RESERVED
OVP_SEL
OVP_EN
RESERVED
OTW_REP
R/W-0h
R/W-0h
R/W-1h
R/W-0h
R/W-0h
R/W-0h
R/W-1h
R/W-0h
13
12
9
8
15
14
11
10
RESERVED
RESERVED
OCP_DEG
OCP_RETRY
OCP_LVL
OCP_MODE
R/W-1h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
7
6
3
2
BEMF_THR
RESERVED
EN_ASR
EN_AAR
CSA_GAIN
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
5
4
ADCOMP_TH_ ADCOMP_TH_
LS
HS
R/W-0h
R/W-0h
1
0
Table 7-36. GD_CONFIG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
31
PARITY
R/W
0h
Parity bit
30-29
RESERVED
R/W
0h
Reserved
28
RESERVED
R/W
0h
Reserved
27-26
SLEW_RATE
R/W
0h
Slew rate
0h = 25 V/µs
1h = 50 V/µs
2h = 125 V/µs
3h = 200 V/µs
25-24
RESERVED
R/W
0h
Reserved
23
CLR_FLT
R/W
0h
Clear fault
0h = No clear fault command is issued
1h = To clear the latched fault bits. This bit automatically resets after
being written.
22
RESERVED
R/W
0h
Reserved
21
RESERVED
R/W
1h
Reserved
20
RESERVED
R/W
0h
Reserved
19
OVP_SEL
R/W
0h
Overvoltage protection level
0h = VM overvoltage level is 34-V
1h = VM overvoltage level is 22-V
18
OVP_EN
R/W
0h
Overvoltage protection enable
0h = Disable
1h = Enable
17
RESERVED
R/W
1h
Reserved
16
OTW_REP
R/W
0h
Overtemperature warning reporting on nFAULT
0h = Over temperature reporting on nFAULT is disabled
1h = Over temperature reporting on nFAULT is enabled
15
RESERVED
R/W
1h
Reserved
14
RESERVED
R/W
0h
Reserved
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Table 7-36. GD_CONFIG1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
OCP_DEG
R/W
0h
OCP deglitch time
0h = 0.2 µs
1h = 0.6 µs
2h = 1.2 µs
3h = 1.6 µs
11
OCP_RETRY
R/W
0h
OCP retry time
0h = 5 ms
1h = 500 ms
10
OCP_LVL
R/W
0h
OCP level
0h = 9 A (Typical)
1h = 13 A (Typical)
9-8
OCP_MODE
R/W
0h
OCP fault mode
0h = Overcurrent causes a latched fault
1h = Overcurrent causes an automatic retrying fault
2h = Overcurrent is report only but no action is taken
3h = Overcurrent is not reported and no action is taken
7
BEMF_THR
R/W
0h
BEMF comparator threshold
0h = BEMF comparator threshold is 20 mV
1h = BEMF comparator threshold is 100 mV
6
RESERVED
R/W
0h
Reserved
5
ADCOMP_TH_LS
R/W
0h
Active demag comparator threshold for low-side
0h = 100 mA
1h = 150 mA
4
ADCOMP_TH_HS
R/W
0h
Active demag comparator threshold for high-side
0h = 100 mA
1h = 150 mA
3
EN_ASR
R/W
0h
Active synchronous rectification enable
0h = Disable
1h = Enable
2
EN_AAR
R/W
0h
Active asynchronous rectification enable
0h = Disable
1h = Enable
CSA_GAIN
R/W
0h
Current Sense Amplifier (CSA) Gain
0h = 0.24 V/A
1h = 0.48 V/A
2h = 0.96 V/A
3h = 1.92 V/A
13-12
1-0
126
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7.7.4.2 GD_CONFIG2 Register (Offset = AEh) [Reset = 01200000h]
GD_CONFIG2 is shown in Figure 7-75 and described in Table 7-37.
Return to the Summary Table.
Register to configure gated driver settings2
Figure 7-75. GD_CONFIG2 Register
31
30
29
25
24
PARITY
DELAY_COMP
_EN
28
TARGET_DELAY
RESERVED
BUCK_PS_DIS
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-1h
23
22
17
16
21
27
20
19
26
18
BUCK_CL
BUCK_SEL
RESERVED
RESERVED
R/W-0h
R/W-1h
R/W-0h
R/W-0h
15
14
13
12
11
10
9
8
3
2
1
0
RESERVED
R/W-0h
7
6
5
4
RESERVED
R/W-0h
Table 7-37. GD_CONFIG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
31
PARITY
R/W
0h
Parity bit
30
DELAY_COMP_EN
R/W
0h
Driver delay compensation enable
0h = Disable
1h = Enable
TARGET_DELAY
R/W
0h
Target delay
0h = Automatic based on slew rate
1h = 0.4 µs
2h = 0.6 µs
3h = 0.8 µs
4h = 1 µs
5h = 1.2 µs
6h = 1.4 µs
7h = 1.6 µs
8h = 1.8 µs
9h = 2 µs
Ah = 2.2 µs
Bh = 2.4 µs
Ch = 2.6 µs
Dh = 2.8 µs
Eh = 3 µs
Fh = 3.2 µs
25
RESERVED
R/W
0h
Reserved
24
BUCK_PS_DIS
R/W
1h
Buck power sequencing disable
0h = Buck power sequencing is enabled
1h = Buck power sequencing is disabled
23
BUCK_CL
R/W
0h
Buck current limit
0h = 600 mA
1h = 150 mA
BUCK_SEL
R/W
1h
Buck voltage selection
0h = Buck voltage is 3.3 V
1h = Buck voltage is 5.0 V
2h = Buck voltage is 4.0 V
3h = Buck voltage is 5.7 V
29-26
22-21
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Table 7-37. GD_CONFIG2 Register Field Descriptions (continued)
128
Bit
Field
Type
Reset
Description
20
RESERVED
R/W
0h
Reserved
19-0
RESERVED
R/W
0h
Reserved
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7.8 RAM (Volatile) Register Map
7.8.1 Fault_Status Registers
Table 7-38 lists the memory-mapped registers for the Fault_Status registers. All register offset addresses not
listed in Table 7-38 should be considered as reserved locations and the register contents should not be modified.
Table 7-38. FAULT_STATUS Registers
Offset
Acronym
Register Name
Section
E0h
GATE_DRIVER_FAULT_STATUS Fault Status Register
GATE_DRIVER_FAULT_STATUS Register
(Offset = E0h) [Reset = 00000000h]
E2h
CONTROLLER_FAULT_STATUS Fault Status Register
CONTROLLER_FAULT_STATUS Register
(Offset = E2h) [Reset = 00000000h]
Complex bit access types are encoded to fit into small table cells. Table 7-39 shows the codes that are used for
access types in this section.
Table 7-39. Fault_Status Access Type Codes
Access Type
Code
Description
R
Read
Read Type
R
Reset or Default Value
-n
Value after reset or the default
value
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7.8.1.1 GATE_DRIVER_FAULT_STATUS Register (Offset = E0h) [Reset = 00000000h]
GATE_DRIVER_FAULT_STATUS is shown in Figure 7-76 and described in Table 7-40.
Return to the Summary Table.
Status of various faults
Figure 7-76. GATE_DRIVER_FAULT_STATUS Register
31
30
29
28
27
26
25
24
DRIVER_FAUL
T
BK_FLT
RESERVED
OCP
NPOR
OVP
OT
RESERVED
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
23
22
21
20
19
18
17
16
OTW
TSD
OCP_HC
OCP_LC
OCP_HB
OCP_LB
OCP_HA
OCP_LA
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
15
14
13
12
11
10
9
8
RESERVED
OTP_ERR
BUCK_OCP
BUCK_UV
VCP_UV
RESERVED
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
7
6
5
4
3
2
1
0
RESERVED
R-0h
Table 7-40. GATE_DRIVER_FAULT_STATUS Register Field Descriptions
130
Bit
Field
Type
Reset
Description
31
DRIVER_FAULT
R
0h
Logic OR of driver fault registers
0h = No Gate Driver fault condition is detected
1h = Gate Driver fault condition is detected
30
BK_FLT
R
0h
Buck fault
0h = No buck regulator fault condition is detected
1h = Buck regulator fault condition is detected
29
RESERVED
R
0h
Reserved
28
OCP
R
0h
Overcurrent protection status
0h = No overcurrent condition is detected
1h = Overcurrent condition is detected
27
NPOR
R
0h
Supply power on reset
0h = Power on reset condition is detected on VM
1h = No power-on-reset condition is detected on VM
26
OVP
R
0h
Supply overvoltage protection status
0h = No overvoltage condition is detected on VM
1h = Overvoltage condition is detected on VM
25
OT
R
0h
Overtemperature fault status
0h = No overtemperature warning / shutdown is detected
1h = Overtemperature warning / shutdown is detected
24
RESERVED
R
0h
Reserved
23
OTW
R
0h
Overtemperature warning status
0h = No overtemperature warning is detected
1h = Overtemperature warning is detected
22
TSD
R
0h
Overtemperature shutdown status
0h = No overtemperature shutdown is detected
1h = Overtemperature shutdown is detected
21
OCP_HC
R
0h
Overcurrent status on high-side switch of OUTC
0h = No overcurrent detected on high-side switch of OUTC
1h = Overcurrent detected on high-side switch of OUTC
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Table 7-40. GATE_DRIVER_FAULT_STATUS Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
20
OCP_LC
R
0h
Overcurrent status on low-side switch of OUTC
0h = No overcurrent detected on low-side switch of OUTC
1h = Overcurrent detected on low-side switch of OUTC
19
OCP_HB
R
0h
Overcurrent status on high-side switch of OUTB
0h = No overcurrent detected on high-side switch of OUTB
1h = Overcurrent detected on high-side switch of OUTB
18
OCP_LB
R
0h
Overcurrent status on low-side switch of OUTB
0h = No overcurrent detected on low-side switch of OUTB
1h = Overcurrent detected on low-side switch of OUTB
17
OCP_HA
R
0h
Overcurrent status on high-side switch of OUTA
0h = No overcurrent detected on high-side switch of OUTA
1h = Overcurrent detected on high-side switch of OUTA
16
OCP_LA
R
0h
Overcurrent status on low-side switch of OUTA
0h = No overcurrent detected on low-side switch of OUTA
1h = Overcurrent detected on low-side switch of OUTA
15
RESERVED
R
0h
Reserved
14
OTP_ERR
R
0h
One-time programmable (OTP) error
0h = No OTP error is detected
1h = OTP Error is detected
13
BUCK_OCP
R
0h
Buck regulator overcurrent status
0h = No buck regulator overcurrent is detected
1h = Buck regulator overcurrent is detected
12
BUCK_UV
R
0h
Buck regulator undervoltage status
0h = No buck regulator undervoltage is detected
1h = Buck regulator undervoltage is detected
11
VCP_UV
R
0h
Charge pump undervoltage status
0h = No charge pump undervoltage is detected
1h = Charge pump undervoltage is detected
RESERVED
R
0h
Reserved
10-0
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7.8.1.2 CONTROLLER_FAULT_STATUS Register (Offset = E2h) [Reset = 00000000h]
CONTROLLER_FAULT_STATUS is shown in Figure 7-77 and described in Table 7-41.
Return to the Summary Table.
Status of various faults
Figure 7-77. CONTROLLER_FAULT_STATUS Register
31
30
CONTROLLER
_FAULT
RESERVED
R-0h
R-0h
29
28
27
26
25
IPD_FREQ_FA IPD_T1_FAULT IPD_T2_FAULT
ULT
R-0h
R-0h
24
RESERVED
R-0h
R-0h
23
22
21
20
19
18
ABN_SPEED
LOSS_OF_SYN
C
NO_MTR
MTR_LCK
CBC_ILIMIT
LOCK_ILIMIT
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
15
14
13
12
11
10
9
8
2
1
0
RESERVED
STL_EN
STL_STATUS
APP_RESET
R-0h
R-0h
R-0h
R-0h
EXT_WD_TIME
OUT
RESERVED
R-0h
R-0h
7
6
5
4
3
17
16
MTR_UNDER_ MTR_OVER_V
VOLTAGE
OLTAGE
Table 7-41. CONTROLLER_FAULT_STATUS Register Field Descriptions
132
Bit
Field
Type
Reset
Description
31
CONTROLLER_FAULT
R
0h
Logic OR of controller fault registers
0h = No controller fault condition is detected
1h = Controller fault condition is detected
30
RESERVED
R
0h
Reserved
29
IPD_FREQ_FAULT
R
0h
Indicates IPD frequency fault
0h = No IPD frequency fault detected
1h = IPD frequency fault detected
28
IPD_T1_FAULT
R
0h
Indicates IPD T1 fault
0h = No IPD T1 fault detected
1h = IPD T1 fault detected
27
IPD_T2_FAULT
R
0h
Indicates IPD T2 fault
0h = No IPD T2 fault detected
1h = IPD T2 fault detected
26-24
RESERVED
R
0h
Reserved
23
ABN_SPEED
R
0h
Indicates abnormal speed motor lock condition
0h = No abnormal speed fault detected
1h = Abnormal Speed fault detected
22
LOSS_OF_SYNC
R
0h
Indicates sync lost motor lock condition
0h = No sync lost fault detected
1h = Sync lost fault detected
21
NO_MTR
R
0h
Indicates no motor fault
0h = No motor fault not detected
1h = No motor fault detected
20
MTR_LCK
R
0h
Indicates when one of the motor lock is triggered
0h = Motor lock fault not detected
1h = Motor lock fault detected
19
CBC_ILIMIT
R
0h
Indicates CBC current limit fault
0h = No CBC fault detected
1h = CBC fault detected
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Table 7-41. CONTROLLER_FAULT_STATUS Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
18
LOCK_ILIMIT
R
0h
Indicates lock detection current limit fault
0h = No lock current limit fault detected
1h = Lock current limit fault detected
17
MTR_UNDER_VOLTAGE
R
0h
Indicates motor undervoltage fault
0h = No motor undervoltage detected
1h = Motor undervoltage detected
16
MTR_OVER_VOLTAGE
R
0h
Indicates motor overvoltage fault
0h = No motor overvoltage detected
1h = Motor overvoltage detected
15
EXT_WD_TIMEOUT
R
0h
Indicates external watchdog timeout fault
0h = No external watchdog timeout fault detected
1h = External watchdog timeout fault detected
14-3
RESERVED
R
0h
Reserved
2
STL_EN
R
0h
Indicates STL is enabled in EEPROM
0h = STL Disable
1h = STL Enable
1
STL_STATUS
R
0h
Indicates STL success criteria Pass = 1b; Fail = 0b
0h = STL Fail
1h = STL Pass
0
APP_RESET
R
0h
App reset
0h = App Reset Fail
1h = App Reset Successful
7.8.2 System_Status Registers
Table 7-42 lists the memory-mapped registers for the System_Status registers. All register offset addresses not
listed in Table 7-42 should be considered as reserved locations and the register contents should not be modified.
Table 7-42. SYSTEM_STATUS Registers
Offset
Acronym
Register Name
E4h
SYS_STATUS1
System Status Register1
SYS_STATUS1 Register (Offset = E4h)
[Reset = 00000000h]
Section
EAh
SYS_STATUS2
System Status Register2
SYS_STATUS2 Register (Offset = EAh)
[Reset = 00000000h]
ECh
SYS_STATUS3
System Status Register3
SYS_STATUS3 Register (Offset = ECh)
[Reset = 00000000h]
Complex bit access types are encoded to fit into small table cells. Table 7-43 shows the codes that are used for
access types in this section.
Table 7-43. System_Status Access Type Codes
Access Type
Code
Description
R
Read
Read Type
R
Reset or Default Value
-n
Value after reset or the default
value
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7.8.2.1 SYS_STATUS1 Register (Offset = E4h) [Reset = 00000000h]
SYS_STATUS1 is shown in Figure 7-78 and described in Table 7-44.
Return to the Summary Table.
Status of various system and motor parameters
Figure 7-78. SYS_STATUS1 Register
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
VOLT_MAG
R-0h
23
22
21
20
VOLT_MAG
R-0h
15
14
13
12
SPEED_CMD
R-0h
7
6
5
4
SPEED_CMD
I2C_ENTRY_S
TATUS
R-0h
R-0h
Table 7-44. SYS_STATUS1 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-16
VOLT_MAG
R
0h
Applied DC input voltage (/10 to get DC input voltage in V)
15-1
SPEED_CMD
R
0h
Decoded speed command in PWM/Analog/Freq. mode
(SPEED_CMD (%) = SPEED_CMD/32767 * 100%)
I2C_ENTRY_STATUS
R
0h
Indicates if I2C entry has happened
0h = I2C mode not entered through pin sequence
1h = I2C mode entered through pin sequence
0
134
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7.8.2.2 SYS_STATUS2 Register (Offset = EAh) [Reset = 00000000h]
SYS_STATUS2 is shown in Figure 7-79 and described in Table 7-45.
Return to the Summary Table.
Status of various system and motor parameters
Figure 7-79. SYS_STATUS2 Register
31
30
23
29
27
26
25
24
17
16
RESERVED
STL_FAULT
RESERVED
R-0h
R-0h
R-0h
10
9
8
2
1
0
RESERVED
R-0h
R-0h
22
15
28
STATE
14
21
20
13
19
12
11
18
MOTOR_SPEED
R-0h
7
6
5
4
3
MOTOR_SPEED
R-0h
Table 7-45. SYS_STATUS2 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-28
STATE
R
0h
Current status of state machine; 4-bit value indicating status of state
machine
0h = SYSTEM_IDLE
1h = MOTOR_START
2h = MOTOR_RUN
3h = SYSTEM_INIT
4h = MOTOR_IPD
5h = MOTOR_ALIGN
6h = MOTOR_IDLE
7h = MOTOR_STOP
8h = FAULT
9h = MOTOR_DIRECTION
Ah = HALL_ALIGN
Ch = MOTOR_FREEWHEEL
Dh = MOTOR_DESCEL
Eh = MOTOR_BRAKE
Fh = N/A
27-18
RESERVED
R
0h
Reserved
17
STL_FAULT
R
0h
STL fault status
0h = Pass
1h = Fail
16
RESERVED
R
0h
Reserved
MOTOR_SPEED
R
0h
Speed output (/10 to get motor electrical speed in Hz)
15-0
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7.8.2.3 SYS_STATUS3 Register (Offset = ECh) [Reset = 00000000h]
SYS_STATUS3 is shown in Figure 7-80 and described in Table 7-46.
Return to the Summary Table.
Status of various system and motor parameters
Figure 7-80. SYS_STATUS3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
DC_BUS_CURR
DC_BATT_POW
R-0h
R-0h
4
3
2
1
0
Table 7-46. SYS_STATUS3 Register Field Descriptions
Field
Type
Reset
Description
31-16
Bit
DC_BUS_CURR
R
0h
DC bus current (/256 to get DC bus current in A)
15-0
DC_BATT_POW
R
0h
Battery (input) power (/64 to get battery power in W)
7.8.3 Algo_Control Registers
Table 7-47 lists the memory-mapped registers for the Algo_Control registers. All register offset addresses not
listed in Table 7-47 should be considered as reserved locations and the register contents should not be modified.
Table 7-47. ALGO_CONTROL Registers
Offset
E6h
Acronym
Register Name
Section
ALGO_CTRL1
Algorithm Control Parameters
ALGO_CTRL1 Register (Offset = E6h) [Reset
= 00000000h]
Complex bit access types are encoded to fit into small table cells. Table 7-48 shows the codes that are used for
access types in this section.
Table 7-48. Algo_Control Access Type Codes
Access Type
Code
Description
W
Write
Write Type
W
Reset or Default Value
-n
136
Value after reset or the default
value
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7.8.3.1 ALGO_CTRL1 Register (Offset = E6h) [Reset = 00000000h]
ALGO_CTRL1 is shown in Figure 7-81 and described in Table 7-49.
Return to the Summary Table.
Algorithm Control Parameters
Figure 7-81. ALGO_CTRL1 Register
31
30
29
28
CLR_FLT
CLR_FLT_RET
RY_COUNT
EEPROM_WRITE_ACCESS_KEY
W-0h
W-0h
W-0h
W-0h
22
21
20
EEPROM_WRT EEPROM_REA
D
W-0h
23
27
19
26
25
18
EEPROM_WRITE_ACCESS_KEY
RESERVED
W-0h
W-0h
15
14
13
12
24
17
16
8
11
10
9
3
2
1
RESERVED
W-0h
7
6
5
4
0
RESERVED
EXT_WD_STAT
US_SET
W-0h
W-0h
Table 7-49. ALGO_CTRL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
31
EEPROM_WRT
W
0h
Write the configuration to EEPROM
1h = Write to the EEPROM registers from shadow registers
30
EEPROM_READ
W
0h
Read the default configuration from EEPROM
1h = Read the EEPROM registers to shadow registers
29
CLR_FLT
W
0h
Clears all faults
1h = Clear all the driver and controller faults
28
CLR_FLT_RETRY_COUN W
T
0h
Clears fault retry count
1h = clear the lock fault retry counts
27-20
EEPROM_WRITE_ACCE
SS_KEY
W
0h
EEPROM write access key; 8-bit key to unlock the EEPROM write
command
19-1
RESERVED
W
0h
Reserved
EXT_WD_STATUS_SET
W
0h
Watchdog status to be set by external MCU in I2C watchdog mode
0h = Reset automatically by the MCC
1h = To set the EXT_WD_STATUS_SET
0
7.8.4 Device_Control Registers
Table 7-50 lists the memory-mapped registers for the Device_Control registers. All register offset addresses not
listed in Table 7-50 should be considered as reserved locations and the register contents should not be modified.
Table 7-50. DEVICE_CONTROL Registers
Offset
E8h
Acronym
Register Name
DEVICE_CTRL
Device Control Parameters
Section
DEVICE_CTRL Register (Offset = E8h)
[Reset = 00000000h]
Complex bit access types are encoded to fit into small table cells. Table 7-51 shows the codes that are used for
access types in this section.
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Table 7-51. Device_Control Access Type Codes
Access Type
Code
Description
R
Read
W
Write
Read Type
R
Write Type
W
Reset or Default Value
-n
138
Value after reset or the default
value
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7.8.4.1 DEVICE_CTRL Register (Offset = E8h) [Reset = 00000000h]
DEVICE_CTRL is shown in Figure 7-82 and described in Table 7-52.
Return to the Summary Table.
Device Control Parameters
Figure 7-82. DEVICE_CTRL Register
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
2
1
0
RESERVED
SPEED_CTRL
W-0h
W-0h
23
22
21
20
SPEED_CTRL
W-0h
15
14
13
12
OVERRIDE
RESERVED
W-0h
R-0h
7
6
5
4
3
RESERVED
R-0h
Table 7-52. DEVICE_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
31
RESERVED
W
0h
Reserved
SPEED_CTRL
W
0h
Digital speed command (SPEED_CTRL (%) = SPEED_CTRL/32767
* 100%)
15
OVERRIDE
W
0h
Speed input select for I2C vs speed pin
0h = SPEED_CMD using Analog/Freq/PWM mode
1h = SPEED_CMD using SPD_CTRL[14:0]
14-0
RESERVED
R
0h
Reserved
30-16
7.8.5 Algorithm_Variables Registers
Table 7-53 lists the memory-mapped registers for the Algorithm_Variables registers. All register offset addresses
not listed in Table 7-53 should be considered as reserved locations and the register contents should not be
modified.
Table 7-53. ALGORITHM_VARIABLES Registers
Offset
Acronym
Register Name
Section
40Ch
INPUT_DUTY
Input Duty Cycle
INPUT_DUTY Register (Offset = 40Ch)
[Reset = 00000000h]
4F6h
CURRENT_DUTY
Current Duty Cycle
506h
SET_DUTY
Set Duty Cycle
5B2h
MOTOR_SPEED_PU
Motor Speed in PU
6F4h
DC_BUS_POWER_PU
DC Bus Power in PU
CURRENT_DUTY Register (Offset = 4F6h)
[Reset = 00000000h]
SET_DUTY Register (Offset = 506h) [Reset =
00000000h]
MOTOR_SPEED_PU Register (Offset =
5B2h) [Reset = 00000000h]
DC_BUS_POWER_PU Register (Offset =
6F4h) [Reset = 00000000h]
Complex bit access types are encoded to fit into small table cells. Table 7-54 shows the codes that are used for
access types in this section.
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Table 7-54. Algorithm_Variables Access Type Codes
Access Type
Code
Description
R
Read
Read Type
R
Reset or Default Value
-n
140
Value after reset or the default
value
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7.8.5.1 INPUT_DUTY Register (Offset = 40Ch) [Reset = 00000000h]
INPUT_DUTY is shown in Figure 7-83 and described in Table 7-55.
Return to the Summary Table.
Input duty cycle from SPEED pin or SPEED_CMD (Input duty cycle( in %) = (Measured voltage on DAC pin) / 3V
*100 )
Figure 7-83. INPUT_DUTY Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
INPUT_DUTY
R-0h
Table 7-55. INPUT_DUTY Register Field Descriptions
Bit
31-0
Field
Type
Reset
Description
INPUT_DUTY
R
0h
32-bit value indicating the duty cycle that the user commands Input
duty cycle (in %) = (Input Duty Cycle / 230) * 100
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7.8.5.2 CURRENT_DUTY Register (Offset = 4F6h) [Reset = 00000000h]
CURRENT_DUTY is shown in Figure 7-84 and described in Table 7-56.
Return to the Summary Table.
Current duty cycle (Current duty cycle( in %) = (Measured voltage on DAC pin) / 3V *100 )
Figure 7-84. CURRENT_DUTY Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
CURRENT_DUTY
R-0h
Table 7-56. CURRENT_DUTY Register Field Descriptions
Bit
31-0
142
Field
Type
Reset
Description
CURRENT_DUTY
R
0h
32-bit value indicating the duty cycle that is currently being applied.
Current duty cycle (in %) = (Current Duty Cycle / 230) * 100
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7.8.5.3 SET_DUTY Register (Offset = 506h) [Reset = 00000000h]
SET_DUTY is shown in Figure 7-85 and described in Table 7-57.
Return to the Summary Table.
Target duty cycle (Set duty cycle( in %) = (Measured voltage on DAC pin) / 3V *100 )
Figure 7-85. SET_DUTY Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
SET_DUTY
R-0h
Table 7-57. SET_DUTY Register Field Descriptions
Bit
31-0
Field
Type
Reset
Description
SET_DUTY
R
0h
32-bit value indicating the duty cycle that the FW wants. Set duty
cycle (in %) = (Set Duty Cycle / 230) * 100
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7.8.5.4 MOTOR_SPEED_PU Register (Offset = 5B2h) [Reset = 00000000h]
MOTOR_SPEED_PU is shown in Figure 7-86 and described in Table 7-58.
Return to the Summary Table.
Motor speed in PU (Motor speed (in Hz) = (Measured voltage on DAC pin) / 3V * Maximum speed (in Hz))
Maximum speed (in Hz) = MAX_SPEED/16
Figure 7-86. MOTOR_SPEED_PU Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
MOTOR_SPEED_PU
R-0h
Table 7-58. MOTOR_SPEED_PU Register Field Descriptions
Bit
31-0
144
Field
Type
Reset
Description
MOTOR_SPEED_PU
R
0h
32-bit value indicating the speed of the motor. Motor speed (in Hz) =
(Motor Speed in PU / 230) * (MAX_SPEED / 16)
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7.8.5.5 DC_BUS_POWER_PU Register (Offset = 6F4h) [Reset = 00000000h]
DC_BUS_POWER_PU is shown in Figure 7-87 and described in Table 7-59.
Return to the Summary Table.
DC bus power in PU (DC bus power( in W) = (Measured voltage on DAC pin) / 3V * Maximum power(in W))
Maximum power (in W) = MAX_POWER/4
Figure 7-87. DC_BUS_POWER_PU Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DC_BUS_POWER_PU
R-0h
Table 7-59. DC_BUS_POWER_PU Register Field Descriptions
Bit
31-0
Field
Type
Reset
Description
DC_BUS_POWER_PU
R
0h
32-bit value indicating the power drawn by the motor. DC Bus Power
(in W) = (DC Bus Power in PU / 230) * (MAX_POWER / 4)
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The MCT8315A device is used in sensorless 3-phase BLDC motor control. The driver provides a high
performance, high-reliability, flexible solution for robotic vacuum, fuel pumps, automotive fans and blowers,
medical CPAP blowers etc., The following section shows a common application of the MCT8315A device.
8.2 Typical Applications
Figure 8-1 shows the typical schematic of MCT8315A.
VVM
1 µF
47 nF
CPL
CPH
CP
0.1 µF
+
>10 µF
VM
SPEED/WAKE (PWM/Analog/Freq)
AVDD
CAVDD
1 µF
AGND
DRVOFF
DVDD
BRAKE
CDVDD
2.2 µF
AGND
DIR
EXT_CLK
Optional
Control
Interface
EXT_WD
LBK
ALARM
Replace resistor (RBK) with
inductor (LBK) for larger
external load or to reduce
power dissipa on
SW_BK
RBK
MCT8315A
External
Load
CBK
GND_BK
DACOUT1
DACOUT2
SOX
FB_BK
AVDD or EXT SUPPLY
OUTA
RnFAULT
RFG
FG
nFAULT
OUTB
AVDD or EXT SUPPLY
RSCL
RSDA
Optional
Serial
Interface
OUTC
SDA
I2C
SCL
PGND
Figure 8-1. Primary Application Schematic
Table 8-1 lists the recommended values of the external components for MCT8315A.
Table 8-1. MCT8315A External Components
146
COMPONENTS
PIN 1
PIN 2
RECOMMENDED
CVM1
VM
PGND
X5R or X7R, 0.1-µF, TI recommends a capacitor
voltage rating at least twice the normal operating
voltage of the device
CVM2
VM
PGND
≥ 10-µF, TI recommends a capacitor voltage rating at
least twice the normal operating voltage of the device
CCP
CP
VM
X5R or X7R, 16-V, 1-µF capacitor
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Table 8-1. MCT8315A External Components (continued)
COMPONENTS
PIN 1
PIN 2
RECOMMENDED
CFLY
CPH
CPL
X5R or X7R, 47-nF, TI recommends a capacitor
voltage rating at least twice the normal operating
voltage of the pin
CAVDD
AVDD
AGND
X5R or X7R, 1-µF, ≥ 6.3-V. In order for AVDD to
accurately regulate output voltage, capacitor should
have effective capacitance between 0.7-µF to 1.3-µF
at 3.3-V across operating temperature.
CDVDD
DVDD
DGND
X5R or X7R, 2.2-µF, ≥ 6.3-V. In order for DVDD to
accurately regulate output voltage, capacitor should
have effective capacitance between 1.1-µF to 2.5-µF
at 1.5-V across operating temperature.
CBK
FB_BK
GND_BK
X5R or X7R, buck-output rated capacitor
LBK
SW_BK
FB_BK
Buck-output inductor
RFG
1.8 to 5-V Supply
FG
5.1-kΩ, Pull-up resistor
RnFAULT
1.8 to 5-V Supply
nFAULT
5.1-kΩ, Pull-up resistor
RSDA
1.8 to 3.3-V Supply
SDA
5.1-kΩ, Pull-up resistor
RSCL
1.8 to 3.3-V Supply
SCL
5.1-kΩ, Pull-up resistor
Recommended application range for MCT8315A is shown in Table 8-2.
Table 8-2. Recommended Application Range
Parameter
Min
Max
Unit
Motor voltage
4.5
35
V
Motor electrical speed
-
3000
Hz
Peak motor phase current
-
4
A
Default EEPROM configuration for MCT8315A is listed in Table 8-3. Default values are chosen for reliable motor
start-up and closed loop operation. Refer to MCT8315A tuning guide which provides step by step procedure to
tune a 3-phase BLDC motor in closed loop, conform to use-case and explore features in the device.
Table 8-3. Recommended Default Values
Address Name
Address
Recommended Value
ISD_CONFIG
0x00000080
0x6EC4C100
MOTOR_STARTUP1
0x00000082
0x2EA610E4
MOTOR_STARTUP2
0x00000084
0x1221109C
CLOSED_LOOP1
0x00000086
0x0C321200
CLOSED_LOOP2
0x00000088
0x024224B0
CLOSED_LOOP3
0x0000008A
0x4CCC03E0
CLOSED_LOOP4
0x0000008C
0x000CE944
CONST_SPEED
0x0000008E
0x00A00510
CONST_PWR
0x00000090
0x5DC04C84
FAULT_CONFIG1
0x00000092
0x60F43025
FAULT_CONFIG2
0x00000094
0x7F87A009
TRAP_CONFIG1
0x0000009A
0x0548A186
TRAP_CONFIG2
0x0000009C
0x3A840000
150_DEG_TWO_PH_PROFILE
0x00000096
0x6ADB44A6
150_DEG_THREE_PH_PROFILE
0x00000098
0x392DFF80
PIN_CONFIG1
0x000000A4
0x2D720600
PIN_CONFIG2
0x000000A6
0x08000000
DEVICE_CONFIG
0x000000A8
0x7FFF0000
PERIPH_CONFIG
0x000000AA
0x00000000
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Table 8-3. Recommended Default Values (continued)
GD_CONFIG1
0x000000AC
0x1C440000
GD_CONFIG2
0x000000AE
0x00000000
Once the device EEPROM is programmed with the desired configuration, device can be operated stand-alone
and I2C serial interface is not required anymore. Speed can be commanded using SPEED pin.
Below are the two essential parameters that are required to spin the motor in closed loop.
1. Maximum motor speed.
2. Cycle by cycle (CBC) current limit.
8.2.1 Application curves
8.2.1.1 Motor startup
Figure 8-2 shows the phase current waveforms of various startup methods in MCT8315A such as align, double
align, IPD and slow first cycle.
Figure 8-2. Motor phase current waveforms of all startup methods
8.2.1.2 120o and variable commutation
In 120° commutation scheme, each motor phase is driven for 120° and Hi-Z for 60° within each half electrical
cycle, resulting in six different commutation states for a motor. Figure 8-3 shows the phase current and current
waveform FFT in 120° commutation mode. In variable commutation scheme, MCT8315A device switches
dynamically between 120° and 150° trapezoidal commutation depending on motor speed. The device operates
148
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in 150° mode at lower speeds and moves to 120° mode at higher speeds. Figure 8-4 shows the phase current
and current waveform FFT in 150° commutation.
Phase current
FFT
Figure 8-3. Phase current and FFT - 120 ocommutation
Phase current
FFT
Figure 8-4. Phase current and FFT - 150ocommutation
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8.2.1.3 Faster startup time
Startup time is the time taken for the motor to reach the target speed from zero speed. Faster startup time can
be achieved in MCT8315A by tuning motor startup, open loop and closed loop settings. Figure 8-5 shows FG,
phase current and motor electrical speed waveform. Motor takes 50 ms to reach target speed from zero speed.
FG
Phase current
Speed
Figure 8-5. Phase current, FG and motor speed - Faster startup time
8.2.1.4 Setting the BEMF threshold
The BEMF_THRESHOLD1 and BEMF_THRESHOLD2 values used for commutation instant detection in
MCT8315A can be computed from the motor phase voltage waveforms during coasting. For example, consider
the three-phase voltage waveforms of a BLDC motor while coasting as in Figure 8-6. The motor phase voltage
during coasting is the motor back-EMF.
Figure 8-6. Motor phase voltage during coasting
150
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In Figure 8-6, one floating phase voltage interval is denoted by the vertical markers on channel 3. The Vpeak
(peak-peak back-EMF) on channel 3 is 208-mV and Tc (commutation interval) is 2.22-ms as denoted by the
horizontal and vertical markers on channel 3. The digital equivalent counts for Vpeak and Tc are calculated as
follows.
In MCT8315A, a 3-V analog input corresponds to 4095 counts(12-bit) and phase voltage is scaled down by
10x factor before ADC input; therfore, Vpeak of 208-mV corresponds to an ADC input of 20.8mV, which in turn
equals 29 ADC counts. Assuming the PWM switching frequency is 25-kHz, one back-EMF sample is available
every 40-μs. So, in a time interval of 2.22-ms, a total of 55 back-EMF samples are integrated. Therefore, the
BEMF_THRESHOLD1 or BEMF_THRESHOLD2 value calculated as per Equation 7 is (½) * (29/2) * (55/2) =
199. Hence, in this example, BEMF_THRESHOLD1 and BEMF_THRESHOLD2 are set to 8h (corresponding to
200 which is the closest value to 199) for commutation instant detection using back-EMF integration method
during fast start-up. The exact speed at which the Vpeak and Tc values are measured to calculate the
BEMF_THRESHOLD1 and BEMF_THRESHOLD2 values is not critical (as long as there is sufficient resolution
in digital counts) since the product (Vpeak * Tc) is, largely, a constant for a given BLDC motor.
8.2.1.5 Maximum speed
Figure 8-7 shows phase current, phase voltage and FG of a motor that spins at maximum electrical speed of 3
kHz.
Phase current
Phase voltage
FG
Figure 8-7. Phase current, Phase voltage and FG at Maximum speed
8.2.1.6 Faster deceleration
MCT8315A has features to decelerate the motor quickly. Figure 8-8 shows phase current and motor electrical
speed waveform when the motor decelerates from 100% duty cycle to 10% duty cycle. Time taken for the motor
to decelerate from 100% duty cycle to 10% duty cycle when fast deceleration is disabled is around 10 seconds.
Figure 8-9 shows phase current and motor electrical speed waveform when the motor decelerates from 100%
duty cycle to 10% duty cycle. Time taken for the motor to decelerate from 100% duty cycle to 10% duty cycle
when fast deceleration is enabled is around 1.5 seconds.
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Note
Please note that when fast deceleration is enabled and anti-voltage surge (AVS) is disabled, there
might be voltage spikes seen in supply voltage. Enable AVS to protect the power supply from voltage
overshoots during motor deceleration.
Phase current
Speed
Figure 8-8. Phase current and motor speed - Faster deceleration disabled
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Phase current
Speed
Figure 8-9. Phase current and motor speed -Faster deceleration enabled
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9 Power Supply Recommendations
9.1 Bulk Capacitance
Having an appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors, including:
• The highest current required by the motor system
• The capacitance and current capability of the power supply
• The amount of parasitic inductance between the power supply and motor system
• The acceptable voltage ripple
• The type of motor used (brushed DC, brushless DC, stepper)
• The motor braking method
The inductance between the power supply and the motor drive system limits the rate at which current can
change from the power supply. If the local bulk capacitance is too small, the system responds to excessive
current demands or dumps from the motor with a change in VM voltage. When adequate bulk capacitance is
used, the VM voltage remains stable and high current can be quickly supplied.
The data sheet generally provides a recommended value, but system-level testing is required to determine the
appropriate bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
+
Motor Driver
±
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 9-1. Example Setup of Motor Drive System With External Power Supply
The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.
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10 Layout
10.1 Layout Guidelines
The bulk capacitor should be placed to minimize the distance of the high-current path through the motor driver
device. The connecting metal trace widths should be as wide as possible, and numerous vias should be used
when connecting PCB layers. These practices minimize parasitic inductance and allow the bulk capacitor to
deliver high current.
Small-value capacitors should be ceramic, and placed closely to device pins.
The high-current device outputs should use wide metal traces.
To reduce noise coupling and EMI interference from large transient currents into small-current signal paths,
grounding should be partitioned between PGND and AGND. TI recommends connecting all non-power stage
circuitry (including the thermal pad) to AGND to reduce parasitic effects and improve power dissipation from the
device. Optionally, GND_BK can be split. Ensure grounds are connected through net-ties or wide resistors to
reduce voltage offsets and maintain gate driver performance.
The device thermal pad should be soldered to the PCB top-layer ground plane. Multiple vias should be used to
connect to a large bottom-layer ground plane. The use of large metal planes and multiple vias helps dissipate
the I2 × RDS(on) heat that is generated in the device.
To improve thermal performance, maximize the ground area that is connected to the thermal pad ground across
all possible layers of the PCB. Using thick copper pours can lower the junction-to-air thermal resistance and
improve thermal dissipation from the die surface.
Separate the SW_BK and FB_BK traces with ground separation to reduce buck switching from coupling as noise
into the buck outer feedback loop. Widen the FB_BK trace as much as possible to allow for faster load switching.
Figure 10-1 shows a layout example for the MCT8315A. Also, for layout example, refer to MCT8315A EVM.
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10.2 Layout Example
Figure 10-1. Recommended Layout Example
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10.3 Thermal Considerations
The MCT8315A has thermal shutdown (TSD) as previously described. A die temperature in excess of 150°C
(minimally) disables the device until the temperature drops to a safe level.
Any tendency of the device to enter thermal shutdown is an indication of excessive power dissipation, insufficient
heatsinking, or too high an ambient temperature.
10.3.1 Power Dissipation
The power dissipated in the output FET resistance (RDS(on)) dominates power dissipation in MCT8315A.
At start-up and fault conditions, the FET current is much higher than normal operating FET current; remember to
take these peak currents and their duration into consideration.
The total device power dissipation is the power dissipated in each of the three half-bridges added together along
with standby power, LDO and buck regulator losses.
The maximum amount of power that the device can dissipate depends on ambient temperature and heatsinking.
Note that RDS(on) increases with temperature, so as the device heats, the power dissipation increases. Take this
into consideration when sizing the heatsink.
A summary of equations for calculating each loss is shown below in Table 10-1.
Table 10-1. Power Losses for MCT8315A
Loss type
MCT8315A
Pstandby = VM x IVM_TA
Standby power
LDO
PLDO = (VM-VAVDD) x IAVDD, if BUCK_PS_DIS = 1b
PLDO = (VBK-VAVDD) x IAVDD, if BUCK_PS_DIS = 0b
PCON = 2 x (IRMS(trap))2 x Rds,on(TA)
FET conduction
FET switching
Diode
Demagnetization
PSW = IPK(trap) x VPK(trap) x trise/fall x fPWM
Pdiode = IPK(trap) x Vdiode x tdead x fPWM
Without Active Demag: 3 x IPK(trap) x Vdiode x tcommutation x fmotor_elec
With Active Demag: 3 x (IRMS(trap))2 x Rds,on(TA) x tcommutation x
fmotor_elec
PBK = 0.11 x VBK x IBK (ηBK = 90%)
Buck
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11 Device and Documentation Support
11.1 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.2 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.4 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated device. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
12.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
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Device
Package
Type
Package
Drawing
Pins
SPQ
Reel
Diameter
(mm)
Reel
Width W1
(mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
MCT8315A1VRGFR
VQFN
RGF
40
3000
330.0
16.4
5.25
7.25
1.45
8.0
16.0
Q1
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MCT8315A1VRGFR
VQFN
RGF
40
3000
367.0
367.0
38.0
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
MCT8315A1VRGFR
ACTIVE
VQFN
RGF
40
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
MCT83
15A1V
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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