MF10CCWMX/NOPB

MF10-N www.ti.com SNOS547C – JUNE 1999 – REVISED APRIL 2013 MF10-N Universal Monolithic Dual Switched Capacitor Filter Check for Samples: MF10-N FEATURES DESCRIPTION • • The MF10-N consists of 2 independent and extremely easy to use, general purpose CMOS active filter building blocks. Each block, together with an external clock and 3 to 4 resistors, can produce various 2nd order functions. Each building block has 3 output pins. One of the outputs can be configured to perform either an allpass, highpass or a notch function; the remaining 2 output pins perform lowpass and bandpass functions. The center frequency of the lowpass and bandpass 2nd order functions can be either directly dependent on the clock frequency, or they can depend on both clock frequency and external resistor ratios. The center frequency of the notch and allpass functions is directly dependent on the clock frequency, while the highpass center frequency depends on both resistor ratio and clock. Up to 4th order functions can be performed by cascading the two 2nd order building blocks of the MF10-N; higher than 4th order functions can be obtained by cascading MF10-N packages. Any of the classical filter configurations (such as Butterworth, Bessel, Cauer and Chebyshev) can be formed. 1 • • • • • • • Easy to Use Clock to Center Frequency Ratio Accuracy ±0.6% Filter Cutoff Frequency Stability Directly Dependent on External Clock Quality Low Sensitivity to External Component Variation Separate Highpass (or Notch or Allpass), Bandpass, Lowpass Outputs fO × Q Range up to 200 kHz Operation up to 30 kHz 20-pin 0.3″ Wide PDIP Package 20-pin Surface Mount (SOIC) Wide-Body Package For pin-compatible device with improved performance refer to LMF100 datasheet. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999–2013, Texas Instruments Incorporated MF10-N SNOS547C – JUNE 1999 – REVISED APRIL 2013 www.ti.com System Block Diagram Package in 20 pin molded wide body SOIC and 20 pin PDIP. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) Supply Voltage (V+ − V−) 14V + V + 0.3V Voltage at Any Pin V− − 0.3V Input Current at Any Pin Package Input Current (3) 5 mA (3) 20 mA Power Dissipation (4) 500 mW Storage Temperature 150°C ESD Susceptability (5) 2000V Soldering Information SO Package (1) (2) (3) (4) (5) 2 N Package: 10 sec 260°C Vapor Phase (60 Sec.) 215°C Infrared (15 Sec.) 220°C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V− or VIN > V+) the absolute value of current at that pin should be limited to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX − TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, TJMAX = 125°C, and the typical junction-to-ambient thermal resistance of the MF10ACN/CCN when board mounted is 55°C/W. For the MF10AJ/CCJ, this number increases to 95°C/W and for the MF10ACWM/CCWM this number is 66°C/W. Human body model, 100 pF discharged through a 1.5 kΩ resistor. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: MF10-N MF10-N www.ti.com SNOS547C – JUNE 1999 – REVISED APRIL 2013 Operating Ratings (1) Temperature Range (TMIN ≤ TA ≤ TMAX) (1) 0°C ≤ TA ≤ 70°C MF10ACN, MF10CCN, MF10CCWM Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Electrical Characteristics V+ = +5.00V and V− = −5.00V unless otherwise specified. Boldface limits apply for TMIN to TMAX; all other limits TA = TJ = 25°C. Symbol Parameter Conditions MF10ACN, MF10CCN, MF10CCWM Typical (1) V+ − V− IS Supply Voltage Center Frequency Range fCLK Clock Frequency Range fCLK/fO fCLK/fO 50:1 Clock to Center Frequency Ratio Deviation 100:1 Clock to Center Frequency Ratio Deviation 9 Max 14 Clock Applied to Pins 10 & 11 No Input Signal Min fO × Q < 200 kHz Hz 20 kHz Min 5.0 10 Hz 1.0 MHz Max 1.5 MF10A MF10C MF10A MF10C Min DC Offset Voltage (5) Max Min Max VOS3 ±0.2 ±0.6 ±0.6 Q = 10, Mode 1 Vpin12 = 5V fCLK = 250 KHz ±0.2 ±1.5 ±1.5 Q = 10, Mode 1 Vpin12 = 0V fCLK = 500 kHz ±0.2 ±0.6 ±0.6 ±0.2 ±1.5 ±1.5 DC Offset Voltage (5) Min Max VOS2 DC Offset Voltage 10 (5) ±2 ±6 ±6 Vpin12 = 0V fCLK = 500 kHz ±2 ±6 ±6 % 0 ±0.2 ±0.2 dB ±5.0 ±20 ±20 mV −150 −185 −185 −85 −85 Vpin12 = +5V (fCLK/fO = 50) SA/B = V+ Vpin12 = +5V (fCLK/fO = 50) SA/B = V− Vpin12 = +5V (fCLK/fO = 50) All Modes Vpin12 = 0V (fCLK/fO = 100) SA/B = V+ −300 mV Vpin12 = 0V (fCLK/fO = 100) SA/B = V− −140 mV Vpin12 = 0V (fCLK/fO = 100) All Modes −140 mV −70 −70 −100 −100 −20 −20 DC Offset Voltage (5) VOUT Minimum Output BP, LP Pins RL = 5k ±4.25 ±3.8 ±3.8 Voltage Swing N/AP/HP Pin RL = 3.5k ±4.25 ±3.8 ±3.8 Op Amp Gain BW Product SR Op Amp Slew Rate (1) (2) (3) (4) (5) mV mV VOS3 GBW % mV Vpin12 = 5V fCLK = 250 kHz Mode 1 R1 = R2 = 10k VOS2 mA 0.2 Q = 10, Mode 1 DC Offset Voltage (5) 12 30 Q Error (MAX) (4) DC Lowpass Gain 12 V 0.1 Q = 10, Mode 1 VOS1 8 Units Max Clock Feedthrough HOLP Design Limit (3) Min Maximum Supply Current fO Tested Limit (2) mV V V 2.5 MHz 7 V/μs Typicals are at 25°C and represent most likely parametric norm. Tested limits are ensured to AOQL (Average Outgoing Quality Level). Design limits are specified but not 100% tested. These limits are not used to calculate outgoing quality levels. The accuracy of the Q value is a function of the center frequency (fO). This is illustrated in the curves under the heading “Typical Performance Characteristics”. VOS1, VOS2, and VOS3 refer to the internal offsets as discussed in OFFSET VOLTAGE. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: MF10-N 3 MF10-N SNOS547C – JUNE 1999 – REVISED APRIL 2013 www.ti.com Electrical Characteristics (continued) V+ = +5.00V and V− = −5.00V unless otherwise specified. Boldface limits apply for TMIN to TMAX; all other limits TA = TJ = 25°C. Symbol Parameter MF10ACN, MF10CCN, MF10CCWM Conditions Typical (1) (6) (7) Maximum Output Short Circuit Current (7) Design Limit (3) Units Vpin12 = +5V, (fCLK/fO = 50) 83 dB Vpin12 = 0V, (fCLK/fO = 100) 80 dB Source 20 mA Sink 3.0 mA Dynamic Range (6) ISC Tested Limit (2) For ±5V supplies the dynamic range is referenced to 2.82V rms (4V peak) where the wideband noise over a 20 kHz bandwidth is typically 200 μV rms for the MF10-N with a 50:1 CLK ratio and 280 μV rms for the MF10-N with a 100:1 CLK ratio. The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output to the negative supply. The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage swing and then shorting that output to the positive supply. These are the worst case conditions. Logic Input Characteristics Boldface limits apply for TMIN to TMAX; all other limits TA = TJ = 25°C MF10ACN, MF10CCN, MF10CCWM Parameter Min Logical “1” CMOS Clock Input Voltage Max Logical “0” Min Logical “1” Max Logical “0” Min Logical “1” TTL Clock Input Voltage Max Logical “0” Min Logical “1” Max Logical “0” (1) (2) (3) 4 Conditions V+ = +5V, V− = −5V, VLSh = 0V V+ = +10V, V− = 0V, VLSh = +5V V+ = +5V, V− = −5V, VLSh = 0V V+ = +10V, V− = 0V, VLSh = 0V Typical (1) Tested Limit (2) Design Limit (3) Units +3.0 +3.0 V −3.0 −3.0 V +8.0 +8.0 V +2.0 +2.0 V +2.0 +2.0 V +0.8 +0.8 V +2.0 +2.0 V +0.8 +0.8 V Typicals are at 25°C and represent most likely parametric norm. Tested limits are ensured to AOQL (Average Outgoing Quality Level). Design limits are specified but not 100% tested. These limits are not used to calculate outgoing quality levels. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: MF10-N MF10-N www.ti.com SNOS547C – JUNE 1999 – REVISED APRIL 2013 Typical Performance Characteristics Power Supply Current vs. Power Supply Voltage Positive Output Voltage Swing vs. Load Resistance (N/AP/HP Output) Figure 1. Figure 2. Negative Output Voltage Swing vs. Load Resistance (N/AP/HP Output) Negative Output Swing vs. Temperature Figure 3. Figure 4. Positive Output Swing vs. Temperature Crosstalk vs. Clock Frequency Figure 5. Figure 6. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: MF10-N 5 MF10-N SNOS547C – JUNE 1999 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) 6 Q Deviation vs. Temperature Q Deviation vs. Temperature Figure 7. Figure 8. Q Deviation vs. Clock Frequency Q Deviation vs. Clock Frequency Figure 9. Figure 10. fCLK/fO Deviation vs. Temperature fCLK/fO Deviation vs. Temperature Figure 11. Figure 12. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: MF10-N MF10-N www.ti.com SNOS547C – JUNE 1999 – REVISED APRIL 2013 Typical Performance Characteristics (continued) fCLK/fO Deviation vs. lock Frequency fCLK/fO Deviation vs. Clock Frequency Figure 13. Figure 14. Deviation of fCLK/fO vs. Nominal Q Deviation of fCLK/fO vs. Nominal Q Figure 15. Figure 16. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: MF10-N 7 MF10-N SNOS547C – JUNE 1999 – REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS LP(1,20), BP(2,19), N/AP/HP(3,18) The second order lowpass, bandpass and notch/allpass/highpass outputs. These outputs can typically sink 1.5 mA and source 3 mA. Each output typically swings to within 1V of each supply. INV(4,17) The inverting input of the summing op-amp of each filter. These are high impedance inputs, but the non-inverting input is internally tied to AGND, making INVA and INVB behave like summing junctions (low impedance, current inputs). S1(5,16) S1 is a signal input pin used in the allpass filter configurations (see modes 4 and 5). The pin should be driven with a source impedance of less than 1 kΩ. If S1 is not driven with a signal it should be tied to AGND (mid-supply). SA/B(6) This pin activates a switch that connects one of the inputs of each filter's second summer to either AGND (SA/B tied to V−) or to the lowpass (LP) output (SA/B tied to V+). This offers the flexibility needed for configuring the filter in its various modes of operation. VA+(7),VD+(8) Analog positive supply and digital positive supply. These pins are internally connected through the IC substrate and therefore VA+ and VD+ should be derived from the same power supply source. They have been brought out separately so they can be bypassed by separate capacitors, if desired. They can be externally tied together and bypassed by a single capacitor. VA−(14), VD−(13) Analog and digital negative supplies. The same comments as for VA+ and VD+ apply here. LSh(9) Level shift pin; it accommodates various clock levels with dual or single supply operation. With dual ±5V supplies, the MF10-N can be driven with CMOS clock levels (±5V) and the LSh pin should be tied to the system ground. If the same supplies as above are used but only TTL clock levels, derived from 0V to +5V supply, are available, the LSh pin should be tied to the system ground. For single supply operation (0V and +10V) the VA−, VD−pins should be connected to the system ground, the AGND pin should be biased at +5V and the LSh pin should also be tied to the system ground for TTL clock levels. LSh should be biased at +5V for CMOS clock levels in 10V single-supply applications. CLKA(10), CLKB(11) Clock inputs for each switched capacitor filter building block. They should both be of the same level (TTL or CMOS). The level shift (LSh) pin description discusses how to accommodate their levels. The duty cycle of the clock should be close to 50% especially when clock frequencies above 200 kHz are used. This allows the maximum time for the internal op-amps to settle, which yields optimum filter operation. 50/100/CL(12) By tying this pin high a 50:1 clock-to-filter-center-frequency ratio is obtained. Tying this pin at midsupplies (i.e. analog ground with dual supplies) allows the filter to operate at a 100:1 clock-to-centerfrequency ratio. When the pin is tied low (i.e., negative supply with dual supplies), a simple current limiting circuit is triggered to limit the overall supply current down to about 2.5 mA. The filtering action is then aborted. AGND(15) This is the analog ground pin. This pin should be connected to the system ground for dual supply operation or biased to mid-supply for single supply operation. For a further discussion of mid-supply biasing techniques see the Applications Information. For optimum filter performance a “clean” ground must be provided. Definition of Terms fCLK: the frequency of the external clock signal applied to pin 10 or 11. fO: center frequency of the second order function complex pole pair. fO is measured at the bandpass outputs of the MF10-N, and is the frequency of maximum bandpass gain (Figure 17). fnotch: the frequency of minimum (ideally zero) gain at the notch outputs. fz: the center frequency of the second order complex zero pair, if any. If fz is different from fO and if QZ is high, it can be observed as the frequency of a notch at the allpass output (Figure 26). Q: “quality factor” of the 2nd order filter. Q is measured at the bandpass outputs of the MF10-N and is equal to fO divided by the −3 dB bandwidth of the 2nd order bandpass filter (Figure 17). The value of Q determines the shape of the 2nd order filter responses as shown in Figure 22. 8 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: MF10-N MF10-N www.ti.com SNOS547C – JUNE 1999 – REVISED APRIL 2013 QZ: the quality factor of the second order complex zero pair, if any. QZ is related to the allpass characteristic, which is written: (1) where QZ = Q for an all-pass response. HOBP: the gain (in V/V) of the bandpass output at f = fO. HOLP: the gain (in V/V) of the lowpass output as f → 0 Hz (Figure 18). HOHP: the gain (in V/V) of the highpass output as f → fCLK/2 (Figure 19). HON: the gain (in V/V) of the notch output as f → 0 Hz and as f → fCLK/2, when the notch filter has equal gain above and below the center frequency (Figure 20). When the low-frequency gain differs from the high-frequency gain, as in modes 2 and 3a (Figure 27 and Figure 24), the two quantities below are used in place of HON. HON1: the gain (in V/V) of the notch output as f → 0 Hz. HON2: the gain (in V/V) of the notch output as f → fCLK/2. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: MF10-N 9 MF10-N SNOS547C – JUNE 1999 – REVISED APRIL 2013 www.ti.com (a) (b) Figure 17. 2nd-Order Bandpass Response 10 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: MF10-N MF10-N www.ti.com SNOS547C – JUNE 1999 – REVISED APRIL 2013 (a) (b) Figure 18. 2nd-Order Low-Pass Response Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: MF10-N 11 MF10-N SNOS547C – JUNE 1999 – REVISED APRIL 2013 www.ti.com (a) (b) Figure 19. 2nd-Order High-Pass Response 12 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: MF10-N MF10-N www.ti.com SNOS547C – JUNE 1999 – REVISED APRIL 2013 (a) (b) Figure 20. 2nd-Order Notch Response Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: MF10-N 13 MF10-N SNOS547C – JUNE 1999 – REVISED APRIL 2013 www.ti.com (a) (b) Figure 21. 2nd-Order All-Pass Response (a) Bandpass (b) Low Pass (d) Notch (c) High-Pass (e) All-Pass Figure 22. Response of various 2nd-order filters as a function of Q. Gains and center frequencies are normalized to unity. 14 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: MF10-N MF10-N www.ti.com SNOS547C – JUNE 1999 – REVISED APRIL 2013 Modes of Operation The MF10-N is a switched capacitor (sampled data) filter. To fully describe its transfer functions, a time domain approach is appropriate. Since this is cumbersome, and since the MF10-N closely approximates continuous filters, the following discussion is based on the well known frequency domain. Each MF10-N can produce a full 2nd order function. See Table 1 for a summary of the characteristics of the various modes. MODE 1: Notch 1, Bandpass, Lowpass Outputs: fnotch = fO (See Figure 23) (2) fO= center frequency of the complex pole pair (3) fnotch= center frequency of the imaginary zero pair = fO. (4) (5) = quality factor of the complex pole pair BW = the −3 dB bandwidth of the bandpass output. Circuit dynamics: (6) MODE 1a: Non-Inverting BP, LP (See Figure 24) (7) Figure 23. MODE 1 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: MF10-N 15 MF10-N SNOS547C – JUNE 1999 – REVISED APRIL 2013 www.ti.com VIN should be driven from a low impedance (