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TUSB1211
SLLSE80B – MARCH 2011 – REVISED JUNE 2015
TUSB1211 Stand-Alone USB Transceiver Chip
1 Device Overview
1.1
Features
1
• USB2.0 PHY Transceiver Chip, Designed to
Interface With a USB Controller Through a ULPI
Interface, Fully Compliant With:
– Universal Serial Bus Specification Rev. 2.0
– On-The-Go Supplement to the USB 2.0
Specification Rev. 1.3
– UTMI+ Low Pin Interface (ULPI) Specification
Rev. 1.1
• DP/DM Line External Component Compensation
(Patent #US7965100 B1)
• Interfaces to Host, Peripheral, and OTG Device
Cores; Optimized for Portable Devices or System
ASICs With Built-in USB OTG Device Core
• Complete USB OTG Physical Front-End
• USB Battery Charger Detection Feature
1.2
•
•
•
Applications
Mobile Phones
Portable Computers
Tablet Devices
1.3
• USB HS Start-of-Frame Clock Output Feature
Available on SOF Pin Can be Used to Synchronize
Another Application, for Example Audio, With the
USB Packet Stream
• ULPI Interface:
– I/O Interface (1.8 V) Optimized for NonTerminated 50-Ω Line Impedance
– ULPI CLOCK Pin (60 MHz) Supports Both Input
and Output Clock Configurations
– Fully Programmable ULPI-Compliant Register
Set
• Full Industrial-Grade Operating Temperature
Range from –40°C to 85°C
• Available in a TFBGA36 Ball Package
•
•
•
Video Game Consoles
Desktop Computers
Portable Music Payers
Description
The TUSB1211 device is a USB2.0 transceiver chip, designed to interface with a USB controller through a
ULPI interface. The device supports all USB2.0 data rates (high-speed 480 Mbps, full-speed 12 Mbps and
low-speed 1.5 Mbps), and is compliant to both Host and Peripheral modes. The TUSB1211 also supports
a UART mode and legacy ULPI serial modes.
The TUSB1211 device supports the OTG (Ver1.3) optional addendum to the USB 2.0 Specification,
including Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). TUSB1211 also supports
USB Battery Charging Specification Ver1.1 integrating a charger detection module for sensing and control
on DP/DM lines, and ACA (Accessory Charger Adapter) detection and control on ID line.
The DP/DM external component compensation in the transmitter compensates for variations in the series
impendence to match with the data line impedance and the receiver input impedance, to limit data
reflections and, thereby, improve eye diagrams.
Device Information (1)
PART NUMBER
TUSB1211
(1)
PACKAGE
BGA MICROSTAR JUNIOR (36)
BODY SIZE (NOM)
3.50 mm × 3.50 mm
For all available packages, see the orderable addendum at the end of the data sheet.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TUSB1211
SLLSE80B – MARCH 2011 – REVISED JUNE 2015
1.4
Functional Block Diagram
2
Device Overview
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SLLSE80B – MARCH 2011 – REVISED JUNE 2015
Table of Contents
1
2
3
Device Overview ......................................... 1
4.23
HS Transmitter ...................................... 16
1.1
Features .............................................. 1
4.24
Pullup and Pulldown Resistors ...................... 17
1.2
Applications ........................................... 1
4.25
Autoresume Watchdog Timer ....................... 17
1.3
Description ............................................ 1
1.4
Functional Block Diagram ............................ 2
..................................
...................................
4.28 Electrical Specs – Charger Detection Currents .....
4.29 Electrical Specs – Resistance ......................
4.30 Electrical Specs – Capacitance .....................
4.31 Charger Detection Debounce and Wait Timing .....
4.32 ULPI Interface .......................................
4.33 Power-On Timing Diagrams .........................
4.34 Clock System ........................................
4.35 Clock System ........................................
4.36 Power Management .................................
4.37 Power Provider ......................................
4.38 Power Control .......................................
Detailed Description ...................................
5.1
Overview ............................................
5.2
Functional Block Diagram ..........................
5.3
Feature Description .................................
5.4
Register Maps .......................................
Application, Implementation, and Layout .........
6.1
Application Information ..............................
6.2
Typical Application ..................................
6.3
Layout ...............................................
6.4
Power Supply Recommendations ...................
Device and Documentation Support ...............
7.1
Documentation Support .............................
7.2
Trademarks..........................................
7.3
Electrostatic Discharge Caution .....................
7.4
Glossary .............................................
Revision History ......................................... 4
Pin Configuration and Functions ..................... 5
.......................................... 5
Specifications ............................................ 8
4.1
Absolute Maximum Ratings .......................... 8
4.2
ESD Ratings .......................................... 8
4.3
Recommended Operating Conditions ................ 8
4.4
Power Consumption Summary ....................... 9
4.5
Electrical Characteristics – Analog Output Pins ...... 9
4.6
Electrical Characteristics – Analog Input Pins ...... 10
3.1
4
4.7
4.8
Pin Diagram
Digital I/O Electrical Characteristics – Non-ULPI
Pins .................................................. 10
Digital I/O Electrical Characteristics – Non-ULPI
Pins .................................................. 10
4.9
Electrical Characteristics – REFCLK ................ 10
4.10
Electrical Characteristics – CLOCK Input ........... 11
4.11
4.12
Electrical Characteristics – REFCLK ................ 11
Electrical Characteristics – CK32K Clock
Generator............................................ 11
4.13
Thermal Characteristics ............................. 11
4.14
REG3V3 Internal LDO Regulator Characteristics ... 12
4.15
REG1V8 Internal LDO Regulator Characteristics ... 12
4.16
REG1V5 Internal LDO Regulator Characteristics ... 12
4.17
Timers and Debounce
4.18
4.19
4.20
4.21
4.22
..............................
OTG VBUS Electrical ...............................
LS/FS Single-Ended Receivers .....................
LS/FS Differential Receiver .........................
LS Transmitter ......................................
FS Transmitter ......................................
5
6
7
13
14
15
15
15
15
8
4.26
UART Transceiver
17
4.27
OTG ID Electrical
17
19
19
19
19
20
20
23
23
23
24
25
26
26
26
26
32
70
70
70
72
73
74
74
74
74
74
Mechanical Packaging and Orderable
Information .............................................. 74
8.1
Packaging Information
..............................
Table of Contents
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3
TUSB1211
SLLSE80B – MARCH 2011 – REVISED JUNE 2015
www.ti.com
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (January 2012) to Revision B
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
4
Page
Deleted some of the features per the submitted sources ....................................................................... 1
Changed the document to the new TI standard layout ......................................................................... 1
Changed pin F5 from A to D in the A/D column ................................................................................. 6
Added the Analog Output Pins section ............................................................................................ 9
Added the word Non to the tile Non-ULPI Pins and replaced the Digital I/O Electrical Characteristics – Non-ULPI
Pins table data ....................................................................................................................... 10
Added the Timers and Debounce section........................................................................................ 13
Added the OTG VBUS Specifications ............................................................................................ 14
Added the Pullup and Pulldown Resistors table ................................................................................ 17
Added Section 4.26 ................................................................................................................ 17
Added the OTG ID Electrical table ................................................................................................ 17
Added the ULPI Interface section ................................................................................................. 20
Added the Power-On Timing Diagrams section ................................................................................. 20
Added the Internal Clock Generator (32 kHz) ................................................................................... 23
Added the Power Provider section ............................................................................................... 24
Changed the location of paragraphs from Description to Detailed Description, subsection Overview................... 26
Added the LS/FS Single-Ended Receivers section ............................................................................. 28
Added the LS/FS Differential Receiver section.................................................................................. 28
Added the LS/FS Transmitter ...................................................................................................... 28
Added the HS Differential Receiver section ..................................................................................... 28
Added the HS Differential Transmitter section .................................................................................. 29
Added the Autoresume section .................................................................................................... 29
Added the Register Map section ................................................................................................. 32
Added the Application and Implementation section ............................................................................ 70
Deleted two List Items from the Unused Pins Connection section ........................................................... 71
Added the Layout section .......................................................................................................... 72
Added the Power Supply Recommendations section .......................................................................... 73
Revision History
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SLLSE80B – MARCH 2011 – REVISED JUNE 2015
3 Pin Configuration and Functions
3.1
Pin Diagram
ZRQ Package
36-Pin TFBGA
Bottom View
TFBGA36 PACKAGE
(BOTTOM VIEW)
(1)
(2)
3.1.1
F
CHRG_
POL
CHRG_
DET
VBAT
VBUS
REFCLK
SOF
E
CHRG_
EN_N
FAULT
REG3V3
GND
DIR
REG1V5
D
DP
GND
ID
PSW
NXT
STP
C
DM
NC
CS_N
RESET_N
GND
DATA7
B
DATA0
VDDIO
CS
CFG
VDDIO
DATA6
A
DATA1
DATA2
DATA3
CLOCK
DATA4
DATA5
(1)
5
3
6
1
4
2
NC = Not Connected
The size of the device should be 3.5 mm ±0.1 mm by 3.5 mm ±0.1 mm. Height is 1.0 mm typical 1.15 mm max including the solder
balls. The pitch of the device is 0.5 mm. Ball width 0.3 mm ±0.05 mm.
Pin Attributes
Pin Functions
NO.
PIN
(1)
NAME
A/D
(2)
TYPE
(3)
LEVEL (4)
DESCRIPTION
1
D5
NXT
D
O
VDDIO
ULPI NXT output signal
2
B1
DATA0
D
I/O
VDDIO
ULPI DATA input/output signal synchronized to CLOCK
3
A1
DATA1
D
I/O
VDDIO
ULPI DATA input/output signal synchronized to CLOCK
4
A2
DATA2
D
I/O
VDDIO
ULPI DATA input/output signal synchronized to CLOCK
5
A3
DATA3
D
I/O
VDDIO
ULPI DATA input/output signal synchronized to CLOCK
6
A5
DATA4
D
I/O
VDDIO
ULPI DATA input/output signal synchronized to CLOCK
7
A6
DATA5
D
I/O
VDDIO
ULPI DATA input/output signal synchronized to CLOCK
8
B6
DATA6
D
I/O
VDDIO
ULPI DATA input/output signal synchronized to CLOCK
9
B3
CS
D
I
VDDIO
Active-high chip select pin. When low the IC is in power down
and ULPI bus is tri-stated. When high (and CS_N pin iTie to
VDDIO if unused.s low) normal operation.
10
E6
REG1V5
A
POWER
VDD15
1.5 V internal LDO output. Connect to external filtering
capacitor.
11
C6
DATA7
D
I/O
VDDIO
ULPI DATA input/output signal synchronized to CLOCK
(1)
(2)
(3)
(4)
Pin = Package Pin coordinate of
A/D: A = Analog pin, D = Digital pin
TYPE: I = Input pin type, O = Output pin type, I/O = Input/Output pin type, POWER = Power supply pin type,
GROUND = Ground type pin
LEVEL = Pin power supply level
Pin Configuration and Functions
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SLLSE80B – MARCH 2011 – REVISED JUNE 2015
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Pin Functions (continued)
NO.
NAME
A/D
(2)
TYPE (3)
LEVEL (4)
DESCRIPTION
12
B4
CFG
D
I
VDDIO
REFCLK clock frequency configuration pin.
Two frequencies are supported: 19.2 MHz when 0, or 26 MHz
when 1.
13
D1
DP
A
I/O
VDD33
DP pin of the USB connector
14
C1
DM
A
I/O
VDD33
DM pin of the USB connector
15
E3
REG3V3
A
POWER
VDD33
3.3 V internal LDO output. Connect to external filtering
capacitor.
16
F3
VBAT
A
POWER
VBAT
Input supply voltage or battery source. Nominally 3.3 V to 4.5 V
17
F4
VBUS
A
I/O
VBUS
VBUS pin of the USB connector
18
D3
ID
A
I/O
VBUS
Identification (ID) pin of the USB connector
VDDIO
ULPI 60-MHz clock on which ULPI data is synchronized. 2
modes are possible:
Input Mode: CLOCK defaults as an input (this is the default
clock mode)
Output Mode: When an input clock is detected on REFCLK pin
then CLOCK will change to an output
19
6
PIN
(1)
A4
CLOCK
D
I/O
20
C4
RESET_N
D
I
VDDIO
Active low chip reset pin. Minimum pulse width 100 µs. When
low all digital logic (except 32-kHz logic required for power-up
sequencing and charger detection state-machine) including
registers are reset to their default values. ULPI bus is in “ULPI
Synchronous mode power-up PLL OFF” state as described in
Table 5-5. When high normal USB operation.
21
D6
STP
D
I
VDDIO
ULPI STP input signal
22
E5
DIR
D
O
VDDIO
ULPI DIR output signal
23
B5
VDDIO
A
I
VDDIO
External 1.8-V supply input for digital I/Os. Connect to external
filtering capacitor.
24
B2
VDDIO
A
I
VDDIO
External 1.8-V supply input for digital I/Os. Connect to external
filtering capacitor.
25
C5
GND
A
GROUND
GND
Ground
26
D2
GND
A
GROUND
GND
Ground
27
E4
GND
A
GROUND
GND
Ground
28
F5
REFCLK
D
I
VDDIO
Reference clock input.
Input reference clock frequency must be indicated by CFG pin.
Two frequencies are supported: 19.2 MHz (when CFG = 0), and
26 MHz (when CFG = 1).
29
F6
SOF
D
O
VDDIO
HS USB SOF (Start-of-Frame) output clock. (feature controlled
by SOF_EN bit, disabled and output logic low by default.). HS
USB SOF packet rate is 8 kHz.
30
C2
NC
—
—
31
C3
CS_N
D
I
VDDIO
Active-low chip select pin. When high the IC is in power down
and ULPI bus is tri-stated. When low (and CS pin is high)
normal operation. Tie to GND if unused.
32
E1
CHRG_EN_N
D
I
VBAT
Active low input pin used to enable Battery Charging Detection
in Dead Battery Charger Detection mode. This pin is ignored in
ACTIVE mode. Connect to GND to activate. Connect to VBAT
when charger detection not required.
Not connected
33
E2
FAULT
D
I
VBAT
VBUS fault detector input used as
EXTERNALVBUSINDICATOR in TUSB1211. The link must
enable VBUS fault detection through the
USEEXTERNALVBUSINDICATOR register bit, and the polarity
must be set through the INDICATORCOMPLEMENT register
bit. INDICATORPASSTHRU bit can be used to qualify FAULT
with the internal vbusvalid comparator. Connect to GND if not
used. This pin is 5-V tolerant.
34
F1
CHRG_POL
D
I
VBAT
When connected to GND then CHRG_DET output pin is active
low. When connected to VBAT then CHRG_DET output pin is
active high.
Pin Configuration and Functions
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Pin Functions (continued)
NO.
35
36
PIN
(1)
F2
D4
NAME
CHRG_DET
PSW
A/D
(2)
TYPE (3)
D
D
O
O
LEVEL (4)
DESCRIPTION
VBAT
When CHRG_POL pin is at GND then CHRG_DET is in active
low open-drain mode with external RCHRGDET (100K)
connected to VBAT. When CHRG_POL pin is at VBAT then
CHRG_DET is in active high open-source mode with external
RCHRGDET (100K) connected to GND. This pin is 5-V tolerant.
VBAT
Controls an external, active high, VBUS power switch or charge
pump. Open source output on VBAT supply when PSW_OSOD
bit is 0 (default), open-drain active-low output when
PSW_OSOD bit is 1. Requires an external RPSW (100K)
pulldown/pullup resistor to GND/VBAT.
Pin Configuration and Functions
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TUSB1211
SLLSE80B – MARCH 2011 – REVISED JUNE 2015
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4 Specifications
4.1
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VBAT (2)
VDDIO
MIN
MAX
UNIT
0
5.0
V
The product will have negligible reliability
impact for pulsed voltage spikes of 5.5 V for a
total (cumulative over lifetime) duration of 5
milliseconds
5.5
V
IO supply voltage
Continuous
1.98
V
Voltage on any input except VDDIO,
VBAT, and VBUS pads
Where VDD represents the voltage applied to
the power supply pin associated with the
input
1.0 × VDD + 0.3
V
DP, DM, ID high voltage short circuit
DP or DM or ID pins short-circuited to VBUS
supply, in any mode of TUSB1211 operation,
continuously for 24 hours
5.25
V
DP, DM, ID low voltage short circuit
DP or DM or ID pins short-circuited to GND in
any mode of TUSB1211 operation,
continuously for 24 hours
Main battery supply voltage
Continuous
Main battery supply voltage pulsed
–0.3
0
V
VBUS input (3)
–2
TA
Ambient temperature
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
20
V
–40
85
°C
–40
150
°C
–55
125
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 4.3 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If VBAT exceeds above rating a device to drop down the voltage before applied to the device.
If VBUS exceeds above rating an external voltage protection on the line is mandatory between the VBUS line and the TUSB1211.
4.2
ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
4.3
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VBAT
Battery supply voltage
VBAT_ACTIVE
TYP
MAX
2.7
3.6
4.8
When VDD33 is supplied internally
3.15
When VDD33 is shorted to VBAT
externally
3.05
VBAT_CERT
Battery supply voltage for USB 2.0 compliancy
(USB 2.0 certification)
VBAT_DB
Battery supply voltage for charger detect in
“dead-battery condition”
VBAT_DB
VDDIO
IO supply voltage
VDDIO_ACTIVE
TA
Ambient temperature range
TJ
Junction temperature
8
MIN
For parametric compliance
Specifications
V
V
2.4
1.62
UNIT
V
1.95
V
–40
1.8
85
°C
–40
125
°C
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4.4
SLLSE80B – MARCH 2011 – REVISED JUNE 2015
Power Consumption Summary (1) (2)
MODE
CONDITIONS
VBAT = 3.6 V, VDDIO = 1.8 V,
CS = 0 V
OFF
Suspend
HS USB Mode
FS USB Mode
(1)
(2)
4.5
SUPPLY
TYPICAL POWER
CONSUMPTION
IVBAT
8
IVDDIO
1.8
ITOTAL
9.8
IVBAT
251
VBUS = 5 V, VBAT = 3.6 V,
VDDIO = 1.8 V, VCHRG_EN_N = 0 V,
no clock
IVDDIO
21
ITOTAL
272
IVBAT
46.4
VBAT = 3.6 V, VDDIO = 1.8 V,
active USB transfer
IVDDIO
1.3
ITOTAL
47.7
IVBAT
31.4
VBAT = 3.6 V, VDDIO = 1.8 V,
active USB transfer
IVDDIO
1.3
ITOTAL
32.7
UNIT
µA
µA
mA
mA
Describes the power consumption depending on the use cases.
Typical power consumption is obtained in nominal operating conditions of the TUSB1211 device.
Electrical Characteristics – Analog Output Pins
PARAMETER
TEST CONDITIONS
MIN
TYP
100
MAX
UNIT
CHRG_DET OUTPUT PIN
RCDETPUOD
CHRG_DET external pullup
resistor to VBAT
When CHRG_POL pin = GND, that is, in opendrain mode (active-low)
60
VOHCDETOD
CHRG_DET minimum high-level
output voltage
When CHRG_POL pin = GND, that is, in opendrain mode (active-low)
0.7 ×
VBAT
IOHCDETOD
CHRG_DET maximum current
from VBAT
When CHRG_POL pin = GND, that is, in opendrain mode (active-low)
RCDETPDOS
CHRG_DET external pulldown
resistor to GND
When CHRG_POL pin = VBAT, that is, in opensource mode (active-high)
VOLCDETOS
CHRG_DET maximum low-level
output voltage
When CHRG_POL pin = VBAT, that is, in opensource mode (active-high)
IOHCDETOS
CHRG_DET minimum current
from VBAT
When CHRG_POL pin = VBAT, that is, in opensource mode (active-high)
–2
60
kΩ
V
2
60
100
mA
kΩ
0.3 ×
VBAT
V
mA
PSW OUTPUT PIN
RPSWPUOD
PSW external pullup resistor to
VBAT
When configured in open-drain active low mode
VOHPSW
PSW minimum high-level output
voltage
When configured in open-drain active low mode or
CMOS mode
IOHPSWOD
PSW maximum current from
VBAT
When configured in open-drain active low mode
RPSWPDOS
PSW external pulldown resistor
to ground
When configured in open-source active high mode
(default)
VOLPSW
PSW minimum high-level output
voltage
When configured in open-source active high mode
(default) or CMOS mode
IOHPSWOS
PSW maximum current from
VBAT
When configured in open-source active high mode
(default)
100
kΩ
0.7 ×
VBAT
V
2
60
100
kΩ
0.3 ×
VBAT
–2
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V
mA
Specifications
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mA
9
TUSB1211
SLLSE80B – MARCH 2011 – REVISED JUNE 2015
4.6
www.ti.com
Electrical Characteristics – Analog Input Pins
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CHRG_EN_N INPUT PIN
VILCDETENN
CHRG_EN_N maximum low-level input voltage
VIHCDETENN
CHRG_EN_N minimum high-level input voltage
0.3
1.0
V
V
CHRG_POL INPUT PIN
VILCHRG_POL
CHRG_POL maximum low-level input voltage
VIHCHRG_POL
CHRG_POL minimum high-level input voltage
0.3
1.0
V
V
FAULT INPUT PIN
VILFAULT
FAULT maximum low-level input voltage
VIHFAULT
FAULT minimum high-level input voltage
4.7
0.3
1.0
V
V
Digital I/O Electrical Characteristics – Non-ULPI Pins
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CLOCK
VOL
Low-level input voltage
VOH
High-level input voltage
Frequency = 60 MHz, Load = 10 pF
0.4
VDDIO – 0.45
V
V
STP, DIR, NXT, DATA0 to DATA7
VOL
Low-level input voltage
VOH
High-level input voltage
4.8
Frequency = 360 MHz, Load = 10 pF
0.45
VDDIO – 0.45
V
V
Digital I/O Electrical Characteristics – Non-ULPI Pins
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CS, CFG, RESETB INPUT PINS
VIL
Maximum low-level input voltage
VIH
Minimum high-level input voltage
0.35 × VDDIO
V
0.65 × VDDIO
V
0.2
µs
RESET_N INPUT PIN TIMING SPECIFICATION
tw(POR)
Internal power-on reset pulse width
tw(RESET)
External RESET_N pulse width
4.9
VIL
Low level input voltage
VIH
High level input voltage
10
CLOCK
cycles
8
Electrical Characteristics – REFCLK
PARAMETER
(1)
Applied to external RESET_N pin when
CLOCK is toggling.
TEST CONDITIONS
MIN (1)
TYP
MAX (1)
0.35 × VDDIO
0.65 × VDDIO
UNIT
V
V
VDDIO voltage level = 1.8 V
Specifications
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4.10 Electrical Characteristics – CLOCK Input
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
CLOCK input duty cycle
MIN
TYP
MAX
40%
60%
FCLOCK CLOCK nominal frequency
CLOCK input rise/fall time
UNIT
60
MHz
In % of CLOCK period TCLOCK ( = 1/FCLOCK )
10%
CLOCK input frequency accuracy
250
ppm
CLOCK input integrated jitter
600
ps rms
MAX
UNIT
4.11 Electrical Characteristics – REFCLK
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
REFCLK input duty cycle
MIN
TYP
40%
FREFCLK REFCLK nominal frequency
REFCLK input rise/fall time
60%
When CFG pin is tied to GND
19.2
When CFG pin is tied to VDDIO
MHz
26
In % of REFCLK period TREFCLK ( = 1/FREFCLK )
20%
REFCLK input freq accuracy
250
ppm
REFCLK input integrated jitter
600
ps rms
4.12 Electrical Characteristics – CK32K Clock Generator
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
Output duty cycle
PARAMETER
TEST CONDITIONS
48%
50%
52%
Output frequency
23
32.7
38
UNIT
kHz
4.13 Thermal Characteristics
THERMAL METRIC (1)
TUSB1211
ZRQ (BGA MICROSTAR JUNIOR)
UNIT
36 PINS
RθJA
Junction-to-ambient thermal resistance (2)
69.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance (3) (4)
41
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance (4) (5)
N/A
°C/W
RθJB
Junction-to-board thermal resistance or junction-to-pin thermal
resistance (6)
42
°C/W
0.9
°C/W
71
°C/W
ΨJT
ΨJB
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Junction-to-top of package (not a true thermal resistance)
Junction-to-board (not a true thermal resistance)
(7)
(8)
For more information about traditional and new thermal metrics, see the application report, Semiconductor and IC Package Thermal
Metrics (SPRA953).
Measurement method: EIA/JESD 51-1
Top is surface of the package facing away from the PCB.
No current JEDEC specification (see the application report, Semiconductor and IC Package Thermal Metrics (SPRA953).
Bottom surface is the surface of the package facing towards the PCB.
Measurement method: EIA/ JESD 51-8
Measurement method: EIA/JESD 51-2
Measurement method: EIA/JESD 51-6
Specifications
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4.14 REG3V3 Internal LDO Regulator Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VINREG3V3
Input voltage
Output voltage
ACTIVE mode
VVDD33
TEST CONDITIONS
VBAT
MIN
TYP
MAX
VOUT(typ) + 0.15
3.6
4.8
On mode – REG3V3_VSEL = ‘000
2.4
2.5
2.6
On mode – REG3V3_VSEL = ‘001
2.65
2.75
2.85
On mode – REG3V3_VSEL = ‘010
2.9
3.
3.1
On mode – REG3V3_VSEL = ‘011
(default)
3
3.1
3.2
On mode – REG3V3_VSEL = ‘100
3.1
3.2
3.3
On mode – REG3V3_VSEL = ‘101
3.2
3.3
3.4
On mode – REG3V3_VSEL = ‘110
3.3
3.4
3.5
On mode – REG3V3_VSEL = ‘111
3.4
3.5
3.6
VBAT – 0.05
VBAT
VBAT + 0.05
3
3.1
3.2
VVDD33_DB
Output voltage
hardware charger
detection
(dead battery) mode
VBAT_DB < VBAT < 3.1 V
IREG3V3
Rated output current
VBAT: ACTIVE mode,
Hardware charger detection (dead battery)
mode
IREG3V3_SUSP
Rated output current:
IREG3V3_SUSP
Suspend mode/reset mode
VBAT > 3.1 V
UNIT
V
V
V
15
mA
1
mA
4.15 REG1V8 Internal LDO Regulator Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VINREG1V8
Input voltage
VREG1V8
Output voltage
IREG1V8
Rated output current
TEST CONDITIONS
On mode : VINREG1V8 = VBAT
MIN
TYP
MAX
2.4
3.6
4.8
1.75
1.87
1.98
On mode
30
UNIT
V
V
mA
4.16 REG1V5 Internal LDO Regulator Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VINREG1V8
Input voltage
VREG1V8
Output voltage
IREG1V8
Rated output current
12
TEST CONDITIONS
On mode : VINREG1V8 = VBAT
On mode
Specifications
MIN
TYP
MAX
2.4
3.6
4.8
V
1.45
1.56
1.65
V
50
UNIT
mA
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4.17 Timers and Debounce
over operating free-air temperature range (unless otherwise noted)
NB CK32K
CYCLES
PARAMETER
TDEL_CS_SUPPLYOK Chip-select-to-Supplies ok delay
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
N/A
4.19
ms
TDEL_RST_DIR
Resetb to PHY PLL locked and DIR
falling-edge delay
N/A
0.42
ms
TVBAT_DET
VBAT detection delay
N/A
10.0
µs
TBGAP
Bandgap power-on delay
N/A
2.0
ms
TPWONREG1V5
REG1V5 power-on delay
N/A
100.0
µs
TPWONREG1V8
REG1V8 power-on delay
N/A
100.0
µs
TPWONVREG3V3
REG3V3 power-on delay
N/A
1.0
ms
TPWONCK32K
32KHz RC-OSC power-on delay
N/A
TDELRSTPWR
Power control reset delay
2
TDELMNTRVIOEN
Monitor enable delay
3
TMNTR
Supply monitoring debounce
6
TDELREG3V3EN
REG3V3 LDO enable delay
3
TDELRESET_N
RESET_N internal delay
4
TPLL
PLL Lock time
TERROR_DELAY
125.0
52.6
87.0
µs
78.9
91.6
130.4
µs
157.9
183.1
260.9
µs
78.9
91.6
130.4
µs
105.3
122.1
173.9
µs
N/A
PWR FSM ERROR state delay
Min 4100
Max 8196
µs
61.0
300.0
107.9
125.1
µs
356.3
Specifications
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4.18 OTG VBUS Electrical
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
RVBUS = 0 Ω and R1KSERIES = 0
4.4
4.5
4.625
RVBUS = 1000 Ω ±10% and
R1KSERIES = 1
4.4
4.5
4.625
RVBUS = 1200 Ω ±10% and
R1KSERIES = 1
4.4
4.5
4.625
RVBUS = 1800 Ω ±10% and
R1KSERIES = 1
4.4
4.5
4.675
VBUS COMPARATORS
VA_VBUS_VLD
A-device VBUS valid
V
VSESS_VLD
A-device session valid
0.8
1.4
2.0
V
VB_SESS_VLD
B-device session valid
2.1
2.4
2.7
V
VB_SESS_END
B-device session end
0.2
0.5
0.8
V
VBUS LINE
A-device VBUS input
impedance to ground
SRP (VBUS pulsing) capable A-device not driving
VBUS,
For VBUS < VSESS_VLD, (When bit RABUSIN_EN=1
RVBUS_IDLE_A / RVUS_IDLE_A_HI_RANGE impedance
controlled automatically by hardware)
40
100
kΩ
RVUS_IDLE_A_HI_RANGE
A-device VBUS input
impedance to ground (for
VBUS hi-range)
SRP (VBUS pulsing) capable A-device not driving
VBUS
For VBUS > VSESS_VLD
(When bit RABUSIN_EN=1 RVBUS_IDLE_A /
RVUS_IDLE_A_HI_RANGE impedance controlled
automatically by hardware)
70
100
kΩ
RVBUS_IDLE_B
B-device VBUS input
impedance to ground
When bit RABUSIN_EN = 0
For VBUS in range [0 V : 20 V]
(Not valid for negative values of VBUS)
RB_SRP_DWN
B-device VBUS SRP
pulldown
RB_SRP_UP
B-device VBUS SRP pullup
RVBUS_IDLE_A
tRISE_SRP_UP_MAX
B-device VBUS SRP rise
time maximum for OTG-A
communication
0 to 2.1 V
with < 13 μF
load,
tRISE_SRP_UP_MIN
0.8 to 2.0 V
with > 97 μF
load,
400
kΩ
5
10
20
kΩ
0.85
1.3
1.75
kΩ
31.4
RVBUS = 1000 Ω ±10% and
R1KSERIES = 1
57.8
RVBUS = 1200 Ω ±10% and
R1KSERIES = 1
64
RVBUS = 1800 Ω ±10% and
R1KSERIES = 1
85.4
ms
46.2
RVBUS = 1000 Ω ±10% and
R1KSERIES = 1
96
RVBUS = 1200 Ω ±10% and
R1KSERIES = 1
100
RVBUS = 1800 Ω ±10% and
R1KSERIES = 1
100
VBUS line maximum
voltage
14
220
RVBUS = 0 Ω and
R1KSERIES = 0
RVBUS = 0 Ω and
R1KSERIES = 0
B-device VBUS SRP rise
time minimum for
standard host connection
150
ms
–2
Specifications
20
V
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4.19 LS/FS Single-Ended Receivers
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
–2
0
2
UNIT
USB SINGLE-ENDED RECEIVERS
SKWVP_VM
Skew between VP and VM
VSE_HYS
Single-ended hysteresis
VIH
High (driven)
VIL
Low
Driver outputs unloaded
ns
50
mV
2
V
0.8
V
4.20 LS/FS Differential Receiver
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VDI
Differential Input Sensitivity
Ref. USB2.0
200
VCM
Differential Common Mode Range
Ref. USB2.0
0.8
TYP
MAX
UNIT
mV
2.5
V
4.21 LS Transmitter
over operating free-air temperature range (unless otherwise noted)
MAX
UNIT
VOL
Low
PARAMETER
Ref. USB2.0
0
300
mV
VOH
High (driven)
Ref. USB2.0
2.8
3.6
V
VCRS
Output signal crossover voltage
Ref. USB2.0
1.3
2
V
TFR
Rise time
Ref. USB2.0,
covered by eye diagram
75
300
ns
TFF
Fall time
Ref. USB2.0,
covered by eye diagram
75
300
ns
TFRFM
Differential rise and fall time matching
TFDRATE
Low-speed data rate
Total source jitter
(including frequency tolerance):
TEST CONDITIONS
Ref. USB2.0, covered by eye
diagram
TDJ1
To next transition
TDJ2
For paired transitions
TFEOPT
Source SE0 interval of EOP
Ref. USB2.0,
covered by eye diagram
Downstream eye diagram
Ref. USB2.0,
covered by eye diagram
Differential common mode range
Ref. USB2.0
VCM
MIN
TYP
80%
125%
1.4775
1.5225
–25
25
–10
10
1.25
1.5
µs
0.8
2.5
V
Mb/s
ns
4.22 FS Transmitter
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOL
Low
Ref. USB2.0
0
300
mV
VOH
High (driven)
Ref. USB2.0
2.8
3.6
V
VCRS
Output signal crossover voltage
Ref. USB2.0
1.3
2
V
TFR
Rise time
Ref. USB2.0,
covered by eye diagram
4
20
ns
TFF
Fall time
Ref. USB2.0
4
20
ns
TFRFM
Differential rise and fall time matching
Ref. USB2.0,
covered by eye diagram
90%
111.11%
ZDRV
Driver output resistance
Ref. USB2.0
28
44
Full-speed data rate
Ref. USB2.0,
covered by eye diagram
11.97
12.03
TFDRATE
Specifications
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FS Transmitter (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Total source jitter
(including frequency tolerance):
TDJ1
To next transition
TDJ2
For paired transitions
TFEOPT
Source SE0 interval of EOP
Downstream eye diagram
Upstream eye diagram
TEST CONDITIONS
MIN
Ref. USB2.0,
covered by eye diagram
Ref. USB2.0,
covered by eye diagram
TYP
MAX
–2
2
–1
1
160
175
UNIT
ns
ns
Ref. USB2.0,
covered by eye diagram
4.23 HS Transmitter
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VHSOI
High-speed idle level
Ref. USB2.0
–10
10
mV
VHSOH
High-speed data signaling high
Ref. USB2.0
360
440
mV
VHSOL
High-speed data signaling low
Ref. USB2.0
–10
10
mV
VCHIRPJ
Chirp J level (differential voltage)
Ref. USB2.0
700
1100
mV
VCHIRPK
Chirp K level (differential voltage)
Ref. USB2.0
–825
–500
mV
Rise time (10% to 90%)
THSR
Fall time (10% to 90%)
ZHSDRV
Driver output resistance
(which also serves as high-speed
termination)
THSDRAT High-speed data range
16
Ref. USB2.0, covered by eye diagram
Ref. USB2.0
Ref. USB2.0, covered by eye diagram
Data source jitter
Ref. USB2.0, covered by eye diagram
Downstream eye diagram
Ref. USB2.0, covered by eye diagram
Upstream eye diagram
Ref. USB2.0, covered by eye diagram
Specifications
500
ps
500
40.5
49.5
479.76
480.24
Ω
Mb/s
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4.24 Pullup and Pulldown Resistors
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.9
1.1
1.575
kΩ
1.425
2.2
3.09
PULLUP RESISTORS
RPUI
Bus pullup resistor on upstream port (idle bus)
Bus idle
RPUA
Bus pullup resistor on upstream port (receiving)
Bus driven, outputs of the driver
unloaded
VIHZ
High (floating)
Pullups and pulldowns on both DP
and DM lines
VPH_DP_UP
DP pullup voltage
Outputs of the driver unloaded
3
DP/DM pulldown
Outputs of the driver unloaded
14.25
High (floating)
Pullups and pulldowns on both DP
and DM lines
2.7
3.6
V
3.3
3.6
V
18
24.8
kΩ
3.6
V
0.342
V
PULLDOWN RESISTORS
RPH_DP_DWN
RPH_DM_DWN
VIHZ
2.7
DP/-DATA LINE
VOTG_DATA_LKG
On-the-go device leakage
Input impedance exclusive of pullup and
pulldown
ZINP
Outputs of the driver unloaded,
Measured at VDP or VDM = 0.8 V,
and 2.0 V
800
Measured at VBAT > VBAT_CERT
105
kΩ
CHARGER DETECTION PULLUP RESISTOR
RDP_WK_PU
DP weak pullup resistor
150
195
kΩ
4.25 Autoresume Watchdog Timer
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TAUTORESUME
NB CK32K cycles
Autoresume time-out
TEST
CONDITIONS
918
MIN
TYP
MAX
UNIT
20.0
28.0
46.7
ms
4.26 UART Transceiver
over operating free-air temperature range (unless otherwise noted)
PARAMETER
COMMENTS
MIN
TYP
MAX
UNIT
VVDD33 – 0.4
VVDD33 – 0.1
9600
3.6
bps
V
0.1
0.4
V
UART TRANSMITTER AT DM PIN
fUART_DFLT
UART signaling rate
VOH_UART
UART interface output high
ISOURCE = 4 mA
VOL_UART
UART interface output low
ISINK = –4 mA
0
2
UART RECEIVER AT DP PIN
VIH_UART
UART interface input high
DP_PULLDOWN asserted
VIL_UART
UART interface input low
DP_PULLDOWN asserted
V
0.8
V
4.27 OTG ID Electrical
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ID COMPARATORS — ID EXTERNAL RESISTORS SPECIFICATIONS
RID_FLOAT
ID pulldown, when ID pin is floating
Input spec for external ID resistor
220
RID_A
ACA ID pulldown, TUSB1211 is ADevice
kΩ
Input spec for external ID resistor
119
132
kΩ
RID_B
ACA ID pulldown, TUSB1211 is BDevice, but can’t connect
Input spec for external ID resistor
65
72
kΩ
RID_C
ACA ID pulldown, TUSB1211 is BDevice, can connect
Input spec for external ID resistor
35
39
kΩ
RIDGND
ID pulldown when ID pin is grounded
Input spec for external ID resistor
1
kΩ
60
kΩ
ID DETECTION CIRCUITRY
RID_UP
ID pullup resistor
ID_PULLUP = ‘1, ID_WKPU = ‘0,
Measured for V(ID) = [0.9,2.7]V
40
50
Specifications
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OTG ID Electrical (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
300
400
500
kΩ
RID_UP_WK
ID weak pullup resistor
ID_PULLUP = ‘1, ID_WKPU = ‘1,
Measured for V(ID) = [0.9,2.7]V
ID_R_ID_A_TO_FLOA
T
ID R_ID_A_TO_FLOAT comparator
threshold
Internal ID comparator threshold
132
182
220
kΩ
ID_R_ID_B_TO_A
ID R_ID_B_TO_A comparator threshold
Internal ID comparator threshold
72
103
119
kΩ
ID_R_ID_C_TO_B
ID R_ID_C_TO_B comparator threshold
Internal ID comparator threshold
39
55
65
kΩ
ID_R_ID_GND_TO_C
ID ground-to-RID_C detection
comparator threshold
Internal ID comparator threshold ID_PULLUP = ‘1,
ID_WKPU = ‘1
20
27
30
kΩ
VIDGND-to-RID_C
ID ground-to-RID_C voltage detection
threshold
ID_PULLUP = ‘1, ID_WKPU = ‘1,
Valid for VBAT > VBAT_CERT max
0.9
1.05
2.0
V
VID_MAX
ID line maximum rated voltage
5.25
V
tID_DEB
tID_MASK
18
ID detection debounce time
Min 48 cycles of CK32K clock
Max 64 cycles of CK32K clock
ID detection mask
ID detection is masked for tID_MASK after
IDPULLUP=1 or IDPULLUP_WK_EN=1 bits are
enabled.
Min 1120 cycles of CK32K clock
Max 1152 cycles of CK32K clock During mask time
TUSB1211 will indicate ID is grounded (ULPI RX CMD
Bit6 = ID = 0).
Specifications
1.3
1.5
2.8
ms
29.5
35.2
50.0
ms
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4.28 Electrical Specs – Charger Detection Currents
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ISUSP
(USB BC Ver1.1
spec)
VBUS maximum current in dead battery.
Maximum current the device is allowed to draw
from VBUS in dead battery condition if VDP_SRC is
not asserted
IVBAT_DET
VBAT maximum current during battery charger
detection
IDP_SRC
Data contact detect current source
IDM_SINK
DM sink current
IDEV_HCHG_CHRP
Portable device current from charging
downstream port during chirp
IVDP_SRC_ILIM
DP voltage source current limitation
MIN
TYP
Averaged over 1 s
MAX
UNIT
1
mA
550
µA
7
13
µA
50
150
µA
Refer to USB Battery
Charging spec V1.1 Ch6.3.2
and values of VHSCM, and
VCHIRPK
710
mA
VDP = 0 V
800
µA
MAX
UNIT
450
4.29 Electrical Specs – Resistance
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
RDP_DWN
DP pulldown resistance
14.25
24.8
kΩ
RDM_DWN
DP pulldown resistance
14.25
24.8
kΩ
RDCHG_DAT
Dedicated charging port resistance across DP/DM
(input spec to TUSB1211)
200
Ω
RDCHRGR_PWR
Dedicated charging port resistance from DP/DM to
VBUS/GND (input spec to TUSB1211)
2
MΩ
4.30 Electrical Specs – Capacitance
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Dedicated charging port capacitance from DP or
DP to VBUS or GND (input spec to TUSB1211)
CDCHG_PWR
MAX
1
UNIT
nF
4.31 Charger Detection Debounce and Wait Timing
over operating free-air temperature range (unless otherwise noted)
PARAMETER
NB
CK32K
CYCLES
TEST CONDITIONS
BC1.1
SPEC
MIN
TYP
MAX
UNIT
ms
DEBVBUS_TIME
VBUS debounce time
459
> 10
12.1
14.0
20.0
TIDP_SRC_ON
DP Current source on-time
8
> 200
210.5
244.1
347.8
µA
TVDP_SRC_ON
DP Voltage source on-time
1792
> 40
47.2
54.7
77.9
ms
TVDP_SRC_HICRNT
DP Voltage source off to high
current on charger delay
1792
> 40
47.2
54.7
77.9
ms
TDCD_TIMEOUT
Data contact detect timeout
89400
>2
2.4
2.7
3.9
s
TSVLD_CON_WKB
Session valid to connect for
peripheral with dead or weak
battery
Used to generate
SVLDCONWKB_CNTR in FSM
< 45
27.0
23.3
38.5
min
TVDPSRC_CON
DP voltage source off to
connect delay
N/A
Input spec
> 40
N/A
N/A
N/A
ms
TVDPSRC_DEB
VDP_SRC comparator
debounce time
760
Used to generate
CHGD_VDM_DEB in FSM
N/A
20.0
23.2
33.0
ms
TCHGD_SERX_DEB
Charger detect SERX debounce
time
1520
Used to generate
CHGD_SERX_DP_DEB and
CHGD_SERX_DM_DEB in FSM
N/A
40.0
46.4
66.1
ms
TACA_SETUP
ACA setup time
2300
N/A
60.5
70.2
100.0
ms
TID_RARBRC_DEB
ACA ID RA, RB, RC
comparators debounce
N/A
40.0
46.4
66.1
ms
53084160
1520
Used to generate
ID_RARBRC_DEB in FSM
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4.32 ULPI Interface
4.32.1 ULPI Interface Timing
Table 4-1. ULPI Interface Timing
PARAMETER
SYMBOL
MIN
MAX
UNIT
OUTPUT CLOCK
Setup time (control in, 8-bit data in)
TSC, TSD
Hold time (control in, 8-bit data in)
TSC, THD
Output Delay (control out, 8-bit data out)
TDC, TDD
6
0
ns
ns
6.5
ns
3
ns
INPUT CLOCK
Setup time (control in, 8-bit data in)
TSC, TSD
Hold time (control in, 8-bit data in)
TSC, THD
Output Delay (control out, 8-bit data out)
TDC, TDD
1.5
ns
6
ns
4.33 Power-On Timing Diagrams
4.33.1 Standard Power-up Timing
This scenario corresponds to standard power-up of TUSB1211 device in presence of valid VBAT, VIO, and chip
selected (CS = 1 and CS_N = 0).
A timing diagram for standard power up is shown in Figure 4-1. In this plot USB ULPI clock is configured in
output mode. A suggested application diagram for this configuration is shown in Section 6.
20
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NOTE
The ULPI clock can also be configured in input mode, see Figure 4-1 for details.
TUS1211
STATE=>
NO
PWR
OFF
HWRST
ACTIVE
COLDRST
ACTIVE
VBAT
VDDIO
VUPR
CS
CS_N
TVBBDET (10 ms)
VREF
TBGAP (2 ms)
BGOK
TPWONVDD1V5 (100 ms)
VDD1V5
DIGPOR
CK32K
TCK32K_PWON (125 ms)
CK32KOK
TDELRSTPWR (61 ms)
RESETN_PWR
TDELMNTRVBATEN (30.5 ms)
MNTR_BAT_OK
TMNTR (214 ms)
TDELREG1V8EN (61 ms)
REG1V8_EN
TPWONVREG1V8 (100 ms)
REG1V8
TMNTR (214 ms)
MNTR_REG1V8_OK
TDELREG3V3EN (61 ms)
REG3V3_EN
TPWONREG3V3 (1 ms)
VCC3V3
TMNTR (214 ms)
MNTR_REG3V3_OK
(91.5 ms)
(30.5 ms)
PORZ
REFCLK
TCLKDET (122 ms)
TCLKSTART (200 ns)
PLLREFCLK
TCLKSTART (200 ns)
TCLKDET (122 ms)
RESET_N
TPLL (300 ms)
TDELRESET_N (122 ms)
PLL 480M LOCKED
DIR
DATA(0:7)
KEY:
Blue = Primary IOs
TPLL (300 ms)
Internal Weak PU on DIR
Internal Weak PD on DATA(0:7)
TDEL_CS_SUPPLYOK (4.190 ms)
TDEL_RST_DIR (0.422 ms)
Black = Internal Signals
Figure 4-1. Power-Up Timing: (ULPI Clock Output Mode), Normal Battery
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4.33.2 Hardware Charger Detection Power-Up Timing
This scenario corresponds to “dead battery” scenario in USB Battery Charging Specification V1.1.
Here VBUS is plugged while chip is not enabled (CS = 0 or CS_N = 1 or both), with VBAT > VBAT_DET. This
causes the device to power up to and initiate Charger Detection through hardware. See Section 5.3.12 for
details.
TUSB1211
STATE
NO
PWR
POWER
DOWN
PWR
UP
USB OFF
LDO1
P8EN
USB
ON
LDO3P1EN
CHARGER
DETECTION
VBAT
VDDIO
VUPR
CS
CS_N
CHRG_EN_N
VBUS
TVBUSDET (10 ms)
VREF
TBGAP (2 ms)
BGOK
TPWONVDD1V5 (100 ms)
REG1V5
DIGPOR
CK32K
TCK32K PWON (125 ms)
CK32KOK
TDELRSTPWR (61 ms)
RESETN_PWR
TDELMNTRVBATEN (30.5 ms)
MNTR_BAT_OK
MNTR_BUS_OK
REG1V8_EN
REG1V8
MNTR_REG1V8_OK
TMNTR (214 ms)
TMNTR_VBUS (14 ms)
TDELREG1V8EN (61 ms)
TPWONVREG1V8 (100 ms)
TMNTR (214 ms)
TDELREG3V3EN
(61 ms)
us)
REG3V3_EN
TPWONREG3V3 (1 ms)
REG3V3
TMNTR (214 ms)
MNTR_REG3V3_OK
PORZ
TCHG_DEL (61 ms)
CHGD_VDP_SRC_EN
600 mV
DP
Depending on external DP/DM short
DM
KEY:
Blue = Primary IOs
Black = Internal Signals
Figure 4-2. Power-Up Timing (ULPI Clock Output Mode), "Dead" Battery
22
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4.34 Clock System
4.34.1 USB PLL Reference Clock
The USB PLL block generates the clocks used to synchronize:
• the ULPI interface (60 MHz clock)
• the USB interface (depending on the USB data rate, 480 Mbps, 12 Mbps or 1.5 Mbps)
TUSB1211 requires an external reference clock which is used as an input to the 480MHz USB PLL block.
Depending on the clock configuration, this reference clock can be provided either at REFCLK pin or at CLOCK
pin.
By default CLOCK pin is configured as an input.
Two clock configurations are possible:
• Input clock configuration (see Section 4.34.1.1)
• Output clock configuration (see Section 4.34.1.2)
4.34.1.1 ULPI Input Clock Configuration
In this mode REFCLK must be externally tied to GND.
CLOCK remains configured as an input.
When the ULPI interface is used in “input clock configuration”, that is, the 60 MHz ULPI clock is provided to
TUSB1211 on CLOCK pin, then this is used as the reference clock for the 480 MHz USB PLL block.
4.34.1.2 ULPI Output Clock Configuration
In this mode a reference clock must be externally provided on REFCLK pin.
When an input clock is detected on REFCLK pin then CLOCK will automatically change to an output, that is, 60
MHz ULPI clock is output by TUSB1211 on CLOCK pin.
Two reference clock input frequencies are supported. REFCLK input frequency is communicated to TUSB1211
through a configuration pin, CFG, see FREFCLK in Section 4.11 for frequency correspondence.
TUSB1211 supports square-wave reference clock input only.
4.35 Clock System
4.35.1 Internal Clock Generator (32 kHz)
An internal clock generator running at 32 kHz has been implemented to provide a low speed low power clock to
the system. This is referred to as CK32K elsewhere in this specification.
4.36 Power Management
This chapter describes the electrical characteristics of the voltage regulators and timing characteristics of the
supplies digitally controlled within the TUSB1211 device.
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4.36.1 Power Provider
Table 4-2. Summary of Internal Power Providers (1)
(1)
SUPPLY NAME
PIN NAME
TYPE
TYPICAL VOLTAGE (V)
REG1V5
REG1V5
LDO
1.5
REG1V8
—
LDO
1.8
REG3V3
REG3V3
LDO
3.1
REG3V3 may be supplied externally, or by shorting the REG3V3 pin to VBAT pin provided VBAT min
is in range [3.2 V : 3.6 V]. Note that the REG3V3 LDO will always power-on when the chip is enabled,
irrespective of whether VDD33 is supplied externally or not.
4.37 Power Provider
Table 4-3. Summary of the Power Provider
LDO NAME
PIN NAME
USAGE
TYPE
TYPICAL VOLTAGE (V)
MAXIMUM CURRENT
REG1V5
REG1V5
Internal
LDO
1.5
50 mA
REG1V8
—
Internal (capless)
LDO
1.8
30 mA
REG3V3
REG3V3
Internal
LDO
3.1
15 mA
4.37.1 REG3V3 Regulator
The REG3V3 internal LDO regulator powers the USB PHY, Charger detection, and OTG functions of the USB
subchip inside TUSB1211.
It takes its power from the VBAT pin. It is connected to an external filtering capacitor at the REG3V3 pin (E3).
The USB standard requires data lines to be biased with pullups powered from a >3.0 V supply. Hence
TUSB1211 cannot be guaranteed USB2.0 compliant for VBAT voltage lower than VBAT_CERT. TUSB1211 will
however keep operating below this voltage.
4.37.2
REG1V8 Regulator
The REG1V8 internal LDO regulator powers the USB PHY, and USB PLL.
It takes its power from the VBAT pin. This LDO is capless, that is, its output is not connected to any external pin.
Section 4.15 describes its characteristics.
4.37.3
REG1V5 Regulator
The REG1V5 internal LDO regulator powers the USB PHY and internal digital circuitry of TUSB1211.
Section 4.16 describes the regulator characteristics.
It takes its power from the VBAT pin. It is connected to an external filtering capacitor at the REG1V5 pin (E6).
24
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4.38 Power Control
TUSB1211 can be powered up in two different modes:
• Standard power-up condition
For this, VBAT and VIO must be present and chip must be selected (CS=1 and CS_N=0). See Section 4.33.1.
Standard Power-up Timing Power resources will be configured sequentially until the device reaches the
power state.
USBON . At this time internal power-on-reset signal PORZ will be released and USB PLL will start up. Once
PLL is locked, the DIR output pin will be deasserted allowing TUSB1211 to be configured by the USB Link
Controller through the ULPI interface.
Note that by default TUSB1211 will be configured as a Host not providing VBUS as required by register map
in ULPI specification Rev1.1.
This is the case because OTG_CONTROL register bits DRVVBUS and DRVVBUSEXTERNAL bits are 0 by
default, and DPPULLDOWN, DMPULLDOWN bits are 1 by default such that the 15 kΩ pulldown resistors at
DP/DM pins are enabled by default.
It is the responsibility of the link to enable external VBUS supply if required in Host mode, or to reconfigure
the PHY if required in Device mode.
• Hardware charger detection power-up
When the chip is not selected (CS=0 or CS_N=1), but VBUS is present and CHRG_EN_N pin is at GND, and
VBAT > VBAT_MNTR then TUSB1211 will power-up in Hardware Charger Detection Mode.
Power resources will be configured sequentially until the device reaches the power state USBON. However,
because the chip is not selected, the internal power-on-reset signal PORZ will be not be released and USB
PLL will not start up. Instead the device will enter the USB battery charger finite state machine (FSM) .
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5 Detailed Description
5.1
Overview
The TUSB1211 device is optimized to be interfaced through a 12-pin SDR UTMI Low Pin Interface (ULPI),
supporting both input clock and output clock modes, with 1.8 V interface supply voltage. The TUSB1211
device integrates a 3.3-V LDO, which makes it flexible to work with either battery operated systems or
pure 3.3-V supplied systems. Both the main supply and the 3.3-V power domain can be supplied through
an external switched-mode converter for optimized power efficiency.
The TUSB1211 device includes a POR circuit to detect supply presence on VBAT and VDDIO pins. The
TUSB1211 device can be disabled or configured in low power mode for energy saving.
The TUSB1211 device is protected against accidental shorts to 5 V or ground on its exposed interface
(DP/DM/ID). It is also protected against up to 20-V surges on VBUS.
The TUSB1211 device also supports the OTG (Ver1.3) optional addendum to the USB2.0 specification,
including host negotiation protocol (HNP) and session request protocol (SRP).
The TUSB1211 device integrates a high-performance low-jitter 480-MHz PLL and supports two clock
configurations. Depending on the required link configuration, the TUSB1211 device supports both ULPI
input and output clock mode: input clock mode, in which case a square-wave 60-MHz clock is provided to
TUSB1211 at the ULPI interface CLOCK pin; and output clock mode in which case the TUSB1211 device
can accept a square-wave reference clock at REFCLK of either 19.2 MHz or 26 MHz. Frequency is
indicated to the TUSB1211 device through the configuration pin CFG, which can be useful if a reference
clock is already available in the system.
5.2
Functional Block Diagram
5.3
Feature Description
5.3.1
USB On-The-Go (OTG) Feature
The on-the-go (OTG) block integrates two main functions:
• ID resistor detection including Accessory Charger Adapter (ACA) detection
• VBUS level detection and SRP pullup/pulldown resistors
26
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5.3.2
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VBUS Detection Status Bits vs VBUS Comparators
Four VBUS comparators permit detection of four VBUS levels as described in Table 5-1.
Table 5-1. VBUS Detection Status Bits vs VBUS Comparators
5.3.3
VBUS COMPARATOR
DETECTION STATUS BIT
DETECTION BIT LOGIC
VA_VBUS_VLD
VBUSVALID
VBUSVALID = 1 if VBUS > VA_VBUS_VLD else 0
VSESS_VLD
SESSVALID
SESSVALID = 1 if VBUS > VSESS_VLD else 0
VB_SESS_VLD
BVALID_STS
BVALID_STS = 1 if VBUS > VB_SESS_VLD else 0
VB_SESS_END
SESSEND
SESSEND = 0 if VBUS > VB_SESS_END else 1
USB Transceiver (PHY)
The TUSB1211 device includes a universal serial bus (USB) on-the-go (OTG) transceiver that supports
USB 480-Mb/s high-speed (HS), 1-Mb/s full-speed (FS), and USB 1.5-Mb/s low-speed (LS) through a
12-pin UTMI+ low pin interface (ULPI).
NOTE
LS device mode is not allowed by a USB2.0 HS capable PHY, therefore it is not supported
by the TUSB1211 device. This is clearly stated in USB2.0 standard Chapter 7, page 119,
second paragraph: “A high-speed capable upstream facing transceiver must not support lowspeed signaling mode..” There is also some related commentary in Chapter 7.1.2.3.
Table 5-2. Interface Target Frequencies
IO INTERFACE
INTERFACE DESIGNATION
High speed
USB
Universal serial bus
TARGET FREQUENCY
480 Mbits/s
Full speed
12 Mbits/s
Low speed
1.5 Mbits/s
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5.3.3.1
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PHY Overview
The PHY is the physical signaling layer of the USB 2.0. It essentially contains all the drivers and receivers
required for physical data and protocol signaling on the DP and DM lines.
The PHY interfaces to the USB controller through a standard 12-pin digital interface called UTMI+ low pin
interface (ULPI).
The transmitters and receivers inside the PHY are classified into two main classes.
• The full-speed (FS) and low-speed (LS) transceivers. These are the legacy USB1.x transceivers.
• The HS (HS) transceivers
To bias the transistors and run the logic, the PHY also contains reference generation circuitry which
consists of:
• A PLL which does a frequency multiplication to achieve the 480-MHz low-jitter clock necessary for
USB and also the clock required for the switched capacitor resistance block.
• Internal biasing circuitry
Built-in pullup and pulldown resistors are used as part of the protocol signaling.
Apart from this, the PHY also contains circuitry which protects it from accidental short on the DP and DM
lines to 5 V or GND.
5.3.4
LS/FS Single-Ended Receivers
In addition to the differential receiver, there is a single-ended receiver (SE–, SE+) for each of the two data
lines DP/–. The main purpose of the single-ended receivers is to qualify the DP and DM signals in the fullspeed/low-speed modes of operation.
5.3.5
LS/FS Differential Receiver
A differential input receiver (Rx) retrieves the LS/FS differential data signaling. The differential voltage on
the line is converted into digital data by a differential comparator on DP/DM. This data is then sent to a
clock and data recovery circuit that recovers the clock from the data. An additional serial mode exists in
which the differential data is directly output on the RXRCV pin.
5.3.6
LS/FS Transmitter
The USB transceiver (Tx) uses a differential output driver to drive the USB data signal DP/– onto the USB
cable. The driver’s outputs support 3-state operation to achieve bidirectional half-duplex transactions.
5.3.7
HS Differential Receiver
The HS receiver consists of the following blocks:
• A differential input comparator to receive the serial data
• A squelch detector to qualify the received data
• An oversampler-based clock data recovery scheme followed by a NRZI decoder, bit unstuffing, and
serial-to-parallel converter to generate the ULPI DATAOUT
28
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Table 5-3. HS Differential Receiver
PARAMETER
TEST CONDITIONS
VHSSQ
High-speed squelch detection threshold (differential
signal amplitude)
Ref. USB2.0
VHSDSC
High-speed disconnect detection threshold (differential
signal amplitude)
Ref. USB2.0
High-speed differential input signaling levels
Ref. USB2.0, specified by eye pattern
templates
High-speed data signaling common mode voltage range
(guidelines for receiver)
Ref. USB2.0
Receiver jitter tolerance
Ref. USB2.0, specified by eye pattern
templates
VHSCM
(1)
MIN
TYP
MAX
UNIT
100
150
mV
525
625
mV
mV
–50
500
(1)
150
mV
ps
For low-frequency Chirp signaling, the max common mode voltage range value is 600 mV
5.3.8
HS Differential Transmitter
The HS transmitter is always operated through the ULPI parallel interface. The parallel data on the
interface is serialized, bit stuffed, NRZI encoded, and transmitted as a dc output current on DP or DM
depending on the data. Each line has an effective 22.5-Ω load to ground, which generates the voltage
levels for signaling.
A disconnect detector is also part of the HS transmitter. A disconnect on the far end of the cable causes
the impedance seen by the transmitter to double thereby doubling the differential amplitude seen on the
DP/DM lines.
5.3.9
Autoresume
Asserting AUTORESUME bit enables the PHY to automatically transmit resume signaling.
Refer to USB2.0 specification Section 7.1.7.7 and Section 7.9 for more details. When autoresume is
enabled, if the PHY detects a resume-K it takes automatically over-driving of the resume-K within 1 ms.
If AUTORESUME_WDOG_EN bit is set (default is 1), then an internal autoresume watchdog timer, based
on the internal 32K oscillator, CK32K, will be initialized and will start counting when the PHY detects a
resume-K.
If AUTORESUME_WDOG_EN bit is set then if the PHY does not receive a TXCMD of the NOPID type
within TAUTORESUME it will stop driving the resume-K and the USB bus will go back to IDLE-J state
Otherwise the PHY will continue to drive the resume-K until it receives a TXCMD of the NOPID type from
the LINK.
5.3.10 UART Transceiver
By setting CARKITMODE bit in IFC_CTRL register, the TUSB1211 device will enter UART mode. In this
mode, the ULPI data bus is redefined as a 2-pin UART interface, which exchanges data through a direct
access to the FS/LS analog transmitter at DM pin and receiver at DP pin. See Figure 5-1 for the USB
UART data flow.
Figure 5-1. USB UART Data Flow
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5.3.11 USB On-The-Go (OTG)
5.3.11.1 ID Detection Status Bits vs ID Comparators
Four ID comparators permit detection of five external ID resistances as described in Table 5-4.
Table 5-4. OTG ID Detection Status Bits vs ID Comparators
EXTERNAL RID
DETECTED
DETECTION STATUS BIT
DETECTION BIT LOGIC
(DETECTION IF COMP1 < RID < Comp2)
COMP1
COMP2
RID_FLOAT
ID_FLOAT_STS
ID_FLOAT_STS = 1 if (ID_R_ID_A_TO_FLOAT < RID ) else 0
ID_R_ID_A_TO_FLOAT
—
ID_RARBRC_STS
ID_RARBRC_STS = "11" if (ID_R_ID_B_TO_A < RID <
ID_R_ID_A_TO_FLOAT) else 0
ID_R_ID_B_TO_A
ID_R_ID_A_TO_FLOAT
RID_B
ID_RARBRC_STS
ID_RARBRC_STS = "10" if (ID_R_ID_C_TO_B < RID <
ID_R_ID_B_TO_A) else 0
ID_R_ID_C_TO_B
ID_R_ID_B_TO_A
RID_C
ID_RARBRC_STS
ID_RARBRC_STS = "01" if (ID_R_ID_GND_TO_C < RID <
ID_R_ID_C_TO_B) else 0
ID_R_ID_GND_TO_C
ID_R_ID_C_TO_B
RIDGND
IDGND
IDGND = 0 if (RID < ID_R_ID_GND_TO_C) else 1
—
ID_R_ID_GND_TO_C
RID_A
5.3.12 USB Battery Charger Detection and ACA
In order to support Battery Charging Specification v1.1 April 2009 [BCS v1.1], a charger detection module
is included inside the TUSB1211 module.
This feature includes:
• Battery charger detection sensing and control on DP/DM lines
• ACA (Accessory Charger Adapter) detection and control on ID line
The detection mechanism aims at distinguishing several types of power sources that can be connected on
VBUS line:
• Dedicated Charging Port
• Standard Downstream Port
• Charging Downstream Port
Hardware includes:
• a dedicated voltage referenced pullup on DP line
• a dedicated current controlled pulldown on DM line
• a detection comparator on DM line—a control/detection finite state machine (FSM) including timers
• a charger detection output pin (CHRG_DET) for external charger control
• detection comparators on ID line
ID pin status detection (as defined per OTG v1.3 standard as well as ACA resistor types as described in
BCS v1.1) and DP/DM Single-Ended receivers (as defined per USB v2.0 standard) are also used to
determine the type of device plugged on USB connector.
USB charger detection is an independent feature, on VBAT supply domain, using CK32K clock.
30
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5.3.13 USB Battery Charger Detection Modes
There are 3 modes of operation of battery charger detection module:
1. Hardware Charger Detection Module
2. Software Mode
3. Software FSM Mode
5.3.14 Accessory Charger Adapter (ACA) Detection
Accessory Charger Adapter (ACA) feature is defined in the USB Battery Charging Specification Rev. 1.1
specification. ACA allows simultaneous connection of a USB Charger or Charging Downstream Port and
an Accessory to a portable OTG device (TUSB1211).through only a single USB OTG port.
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Register Maps
Table 5-5. USB Register Summary
32
REGISTER NAME
TYPE
REGISTER WIDTH (BITS)
PHYSICAL ADDRESS
VENDOR_ID_LO
R
8
0x00
VENDOR_ID_HI
R
8
0x01
PRODUCT_ID_LO
R
8
0x02
PRODUCT_ID_HI
R
8
0x03
FUNC_CTRL
RW
8
0x04
FUNC_CTRL_SET
RW
8
0x05
FUNC_CTRL_CLR
RW
8
0x06
IFC_CTRL
RW
8
0x07
IFC_CTRL_SET
RW
8
0x08
IFC_CTRL_CLR
RW
8
0x09
OTG_CTRL
RW
8
0x0A
OTG_CTRL_SET
RW
8
0x0B
OTG_CTRL_CLR
RW
8
0x0C
USB_INT_EN_RISE
RW
8
0x0D
USB_INT_EN_RISE_SET
RW
8
0x0E
USB_INT_EN_RISE_CLR
RW
8
0x0F
USB_INT_EN_FALL
RW
8
0x10
USB_INT_EN_FALL_SET
RW
8
0x11
USB_INT_EN_FALL_CLR
RW
8
0x12
USB_INT_STS
R
8
0x13
USB_INT_LATCH
R
8
0x14
DEBUG
R
8
0x15
SCRATCH_REG
RW
8
0x16
SCRATCH_REG_SET
RW
8
0x17
SCRATCH_REG_CLR
RW
8
0x18
Reserved
R
8
0x19 0x2E
ACCESS_EXT_REG_SET
RW
8
0x2F
Reserved
R
8
0x30 0x3C
POWER_CONTROL
RW
8
0x3D
POWER_CONTROL_SET
RW
8
0x3E
POWER_CONTROL_CLR
RW
8
0x3F
VENDOR_SPECIFIC1
RW
8
0x80
VENDOR_SPECIFIC1_SET
RW
8
0x81
VENDOR_SPECIFIC1_CLR
RW
8
0x82
VENDOR_SPECIFIC2_STS
R
8
0x83
VENDOR_SPECIFIC2_LATCH
R
8
0x84
VENDOR_SPECIFIC3
RW
8
0x85
VENDOR_SPECIFIC3_SET
RW
8
0x86
VENDOR_SPECIFIC3_CLR
RW
8
0x87
VENDOR_SPECIFIC4
RW
8
0x88
VENDOR_SPECIFIC4_SET
RW
8
0x89
VENDOR_SPECIFIC4_CLR
RW
8
0x8A
VENDOR_SPECIFIC5
RW
8
0x8B
VENDOR_SPECIFIC5_SET
RW
8
0x8C
VENDOR_SPECIFIC5_CLR
RW
8
0x8D
VENDOR_SPECIFIC6
RW
8
0x8E
VENDOR_SPECIFIC6_SET
RW
8
0x8F
VENDOR_SPECIFIC6_CLR
RW
8
0x90
Detailed Description
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5.4.1
SLLSE80B – MARCH 2011 – REVISED JUNE 2015
VENDOR_ID_LO
ADDRESS OFFSET
0x00
PHYSICAL ADDRESS
0x00
DESCRIPTION
Lower byte of vendor ID supplied by USB-IF (TI Vendor ID = 0x0451)
TYPE
R
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
5
4
3
2
1
0
VENDOR_ID
5.4.2
BITS
FIELD NAME
7:0
VENDOR_ID
DESCRIPTION
TYPE
RESET
R
0x51
VENDOR_ID_HI
ADDRESS OFFSET
0x01
PHYSICAL ADDRESS
0x01
DESCRIPTION
Upper byte of vendor ID supplied by USB-IF (TI Vendor ID = 0x0451)
TYPE
R
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
5
4
3
2
1
0
VENDOR_ID
BITS
FIELD NAME
7:0
VEN DOR_ID
DESCRIPTION
TYPE
RESET
R
0x04
Detailed Description
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PRODUCT_ID_LO
ADDRESS OFFSET
0x02
PHYSICAL ADDRESS
0x02
DESCRIPTION
Lower byte of Product ID supplied by Vendor (SAUSB Product ID is 0x1508).
TYPE
R
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
5
4
3
2
1
0
PRODUCT_ID
BITS
FIELD NAME
7:0
5.4.4
DESCRIPTION
TYPE
RESET
R
0x08
PRODUCT_ID
PRODUCT_ID_HI
ADDRESS OFFSET
0x03
PHYSICAL ADDRESS
0x03
DESCRIPTION
Upper byte of Product ID supplied by Vendor (SAUSB Product ID is 0x1508).
TYPE
R
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
5
4
3
2
1
0
PRODUCT_ID
BITS
7:0
34
FIELD NAME
DESCRIPTION
PRODUCT_ID
Detailed Description
TYPE
RESET
R
0x15
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5.4.5
SLLSE80B – MARCH 2011 – REVISED JUNE 2015
FUNC_CTRL
ADDRESS OFFSET
0x04
PHYSICAL ADDRESS
0x04
DESCRIPTION
Controls UTMI function settings of the PHY.
TYPE
RW
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
5
Reserved
SUSPENDM
RESET
BITS
4
FIELD NAME
7
Reserved
6
SUSPENDM
5
RESET
3
OPMODE
2
TERMSELECT
DESCRIPTION
1
0
XCVRSELECT
TYPE
RESET
R
0
Active low PHY suspend. Put PHY into Low Power Mode. In Low Power
Mode the PHY power down all blocks except the full speed receiver, OTG
comparators, and the ULPI interface pins. The PHY automatically set this bit
to '1' when Low Power Mode is exited.
RW
1
Active high transceiver reset. Does not reset the ULPI interface or ULPI
register set.
RW
0
RW
0x0
Once set, the PHY asserts the DIR signal and reset the UTMI core. When the
reset is completed, the PHY de-asserts DIR and clears this bit. After deasserting DIR, the PHY re-assert DIR and send an RX command update.
Note: This bit is auto-cleared, this explain why it can't be read at '1'.
4:03
OPMODE
Select the required bit encoding style during transmit
0x0:
Normal operation
0x1:
Non-driving
0x2:
Disable bit-stuff and NRZI encoding
0x3:
Reserved (No SYNC and EOP generation feature not supported)
2
TERMSELECT
Controls the internal 1.5 kΩ pullup resistor and 45 Ω HS terminations. Control
over bus resistors changes depending on XcvrSelect, OpMode, DpPulldown
and DmPulldown.
RW
0
1:0
XCVRSELECT
Select the required transceiver speed.
RW
0x1
0x0:
Enable HS transceiver
0x1:
Enable FS transceiver
0x2:
Enable LS transceiver
0x3:
Enable FS transceiver for LS packets
(FS preamble is automatically pre-pended)
Detailed Description
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FUNC_CTRL_SET
ADDRESS OFFSET
0x05
PHYSICAL ADDRESS
0x05
DESCRIPTION
This register doesn't physically exist.
INSTANCE
USB_SCUSB
It is the same as the func_ctrl register with read/set-only property (write '1' to set a particular bit, a write
'0' has no-action).
TYPE
RW
WRITE LATENCY
7
6
5
Reserved
SUSPENDM
RESET
5.4.7
4
3
OPMODE
2
1
TERMSELECT
DESCRIPTION
0
XCVRSELECT
BITS
FIELD NAME
TYPE
RESET
7
Reserved
R
0
6
SUSPENDM
RW
1
5
RESET
RW
0
4:3
OPMODE
RW
0x0
2
TERMSELECT
RW
0
1:0
XCVRSELECT
RW
0x1
FUNC_CTRL_CLR
ADDRESS OFFSET
0x06
PHYSICAL ADDRESS
0x06
DESCRIPTION
This register doesn't physically exist.
INSTANCE
USB_SCUSB
It is the same as the func_ctrl register with read/clear-only property (write '1' to clear a particular bit, a
write '0' has no-action).
TYPE
RW
WRITE LATENCY
7
6
5
Reserved
SUSPENDM
RESET
BITS
36
FIELD NAME
4
3
OPMODE
DESCRIPTION
2
1
TERMSELECT
0
XCVRSELECT
TYPE
RESET
7
Reserved
R
0
6
SUSPENDM
RW
1
5
RESET
RW
0
4:3
OPMODE
RW
0x0
2
TERMSELECT
RW
0
1:0
XCVRSELECT
RW
0x1
Detailed Description
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5.4.8
SLLSE80B – MARCH 2011 – REVISED JUNE 2015
IFC_CTRL
ADDRESS OFFSET
0x07
PHYSICAL ADDRESS
0x07
DESCRIPTION
Enables alternative interfaces and PHY features.
TYPE
RW
INSTANCE
USB_SCUSB
6
5
4
3
2
1
INDICATORPASSTHRU
INDICATORCOMPLEMENT
AUTORESUME
CLOCKSUSPENDM
CARKITMODE
FSLSSERIALMODE_3PIN
BITS
FIELD NAME
7
INTERFACE_PROTECT_DI
SABLE
DESCRIPTION
Controls circuitry built into the PHY for protecting the ULPI interface when the link tristates stp and data.
0
FSLSSERIALMODE_6PIN
7
INTERFACE_PROTECT_DISABLE
WRITE LATENCY
TYPE
RESET
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
0b: Enables the interface protect circuit
1b: Disables the interface protect circuit
6
INDICATORPASSTHRU
Controls whether the complement output is qualified with the internal vbusvalid
comparator before being used in the VBUS State in the RXCMD.
EXTERNALVBUSINDICATOR input signal is the FAULT input pin of TUSB1211.
0b: Complement output signal is qualified with the internal VBUSVALID comparator.
1b: Complement output signal is not qualified with the internal VBUSVALID comparator.
5
INDICATORCOMPLEMENT
Tells the PHY to invert EXTERNALVBUSINDICATOR input signal, generating the
complement output.
EXTERNALVBUSINDICATOR input signal is the FAULT input pin of TUSB1211.
0b: PHY will not invert signal EXTERNALVBUSINDICATOR (default)
1b: PHY will invert signal EXTERNALVBUSINDICATOR
4
AUTORESUME
Enables the PHY to automatically transmit resume signaling.
Refer to USB specification 7.1.7.7 and 7.9 for more details.
0 = AutoResume disabled (default)
1 = AutoResume enabled
3
CLOCKSUSPENDM
Active low clock suspend. Valid only in Serial Modes. Powers down the internal clock
circuitry only. Valid only when SuspendM = 1b. The PHY must ignore ClockSuspend
when SuspendM = 0b. By default, the clock will not be powered in Serial and Carkit
Modes.
0b : Clock will not be powered in Serial and UART Modes.
1b : Clock will be powered in Serial and UART Modes.
2
CARKITMODE
Changes the ULPI interface to UART interface. The PHY automatically clear this field
when UART mode is exited.
0b: UART disabled.
1b: Enable serial UART mode.
1
FSLSSERIALMODE_3PIN
Changes the ULPI interface to 3-pin Serial.
The PHY must automatically clear this field when serial mode is exited.
0b: FS/LS packets are sent using parallel interface
1b: FS/LS packets are sent using 3-pin serial interface
0
FSLSSERIALMODE_6PIN
Changes the ULPI interface to 6-pin Serial.
The PHY must automatically clear this field when serial mode is exited.
0b: FS/LS packets are sent using parallel interface
1b: FS/LS packets are sent using 6-pin serial interface
Detailed Description
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5.4.9
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IFC_CTRL_SET
ADDRESS OFFSET
0x08
PHYSICAL ADDRESS
0x08
DESCRIPTION
This register doesn't physically exist.
INSTANCE
USB_SCUSB
It is the same as the ifc_ctrl register with read/set-only property (write '1' to set a particular bit, a write '0'
has no-action).
TYPE
RW
38
3
2
CARKITMODE
DESCRIPTION
1
0
FSLSSERIALMODE_6PIN
4
AUTORESUME
FSLSSERIALMODE_3PIN
5
CLOCKSUSPENDM
6
INDICATORPASSTHRU
INTERFACE_PROTECT_DISABLE
7
INDICATORCOMPLEMENT
WRITE LATENCY
BITS
FIELD NAME
TYPE
RESET
7
INTERFACE_PROTECT_DISABLE
RW
0
6
INDICATORPASSTHRU
RW
0
5
INDICATORCOMPLEMENT
RW
0
4
AUTORESUME
RW
0
3
CLOCKSUSPENDM
RW
0
2
CARKITMODE
RW
0
1
FSLSSERIALMODE_3PIN
RW
0
0
FSLSSERIALMODE_6PIN
R
0
Detailed Description
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5.4.10 IFC_CTRL_CLR
ADDRESS OFFSET
0x09
PHYSICAL ADDRESS
0x09
DESCRIPTION
This register doesn't physically exist.
INSTANCE
USB_SCUSB
It is the same as the ifc_ctrl register with read/clear-only property (write '1' to clear a particular bit, a
write '0' has no-action).
TYPE
RW
4
AUTORESUME
3
2
CARKITMODE
1
0
FIELD NAME
TYPE
RESET
7
INTERFACE_PROTECT_DISABLE
RW
0
6
INDICATORPASSTHRU
RW
0
5
INDICATORCOMPLEMENT
RW
0
4
AUTORESUME
RW
0
3
CLOCKSUSPENDM
RW
0
2
CARKITMODE
RW
0
1
FSLSSERIALMODE_3PIN
RW
0
0
FSLSSERIALMODE_6PIN
R
0
IN DICATORPASSTHRU
BITS
INTERFACE_PROTECT_DISABLE
FSLSSERIALMODE_6PIN
5
FSLSSERIALMODE_3PIN
6
CLOCKSUSPENDM
7
INDICATORCOMPLEMENT
WRITE LATENCY
DESCRIPTION
Detailed Description
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5.4.11 OTG_CTRL
ADDRESS OFFSET
0x0A
PHYSICAL ADDRESS
0x0A
DESCRIPTION
Controls UTMI+ OTG functions of the PHY.
TYPE
RW
INSTANCE
USB_SCUSB
USEEXTERNALVBUSINDICATOR
7
6
5
4
3
2
1
0
DRVVBUSEXTERNAL
WRITE LATENCY
DRVVBUS
CHRGVBUS
DISCHRGVBUS
DMPULLDOWN
DPPULLDOWN
IDPULLUP
BITS
FIELD NAME
7
USEEXTERNALVBUSINDI
CATOR
DESCRIPTION
Tells the PHY to use an external VBUS over-current indicator.
TYPE
RESET
RW
0
RW
0
RW
0
RW
0
RW
0
RW
1
RW
1
RW
0
EXTERNALVBUSINDICATOR input signal is the FAULT input pin of TUSB1211.
0b: Use the internal OTG comparator (VA_VBUS_VLD) or internal VBUS valid indicator
(default)
1b: Use external VBUS valid indicator signal.
6
DRVVBUSEXTERNAL
Selects between the internal and the external 5 V VBUS supply.
0b: Drive VBUS using the internal charge pump.
This function does nothing as TUSB1211 does not include an internal charge-pump (default)
1b: Drive VBUS using external supply (assert PSW pin).
5
DRVVBUS
Signals the internal charge pump to drive 5 V on VBUS.
0b : do not drive VBUS (deassert PSW pin)
1b : drive 5V on VBUS (assert PSW pin)
4
CHRGVBUS
Charge VBUS through a resistor. Used for VBUS pulsing SRP. The Link must first check that
VBUS has been discharged (see DischrgVbus register bit), and that both DP and DM data
lines have been low (SE0) for 2 ms.
0b : do not charge VBUS
1b : charge VBUS
3
DISCHRGVBUS
Discharge VBUS through a resistor. If the Link sets this bit to 1, it waits for an RX CMD
indicating SessEnd has transitioned from 0 to 1, and then resets this bit to 0 to stop the
discharge.
0b : do not discharge VBUS
1b : discharge VBUS
2
DMPULLDOWN
Enables the 15 kΩ pulldown resistor on DM.
0b : Pulldown resistor not connected to DM.
1b : Pulldown resistor connected to DM.
1
DPPULLDOWN
Enables the 15 kΩ pulldown resistor on DP.
0b : pulldown resistor not connected to DP.
1b : pulldown resistor connected to DP.
0
IDPULLUP
Connects a pullup to the ID line and enables sampling of the signal level.
0b
:
40
Disable sampling of ID line. when IDPULLUP_WK_EN = 0
Detailed Description
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BITS
SLLSE80B – MARCH 2011 – REVISED JUNE 2015
FIELD NAME
DESCRIPTION
TYPE
RESET
Enable sampling of the ID line when IDPULLUP_WK_EN = 1
Note Weak pull-up (RID_UP_WK) on ID is enabled when IDPULLUP = 0 to avoid floating
condition, but sampling is not enabled unless IDPULLUP_WK_EN = 1
1b
:
Enable sampling of ID line and strong pullup resistor (RID_UP) on ID
Note: If ACA_DET_EN=1, then ID strong pullup resistor will be enabled automatically during
ACA detection states (ACA_DETECTION, ACA_SETUP) of the charger detection statemachine , irrespective of status of IDPULLUP bit. This is to ensure correct functionality of ID
ACA RA/RB/RC detection comparators. Otherwise ID pullup is controlled as described above.
5.4.12 OTG_CTRL_SET
ADDRESS OFFSET
0x0B
PHYSICAL ADDRESS
0x0B
DESCRIPTION
This register doesn't physically exist.
INSTANCE
USB_SCUSB
It is the same as the otg_ctrl register with read/set-only property (write '1' to set a particular bit, a write
'0' has no-action).
TYPE
RW
7
6
5
4
3
2
1
0
USEEXTERNALVBUSINDICATOR
DRVVBUSEXTERNAL
DRVVBUS
CHRGVBUS
DISCHRGVBUS
DMPULLDOWN
WRITE LATENCY
DPPULLDOWN
IDPULLUP
BITS
FIELD NAME
7
6
5
DESCRIPTION
TYPE
RESET
USEEXTERNALVBUSINDICATOR
RW
0
DRVVBUSEXTERNAL
RW
0
DRVVBUS
RW
0
4
CHRGVBUS
RW
0
3
DISCHRGVBUS
RW
0
2
DMPULLDOWN
RW
1
1
DPPULLDOWN
RW
1
0
IDPULLUP
RW
0
Detailed Description
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5.4.13 OTG_CTRL_CLR
ADDRESS OFFSET
0x0C
PHYSICAL ADDRESS
0x0C
DESCRIPTION
This register doesn't physically exist.
INSTANCE
USB_SCUSB
It is the same as the otg_ctrl register with read/Clear-only property (write '1' to clear a particular bit, a
write '0' has no-action).
TYPE
RW
42
7
6
5
4
3
2
1
0
USEEXTERNALVBUSINDICATOR
DRVVBUSEXTERNAL
DRVVBUS
CHRGVBUS
DISCHRGVBUS
DMPULLDOWN
WRITE LATENCY
DPPULLDOWN
IDPULLUP
TYPE
RESET
BITS
FIELD NAME
DESCRIPTION
7
USEEXTERNALVBUSINDICATOR
RW
0
6
DRVVBUSEXTERNAL
RW
0
5
DRVVBUS
RW
0
4
CHRGVBUS
RW
0
3
DISCHRGVBUS
RW
0
2
DMPULLDOWN
RW
1
1
DPPULLDOWN
RW
1
0
IDPULLUP
RW
0
Detailed Description
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5.4.14 USB_INT_EN_RISE
ADDRESS OFFSET
0x0D
PHYSICAL ADDRESS
0x0D
DESCRIPTION
If set, the bits in this register cause an interrupt event notification to be generated when the
corresponding PHY signal changes from low to high. By default, all transitions are enabled.
TYPE
RW
INSTANCE
USB_SCUSB
4
Reserved
Reserved
Reserved
IDGND_RISE
3
2
1
DESCRIPTION
0
HOSTDISCONNECT_RISE
5
VBUSVALID_RISE
6
SESSVALID_RISE
7
SESSEND_RISE
WRITE LATENCY
BITS
FIELD NAME
TYPE
RESET
7
Reserved
R
0
6
Reserved
R
0
5
Reserved
R
0
4
IDGND_RISE
RW
1
Generate an interrupt event notification when IdGnd changes from
low to high.
Event is automatically masked if IdPullup bit is clear to 0 and for
50ms after IdPullup is set to 1.
3
SESSEND_RISE
Generate an interrupt event notification when SessEnd changes
from low to high.
RW
1
2
SESSVALID_RISE
Generate an interrupt event notification when SessValid changes
from low to high. SessValid is the same as UTMI+ AValid.
RW
1
1
VBUSVALID_RISE
Generate an interrupt event notification when VbusValid changes
from low to high.
RW
1
0
HOSTDISCONNECT_RISE
Generate an interrupt event notification when Hostdisconnect
changes from low to high. Applicable only in host mode
(DpPulldown and DmPulldown both set to 1b).
RW
1
Detailed Description
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5.4.15 USB_INT_EN_RISE_SET
ADDRESS OFFSET
0x0E
PHYSICAL ADDRESS
0x0E
DESCRIPTION
This register doesn't physically exist.
INSTANCE
USB_SCUSB
It is the same as the usb_int_en_rise register with read/set-only property (write '1' to set a particular bit,
a write '0' has no-action).
TYPE
RW
WRITE LATENCY
44
3
Reserved
Reserved
Reserved
IDGND_RISE
DESCRIPTION
2
1
0
HOSTDISCONNECT_RISE
4
VBUSVALID_RISE
5
SESSVALID_RISE
6
SESSEND_RISE
7
BITS
FIELD NAME
TYPE
RESET
7
Reserved
R
0
6
Reserved
R
0
5
Reserved
R
0
4
IDGND_RISE
RW
1
3
SESSEND_RISE
RW
1
2
SESSVALID_RISE
RW
1
1
VBUSVALID_RISE
RW
1
0
HOSTDISCONNECT_RIS
E
RW
1
Detailed Description
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5.4.16 USB_INT_EN_RISE_CLR
ADDRESS OFFSET
0x0F
PHYSICAL ADDRESS
0x0F
DESCRIPTION
This register doesn't physically exist.
INSTANCE
USB_SCUSB
It is the same as the usb_int_en_rise register with read/clear-only property (write '1' to clear a particular
bit, a write '0' has no-action).
TYPE
RW
4
Reserved
Reserved
Reserved
IDGND_RISE
3
2
DESCRIPTION
1
0
HOSTDISCONNECT_RISE
5
VBUSVALID_RISE
6
SESSVALID_RISE
7
SESSEN D_RISE
WRITE LATENCY
BITS
FIELD NAME
TYPE
RESET
7
Reserved
R
0
6
Reserved
R
0
5
Reserved
R
0
4
IDGND_RISE
RW
1
3
SESSEND_RISE
RW
1
2
SESSVALID_RISE
RW
1
1
VBUSVALID_RISE
RW
1
0
HOSTDISCONNECT_RISE
RW
1
Detailed Description
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5.4.17 USB_INT_EN_FALL
ADDRESS OFFSET
0x10
PHYSICAL ADDRESS
0x10
DESCRIPTION
If set, the bits in this register cause an interrupt event notification to be generated when the
corresponding PHY signal changes from low to high. By default, all transitions are enabled.
TYPE
RW
INSTANCE
USB_SCUSB
4
Reserved
Reserved
Reserved
IDGND_FALL
BITS
FIELD NAME
3
2
DESCRIPTION
1
0
HOSTDISCONNECT_FALL
5
VBUSVALID_FALL
6
SESSVALID_FALL
7
SESSEND_FALL
WRITE LATENCY
TYPE
RESET
7
Reserved
R
0
6
Reserved
R
0
5
Reserved
R
0
4
IDGND_FALL
RW
1
Generate an interrupt event notification when IdGnd changes
from high to low.
Event is automatically masked if IdPullup bit is clear to 0 and for
50ms after IdPullup is set to 1.
46
3
SESSEND_FALL
Generate an interrupt event notification when SessEnd changes
from high to low.
RW
1
2
SESSVALID_FALL
Generate an interrupt event notification when SessValid changes
from high to low. SessValid is the same as UTMI+ AValid.
RW
1
1
VBUSVALID_FALL
Generate an interrupt event notification when VbusValid changes
from high to low.
RW
1
0
HOSTDISCONNECT_FALL
Generate an interrupt event notification when Hostdisconnect
changes from high to low. Applicable only in host mode
(DpPulldown and DmPulldown both set to 1b).
RW
1
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5.4.18 USB_INT_EN_FALL_SET
ADDRESS OFFSET
0x11
PHYSICAL ADDRESS
0x11
DESCRIPTION
This register doesn't physically exist.
INSTANCE
USB_SCUSB
It is the same as the usb_int_en_fall register with read/set-only property (write '1' to set a particular bit, a
write '0' has no-action)
TYPE
RW
4
Reserved
Reserved
Reserved
IDGND_FALL
3
2
DESCRIPTION
1
0
HOSTDISCONNECT_FALL
5
VBUSVALID_FALL
6
SESSVALID_FALL
7
SESSEND_FALL
WRITE LATENCY
BITS
FIELD NAME
TYPE
RESET
7
Reserved
R
0
6
Reserved
R
0
5
Reserved
R
0
4
IDGND_FALL
RW
1
3
SESSEND_FALL
RW
1
2
SESSVALID_FALL
RW
1
1
VBUSVALID_FALL
RW
1
0
HOSTDISCONNECT_FALL
RW
1
Detailed Description
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5.4.19 USB_INT_EN_FALL_CLR
ADDRESS OFFSET
0x12
PHYSICAL ADDRESS
0x12
DESCRIPTION
This register doesn't physically exist.
INSTANCE
USB_SCUSB
It is the same as the usb_int_en_fall register with read/clear-only property (write '1' to clear a particular
bit, a write '0' has no-action).
TYPE
RW
4
Reserved
Reserved
Reserved
IDGND_FALL
BITS
48
FIELD NAME
3
2
1
DESCRIPTION
0
HOSTDISCONNECT_FALL
5
VBUSVALID_FALL
6
SESSVALID_FALL
7
SESSEND_FALL
WRITE LATENCY
TYPE
RESET
7
Reserved
R
0
6
Reserved
R
0
5
Reserved
R
0
4
IDGND_FALL
RW
1
3
SESSEN D_FALL
RW
1
2
SESSVALID_FALL
RW
1
1
VBUSVALID_FALL
RW
1
0
HOSTDISCONNECT_FALL
RW
1
Detailed Description
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5.4.20 USB_INT_STS
ADDRESS OFFSET
0x13
PHYSICAL ADDRESS
0x13
DESCRIPTION
Indicates the current value of the interrupt source signal.
TYPE
R
INSTANCE
USB_SCUSB
WRITE LATENCY
6
5
4
3
2
1
Reserved
Reserved
IDGND
SESSEND
SESSVALID
VBUSVALID
BITS
FIELD NAME
DESCRIPTION
0
HOSTDISCONNECT
7
Reserved
TYPE
RESET
7
Reserved
R
0
6
Reserved
R
0
5
Reserved
R
0
4
IDGND
R
0
Current value of UTMI+ IdGnd output.
This bit is not updated if IdPullup bit is reset to 0 and for 50 ms after IdPullup is set to
1.
3
SESSEND
Current value of UTMI+ SessEnd output.
R
0
2
SESSVALID
Current value of UTMI+ SessValid output. SessValid is the same as UTMI+ AValid.
R
0
1
VBUSVALID
Current value of UTMI+ VbusValid output.
R
0
0
HOSTDISCONNECT Current value of UTMI+ Hostdisconnect output.
R
0
Applicable only in host mode.
Automatically reset to 0 when Low Power Mode is entered.
NOTE: Reset value is '0' when host is connected.
Reset value is '1' when host is disconnected.
Detailed Description
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5.4.21 USB_INT_LATCH
ADDRESS OFFSET
0x14
PHYSICAL ADDRESS
0x14
DESCRIPTION
These bits are set by the PHY when an unmasked change occurs on the corresponding internal signal.
The PHY will automatically clear all bits when the Link reads this register, or when Low Power Mode is
entered. The PHY also clears this register when Serial Mode or Carkit Mode is entered regardless of the
value of ClockSuspendM.
INSTANCE
USB_SCUSB
The PHY follows the rules defined in Table 26 of the ULPI spec for setting any latch register bit. It is
important to note that if register read data is returned to the Link in the same cycle that a USB Interrupt
Latch bit is to be set, the interrupt condition is given immediately in the register read data and the Latch
bit is not set.
Note that it is optional for the Link to read the USB Interrupt Latch register in Synchronous Mode because
the RX CMD byte already indicates the interrupt source directly
TYPE
R
4
Reserved
Reserved
Reserved
IDGND_LATCH
BITS
FIELD NAME
3
2
1
DESCRIPTION
0
HOSTDISCONNECT_LATCH
5
VBUSVALID_LATCH
6
SESSVALID_LATCH
7
SESSEND_LATCH
WRITE LATENCY
TYPE
RESET
7
Reserved
R
0
6
Reserved
R
0
5
Reserved
R
0
4
IDGND_LATCH
Set to 1 by the PHY when an unmasked event occurs on IdGnd. Cleared when this
register is read.
R
0
3
SESSEND_LATCH
Set to 1 by the PHY when an unmasked event occurs on SessEnd. Cleared when
this register is read.
R
0
2
SESSVALID_LATCH
Set to 1 by the PHY when an unmasked event occurs on SessValid. Cleared when
this register is read. SessValid is the same as UTMI+ AValid.
R
0
1
VBUSVALID_LATCH
Set to 1 by the PHY when an unmasked event occurs on VbusValid. Cleared when
this register is read.
R
0
0
HOSTDISCONNECT_LATCH
Set to 1 by the PHY when an unmasked event occurs on Hostdisconnect. Cleared
when this register is read. Applicable only in host mode.
R
0
NOTE: As this IT is enabled by default, the reset value depends on the host status
Reset value is '0' when host is connected.
Reset value is '1' when host is disconnected.
50
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5.4.22 DEBUG
ADDRESS OFFSET
0x15
PHYSICAL ADDRESS
0x15
DESCRIPTION
Indicates the current value of various signals useful for debugging.
TYPE
R
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
5
4
3
2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
BITS
0
LINESTATE
TYPE
RESET
7
Reserved
R
0
6
Reserved
R
0
5
Reserved
R
0
4
Reserved
R
0
3
Reserved
R
0
2
Reserved
R
0
R
0x0
1:0
FIELD NAME
1
LINESTATE
DESCRIPTION
These signals reflect the current state of the single ended receivers. They directly
reflect the current state of the DP (LineState[0]) and DM (LineState[1]) signals.
Read 0x0:
SE0 (LS/FS), Squelch (HS/Chirp)
Read 0x1:
LS: 'K' State,
FS: 'J' State,
HS: !Squelch,
Chirp: !Squelch and HS_Differential_Receiver_Output
Read 0x2:
LS: 'J' State,
FS: 'K' State,
HS: Invalid,
Chirp: !Squelch and !HS_Differential_Receiver_Output
Read 0x3:
SE1 (LS/FS), Invalid (HS/Chirp)
Detailed Description
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5.4.23 SCRATCH_REG
ADDRESS OFFSET
0x16
PHYSICAL ADDRESS
0x16
DESCRIPTION
Empty register byte for testing purposes. Software can read, write, set, and clear this register and the
PHY functionality will not be affected.
TYPE
RW
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
5
4
3
2
1
0
SCRATCH
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7:0
SCRATCH
Scratch data.
RW
0x00
5.4.24 SCRATCH_REG_SET
ADDRESS OFFSET
0x17
PHYSICAL ADDRESS
0x17
DESCRIPTION
This register doesn't physically exist.
INSTANCE
USB_SCUSB
It is the same as the scratch_reg register with read/set-only property (write '1' to set a particular bit, a
write '0' has no-action).
TYPE
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
SCRATCH
BITS
7:0
FIELD NAME
DESCRIPTION
SCRATCH
TYPE
RESET
RW
0x00
5.4.25 SCRATCH_REG_CLR
ADDRESS OFFSET
0x18
PHYSICAL ADDRESS
0x18
DESCRIPTION
This register doesn't physically exist.
INSTANCE
USB_SCUSB
It is the same as the scratch_reg with read/clear-only property (write '1' to clear a particular bit, a write
'0' has no-action).
TYPE
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
SCRATCH
BITS
7:0
52
FIELD NAME
DESCRIPTION
SCRATCH
Detailed Description
TYPE
RESET
RW
0x00
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5.4.26 POWER_CONTROL
ADDRESS OFFSET
0x3D
PHYSICAL ADDRESS
0x3D
DESCRIPTION
Power Control register
TYPE
RW
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
5
4
3
2
1
0
HWDETECT
DP_VSRC_EN
VDAT_DET
DP_WKPU_EN
BVALID_FALL
BVALID_RISE
DET_COMP
SW_CONTROL
BITS
7
FIELD NAME
HWDETECT
DESCRIPTION
When SW_CONTROL= 0, HWDETECT bit is read-only. This bit indicates if
the transceiver is connected to a Charging Port (Dedicated Charging Port
or Charging Downstream Port ).
TYPE
RESET
RW
0
RW
0
RW
0
RW
0
0b: No charger detected.
1b: Charger detected.
Note when SW_CONTROL=0, hardware controls the CHRG_DET pin with
the same logic described below for SW_CONTROL=1 case. When
SW_CONTROL=1, HWDETECT is writeable. This bit allows manual control
over the logic levels on the CHRG_DET pin.
0b: CHRG_DET is externally pulled LOW (CHRG_DET_POL is HIGH) or
CHRG_DET is externally pulled HIGH (CHRG_DET_POL is LOW).
1b: CHRG_DET is driven LOW (CHRG_DET_POL is LOW) or CHRG_DET
is driven HIGH (CHRG_DET_POL is HIGH)
6
DP_VSRC_EN
This bit controls whether DP is allowed to send VDAT_SRC, which is a
sensing voltage for charger detection. This bit also enables IDAT_SINK on
DM and VDAT_REF. (Used when manual control over the charger detection
is needed.) Note when SW_CONTROL=0, this bit is read-only. In this case
hardware controls IDAT_SINK and VDAT_REF with the same logic described
below for SW_CONTROL=1 case.
When SW_CONTROL=1, DP_VSRC_EN is writeable:
0b: No transmission of sensing voltage is performed. IDAT_SINK and
VDAT_REF are disabled.
1b: DP transmits sensing voltage; enables IDAT_SINK and VDAT_REF.
5
VDAT_DET
This bit indicates the presence of a voltage level higher that VDAT_REF on
the DM. (Used when manual control over the charger detection is needed.)
0b: Voltage on DM is lower than VDAT_REF
1b: Voltage on DM is higher than VDAT_REF
4
DP_WKPU_EN
Enables the weak pull-up resistor on the DP pin in synchronous mode
when VBUS is above the VSESS_VLD threshold.
0b: DP weak pull-up is disabled.
1b: DP weak pull-up is enabled when VBUS > VSESS_VLD
Detection of DP/DM condition while this bit is set should be done through
LINESTATEbits in DEBUG register (0x15) or through RX CMD.
3
BVALID_FALL
Enables RX CMD’s for high to low transitions on BVALID. When BVALID changes
from high to low, the USB TRANS will send an RX CMD to the link with the alt_int bit
set to 1b. This bit is optional and is not necessary for OTG devices. This bit is
provided for debugging purposes. Disabled by default.
RW
0
2
BVALID_RISE
Enables RX CMD’s for low to high transitions on BVALID. When BVALID changes
from low to high, the USB Trans will send an RX CMD to the link with the alt_int bit
set to 1b. This bit is optional and is not necessary for OTG devices. This bit is
provided for debugging purposes. Disabled by default.
RW
0
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BITS
1
FIELD NAME
DET_COMP
www.ti.com
DESCRIPTION
This bit indicates if a Charging Port has been detected.
TYPE
RESET
RW
0
RW
0
0b: A Charging Port has not been detected, or charger detection has not
been activated. (Identical to HWDETECT)
1b: A Charging Port has been detected (Identical to HWDETECT) When
SW_CONTROL = 1 this bit is reset to 0.
0
SW_CONTROL
This bit controls whether CHRG_DET pin is controlled automatically or
manually. When manual control is required, the software must set the
SW_CONTROL bit to logic 1 in the first register access, followed by issuing
a second register access to set or clear the HWDETECT bit. Software must
never set the SW_CONTROL bit and change the HWDETECT bit in the
same register access.
0b: The CHRG_DET pin will be asserted or deasserted depending on the
automatic USB charger detection result.
1b: At rising-edge of SW_CONTROL bit save current hardware charger
detection context and hand-off control to software:
a. DP_VSRC_EN register bit is loaded with current status of VDP_SRC
b. HWDETECT register bit is loaded with current status of charger
detection result. Therefore battery charger indication signal to external
charger remains unchanged.
c. Charger detection circuitry is maintained enabled if it was enabled in
dead-battery condition
d. Charger Detection FSM is exited (to state USB_DET_OFF)
e. Control of POWER_CONTROL register bits is handed over to software
Therefore if charger detection has been initiated in dead-battery condition
(while the chip is disabled (CS=0)), VDP_SRC will remain enabled and
CHRG_DET pin status will not change when SW takes control, and SW
can read register status before deciding to perform further
charger/device/accessory detection or USB attach The CHRG_DET pin will
be asserted or deasserted depending on the HWDETECT bit setting.
54
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5.4.27 POWER_CONTROL_SET
ADDRESS OFFSET
0x3E
PHYSICAL ADDRESS
0x3E
DESCRIPTION
This register doesn't physically exist. It is the same as the POWER_CONTROL register with read/setonly property (write '1' to set a particular bit, a write '0' has no-action).
TYPE
RW
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
5
4
3
2
1
0
HWDETECT
DP_VSRC_EN
VDAT_DET
DP_WKPU_EN
BVALID_FALL
BVALID_RISE
DET_COMP
SW_CONTROL
BITS
TYPE
RESET
7
HWDETECT
FIELD NAME
DESCRIPTION
RW
0
6
DP_VSRC_EN
RW
0
5
VDAT_DET
R
0
4
DP_WKPU_EN
RW
0
3
BVALID_FALL
RW
0
2
BVALID_RISE
RW
0
1
DET_COMP
R
0
0
SW_CONTROL
RW
0
5.4.28 POWER_CONTROL_CLR
ADDRESS OFFSET
0x3F
PHYSICAL ADDRESS
0x3F
DESCRIPTION
This register doesn't physically exist. It is the same as the POWER_CONTROL register with read/setonly property (write '1' to set a particular bit, a write '0' has no-action).
TYPE
RW
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
5
4
3
2
1
0
HWDETECT
DP_VSRC_EN
VDAT_DET
DP_WKPU_EN
BVALID_FALL
BVALID_RISE
DET_COMP
SW_CONTROL
BITS
TYPE
RESET
7
HWDETECT
FIELD NAME
DESCRIPTION
RW
0
6
DP_VSRC_EN
RW
0
5
VDAT_DET
R
0
4
DP_WKPU_EN
RW
0
3
BVALID_FALL
RW
0
2
BVALID_RISE
RW
0
1
DET_COMP
R
0
0
SW_CONTROL
RW
0
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5.4.29 VENDOR_SPECIFIC1
ADDRESS OFFSET
0x80
PHYSICAL ADDRESS
0x80
DESCRIPTION
Eye diagram programmability and DP/DM swap control
TYPE
RW
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
Reserved
DATAPOLARITY
BITS
FIELD NAME
5
4
3
ZHSDRV
2
1
0
IHSTX
TYPE
RESET
7
Reserved
DESCRIPTION
RW
0
6
DATAPOLARITY
RW
1
RW
0x0
RW
0x1
Control data polarity on DP/DM
DATAPOLARITY bit will control both DP/DM polarity in USB PHY and
Charger Detection polarity in active mode but not charger detection in
polarity in dead battery condition.
0b: DP & DM polarity is swapped
DP is mapped to C1 pin, DM mapped to D1 pin
1b: DP & DM polarity is not swapped
DP is mapped to D1 pin, DM mapped to C1 pin as described in Terminal
description chapter
5:4
ZHSDRV
3:0
IHSTX
High speed output impedance configuration for eye diagram tuning :
00 45.455 Ω
01 43.779 Ω
10 42.793 Ω
11 42.411 Ω
High speed output drive strength configuration for eye diagram tuning :
0000 17.928 mA
0001 18.117 mA
0010 18.306 mA
0011 18.495 mA
0100 18.683 mA
0101 18.872 mA
0110 19.061 mA
0111 19.249 mA
1000 19.438 mA
1001 19.627 mA
1010 19.816 mA
1011 20.004 mA
1100 20.193 mA
1101 20.382 mA
1110 20.570 mA
1111 20.759 mA
IHSTX[0] is also the AC BOOST enable
IHSTX[0] = 0 → AC BOOST is disabled
IHSTX[0] = 1 → AC BOOST is enabled
56
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5.4.30 VENDOR_SPECIFIC1_SET
ADDRESS OFFSET
0x81
PHYSICAL ADDRESS
0x81
DESCRIPTION
This register doesn't physically exist.
INSTANCE
USB_SCUSB
It is the same as VENDOR_SPECIFIC1 register with read/set-only property (write '1' to set a particular
bit, a write '0' has no-action).
TYPE
RW
7
6
Reserved
DATAPOLARITY
WRITE LATEN CY
BITS
5
4
3
2
ZHSDRV
1
0
IHSTX
FIELD NAME
DESCRIPTION
TYPE
RESET
0
7
Reserved
RW
6
DATAPOLARITY
RW
1
5:4
ZHSDRV
RW
0x0
3:0
IHSTX
RW
0x1
5.4.31 VENDOR_SPECIFIC1_CLR
ADDRESS OFFSET
0x82
PHYSICAL ADDRESS
0x82
DESCRIPTION
This register doesn't physically exist.
INSTANCE
USB_SCUSB
It is the same as the VENDOR_SPECIFIC1 register with read/clear-only property (write '1' to clear a
particular bit, a write '0' has no-action).
TYPE
RW
7
6
Reserved
DATAPOLARITY
WRITE LATENCY
BITS
5
4
3
ZHSDRV
FIELD NAME
2
1
0
IHSTX
DESCRIPTION
TYPE
RESET
0
7
Reserved
RW
6
DATAPOLARITY
RW
1
5:4
ZHSDRV
RW
0x0
3:0
IHSTX
RW
0x1
Detailed Description
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5.4.32 VENDOR_SPECIFIC2_STS
ADDRESS OFFSET
0x83
PHYSICAL ADDRESS
0x83
DESCRIPTION
Indicates the current value of the interrupt source signal.
TYPE
RW
INSTANCE
USB_SCUSB
7
6
5
4
VBUS_MNTR_STS
REG3V3IN_MNTR_STS
SVLDCONWKB_WDOG_STS
WRITE LATENCY
ID_FLOAT_STS
BITS
FIELD NAME
7
VBUS_MNTR_STS
6
REG3V3IN_MNTR_STS
3
2
ID_RARBRC_STS
DESCRIPTION
Current value of VBUS_MNTR comparator
Current value of REG3V3IN_MNTR comparator
1
0
Reserved
BVALID_STS
TYPE
RESET
R
0
R
0
R
0
R
0
R
0x0
R
0
R
0
0: VBAT REG3V3IN_MNTR threshold
1: VBAT REG3V3IN_MNTR threshold
5
SVLDCONWKB_WDOG_STS
Current value of SVLDCONWKB_WDOG status.
0: Watchdog timer has not expired
1: Watchdog timer has expired
4
ID_FLOAT_STS
Current value of ID_FLOAT detection on ID pin
0: If RID_FLOAT not detected
1: If RID_FLOAT detected
3:2
ID_RARBRC_STS
ACA Detection status output
00: ACA not detected
01: R_ID_A resistance on ID detected
10: R_ID_B resistance on ID detected
11: R_ID_C resistance on ID detected
58
1
Reserved
0
BVALID_STS
Current value of VB_SESS_VLD output
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5.4.33 VENDOR_SPECIFIC2_LATCH
ADDRESS OFFSET
0x84
PHYSICAL ADDRESS
0x84
DESCRIPTION
These bits are set by the PHY when an unmasked change occurs on the corresponding internal signal.
The PHY will automatically clear all bits when the Link reads this register, or when Low Power Mode is
entered. The PHY also clears this register when Serial mode is entered regardless of the value of
ClockSuspendM.
INSTANCE
USB_SCUSB
The PHY follows the rules defined in Table 26 of the ULPI spec for setting any latch register bit.
TYPE
R
7
6
5
4
VBUS_MNTR_LATCH
REG3V3IN_MNTR_LATCH
SVLDCONWKB_WDOG _LATCH
ID_FLOAT_LATCH
WRITE LATENCY
BITS
2
ID_RARBRC_LATCH
1
0
Reserved
BVALID_LATCH
TYPE
RESET
7
VBUS_MNTR_LATCH
Set to ‘1’ when an unmasked event occurs on VBUS_MNTR comparator Clear on read
register.
R
0
6
REG3V3IN_MNTR_LATCH
Set to ‘1’ when an unmasked event occurs on REG3V3IN_MNTR. comparator Clear on
read register.
R
0
5
SVLDCONWKB_WDOG _LATCH
Set to ‘1’ when an unmasked event occurs on SVLDCONWKB_WDOG,that is,, when
watchdog counter has expired. Clear on read register.
R
0
4
ID_FLOAT_LATCH
Set to ‘1’ when an unmasked event occurs on ID_FLOAT detection. Clear on read
register.
R
0
R
0x0
R
0
R
0
3:2
FIELD NAME
3
DESCRIPTION
ID_RARBRC_LATCH
Set according to table below when an unmasked event occurs on ACA Detection status output
00: No ACA event detected
01: ACA event. Detected
10: ACA event. Detected
11: ACA event. Detected
1
Reserved
0
BVALID_LATCH
Set to ‘1’ when an unmasked event occurs on VB_SESS_VLD comparator. Clear on read
register.
Detailed Description
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5.4.34 VENDOR_SPECIFIC3
ADDRESS OFFSET
0x85
PHYSICAL ADDRESS
0x85
INSTANCE
USB_SCUSB
DESCRIPTION
TYPE
RW
7
6
5
4
3
Reserved
CHGD_IDP_SRC_EN _EN
IDPULLUP_WK_EN
SW_USB_DET
DATA_CONTACT_DET_EN
WRITE LATENCY
BITS
FIELD NAME
2
1
0
REG3V3_VSEL
TYPE
RESET
7
Reserved
Software must not set this bit
DESCRIPTION
RW
0
6
CHGD_IDP_SRC_EN
Enable IDP_SRC on DP and RDM_DWN on DM.Can be used to perform data
contact detect (Used when manual control over the charger detection is needed.)
When SW_CONTROL=0 this bit is Read-only and gives the status of IDP_SRC
control signal in charger detection FSM. When SW_CONTROL=1, this bit is
Read/Write:
RW
0
RW
0
RW
0
0b: IDP_SRC on DP and RDM_DWN on DM are disabled.
1b: IDP_SRC on DP and RDM_DWN on DM are enabled
Note: Conflict resolution case: If DP_VSRC_EN = 1 at the same time as this bit is
set, then IDP_SRC on DP and RDM_DWN on DM are disabled, (and VDPSRC
will remain enabled).
5
IDPULLUP_WK_EN
Enable of sampling of ID line with RID_WK_PU. This bit is ignored when
IDPULLUP = 1 Refer to IDPULLUP bit description
0b: Disable sampling of ID line
1b: Enable sampling of the ID line with custom RID_UP_WK
4
SW_USB_DET
Battery Charger Detection state-machine enable bit
0b: Disable Battery Charger Detection State machine
1b: Enable Battery Charger Detection State-machine if SW_CONTROL = 0
Note: This bit is automatically set to 1 by hardware during Dead Battery Detection.
When the chip is powered up and enters ACTIVE mode this bit can be read to
check if Charger Detection FSM is active. Setting this bit to 0 will stop Battery
Charger Detection that was initiated during Dead Battery Condition. This bit is
reset automatically when SW_CONTROL bit is 1. This bit is reset to 0 by
RESETN pin This bit will also be reset to 0 if SVLDCONWKB_CNTR timeout
occurs. Software must then write this bit to 1 to reenable Battery Charger
Detection state-machine if required.
3
DATA_CONTACT_D
ET_EN
If state-machine is enabled in active mode (through SW_USB_DET bit above)
and this bit is set to 1, then Data Contact Detection will be enabled in the charger
detection state-machine. This optional feature is disabled by default.
RW
0
2:0
REG3V3_VSEL
When 000 REG3V3 = 2.5 V
RW
0x3
When 001 REG3V3 = 2.75 V
When 010 REG3V3 = 3.0 V
When 011 REG3V3 = 3.10 V (default)
When 100 REG3V3 = 3.20 V
When 101 REG3V3 = 3.30 V
When 110 REG3V3 = 3.40 V
When 111 REG3V3 = 3.50 V
60
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5.4.35 VENDOR_SPECIFIC3_SET
ADDRESS OFFSET
0x86
PHYSICAL ADDRESS
0x86
INSTANCE
USB_SCUSB
DESCRIPTION
TYPE
RW
7
6
5
4
3
Reserved
CHGD_IDP_SRC_EN
IDPULLUP_WK_EN
SW_USB_DET
DATA_CONTACT_DET_EN
WRITE LATENCY
2
1
0
REG3V3_VSEL
BITS
FIELD NAME
TYPE
RESET
7
Reserved
DESCRIPTION
RW
0
6
CHGD_IDP_SRC_EN
RW
0
5
IDPULLUP_WK_EN
RW
0
4
SW_USB_DET
RW
0
3
DATA_CONTACT_DET_EN
RW
0
2:0
REG3V3_VSEL
RW
0x3
5.4.36 VENDOR_SPECIFIC3_CLR
ADDRESS OFFSET
0x87
PHYSICAL ADDRESS
0x87
INSTANCE
USB_SCUSB
DESCRIPTION
TYPE
RW
7
6
5
4
3
Reserved
CHGD_IDP_SRC_EN
IDPULLUP_WK_EN
SW_USB_DET
DATA_CONTACT_DET_EN
WRITE LATENCY
DESCRIPTION
2
1
0
REG3V3_VSEL
BITS
FIELD NAME
TYPE
RESET
7
Reserved
RW
0
6
CHGD_IDP_SRC_EN
RW
0
5
IDPULLUP_WK_EN
RW
0
4
SW_USB_DET
RW
0
3
DATA_CONTACT_DET_EN
RW
0
2:0
REG3V3_VSEL
RW
0x3
Detailed Description
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5.4.37 VENDOR_SPECIFIC4
ADDRESS OFFSET
0x88
PHYSICAL ADDRESS
0x88
DESCRIPTION
Charger Detection SERX Status and PSW,VBUS ext resistor configuration register
TYPE
RW
INSTANCE
USB_SCUSB
6
5
4
3
2
1
Reserved
ACA_DET_EN
RABUSIN_EN
R1KSERIES
PSW_OSOD
PSW_CMOS
BITS
FIELD NAME
7
Reserved
6
ACA_DET_EN
5
RABUSIN_EN
DESCRIPTION
This bit is used to enable Accessory Charger Adapter (ACA)
detection in Battery Charger State-Machine in active-mode
This bit is used modify VBUS resistance to ground.
0
CHGD_SERX_DM
7
CHGD_SERX_DP
WRITE LATENCY
TYPE
RESET
RW
0
RW
1
RW
1
RW
1
RW
0
RW
0x0
0: A-Device VBUS resistor RVBUS_IDLE_A is disabled. VBUS
resistance to ground becomes RVBUS_IDLE_B (see Section 4.18)
1: A-Device VBUS resistor RVBUS_IDLE_A is enabled (see
Section 4.18)
4
R1KSERIES
This bit is used to indicate to TUSB1211 whether an external series
1kohm resistor is connected on VBUS. When this bit is set internal
VBUS comparator thresholds are adjusted so they remain in spec.
0: No external series resistor on VBUS
1: An external 1=kΩ series resistor is connected on VBUS
3
PSW_OSOD
This bit controls PSW pin configuration. It can be overridden by
PSW_CMOS bit below
‘0’: PSW pad is in OS mode (active high)
‘1’: PSW pad is in OD mode (active low)
2
PSW_CMOS
This bit controls PSW pin configuration. It overrides PSW_OSOD
bit above.
‘0’ : PSW pad is in OD or OS mode (controlled by PSW_OD bit)
‘1’: PSW pad is in CMOS mode
62
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BITS
FIELD NAME
1
CHGD_SERX_DP
DESCRIPTION
Read-only status bit showing status of debounced charger
detection single-ended receiver comparator on DP
TYPE
RESET
R
0x0
R
0x0
0: VDP < [0.8V : 2.0V] SERX threshold
1: VDP > [0.8V : 2.0V] SERX threshold
Note: This comparator and status bit is enabled automatically in the
following scenarios:
•
When charger detection FSM is enabled and VDP_SRC or
IDP_SRC are enabled by FSM
•
When SW_CONTROL=1 and DP_VSRC_EN =1
•
When SW_CONTROL=1 and CHGD_IDP_SRC_EN=1
•
When DP_WKPU_EN bit is enabled
In all other cases (including when DP 1.5K pullup is enabled by SW
for CDP/DCP/SDP differentiation after SW charger detection step)
this status bit should be ignored and LINESTATE bits in
DEBUG register, or RXCMD should be used for DP/DM detection
0
CHGD_SERX_DM
Read-only status bit showing status of debounced charger
detection single-ended receiver comparator on DM
0: VDM < [0.8V : 2.0V] SERX threshold
1: VDM > [0.8V : 2.0V] SERX threshold
Note: This comparator and status bit is enabled automatically in the
following scenarios:
•
When charger detection FSM is enabled and VDP_SRC or
IDP_SRC are enabled by FSM
•
When SW_CONTROL=1 and DP_VSRC_EN =1
•
When SW_CONTROL=1 and CHGD_IDP_SRC_EN=1
•
When DP_WKPU_EN bit is enabled
In all other cases (including when DP 1.5K pullup is enabled by SW
for CDP/DCP/SDP differentiation after SW charger detection step)
this status bit should be ignored and LINESTATE bits in
DEBUG register, or RXCMD should be used for DP/DM detection
Detailed Description
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5.4.38 VENDOR_SPECIFIC4_SET
ADDRESS OFFSET
0x89
PHYSICAL ADDRESS
0x89
DESCRIPTION
Charger Detection SERX Status and PSW,VBUS ext resistor configuration register
TYPE
RW
INSTANCE
USB_SCUSB
6
5
4
3
2
1
Reserved
ACA_DET_EN
RABUSIN_EN
R1KSERIES
PSW_OSOD
PSW_CMOS
BITS
FIELD NAME
DESCRIPTION
0
CHGD_SERX_DM
7
CHGD_SERX_DP
WRITE LATENCY
TYPE
RESET
7
Reserved
RW
0
6
ACA_DET_EN
RW
1
5
RABUSIN_EN
RW
1
4
R1KSERIES
RW
1
3
PSW_OSOD
RW
0
2
PSW_CMOS
RW
0x0
1
CHGD_SERX_DP
R
0x0
0
CHGD_SERX_DM
R
0x0
5.4.39 VENDOR_SPECIFIC4_CLR
ADDRESS OFFSET
0x8A
PHYSICAL ADDRESS
0x8A
DESCRIPTION
Charger Detection SERX Status and PSW,VBUS ext resistor configuration register
TYPE
RW
INSTANCE
USB_SCUSB
64
6
5
4
3
2
1
Reserved
ACA_DET_EN
RABUSIN_EN
R1KSERIES
PSW_OSOD
PSW_CMOS
DESCRIPTION
0
CHGD_SERX_DM
7
CHGD_SERX_DP
WRITE LATENCY
BITS
FIELD NAME
TYPE
RESET
7
Reserved
RW
0
6
ACA_DET_EN
RW
1
5
RABUSIN_EN
RW
1
4
R1KSERIES
RW
1
3
PSW_OSOD
RW
0
2
PSW_CMOS
RW
0x0
1
CHGD_SERX_DP
R
0x0
0
CHGD_SERX_DM
R
0x0
Detailed Description
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5.4.40 VENDOR_SPECIFIC5
ADDRESS OFFSET
0x8B
PHYSICAL ADDRESS
0x8B
DESCRIPTION
Vendor-specific interrupt enable register
TYPE
RW
INSTANCE
USB_SCUSB
Reserved
ID_FLOAT_EN
ID_RES_EN
3
2
1
DESCRIPTION
0
REG3V3IN_MNTR_EN
4
VBUS_MNTR_FALL_EN
5
VBUS_MNTR_RISE_EN
6
SVLDCONWKB_WDOG _EN
7
AUTORESUME_WDOG_EN
WRITE LATENCY
BITS
FIELD NAME
TYPE
RESET
7
Reserved
RW
0
6
AUTORESUME_WDOG_EN
RW
1
RW
0
RW
0
Autoresume watchdog timer enable bit
0b: Disable the Autoresume watchdog timer
1b: Enable the Autoresume watchdog timer
Timer is be initialized and starts counting when the PHY detects a
resume-K.
5
ID_FLOAT_EN
4
ID_RES_EN
When set to ‘1’, it enables RX CMD’s for high to low or low to high transitions
on ID_FLOAT.
When set to ‘1’, this bit enables RX CMD’s for high to low or low to
high transitions on detection of ACA resistors RID_A , RID_B or
RID_C .
When this bit is set to ‘1’ and any of the above ACA resistors are
detected, TUSB1211 will send an RX CMD to the link with the
alt_int bit set to 1b.
The status of ACA detection can then be read back through status
bits ID_RARBRC_STS Setting this bit also forces ID pull-up
(RID_UP) to be enabled irrespective of IDPULLUP bit setting
3
SVLDCONWKB_WDOG _EN
Generate an interrupt event notification when SVLDCONWKB_WDOG
watchdog timer times out Note SVLDCONWKB_WDOG watchdog timer is
enabled and disabled separately, see Section 5.3.12 for more details.
RW
0
2
VBUS_MNTR_RISE_EN
Generate an interrupt event notification when VBUS_MNTR changes from
low to high.
RW
0
1
VBUS_MNTR_FALL_EN
Generate an interrupt event notification when VBUS_MNTR changes from
high to low.
R
0
0
REG3V3IN_MNTR_EN
R
0
Optional feature which can be used to indicate to Link if VBAT level
is high enough to guarantee USB functionality
0b: Disable this monitoring featue
1b: Enable monitoring of REG3V3IN (=VBAT) level through
RXCMD on detection of high to low or low to high transitions on
comparator REG3V3IN_MNTR after debounce.
Detailed Description
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5.4.41 VENDOR_SPECIFIC5_SET
ADDRESS OFFSET
0x8C
PHYSICAL ADDRESS
0x8C
DESCRIPTION
Vendor-specific interrupt set register
TYPE
RW
INSTANCE
USB_SCUSB
66
Reserved
ID_FLOAT_EN
ID_RES_EN
3
2
1
DESCRIPTION
0
REG3V3IN_MNTR_EN
4
VBUS_MNTR_FALL_EN
5
VBUS_MNTR_RISE_EN
6
SVLDCONWKB_WDOG _EN
7
AUTORESUME_WDOG_EN
WRITE LATENCY
BITS
FIELD NAME
TYPE
RESET
7
Reserved
RW
0
6
AUTORESUME_WDOG_EN
RW
1
5
ID_FLOAT_EN
RW
0
4
ID_RES_EN
RW
0
3
SVLDCONWKB_WDOG _EN
RW
0
2
VBUS_MNTR_RISE_EN
RW
0
1
VBUS_MNTR_FALL_EN
RW
0
0
REG3V3IN_MNTR_EN
RW
0
Detailed Description
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5.4.42 VENDOR_SPECIFIC5_CLR
ADDRESS OFFSET
0x8D
PHYSICAL ADDRESS
0x8D
DESCRIPTION
Vendor-specific interrupt clear register
TYPE
RW
INSTANCE
USB_SCUSB
Reserved
ID_FLOAT_EN
ID_RES_EN
3
2
1
DESCRIPTION
0
REG3V3IN_MNTR_EN
4
VBUS_MNTR_FALL_EN
5
VBUS_MNTR_RISE_EN
6
SVLDCONWKB_WDOG _EN
7
AUTORESUME_WDOG_EN
WRITE LATENCY
BITS
FIELD NAME
TYPE
RESET
7
Reserved
RW
0
6
AUTORESUME_WDOG_EN
RW
1
5
ID_FLOAT_EN
RW
0
4
ID_RES_EN
RW
0
3
SVLDCONWKB_WDOG _EN
RW
0
2
VBUS_MNTR_RISE_EN
RW
0
1
VBUS_MNTR_FALL_EN
RW
0
0
REG3V3IN_MNTR_EN
RW
0
Detailed Description
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5.4.43 VENDOR_SPECIFIC6
ADDRESS OFFSET
0x8E
PHYSICAL ADDRESS
0x8E
DESCRIPTION
SOF and ACA CFG Register
TYPE
RW
INSTANCE
USB_SCUSB
7
6
5
ACA_RID_B_CFG
ACA_RID_A_CFG
WRITE LATENCY
SOF_EN
BITS
FIELD NAME
7
ACA_RID_B_CFG
4
3
2
1
0
Reserved
DESCRIPTION
This bit is used to enable correct configuration of TUSB1211 as a
B-device with ACA connected and nothing (or A-device OFF) at
ACA Accessory port and charger present on ACA Charger Port,
if ACA RID_B is detected on ID pin. It impacts:
TYPE
RESET
RW
0
RW
0
RW
0
RW
0
a) VA_VBUS_VLD in RX CMD
b) VSESS_VLD in RX CMD
c) VBUS SRP
When this bit is‘1’ and RID_B is detected on ID pin , then mask
VBUS plug detection information from being sent to the link, and
mask
OTG
VBUS
SRP
commands
(CHRGVBUS,
DISCHRGVBUS bits) from the link. Set VA_VBUS_VLD =0 and
VSESS_VLD =0 in RX CMD, and disable RB_SRP_UP,
RB_SRP_DWN
Note: CHRGVBUS, DISCHRGVBUS register bit settings
themselves are unchanged but VBUS SRP pullup and pulldown
are disabled.
When this bit is ‘0’ RID_B detection has no impact on
VA_VBUS_VLD detection and VA_SESS_VLD detection in RX
CMD
6
ACA_RID_A_CFG
This bit is used to enable correct configuration of TUSB1211 as
an A-device with ACA connected and B-device at ACA
Accessory port and charger connected to Charger Port , if ACA
RID_A is detected on ID pin. It impacts:
a) IDGND detection in RXCMD and
b) Enabling of external VBUS on PSW pin
When this bit is ‘1’ and RID_A is detected on ID pin then
TUSB1211 will be configured as an A-device by set ID=0 in
RXCMD (equivalent to IDGND detected). In addition PSW pin is
deasserted to avoid contention on VBUS pin since the charger at
ACA port already provides VBUS.
When this bit is ‘0’ RID_A detection has no impact on RXCMD
nor PSW pin
5
SOF_EN
USB HS Start-of-Frame clock output feature enable
0: Disable HS SOF clock
1: Enable HS SOF clock output on SOF pin
HS USB SOF packet rate is 8kHz
4:0
68
Reserved
Detailed Description
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5.4.44 VENDOR_SPECIFIC6_SET
ADDRESS OFFSET
0x8F
PHYSICAL ADDRESS
0x8F
DESCRIPTION
SOF and ACA CFG Register
TYPE
RW
INSTANCE
USB_SCUSB
7
6
5
ACA_RID_B_CFG
ACA_RID_A_CFG
WRITE LATENCY
SOF_EN
BITS
FIELD NAME
7
6
4
3
2
1
0
Reserved
DESCRIPTION
TYPE
RESET
ACA_RID_B_CFG
RW
0
ACA_RID_A_CFG
RW
0
5
SOF_EN
RW
0
4:0
Reserved
RW
0
5.4.45 VENDOR_SPECIFIC6_CLR
ADDRESS OFFSET
0x90
PHYSICAL ADDRESS
0x90
DESCRIPTION
SOF and ACA CFG Register
TYPE
RW
INSTANCE
USB_SCUSB
7
6
5
ACA_RID_B_CFG
ACA_RID_A_CFG
WRITE LATENCY
SOF_EN
4
3
2
1
0
Reserved
BITS
FIELD NAME
TYPE
RESET
7
ACA_RID_B_CFG
DESCRIPTION
RW
0
6
ACA_RID_A_CFG
RW
0
5
SOF_EN
RW
0
4:0
Reserved
RW
0
Detailed Description
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6 Application, Implementation, and Layout
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
6.1
Application Information
Figure 6-1 shows the suggested application diagram (host or OTG, ULPI output-clock mode).
The TUSB1211 is a USB2.0 transceiver chip, designed to interface with a USB controller through a ULPI
interface. The device supports all USB2.0 data rates (high-speed, full-speed, and low-speed) and it is
compliant to both host and peripheral (OTG) modes. Use Section 6.2.1 and Section 6.2.2 to select the
wished operation mode. This section presents a simplified discussion of the design process.
6.2
Typical Application
VBAT Supply
RCDETPUOD
CHRG_DET
CHRG_POL
(D)
CHRG_EN_N
D)
(C
F2
To Charger
F1
E1
VBUSSupply
(B)
Link
Controller
(A)
SOF
REFCLK
(A)
RESET_N
CS
DIR
NXT
STP
CLOCK
C3
F6
F5
C4
B3
E5
D5
D6
A4
CS_N
SOF
REFCLK
RESET_N
cS
DIR
NXT
STP
CLOCK
FAULT
PSW
VBUS
ID
DM
DP
GND
GND
GND
NC
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
B1
A1
A2
A3
A5
A6
B6
C6
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
REG1V5
REG3V3
(E)
CFG
VDDIO
VDDIO
VBAT
E2
D4
FAULT
EN OUT
F4
USB Receptacle
VBUS
D3
ID
DM
DP
SHIELD
GND
C1
D1
E4
D2
ESD
TPD4S012
C5
No Connection
C2
E6
CVDD15
CVDD33
E3
B4
VDDIO Supply
B2
CVDDIO
B5
F3
VBAT Supply
CBYP
A.
B.
C.
D.
E.
Optional: SOF (open if unused); RESET_N (tie to VDDIO if unused)
Link controls chip select through CS pin with CS_N at GND. Alternatively, Link may control CS_N pin with CS pin tied
to VDDIO.
CHRG_DET is active-low (tie CHRG_POL to VBAT for CHRG_DET active high).
Dead battery charger detection is enabled (tie CHRG_EN_N to VBAT to disable).
CFG tied to VDDIO for 26 MHz input at REFCLK (tie to GND for 19.2 MHz).
Figure 6-1. USB-OTG With ULPI Output Clock
70
Application, Implementation, and Layout
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Design Requirements
Table 6-1. Design Parameters
6.2.2
DESIGN PARAMETER
EXAMPLE VALUE
VBAT
3.3 V
VDDIO
1.8 V
VBUS
5V
USB Support
HS, FS, LS
USB Battery Charger Detection
Yes
USB On the Go (OTG)
Yes
Clock sources
26 MHz or 19.2 MHz oscillator
Detailed Design Procedure
Connect the TUSB12111 device as is shown in the suggested application diagram, Figure 6-1. Follow the
Board Guidelines of the Application Report, TUSB121x USB2.0 Board Guidelines (SWCA124)
Table 6-2. External Components
FUNCTION
COMPONENT
REFERENCE
VALUE
NOTE
VDDIO
Capacitor
CVDDIO.IN
100 nF
REG3V3
Capacitor
CREG3V3
2.2 µF (recommended)
Suggested value, application dependent
Range: [0.45 μF : 6.5 μF]
ESR = [0 : 600 mΩ] for f > 10 kHz
REG1V5
Capacitor
CREG1V5
2.2 µF (recommended)
Range: [0.45 μF : 6.5 μF]
ESR = [0 : 600 mΩ] for f > 10 kHz
VBAT
Capacitor
CBYP
2.2 µF (recommended)
Range: [0.45 μF : 6.5 μF]
ESR = [0 : 600 mΩ] for f > 10 kHz
VBUS
Capacitor
CVBUS
4.7 µF (recommended)
Place close to USB connector
Table 6-3. VBUS Capacitors
FUNCTION
COMPONENT
REFERENCE
VALUE
VBUS – HOST
Capacitor
CVBUS
> 120 μF
VBUS – DEVICE
Capacitor
CVBUS
4.7 μF
Range: 1.0 μF to 10.0 μF
VBUS – OTG
Capacitor
CVBUS
4.7 μF
Range: 1.0 μF to 6.5 μF
6.2.2.1
•
•
•
•
•
•
NOTE
Unused Pins Connection
CHRG_DET Output. Leave floating if unused.
CHRG_POL Input. Tie to GND to make CHRG_DET pin active low if unused.
CHRG_EN_N Input. Tie to VBAT to disable dead-battery charger detection if unused.
SOF Output. Leave floating if unused.
REFCLK Input. If REFCLK is unused, and 60-MHz clock is provided by MODEM (60 MHz should be
connected to CLOCK pin in this case) then tie REFCLK to GND.
CFG tie to GND if REFCLK is 19.2 MHz, or tie to VDDIO if REFCLK is 26 MHz. Tie to either GND or
VDDIO (do not care which) if REFCLK not used (that is, ULPI input clock configuration).
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6.2.3
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Application Curves
Figure 6-2. High-Speed Eye Diagram
6.3
Figure 6-3. Full-Speed Eye Diagram
Layout
6.3.1
Layout Guidelines
•
•
•
•
6.3.1.1
The VDDIO pins of the TUSB1211 supply 1.8 V (nominal) power to the core of the TUSB1211 device.
This power rail can be isolated from all other power rails by a ferrite bead to reduce noise.
The VBAT pin of the TUSB1211 supply 3.3 V (nominal) power rail to the TUSB1211 device. This
power rail can be isolated from all other power rails by a ferrite bead to reduce noise.
The VBUS pin of the TUSB1211 supply 5 V (nominal) power rail to the TUSB1211 device. This pin is
normally connected to the VBUS pin of the USB connector.
All power rails require 0.1-μF decoupling capacitors for stability and noise immunity. The smaller
decoupling capacitors should be placed as close to the TUSB1211 device power pins as possible with
an optimal grouping of two of differing values per pin.
Ground
TI recommends using almost one board ground plane be used in the design. This provides the best image
plane for signal traces running above the plane. An earth or chassis ground is implemented only near the
USB port connectors on a different plane for EMI and ESD purposes.
72
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6.3.2
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Layout Example
Figure 6-4. TUSB1211 Layout
6.4
Power Supply Recommendations
VBUS, VBAT, and VDDIO are needed for power the TUSB1211 device.
The recommended operation is for VBAT to be present before VDDIO. Applying VDDIO before VBAT to
the TUSB1211 device is not recommended because a diode from VDDIO to VBAT will be forward-biased
when VDDIO is present but VBAT is not present. TUSB121x does not strictly require VBUS to function.
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7 Device and Documentation Support
7.1
7.1.1
Documentation Support
Related Documentation
See TUSB121x USB2.0 Board Guidelines (SWCA124) for a description of the TUSB1211 board
guidelines.
7.1.2
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools
and contact information for technical support.
7.2
Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
7.3
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
7.4
Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
8 Mechanical Packaging and Orderable Information
8.1
Packaging Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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