MPC506AU

MP C50 6 MP MPC506A MPC507A C50 7 SBFS018A – JANUARY 1988 – REVISED OCTOBER 2003 Single-Ended 16-Channel/Differential 8-Channel CMOS ANALOG MULTIPLEXERS FEATURES q ANALOG OVERVOLTAGE PROTECTION: 70VPP q NO CHANNEL INTERACTION DURING OVERVOLTAGE q BREAK-BEFORE-MAKE SWITCHING q ANALOG SIGNAL RANGE: ±15V q STANDBY POWER: 7.5mW typ q TRUE SECOND SOURCE In 16 In 2 1kΩ 1kΩ In 1 1kΩ Decoder/ Driver Out FUNCTIONAL DIAGRAMS DESCRIPTION The MPC506A is a 16-channel single-ended analog multiplexer, and the MPC507A is an 8-channel differential multiplexer. The MPC506A and MPC507A multiplexers have input overvoltage protection. Analog input voltages may exceed either power supply voltage without damaging the device or disturbing the signal path of other channels. The protection circuitry assures that signal fidelity is maintained even under fault conditions that would destroy other multiplexers. Analog inputs can withstand 70VPP signal levels and standard ESD tests. Signal sources are protected from short circuits should multiplexer power loss occur; each input presents a 1kΩ resistance under this condition. Digital inputs can also sustain continuous faults up to 4V greater than either supply voltage. These features make the MPC506A and MPC507A ideal for use in systems where the analog signals originate from external equipment or separately powered sources. The MPC506A and MPC507A are fabricated with BurrBrown’s dielectrically isolated CMOS technology. The multiplexers are available in plastic DIP and plastic SOIC packages. Temperature range is –40/+85°C. Overvoltage Clamp and Signal Isolation NOTE: (1) Digital Input Protection. MPC506A 5V Ref Level Shift (1) (1) (1) (1) (1) VREF A0 A1 A2 A3 EN 1kΩ In 1A 1kΩ In 8A 1kΩ In 1B 1kΩ In 8B Overvoltage Clamp and Signal Isolation NOTE: (1) Digital Input Protection. MPC507A Out B Decoder/ Driver Out A 5V Ref Level Shift (1) (1) (1) (1) VREF A0 A1 A2 EN Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1988-2003, Texas Instruments Incorporated www.ti.com ELECTRICAL CHARACTERISTICS Supplies = +15V, –15V; VREF (Pin 13) = Open; VAH (Logic Level High) = +4.0V; VAL (Logic Level Low) = +0.8V unless otherwise specified. MPC506A/MPC507A PARAMETER ANALOG CHANNEL CHARACTERISTICS VS, Analog Signal Range RON, On Resistance(1) IS (OFF), Off Input Leakage Current ID (OFF), Off Output Leakage Current MPC506A MPC507A ID (OFF) with Input Overvoltage Applied(2) ID (ON), On Channel Leakage Current MPC506A MPC507A IDIFF Differential Off Output Leakage Current (MPC507A Only) DIGITAL INPUT CHARACTERISTICS VAL, Input Low Threshold VAH, Input High Threshold(3) VAL, MOS Drive(4) VAH, MOS Drive(4) IA, Input Leakage Current (High or Low)(5) SWITCHING CHARACTERISTICS tA, Access Time tOPEN, Break-Before-Make Delay tON (EN), Enable Delay (ON) tOFF (EN), Enable Delay (OFF) Settling Time (0.1%) (0.01%) "OFF Isolation"(6) CS (OFF), Channel Input Capacitance CD (OFF), Channel Output Capacitance: MPC506A MPC507A CA, Digital Input Capacitance CDS, (OFF), Input to Output Capacitance POWER REQUIREMENTS PD, Power Dissipation I+, Current Pin 1(7) I–, Current Pin 27(7) TEMP Full +25°C Full +25°C Full +25°C Full Full +25°C +25°C Full Full Full Full Full +25°C +25°C Full +25°C Full +25°C +25°C Full +25°C Full +25°C +25°C +25°C +25°C +25°C +25°C 25°C +25°C Full Full Full MIN –15 1.3 1.5 0.5 0.2 5 5 2 2 10 10 10 0.8 4.0 0.8 6.0 1.0 0.3 0.6 25 80 200 500 250 500 1.2 3.5 68 5 50 25 5 0.1 7.5 0.7 5 TYP MAX +15 1.5 1.8 10 UNITS V kΩ kΩ nA nA nA nA nA µA nA nA nA nA V V V V µA µs µs ns ns ns ns ns µs µs dB pF pF pF pF pF mW mA µA 50 1.5 20 NOTES: (1) VOUT = ±10V, IOUT = –100µA. (2) Analog overvoltage = ±33V. (3) To drive from DTL/TTL circuits. 1kΩ pull-up resistors to +5.0V supply are recommended. (4) VREF = +10V. (5) Digital input leakage is primarily due to the clamp diodes. Typical leakage is less than 1nA at 25°C. (6) VEN = 0.8V, RL = 1kΩ, CL = 15pF, VS = 7Vrms, f = 100kHz. Worst-case isolation occurs on channel 8 due to proximity of the output pins. (7) VEN, VA = 0V or 4.0V. 2 MPC506A, MPC507A www.ti.com SBFS018A PIN CONFIGURATION Top View +VSUPPLY NC NC In 16 In 15 In 14 In 13 In 12 In 11 1 2 3 4 5 6 7 8 9 28 Out 27 –VSUPPLY +VSUPPLY Out B NC In 8B In 7B In 6B In 5B In 4B In 3B 1 2 3 4 5 6 7 8 9 Top View 28 Out A 27 –VSUPPLY 26 In 8 25 In 7 24 In 6 23 In 5 22 In 4 21 In 3 20 In 2 19 In 1 18 Enable 17 Address A0 16 Address A1 15 Address A2 MPC506A (Plastic) 26 In 8A 25 In 7A 24 In 6A 23 In 5A 22 In 4A 21 In 3A 20 In 2A 19 In 1A 18 Enable 17 Address A0 16 Address A1 15 Address A2 MPC507A (Plastic) In 10 10 In 9 11 Ground 12 VREF 13 Address A3 14 In 2B 10 In 1B 11 Ground 12 VREF 13 NC 14 TRUTH TABLES MPC506A A3 X L L L L L L L L H H H H H H H H A2 X L L L L H H H H L L L L H H H H A1 X L L H H L L H H L L H H L L H H A0 X L H L H L H L H L H L H L H L H EN L H H H H H H H H H H H H H H H H "ON" CHANNEL None 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A2 X L L L L H H H H A1 X L L H H L L H H A0 X L H L H L H L H EN L H H H H H H H H MPC507A "ON" CHANNEL PAIR None 1 2 3 4 5 6 7 8 MPC506A, MPC507A SBFS018A www.ti.com 3 ABSOLUTE MAXIMUM RATINGS(1) Voltage between supply pins ............................................................... 44V VREF to ground, V+ to ground ............................................................... 22V V– to ground ........................................................................................ 25V Digital input overvoltage: VEN, VA: VSUPPLY (+) ............................................................................ +4V VSUPPLY (–) ............................................................................ –4V or 20mA, whichever occurs first. Analog input overvoltage: VS: VSUPPLY (+) .................................................................................. +20V VSUPPLY (–) .................................................................................. –20V Continuous current, S or D ............................................................... 20mA Peak current, S or D (pulsed at 1ms, 10% duty cycle max) ............................................ 40mA Power dissipation* ............................................................................. 2.0W Operating temperature range ........................................... –40°C to +85°C Storage temperature range ............................................. –65°C to +150°C *Derate 20.0mW/°C above TA = 70 NOTE: (1) Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be impaired. Functional operation under any of these conditions is not necessarily implied. PACKAGE/ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet. TYPICAL PERFORMANCE CURVES TA = +25°C unless otherwise noted. SETTLING TIME vs SOURCE RESISTANCE FOR 20V STEP CHANGE 1k Crosstalk (% of Off Channel Signal) CROSSTALK vs SIGNAL FREQUENCY 1 100 Settling Time (µs) 0.1 Rs = 100kΩ To ±0.01% 10 To ±0.1% 1 0.01 Rs = 10kΩ R s = 1kΩ Rs = 100Ω 0.001 0.1 0.01 0.0001 0.1 1 Source Resistance (kΩ) 10 100 1 10 100 Signal Frequency (Hz) 1k 10k COMBINED CMR vs FREQUENCY MPC507A AND INA110 120 Common-Mode Rejection (dB) 100 80 60 40 20 0 1 10 100 Frequency (Hz) G = 500 G = 100 G = 10 1k 10k 4 MPC506A, MPC507A www.ti.com SBFS018A DISCUSSION OF SPECIFICATIONS DC CHARACTERISTICS The static or dc transfer accuracy of transmitting the multiplexer input voltage to the output depends on the channel ON resistance (RON), the load impedance, the source impedance, the load bias current and the multiplexer leakage current. Single-Ended Multiplexer Static Accuracy The major contributors to static transfer accuracy for singleended multiplexers are: Source resistance loading error Multiplexer ON resistance error dc offset error caused by both load bias current and multiplexer leakage current. Resistive Loading Errors The source and load impedances will determine the input resistive loading errors. To minimize these errors: • Keep loading impedance as high as possible. This minimizes the resistive loading effects of the source resistance and multiplexer ON resistance. As a guideline, load impedance of 108Ω or greater will keep resistive loading errors to 0.002% or less for 1000Ω source impedances. A 106Ω load impedance will increase source loading error to 0.2% or more. • Use sources with impedances as low as possible. A 1000Ω source resistance will present less than 0.001% loading error and 10kΩ source resistance will increase source loading error to 0.01% with a 108 load impedance. Input resistive loading errors are determined by the following relationship (see Figure 1). IBIAS VM VS1 RS16 ROFF IL Measured Voltage ZL VS16 Input Offset Voltage Bias current generates an input OFFSET voltage as a result of the IR drop across the multiplexer ON resistance and source resistance. A load bias current of 10nA will generate an offset voltage of 20µV if a 1kΩ source is used. In general, for the MPC506A, the OFFSET voltage at the output is determined by: VOFFSET = (IB + IL) (RON + RS) where IB = Bias current of device multiplexer is driving IL = Multiplexer leakage current RON = Multiplexer ON resistance RS = Source resistance Differential Multiplexer Static Accuracy Static accuracy errors in a differential multiplexer are difficult to control, especially when it is used for multiplexing low-level signals with full-scale ranges of 10mV to 100mV. The matching properties of the multiplexer, source and output load play a very important part in determining the transfer accuracy of the multiplexer. The source impedance unbalance, common-mode impedance, load bias current mismatch, load differential impedance mismatch, and common-mode impedance of the load all contribute errors to the multiplexer. The multiplexer ON resistance mismatch, leakage current mismatch and ON resistance also contribute to differential errors. Referring to Figure 2, the effects of these errors can be minimized by following the general guidelines described in this section, especially for low-level multiplexing applications. RS1 RON RS1A RON1A IBIAS A Cd/2 RCM IL VS1 RS1B RON1B IBIAS B Cd/2 Rd/2 RS8A ROFF8A Rd/2 RCM ZL CCM RCM1 FIGURE 1. MPC506A Static Accuracy Equivalent Circuit. VS8 Source and Multiplexer Resistive Loading Error ∈(RS + RON ) = RS + RON × 100 RS + RON + RL RCM8 RS8B ROFF8B where RS = source resistance RL = load resistance RON = multiplexer ON resistance FIGURE 2. MPC507A Static Accuracy Equivalent Circuit. MPC506A, MPC507A SBFS018A www.ti.com 5 Load (Output Device) Characteristics • Use devices with very low bias current. Generally, FET input amplifiers should be used for low-level signals less than 50mV FSR. Low bias current bipolar input amplifiers are acceptable for signal ranges higher than 50mV FSR. Bias current matching will determine the input offset. • The system dc common-mode rejection (CMR) can never be better than the combined CMR of the multiplexer and driven load. System CMR will be less than the device which has the lower CMR figure. • Load impedances, differential and common-mode, should be 1010Ω or higher. SOURCE CHARACTERISTICS • The source impedance unbalance will produce offset, common-mode and channel-to-channel gain-scatter errors. Use sources which do not have large impedance unbalances if at all possible. • Keep source impedances as low as possible to minimize resistive loading errors. • Minimize ground loops. If signal lines are shielded, ground all shields to a common point at the system analog common. If the MPC507A is used for multiplexing high-level signals of 1V to 10V full-scale ranges, the foregoing precautions should still be taken, but the parameters are not as critical as for low-level signal applications. DYNAMIC CHARACTERISTICS Settling Time The gate-to-source and gate-to-drain capacitance of the CMOS FET switches, the RC time constants of the source and the load determine the settling time of the multiplexer. Governed by the charge transfer relation i = C (dV/dt), the charge currents transferred to both load and source by the analog switches are determined by the amplitude and rise time of the signal driving the CMOS FET switches and the gate-to-drain and gate-to-source junction capacitances as shown in Figures 3 and 4. Using this relationship, one can see that the amplitude of the switching transients seen at the source and load decrease proportionally as the capacitance of the load and source increase. The trade-off for reduced switching transient amplitude is increased settling time. In effect, the amplitude of the transients seen at the source and load are: dVL = (i/C) dt where i = C (dV/dt) of the CMOS FET switches C = load or source capacitance The source must then redistribute this charge, and the effect of source resistance on settling time is shown in the Typical Performance Curves. This graph shows the settling time for a 20V step change on the input. The settling time for smaller step changes on the input will be less than that shown in the curve. RSA Node A CSA Source CSB RdA CdA ZCM RCMS MPC507A Load Channel RdB Node B CdB CCMS RSB FIGURE 4. Settling and Common-Mode Effects— MPC507A Switching Time This is the time required for the CMOS FET to turn ON after a new digital code has been applied to the Channel Address inputs. It is measured from the 50 percent point of the address input signal to the 90 percent point of the analog signal seen at the output for a 10V signal change between channels. Crosstalk Crosstalk is the amount of signal feedthrough from the seven (MPC507A) or 15 (MPC506A) OFF channels appearing at the multiplexer output. Crosstalk is caused by the voltage divider effect of the OFF channel, OFF resistance and junction capacitances in series with the RON and RS impedances of the ON channel. Crosstalk is measured with a 20Vp-p 1000Hz sine wave applied to all off channels. The crosstalk for these multiplexers is shown in the Typical Performance Curves. MPC506A Channel Source Load Node A RS CS CL RL FIGURE 3. Settling Time Effects—MPC506A. 6 MPC506A, MPC507A www.ti.com SBFS018A Common-Mode Rejection (MPC507A Only) The matching properties of the load, multiplexer and source affect the common-mode rejection (CMR) capability of a differentially multiplexed system. CMR is the ability of the multiplexer and input amplifier to reject signals that are common to both inputs, and to pass on only the signal difference to the output. For the MPC507A, protection is provided for common-mode signals of ±20V above the power supply voltages with no damage to the analog switches. The CMR of the MPC507A and Burr-Brown's INA110 instrumentation amplifier (G = 100) is 110dB at DC to 10Hz with a 6dB/octave roll-off to 70dB at 1000Hz. This measurement of CMR is shown in the Typical Performance Curves and is made with a Burr-Brown INA110 instrumentation amplifier connected for gains of 500, 100, and 10. Factors which will degrade multiplexer and system DC CMR are: • Amplifier bias current and differential impedance mismatch • Load impedance mismatch • Multiplexer impedance and leakage current mismatch • Load and source common-mode impedance AC CMR roll-off is determined by the amount of commonmode capacitances (absolute and mismatch) from each signal line to ground. Larger capacitances will limit CMR at higher frequencies; thus, if good CMR is desired at higher frequencies, the common-mode capacitances and unbalance of signal lines and multiplexer to amplifier wiring must be minimized. Use twisted-shielded pair signal lines wherever possible. SWITCHING WAVEFORMS Typical at +25°C, unless otherwise noted. BREAK-BEFORE-MAKE DELAY (tOPEN) VAM 4.0V Address Drive VA (VA) Output 50% tOPEN 50% MPC506A1 A3 A2 A1 A0 En +4.0V In 1 In 2 Thru In 15 In 16 +5V VA Input 2V/Div 0V 50Ω 1 On VOUT GND Out 1kΩ 12.5pF 16 On Output 0.5V/Div NOTE: (1) Similar connection for MPC507A. 100ns/Div ENABLE DELAY (tON (EN), tOFF (EN)) Enable Drive VAM = 4.0V 50% 0V Output 90% 90% tON(EN) tOFF(EN) VA MPC506A1 A3 A2 A1 A0 En 50Ω In 1 In 2 Thru In 16 +10V GND Out 1kΩ 1 On 12.5pF In 1 Thru In 16 Off Output 2V/Div NOTE: (1) Similar connection for MPC507A. 100ns/Div MPC506A, MPC507A SBFS018A www.ti.com 7 PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS TA = +25°C, VS = ±15V, VAM = +4V, VAL = 0.8V and VREF = Open, unless otherwise noted. ON RESISTANCE vs INPUT SIGNAL, SUPPLY VOLTAGE 100µA RON = V2/100µA In Out VIN ON RESISTANCE vs ANALOG INPUT VOLTAGE 1.4 Normalized On Resistance (Referred to Value at ±15V) 1.3 1.2 On Resistance (kΩ) 1.1 1.0 0.9 0.8 0.7 0.6 –10 –8 –6 –4 –2 0 2 4 6 8 10 V2 NORMALIZED ON RESISTANCE vs SUPPLY VOLTAGE 1.6 ±125°C > T A > –55°C VIN = +5V TA = +125°C TA = +25°C 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 ±5 ±6 ±7 ±8 ±9 TA = –55°C ±10 ±11 ±12 ±13 ±14 ±15 Analog Input (V) Supply Voltage (V) ANALOG INPUT OVERVOLTAGE CHARACTERISTICS 21 Positive Input Overvoltage Analog Input Current (mA) 7 6 5 Analog Input Current (IIN) 4 3 Output Off Leakage Current IO (Off) +12 +15 +18 +21 +24 +27 +30 +33 2 1 0 +36 Output Off Leakage Current (nA) Output Off Leakage Current (µA) 18 15 12 9 6 3 0 Analog Input Overvoltage (V) IIN A +VIN IO (Off) A 21 Negative Input Overvoltage Analog Input Current (mA) 18 15 12 9 6 3 0 −12 −15 −18 −21 −24 −27 −30 −33 −36 Analog Input Overvoltage (V) Output Off Leakage Current IO (Off) Analog Input Current (IIN) 4 IIN A −V IN IO (Off) A 2 0 8 MPC506A, MPC507A www.ti.com SBFS018A PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS (CONT) TA = +25°C, VS = ±15V, VAM = +4V, VAL = 0.8V and VREF = Open, unless otherwise noted. LEAKAGE CURRENT vs TEMPERATURE En Out +0.8V Out A ±10V ID (Off) 10V ±10V A0 En A1 A ID (On) ± 10V Out IS (Off) ±10V ± 10V A En +0.8V Leakage Current NOTE: (1) Two measurements per channel: +10V/–10V and –10V/+10V. (Two measurements per device for ID (Off): +10V/–10V and –10V/+10V). ON-CHANNEL CURRENT vs VOLTAGE ±14 ±12 –55°C +25°C +125°C Switch Current (mA) ±V IN MPC506A, MPC507A SBFS018A ± +4.0V 100nA Off Output Current ID (Off) On Leakage Current ID (On) 1nA Off Input Leakage Current IS (Off) 10nA 100pA 10pA 25 50 75 Temperature (°C) 100 125 ±10 ±8 ±6 ±4 ±2 0 0 ±2 ±4 ±6 ±8 ±10 ±12 A ±14 ±16 VIN –Voltage Across Switch (V) www.ti.com 9 PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS (CONT) TA = +25°C, VS = ±15V, VAM = +4V, VAL = 0.8V and VREF = Open, unless otherwise noted. SUPPLY CURRENT vs TOGGLE FREQUENCY +15V/+10V 8 A +ISUPPLY MPC506A(1) +V A3 In 1 A2 A In 2 Thru In 15 1 ±10V/±5V VA 50Ω Supply Current (mA) 6 4 A0 En GND +4V VS = ±15V In 16 –V Out ±10V/±5V 2 10MΩ 14pF 0 100 1k 10k 100k VS = ±10V A –ISUPPLY –15V/–10V NOTE: (1) Similar connection for MPC507A. 1M 10M Toggle Frequency (Hz) ACCESS TIME vs LOGIC LEVEL (High) 1000 +15V Access Time (ns) A3 A2 A1 A0 VREF +V –10V In 1 In 2 Thru In 15 MPC 506A(1) In 16 –V Out 10MΩ –15V 14pF 900 800 700 600 500 400 300 3 NOTE: (1) Similar connection for MPC507A. 4 5 6 7 8 9 10 11 12 13 14 15 Logic Level High (V) VREF = Open for logic high levels ≤ 6V VREF = Logic high for logic high levels > 6V VA 50Ω +10V Probe +4V En GND ACCESS TIME WAVEFORM VAH 1/2VAH 10V 4.0V Address Drive (VA) 0V VA Input 2V/Div 90% 10V tA Output A 5V/Div 200ns/Div 10 MPC506A, MPC507A www.ti.com SBFS018A INSTALLATION AND OPERATING INSTRUCTIONS The ENABLE input, pin 18, is included for expansion of the number of channels on a single node as illustrated in Figure 5. With ENABLE line at a logic 1, the channel is selected by the 3-bit (MPC507A or 4-bit MPC506A) Channel Select Address (shown in the Truth Tables). If ENABLE is at logic 0, all channels are turned OFF, even if the Channel Address Lines are active. If the ENABLE line is not to be used, simply tie it to +V supply. If the +15V and/or –15V supply voltage is absent or shorted to ground, the MPC507A and MPC506A multiplexers will not be damaged; however, some signal feedthrough to the output will occur. Total package power dissipation must not be exceeded. For best settling speed, the input wiring and interconnections between multiplexer output and driven devices should be kept as short as possible. When driving the digital inputs from TTL, open collector output with pull up resistors are recommended (see Typical Performance Curves, Access Time). To preserve common-mode rejection of the MPC507A, use twisted-shielded pair wire for signal lines and inter-tier connections and/or multiplexer output lines. This will help common-mode capacitance balance and reduce stray signal pickup. If shields are used, all shields should be connected as close as possible to system analog common or to the common-mode guard driver. In 1 In 2 MPC Out In 3 506A 28 Group 1 Ch1-16 Group 1 In 16 18 Enable A3 A 2 A 1 A 0 20 21 22 23 24 25 A 3 A2 A1 A0 Group 4 18 Enable MPC506A Group 4 Out 49-64 28 6-Bit To Binary Group Counter 2 1 of 4 Decoder Differential Multiplexer (MPC507A) Single or multitiered configurations can be used to expand multiplexer channel capacity up to 64 channels using a 64 x 1 or an 8 x 8 configuration. Single-Node Expansion The 64 x 1 configuration is simply eight (MPC507A) units tied to a single node. Programming is accomplished with a 6-bit counter, using the 3LSBs of the counter to control Channel Address inputs A0, A1, A2 and the 3MSBs of the counter to drive a 1-of-8 decoder. The 1-of-8 decoder then is used to drive the ENABLE inputs (pin 18) of the MPC507A multiplexers. Two-Tier Expansion Using an 8 x 8 two-tier structure for expansion to 64 channels, the programming is simplified. The 6-bit counter output does not require a 1-of-8 decoder. The 3LSBs of the counter drive the A0, A1 and A2 inputs of the eight first-tier multiplexers and the 3MSBs of the counter are applied to the A0, A1, and A2 inputs of the second-tier multiplexer. Single vs Multitiered Channel Expansion In addition to reducing programming complexity, two-tier configuration offers the added advantages over single-node expansion of reduced OFF channel current leakage (reduced OFFSET), better CMR, and a more reliable configuration if a channel should fail ON in the single-node configuration, data cannot be taken from any channel, whereas only one channel group is failed (8 or 16) in the multitiered configuration. 16 Analog Inputs (Ch1 to 16) 16 Analog Inputs Multiplexer Output Direct In 1 In 2 In 3 28 Out MPC506A In 16 18 En +V In 1 Out 28 En 18 In 16 A 0 A1 A2 A3 Out +V Buffered OPA602 1/4 OPA404 Multiplexer Output Direct A 0 A1 A 2 A3 16 Analog Inputs To Group 3 16 Analog Inputs (Ch241 to 256) Buffered OPA602 1/4 OPA404 MPC506A In 1 In 2 In 3 18 Settling time to 0.01% for RS 100Ω —Two MPC506A units in parallel 10µs —Four MPC507A units in parallel 12µs In 16 MPC506A En 28 +V A 0 A1 A2 A3 FIGURE 5. 64-Channel, Single-Tier Expansion. CHANNEL EXPANSION Single-Ended Multiplexer (MPC506A) Up to 64 channels (four multiplexers) can be connected to a single node, or up to 256 channels using 17 MPC506A multiplexers on a two-tiered structure as shown in Figures 5 and 6. Settling Time to 0.01% is 20µs with RS = 100Ω 4LSBs 4MSBs 8-Bit Channel Address Generator FIGURE 6. Channel Expansion up to 256 Channels Using 16x16 Two-Tiered Expansion 11 MPC506A, MPC507A SBFS018A www.ti.com PACKAGE OPTION ADDENDUM www.ti.com 27-Aug-2004 PACKAGING INFORMATION ORDERABLE DEVICE MPC506AP MPC506AU MPC506AU/1K MPC507AP MPC507AU MPC507AU/1K STATUS(1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE PACKAGE TYPE PDIP SOIC SOIC PDIP SOIC SOIC PACKAGE DRAWING NTD DW DW NTD DW DW PINS 28 28 28 28 28 28 PACKAGE QTY 13 1 1000 13 28 1000 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. MECHANICAL DATA MPDI056 – APRIL 2001 NTD (R-PDIP-T28) PLASTIC DUAL-IN-LINE 1.565 (39,75) 1.380 (35,05) 28 D 15 0.580 (14,73) 0.485 (12,32) D 1 Index Area H 0.015 (0,38) MIN C 0.070 (1,78) Base Plane 0.030 (0,76) 14 0.250 (6,35) MAX C 0.195 (4,95) 0.125 (3,18) 0.625 (15,88) 0.600 (15,24) E –C– E Seating Plane 0.005 (0,13) MIN 4 PL D Full Lead 0.100 (2,54) 0.022 (0,56) 0.014 (0,36) 0.010 (0,25) M C 0.200 (5,08) 0.115 (2,92) C 0.600 (15,26) 0.015 (0,38) 0.008 (0,20) 0.060 (1,52) F 0.000 (0,00) 0.700 (17,78) MAX F 4202496/A 03/01 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Dimensions are measured with the package seated in JEDEC seating plane gauge GS-3. D. Dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 (0,25). E. Dimensions measured with the leads constrained to be perpendicular to Datum C. F. Dimensions are measured at the lead tips with the leads unconstrained. G. Pointed or rounded lead tips are preferred to ease insertion. H. Maximum dimension does not include dambar protrusions. Dambar protrusions shall not exceed 0.010 (0,25). I. Distance between leads including dambar protrusions to be 0.005 (0,13) minumum. J. A visual index feature must be located within the cross-hatched area. K. For automatic insertion, any raised irregularity on the top surface (step, mesa, etc.) shall be symmetrical about the lateral and longitudinal package centerlines. L. Controlling dimension in inches. M. Falls within JEDEC MS-011-AB. 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