MSP432™ SimpleLink™ Microcontrollers
Hardware Tools
User's Guide
Literature Number: SLAU571D
March 2015 – Revised June 2018
Contents
Preface ........................................................................................................................................ 4
1
Hardware
1.1
1.2
1.3
............................................................................................................................ 5
MSP-FET-432ADPTR ....................................................................................................... 6
1.1.1 Introduction .......................................................................................................... 6
1.1.2 Key Features ........................................................................................................ 6
1.1.3 Kit Contents.......................................................................................................... 6
1.1.4 Configuration and Usage .......................................................................................... 6
1.1.5 Hardware Design ................................................................................................... 7
MSP-TS432PZ100 ........................................................................................................... 8
1.2.1 Introduction .......................................................................................................... 8
1.2.2 Key Features ........................................................................................................ 8
1.2.3 Kit Contents.......................................................................................................... 8
1.2.4 Configuration and Usage .......................................................................................... 8
1.2.5 Hardware Design .................................................................................................. 15
MSP-FET .................................................................................................................... 24
Revision History .......................................................................................................................... 25
2
Contents
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List of Figures
.........................................................................................
1-1.
MSP-FET-432ADPTR Schematic
1-2.
Board Configuration For External Target Power Supply................................................................ 9
7
1-3.
Board Configuration For Debugger-Supplied Target Power .......................................................... 11
1-4.
Board Configuration When Using Cortex-M Debug Probes With Target Power Supply Capability ............. 12
1-5.
Board Configuration for Debug Probe Does Not Supply Logic Level on Pin 19 ................................... 13
1-6.
Board Configuration for Debug Probe Does Supply Logic Level on Pin 19 ........................................ 14
1-7.
MSP-TS432PZ100 Rev 1.1 Target Socket Board, Schematic ....................................................... 15
1-8.
MSP-TS432PZ100 Rev 1.1 Target Socket Board, PCB .............................................................. 16
1-9.
MSP-TS432PZ100 Rev 1.3 Target Socket Board, Schematic ....................................................... 19
1-10.
MSP-TS432PZ100 Rev 1.3 Target Socket Board, PCB .............................................................. 20
List of Tables
1-1.
Matrix of S1 Switch Orientation Compared to ARM Connector Option ............................................... 6
1-2.
MSP-FET-432ADPTR Bill of Materials .................................................................................... 7
1-3.
Device Compatibility ......................................................................................................... 8
1-4.
Jumper Settings for External Target Power Supply ..................................................................... 9
1-5.
Jumper Settings to Use Onboard LDO .................................................................................. 10
1-6.
Jumpers for Debug Probe Does Not Supply Logic Level on Pin 19 ................................................. 10
1-7.
Jumpers for Debug Probe Does Supply Logic Level on Pin 19 ...................................................... 10
1-8.
Jumper Settings ............................................................................................................ 12
1-9.
Jumper Settings to Use LDO ............................................................................................. 13
1-10.
Jumper Settings for Debug Probe Does Not Supply Logic Level on Pin 19
13
1-11.
Jumper Settings for Debug Probe Does Supply Logic Level on Pin 19
14
1-12.
1-13.
1-14.
1-15.
.......................................
............................................
MSP-TS432PZ100 Rev 1.1 Important Board Components ...........................................................
MSP-TS432PZ100 Rev 1.1 Bill Of Materials ...........................................................................
MSP-TS432PZ100 Rev 1.3 Important Board Components ...........................................................
MSP-TS432PZ100 Rev 1.3 Bill Of Materials ...........................................................................
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List of Figures
16
17
21
22
3
Preface
SLAU571D – March 2015 – Revised June 2018
Read This First
About This Manual
This manual describes the hardware tools that support the Texas Instruments SimpleLink™ MSP432™
device family of ARM® Cortex®-M based microcontrollers.
How to Use This Manual
This manual describes the setup and operation of the hardware tools. It does not fully describe the
MSP432 microcontrollers or the development software systems. For details of these items, see the
appropriate TI documents listed in Important MSP432 Documents on the Web.
Important MSP432 Documents on the Web
The primary sources of MSP432 information are the device-specific data sheets and user's guides. The
MSP432 web site contains the most recent versions of these documents.
Documents that describe the Code Composer Studio™ tools (Code Composer Studio IDE, assembler, C
compiler, linker, and librarian) are available on the Code Composer Studio page. A Wiki page (FAQ) that
is specific to the Code Composer Studio tools is available at
processors.wiki.ti.com/index.php/Category:CCS. The TI E2E™ Community support forums provide
additional help.
Documentation for third-party tools, such as the IAR Embedded Workbench® for ARM IDE or the Segger
J-Link debug probe, can be found on the respective third-party website.
If You Need Assistance
Support for the MSP432 devices and the hardware development tools is provided by the Texas
Instruments Product Information Center (PIC). Contact information for the PIC can be found on the TI web
site. The TI E2E™ Community support forums for the MSP432 provide open interaction with peer
engineers, TI engineers, and other experts. Additional device-specific information can be found on the
MSP432 web site.
Trademarks
SimpleLink™ MSP432, SimpleLink, Code Composer Studio, TI E2E are trademarks of Texas Instruments.
ARM, Cortex are registered trademarks of ARM Limited.
IAR Embedded Workbench is a registered trademark of IAR Systems.
4
Read This First
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Chapter 1
SLAU571D – March 2015 – Revised June 2018
Hardware
This chapter contains information relating to the hardware tools and includes schematics, PCB pictorials,
and bills of materials. Other tools such as EVMs and LaunchPad development kits are described in
separate product-specific user's guides. Information about the TI XDS100 and XDS200 debug probes is
not included in this document and can be found at www.ti.com/tool/xds100 and www.ti.com/tool/xds200,
respectively.
Topic
1.1
1.2
1.3
...........................................................................................................................
Page
MSP-FET-432ADPTR ............................................................................................ 6
MSP-TS432PZ100 ................................................................................................. 8
MSP-FET ........................................................................................................... 24
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Hardware
5
MSP-FET-432ADPTR
1.1
www.ti.com
MSP-FET-432ADPTR
1.1.1 Introduction
The MSP-FET-432ADPTR is an adapter to convert the 14-pin JTAG connector to either standard ARM 10pin or ARM 20-pin connectors. This allows for use of the MSP-FET debug probe with MSP432 Cortex-M
devices.
1.1.2 Key Features
•
•
•
Use MSP-FET to debug MSP432 Cortex-M Devices
10-pin ARM support
20-pin ARM support
1.1.3 Kit Contents
•
1x MSP-FET-432ADPTR 14-pin JTAG to ARM adapter
1.1.4 Configuration and Usage
The MSP-FET-432ADPTR allows the use of the MSP-FET debug probe with the MSP432 Cortex-M family
of devices. Operation is straight-forward, with only one selection for how the power is sourced. This
selection is required because of the difference in the power source and sense behavior of the MSP-FET
and the ARM debug standard.
The MSP-FET debug probe has two power states:
1. VCC Output
• MSP-FET outputs a voltage to the target.
• Output voltage is configurable in the IDE.
• In VCC output state, the MSP-FET voltage sense functionality is not enabled.
2. VCC Sense
• MSP-FET senses an existing external voltage (not from the MSP-FET itself).
• The JTAG signals are level shifted accordingly to match this voltage.
• In VCC Sense state, the MSP-FET output voltage is not provided.
The Cortex-M debug standard works a bit differently. In this standard, the VCC Sense is always active, no
matter where the external voltage is coming from. Some debug probes, such as the IAR I-jet and Segger
J-Link have a voltage output, all while still sensing the VCC Sense.
Table 1-1. Matrix of S1 Switch Orientation Compared to ARM Connector Option
VCC Sense (S1 Left)
6
VCC Output (S1 Right)
ARM 20-pin connector
• External power is sensed through ARM pin 1
• External power needs to be connected to
debug target
• Power is provided by the MSP-FET through
ARM pin 19.
• Alternatively, power can be wired to the target
using connector J4.
• This output matches other ARM debug probes
like IAR i-Jet and SEGGER J-Link
• Note that the IAR i-Jet outputs 3.3 V, and
SEGGER J-Link outputs 5 V on this pin.
Ensure the target accounts for the specific
voltage output by MSP-FET.
ARM 10-pin connector
• External power is sensed through ARM pin 1
• External power needs to be connected to
debug target
• There is no pin to connect the power output
on the 10 pin connector
• Power output is provided on connector J4.
This can be wired to the target board.
Hardware
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MSP-FET-432ADPTR
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1.1.5 Hardware Design
Figure 1-1 shows the schematic of the MSP-FET-432ADPTR.
1
2
A
2
4
6
8
10
12
14
3
4
A
1
3
5
7
9
11
13
1
3
5
7
9
2
4
6
8
10
B
B
2
C
5
L1
1
L2
3
L3
4
L4
6
C1
C2
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
C
1
2
3
D
1
D
2
3
4
Copyright © 2016, Texas Instruments Incorporated
Figure 1-1. MSP-FET-432ADPTR Schematic
Table 1-2 lists the bill of materials for the MSP-FET-432ADPTR.
Table 1-2. MSP-FET-432ADPTR Bill of Materials
Qty
Reference
Manufacturer
Description
1
J1
Standard
Conn Header 14POS 0.100" TH,
RA, Gold, Digikey S9203-ND
1
J2
Samtec
CONN HEADER 10POS DUAL
VERT, Digikey FTSH-105-01-FD-K-ND
1
J3
Standard
1
J4
1
Part Number
Alternate
Part
Number
PCB Decal,
Package
Supplier
Digi-Key Number
2 x 7 0.100"
Digikey
S9203-ND
2 x 5 0.050"
Digikey
FTSH-105-01-F-D-K-ND
CONN HEADER LOW-PRO
20POS GOLD, Digikey
HRP20H-ND
2 x 10 0.100"
Digikey
HRP20H-ND
Standard
CONN HEADER .100 SINGL
STR 3POS, Digikey S1012E-03ND
1 x 3 0.100"
Digikey
S1012E-03-ND
S1
Standard
SW SLIDE DPDT 2POS,
Digikey 401-2001-ND
Digikey
401-2001-ND
1
MH1
Standard
Standoff Nylon 4-40 8mm/
0.375"
CM
1
MH2
Standard
Standoff Nylon 4-40 8mm/
0.375"
CM
FTSH-105-01F-D-K
M096V
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7
MSP-TS432PZ100
1.2
www.ti.com
MSP-TS432PZ100
1.2.1 Introduction
NOTE: This kit does not include MSP432 microcontroller samples. To sample the compatible
devices, visit the product page or select the related MCU after adding the tool to the TI Store
cart: MSP432P401R.
The MSP-TS432PZ100 is a stand-alone ZIF socket target board used to program and debug the MSP432
MCU in-system through the JTAG interface or the Serial Wire Debug (SWD 2-wire JTAG) protocol. Two
standard ARM Cortex-M debug connectors provide connectivity to a large number of debug probes from
Texas Instruments and third parties.
All device pins are readily accessible through dedicated headers, which makes the board the ideal center
of a prototype setup.
1.2.2 Key Features
•
•
•
•
ZIF socket for 100-pin QFP (PZ) packages
Access to all 100 device pins
LEDs and buttons
2 x Cortex-M JTAG connectors supporting all 10- or 20-pin compatible debug probes
1.2.3 Kit Contents
•
•
•
•
•
•
One READ ME FIRST document
One MSP-TS432PZ100 target socket board
One TI Terms and Conditions for Evaluation Modules
One 32.768-kHz crystal from Micro Crystal
Four SAM1029-25-ND 25-pin 100-mil through-hole male headers
Four SAM1213-25-ND 25-pin 100-mil through-hole female headers
1.2.4 Configuration and Usage
Table 1-3 lists the devices that are compatible with the MSP-TS432PZ100 target socket board.
Table 1-3. Device Compatibility
Board
MSP-TS432PZ100
8
Hardware
Socket Type
Supported Devices
100-pin QFP (PZ100)
MSP432P401RIPZ
MSP432P401MIPZ
MSP432P4111TPZ
MSP432P4111IPZ
MSP432P411YTPZ
MSP432P411YIPZ
MSP432P411VTPZ
MSP432P411VIPZ
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MSP-TS432PZ100
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1.2.4.1
MSP-TS432PZ100 Rev 1.1
1.2.4.1.1 Board Configuration For External Target Power Supply
If the application needs to operate in stand-alone mode (for example, to measure current consumption
without debug overhead) or when using ARM Cortex-M debug probes that do not provide power for the
target device (for example, TI XDS100, XDS200, Keil ULINK2, or Keil ULINK Pro), power must be
supplied externally to the target socket board.
Always follow the voltage limits defined in the device data sheet. Set the jumpers according to Table 1-4
before connecting the debug probe and power supply (see Figure 1-2).
Table 1-4. Jumper Settings for External Target Power Supply
Jumper
State
J1
Close 2-3
Description
Connect EXTERNAL VCC to board VCC
Connect external VCC to J2-1, and external GND to J2-2 or J2-3, per the labelling on the PCB
silkscreen.
J2
JP1
Closed
Current-measurement header (closed unless measuring ICC)
JP2
Closed
Current-measurement header (closed unless measuring IDVCC)
JP16
Closed
Current-measurement header (closed unless measuring IAVCC)
JP8
Open
Disconnect Pin 19 from LDO input
JP12
Open
Disconnect LDO output from internal VCC (INTVCC)
JP15
Open
Do not short LDO input to output
Feed external
VCC here
Feed external
GND here
Figure 1-2. Board Configuration For External Target Power Supply
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1.2.4.1.2 Board Configuration When Using ARM Cortex-M Debug Probes With Target Power Supply
Capability
Some third-party ARM Cortex-M debuggers (for example, Segger J-Link and IAR i-Jet) can optionally
supply a 5-V voltage to the target system through pin 19 of the debug connector. The LDO IC2 uses this
voltage to generate the 3.3-V target supply voltage. To use the LDO, set the jumpers according to
Table 1-5 before connecting the debug probe (see Figure 1-3).
Table 1-5. Jumper Settings to Use Onboard LDO
Jumper
State
J1
Close 1-2
Description
JP1
Closed
Current-measurement header (closed unless measuring ICC)
JP2
Closed
Current-measurement header (closed unless measuring IDVCC)
JP16
Closed
Current-measurement header (closed unless measuring IAVCC)
Connect Internal VCC (INTVCC) to board VCC
If the debug probe does not supply a logic level through pin 19 on the 20-pin connector, follow the jumper
setting in Table 1-5.
Table 1-6. Jumpers for Debug Probe Does Not Supply Logic Level on Pin 19
Jumper
State
Description
JP8
Closed
Connect pin 19 to LDO input
JP12
Closed
Connect LDO output to the internal VCC (INTVCC)
JP15
Open
Do not short LDO input to output
If the debug probe does supply a logic level through pin 19 on the 20-pin connector, follow the jumper
settings in Table 1-7.
Table 1-7. Jumpers for Debug Probe Does Supply Logic Level on Pin 19
10
Jumper
State
JP8
Open
Disconnect pin 19 from LDO input
JP12
Open
Disconnect LDO output from internal VCC (INTVCC)
JP15
Closed
Hardware
Description
Bypasses the LDO by connecting pin 19 directly to onboard VCC (INTVCC)
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Figure 1-3. Board Configuration For Debugger-Supplied Target Power
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MSP-TS432PZ100
1.2.4.2
www.ti.com
MSP-TS432PZ100 Rev 1.3 and Newer
1.2.4.2.1 Board Configuration For External Target Power Supply
If the applications needs to operate in stand-alone mode (for example, to measure current consumption
without debug overhead) or when using ARM Cortex-M debug probes that do not provide power for the
target device (for example, TI XDS100, XDS200, Keil ULINK2, or Keil ULINK Pro), power must be
supplied externally to the target socket board.
Always follow the voltage limits defined in the device data sheet. Set the jumpers according to Table 1-8
before connecting the debug probe and power supply (see Figure 1-4).
Table 1-8. Jumper Settings
Jumper
State
Description
Connect external VCC to J2-1, and external GND to J2-2 or J2-3, per the labelling on the PCB
silkscreen.
NOTE: Some V1.3 boards have incorrect silkscreen labeling. Make sure to follow the figures
shown in this user's guide.
J2
JP1
Closed
Current-measurement header (closed unless measuring ICC)
JP2
Closed
Current-measurement header (closed unless measuring IDVCC)
JP3
Closed
Current-measurement header (closed unless measuring IAVCC)
JP6
Open
Disconnects input of LDO to allow VCC to be driven externally
Figure 1-4. Board Configuration When Using Cortex-M Debug Probes With Target Power Supply
Capability
12
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Some third-party ARM Cortex-M debuggers (for example, Segger J-Link and IAR i-Jet) can optionally
supply a 5-V voltage to the target system through pin 19 of the debug connector. The LDO IC2 uses this
voltage to generate the 3.3-V target supply voltage. To use the LDO, set the jumpers according to
Table 1-9 before connecting the debug probe (see Figure 1-5 or Figure 1-6):
Table 1-9. Jumper Settings to Use LDO
Jumper
State
JP1
Closed
Current-measurement header (closed unless measuring ICC)
Description
JP2
Closed
Current-measurement header (closed unless measuring IDVCC)
JP3
Closed
Current-measurement header (closed unless measuring IAVCC)
If the debug probe does not supply a logic level through pin 19 on the 20-pin connector, also close pins
1‑2 on JP6 (see Figure 1-5):
Table 1-10. Jumper Settings for Debug Probe Does Not Supply Logic Level on Pin 19
Jumper
State
JP6
Close 1-2
Description
Connect board VCC to LDO output
Figure 1-5. Board Configuration for Debug Probe Does Not Supply Logic Level on Pin 19
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MSP-TS432PZ100
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If the debug probe does supply a logic level through pin 19 on the 20-pin connector, also close pins 2-3 on
JP6 (see Figure 1-6):
Table 1-11. Jumper Settings for Debug Probe Does Supply Logic Level on Pin 19
Jumper
State
JP6
Close 2-3
Description
Connect board VCC to pin 19, bypassing LDO
Figure 1-6. Board Configuration for Debug Probe Does Supply Logic Level on Pin 19
14
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MSP-TS432PZ100 Rev 1.1
1.2.5.1
MSP-TS432PZ100
www.ti.com
1.2.5 Hardware Design
Figure 1-7 shows the MSP-TS432PZ100 Rev 1.1 schematic.
3
2
1
19
17
15
13
11
9
7
5
3
1
RSTN/NMI
TDO
27R SWCLKTCK
27R SWDIOTMS
27R TDI
C
JP8
R23
D
VUSB
GND
C15
1uF
1
3
IN
JP15
OUT
5
IC2 TLV70033DDC
EN
GND
E
GND
C16
1uF
JP12
INTVCC
INTVCC
DNP
DNP
F
DNP
10
27R 8
6
27R 4
27R 2
JB
9
7
5
3
1
J5
G
VCC
DVSS
DVCC
AVSS
HFGND
connection by via
GND
FTSH-105-01-F-D-K
22pF
C9
22pF
C8
DVCC
DVSS
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
FE25-1A3
Socket:
Yamaichi IC357-1004-053N
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DNP
RSTN/NMI
R22
TDI
TDO
SWCLKTCK R20
SWDIOTMS R21
2
DVSS 1 JP7
DNP
AVSS
GND
C6
1
2
3
DNP
R7
H
P1.5
BSL.10
0R
R15
RSTN/NMI
JP3A JP4A
JP3B
JP2X2
R10
4k7
1BJP14B
2B
P1.4
P3.7
P1.6
P1.2
P1.3
P3.6
P1.7
10
8
6
4
2
BSL
VCC
100nF
9
7
5
3
1
VCC
J2
EXTVCC
Ext_PWR
BSL.9
BSLRX
BSLTX
C7
GND
1uF/10V
VCC
P3.6
P3.7
J7
File: MSP-TS432PZ100
Date: 3/3/2015 3:32:52 PM
G
H
JP4B
JP5A
JP5B
JP6A
JP6B
BSLTX
BSLRX
BSL.9
I
I
Page 1/1
BSL.10
JP2X2
R11
4k7
1AJP14A
2A
Rev.: 1.1
Target Socket Board for MSP432P401xIPZ device
Title: MSP-TS432PZ100
C1
Q1
LFGND
DNP
QUARZ5 connection by via
DNP
C2
3
2
1
B
R17
R18
R19
TDO
TDI
SWDIOTMS
SWCLKTCK
RSTN/NMI
27R
TDO
RSTN/NMI
HFXIN
HFXOUT
Q3
P9.3/TA3.4
P9.2/TA3.3
DVCC2
DVSS2
P5.7/TA2.2/VREF-/VEREF-/C1.6
P5.6/TA2.1/VREF+/VEREF+/C1.7
P5.5/A0
P5.4/A1
P5.3/A2
P5.2/A3
P5.1/A4
P5.0/A5
P4.7/A6
P4.6/A7
P4.5/A8
P4.4/HSMCLK/SVMHOUT/A9
P4.3/MCLK/RTCCLK/A10
P4.2/ACLK/TA2CLK/A11
P4.1/A12
P4.0/A13
P6.1/A14
P6.0/A15
P9.1/A16
P9.0/A17
P8.7/A18
LFXOUT
LFXIN
DNP
F
GND
JA
ML20
EVQ11
GND
DCOR
91kOhm, 0.1%, 25ppm/C
R16
GND
QUARZ5
Q2
A
20
18
16
14
12
10
8
6
4
2
EXTVCC
VCC
INTVCC
SW1
C5
1.1nF
IC1
2
1
P10.1/UCB3CLK
P10.2/UCB3SIMO/UCB3SDA
P10.3/UCB3SOMI/UCB3SCL
P1.0/UCA0STE
P1.1/UCA0CLK
P1.2/UCA0RXD/UCA0SOMI
P1.3/UCA0TXD/UCA0SIMO
P1.4/UCB0STE
P1.5/UCB0CLK
P1.6/UCB0SIMO/UCB0SDA
P1.7/UCB0SOMI/UCB0SCL
VCORE
DVCC1
VSW
DVSS1
P2.0/PM_UCA1STE
P2.1/PM_UCA1CLK
P2.2/PM_UCA1RXD/PM_UCA1SOMI
P2.3/PM_UCA1TXD/PM_UCA1SIMO
P2.4/PM_TA0.1
P2.5/PM_TA0.2
P2.6/PM_TA0.3
P2.7/PM_TA0.4
P10.4/TA3.0/C0.7
P10.5/TA3.1/C0.6
AVCC
AVSS
E
A3
6
5
4
3
2
1
Copyright © 2015–2018, Texas Instruments Incorporated
6
J1
R4
47k
P1.3
P1.0
P1.1
P1.2
P1.4
P1.5
P1.6
P1.7
VCORE
DVCC
VSW
DVSS
P2.0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
MSP432P401RIPZ
D
KX-7
15
Hardware
SLAU571D – March 2015 – Revised June 2018
Submit Documentation Feedback
Vcc
ext
int
2
1
JP1
DVCC
AVCC
C4
100nF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
FE25-1A1
J3
P1.1
P2.0
P6.7
EVQ-11L05R
P1.0
C
UART
2
1
2
1
JP2
JP16
C3
10uF/10V
L1
VSW
4.7uH
LQM2MPN4R7NG0
VCORE
DVSS
DVCC
DVSS
AVSS
AVSS
DVSS
R14DNP
R3 DNP
JP11
JP10
B
I2C
5
4
AVSS
0R R12
0R R13
D3 red
DNP
R2 DNP
R1 330R
D2 yellow
DNP
JP9
SPI
1A
2A
1B
2B
1A
2A
1B
2B
1A
2A
1B
2B
1A
2A
1B
2B
3
1
R8
0R
R9
0R
R6 R5
0R 0R
1
2
GND
2
2
1
FE25-1A4
J4
3
2
1
D1
green
A
GND
DVCC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
C14
C11
100
99
98
97
96
95 SWCLKTCK
94 SWDIOTMS
93
92 TDI
91
90
89
88
87 AVCC
86
85
84 AVSS
83 RSTN/NMI
82
81 P6.7
80
79
78
77
76
P10.0/UCB3STE
P7.4/PM_TA1.4/C0.5
P9.7/UCA3TXD/UCA3SIMO
P7.5/PM_TA1.3/C0.4
P9.6/UCA3RXD/UCA3SOMI
P7.6/PM_TA1.2/C0.3
P9.5/UCA3CLK
P7.7/PM_TA1.1/C0.2
P9.4/UCA3STE
P8.0/UCB3STE/TA1.0/C0.1
SWCLKTCK
P8.1/UCB3CLK/TA2.0/C0.0
SWDIOTMS
P3.0/PM_UCA2STE
PJ.5/TDO/SWO
P3.1/PM_UCA2CLK
PJ.4/TDI/ADC14CLK
P3.2/PM_UCA2RXD/PM_UCA2SOMI
P7.3/PM_TA0.0
P3.3/PM_UCA2TXD/PM_UCA2SIMO
P7.2/PM_C1OUT/PM_TA1CLK
P3.4/PM_UCB2STE
P7.1/PM_C0OUT/PM_TA0CLK
P3.5/PM_UCB2CLK
P7.0/PM_SMCLK/PM_DMAE0
P3.6/PM_UCB2SIMO/PM_UCB2SDA
AVCC2
P3.7/PM_UCB2SOMI/PM_UCB2SCL
PJ.3/HFXIN
AVSS3
PJ.2/HFXOUT
PJ.0/LFXIN
AVSS2
PJ.1/LFXOUT
RSTN/NMI
AVSS1
NC
DCOR
P6.7/TA2.4/UCB3SOMI/UCB3SCL/C1.0
AVCC1
P6.6/TA2.3/UCB3SIMO/UCB3SDA/C1.1
P8.2/TA3.2/A23
P6.5/UCB1SOMI/UCB1SCL/C1.2
P8.3/TA3CLK/A22
P6.4/UCB1SIMO/UCB1SDA/C1.3
P8.4/A21
P6.3/UCB1CLK/C1.4
P8.5/A20
P6.2/UCB1STE/C1.5
P8.6/A19
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
26
27
28
29
30
31
32
33
34
35
36
37
38 P3.6
39 P3.7
40 AVSS
41
42
43 AVSS
44 DCOR
45 AVCC
46
47
48
49
50
C13
100nF
C10
J6
FE25-1A2
1uF/10V
2
1
2
1
2
1
100nF
SW2
C12
4u7
100nF
TP1TP2
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 1-7. MSP-TS432PZ100 Rev 1.1 Target Socket Board, Schematic
MSP-TS432PZ100
www.ti.com
Figure 1-8 shows the MSP-TS432PZ100 Rev 1.1 assembly drawing.
UART
I2C
SPI
R4
75
C3
C4
Q2
MSP-TS432PZ100
Rev. 1.1 RoHS
70
5
R23
65
C12
C13
C11
Klebpkt
C10
IC1
60
10
15
D1 R1
C5
SW1
R9
C8
Q3
JP6
JP5
C9
R8
1
J3
1
D2 R2
J6 76
L1
P1.0
20
55
C14
Q1
SW2
R11
25
R6
C2
R14
26 J4
30
35
40
TP1
R10 JP14
GND
R16
51 J5
P6.7
C1
R5
P1.1
80
C7 C6
VCC
GND
GND
D3 R3
R7
R15
85
R13 RESET
1
J7
JP11JP10 JP9
P1.2
JP4
JP7
90
JP1
DVCC
JP2
JP16
AVCC
JP3
BSL
R12
C15
R18
95
1
2
JA
R19
R17
IC2
C16
Ext. Pwr.
JP15
Vcc
JP12
GND
GND
J2
100
PWR J1
ext
Vcc
int
10
1
2
BSL
Selection
20
JP8
JB
R20
R21
TP2
GND
1
2
R22
9
10
45
50
Figure 1-8. MSP-TS432PZ100 Rev 1.1 Target Socket Board, PCB
Table 1-12 lists the key components of the MSP-TS432PZ100 Rev 1.1 board.
Table 1-12. MSP-TS432PZ100 Rev 1.1 Important Board Components
Reference
16
Description
Comment
IC1
Socket for PZ100 package
J1
Selector between internal and external power supply.
J2
Header to feed external voltage to device. If used, connect a 2-wire
cable to J1-1, J1-2 (Vcc,Gnd).
J7
VCC header. Can be used to observe device VCC when supplied by
the debug probe or to feed in external power.
JA
20-pin Cortex-M debug connector
JB
10-pin Cortex-M debug connector
JP1
Header to measure current flowing into AVCC and DVCC power
domains.
JP2
Header to disconnect DVCC from VCC supply. Connect an ammeter Jumper = Normal operation
to measure current flowing into the digital domain.
Open = Measure current from pin 2 to 1
Hardware
J1-J2 = Internal
J2-J3 = External
Jumper = Normal operation
Open = Measure current from pin 2 to 1
SLAU571D – March 2015 – Revised June 2018
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Copyright © 2015–2018, Texas Instruments Incorporated
MSP-TS432PZ100
www.ti.com
Table 1-12. MSP-TS432PZ100 Rev 1.1 Important Board Components (continued)
Reference
Description
JP8
Header to disconnect 3.3-V LDO voltage input from pin 19 of header
JA. Pin 19 of header JA is used by some third party ARM Cortex-M
debuggers (for example, Segger J-Link and IAR i-Jet) to supply a 5V voltage to the target system.
Comment
JP12
Header to disconnect 3.3-V LDO voltage output from INTVCC.
Remove this header if your debugger does not supply power to
avoid current draw by the unpowered LDO.
JP15
Header to bypass 3V3 LDO in case a debug probe supplies a logic
level voltage through pin 19 of header JA.
JP16
Header to disconnect AVCC from VCC supply. Connect an ammeter Jumper = Normal operation
to measure current flowing into the analog domain.
Open = Measure current from pin 2 to 1
1.2.5.1.1 Bill Of Materials
Table 1-13 lists the bill of materials for the MSP-TS432PZ100 Rev 1.1.
Table 1-13. MSP-TS432PZ100 Rev 1.1 Bill Of Materials
Pos.
Ref Des. No.
No. Per
Board
Description
Digi-Key Part No.
Comment
1
PCB
1
95.0 x 100.0 mm
"MSP-TS432PZ100" Rev.
1.1
2 layers, green solder mask
2
C1, C2
2
12pF, CSMD0805
1276-1120-1-ND
DNP
3
C8, C9
2
22pF, CSMD0805
490-3608-1-ND
4
C3
1
10uF/10V, CSMD0805
490-1709-2-ND
5
C4, C6, C10, C13,
C14
5
100nF, CSMD0805
490-1666-1-ND
6
C5
1
1.1nF, CSMD0805
490-1623-2-ND
7
C7, C11, C15, C16
4
1uF/10V, CSMD0805
490-1702-2-ND
8
C12
1
4u7, CSMD0805
445-1370-1-ND
9
D1
1
green LED, HSMG-C170,
DIODE0805
516-1434-1-ND
10
D2
1
yellow LED, DIODE0805
DNP
11
D3
1
red LED, DIODE0805
DNP
12
R1
1
330R, 0805
541-330ATR-ND
13
R2, R3,
2
330R, 0805
541-330ATR-ND
DNP
14
R5, R6, R7, R8, R9
5
0R, 0805
541-0.0ATR-ND
DNP
15
L1
1
4.7uH, 0806
490-4044-1-ND
Murata
16
R12, R13, R15
3
0R, 0805
541-0.0ATR-ND
17
R4
1
47k, 0805
541-47KATR-ND
18
R10, R11
2
4k7, 0805
541-4.7KATR-ND
19
R14
1
47k, 0805
541-47KATR-ND
P91KDACT-ND
DNP
20
R16
1
91kOhm, 0.1%, 25ppm/°C ,
0805
21
R17, R18, R19,
R20, R21, R22, R23
7
27R, 0805
541-27ATR-ND
22
JP1, JP2, JP9, JP7,
JP16
4
2-pin header, male, TH
SAM1035-02-ND
Place jumper on header
23
JP8, JP12, JP15
3
2-pin header, male, TH
SAM1035-02-ND
Not jumpered
24
JP10, JP11
2
2-pin header, male, TH
SAM1035-02-ND
DNP, keep pads free of
solder
25
J1
1
3-pin header, male, TH
SAM1035-03-ND
Place jumpers on pins 1-2
SLAU571D – March 2015 – Revised June 2018
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Copyright © 2015–2018, Texas Instruments Incorporated
Hardware
17
MSP-TS432PZ100
www.ti.com
Table 1-13. MSP-TS432PZ100 Rev 1.1 Bill Of Materials (continued)
18
Pos.
Ref Des. No.
No. Per
Board
26
JP3, JP4, JP5, JP6,
JP14
5
2x2-pin header, male, TH
SAM1034-02-ND
27
J2, J7
2
3-pin header, male, TH
SAM1035-03-ND
28
J3, J4, J5, J6
4
25-pin header, TH
SAM1029-25-ND
DNP: Headers are enclosed
in kit. Keep vias free of
solder.
29
J3, J4, J5, J6
4
25-pin receptacle, TH
SAM1213-25-ND
DNP: Receptacles are
enclosed in kit. Keep vias
free of solder.
30
JA
1
20-pin connector, male, TH
HRP20H-ND
31
JB
1
10-pin connector
FTSH-105-01-F-D-K
32
BSL
1
10-pin connector, male, TH
HRP10H-ND
Manuf. Yamaichi
Not enclosed in kit
Description
Digi-Key Part No.
Comment
Samtec: FTSH-105-01-F-DK
33
IC1
1
Socket: IC357-1004-053N,
LQFP100
34
IC1
2
MSP432P401RIPZ
35
Q1
1
MS3V-TR1 (32,768kHz/
20ppm/12,5pF)
depends on application
DNP, Micro Crystal,
enclosed in kit, keep vias
free of solder
36
Q2
1
DNP, Crystal
depends on application
DNP, keep vias free of
solder
37
Q3
1
KX-7T 48MHz 12pF
30/30/50ppm
38
SW2
1
EVQ-11L05R
P8079STB-ND
39
SW1
1
EVQ-11L05R
P8079STB-ND
40
IC2
1
TLV70033DDC, TSOT23-5
296-25276-2-ND
Hardware
Geyer Electronic - 12.88710
SLAU571D – March 2015 – Revised June 2018
Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
MSP-TS432PZ100 Rev 1.3
1.2.5.2
MSP-TS432PZ100
www.ti.com
Figure 1-9 shows the MSP-TS432PZ100 schematic.
A
B
C
D
GND
20
18
16
14
12
10
8
6
4
2
JA
5103309-5
VCC
SH-JP2
19
17
15
13
11
9
7
5
3
1
1
SH-JP3
JP1: 1-2 JP2: 1-2 JP3:1-2
SH-JP1
2
1
DVCC
DVCC R4
47k
C3
10µF
AVCC
R24
0
27
R18
0 R25
R17
27
BSLTX
BSLRX
R19
27
SW2
RSTn/NMI
TDO
SWCLKTCK
SWDIOTMS
TDI
EVQ-11L05R
C5
2
JP6
10
8
6
4
2
C15
1µF
GND
DCOR
R16
91.0k
R22
R20 27
R21 27
27
3
2
1
TSW-103-07-T-S
JP6: 2-3
SH-JP6
AVCC
2
JB
9
7
5
3
1
GND
IN
NC
OUT
GND
TLV70033DDCR
EN
IC2
FTSH-105-01-F-D-K
1
3
GND
J3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
5
4
VCC
C16
1µF
GND
TDO
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
VCORE
DVCC
VSW
DVSS
P2.0
TSW-125-07-G-S
3
VCC
R23
27
1
2
3
GND
VCC
J2
TSW-103-07-T-S
TDO_Dev
BSLCLK
BSLSDA
BSLSCL
J6
BSLSIMO
BSLSOMI
IC1
P10.1/UCB3CLK
1
P10.2/UCB3SIMO/UCB3SDA
2
P10.3/UCB3SOMI/UCB3SCL
3
P1.0/UCA0STE
4
P1.1/UCA0CLK
5
P1.2/UCA0RXD/UCA0SOMI
6
P1.3/UCA0TXD/UCA0SIMO
7
P1.4/UCB0STE
8
P1.5/UCB0CLK
9
P1.6/UCB0SIMO/UCB0SDA
10
P1.7/UCB0SOMI/UCB0SCL
11
VCORE
12
DVCC1
13
VSW
14
15
DVSS1
16
P2.0/PM_UCA1STE
17
P2.1/PM_UCA1CLK
P2.2/PM_UCA1RXD/PM_UCA1SOMI 18
P2.3/PM_UCA1TXD/PM_UCA1SIMO 19
P2.4/PM_TA0.1
20
P2.5/PM_TA0.2
21
P2.6/PM_TA0.3
22
23
P2.7/PM_TA0.4
24
P10.4/TA3.0/C0.7
25
P10.5/TA3.1/C0.6
3
BSLRX
BSLTX
GND
9
7
5
3
1
4
BSL
10
8
6
4
2
BSLSTE
VCC
RSTn/NMI
AWHW-10G-0202-T
TSW-125-07-G-S
4
AVSS
J4
TSW-125-07-G-S
Texas Instruments and/or its licensors do not warranturacy
the acc
or completeness of this specification or any tion
informa
contained therein.
Texas Instruments and/or its
sors
licen
do not
warrant that this design will meet the specifications,
be suitable
will
for your application or fit for any particular
rpose, pu
or will operate in an implementation. Texas Instrume
nts and/or its
licensors do not warrant that the design is production
y. You
worth
should completely validate and test your design
mentation
imple to confirm the system functionality for your
icatio
appl
C14
0.1µF
AVSS
Bypass
External (NC)
Use
DVSS
JP5: 1-2
1100pF
P1.1
RSTn/NMI
C4
0.1µF
AVSS
VSW
R14
DNP
P2.0
JP4: 1-2
SH-JP5
JP5
HMTSW-102-07-G-S-240
P1.0
JP4
SH-JP4
HMTSW-102-07-G-S-240
R15
0
R7
DNP
1
3
5
SW4
0
R3
2
4
HFXIN
TP3
TP4
P1.7
P1.6
P1.5
P1.4
P3.6
P3.7
P3.6
P3.7
J5
AVSS
LFGND
10
6
2 BSLSOMI
4 BSLSIMO
6 BSLCLK
8 BSLSTE
7
SPI BSL Connection
1
3
5
7
SW3
6
SW6
2
4
2 BSLSDA
4 BSLSCL
5
I2C BSL Connection
1
3
SW5
R10
1
3
I2C Pullups
4.7k
R11
4.7k
C9
AVSS
22pF connection by via
Q2
HFGND
MS3V-T1R
C8
22pF
VCC
TP7
TP8
TP9
TP10
TP5
TP6
C7
1µF
© Texas Instruments 2016
http://www.ti.com
C6
0.1µF
DVCC
DVSS
6
Sheet:1 of 2
Size: B
Mod. Date: 2/10/2017
connection by via
TSW-125-07-G-S
DVCC
DVSS
C2
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Q3
Q22FA2380185214
48MHz
BSLTX
BSLRX
HFXOUT
DVSS
4
3
UART BSL Connection
P1.3
P1.2
DVSS3
HFXOUT_extR8
DNP
HFXIN_ext R9
DNP
LFXIN
DNP
Designed for:Public Release
Project Title: MSP-TS432PZ100
Sheet Title:
Assembly Variant:[No Variations]
File: Schematic.SchDoc
Contact: http://www.ti.com/support
LFXOUT
Q1 DNP
MS3V-T1R
C1
75 P9.3/TA3.4
74 P9.2/TA3.3
73 DVCC2
72 DVSS2
71 P5.7/TA2.2/VREF-/VeREF-/C1.6
70 P5.6/TA2.1/VREF+/VeREF+/C1.7
69 P5.5/A0
68 P5.4/A1
67 P5.3/A2
66 P5.2/A3
65 P5.1/A4
64 P5.0/A5
63 P4.7/A6
62 P4.6/A7
61 P4.5/A8
60 P4.4/HSMCLK/SVMHOUT/A9
59 P4.3/MCLK/RTCCLK/A10
58 P4.2/ACLK/TA2CLK/A11
57 P4.1/A12
56 P4.0/A13
55 P6.1/A14
54 P6.0/A15
53 P9.2/A16
52 P9.0/A17
51 P8.7/A18
LFXIN_ext R6
DNP
LFXOUT_extR5
DNP
5
Orderable: EVM_orderable
TID #:
N/A
Rev: 1.3
Number:
SVN Rev: Version control disabled
Drawn By:
Engineer: Mike Pridgen
A
B
C
D
Copyright © 2015–2018, Texas Instruments Incorporated
19
Hardware
SLAU571D – March 2015 – Revised June 2018
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JP1
2
1
HMTSW-102-07-G-S-240
JP2
HMTSW-102-07-G-S-240
JP3
2
1
L1
4.7µH
C12
4.7µF
DVSS
VCORE
C13
0.1µF
C11
1µF
DVSS
AVSS
330
R1
200
R2
EVQ-11L05R
SW1
AVSS
DVCC
C10
0.1µF
1
2
R12
0
Green
D1
Blue
D2
GND
HMTSW-102-07-G-S-240
TP2
R13
0
TP1
DVSS 1
2
1
101
EP
2
25
24
23
22
21
SWCLKTCK 20
SWDIOTMS 19
TDO_Dev 18
TDI
17
16
15
14
13
12
AVCC
HFXIN_ext 11
HFXOUT_ext10
AVSS
9
8
RSTn/NMI
7
6
P6.7
5
4
3
2
1
100P10.0/UCB3STe
99 P9.7/UCA3TXD/UCA3SIMO
98 P9.6/UCA3RXD/UCA3SOMI
97 P9.5/UCA3CLK
96 P9.4/UCA3STE
95 SWCLKTCK
94 SWDIOTMS
93 PJ.5/TDO/SWO
92 PJ.4/TDI/ADC14CLK
91 P7.3/PM_TA0.0
90 P7.2/PM_C1OUT/PM_TA1CLK
89 P7.1/PM_COUT/PM_TA0CLK
88 P7.0/PM_SMCLK/PM_DMAE0
87 AVCC2
86 HFXIN
85 HFXOUT
84 AVSS
83 RSTn/NMI
82 DVSS3
81 P6.7/TA2.4/UCB3SOMI/UCB3SCL/C1.0
80 P6.6/TA2.3/UCB3SIMO/UCB3SDA/C1.1
79 P6.5/UCB1SOMI/UCB1SCL/C1.2
78 P6.4/UCB1SIMO/UCB1SDA/C1.3
77 P6.3/UCB1CLK/C1.4
76 P6.2/UCB1STE/C1.5
P7.4/PM_TA1.5/C0.5
26
27
P7.5/PM_TA1.3/C0.4
28
P7.6/PM_TA1.2/C0.3
29
P7.7/PM_TA1.1/C0.2
P8.0/UCB3STE/TA1.0/C0.1
30
31
P8.1/UCB3CLK/TA2.0/C0.0
PM3.0/PM_UCA2STE
32
P3.1/PM_UCA2CLK
33
P3.2/PM_UCA2RXD/PM_UCA2SOMI 34
P3.3/PM_UCA2TXD/PM_UCA2SIMO 35
36
P3.4/PM_UCB2STE
37
P3.5/PM_UCB2CLK
P3.6/PM_UCB2SIMO/PM_UCB2SDA 38
P3.6
P3.7/PM_UCB2SOMI/PM_UCB2SCL 39
P3.7
AVSS3
AVSS
40
LFXIN_ext
LFXIN
PJ.0/LFXIN
41
LFXOUT_ext LFXOUT
PJ.1/LFXOUT
42
AVSS1
43
AVSS
44
DCOR
DCOR
AVCC1
45
AVCC
P8.2/TA3.2/A23
46
47
P8.3/TA3CLK/A22
48
P8.4/A21
P8.5/A20
49
P8.6/A19
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
DVCC
2
1
2
1
Figure 1-9. MSP-TS432PZ100 Rev 1.3 Target Socket Board, Schematic
MSP-TS432PZ100
www.ti.com
Figure 1-10 shows the MSP-TS432PZ100 assembly drawing.
Figure 1-10. MSP-TS432PZ100 Rev 1.3 Target Socket Board, PCB
20
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MSP-TS432PZ100
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Table 1-14 lists the key components of the MSP-TS432PZ100 Rev 1.3 board.
Table 1-14. MSP-TS432PZ100 Rev 1.3 Important Board Components
Reference
Description
Comment
IC1
Socket for PZ100 package
J2
Header to feed external voltage to device. If used, connect a
2-wire cable to J1-1, J1-2 (VCC, GND).
JA
20-pin Cortex-M debug connector
JB
10-pin Cortex-M debug connector
JP1
Header to measure current flowing into AVCC and DVCC
power domains.
Jumper = normal operation
Open = measure current from pin 2 to 1
JP2
Header to disconnect DVCC from VCC supply. Connect an
ammeter to measure current flowing into the digital domain.
Jumper = normal operation
Open = measure current from pin 2 to 1
JP3
Header to disconnect AVCC from VCC supply. Connect an
ammeter to measure current flowing into the analog domain.
Jumper = normal operation
Open = measure current from pin 2 to 1
JP6
Header to select how VCC is supplied to the target.
No Jumper = externally sourced VCC
Jumper pins 1-2 = VCC sourced from JTAG directly
Jumper pins 2-3 = VCC sourced from LDO output
SW3
Switch to connect SPI BSL connections between target
device and BSL header
Switch ON to enable, SW4 and SW5 should be OFF
SW4
Switch to connect UART BSL connections between target
device and BSL header
Switch ON to enable, SW3 and SW5 should be OFF
SW5
Switch to connect I2C BSL connections between target
device and BSL header
Switch ON to enable, SW3 and SW4 should be OFF
SW6
Switch to connect 4.7kOhm pullup resistors to target device
pins 38 and 39, which are also the I2C BSL connections
Switch ON to connect pullup resistors
Switch OFF to disconnect pullup resistors
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MSP-TS432PZ100
www.ti.com
1.2.5.2.1 Bill Of Materials
Table 1-15 lists the bill of materials for the MSP-TS432PZ100 Rev 1.3.
Table 1-15. MSP-TS432PZ100 Rev 1.3 Bill Of Materials
Item
Quantity
Description
Supplier Part Number
!PCB1
1
PCB, 3.20" x 4.50"
2
BSL
1
Header (shrouded), 100mil, 5x2,
Gold, TH
A33159-ND
3
C1, C2
0
CAP, CERM, 12 pF, 50 V, +/- 5%,
C0G/NP0, 0805
311-1100-1-ND
4
C3
1
CAP, CERM, 10 µF, 10 V, +/- 10%,
X5R, 0805
490-1709-1-ND
5
C4, C6, C10,
C13, C14
5
CAP, CERM, 0.1 µF, 50 V, +/- 10%,
490-1666-1-ND
X7R, 0805
6
C5
1
CAP, CERM, 1100 pF, 50 V, +/5%, C0G/NP0, 0805
490-1623-1-ND
7
C7, C11,
C15, C16
4
CAP, CERM, 1 µF, 10 V, +/- 10%,
X5R, 0805
490-1702-1-ND
8
C8, C9
2
CAP, CERM, 22 pF, 50 V, +/- 5%,
C0G/NP0, 0805
490-3608-1-ND
9
C12
1
CAP, CERM, 4.7 µF, 10 V, +80/20%, Y5V, 0805
311-1371-2-ND
10
D1
1
LED, Green, SMD
754-1939-1-ND
11
D2
1
LED, Blue, SMD
732-4982-1-ND
12
H1, H2, H3,
H4
4
125mil Mounting Hole
13
IC1
1
MSP432P401RIPZ Socket
945-IC357-1004-053N
IC2
1
Single Output LDO, 200 mA, Fixed
3.3 V Output, 2 to 5.5 V Input, with
Low IQ, 5-pin SOT (DDC), -40 to
125 degC, Green (RoHS & no
Sb/Br)
296-27937-2-ND
15
J2, JP6
2
Header, 2.54 mm, 3x1, Tin, TH
SAM1035-03-ND
16
J3, J4, J5, J6
4
Header, 100mil, 25x1, Gold, TH
SAM1029-25-ND
JA
1
Header (shrouded), 100mil, 10x2,
Gold, TH
A33166-ND
18
JB
1
Header, 1.27 mm, 5x2, Gold, TH
FTSH-105-01-F-D-K-ND
19
JP1, JP2,
JP3, JP4,
JP5
5
Header, 100mil, 2x1, Gold, TH
HMTSW-102-07-G-S-240-ND
20
L1
1
Inductor, Wirewound, Ferrite, 4.7
µH, 0.3 A, 0.8 ohm, SMD
490-4044-1-ND
21
Q1, Q2
0
32.768KHz +/-20ppm 12.5pF
94M8466
22
Q3
1
SMD Crystal
FA-238 48.0000MB-W0-ND
23
R1
1
RES, 330, 5%, 0.125 W, 0805
541-330ACT-ND
24
R2
1
RES, 200, 5%, 0.125 W, 0805
541-200ACT-ND
25
R3, R12,
R13, R15,
R24, R25
6
RES, 0, 5%, 0.125 W, 0805
541-0.0ACT-ND
26
R4
1
RES, 47 k, 5%, 0.125 W, 0805
541-47KACT-ND
27
R5, R6, R7,
R8, R9
0
RES, 0, 5%, 0.125 W, 0805
541-0.0ACT-ND
28
R10, R11
2
RES, 4.7 k, 5%, 0.125 W, 0805
541-4.7KACT-ND
29
R14
0
RES, 47 k, 5%, 0.125 W, 0805
541-47KACT-ND
1
RES, 91.0 k, 0.1%, 0.125 W, AECQ200 Grade 0, 0805
P91KDACT-ND
17
30
Hardware
R16
Note
2 layers, green solder
mask
1
14
22
Designator
DNP
DNP
DNP
DNP
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Table 1-15. MSP-TS432PZ100 Rev 1.3 Bill Of Materials (continued)
1.2.5.3
Item
Designator
Quantity
31
R17, R18,
R19, R20,
R21, R22,
R23
Description
Supplier Part Number
7
RES, 27, 5%, 0.125 W, 0805
541-27ACT-ND
32
SH-JP1, SHJP2, SH-JP3,
SH-JP4, SHJP5, SH-JP6
6
Shunt, 100mil, Gold plated, Black
3M9580-ND
33
SW1, SW2
2
Switch Tactile SPST-NO 0.02A 15V
P8079STB-ND
34
SW3
1
Quad Pole Single Throw TH DIP
Switch
GH7198-ND
35
SW4, SW5,
SW6
3
Double Pole Single Throw TH DIP
Switch
GH7727-ND
36
TP1, TP2,
TP3, TP4,
TP5, TP6,
TP7, TP8,
TP9, TP10
0
Test Point, Miniature, Black, TH
36-5001-ND
Note
JP1: 1-2, JP2: 1-2,
JP3:1-2, JP4: 1-2,
JP5: 1-2, JP6: 2-3
DNP
MSP-TS432PZ100 Revision History
Revision
Date
Rev 1.1
March 2015
Rev 1.3
Comments
First released revision
September 2016 Changed LDO configuration jumpers. Replaced BSL selection jumpers with switches.
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MSP-FET
1.3
www.ti.com
MSP-FET
See the MSP Debuggers User’s Guide.
24
Hardware
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Revision History
www.ti.com
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from July 20, 2017 to June 8, 2018 ................................................................................................................... Page
•
•
•
•
•
•
•
•
•
Added note to description of jumper J2 in Table 1-8, Jumper Settings .......................................................... 12
Changed Figure 1-4, Board Configuration When Using Cortex-M Debug Probes With Target Power Supply Capability . 12
Changed "close pins 2-3 on JP6" to "close pins 1-2 on JP6" in the paragraph before Table 1-10, Jumper Settings for
Debug Probe Does Not Supply Logic Level on Pin 19 ............................................................................. 13
Changed the State column from "Close 2-3" to "Close 1-2" in Table 1-10, Jumper Settings for Debug Probe Does Not
Supply Logic Level on Pin 19 .......................................................................................................... 13
Changed Figure 1-5, Board Configuration for Debug Probe Does Not Supply Logic Level on Pin 19 ....................... 13
Changed "close pins 1-2 on JP6" to "close pins 2-3 on JP6" in the paragraph before Table 1-11, Jumper Settings for
Debug Probe Does Supply Logic Level on Pin 19 .................................................................................. 14
Changed the State column from "Close 1-2" to "Close 2-3" in Table 1-11, Jumper Settings for Debug Probe Does Supply
Logic Level on Pin 19 ................................................................................................................... 14
Changed Figure 1-6, Board Configuration for Debug Probe Does Supply Logic Level on Pin 19 ............................ 14
Changed Figure 1-10, MSP-TS432PZ100 Rev 1.3 Target Socket Board, PCB................................................. 20
SLAU571D – March 2015 – Revised June 2018
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Revision History
25
STANDARD TERMS FOR EVALUATION MODULES
1.
Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or
documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance
with the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
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clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,
or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2
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Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused by
neglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that have
been altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specifications
or instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality control
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User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10)
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2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or credit
User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warranty
period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair or
replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be
warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day
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3
Regulatory Notices:
3.1 United States
3.1.1
Notice applicable to EVMs not FCC-Approved:
FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software
associated with the kit to determine whether to incorporate such items in a finished product and software developers to write
software applications for use with the end product. This kit is not a finished product and when assembled may not be resold or
otherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the condition
that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference.
Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must
operate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter.
3.1.2
For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTION
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not
cause harmful interference, and (2) this device must accept any interference received, including interference that may cause
undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to
operate the equipment.
FCC Interference Statement for Class A EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is
operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to
correct the interference at his own expense.
FCC Interference Statement for Class B EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance
with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference
will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which
can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more
of the following measures:
•
•
•
•
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
Consult the dealer or an experienced radio/TV technician for help.
3.2 Canada
3.2.1
For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210 or RSS-247
Concerning EVMs Including Radio Transmitters:
This device complies with Industry Canada license-exempt RSSs. Operation is subject to the following two conditions:
(1) this device may not cause interference, and (2) this device must accept any interference, including interference that may
cause undesired operation of the device.
Concernant les EVMs avec appareils radio:
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation
est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit
accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concerning EVMs Including Detachable Antennas:
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)
gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type
and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for
successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types
listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.
Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited
for use with this device.
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et
d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage
radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope
rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le
présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le
manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne
non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de
l'émetteur
3.3 Japan
3.3.1
Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に
輸入される評価用キット、ボードについては、次のところをご覧ください。
http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page
3.3.2
Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified
by TI as conforming to Technical Regulations of Radio Law of Japan.
If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required to follow the
instructions set forth by Radio Law of Japan, which includes, but is not limited to, the instructions below with respect to EVMs
(which for the avoidance of doubt are stated strictly for convenience and should be verified by User):
1.
2.
3.
Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal
Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for
Enforcement of Radio Law of Japan,
Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to
EVMs, or
Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan
with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note
that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.
【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて
いないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの
措置を取っていただく必要がありますのでご注意ください。
1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用
いただく。
実験局の免許を取得後ご使用いただく。
技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ
ンスツルメンツ株式会社
東京都新宿区西新宿６丁目２４番１号
西新宿三井ビル
3.3.3
Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧ください。http:/
/www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
3.4 European Union
3.4.1
For EVMs subject to EU Directive 2014/30/EU (Electromagnetic Compatibility Directive):
This is a class A product intended for use in environments other than domestic environments that are connected to a
low-voltage power-supply network that supplies buildings used for domestic purposes. In a domestic environment this
product may cause radio interference in which case the user may be required to take adequate measures.
4
EVM Use Restrictions and Warnings:
4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT
LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.
4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling
or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety information
related to, for example, temperatures and voltages.
4.3 Safety-Related Warnings and Restrictions:
4.3.1
User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user
guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable and
customary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to input
and output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, or
property damage. If there are questions concerning performance ratings and specifications, User should contact a TI
field representative prior to connecting interface electronics including input power and intended loads. Any loads applied
outside of the specified output range may also result in unintended and/or inaccurate operation and/or possible
permanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting any
load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.
During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuit
components may have elevated case temperatures. These components include but are not limited to linear regulators,
switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using the
information in the associated documentation. When working with the EVM, please be aware that the EVM may become
very warm.
4.3.2
EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with the
dangers and application risks associated with handling electrical mechanical components, systems, and subsystems.
User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,
affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronic
and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely
limit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility and
liability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors or
designees.
4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal,
state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes all
responsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility and
liability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and local
requirements.
5.
Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurate
as possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites as
accurate, complete, reliable, current, or error-free.
6.
Disclaimers:
6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY MATERIALS PROVIDED WITH THE EVM (INCLUDING, BUT NOT
LIMITED TO, REFERENCE DESIGNS AND THE DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL
FAULTS." TI DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT
NOT LIMITED TO ANY EPIDEMIC FAILURE WARRANTY OR IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS
FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADE
SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.
6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS SHALL BE
CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY OTHER INDUSTRIAL OR
INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD PARTY, TO USE THE
EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY INVENTION, DISCOVERY OR
IMPROVEMENT, REGARDLESS OF WHEN MADE, CONCEIVED OR ACQUIRED.
7.
USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS
LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,
EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY
HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS. THIS OBLIGATION SHALL APPLY
WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY OTHER LEGAL
THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.
8.
Limitations on Damages and Liability:
8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,
INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE
TERMS OR THE USE OF THE EVMS , REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL OR
REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, RETESTING,
OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, LOSS OF
USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL BE BROUGHT AGAINST TI
MORE THAN TWELVE (12) MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HAS
OCCURRED.
8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY USE OF AN EVM PROVIDED
HEREUNDER, INCLUDING FROM ANY WARRANTY, INDEMITY OR OTHER OBLIGATION ARISING OUT OF OR IN
CONNECTION WITH THESE TERMS, , EXCEED THE TOTAL AMOUNT PAID TO TI BY USER FOR THE PARTICULAR
EVM(S) AT ISSUE DURING THE PRIOR TWELVE (12) MONTHS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE
CLAIMED. THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT.
9.
Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)
will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in
a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable
order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),
excluding any postage or packaging costs.
10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,
without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to
these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.
Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief
in any United States or foreign court.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated
IMPORTANT NOTICE FOR TI DESIGN INFORMATION AND RESOURCES
Texas Instruments Incorporated (‘TI”) technical, application or other design advice, services or information, including, but not limited to,
reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are
developing applications that incorporate TI products; by downloading, accessing or using any particular TI Resource in any way, you
(individually or, if you are acting on behalf of a company, your company) agree to use it solely for this purpose and subject to the terms of
this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources.
You understand and agree that you remain responsible for using your independent analysis, evaluation and judgment in designing your
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(and of all TI products used in or for your applications) with all applicable regulations, laws and other applicable requirements. You
represent that, with respect to your applications, you have all the necessary expertise to create and implement safeguards that (1)
anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that
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You are authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include
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TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING TI RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
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TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY YOU AGAINST ANY CLAIM, INCLUDING BUT NOT
LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF
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POSSIBILITY OF SUCH DAMAGES.
You agree to fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of your noncompliance with the terms and provisions of this Notice.
This Notice applies to TI Resources. Additional terms apply to the use and purchase of certain types of materials, TI products and services.
These include; without limitation, TI’s standard terms for semiconductor products http://www.ti.com/sc/docs/stdterms.htm), evaluation
modules, and samples (http://www.ti.com/sc/docs/sampterms.htm).
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated
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