MSP-FET430U128

Product Folder Order Now Technical Documents Tools & Software Support & Community MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 MSP430F677x, MSP430F676x, MSP430F674x Polyphase Metering SoCs 1 Device Overview 1.1 Features 1 • Accuracy < 0.1% Over 2000:1 Dynamic Range for Phase Current • Meets or Exceeds ANSI C12.20 and IEC 62053 Standards • Support for Multiple Sensors Such as Current Transformers, Rogowski Coils, or Shunts • Power Measurement for up to Three Phases Plus Neutral • Dedicated Pulse Output Pins for Active and Reactive Energy for Calibration • Four-Quadrant Measurement per Phase or Cumulative • Exact Phase Angle Measurements • Digital Phase Correction for Current Transformers • Temperature Compensated Energy Measurements • 40-Hz to 70-Hz Line Frequency Range Using Single Calibration • Flexible Power Supply Options With Automatic Switching • Display Operates at Very Low Power During AC Mains Failure: 3 µA in LPM3 • LCD Driver With Contrast Control for up to 320 Segments • Password-Protected Real-Time Clock (RTC) With Crystal Offset Calibration and Temperature Compensation • Integrated Security Modules to Support AntiTamper and Encryption • Multiple Communication Interfaces for Smart Meter Implementations • High-Performance 25-MHz CPU With 32-Bit Multiplier 1.2 • • • Wide Input Supply Voltage Range: 3.6 V Down to 1.8 V • Ultra-Low Power Consumption During Energy Measurement – 2.9 mW at 10-MHz Operation (3 V) • Multiple Low-Power Modes – Standby Mode (LPM3): 2.1 µA at 3 V, Wake up in Less Than 5 µs – RTC Mode (LPM3.5): 0.34 µA at 3 V – Shutdown Mode (LPM4.5): 0.18 µA at 3 V • Up to 512KB of Single-Cycle Flash • Up to 32KB of RAM With Single-Cycle Access • Up to Seven Independent 24-Bit Sigma-Delta ADCs With Differential Inputs and Variable Gain • System 10-Bit 200-ksps ADC – Six Channels Plus Supply and Temperature Sensor Measurement • Integrated Hardware AES-128 Module for Encryption • Six Enhanced Communications Ports – Configurable Among Four UART, Six SPI, and Two I²C Interfaces • Four 16-Bit Timers With Nine Total Capture/Compare Registers • 128-Pin LQFP (PEU) Package With 90 I/O Pins • 100-Pin LQFP (PZ) Package With 62 I/O Pins • Industrial Temperature Range of –40°C to 85°C • 3-Phase Electronic Watt-Hour Meter Development Tool (Also See Tools and Software) – EVM430-F6779 With Application Note – Energy Measurement Design Center for MSP430™ MCUs Applications 3-Phase Electronic Watt-Hour Meters Utility Metering • Energy Monitoring 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 1.3 www.ti.com Description The TI MSP430F677x family of polyphase metering SoCs are powerful highly integrated solutions for revenue meters that offer accuracy and low system cost with few external components. The F677x family of devices uses the low-power MSP430 CPU with a 32-bit multiplier to perform all energy calculations, metering applications such as tariff rate management, and communications with AMR and AMI modules. The F677x devices feature TI's 24-bit sigma-delta converter technology, which provides better than 0.1% accuracy. Family members include up to 512KB of flash, 32KB of RAM, and an LCD controller with support for up to 320 segments. The ultra-low-power nature of the F677x devices means that the system power supply can be minimized to reduce overall cost. Lowest standby power means that backup energy storage can be minimized and critical data retained longer in case of a mains power failure. The F677x family of devices executes the TI energy measurement software library, which calculates all relevant energy and power results. The energy measurement software library is available with the F677x devices at no cost. Industry standard development tools and hardware platforms are available to speed development of meters that meet all of the ANSI and IEC standards globally. For complete module descriptions, see the MSP430F5xx and MSP430F6xx Family User's Guide. Device Information (1) PACKAGE BODY SIZE (2) MSP430F6779IPEU LQFP (128) 20 mm × 14 mm MSP430F6779IPZ LQFP (100) 14 mm × 14 mm PART NUMBER (1) (2) 2 For the most current device, package, and ordering information, see the Package Option Addendum in Section 8, or see the TI website at www.ti.com. The sizes shown here are approximations. For the package dimensions with tolerances, see the Mechanical Data in Section 8. Device Overview Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 www.ti.com 1.4 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 Application Diagram Figure 1-1 shows a typical application diagram. TOTAL kWh Load Sx, COMx Phase C VCC MSP430F677x Phase A R33 RST Phase B LCDCAP VSS Px.x Neutral + IA CT STATUS LEDs ΣΔ Modulator – + IB CT Px.y ΣΔ Modulator – PULSE LEDs + CT IC ΣΔ Modulator – XIN + Ineutral CT 32768 Hz ΣΔ Modulator – VA XOUT AFE + USCIA0 UART or SPI USCIA1 UART or SPI USCIA2 UART or SPI USCIA3 UART or SPI USCIB0 I2C or SPI USCIB1 I2C or SPI ΣΔ Modulator – VB + ΣΔ Modulator – VC + VN ΣΔ Modulator – Vref Neutral Phase B Phase A Phase C Source From Utility Figure 1-1. 3-Phase 4-Wire Star Connection Using MSP430F677x Device Overview Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 Copyright © 2012–2018, Texas Instruments Incorporated 3 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com Table of Contents 1 2 3 Device Overview ......................................... 1 5.31 Auxiliary Supplies, Switching Time.................. 43 1.1 Features .............................................. 1 5.32 Auxiliary Supplies, Switch Leakage ................. 43 1.2 Applications ........................................... 1 5.33 Auxiliary Supplies, Auxiliary Supplies to ADC10_A . 43 1.3 Description ............................................ 2 5.34 Auxiliary Supplies, Charge Limiting Resistor 1.4 Application Diagram .................................. 3 5.35 Timer_A Revision History ......................................... 6 Device Comparison ..................................... 7 5.36 Related Products ..................................... 8 5.38 Terminal Configuration and Functions .............. 9 5.39 4.1 Pin Diagrams ......................................... 9 5.40 4.2 3.1 4 5 5.37 Signal Descriptions .................................. 13 5.41 Specifications ........................................... 26 5.42 5.1 Absolute Maximum Ratings ......................... 26 5.43 5.2 ESD Ratings ........................................ Recommended Operating Conditions ............... 26 5.44 26 5.45 Active Mode Supply Current Into VCC Excluding External Current ..................................... 28 Low-Power Mode Supply Currents (Into VCC) Excluding External Current.......................... 29 Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current .................... 30 5.46 5.3 5.4 5.5 5.6 5.7 Thermal Packaging Characteristics ................. 31 5.8 Schmitt-Trigger Inputs – General-Purpose I/O...... 32 ........................... 5.47 5.48 44 44 44 45 45 46 48 49 49 49 49 50 51 SD24_B Power Supply and Recommended Operating Conditions ................................ 52 .............................. ........................... SD24_B Performance ............................... SD24_B, AC Performance .......................... SD24_B, AC Performance .......................... SD24_B, AC Performance .......................... SD24_B External Reference Input .................. SD24_B Analog Input 52 5.50 SD24_B Supply Currents 53 5.52 54 56 5.9 Inputs – Ports P1 and P2 5.10 5.11 Leakage Current – General-Purpose I/O ........... 32 Outputs – General-Purpose I/O (Full Drive Strength) ............................................ 33 Outputs – General-Purpose I/O (Reduced Drive Strength) ............................................ 33 5.53 Output Frequency – General-Purpose I/O .......... 33 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0) ............................... 34 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1) ............................... 35 5.57 10-Bit ADC Switching Characteristics............... 58 5.58 10-Bit ADC Linearity Parameters 5.59 10-Bit ADC External Reference ..................... 59 5.60 REF Built-In Reference 5.61 Comparator_B ....................................... 61 5.62 Flash Memory ....................................... 62 5.63 JTAG and Spy-Bi-Wire Interface .................... 62 5.12 5.13 5.14 5.15 5.16 5.17 5.18 Crystal Oscillator, XT1, Low-Frequency Mode ...... 36 Internal Very-Low-Power Low-Frequency Oscillator (VLO) ................................................ 37 Internal Reference, Low-Frequency Oscillator (REFO) .............................................. 37 5.54 5.55 5.56 6 56 56 57 10-Bit ADC Power Supply and Input Range Conditions ........................................... 58 ................... ............................. 59 60 Detailed Description ................................... 63 6.1 Functional Block Diagrams.......................... 63 5.19 DCO Frequency ..................................... 38 6.2 CPU (Link to User's Guide) ......................... 64 5.20 PMM, Brownout Reset (BOR)....................... 39 6.3 Instruction Set ....................................... 65 5.21 PMM, Core Voltage ................................. 39 6.4 Operating Modes .................................... 66 5.22 PMM, SVS High Side ............................... 40 6.5 Interrupt Vector Addresses.......................... 67 5.23 PMM, SVM High Side ............................... 40 6.6 Special Function Registers (SFRs) ................. 69 5.24 PMM, SVS Low Side ................................ 41 6.7 Memory Organization ............................... 70 5.25 5.26 PMM, SVM Low Side ............................... Wake-up Times From Low-Power Modes and Reset ................................................ Auxiliary Supplies Recommended Operating Conditions ........................................... Auxiliary Supplies, AUXVCC3 (Backup Subsystem) Currents ............................................. 6.8 Bootloader (BSL) .................................... 72 5.27 41 41 42 6.9 JTAG Operation ..................................... 72 6.10 Flash Memory (Link to User's Guide) ............... 73 6.11 RAM (Link to User's Guide) ......................... 73 6.12 Backup RAM (Link to User's Guide) ................ 73 42 6.13 Peripherals 5.29 Auxiliary Supplies, Auxiliary Supply Monitor ........ 42 6.14 Input/Output Diagrams ............................. 100 5.30 Auxiliary Supplies, Switch ON-Resistance .......... 43 6.15 Device Descriptors (TLV) .......................... 154 5.28 7 4 43 5.49 5.51 32 ....... ............................................. eUSCI (UART Mode) Clock Frequency ............. eUSCI (UART Mode)................................ eUSCI (SPI Master Mode) Clock Frequency ....... eUSCI (SPI Master Mode) .......................... eUSCI (SPI Slave Mode) ........................... eUSCI (I2C Mode) ................................... Schmitt-Trigger Inputs, RTC Tamper Detect Pin ... Inputs, RTC Tamper Detect Pin..................... Leakage Current, RTC Tamper Detect Pin ......... Outputs, RTC Tamper Detect Pin ................... LCD_C Recommended Operating Conditions ...... LCD_C Electrical Characteristics ................... Table of Contents .......................................... 74 Device and Documentation Support .............. 157 Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 www.ti.com SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 7.1 Getting Started and Next Steps 157 7.7 Trademarks ........................................ 163 7.2 Device Nomenclature .............................. 157 7.8 Electrostatic Discharge Caution 7.3 Tools and Software ................................ 159 7.9 Export Control Notice .............................. 164 7.4 Documentation Support ............................ 161 7.10 Glossary............................................ 164 7.5 Related Links 7.6 ................... ...................................... Community Resources............................. 163 163 8 ................... Mechanical, Packaging, and Orderable Information ............................................. 165 Table of Contents Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 Copyright © 2012–2018, Texas Instruments Incorporated 164 5 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 2 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from December 19, 2013 to September 28, 2018 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 6 Page Document format changes throughout, including addition of section numbering ............................................ 1 Updated links to development tool and design center in , Features ........................................................... 1 Added Device Information table .................................................................................................... 2 Added Section 3, Device Comparison, and moved Table 3-1 to it ............................................................. 7 Added Section 3.1, Related Products ............................................................................................. 8 Added Section 4 and moved pinouts and terminal functions tables to it ...................................................... 9 Corrected the port number (P4.2) on pin 61 in Figure 4-2, 100-Pin PZ Package (Top View) ............................ 11 Added note to P1.3/ADC10CLK/A3 (pin 8) in Table 4-3, Terminal Functions – PEU Package........................... 13 Added typical conditions statements at the beginning of Section 5, Specifications ........................................ 26 Moved all electrical specifications to Section 5.................................................................................. 26 Added SD24_B input pins and AUXVCCx pins to exception list on "Voltage applied to pins" parameter, and added SD24_B input pin limits in "Diode current at pins" parameter in Section 5.1, Absolute Maximum Ratings ..... 26 Added Section 5.2, ESD Ratings.................................................................................................. 26 Added note to CVCORE ............................................................................................................... 26 Added Section 5.7, Thermal Packaging Characteristics ...................................................................... 31 Changed the TYP value of the CL,eff parameter with Test Conditions of "XTS = 0, XCAPx = 0" from 2 pF to 1 pF in Section 5.16, Crystal Oscillator, XT1, Low-Frequency Mode............................................................... 36 Updated notes (1) and (2) and added note (3) in Section 5.26, Wake-up Times From Low-Power Modes and Reset ................................................................................................................................. 41 Corrected the names of the AUXVCC1, AUXVCC2, and AUXVCC3 pins in Auxiliary Supplies tables.................. 42 Corrected the bit name in the Test Conditions of the RCHARGE parameter (changed CHCx to AUXCHCx) in Section 5.34, Auxiliary Supplies, Charge Limiting Resistor.................................................................... 43 Replaced fFrame parameter with fLCD, fFRAME,4mux, and fFRAME,8mux parameters in Section 5.46, LCD_C Recommended Operating Conditions ............................................................................................ 50 On the VID,FS parameter in Section 5.48, SD24_B Power Supply and Recommended Operating Conditions: Changed the MIN value from "VREF/GAIN" to "–VREF/GAIN"; Removed "Unipolar mode" test condition (mode is not supported) ....................................................................................................................... 52 Removed ADC10DIV from the formula for the TYP value in the second row of the tCONVERT parameter in Section 5.57, 10-Bit ADC Switching Characteristics, because ADC10CLK is after division .............................. 58 Changed Test Conditions for all parameters in Section 5.58, 10-Bit ADC Linearity Parameters: Removed "VREF–"; Changed from "(VeREF+ – VeREF–)min ≤ (VeREF+ – VeREF–)" to "1.4 V ≤ (VeREF+ – VeREF–)"; Changed from "CVREF+ = 20 pF" to "CVeREF+ = 20 pF"; Added "CVeREF+ = 20 pF" to EI; Added "ADC10SREFx = 11b" to ET and EG .. 59 Removed "VREF–" from the Test Conditions for the VeREF+, VeREF–, and (VeREF+ – VeREF–) parameters in Section 5.59, 10-Bit ADC External Reference ................................................................................... 59 Changed MIN value of AVCC(min) parameter with Test Conditions of "REFVSEL = {0} for 1.5 V" from 2.2 V to 1.8 V in Section 5.60, REF Built-In Reference .................................................................................. 60 Changed the MAX value of the tEN_CMP parameter with Test Conditions of "CBPWRMD = 10" from 50 µs to 100 µs in Section 5.61, Comparator_B ........................................................................................... 61 Throughout document, changed all instances of "bootstrap loader" to "bootloader" ....................................... 72 Corrected spelling of NMIIFG in Table 6-13, System Module Interrupt Vector Registers ................................. 78 Added Section 7 and moved Development Tools Support, Device and Development Tool Nomenclature, and Trademarks sections to it ......................................................................................................... 157 Replaced former section Development Tools Support with Section 7.3, Tools and Software .......................... 159 Added Section 8, Mechanical, Packaging, and Orderable Information ..................................................... 165 Revision History Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 www.ti.com SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 3 Device Comparison Table 3-1 summarizes the available family members. Table 3-1. Device Comparison (1) (2) DEVICE FLASH (KB) SRAM (KB) SD24_B CONVERTERS ADC10_A CHANNELS Timer_A (3) eUSCI_A: UART, IrDA, SPI eUSCI_B: SPI, I2C I/Os PACKAGE MSP430F6779IPEU 512 32 7 6 ext, 2 int 3, 2, 2, 2 4 2 90 128 PEU MSP430F6778IPEU 512 16 7 6 ext, 2 int 3, 2, 2, 2 4 2 90 128 PEU MSP430F6777IPEU 256 32 7 6 ext, 2 int 3, 2, 2, 2 4 2 90 128 PEU MSP430F6776IPEU 256 16 7 6 ext, 2 int 3, 2, 2, 2 4 2 90 128 PEU MSP430F6775IPEU 128 16 7 6 ext, 2 int 3, 2, 2, 2 4 2 90 128 PEU MSP430F6769IPEU 512 32 6 6 ext, 2 int 3, 2, 2, 2 4 2 90 128 PEU MSP430F6768IPEU 512 16 6 6 ext, 2 int 3, 2, 2, 2 4 2 90 128 PEU MSP430F6767IPEU 256 32 6 6 ext, 2 int 3, 2, 2, 2 4 2 90 128 PEU MSP430F6766IPEU 256 16 6 6 ext, 2 int 3, 2, 2, 2 4 2 90 128 PEU MSP430F6765IPEU 128 16 6 6 ext, 2 int 3, 2, 2, 2 4 2 90 128 PEU MSP430F6749IPEU 512 32 4 6 ext, 2 int 3, 2, 2, 2 4 2 90 128 PEU MSP430F6748IPEU 512 16 4 6 ext, 2 int 3, 2, 2, 2 4 2 90 128 PEU MSP430F6747IPEU 256 32 4 6 ext, 2 int 3, 2, 2, 2 4 2 90 128 PEU MSP430F6746IPEU 256 16 4 6 ext, 2 int 3, 2, 2, 2 4 2 90 128 PEU MSP430F6745IPEU 128 16 4 6 ext, 2 int 3, 2, 2, 2 4 2 90 128 PEU MSP430F6779IPZ 512 32 7 6 ext, 2 int 3, 2, 2, 2 4 2 62 100 PZ MSP430F6778IPZ 512 16 7 6 ext, 2 int 3, 2, 2, 2 4 2 62 100 PZ MSP430F6777IPZ 256 32 7 6 ext, 2 int 3, 2, 2, 2 4 2 62 100 PZ MSP430F6776IPZ 256 16 7 6 ext, 2 int 3, 2, 2, 2 4 2 62 100 PZ MSP430F6775IPZ 128 16 7 6 ext, 2 int 3, 2, 2, 2 4 2 62 100 PZ MSP430F6769IPZ 512 32 6 6 ext, 2 int 3, 2, 2, 2 4 2 62 100 PZ MSP430F6768IPZ 512 16 6 6 ext, 2 int 3, 2, 2, 2 4 2 62 100 PZ MSP430F6767IPZ 256 32 6 6 ext, 2 int 3, 2, 2, 2 4 2 62 100 PZ MSP430F6766IPZ 256 16 6 6 ext, 2 int 3, 2, 2, 2 4 2 62 100 PZ MSP430F6765IPZ 128 16 6 6 ext, 2 int 3, 2, 2, 2 4 2 62 100 PZ MSP430F6749IPZ 512 32 4 6 ext, 2 int 3, 2, 2, 2 4 2 62 100 PZ MSP430F6748IPZ 512 16 4 6 ext, 2 int 3, 2, 2, 2 4 2 62 100 PZ MSP430F6747IPZ 256 32 4 6 ext, 2 int 3, 2, 2, 2 4 2 62 100 PZ MSP430F6746IPZ 256 16 4 6 ext, 2 int 3, 2, 2, 2 4 2 62 100 PZ MSP430F6745IPZ 128 16 4 6 ext, 2 int 3, 2, 2, 2 4 2 62 100 PZ (1) (2) (3) For the most current device, package, and ordering information, see the Package Option Addendum in Section 8, or see the TI website at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively. Device Comparison Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 Copyright © 2012–2018, Texas Instruments Incorporated 7 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 3.1 www.ti.com Related Products For information about other devices in this family of products or related products, see the following links. Products for TI Microcontrollers TI's low-power and high-performance MCUs, with wired and wireless connectivity options, are optimized for a broad range of applications. Products for MSP430 Ultra-Low-Power Microcontrollers One platform. One ecosystem. Endless possibilities. Enabling the connected world with innovations in ultra-low-power microcontrollers with advanced peripherals for precise sensing and measurement. Companion Products for MSP430F6779 Review products that are frequently purchased or used with this product. Reference Designs for MSP430F6779 The TI Designs Reference Design Library is a robust reference design library that spans analog, embedded processor, and connectivity. Created by TI experts to help you jump start your system design, all TI Designs include schematic or block diagrams, BOMs, and design files to speed your time to market. 8 Device Comparison Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 www.ti.com SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 4 Terminal Configuration and Functions 4.1 Pin Diagrams SD0N0 SD0P0 SD1P0 SD1N0 SD2N0 SD2P0 SD3P0 SD3N0 VASYS2 AVSS2 VREF SD4P0 SD4N0 SD5P0 SD5N0 SD6P0 SD6N0 AVSS1 AVCC VASYS1 AUXVCC2 AUXVCC1 93 P2.0/PM_TA0.0/BSL_TX P1.0/TA1.1/VeREF-/A0 11 92 P11.5/TACLK/RTCCLK P2.4/PM_TA2.0 12 91 P11.4/CBOUT P2.5/PM_UCB0SOMI/PM_UCB0SCL 13 90 P11.3/TA2.1 P2.6/PM_UCB0SIMO/PM_UCB0SDA 14 89 P11.2/TA1.1 P2.7/PM_UCB0CLK 15 88 P11.1/TA3.1/CB3 P3.0/PM_UCA0RXD/PM_UCA0SOMI 16 87 P11.0/S0 P3.1/PM_UCA0TXD/PM_UCA0SIMO 17 86 P10.7/S1 P3.2/PM_UCA0CLK 18 85 P10.6/S2 P3.3/PM_UCA1CLK 19 84 P10.5/S3 P3.4/PM_UCA1RXD/PM_UCA1SOMI 20 83 P10.4/S4 P3.5/PM_UCA1TXD/PM_UCA1SIMO 21 82 P10.3/S5 COM0 22 81 P10.2/S6 COM1 23 80 P10.1/S7 P1.6/COM2 24 79 P10.0/S8 P1.7/COM3 25 78 P9.7/S9 P5.0/COM4 26 77 P9.6/S10 P5.1/COM5 27 76 P9.5/S11 P5.2/COM6 28 75 P9.4/S12 P5.3/COM7 29 74 P9.3/S13 LCDCAP/R33 30 73 P9.2/S14 P5.4/SDCLK/R23 31 72 P9.1/S15 P5.5/SD0DIO/LCDREF/R13 32 71 P9.0/S16 P5.6/SD1DIO/R03 33 70 DVSS2 P5.7/SD2DIO/CB2 34 69 VDSYS2 P6.0/SD3DIO 35 68 P8.7/S17 P3.6/PM_UCA2RXD/PM_UCA2SOMI 36 67 P8.6/S18 P3.7/PM_UCA2TXD/PM_UCA2SIMO 37 66 P8.5/S19 38 65 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 P8.4/S20 P8.3/S21 10 P8.2/S22 P2.1/PM_TA0.1/BSL_RX P1.1/TA2.1/VeREF+/A1 P8.1/S23 94 P8.0/S24 9 P7.7/S25 P2.2/PM_TA0.2 P1.2/ACLK/A2 P7.6/S26 95 P7.5/S27 8 P7.4/S28 P2.3/PM_TA1.0 P1.3/ADC10CLK/A3 P7.3/S29 96 P7.2/S30 7 P7.1/S31 TEST/SBWTCK P1.4/MCLK/CB1/A4 P7.0/S32 97 P6.7/S33 6 P6.6/S34 PJ.0/TDO P1.5/SMCLK/CB0/A5 P6.5/S35 98 P6.4/S36 5 P6.3/SD6DIO/S37 PJ.1/TDI/TCLK RTCCAP0 P6.2/SD5DIOS38 99 P6.1/SD4DIO/S39 4 P4.7/PM_TA3.0 PJ.2/TMS RTCCAP1 P4.6/PM_UCB1CLK 100 P4.1/PM_UCA3RXD/M_UCA3SOMI C. VDSYS1 3 P4.4/PM_UCB1SOMI/PM_UCB1SCL PJ.3/TCK AUXVCC3 P4.5/PM_UCB1SIMO/PM_UCB1SDA 101 P4.0/PM_UCA2CLK B. DVSS1 2 P4.3/PM_UCA3CLK RST/NMI/SBWTDIO XOUT P4.2/PM_UCA3TXD/PM_UCA3SIMO 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 1 102 XIN A. DVCC VCORE Figure 4-1 shows the pinout for the MSP430F677x devices in the 128-pin PEU package. Table 4-1 lists the differences among the pinouts for the MSP430F677x, MSP430F676x, and MSP430F674x devices. The secondary digital functions on Ports P2, P3 and P4 are fully mappable. This pinout shows only the default mapping. See Table 6-11 for details. The pair of pins VDSYS1 and VDSYS2, VASYS1 and VASYS2 must be connected externally on the board for proper device operation. CAUTION: The LCDCAP/R33 pin must be connected to DVSS if it is not used. Figure 4-1. 128-Pin PEU Package (Top View) Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 Copyright © 2012–2018, Texas Instruments Incorporated 9 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com Table 4-1. Pinout Differences for MSP430F677xIPEU , MSP430F676xIPEU , and MSP430F674xIPEU 10 PIN NAME PIN NUMBER MSP430F677xIPEU MSP430F676xIPEU MSP430F674xIPEU 46 P6.1/SD4DIO/S39 P6.1/SD4DIO/S39 P6.1/S39 47 P6.2/SD5DIO/S38 P6.2/SD5DIO/S38 P6.2/S38 48 P6.3/SD6DIO/S37 P6.3/S37 P6.3/S37 113 VREF VREF VREF 114 SD4P0 SD4P0 NC 115 SD4N0 SD4N0 NC 116 SD5P0 SD5P0 NC 117 SD5N0 SD5NO NC 118 SD6P0 NC NC 119 SD6N0 NC NC Terminal Configuration and Functions Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 www.ti.com SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 C. DVSS2 P6.0/S16 P6.1/S15 P6.3/S13 P6.2/S14 P6.4/S12 P6.5/S11 P6.6/S10 P6.7/S9 P7.0/S8 P7.1/S7 P7.2/S6 P7.3/S5 P7.4/S4 P7.5/S3 P7.6/S2 P7.7/S1 P8.0/S0 P8.1/TACLK/RTCCLKCB3 TEST/SBWTCK PJ.0/TDO PJ.1TDI/TCLK 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 VDSYS2 SD0N0 2 74 P5.7/SD6DIO/S17 SD1P0 3 73 P5.6/SD5DIO/S18 SD1N0 4 72 P5.5/SD4DIO/S19 SD2P0 5 71 P5.4/SD3DIO/S20 SD2N0 6 70 P5.3/SD2DIO/S21 SD3P0 7 69 P5.2/SD1DIO/S22 SD3N0 8 68 P5.1/SD0DIO/S23 VASYS2 9 67 P5.0/SDCLK/S24 AVSS2 10 66 P4.7/PM_TA3.0/S25 VREF 11 65 P4.6/PM_UCB1CLK/S26 SD4P0 12 64 P4.5/PM_UCB1SIMO/PM_UCB1SDA/S27 SD4N0 13 63 P4.4/PM_UCB1SOMI/PM_UCB1SCL/S28 SD5P0 14 62 P4.3/PM_UCA3CLK/S29 SD5N0 15 61 P4.2/PM_UCA3TXD/PM_UCA3SIMO/S30 SD6P0 16 60 P4.1/PM_UCA3RXD/PM_UCA3SOMI/S31 SD6N0 17 59 P4.0/PM_UCA2CLK/S32 AVSS1 18 58 P3.7/PM_UCA2TXD/PM_UCA2SIMO/S33 AVCC 19 57 P3.6/PM_UCA2RXD/PM_UCA2SOMI/S34 VASYS1 20 56 P3.5/PM_UCA1TXD/PM_UCA1SIMO/S35 AUXVCC2 21 55 P3.4/PM_UCA1RXD/PM_UCA1SOMI/S36 AUXVCC1 22 54 P3.3/PM_UCA1CLK/S37 VDSYS1 23 53 P3.2/PM_UCA0CLK/S38 DVCC 24 52 P3.1/PM_UCA0TXD/PM_UCA0SIMO/S39 P3.0/PM_UCA0RXD/PM_UCA0SOMI P2.7/PM_UCB0CLK/CB2 P2.6/PM_UCB0SIMO/PM_UCB0SDA/R03 P2.5/PM_UCB0SOMI/PM_UCB0SCL/LCDREF/R13 P2.4/PM_TA2.0/R23 LCDCAP/R33 P2.3/PM_TA1.0/COM7 P2.2/PM_TA0.2/COM6 P2.1/PM_TA0.1/BSL_RX/COM5 P2.0/PM_TA0.0/BSL_TX/COM4 P1.7/COM3 P1.6/COM2 COM1 COM0 P1.0/TA1.1/VeREF-/A0 P1.1/TA2.1/CBOUT/VeREF+/A1 P1.2/ACLK/A2 P1.3/ADC10CLK/A3 P1.4/MCLK/CB1/A4 P1.5/SMCLK/CB0/A5 RTCCAP0 RTCCAP1 AUXVCC3 XOUT XIN 25 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VCORE B. PJ.3/TCK SD0P0 DVSS1 A. PJ.2/TMS RST/NMI/SBWTDIO Figure 4-2 shows the pinout for the MSP430F677x devices in the 100-pin PZ package. Table 4-2 lists the differences among the pinouts for the MSP430F677x, MSP430F676x, and MSP430F674x devices. The secondary digital functions on Ports P2, P3 and P4 are fully mappable. This pinout shows only the default mapping. See Table 6-11 for details. The pair of pins VDSYS1 and VDSYS2, VASYS1 and VASYS2 must be connected externally on the board for proper device operation. CAUTION: The LCDCAP/R33 pin must be connected to DVSS if it is not used. Figure 4-2. 100-Pin PZ Package (Top View) Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 Copyright © 2012–2018, Texas Instruments Incorporated 11 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com Table 4-2. Pinout Differences for MSP430F677xIPZ , MSP430F676xIPZ , and MSP430F674xIPZ 12 PIN NAME PIN NUMBER MSP430F677xIPZ MSP430F676xIPZ MSP430F674xIPZ 11 VREF VREF VREF 12 SD4P0 SD4P0 NC 13 SD4N0 SD4N0 NC 14 SD5P0 SD5P0 NC 15 SD5N0 SD5NO NC 16 SD6P0 NC NC 17 SD6N0 NC NC 72 P5.5/SD4DIO/S19 P5.5/SD4DIO/S19 P5.5/S19 73 P5.6/SD5DIO/S18 P5.6/SD5DIO/S18 P5.6/S18 74 P5.7/SD6DIO/S17 P5.7/S17 P5.7/S17 Terminal Configuration and Functions Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 www.ti.com 4.2 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 Signal Descriptions Table 4-3 describes the signals for devices in the PEU package. See Table 4-4 for the PZ package signal descriptions. Table 4-3. Terminal Functions – PEU Package TERMINAL NAME NO. I/O (1) DESCRIPTION PEU XIN 1 I/O Input terminal for crystal oscillator XOUT 2 I/O Output terminal for crystal oscillator AUXVCC3 3 RTCCAP1 4 I External time capture pin 1 for RTC_C RTCCAP0 5 I External time capture pin 0 for RTC_C Auxiliary power supply AUXVCC3 for back up subsystem General-purpose digital I/O with port interrupt P1.5/SMCLK/CB0/A5 6 I/O SMCLK clock output Comparator_B input CB0 Analog input A5 for 10-bit ADC General-purpose digital I/O with port interrupt P1.4/MCLK/CB1/A4 7 I/O MCLK clock output Comparator_B input CB1 Analog input A4 for 10-bit ADC General-purpose digital I/O with port interrupt P1.3/ADC10CLK/A3 (2) 8 I/O ADC10_A clock output Analog input A3 for 10-bit ADC General-purpose digital I/O with port interrupt P1.2/ACLK/A2 9 I/O ACLK clock output Analog input A2 for 10-bit ADC General-purpose digital I/O with port interrupt P1.1/TA2.1/VeREF+/A1 10 I/O Timer TA2 CCR1 capture: CCI1A input, compare: Out1 output Positive terminal for the ADC reference voltage for an external applied reference voltage Analog input A1 for 10-bit ADC General-purpose digital I/O with port interrupt P1.0/TA1.1/VeREF-/A0 11 I/O Timer TA1 CCR1 capture: CCI1A input, compare: Out1 output Negative terminal for the ADC reference voltage for an external applied reference voltage Analog input A0 for 10-bit ADC General-purpose digital I/O with port interrupt and mappable secondary function P2.4/PM_TA2.0 12 I/O Default mapping: Timer TA2 capture CCR0: CCI0A input, compare: Out0 output General-purpose digital I/O with port interrupt and mappable secondary function P2.5/PM_UCB0SOMI/ PM_UCB0SCL 13 I/O Default mapping: eUSCI_B0 SPI slave out master in Default mapping: eUSCI_B0 I2C clock General-purpose digital I/O with port interrupt and mappable secondary function P2.6/PM_UCB0SIMO/ PM_UCB0SDA 14 I/O Default mapping: eUSCI_B0 SPI slave in master out Default mapping: eUSCI_B0 I2C data General-purpose digital I/O with port interrupt and mappable secondary function P2.7/PM_UCB0CLK 15 I/O Default mapping: eUSCI_B0 clock input/output (1) (2) I = input, O = output Before enabling the analog function (A3), pull this pin low by setting the port function to output low or to input with the internal pulldown resistor enabled. Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 Copyright © 2012–2018, Texas Instruments Incorporated 13 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com Table 4-3. Terminal Functions – PEU Package (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION PEU General-purpose digital I/O with mappable secondary function P3.0/PM_UCA0RXD/ PM_UCA0SOMI 16 I/O Default mapping: eUSCI_A0 UART receive data Default mapping: eUSCI_A0 SPI slave out master in General-purpose digital I/O with mappable secondary function P3.1/PM_UCA0TXD/ PM_UCA0SIMO 17 I/O Default mapping: eUSCI_A0 UART transmit data Default mapping: eUSCI_A0 SPI slave in master out General-purpose digital I/O with mappable secondary function P3.2/PM_UCA0CLK 18 I/O Default mapping: eUSCI_A0 clock input/output General-purpose digital I/O with mappable secondary function P3.3/PM_UCA1CLK 19 I/O Default mapping: eUSCI_A1 clock input/output General-purpose digital I/O with mappable secondary function P3.4/PM_UCA1RXD/ PM_UCA1SOMI 20 I/O Default mapping: eUSCI_A1 UART receive data Default mapping: eUSCI_A1 SPI slave out master in General-purpose digital I/O with mappable secondary function P3.5/PM_UCA1TXD/ PM_UCA1SIMO 21 I/O COM0 22 O LCD common output COM0 for LCD backplane COM1 23 O LCD common output COM1 for LCD backplane P1.6/COM2 24 I/O Default mapping: eUSCI_A1 UART transmit data Default mapping: eUSCI_A1 SPI slave in master out General-purpose digital I/O with port interrupt LCD common output COM2 for LCD backplane General-purpose digital I/O with port interrupt P1.7/COM3 25 I/O LCD common output COM3 for LCD backplane General-purpose digital I/O P5.0/COM4 26 I/O LCD common output COM4 for LCD backplane General-purpose digital I/O P5.1/COM5 27 I/O LCD common output COM5 for LCD backplane General-purpose digital I/O P5.2/COM6 28 I/O LCD common output COM6 for LCD backplane General-purpose digital I/O P5.3/COM7 29 I/O LCD common output COM7 for LCD backplane LCD capacitor connection LCDCAP/R33 30 I/O Input/output port of most positive analog LCD voltage (V1) CAUTION: This pin must be connected to DVSS if not used. General-purpose digital I/O P5.4/SDCLK/R23 31 I/O SD24_B bit stream clock input/output Input/output port of second most positive analog LCD voltage (V2) General-purpose digital I/O P5.5/SD0DIO/ LCDREF/R13 SD24_B converter 0 bit stream data input/output 32 I/O External reference voltage input for regulated LCD voltage Input/output port of third most positive analog LCD voltage (V3 or V4) 14 Terminal Configuration and Functions Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 www.ti.com SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 Table 4-3. Terminal Functions – PEU Package (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION PEU General-purpose digital I/O P5.6/SD1DIO/R03 33 I/O SD24_B converter 1 bit stream data input/output Input/output port of lowest analog LCD voltage (V5) General-purpose digital I/O P5.7/SD2DIO/CB2 34 I/O SD24_B converter 2 bit stream data input/output Comparator_B input CB2 General-purpose digital I/O P6.0/SD3DIO 35 I/O SD24_B converter 3 bit stream data input/output General-purpose digital I/O with mappable secondary function P3.6/PM_UCA2RXD/ PM_UCA2SOMI 36 I/O Default mapping: eUSCI_A2 UART receive data Default mapping: eUSCI_A2 SPI slave out master in General-purpose digital I/O with mappable secondary function P3.7/PM_UCA2TXD/ PM_UCA2SIMO 37 I/O Default mapping: eUSCI_A2 UART transmit data Default mapping: eUSCI_A2 SPI slave in master out General-purpose digital I/O with mappable secondary function P4.0/PM_UCA2CLK 38 I/O Default mapping: eUSCI_A2 clock input/output General-purpose digital I/O with mappable secondary function P4.1/PM_UCA3RXD/ PM_UCA3SOMI 39 I/O Default mapping: eUSCI_A3 UART receive data Default mapping: eUSCI_A3 SPI slave out master in General-purpose digital I/O with mappable secondary function P4.2/PM_UCA3TXD/ PM_UCA3SIMO 40 I/O Default mapping: eUSCI_A3 UART transmit data Default mapping: eUSCI_A3 SPI slave in master out General-purpose digital I/O with mappable secondary function P4.3/PM_UCA3CLK 41 I/O Default mapping: eUSCI_A3 clock input/output General-purpose digital I/O with mappable secondary function P4.4/PM_UCB1SOMI/ PM_UCB1SCL 42 I/O Default mapping: eUSCI_B1 SPI slave out, master in Default mapping: eUSCI_B1 I2C clock General-purpose digital I/O with mappable secondary function P4.5/PM_UCB1SIMO/ PM_UCB1SDA 43 I/O Default mapping: eUSCI_B1 SPI slave in, master out Default mapping: eUSCI_B1 I2C data General-purpose digital I/O with mappable secondary function P4.6/PM_UCB1CLK 44 I/O Default mapping: eUSCI_B1 clock input/output General-purpose digital I/O with mappable secondary function P4.7/PM_TA3.0 45 I/O Default mapping: Timer TA3 capture CCR0: CCI0A input, compare: Out0 output General-purpose digital I/O P6.1/SD4DIO/S39 46 I/O SD24_B converter 4 bit stream data input/output (not available in F674x devices) LCD segment output S39 General-purpose digital I/O P6.2/SD5DIO/S38 47 I/O SD24_B converter 5 bit stream data input/output (not available in F674x devices) LCD segment output S38 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 Copyright © 2012–2018, Texas Instruments Incorporated 15 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com Table 4-3. Terminal Functions – PEU Package (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION PEU General-purpose digital I/O P6.3/SD6DIO/S37 48 I/O SD24_B converter 6 bit stream data input/output (not available in F674x, F676x devices) LCD segment output S37 General-purpose digital I/O P6.4/S36 49 I/O LCD segment output S36 General-purpose digital I/O P6.5/S35 50 I/O LCD segment output S35 General-purpose digital I/O P6.6/S34 51 I/O LCD segment output S34 General-purpose digital I/O P6.7/S33 52 I/O LCD segment output S33 General-purpose digital I/O P7.0/S32 53 I/O LCD segment output S32 General-purpose digital I/O P7.1/S31 54 I/O LCD segment output S31 General-purpose digital I/O P7.2/S30 55 I/O LCD segment output S30 General-purpose digital I/O P7.3/S29 56 I/O LCD segment output S29 General-purpose digital I/O P7.4/S28 57 I/O LCD segment output S28 General-purpose digital I/O P7.5/S27 58 I/O LCD segment output S27 General-purpose digital I/O P7.6/S26 59 I/O LCD segment output S26 General-purpose digital I/O P7.7/S25 60 I/O LCD segment output S25 General-purpose digital I/O P8.0/S24 61 I/O LCD segment output S24 General-purpose digital I/O P8.1/S23 62 I/O LCD segment output S23 General-purpose digital I/O P8.2/S22 63 I/O LCD segment output S22 General-purpose digital I/O P8.3/S21 64 I/O LCD segment output S21 General-purpose digital I/O P8.4/S20 65 I/O LCD segment output S20 General-purpose digital I/O P8.5/S19 66 I/O LCD segment output S19 General-purpose digital I/O P8.6/S18 67 I/O LCD segment output S18 16 Terminal Configuration and Functions Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 www.ti.com SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 Table 4-3. Terminal Functions – PEU Package (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION PEU General-purpose digital I/O P8.7/S17 68 I/O VDSYS2 (3) 69 Digital power supply for I/Os DVSS2 70 Digital ground supply P9.0/S16 71 LCD segment output S17 General-purpose digital I/O I/O LCD segment output S16 General-purpose digital I/O P9.1/S15 72 I/O LCD segment output S15 General-purpose digital I/O P9.2/S14 73 I/O LCD segment output S14 General-purpose digital I/O P9.3/S13 74 I/O LCD segment output S13 General-purpose digital I/O P9.4/S12 75 I/O LCD segment output S12 General-purpose digital I/O P9.5/S11 76 I/O LCD segment output S11 General-purpose digital I/O P9.6/S10 77 I/O LCD segment output S10 General-purpose digital I/O P9.7/S9 78 I/O LCD segment output S9 General-purpose digital I/O P10.0/S8 79 I/O LCD segment output S8 General-purpose digital I/O P10.1/S7 80 I/O LCD segment output S7 General-purpose digital I/O P10.2/S6 81 I/O LCD segment output S6 General-purpose digital I/O P10.3/S5 82 I/O LCD segment output S5 General-purpose digital I/O P10.4/S4 83 I/O LCD segment output S4 General-purpose digital I/O P10.5/S3 84 I/O LCD segment output S3 General-purpose digital I/O P10.6/S2 85 I/O LCD segment output S2 General-purpose digital I/O P10.7/S1 86 I/O LCD segment output S1 General-purpose digital I/O P11.0/S0 87 I/O LCD segment output S0 General-purpose digital I/O P11.1/TA3.1/CB3 88 I/O Timer TA3 capture CCR1: CCI1A input, compare: Out1 output Comparator_B input CB3 (3) The pins VDSYS1 and VDSYS2 must be connected externally on board for proper device operation. Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 Copyright © 2012–2018, Texas Instruments Incorporated 17 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com Table 4-3. Terminal Functions – PEU Package (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION PEU General-purpose digital I/O P11.2/TA1.1 89 I/O Timer TA1 capture CCR1: CCI1A input, compare: Out1 output General-purpose digital I/O P11.3/TA2.1 90 I/O Timer TA2 capture CCR1: CCI1A input, compare: Out1 output General-purpose digital I/O P11.4/CBOUT 91 I/O Comparator_B Output General-purpose digital I/O P11.5/TACLK/RTCCLK 92 I/O Timer clock input TACLK for TA0, TA1, TA2, TA3 RTCCLK clock output General-purpose digital I/O with port interrupt and mappable secondary function P2.0/PM_TA0.0/BSL_TX 93 I/O Default mapping: Timer TA0 capture CCR0: CCI0A input, compare: Out0 output Bootloader: Data transmit General-purpose digital I/O with port interrupt and mappable secondary function P2.1/PM_TA0.1/BSL_RX 94 I/O Default mapping: Timer TA0 capture CCR1: CCI1A input, compare: Out1 output Bootloader: Data receive General-purpose digital I/O with port interrupt and mappable secondary function P2.2/PM_TA0.2 95 I/O Default mapping: Timer TA0 capture CCR2: CCI2A input, compare: Out2 output General-purpose digital I/O port interrupt and with mappable secondary function P2.3/PM_TA1.0 96 I/O Default mapping: Timer TA1 capture CCR0: CCI0A input, compare: Out0 output Test mode pin – select digital I/O on JTAG pins TEST/SBWTCK 97 I Spy-Bi-Wire input clock General-purpose digital I/O PJ.0/TDO 98 I/O Test data output General-purpose digital I/O PJ.1/TDI/TCLK 99 I/O Test data input or Test clock input General-purpose digital I/O PJ.2/TMS 100 I/O Test mode select General-purpose digital I/O PJ.3/TCK 101 I/O Test clock Reset input active low (4) RST/NMI/SBWTDIO 102 I/O Nonmaskable interrupt input Spy-By-Wire data input/output SD0P0 103 I SD24_B positive analog input for converter 0 (5) SD0N0 104 I SD24_B negative analog input for converter 0 (5) SD1P0 105 I SD24_B positive analog input for converter 1 (5) SD1N0 106 I SD24_B negative analog input for converter 1 (5) SD2P0 107 I SD24_B positive analog input for converter 2 (5) SD2N0 108 I SD24_B negative analog input for converter 2 (5) SD3P0 109 I SD24_B positive analog input for converter 3 (5) SD3N0 110 I SD24_B negative analog input for converter 3 (4) VASYS2 111 (4) (5) 18 Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of CVSYS When this pin is configured as reset, the internal pullup resistor is enabled by default. Short unused analog input pairs and connect them to analog ground. Terminal Configuration and Functions Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 www.ti.com SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 Table 4-3. Terminal Functions – PEU Package (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION PEU AVSS2 112 VREF 113 I SD24_B external reference voltage SD4P0 114 I SD24_B positive analog input for converter 4 (5) (not available on F674x devices) SD4N0 115 I SD24_B negative analog input for converter 4 (5) (not available on F674x devices) SD5P0 116 I SD24_B positive analog input for converter 5 (5) (not available on F674x devices) SD5N0 117 I SD24_B negative analog input for converter 5 (5) (not available on F674x devices) SD6P0 118 I SD24_B positive analog input for converter 6 (5) (not available on F676x, F674x devices) SD6N0 119 I SD24_B negative analog input for converter 6 (5) (not available on F676x, F674x devices) AVSS1 120 Analog ground supply AVCC 121 Analog power supply VASYS1 122 Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of CVSYS. AUXVCC2 123 Auxiliary power supply AUXVCC2 AUXVCC1 124 Auxiliary power supply AUXVCC1 VDSYS1 (3) 125 Digital power supply selected between DVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of CVSYS. DVCC 126 Digital power supply DVSS1 127 Digital ground supply VCORE (6) 128 Regulated core power supply (internal use only, no external current loading) (6) Analog ground supply VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended capacitor value, CVCORE. Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 Copyright © 2012–2018, Texas Instruments Incorporated 19 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com Table 4-4 describes the signals for devices in the PZ package. See Table 4-3 for the PEU package signal descriptions. Table 4-4. Terminal Functions – PZ Package TERMINAL NAME NO. I/O (1) DESCRIPTION PZ SD0P0 1 I SD24_B positive analog input for converter 0 (2) SD0N0 2 I SD24_B negative analog input for converter 0 (2) SD1P0 3 I SD24_B positive analog input for converter 1 (2) SD1N0 4 I SD24_B negative analog input for converter 1 (2) SD2P0 5 I SD24_B positive analog input for converter 2 (2) SD2N0 6 I SD24_B negative analog input for converter 2 (2) SD3P0 7 I SD24_B positive analog input for converter 3 (2) SD3N0 8 I SD24_B negative analog input for converter 3 (2) VASYS2 9 AVSS2 10 VREF 11 I SD24_B external reference voltage SD4P0 12 I SD24_B positive analog input for converter 4 (2) (not available on F674x devices) SD4N0 13 I SD24_B negative analog input for converter 4 (2) (not available on F674x devices) SD5P0 14 I SD24_B positive analog input for converter 5 (2) (not available on F674x devices) SD5N0 15 I SD24_B negative analog input for converter 5 (2) (not available on F674x devices) SD6P0 16 I SD24_B positive analog input for converter 6 (2) (not available on F676x, F674x devices) SD6N0 17 I SD24_B negative analog input for converter 6 (2) (not available on F676x, F674x devices) AVSS1 18 Analog ground supply AVCC 19 Analog power supply VASYS1 20 Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of CVSYS AUXVCC2 21 Auxiliary power supply AUXVCC2 AUXVCC1 22 Auxiliary power supply AUXVCC1 23 Digital power supply selected between DVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of CVSYS. 24 Digital power supply 25 Digital ground supply VDSYS1 (3) DVCC DVSS1 VCORE (4) Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of CVSYS. Analog ground supply 26 Regulated core power supply (internal use only, no external current loading) XIN 27 I/O Input terminal for crystal oscillator XOUT 28 I/O Output terminal for crystal oscillator AUXVCC3 29 RTCCAP1 30 I External time capture pin 1 for RTC_C RTCCAP0 31 I External time capture pin 0 for RTC_C Auxiliary power supply AUXVCC3 for back up subsystem General-purpose digital I/O with port interrupt SMCLK clock output P1.5/SMCLK/CB0/A5 32 I/O Comparator_B input CB0 Analog input A5 for 10-bit ADC (1) (2) (3) (4) 20 I = input, O = output Short unused analog input pairs and connect them to analog ground. The pins VDSYS1 and VDSYS2 must be connected externally on board for proper device operation. VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended capacitor value, CVCORE. Terminal Configuration and Functions Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 www.ti.com SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 Table 4-4. Terminal Functions – PZ Package (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION PZ General-purpose digital I/O with port interrupt MCLK clock output P1.4/MCLK/CB1/A4 33 I/O Comparator_B input CB1 Analog input A4 for 10-bit ADC General-purpose digital I/O with port interrupt P1.3/ADC10CLK/A3 34 I/O ADC10_A clock output Analog input A3 for 10-bit ADC General-purpose digital I/O with port interrupt P1.2/ACLK/A2 35 I/O ACLK clock output Analog input A2 for 10-bit ADC General-purpose digital I/O with port interrupt Timer TA2 CCR1 capture: CCI1A input, compare: Out1 output P1.1/TA2.1/CBOUT/ VeREF+/A1 36 I/O Comparator_B Output Positive terminal for the ADC reference voltage for an external applied reference voltage Analog input A1 for 10-bit ADC General-purpose digital I/O with port interrupt Timer TA1 CCR1 capture: CCI1A input, compare: Out1 output P1.0/TA1.1/VeREF-/A0 37 I/O Negative terminal for the ADC reference voltage for an external applied reference voltage Analog input A0 for 10-bit ADC COM0 38 I/O LCD common output COM0 for LCD backplane COM1 39 I/O LCD common output COM1 for LCD backplane P1.6/COM2 40 I/O General-purpose digital I/O with port interrupt LCD common output COM2 for LCD backplane General-purpose digital I/O with port interrupt P1.7/COM3 41 I/O LCD common output COM3 for LCD backplane General-purpose digital I/O with port interrupt and mappable secondary function P2.0/PM_TA0.0/ BSL_TX/COM4 Default Mapping: Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output 42 I/O Bootloader: Data transmit LCD common output COM4 for LCD backplane General-purpose digital I/O with port interrupt and mappable secondary function P2.1/PM_TA0.1/ BSL_RX/COM5 Default Mapping: Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output 43 I/O Bootloader: Data receive LCD common output COM5 for LCD backplane General-purpose digital I/O with port interrupt and mappable secondary function P2.2/PM_TA0.2/COM6 44 I/O Default Mapping: Timer TA0 CCR0 capture: CCI2A input, compare: Out2 output LCD common output COM6 for LCD backplane General-purpose digital I/O with port interrupt and mappable secondary function P2.3/PM_TA1.0/COM7 45 I/O Default Mapping: Timer TA1 CCR0 capture: CCI0A input, compare: Out0 output LCD common output COM7 for LCD backplane Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 Copyright © 2012–2018, Texas Instruments Incorporated 21 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com Table 4-4. Terminal Functions – PZ Package (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION PZ LCD capacitor connection LCDCAP/R33 46 I/O Input/output port of most positive analog LCD voltage (V1) CAUTION: This pin must be connected to DVSS if not used. General-purpose digital I/O with port interrupt and mappable secondary function P2.4/PM_TA2.0/R23 47 I/O Default Mapping: Timer TA2 CCR0 capture: CCI0A input, compare: Out0 output Input/output port of second most positive analog LCD voltage (V2) General-purpose digital I/O with port interrupt and mappable secondary function P2.5/PM_UCB0SOMI/ PM_UCB0SCL/LCDREF/ R13 Default mapping: eUSCI_B0 SPI slave out, master in 48 I/O Default mapping: eUSCI_B0 I2C clock External reference voltage input for regulated LCD voltage Input/output port of third most positive analog LCD voltage (V3 or V4) General-purpose digital I/O with port interrupt and mappable secondary function P2.6/PM_UCB0SIMO/ PM_UCB0SDA/R03 Default mapping: eUSCI_B0 SPI slave in, master out 49 I/O Default mapping: eUSCI_B0 I2C data Input/output port of lowest analog LCD voltage (V5) General-purpose digital I/O with port interrupt and mappable secondary function P2.7/PM_UCB0CLK/CB2 50 I/O Default mapping: eUSCI_B0 clock input/output Comparator_B input CB2 General-purpose digital I/O with mappable secondary function P3.0/PM_UCA0RXD/ PM_UCA0SOMI 51 I/O Default mapping: eUSCI_A0 UART receive data Default mapping: eUSCI_A0 SPI slave out, master in General-purpose digital I/O with mappable secondary function P3.1/PM_UCA0TXD/ PM_UCA0SIMO/S39 Default mapping: eUSCI_A0 UART transmit data 52 I/O Default mapping: eUSCI_A0 SPI slave in, master out LCD segment output S39 General-purpose digital I/O with mappable secondary function P3.2/PM_UCA0CLK/S38 53 I/O Default mapping: eUSCI_A0 clock input/output LCD segment output S38 General-purpose digital I/O with mappable secondary function P3.3/PM_UCA1CLK/S37 54 I/O Default mapping: eUSCI_A1 clock input/output LCD segment output S37 General-purpose digital I/O with mappable secondary function P3.4/PM_UCA1RXD/ PM_UCA1SOMI/S36 Default mapping: eUSCI_A1 UART receive data 55 I/O Default mapping: eUSCI_A1 SPI slave out, master in LCD segment output S36 General-purpose digital I/O with mappable secondary function P3.5/PM_UCA1TXD/ PM_UCA1SIMO/S35 Default mapping: eUSCI_A1 UART transmit data 56 I/O Default mapping: eUSCI_A1 SPI slave in, master out LCD segment output S35 22 Terminal Configuration and Functions Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 www.ti.com SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 Table 4-4. Terminal Functions – PZ Package (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION PZ General-purpose digital I/O with mappable secondary function P3.6/PM_UCA2RXD/ PM_UCA2SOMI/S34 Default mapping: eUSCI_A2 UART receive data 57 I/O Default mapping: eUSCI_A2 SPI slave out, master in LCD segment output S34 General-purpose digital I/O with mappable secondary function P3.7/PM_UCA2TXD/ PM_UCA2SIMO/S33 Default mapping: eUSCI_A2 UART transmit data 58 I/O Default mapping: eUSCI_A2 SPI slave in, master out LCD segment output S33 General-purpose digital I/O with mappable secondary function P4.0/PM_UCA2CLK/S32 59 I/O Default mapping: eUSCI_A2 clock input/output LCD segment output S32 General-purpose digital I/O with mappable secondary function P4.1/PM_UCA3RXD/ PM_UCA3SOMI/S31 Default mapping: eUSCI_A3 UART receive data 60 I/O Default mapping: eUSCI_A3 SPI slave out, master in LCD segment output S31 General-purpose digital I/O with mappable secondary function P4.2/PM_UCA3TXD/ PM_UCA3SIMO/S30 Default mapping: eUSCI_A3 UART transmit data 61 I/O Default mapping: eUSCI_A3 SPI slave in, master out LCD segment output S30 General-purpose digital I/O with mappable secondary function P4.3/PM_UCA3CLK/S29 62 I/O Default mapping: eUSCI_A3 clock input/output LCD segment output S29 General-purpose digital I/O with mappable secondary function P4.4/PM_UCB1SOMI/ PM_UCB1SCL/S28 Default mapping: eUSCI_B1 SPI slave out, master in 63 I/O Default mapping: eUSCI_B1 I2C clock LCD segment output S28 General-purpose digital I/O with mappable secondary function P4.5/PM_UCB1SIMO/ PM_UCB1SDA/S27 Default mapping: eUSCI_B1 SPI slave in, master out 64 I/O Default mapping: eUSCI_B1 I2C data LCD segment output S27 General-purpose digital I/O with mappable secondary function P4.6/PM_UCB1CLK/S26 65 I/O Default mapping: eUSCI_B1 clock input/output LCD segment output S26 General-purpose digital I/O with mappable secondary function P4.7/PM_TA3.0/S25 66 I/O Default Mapping: Timer TA3 CCR0 capture: CCI0A input, compare: Out0 output LCD segment output S25 General-purpose digital I/O P5.0/SDCLK/S24 67 I/O SD24_B bit stream clock input/output LCD segment output S24 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 Copyright © 2012–2018, Texas Instruments Incorporated 23 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com Table 4-4. Terminal Functions – PZ Package (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION PZ General-purpose digital I/O P5.1/PM_SD0DIO/S23 68 I/O Default mapping: SD24_B converter 0 bit stream data input/output LCD segment output S23 General-purpose digital I/O P5.2/PM_SD1DIO/S22 69 I/O Default mapping: SD24_B converter 1 bit stream data input/output LCD segment output S22 General-purpose digital I/O P5.3/PM_SD2DIO/S21 70 I/O Default mapping: SD24_B converter 2 bit stream data input/output LCD segment output S21 General-purpose digital I/O P5.4/PM_SD3DIO/S20 71 I/O Default mapping: SD24_B converter 3 bit stream data input/output LCD segment output S20 General-purpose digital I/O P5.5/PM_SD4DIO/S19 72 I/O Default mapping: SD24_B converter 4 bit stream data input/output (not available on F674x devices) LCD segment output S19 General-purpose digital I/O P5.6/PM_SD5DIO/S18 73 I/O Default mapping: SD24_B converter 5 bit stream data input/output (not available on F674x devices) LCD segment output S18 General-purpose digital I/O I/O Default mapping: SD24_B converter 4 bit stream data input/output (not available on F676x, F674x devices) P5.7/PM_SD6DIO/S17 74 VDSYS2 (5) 75 Digital power supply for I/Os DVSS2 76 Digital ground supply P6.0/S16 77 LCD segment output S17 General-purpose digital I/O I/O LCD segment output S16 General-purpose digital I/O P6.1/S15 78 I/O LCD segment output S15 General-purpose digital I/O P6.2/S14 79 I/O LCD segment output S14 General-purpose digital I/O P6.3/S13 80 I/O LCD segment output S13 General-purpose digital I/O P6.4/S12 81 I/O LCD segment output S12 General-purpose digital I/O P6.5/S11 82 I/O LCD segment output S11 General-purpose digital I/O P6.6/S10 83 I/O LCD segment output S10 General-purpose digital I/O P6.7/S9 84 I/O LCD segment output S9 (5) 24 The pins VDSYS1 and VDSYS2 must be connected externally on board for proper device operation. Terminal Configuration and Functions Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 www.ti.com SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 Table 4-4. Terminal Functions – PZ Package (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION PZ General-purpose digital I/O P7.0/S8 85 I/O LCD segment output S8 P7.1/S7 86 I/O General-purpose digital I/O LCD segment output S7 General-purpose digital I/O P7.2/S6 87 I/O LCD segment output S6 P7.3/S5 88 I/O General-purpose digital I/O LCD segment output S5 General-purpose digital I/O P7.4/S4 89 I/O LCD segment output S4 P7.5/S3 90 I/O General-purpose digital I/O LCD segment output S3 General-purpose digital I/O P7.6/S2 91 I/O LCD segment output S2 General-purpose digital I/O P7.7/S1 92 I/O LCD segment output S1 General-purpose digital I/O P8.0/S0 93 I/O LCD segment output S0 General-purpose digital I/O Timer clock input TACLK for TA0, TA1, TA2, TA3 P8.1/TACLK/RTCCLK/CB3 94 I/O RTCCLK clock output Comparator_B input CB3 Test mode pin – select digital I/O on JTAG pins TEST/SBWTCK 95 I Spy-By-Wire input clock General-purpose digital I/O PJ.0/TDO 96 I/O Test data output General-purpose digital I/O PJ.1/TDI/TCLK 97 I/O Test data input or Test clock input General-purpose digital I/O PJ.2/TMS 98 I/O Test mode select General-purpose digital I/O PJ.3/TCK 99 I/O Test clock Reset input, active low (6) RST/NMI/SBWTDIO 100 I/O Nonmaskable interrupt input Spy-By-Wire data input/output (6) When this pin is configured as reset, the internal pullup resistor is enabled by default. Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 Copyright © 2012–2018, Texas Instruments Incorporated 25 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 5 Specifications All graphs in this section are for typical conditions, unless otherwise noted. Typical (TYP) values are specified at VCC = 3.3 V and TA = 25°C, unless otherwise noted. 5.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Voltage applied at DVCC to DVSS All pins except VCORE, SD24_B input pins (SDxN0, SDxP0) (3), AUXVCC1, AUXVCC2, and AUXVCC3 (4) Voltage applied to pins (2) MIN MAX –0.3 4.1 V –0.3 VCC + 0.3 V All pins except SD24_B input pins (SDxN0, SDxP0) ±2 SD0N0, SD0P0, SD1N0, SD1P0, SD2N0, SD2P0, SD3N0, SD3P0, SD4N0, SD4P0, SD5N0, SD5P0, SD6N0, SD6P0 (5) Diode current at pins Storage temperature, Tstg (1) (2) (3) (4) (5) (6) mA 2 Maximum junction temperature, TJ (6) UNIT –55 95 °C 105 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages referenced to VSS = VDVSS = VAVSS. See Section 5.48 for SD24_B specifications. See Section 5.27 for AUX specifications. A protection diode is connected to VCC for the SD24_B input pins. No protection diode is connected to VSS. Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. 5.2 ESD Ratings VALUE V(ESD) (1) (2) 5.3 Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±1000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±250 Recommended Operating Conditions 1.8 3.6 2.0 3.6 PMMCOREVx = 0, 1, 2 2.2 3.6 PMMCOREVx = 0, 1, 2, 3 2.4 VSS Supply voltage VAVSS = VDVSS = VSS TA Operating free-air temperature I version –40 TJ Operating junction temperature I version –40 CVCORE Recommended capacitor at VCORE (3) CDVCC/ CVCORE Capacitor ratio of DVCC to VCORE 26 MAX PMMCOREVx = 0, 1 Supply voltage during program execution and flash programming. VAVCC = VDVCC = VCC (1) (2) (3) NOM PMMCOREVx = 0 VCC (2) V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±1000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V may actually have higher performance. MIN (1) UNIT UNIT V 3.6 0 V 85 85 470 °C °C nF 10 TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between VAVCC and VDVCC can be tolerated during power up and operation. The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the threshold parameters in Section 5.22 for the exact values and more details. A capacitor tolerance of ±20% or better is required. Specifications Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 www.ti.com SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 Recommended Operating Conditions (continued) MIN Processor frequency (maximum MCLK frequency) (4) (see Figure 5-1) fSYSTEM (5) NOM MAX PMMCOREVx = 0, 1.8 V ≤ VCC ≤ 3.6 V (default condition) 0 8.0 PMMCOREVx = 1, 2 V ≤ VCC ≤ 3.6 V 0 12.0 PMMCOREVx = 2, 2.2 V ≤ VCC ≤ 3.6 V 0 20.0 PMMCOREVx = 3, 2.4 V ≤ VCC ≤ 3.6 V 0 25.0 UNIT MHz ILOAD, DVCCD Maximum load current that can be drawn from DVCC for core and IO (ILOAD = ICORE + IIO) 20 mA ILOAD, AUX1D Maximum load current that can be drawn from AUXVCC1 for core and IO (ILOAD = ICORE + IIO) 20 mA ILOAD, AUX2D Maximum load current that can be drawn from AUXVCC2 for core and IO (ILOAD = ICORE + IIO) 20 mA ILOAD, AVCCA Maximum load current that can be drawn from AVCC for analog modules (ILOAD = IModules) 10 mA ILOAD, AUX1A Maximum load current that can be drawn from AUXVCC1 for analog modules (ILOAD = IModules) 5 mA ILOAD, AUX2A Maximum load current that can be drawn from AUXVCC2 for analog modules (ILOAD = IModules) 5 mA PINT Internal power dissipation VCC × IDVCC W W W PIO I/O power dissipation of the I/O pins powered by DVCC (VCC – VIOH) × IIOH + VIOL × IIOL PMAX Maximum allowed power dissipation, PMAX > PIO + PINT (TJ – TA)/θJA (4) (5) The MSP430 CPU is clocked directly with MCLK. Both the high and low phases of MCLK must not exceed the pulse duration of the specified maximum frequency. Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet. 25 System Frequency - MHz 3 20 2 2, 3 1 1, 2 1, 2, 3 0, 1 0, 1, 2 0, 1, 2, 3 12 8 0 0 1.8 2.0 2.2 2.4 3.6 Supply Voltage - V The numbers within the fields denote the supported PMMCOREVx settings. Figure 5-1. Maximum System Frequency Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 Copyright © 2012–2018, Texas Instruments Incorporated 27 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 5.4 www.ti.com Active Mode Supply Current Into VCC Excluding External Current over recommended operating free-air temperature (unless otherwise noted) (1) (2) (3) FREQUENCY (fDCO = fMCLK = fSMCLK) PARAMETER IAM, IAM, (1) (2) (3) (4) (5) 28 Flash RAM (4) (5) EXECUTION MEMORY Flash RAM VCC 3V 3V PMM COREVx 1 MHz 8 MHz 12 MHz TYP MAX TYP MAX 0 0.32 0.50 2.08 2.84 1 0.35 2 20 MHz TYP MAX 2.35 3.50 4.76 0.39 2.68 3 0.41 2.83 0 0.19 1.04 1 0.21 1.20 1.77 2 0.23 1.38 2.04 3.35 3 0.24 1.47 2.18 3.58 25 MHz TYP MAX 3.99 6.61 8.3 4.22 6.98 TYP UNIT MAX mA 8.67 11.75 mA 4.44 All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are chosen to closely match the required 12.5 pF. Characterized with program executing typical data processing. fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency. XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0. Active mode supply current when program executes in flash at a nominal supply voltage of 3 V. Active mode supply current when program executes in RAM at a nominal supply voltage of 3 V. Specifications Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 www.ti.com 5.5 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 Low-Power Mode Supply Currents (Into VCC) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) TEMPERATURE (TA) PARAMETER VCC PMMCOREVx –40°C TYP ILPM0,1MHz Low-power mode 0 (3) (4) ILPM2 Low-power mode 2 (5) (4) ILPM3,XT1LF ILPM3,XT1LF ILPM3,VLO ILPM4 Low-power mode 3, crystal mode (6) (4) Low-power mode 3, crystal mode (6) (4) Low-power mode 3, VLO mode (7) (4) Low-power mode 4 (8) ILPM3.5 Low-power mode 3.5, RTC active on AUXVCC3 (9) ILPM4.5 Low-power mode 4.5 (10) TYP 85°C MAX TYP 105 100 2.2 V 0 70 75 3V 3 81 87 2.2 V 0 5.9 6.5 3V 3 6.7 7.3 0 1.50 2.0 7.8 1 1.65 2.2 8.3 2 1.80 2.4 8.6 3 1.84 2.4 8.6 0 2.0 2.5 8.5 1 2.1 2.7 9.0 2 2.3 2.9 9.3 3 2.3 2.9 9.3 0 1.3 1.7 7.5 1 1.3 1.8 7.9 2 1.4 1.9 8.2 3 1.4 1.9 8.2 0 1.2 1.6 7.4 1 1.2 1.7 7.8 2 1.3 1.7 7.9 3 2.2 V 3V 3V (4) 25°C MAX 3V UNIT MAX 86 130 12.5 18 13.8 30 µA µA µA µA 25 µA 25.0 µA 1.3 1.7 8.0 2.2 V 0.7 0.9 1.4 23.0 3V 1.0 1.2 1.5 1.8 3.0 3V 0.6 0.7 1.0 1.2 2.0 µA µA (1) (2) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are chosen to closely match the required 12.5 pF. (3) Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz (4) Current for brownout and high-side supervisor (SVSH) normal mode included. Low-side supervisor (SVSL) and low-side monitor (SVML) disabled. High-side monitor (SVMH) disabled. RAM retention enabled. (5) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz, DCO setting = 1 MHz operation, DCO bias generator enabled. (6) Current for watchdog timer and RTC clocked by low-frequency clock included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz (7) Current for watchdog timer and RTC clocked by low-frequency clock included. ACLK = VLO. CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz (8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz (9) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC active on AUXVCC3 supply (10) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 0 Hz, PMMREGOFF = 1 Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 Copyright © 2012–2018, Texas Instruments Incorporated 29 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 5.6 www.ti.com Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) TEMPERATURE (TA) PARAMETER VCC PMMCOREVx –40°C TYP ILPM3 LCD, ext. bias ILPM3 LCD, int. bias Low-power mode 3 (LPM3) current, LCD 4-mux mode, external biasing (3) (4) Low-power mode 3 (LPM3) current, LCD 4-mux mode, internal biasing, charge pump disabled (3) (5) 3V 3V 2.2 V ILPM3 LCD,CP (1) (2) (3) (4) (5) (6) 30 Low-power mode 3 (LPM3) current, LCD 4-mux mode, internal biasing, charge pump enabled (3) (6) 3V 25°C MAX TYP 85°C MAX TYP 0 2.5 3.1 9.1 1 2.6 3.3 9.5 2 2.8 3.5 9.9 3 2.8 3.5 0 2.9 3.5 9.7 1 3.1 3.7 10.1 2 3.2 4.0 10.5 3 3.3 4.0 0 2.2 2.8 8.8 1 2.3 3.0 9.1 2 2.5 3.2 9.5 0 2.6 3.2 9.3 1 2.8 3.4 9.7 2 2.9 3.6 10.1 3 3.0 3.7 10.2 6.0 5.5 10.0 10.5 UNIT MAX µA 25.0 µA 25.0 µA All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are chosen to closely match the required 12.5 pF. Current for watchdog timer and RTC clocked by ACLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz Current for brownout, high-side supervisor (SVSH) normal mode included. Low-side supervisor and monitors disabled (SVSL, SVML). High-side monitor (SVMH) disabled. RAM retention enabled. LCDMx = 11 (4-mux mode), LCDREXT = 1, LCDEXTBIAS = 1 (external biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz) Current through external resistors not included (voltage levels are supplied by test equipment). Even segments S0, S2, ... = 0, odd segments S1, S3, ... = 1. No LCD panel load. LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz) Even segments S0, S2, ... = 0, odd segments S1, S3, ... = 1. No LCD panel load. LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge pump enabled), VLCDx = 1000 (VLCD = 3 V, typical), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz) Even segments S0, S2, ... = 0, odd segments S1, S3, ... = 1. No LCD panel load. Specifications Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 www.ti.com 5.7 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 Thermal Packaging Characteristics THERMAL METRIC (1) (2) RθJA Junction-to-ambient thermal resistance, still air RθJC(TOP) Junction-to-case (top) thermal resistance RθJC(BOTTOM) Junction-to-case (bottom) thermal resistance RθJB Junction-to-board thermal resistance ΨJT Junction-to-package-top thermal characterization parameter ΨJB Junction-to-board thermal characterization parameter (1) (2) (3) VALUE LQFP 128 (PEU) 44.4 LQFP 100 (PZ) 42.9 LQFP 128 (PEU) 10.5 LQFP 100 (PZ) 9.3 LQFP 128 (PEU) N/A (3) LQFP 100 (PZ) N/A LQFP 128 (PEU) 23.1 LQFP 100 (PZ) 20.6 LQFP 128 (PEU) 0.4 LQFP 100 (PZ) 0.3 LQFP 128 (PEU) 22.8 LQFP 100 (PZ) 20.3 UNIT °C/W °C/W °C/W °C/W °C/W °C/W For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics. These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RθJC] value, which is based on a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards: • JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air) • JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages • JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages • JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements N/A = not applicable Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 Copyright © 2012–2018, Texas Instruments Incorporated 31 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 5.8 www.ti.com Schmitt-Trigger Inputs – General-Purpose I/O over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VIT+ Positive-going input threshold voltage VIT– Negative-going input threshold voltage Vhys Input voltage hysteresis (VIT+ – VIT–) RPull Pullup or pulldown resistor (1) For pullup: VIN = VSS, For pulldown: VIN = VCC CI Input capacitance VIN = VSS or VCC (1) VCC MIN 1.8 V 0.80 1.40 3V 1.50 2.10 1.8 V 0.45 1.00 3V 0.75 1.65 1.8 V 0.3 0.85 3V 0.4 1.0 20 TYP 35 MAX UNIT V V V 50 kΩ 5 pF Also applies to RST pin when pullup or pulldown resistor is enabled. Inputs – Ports P1 and P2 (1) 5.9 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER External interrupt timing (2) t(int) (1) (2) TEST CONDITIONS VCC Port P1 and P2: P1.x to P2.x, external trigger pulse duration to set interrupt flag 2.2 V, 3 V MIN MAX UNIT 20 ns Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions. An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals shorter than t(int). 5.10 Leakage Current – General-Purpose I/O over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER Ilkg(Px.y) (1) (2) 32 High-impedance leakage current TEST CONDITIONS See (1) (2) VCC MIN MAX UNIT 1.8 V, 3 V –50 +50 nA The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is disabled. Specifications Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 www.ti.com SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 5.11 Outputs – General-Purpose I/O (Full Drive Strength) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (also see Figure 5-6 through Figure 5-9) PARAMETER TEST CONDITIONS VCC I(OHmax) = –3 mA (1) VOH High-level output voltage 1.8 V I(OHmax) = –10 mA (1) I(OHmax) = –5 mA (1) 3V I(OHmax) = –15 mA (1) I(OLmax) = 3 mA (2) VOL Low-level output voltage I(OLmax) = 10 mA 1.8 V (3) I(OLmax) = 5 mA (2) 3V I(OLmax) = 15 mA (3) (1) (2) (3) MIN MAX 1.55 1.80 1.20 1.80 2.75 3.00 2.40 3.00 0.00 0.25 0.00 0.60 0.00 0.25 0.00 0.60 UNIT V V The maximum total current, I(OHmax), for all outputs combined should not exceed ±20 mA to hold the maximum voltage drop specified. See Section 5.3 for more details. The maximum total current, I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop specified. The maximum total current, I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage drop specified. 5.12 Outputs – General-Purpose I/O (Reduced Drive Strength) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (also see Figure 5-2 through Figure 5-5) PARAMETER TEST CONDITIONS I(OHmax) = –1 mA VOH High-level output voltage VCC (2) 1.8 V I(OHmax) = –3 mA (2) I(OHmax) = –2 mA (2) 3V I(OHmax) = –6 mA (2) I(OLmax) = 1 mA VOL Low-level output voltage (3) 1.8 V I(OLmax) = 3 mA (4) I(OLmax) = 2 mA (3) 3V I(OLmax) = 6 mA (4) (1) (2) (3) (4) MIN MAX 1.55 1.80 1.20 1.80 2.75 3.00 2.40 3.00 0.00 0.25 0.00 0.60 0.00 0.25 0.00 0.60 UNIT V V Selecting reduced drive strength may reduce EMI. The maximum total current, I(OHmax), for all outputs combined should not exceed ±20 mA to hold the maximum voltage drop specified. See Section 5.3 for more details. The maximum total current, I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop specified. The maximum total current, I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage drop specified. 5.13 Output Frequency – General-Purpose I/O over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fPx.y Port output frequency (with load) fPort_CLK (1) (2) Clock output frequency TEST CONDITIONS See (1) (2) ACLK, SMCLK, or MCLK, CL = 20 pF (2) MIN MAX VCC = 1.8 V, PMMCOREVx = 0 16 VCC = 3 V, PMMCOREVx = 3 25 VCC = 1.8 V, PMMCOREVx = 0 16 VCC = 3 V, PMMCOREVx = 3 25 UNIT MHz MHz A resistive divider with 2 × R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For full drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency. Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 Copyright © 2012–2018, Texas Instruments Incorporated 33 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 5.14 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) 8 20 18 7 IOL – Low-Level Output Current – mA IOL – Low-Level Output Current – mA TA = 25°C 16 TA = 85°C 14 12 10 8 6 4 TA = 25°C 6 TA = 85°C 5 4 3 2 1 2 0 0 0 0.5 1 1.5 2 2.5 0 3 0.2 VOL – Low-Level Output Voltage – V 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOL – Low-Level Output Voltage – V Figure 5-2. Typical Low-Level Output Current vs Low-Level Output Voltage Figure 5-3. Typical Low-Level Output Current vs Low-Level Output Voltage 0 0 -5 IOH – High-Level Output Current – mA IOH – High-Level Output Current – mA -1 -10 -15 TA = 85°C -20 TA = 25°C -2 -3 -4 -5 TA = 85°C -6 -7 TA = 25°C -8 -25 0 0.5 1 1.5 2 2.5 VOH – High-Level Output Voltage – V Figure 5-4. Typical High-Level Output Current vs High-Level Output Voltage 34 Specifications 3 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOH – High-Level Output Voltage – V Figure 5-5. Typical High-Level Output Current vs High-Level Output Voltage Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 www.ti.com SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 5.15 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) 60 25 IOL – Low-Level Output Current – mA IOL – Low-Level Output Current – mA 50 TA = 25°C TA = 85°C 40 30 20 10 0 20 TA = 25°C TA = 85°C 15 10 5 0 0 0.5 1 1.5 2 2.5 3 0 0.2 VOL – Low-Level Output Voltage – V 0.6 0.8 1 1.2 1.4 1.6 1.8 VOL – Low-Level Output Voltage – V Figure 5-6. Typical Low-Level Output Current vs Low-Level Output Voltage Figure 5-7. Typical Low-Level Output Current vs Low-Level Output Voltage 0 0 IOH – High-Level Output Current – mA -10 IOH – High-Level Output Current – mA 0.4 -20 -30 -40 TA = 85°C -50 -5 -10 -15 TA = 85°C -20 TA = 25°C TA = 25°C -60 -25 0 0.5 1 1.5 2 2.5 VOH – High-Level Output Voltage – V Figure 5-8. Typical High-Level Output Current vs High-Level Output Voltage 3 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 Figure 5-9. Typical High-Level Output Current vs High-Level Output Voltage Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 Copyright © 2012–2018, Texas Instruments Incorporated 1.8 VOH – High-Level Output Voltage – V 35 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 5.16 Crystal Oscillator, XT1, Low-Frequency Mode (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER ΔIDVCC.LF Differential XT1 oscillator crystal current consumption from lowest drive setting, LF mode TEST CONDITIONS VCC MIN fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1, TA = 25°C fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 2, TA = 25°C 3V 0.170 0.290 XTS = 0, XT1BYPASS = 0 32768 XT1 oscillator crystal frequency, LF mode fXT1,LF,SW XT1 oscillator logic-level square-wave input frequency, XTS = 0, XT1BYPASS = 1 (2) LF mode OALF Oscillation allowance for LF crystals (4) (3) 10 fFault,LF tSTART,LF 210 XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1, fXT1,LF = 32768 Hz, CL,eff = 12 pF 300 (1) (2) (3) (4) (5) (6) (7) (8) 36 XTS = 0, XCAPx = 2 8.5 XTS = 0, XCAPx = 3 12.0 Oscillator fault frequency, LF mode (7) XTS = 0 (8) fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0, TA = 25°C, CL,eff = 6 pF fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 3, TA = 25°C, CL,eff = 12 pF µA Hz 50 kHz 1 5.5 Duty cycle, LF mode UNIT kΩ XTS = 0, XCAPx = 1 XTS = 0, Measured at ACLK, fXT1,LF = 32768 Hz Start-up time, LF mode 32.768 XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0, fXT1,LF = 32768 Hz, CL,eff = 6 pF XTS = 0, XCAPx = 0 (6) CL,eff MAX 0.075 fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 3, TA = 25°C fXT1,LF0 Integrated effective load capacitance, LF mode (5) TYP pF 30% 70% 10 10000 Hz 1000 3V ms 500 To improve EMI on the XT1 oscillator, the following guidelines should be observed. • Keep the trace between the device and the crystal as short as possible. • Design a good ground plane around the oscillator pins. • Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. • Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. • Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins. • If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins. When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in the Schmitt-trigger Inputs section of this data sheet. Maximum frequency of operation of the entire device cannot be exceeded. Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following guidelines, but should be evaluated based on the actual crystal selected for the application: • For XT1DRIVEx = 0, CL,eff ≤ 6 pF. • For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF. • For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF. • For XT1DRIVEx = 3, CL,eff ≥ 6 pF. Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal. Requires external capacitors at both terminals. Values are specified by crystal manufacturers. Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX might set the flag. Measured with logic-level input frequency but also applies to operation with crystals. Specifications Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 www.ti.com SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 5.17 Internal Very-Low-Power Low-Frequency Oscillator (VLO) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC fVLO VLO frequency Measured at ACLK 1.8 V to 3.6 V dfVLO/dT VLO frequency temperature drift Measured at ACLK 1.8 V to 3.6 V Measured at ACLK 1.8 V to 3.6 V Measured at ACLK 1.8 V to 3.6 V dfVLO/dVCC VLO frequency supply voltage drift Duty cycle MIN TYP MAX 6 9.6 15 0.5 kHz %/°C 4 40% UNIT %/V 50% 60% TYP MAX 5.18 Internal Reference, Low-Frequency Oscillator (REFO) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER IREFO fREFO TEST CONDITIONS VCC MIN REFO oscillator current consumption TA = 25°C 1.8 V to 3.6 V REFO frequency calibrated Measured at ACLK 1.8 V to 3.6 V Full temperature range 1.8 V to 3.6 V –3.5% +3.5% 3V –1.5% +1.5% REFO absolute tolerance calibrated TA = 25°C 3 REFO frequency temperature drift Measured at ACLK 1.8 V to 3.6 V 0.01 dfREFO/dVCC REFO frequency supply voltage drift Measured at ACLK 1.8 V to 3.6 V 1.0 Duty cycle Measured at ACLK 1.8 V to 3.6 V REFO start-up time 40%/60% duty cycle 1.8 V to 3.6 V tSTART µA 32768 dfREFO/dT 40% 50% Hz %/°C %/V 60% 25 Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 Copyright © 2012–2018, Texas Instruments Incorporated UNIT µs 37 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 5.19 DCO Frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-10) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT fDCO(0,0) DCO frequency (0, 0) DCORSELx = 0, DCOx = 0, MODx = 0 0.07 0.20 MHz fDCO(0,31) DCO frequency (0, 31) (1) DCORSELx = 0, DCOx = 31, MODx = 0 0.70 1.70 MHz fDCO(1,0) DCO frequency (1, 0) (1) DCORSELx = 1, DCOx = 0, MODx = 0 0.15 0.36 MHz fDCO(1,31) DCO frequency (1, 31) (1) DCORSELx = 1, DCOx = 31, MODx = 0 1.47 3.45 MHz (1) fDCO(2,0) DCO frequency (2, 0) DCORSELx = 2, DCOx = 0, MODx = 0 0.32 0.75 MHz fDCO(2,31) DCO frequency (2, 31) (1) DCORSELx = 2, DCOx = 31, MODx = 0 3.17 7.38 MHz fDCO(3,0) DCO frequency (3, 0) (1) DCORSELx = 3, DCOx = 0, MODx = 0 0.64 1.51 MHz (1) fDCO(3,31) DCO frequency (3, 31) DCORSELx = 3, DCOx = 31, MODx = 0 6.07 14.0 MHz fDCO(4,0) DCO frequency (4, 0) (1) DCORSELx = 4, DCOx = 0, MODx = 0 1.3 3.2 MHz fDCO(4,31) DCO frequency (4, 31) (1) DCORSELx = 4, DCOx = 31, MODx = 0 12.3 28.2 MHz (1) fDCO(5,0) DCO frequency (5, 0) DCORSELx = 5, DCOx = 0, MODx = 0 2.5 6.0 MHz fDCO(5,31) DCO frequency (5, 31) (1) DCORSELx = 5, DCOx = 31, MODx = 0 23.7 54.1 MHz fDCO(6,0) DCO frequency (6, 0) (1) DCORSELx = 6, DCOx = 0, MODx = 0 4.6 10.7 MHz fDCO(6,31) DCO frequency (6, 31) (1) DCORSELx = 6, DCOx = 31, MODx = 0 39.0 88.0 MHz (1) fDCO(7,0) DCO frequency (7, 0) DCORSELx = 7, DCOx = 0, MODx = 0 8.5 19.6 MHz fDCO(7,31) DCO frequency (7, 31) (1) DCORSELx = 7, DCOx = 31, MODx = 0 60 135 MHz SDCORSEL Frequency step between range DCORSEL and DCORSEL + 1 SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO) 1.2 2.3 ratio SDCO Frequency step between tap DCO and DCO + 1 SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO) 1.02 1.12 ratio Duty cycle Measured at SMCLK 40% dfDCO/dT DCO frequency temperature drift fDCO = 1 MHz 0.1 %/°C dfDCO/ dVCORE DCO frequency voltage drift fDCO = 1 MHz 1.9 %/V (1) 50% 60% When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within the range of fDCO(n, 0),MAX ≤ fDCO ≤ fDCO(n, 31),MIN, where fDCO(n, 0),MAX represents the maximum frequency specified for the DCO frequency, range n, tap 0 (DCOx = 0) and fDCO(n,31),MIN represents the minimum frequency specified for the DCO frequency, range n, tap 31 (DCOx = 31). This ensures that the target DCO frequency resides within the range selected. It should also be noted that if the actual fDCO frequency for the selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the selected range is at its minimum or maximum tap setting. 100 VCC = 3.0 V TA = 25°C fDCO – MHz 10 DCOx = 31 1 0.1 DCOx = 0 0 1 2 3 4 5 6 7 DCORSEL Figure 5-10. Typical DCO Frequency 38 Specifications Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 www.ti.com SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 5.20 PMM, Brownout Reset (BOR) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS V(DVCC_BOR_IT–) BORH on voltage, DVCC falling level | dDVCC/dt | < 3 V/s V(DVCC_BOR_IT+) BORH off voltage, DVCC rising level | dDVCC/dt | < 3 V/s V(DVCC_BOR_hys) BORH hysteresis tRESET Pulse duration required at RST/NMI pin to accept a reset MIN TYP 0.80 1.20 50 MAX UNIT 1.45 V 1.50 V 250 mV 2 µs 5.21 PMM, Core Voltage over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCORE3(AM) Core voltage, active mode, PMMCOREV = 3 2.4 V ≤ DVCC ≤ 3.6 V 1.91 V VCORE2(AM) Core voltage, active mode, PMMCOREV = 2 2.2 V ≤ DVCC ≤ 3.6 V 1.81 V VCORE1(AM) Core voltage, active mode, PMMCOREV = 1 2 V ≤ DVCC ≤ 3.6 V 1.61 V VCORE0(AM) Core voltage, active mode, PMMCOREV = 0 1.8 V ≤ DVCC ≤ 3.6 V 1.41 V VCORE3(LPM) Core voltage, low-current mode, PMMCOREV = 3 2.4 V ≤ DVCC ≤ 3.6 V 1.94 V VCORE2(LPM) Core voltage, low-current mode, PMMCOREV = 2 2.2 V ≤ DVCC ≤ 3.6 V 1.92 V VCORE1(LPM) Core voltage, low-current mode, PMMCOREV = 1 2 V ≤ DVCC ≤ 3.6 V 1.73 V VCORE0(LPM) Core voltage, low-current mode, PMMCOREV = 0 1.8 V ≤ DVCC ≤ 3.6 V 1.52 V Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 Copyright © 2012–2018, Texas Instruments Incorporated 39 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 5.22 PMM, SVS High Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN SVSHE = 0, DVCC = 3.6 V I(SVSH) SVS current consumption V(SVSH_IT+) SVSH on voltage level SVSH off voltage level tpd(SVSH) SVSH propagation delay t(SVSH) SVSH on or off delay time dVDVCC/dt DVCC rise time MAX 0 SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0 1.5 µA SVSHE = 1, SVSHRVL = 0 1.60 1.65 1.75 SVSHE = 1, SVSHRVL = 1 1.77 1.84 1.95 SVSHE = 1, SVSHRVL = 2 1.93 2.00 2.12 SVSHE = 1, SVSHRVL = 3 2.09 2.16 2.29 SVSHE = 1, SVSMHRRL = 0 1.65 1.75 1.85 SVSHE = 1, SVSMHRRL = 1 1.85 1.95 2.05 SVSHE = 1, SVSMHRRL = 2 2.05 2.15 2.25 SVSHE = 1, SVSMHRRL = 3 2.15 2.25 2.35 SVSHE = 1, SVSMHRRL = 4 2.30 2.40 2.55 SVSHE = 1, SVSMHRRL = 5 2.57 2.70 2.83 SVSHE = 1, SVSMHRRL = 6 2.90 3.05 3.20 SVSHE = 1, SVSMHRRL = 7 2.90 3.05 3.20 SVSHE = 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1 2.5 SVSHE = 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0 20 SVSHE = 0 → 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1 12.5 SVSHE = 0 → 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0 100 0 UNIT nA 200 SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1 V(SVSH_IT–) TYP V V µs µs 1000 V/s MAX UNIT 5.23 PMM, SVM High Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN SVMHE = 0, DVCC = 3.6 V I(SVMH) SVMH current consumption 0 SVMHE = 1, DVCC = 3.6 V, SVMHFP = 0 SVMH on or off voltage level (1) t(SVMH) (1) 40 SVMH propagation delay SVMH on or off delay time 1.5 µA SVMHE = 1, SVSMHRRL = 0 1.63 1.73 1.83 SVMHE = 1, SVSMHRRL = 1 1.83 1.93 2.03 SVMHE = 1, SVSMHRRL = 2 2.03 2.13 2.23 SVMHE = 1, SVSMHRRL = 3 2.13 2.23 2.33 SVMHE = 1, SVSMHRRL = 4 2.28 2.40 2.53 SVMHE = 1, SVSMHRRL = 5 2.55 2.70 2.81 SVMHE = 1, SVSMHRRL = 6 2.88 3.02 3.18 SVMHE = 1, SVSMHRRL = 7 2.88 3.02 3.18 SVMHE = 1, SVMHOVPE = 1 tpd(SVMH) nA 200 SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1 V(SVMH) TYP V 3.77 SVMHE = 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1 2.5 SVMHE = 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0 20 SVMHE = 0 → 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1 12.5 SVMHE = 0 → 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0 100 µs µs The SVMH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide on recommended settings and use. Specifications Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 www.ti.com SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 5.24 PMM, SVS Low Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN SVSLE = 0, PMMCOREV = 2 I(SVSL) SVSL current consumption tpd(SVSL) SVSL propagation delay t(SVSL) SVSL on or off delay time TYP MAX 0 SVSLE = 1, PMMCOREV = 2, SVSLFP = 0 200 SVSLE = 1, PMMCOREV = 2, SVSLFP = 1 1.5 SVSLE = 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1 2.5 SVSLE = 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0 20 SVSLE = 0 → 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1 12.5 SVSLE = 0 → 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0 100 UNIT nA µA µs µs 5.25 PMM, SVM Low Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN SVMLE = 0, PMMCOREV = 2 I(SVML) SVML current consumption tpd(SVML) SVML propagation delay t(SVML) SVML on or off delay time TYP MAX 0 SVMLE = 1, PMMCOREV = 2, SVMLFP = 0 200 SVMLE = 1, PMMCOREV = 2, SVMLFP = 1 1.5 SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1 2.5 SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0 20 SVMLE = 0 → 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1 12.5 SVMLE = 0 → 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0 100 UNIT nA µA µs µs 5.26 Wake-up Times From Low-Power Modes and Reset over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS tWAKE-UP-FAST Wake-up time from LPM2, LPM3, or LPM4 to active mode (1) PMMCOREV = SVSMLRRL = n fMCLK ≥ 4.0 MHz (where n = 0, 1, 2, or 3), fMCLK < 4.0 MHz SVSLFP = 1 tWAKE-UP-SLOW Wake-up time from LPM2, LPM3, or LPM4 to active mode (2) (3) PMMCOREV = SVSMLRRL = n (where n = 0, 1, 2, or 3), SVSLFP = 0 tWAKE-UP-LPM4.5 tWAKE-UP-RESET (1) (2) (3) (4) MIN TYP MAX UNIT 5 10 µs 150 165 µs Wake-up time from LPM4.5 to active mode (4) 2 3 ms Wake-up time from RST or BOR event to active mode (4) 2 3 ms This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-FAST is possible with SVSL and SVML in full performance mode or disabled. For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode Selection section in the Power Management Module and Supply Voltage Supervisor chapter of the MSP430x5xx and MSP430x6xx Family User's Guide. This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-SLOW is set with SVSL and SVML in normal mode (low current mode). For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode Selection section in the Power Management Module and Supply Voltage Supervisor chapter of the MSP430x5xx and MSP430x6xx Family User's Guide. The wake-up times from LPM0 and LPM1 to AM are not specified. They are proportional to MCLK cycle time but are not affected by the performance mode settings as for LPM2, LPM3, and LPM4. This value represents the time from the wake-up event to the reset vector execution. Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 Copyright © 2012–2018, Texas Instruments Incorporated 41 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 5.27 Auxiliary Supplies Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VCC MAX Supply voltage range for all supplies at pins DVCC, AVCC, AUXVCC1, AUXVCC2, AUXVCC3 1.8 3.6 PMMCOREVx = 0 1.8 3.6 PMMCOREVx = 1 2.0 3.6 PMMCOREVx = 2 2.2 3.6 PMMCOREVx = 3 2.4 3.6 Digital system supply voltage range, VDSYS = VCC – RON × ILOAD VDSYS NOM See module specifications UNIT V V VASYS Analog system supply voltage range, VASYS = VCC – RON × ILOAD TA Ambient temperature range TA,HTOL Ambient temperature during HTOL (module should be functional during HTOL) CVCC, CAUX1/2 Recommended capacitor at pins DVCC, AVCC, AUXVCC1, AUXVCC2 CVSYS Recommended capacitor at pins VDSYS1, VDSYS2 and VASYS1, VASYS2 CVCORE Recommended capacitance at pin VCORE CAUX3 Recommended capacitor at pin AUXVCC3 0.47 µF –40 V 85 °C 150 °C 4.7 µF 4.7 µF 0.47 µF 5.28 Auxiliary Supplies, AUXVCC3 (Backup Subsystem) Currents over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IAUX3,RTCon AUXVCC3 current with RTC enabled RTC and 32-kHz oscillator in backup subsystem enabled 3V IAUX3,RTCoff AUXVCC3 current with RTC disabled RTC and 32-kHz oscillator in backup subsystem disabled 3V TA MIN MAX 25°C 0.86 85°C 1.2 25°C 120 85°C 220 UNIT µA nA 5.29 Auxiliary Supplies, Auxiliary Supply Monitor over operating free-air temperature range (unless otherwise noted) PARAMETER MAX UNIT ICC,Monitor Average supply current for monitoring circuitry drawn from VDSYS LOCKAUX = 0, AUXMRx = 0 AUX0MD = 0, AUX1MD = 0, AUX2MD = 1, VDSYS = DVCC, VASYS = AVCC, Current measured at VDSYS TEST CONDITIONS 1.10 µA IMeas,Montior Average current drawn from monitored supply during measurement cycle LOCKAUX = 0, AUXMRx = 0 AUX0MD = 0, AUX1MD = 0, AUX2MD = 1, VDSYS = DVCC, VASYS = AVCC, Current measured at AUXVCC1 0.13 µA General MIN VSVMH (SVSMHRRLx = AUXLVLx) TYP VSVMH (SVSMHRRLx = AUXLVLx) X – 5% VMonitor 42 Auxiliary supply threshold level (same as high-side SVM) Specifications VSVMH (SVSMHRRLx = AUXLVLx) X + 5% AUXLVLx = 0 1.65 1.75 1.85 AUXLVLx = 1 1.85 1.95 2.05 AUXLVLx = 2 2.05 2.15 2.25 AUXLVLx = 3 2.15 2.25 2.35 AUXLVLx = 4 2.30 2.40 2.55 AUXLVLx = 5 2.57 2.70 2.83 AUXLVLx = 6 2.90 3.00 3.20 AUXLVLx = 7 2.90 3.00 3.20 V Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 www.ti.com SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 5.30 Auxiliary Supplies, Switch ON-Resistance over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT RON,DVCC ON-resistance of switch between DVCC and VDSYS ILOAD = ICORE + IIO = 10 mA + 10 mA = 20 mA 5 Ω RON,DAUX1 ON-resistance of switch between AUXVCC1 and VDSYS ILOAD = ICORE + IIO = 10 mA + 10 mA = 20 mA 5 Ω RON,DAUX2 ON-resistance of switch between AUXVCC2 and VDSYS ILOAD = ICORE + IIO = 10 mA + 10 mA = 20 mA 5 Ω RON,AVCC ON-resistance of switch between AVCC and VASYS ILOAD = IModules = 10 mA 5 Ω RON,AAUX1 ON-resistance of switch between AUXVCC1 and VASYS ILOAD = IModules = 5 mA 20 Ω RON,AAUX2 ON-resistance of switch between AUXVCC2 and VASYS ILOAD = IModules = 5 mA 20 Ω 5.31 Auxiliary Supplies, Switching Time over operating free-air temperature range (unless otherwise noted) PARAMETER MIN tSwitch Time from occurrence of trigger (SVM or software) to "new" supply connected to system supplies tRecover "Recovery time" after a switch over took place. During that time no further switching takes place. MAX UNIT 100 ns 480 µs 170 5.32 Auxiliary Supplies, Switch Leakage over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS ISW,Lkg Current into DVCC, AVCC, AUXVCC1, or AUXVCC2 if not selected IVmax Current drawn from highest supply MIN Per supply (but not the highest supply) TYP MAX UNIT 75 250 nA 500 700 nA UNIT 5.33 Auxiliary Supplies, Auxiliary Supplies to ADC10_A over operating free-air temperature range (unless otherwise noted) PARAMETER V3 RV3 tSample,V3 TEST CONDITIONS Supply voltage divider, V3 = VSupply/3 Load resistance Sampling time required if V3 selected VCC MIN TYP MAX 1.8 V 0.57 0.6 0.63 3V 0.95 1.0 1.05 3.6 V 1.14 1.2 1.26 AUXADCRx = 0 15 AUXADCRx = 1 1.5 AUXADCRx = 2 0.6 Error of conversion result ≤ 1 LSB AUXADCRx = 0 1000 AUXADCRx = 1 1000 AUXADCRx = 2 1000 V kΩ ns 5.34 Auxiliary Supplies, Charge Limiting Resistor over operating free-air temperature range (unless otherwise noted) PARAMETER RCHARGE Charge limiting resistor TEST CONDITIONS VCC MIN TYP MAX AUXCHCx = 1 3V 5 AUXCHCx = 2 3V 10 AUXCHCx = 3 3V 20 Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 Copyright © 2012–2018, Texas Instruments Incorporated UNIT kΩ 43 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 5.35 Timer_A over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN fTA Timer_A input clock frequency Internal: SMCLK or ACLK, External: TACLK, Duty cycle = 50% ±10% 1.8 V, 3 V tTA,cap Timer_A capture timing All capture inputs, minimum pulse duration required for capture 1.8 V, 3 V MAX UNIT 25 MHz 20 ns 5.36 eUSCI (UART Mode) Clock Frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER feUSCI TEST CONDITIONS MIN Internal: SMCLK or ACLK, External: UCLK, Duty cycle = 50% ±10% eUSCI input clock frequency fBITCLK BITCLK clock frequency (equals baud rate in MBaud) MAX UNIT fSYSTEM MHz 5 MHz 5.37 eUSCI (UART Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC UCGLITx = 0 tt UART receive deglitch time (1) UCGLITx = 1 UCGLITx = 2 UCGLITx = 3 (1) 44 2 V, 3 V MIN TYP MAX 10 15 25 30 50 85 50 80 150 70 120 200 UNIT ns Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To make sure that pulses are correctly recognized, their duration should exceed the maximum specification of the deglitch time. Specifications Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 www.ti.com SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 5.38 eUSCI (SPI Master Mode) Clock Frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER feUSCI TEST CONDITIONS MIN Internal: SMCLK or ACLK, Duty cycle = 50% ±10% eUSCI input clock frequency MAX UNIT fSYSTEM MHz MAX UNIT 5.39 eUSCI (SPI Master Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER tSTE,LEAD STE lead time, STE low to clock tSTE,LAG STE lag time, Last clock to STE high TEST CONDITIONS VCC MIN UCSTEM = 0, UCMODEx = 01 or 10 2 V, 3 V 150 UCSTEM = 1, UCMODEx = 01 or 10 2 V, 3 V 150 UCSTEM = 0, UCMODEx = 01 or 10 2 V, 3 V 200 UCSTEM = 1, UCMODEx = 01 or 10 2 V, 3 V 200 UCSTEM = 0, UCMODEx = 01 or 10 tSTE,ACC STE access time, STE low to SIMO data out UCSTEM = 1, UCMODEx = 01 or 10 UCSTEM = 0, UCMODEx = 01 or 10 tSTE,DIS STE disable time, STE high to SIMO high impedance UCSTEM = 1, UCMODEx = 01 or 10 tSU,MI SOMI input data setup time tHD,MI SOMI input data hold time tVALID,MO SIMO output data valid time (2) UCLK edge to SIMO valid, CL = 20 pF tHD,MO SIMO output data hold time (3) CL = 20 pF (1) (2) (3) ns ns 2V 50 3V 30 2V 50 3V 30 2V 40 3V 25 2V 40 3V ns ns 25 2V 50 3V 30 2V 0 3V 0 ns ns 2V 9 3V 5 2V 0 3V 0 ns ns fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)) For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave. Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams in Figure 5-11 and Figure 5-12. Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 511 and Figure 5-12. 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tLOW/HIGH tSU,MI tHD,MI SOMI tVALID,MO SIMO Figure 5-11. SPI Master Mode, CKPH = 0 Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 Copyright © 2012–2018, Texas Instruments Incorporated 45 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tLOW/HIGH tHD,MI tSU,MI SOMI tVALID,MO SIMO Figure 5-12. SPI Master Mode, CKPH = 1 5.40 eUSCI (SPI Slave Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TEST CONDITIONS tSTE,LEAD STE lead time, STE low to clock tSTE,LAG STE lag time, Last clock to STE high tSTE,ACC STE access time, STE low to SOMI data out tSTE,DIS STE disable time, STE high to SOMI high impedance tSU,SI SIMO input data setup time tHD,SI SIMO input data hold time tVALID,SO SOMI output data valid time (2) UCLK edge to SOMI valid, CL = 20 pF tHD,SO SOMI output data hold time (3) CL = 20 pF (1) (2) (3) 46 VCC MIN 2V 4 3V 3 2V 0 3V 0 MAX ns ns 2V 46 3V 24 2V 38 3V 25 2V 2 3V 1 2V 2 3V 2 55 32 3V 16 ns ns 3V 24 ns ns 2V 2V UNIT ns ns fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)) For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master. Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams in Figure 5-13 and Figure 5-14. Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-13 and Figure 5-14. Specifications Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 www.ti.com SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 UCMODEx = 01 tSTE,LEAD STE tSTE,LAG UCMODEx = 10 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tSU,SIMO tLOW/HIGH tHD,SIMO SIMO tVALID,SOMI tACC tDIS SOMI Figure 5-13. SPI Slave Mode, CKPH = 0 tSTE,LAG tSTE,LEAD STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tLOW/HIGH tHD,SI tSU,SI SIMO tACC tVALID,SO tDIS SOMI Figure 5-14. SPI Slave Mode, CKPH = 1 Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 Copyright © 2012–2018, Texas Instruments Incorporated 47 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 5.41 eUSCI (I2C Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-15) PARAMETER feUSCI eUSCI input clock frequency fSCL SCL clock frequency tHD,STA Hold time (repeated) START tSU,STA Setup time for a repeated START tHD,DAT Data hold time TEST CONDITIONS VCC 2 V, 3 V fSCL = 100 kHz 2 V, 3 V fSCL > 100 kHz fSCL = 100 kHz 2 V, 3 V fSCL > 100 kHz 2 V, 3 V Data setup time tSU,STO Setup time for STOP 2 V, 3 V fSCL > 100 kHz fSCL = 100 kHz 2 V, 3 V fSCL > 100 kHz UCGLITx = 0 tSP TYP Internal: SMCLK or ACLK, External: UCLK, Duty cycle = 50% ±10% fSCL = 100 kHz tSU,DAT MIN Pulse duration of spikes suppressed by input filter UCGLITx = 1 2 V, 3 V UCGLITx = 2 UCGLITx = 3 0 Clock low time-out MHz 400 kHz µs 1.5 5.1 µs 1.4 0.4 µs 5.0 µs 1.3 5.2 µs 1.7 75 220 35 120 30 60 20 35 2 V, 3 V 33 UCCLTOx = 3 tSU,STA fSYSTEM ns 30 UCCLTOx = 2 tHD,STA UNIT 5.1 UCCLTOx = 1 tTIMEOUT MAX ms 37 tHD,STA tBUF SDA tLOW tHIGH tSP SCL tSU,DAT tSU,STO tHD,DAT Figure 5-15. I2C Mode Timing 48 Specifications Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 www.ti.com SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 5.42 Schmitt-Trigger Inputs, RTC Tamper Detect Pin over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VIT+ Positive-going input threshold voltage VIT– Negative-going input threshold voltage Vhys Input voltage hysteresis (VIT+ – VIT–) RPull Pullup or pulldown resistor For pullup: VIN = VSS For pulldown: VIN = AUXVCC3 CI Input capacitance VIN = VSS or AUXVCC3 AUXVCC3 MIN TYP 1.8 V 0.80 1.40 3V 1.50 2.10 1.8 V 0.45 1.00 3V 0.75 1.65 1.8 V 0.3 0.85 3V 0.4 1.0 20 35 MAX 50 5 UNIT V V V kΩ pF 5.43 Inputs, RTC Tamper Detect Pin (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER t(int) (1) (2) External interrupt timing (2) TEST CONDITIONS Port P1, P2: P1.x to P2.x, external trigger pulse duration to set interrupt flag AUXVCC3 MIN 2.2 V, 3 V 20 MAX UNIT ns Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions. An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals shorter than t(int). 5.44 Leakage Current, RTC Tamper Detect Pin over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER Ilkg(Px.y) (1) (2) TEST CONDITIONS High-impedance leakage current See (1) (2) AUXVCC3 MIN MAX UNIT 1.8 V, 3 V –50 +50 nA The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is disabled. 5.45 Outputs, RTC Tamper Detect Pin over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS I(OHmax) = –100 µA (1) VOH High-level output voltage I(OHmax) = –200 µA (1) I(OHmax) = –100 µA (1) I(OHmax) = –200 µA (1) I(OLmax) = 100 µA VOL Low-level output voltage 1.8 V 3V (1) I(OLmax) = 200 µA (1) I(OLmax) = 100 µA (1) I(OLmax) = 200 µA (1) (1) AUXVCC3 1.8 V 3V MIN MAX 1.50 1.80 1.20 1.80 2.70 3.00 2.40 3.00 0.00 0.25 0.00 0.60 0.00 0.25 0.00 0.60 UNIT V V The maximum total current, I(OHmax), for all outputs combined should not exceed ±20 mA to hold the maximum voltage drop specified. See Section 5.3 for more details. Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 Copyright © 2012–2018, Texas Instruments Incorporated 49 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 5.46 LCD_C Recommended Operating Conditions PARAMETER CONDITIONS MIN VCC,LCD_C,CP en,3.6 Supply voltage range, charge pump enabled, VLCD ≤ 3.6 V LCDCPEN = 1, 0000 < VLCDx ≤ 1111 (charge pump enabled, VLCD ≤ 3.6 V) NOM 2.2 3.6 V VCC,LCD_C,CP en,3.3 Supply voltage range, charge pump enabled, VLCD ≤ 3.3 V LCDCPEN = 1, 0000 < VLCDx ≤ 1100 (charge pump enabled, VLCD ≤ 3.3 V) 2.0 3.6 V VCC,LCD_C,int. bias Supply voltage range, internal biasing, charge pump disabled LCDCPEN = 0, VLCDEXT = 0 2.4 3.6 V VCC,LCD_C,ext. bias Supply voltage range, external biasing, charge pump LCDCPEN = 0, VLCDEXT = 0 disabled 2.4 3.6 V VCC,LCD_C,VLCDEXT Supply voltage range, external LCD voltage, internal or LCDCPEN = 0, VLCDEXT = 1 external biasing, charge pump disabled 2.0 3.6 V VLCDCAP/R33 External LCD voltage at LCDCAP/R33, internal or LCDCPEN = 0, VLCDEXT = 1 external biasing, charge pump disabled 2.4 3.6 V CLCDCAP Capacitor on LCDCAP when charge pump enabled LCDCPEN = 1, VLCDx > 0000 (charge pump enabled) 4.7 10 µF fLCD LCD frequency range fFRAME = 1/(2 × mux) × fLCD with mux = 1 (static) to 8 1024 Hz fFRAME,4mux LCD frame frequency range fFRAME,4mux(MAX) = 1/(2 × 4) × fLCD(MAX) = 1/(2 × 4) × 1024 Hz 128 Hz fFRAME,8mux LCD frame frequency range fFRAME,8mux(MAX) = 1/(2 × 4) × fLCD(MAX) = 1/(2 × 8) × 1024 Hz 64 Hz fACLK,in ACLK input frequency range 40 kHz CPanel Panel capacitance 100-Hz frame frequency VR33 Analog input voltage at R33 LCDCPEN = 0, VLCDEXT = 1 4.7 0 30 32 2.4 MAX UNIT 10000 pF VCC + 0.2 V VR33 V VR23,1/3bias Analog input voltage at R23 LCDREXT = 1, LCDEXTBIAS = 1, LCD2B = 0 VR13 VR03 + 2/3 × (VR33 – VR03) VR13,1/3bias Analog input voltage at R13 with 1/3 biasing LCDREXT = 1, LCDEXTBIAS = 1, LCD2B = 0 VR03 VR03 + 1/3 × (VR33 – VR03) VR23 V VR13,1/2bias Analog input voltage at R13 with 1/2 biasing LCDREXT = 1, LCDEXTBIAS = 1, LCD2B = 1 VR03 VR03 + 1/2 × (VR33 – VR03) VR33 V VR03 Analog input voltage at R03 R0EXT = 1 VSS VLCD-VR03 Voltage difference between VLCD and R03 LCDCPEN = 0, R0EXT = 1 2.4 VLCDREF/R13 External LCD reference voltage applied at LCDREF/R13 VLCDREFx = 01 0.8 50 Specifications V 1.2 VCC + 0.2 V 1.5 V Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 www.ti.com SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 5.47 LCD_C Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VLCDx = 0000, VLCDEXT = 0 LCD voltage MIN 2.4 V to 3.6 V TYP 2.60 LCDCPEN = 1, VLCDx = 0010 2.66 LCDCPEN = 1, VLCDx = 0011 2.72 LCDCPEN = 1, VLCDx = 0100 2.78 LCDCPEN = 1, VLCDx = 0101 2.84 LCDCPEN = 1, VLCDx = 0111 UNIT 2.90 2 V to 3.6 V 2.96 LCDCPEN = 1, VLCDx = 1000 3.02 LCDCPEN = 1, VLCDx = 1001 3.08 LCDCPEN = 1, VLCDx = 1010 3.14 LCDCPEN = 1, VLCDx = 1011 3.20 LCDCPEN = 1, VLCDx = 1100 3.26 LCDCPEN = 1, VLCDx = 1101 3.32 LCDCPEN = 1, VLCDx = 1110 MAX VCC LCDCPEN = 1, VLCDx = 0001 LCDCPEN = 1, VLCDx = 0110 VLCD VCC 2.2 V to 3.6 V V 3.38 LCDCPEN = 1, VLCDx = 1111 3.50 3.72 ICC,Peak,CP Peak supply currents due to charge pump activities LCDCPEN = 1, VLCDx = 1111 2.2 V 200 tLCD,CP,on Time to charge CLCD when discharged CLCD = 4.7 µF, LCDCPEN = 0→1, VLCDx = 1111 2.2 V 100 ICP,Load Maximum charge pump load current LCDCPEN = 1, VLCDx = 1111 2.2 V RLCD,Seg LCD driver output impedance, segment lines LCDCPEN = 1, VLCDx = 1000, ILOAD = ±10 µA 2.2 V 10 kΩ RLCD,COM LCD driver output impedance, common lines LCDCPEN = 1, VLCDx = 1000, ILOAD = ±10 µA 2.2 V 10 kΩ µA 500 50 µA Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 Copyright © 2012–2018, Texas Instruments Incorporated ms 51 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 5.48 SD24_B Power Supply and Recommended Operating Conditions MIN AVCC = DVCC, AVSS = DVSS = 0 V TYP MAX Analog supply voltage TA Ambient temperature –40 85 °C fSD Modulator clock frequency 0.03 2.3 MHz VI Absolute input voltage range AVSS – 1 AVCC VIC Common-mode input voltage range VID,FS Differential full-scale input voltage Bipolar mode, VID = VI,A+ – VI,A– Differential input voltage for specified performance (1) VID REFON = 1 2.4 AVSS – 1 AVCC –VREF/GAIN +VREF/GAIN SD24GAINx = 1 ±900 ±930 SD24GAINx = 2 ±450 ±460 SD24GAINx = 4 ±225 ±230 SD24GAINx = 8 ±112 ±120 SD24GAINx = 16 ±56 ±60 SD24GAINx = 32 ±28 ±30 SD24GAINx = 64 ±14 ±14 ±7 ±7.25 SD24GAINx = 128 CREF (1) (2) VREF load capacitance (2) 3.6 UNIT AVCC SD24REFS = 1 V V V mV mV 100 nF The full-scale range (FSR) is defined by VFS+ = +VREF/GAIN and VFS– = –VREF/GAIN: FSR = VFS+ – VFS– = 2 × VREF/GAIN. If VREF is sourced externally, the analog input range should not exceed 80% of VFS+ or VFS–, that is, VID = 0.8 VFS– to 0.8 VFS+. If VREF is sourced internally, the given VID ranges apply. MIN values are calculated based on a VREF of 1.125 V. TYP values are calculated based on a VREF of 1.16 V. There is no capacitance required on VREF. However, TI recommends a capacitance of 100 nF to reduce any reference voltage noise. 5.49 SD24_B Analog Input (1) also see Figure 5-16 PARAMETER CI Input capacitance TEST CONDITIONS VCC MIN SD24GAINx = 1 5.0 SD24GAINx = 2 5.0 SD24GAINx = 4 5.0 SD24GAINx = 8 5.0 SD24GAINx = 16 5.0 SD24GAINx = 32, 64, 128 Input impedance (pin A+ or A– to AVSS) fSD24 = 1 MHz SD24GAINx = 8 3V fSD24 = 1 MHz SD24GAINx = 8 SD24GAINx = 32 (1) 52 pF 200 kΩ 200 SD24GAINx = 1 ZID UNIT 200 SD24GAINx = 32 Differential input impedance (pin A+ to pin A–) MAX 5.0 SD24GAINx = 1 ZI TYP 300 3V 400 400 300 kΩ 400 All parameters pertain to each SD24_B converter. Specifications Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 www.ti.com SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 1600 1400 Input Leakage Current – nA 1200 1000 800 600 400 200 0 -200 -1 -0.5 0 0.5 1 1.5 2 2.5 3 Input Voltage – V Figure 5-16. Input Leakage Current vs Input Voltage (Modulator OFF) 5.50 SD24_B Supply Currents PARAMETER ISD,256 ISD,512 Analog plus digital supply current per converter (reference not included) Analog plus digital supply current per converter (reference not included) TEST CONDITIONS fSD24 = 1 MHz, SD24OSR = 256 fSD24 = 2 MHz, SD24OSR = 512 TYP MAX SD24GAIN: 1 490 600 SD24GAIN: 2 490 600 SD24GAIN: 4 490 600 559 700 559 700 SD24GAIN: 32 627 800 SD24GAIN: 64 627 800 SD24GAIN: 128 627 800 SD24GAIN: 1 600 700 677 800 740 900 SD24GAIN: 8 SD24GAIN: 16 SD24GAIN: 8 SD24GAIN: 32 VCC 3V 3V MIN Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 Copyright © 2012–2018, Texas Instruments Incorporated UNIT µA µA 53 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 5.51 SD24_B Performance fSD24 = 1 MHz, SD24OSRx = 256, SD24REFON = 1 PARAMETER TEST CONDITIONS VCC SD24GAIN: 1 Integral nonlinearity, end-point fit INL SD24GAIN: 8 3V SD24GAIN: 32 Gnom +0.01 –0.01 +0.01 –0.01 +0.01 1 SD24GAIN: 2 2 SD24GAIN: 4 4 SD24GAIN: 16 32 SD24GAIN: 64 64 128 3V SD24GAIN: 32, with external reference (1.2 V) ΔEG/ΔT Gain error temperature coefficient (2), internal reference ΔEG/ΔT Gain error temperature coefficient (2), external reference SD24GAIN: 1, 8, or 32 (with internal reference) –1% +1% –2% +2% –2% +2% 3V 80 SD24GAIN: 1 (with external reference) SD24GAIN: 8 (with external reference) ΔEG/ΔVCC Gain error vs VCC 15 SD24GAIN: 32 (with external reference) SD24GAIN: 8 0.1 3V 0.1 Offset error SD24GAIN: 8 2.3 3V 1 SD24GAIN: 32 EOS[FS] Offset error SD24GAIN: 8 3V SD24GAIN: 32 ΔEOS/ΔT (1) (2) (3) (4) (5) 54 Offset error temperature coefficient (5) SD24GAIN: 1 SD24GAIN: 8 SD24GAIN: 32 mV 0.5 SD24GAIN: 1 (with Vdiff = 0 V) (4) %/V 0.4 SD24GAIN: 1 (with Vdiff = 0 V) EOS[V] ppm/°C 15 SD24GAIN: 32 (4) ppm/°C 15 3V SD24GAIN: 1 (3) % FSR 16 SD24GAIN: 32 SD24GAIN: 8, with external reference (1.2 V) UNIT 8 3V SD24GAIN: 1, with external reference (1.2 V) Gain error (1) MAX –0.01 SD24GAIN: 128 EG TYP SD24GAIN: 1 SD24GAIN: 8 Nominal gain MIN –0.2 +0.2 –0.7 +0.7 –1.4 +1.4 % FS 2 3V 0.25 µV/°C 0.1 The gain error EG specifies the deviation of the actual gain Gact from the nominal gain Gnom: EG = (Gact – Gnom)/Gnom. It covers process, temperature, and supply voltage variations. The gain error temperature coefficient ΔEG/ ΔT specifies the variation of the gain error EG over temperature (EG(T) = (Gact(T) – Gnom)/Gnom) using the box method (that is, minimum and maximum values): ΔEG/ ΔT = (MAX(EG(T)) – MIN(EG(T) ) / (MAX(T) – MIN(T)) = (MAX(Gact(T)) – MIN(Gact(T)) / Gnom / (MAX(T) – MIN(T)) with T ranging from –40°C to 85°C. The gain error vs VCC coefficient ΔEG/ ΔVCC specifies the variation of the gain error EG over supply voltage (EG(VCC) = (Gact(VCC) – Gnom)/Gnom) using the box method (that is, minimum and maximum values): ΔEG/ ΔVCC = (MAX(EG(VCC)) – MIN(EG(VCC) ) / (MAX(VCC) – MIN(VCC)) = (MAX(Gact(VCC)) – MIN(Gact(VCC)) / Gnom / (MAX(VCC) – MIN(VCC)) with VCC ranging from 2.4 V to 3.6 V. The offset error EOS is measured with shorted inputs in 2s-complement mode with +100% FS = VREF/G and –100% FS = -VREF/G. Conversion between EOS [FS] and EOS [V] is as follows: EOS [FS] = EOS [V] × G/VREF, EOS [V] = EOS [FS] × VREF/G. The offset error temperature coefficient ΔEOS / ΔT specifies the variation of the offset error EOS over temperature using the box method (that is, minimum and maximum values): ΔEOS / ΔT = (MAX(EOS(T)) – MIN(EOS(T) ) / (MAX(T) – MIN(T)) with T ranging from –40°C to 85°C. Specifications Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 www.ti.com SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 SD24_B Performance (continued) fSD24 = 1 MHz, SD24OSRx = 256, SD24REFON = 1 PARAMETER TEST CONDITIONS VCC SD24GAIN: 1 ΔEOS/ΔVCC Offset error vs VCC (6) SD24GAIN: 8 3V SD24GAIN: 8 3V SD24GAIN: 8, fCM = 50 Hz, VCM = 120 mV AC PSRR,int AC power supply rejection ratio, internal reference (9) XT –110 –110 SD24GAIN: 1, VCC = 3 V + 50 mV × sin(2π × fVCC × t), fVCC = 50 Hz –61 SD24GAIN: 8, VCC = 3 V + 50 mV × sin(2π × fVCC × t), fVCC = 50 Hz –75 SD24GAIN: 32, VCC = 3 V + 50 mV × sin(2π × fVCC × t), fVCC = 50 Hz –79 SD24GAIN: 1, VCC = 3 V + 50 mV × sin(2π × fVCC × t), fVCC = 50 Hz –61 SD24GAIN: 8, VCC = 3 V + 50 mV × sin(2π × fVCC × t), fVCC = 50 Hz –75 SD24GAIN: 32, VCC = 3 V + 50 mV × sin(2π × fVCC × t), fVCC = 50 Hz –79 Crosstalk source: SD24GAIN: 1, Sine-wave with maximum possible Vpp, fIN = 50 Hz or 100 Hz, Converter under test: SD24GAIN: 8 Crosstalk source: SD24GAIN: 1, Sine-wave with maximum possible Vpp, fIN = 50 Hz or 100 Hz, Converter under test: SD24GAIN: 32 dB dB –100 Crosstalk source: SD24GAIN: 1, Sine-wave with maximum possible Vpp, fIN = 50 Hz or 100 Hz, Converter under test: SD24GAIN: 1 Crosstalk between converters (10) µV/V –120 3V SD24GAIN: 32, fCM = 50 Hz, VCM = 30 mV AC power supply AC PSRR,ext rejection ratio, external reference (9) 125 –100 SD24GAIN: 1, fCM = 50 Hz, VCM = 930 mV Common-mode rejection at 50 Hz (8) UNIT –120 SD24GAIN: 32 CMRR,50 Hz MAX 50 SD24GAIN: 1 Common-mode rejection at DC (7) TYP 500 SD24GAIN: 32 CMRR,DC MIN dB dB –120 3V –115 dB –110 (6) The offset error vs VCC ΔEOS / ΔVCC specifies the variation of the offset error EOS over supply voltage using the box method (that is, minimum and maximum values): ΔEOS / ΔVCC = (MAX(EOS(VCC)) – MIN(EOS(VCC) ) / (MAX(VCC) – MIN(VCC)) with VCC ranging from 2.4 V to 3.6 V. (7) The DC CMRR specifies the change in the measured differential input voltage value when the common-mode voltage varies: DC CMRR = –20log(ΔMAX / FSR) with ΔMAX being the difference between the minium value and the maximum value measured when sweeping the common-mode voltage. The DC CMRR is measured with both inputs connected to the common-mode voltage (that is, no differential input signal is applied), and the common-mode voltage is swept from –1 V to VCC. (8) The AC CMRR is the difference between a hypothetical signal with the amplitude and frequency of the applied common-mode ripple applied to the inputs of the ADC and the actual common-mode signal spur visible in the FFT spectrum: AC CMRR = Error Spur [dBFS] – 20log(VCM / 1.2 V / G) [dBFS] with a common-mode signal of VCM × sin(2π × fCM × t) applied to the analog inputs. The AC CMRR is measured with the both inputs connected to the common-mode signal; that is, no differential input signal is applied. With the specified typical values the error spur is within the noise floor (as specified by the SINAD values). (9) The AC PSRR is the difference between a hypothetical signal with the amplitude and frequency of the applied supply voltage ripple applied to the inputs of the ADC and the actual supply ripple spur visible in the FFT spectrum: AC PSRR = Error Spur [dBFS] – 20log(50 mV / 1.2 V / G) [dBFS] with a signal of 50 mV × sin(2π × fVCC × t) added to VCC. The AC PSRR is measured with the inputs grounded; that is, no analog input signal is applied. With the specified typical values the error spur is within the noise floor (as specified by the SINAD values). SD24GAIN: 1 → Hypothetical signal: 20log(50 mV / 1.2 V / 1) = –27.6 dBFS SD24GAIN: 8 → Hypothetical signal: 20log(50 mV / 1.2 V / 8) = –9.5 dBFS SD24GAIN: 32 → Hypothetical signal: 20log(50 mV / 1.2 V / 32) = 2.5 dBFS (10) The crosstalk (XT) is specified as the tone level of the signal applied to the crosstalk source seen in the spectrum of the converter under test. It is measured with the inputs of the converter under test being grounded. Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 Copyright © 2012–2018, Texas Instruments Incorporated 55 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 5.52 SD24_B, AC Performance fSD24 = 1 MHz, SD24OSRx = 256, SD24REFON = 1 (see Figure 5-17) PARAMETER TEST CONDITIONS VCC SD24GAIN: 1 MIN TYP 84 86 SD24GAIN: 2 Signal-to-noise + distortion ratio 84 SD24GAIN: 8 fIN = 50 Hz (1) SD24GAIN: 16 3V SD24GAIN: 32 81 Total harmonic distortion 71 dB 73 SD24GAIN: 64 67 SD24GAIN: 128 61 95 fIN = 50 Hz (1) SD24GAIN: 8 3V 90 SD24GAIN: 32 (1) 83 80 SD24GAIN: 1 THD UNIT 85 SD24GAIN: 4 SINAD MAX dB 86 The following voltages were applied to the SD24_B inputs: VI,A+(t) = 0 V + VPP / 2 × sin(2π × fIN × t) and VI,A–(t) = 0 V – VPP / 2 × sin(2π × fIN × t) resulting in a differential voltage of VID = VI,A+(t) – VI,A–(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value allowed for a given range (according to SD24_B recommended operating conditions). 5.53 SD24_B, AC Performance fSD24 = 2 MHz, SD24OSRx = 512, SD24REFON = 1 PARAMETER SINAD (1) Signal-to-noise + distortion ratio TEST CONDITIONS VCC MIN TYP SD24GAIN: 1 87 SD24GAIN: 2 85 SD24GAIN: 4 84 SD24GAIN: 8 fIN = 50 Hz (1) SD24GAIN: 16 MAX 83 3V dB 81 SD24GAIN: 32 76 SD24GAIN: 64 71 SD24GAIN: 128 65 UNIT The following voltages were applied to the SD24_B inputs: VI,A+(t) = 0 V + VPP / 2 × sin(2π × fIN × t) and VI,A–(t) = 0 V – VPP / 2 × sin(2π × fIN × t) resulting in a differential voltage of VID = VI,A+(t) – VI,A–(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value allowed for a given range (according to SD24_B recommended operating conditions). 5.54 SD24_B, AC Performance fSD24 = 32 kHz, SD24OSRx = 512, SD24REFON = 1 PARAMETER SINAD (1) 56 Signal-to-noise + distortion ratio TEST CONDITIONS VCC MIN TYP SD24GAIN: 1 89 SD24GAIN: 2 85 SD24GAIN: 4 84 SD24GAIN: 8 SD24GAIN: 16 fIN = 50 Hz (1) 3V MAX 82 80 SD24GAIN: 32 76 SD24GAIN: 64 67 SD24GAIN: 128 61 UNIT dB The following voltages were applied to the SD24_B inputs: VI,A+(t) = 0 V + VPP / 2 × sin(2π × fIN × t) and VI,A–(t) = 0 V – VPP / 2 × sin(2π × fIN × t) resulting in a differential voltage of VID = VI,A+(t) – VI,A–(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value allowed for a given range (according to SD24_B recommended operating conditions) (also see Figure 5-18). Specifications Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 www.ti.com SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 110.0 Theoretical limit (second order) 100.0 SINAD − dB 90.0 80.0 70.0 60.0 50.0 10 100 1000 OSR Figure 5-17. SINAD vs OSR (fSD24 = 1 MHz, SD24REFON = 1, SD24GAIN: 1) 100.0 SINAD – dB 80.0 60.0 40.0 20.0 0.0 0 0.2 0.4 0.6 Vpp – Vref/Gain 0.8 1 Figure 5-18. SINAD vs VPP 5.55 SD24_B External Reference Input ensure correct input voltage range according to VREF PARAMETER TEST CONDITIONS VCC MIN TYP MAX 1.0 1.20 1.5 V 50 nA VREF(I) Input voltage SD24REFS = 0 3V IREF(I) Input current SD24REFS = 0 3V Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 Copyright © 2012–2018, Texas Instruments Incorporated UNIT 57 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 5.56 10-Bit ADC Power Supply and Input Range Conditions over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC AVCC Analog supply voltage AVCC and DVCC are connected together, AVSS and DVSS are connected together, V(AVSS) = V(DVSS) = 0 V V(Ax) Analog input voltage range (1) All ADC10_A pins Operating supply current into AVCC terminal, REF module and reference buffer off fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF = 00 Operating supply current into AVCC terminal, REF module on, reference buffer on fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 1, SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF = 01 Operating supply current into AVCC terminal, REF module off, reference buffer on fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF = 10, VEREF = 2.5 V Operating supply current into AVCC terminal, REF module off, reference buffer off fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF = 11, VEREF = 2.5 V CI Input capacitance Only one terminal Ax can be selected at one time from the pad to the ADC10_A capacitor array including wiring and pad. RI Input MUX ON resistance IADC10_A (1) MIN TYP MAX UNIT 1.8 3.6 V 0 AVCC V 2.2 V 68 100 3V 78 110 124 180 105 160 72 110 µA 3V 2.2 V 3.5 pF AVCC > 2.0 V, 0 V ≤ VAx ≤ AVCC 36 1.8 V < AVCC < 2.0 V, 0 V ≤ VAx ≤ AVCC 96 kΩ The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. The external reference voltage requires decoupling capacitors. Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external reference source if it is used for the ADC10_A. Also see the MSP430x5xx and MSP430x6xx Family User's Guide. 5.57 10-Bit ADC Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC MIN TYP MAX UNIT For specified performance of ADC10_A linearity parameters 2.2 V, 3 V 0.45 5 5.5 MHz Internal ADC10_A oscillator (1) ADC10DIV = 0, fADC10CLK = fADC10OSC 2.2 V, 3 V 4.4 4.9 5.6 MHz 2.2 V, 3 V 2.4 Conversion time REFON = 0, Internal oscillator, 12 ADC10CLK cycles, 10-bit mode, fADC10OSC = 4 MHz to 5 MHz fADC10CLK fADC10OSC tCONVERT TEST CONDITIONS µs External fADC10CLK from ACLK, MCLK, or SMCLK, ADC10SSEL ≠ 0 tADC10ON Turnon settling time of the ADC tSample Sampling time (1) (2) (3) 58 See 12 × 1 / fADC10CLK (2) 100 RS = 1000 Ω, RI = 96 kΩ, CI = 3.5 pF (3) RS = 1000 Ω, RI = 36 kΩ, CI = 3.5 pF 3.0 (3) 1.8 V 3 3V 1 ns µs The ADC10OSC is sourced directly from MODOSC inside the UCS. The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already settled. Approximately 8 Tau (τ) are needed to get an error of less than ±0.5 LSB Specifications Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 www.ti.com SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 5.58 10-Bit ADC Linearity Parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS 1.4 V ≤ (VeREF+ – VeREF–) ≤ 1.6 V, CVeREF+ = 20 pF VCC MAX –1.0 +1.0 –1.0 +1.0 UNIT EI Integral linearity error ED Differential linearity error 1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF 2.2 V, 3 V –1.0 +1.0 LSB EO Offset error 1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF Internal impedance of source RS < 100 Ω 2.2 V, 3 V –1.0 +1.0 LSB EG Gain error 1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF, ADC10SREFx = 11b 2.2 V, 3 V –1.0 +1.0 LSB ET Total unadjusted error 1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF, ADC10SREFx = 11b 2.2 V, 3 V –2.0 +2.0 LSB MIN MAX UNIT 1.6 V < (VeREF+ – VeREF–) ≤ VAVCC, CVeREF+ = 20 pF 2.2 V, 3 V MIN LSB 5.59 10-Bit ADC External Reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TEST CONDITIONS VCC VeREF+ Positive external reference voltage input VeREF+ > VeREF– (2) 1.4 AVCC V VeREF– Negative external reference voltage input VeREF+ > VeREF– (3) 0 1.2 V (VeREF+ – VeREF–) Differential external reference voltage input VeREF+ > VeREF– (4) 1.4 AVCC V –26 +26 IVeREF+, IVeREF– CVREF+ (1) (2) (3) (4) (5) Static input current Capacitance at VREF+ terminal 1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V, fADC10CLK = 5 MHz, ADC10SHTx = 0x0001, Conversion rate 200 ksps 1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V, fADC10CLK = 5 MHZ, ADC10SHTX = 0x1000, Conversion rate 20 ksps See (5) 2.2 V, 3 V µA –1 +1 10 µF The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements. Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external reference source if it is used for the ADC10_A. Also see the MSP430x5xx and MSP430x6xx Family User's Guide. Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 Copyright © 2012–2018, Texas Instruments Incorporated 59 MSP430F6779, MSP430F6778, MSP430F6777, MSP430F6776, MSP430F6775 MSP430F6769, MSP430F6768, MSP430F6767, MSP430F6766, MSP430F6765 MSP430F6749, MSP430F6748, MSP430F6747, MSP430F6746, MSP430F6745 SLAS768E – SEPTEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 5.60 REF Built-In Reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS REFVSEL = {2} for 2.5 V, REFON = 1 Positive built-in reference voltage VREF+ REFVSEL = {1} for 2 V, REFON = 1 REFVSEL = {0} for 1.5 V, REFON = 1 AVCC minimum voltage, Positive built-in reference active AVCC(min) VCC 3V 2.2 V, 3 V MIN TYP MAX 2.47 2.51 2.55 1.96 1.99 2.02 1.48 1.5 1.52 REFVSEL = {0} for 1.5 V 1.8 REFVSEL = {1} for 2 V 2.2 REFVSEL = {2} for 2.5 V 2.7 fADC10CLK = 5.0 MHz, REFON = 1, REFBURST = 0, REFVSEL = {2} for 2.5 V Operating supply current into AVCC terminal (1) IREF+ 24 16.1 21 fADC10CLK = 5.0 MHz, REFON = 1, REFBURST = 0, REFVSEL = {0} for 1.5 V 14.4 21