MSP-FET430U48

MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 D Low Supply Voltage Range 1.8 V to 3.6 V D Ultralow-Power Consumption: D D D D D D D Serial Communication Interface (USART0) − Active Mode: 200 μA at 1 MHz, 2.2 V − Standby Mode: 0.7 μA − Off Mode (RAM Retention): 0.1 μA Five Power Saving Modes Wake-Up From Standby Mode in less than 6 μs 16-Bit RISC Architecture, 125 ns Instruction Cycle Time Basic Clock Module Configurations: − Various Internal Resistors − Single External Resistor − 32 kHz Crystal − High Frequency Crystal − Resonator − External Clock Source 16-Bit Timer_A With Three Capture/Compare Registers On-Chip Comparator for Analog Signal Compare Function or Slope A/D Conversion D D D D Software-Selects Asynchronous UART or Synchronous SPI Serial Onboard Programming, No External Programming Voltage Needed Programmable Code Protection by Security Fuse Family Members Include: MSP430F122: 4KB + 256B Flash Memory 256B RAM MSP430F123: 8KB + 256B Flash Memory 256B RAM Available in a 28-Pin Plastic Small-Outline Wide Body (SOWB) Package, 28-Pin Plastic Thin Shrink Small-Outline Package (TSSOP) and 32-Pin QFN Package For Complete Module Descriptions, See the MSP430x1xx Family User’s Guide, Literature Number SLAU049 description The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6μs. The MSP430F12x series is an ultralow-power mixed signal microcontroller with a built-in 16-bit timer and twenty-two I/O pins. The MSP430F12x series also has a built-in communication capability using asynchronous (UART) and synchronous (SPI) protocols in addition to a versatile analog comparator. Typical applications include sensor systems that capture analog signals, convert them to digital values, and then process the data and display them or transmit them to a host system. Stand alone RF sensor front end is another area of application. The I/O port inputs provide single slope A/D conversion capability on resistive sensors. AVAILABLE OPTIONS PACKAGED DEVICES TA −40°C 40°C to 85°C PLASTIC 28-PIN SOWB (DW) PLASTIC 28-PIN TSSOP (PW) PLASTIC 32-PIN QFN (RHB) MSP430F122IDW MSP430F123IDW MSP430F122IPW MSP430F123IPW MSP430F122IRHB MSP430F123IRHB Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 2001 − 2004 Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 pin designation, MSP430x12x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 P1.7/TA2/TDO/TDI P1.6/TA1/TDI/TCLK P1.5/TA0/TMS P1.4/SMCLK/TCK P1.3/TA2 P1.2/TA1 P1.1/TA0 P1.0/TACLK VSS P2.4/CA1/TA2 XOUT P2.3/CA0/TA1 XIN P3.7 NC P3.6 RST/NMI P3.5/URXD0 P2.0/ACLK P3.4/UTXD0 P2.1/INCLK P2.2/CAOUT/TA0 1 31 30 29 28 27 26 24 2 23 3 22 4 21 20 5 6 19 18 7 8 10 11 12 13 14 15 17 P1.3/TA2 P1.2/TA1 P1.1/TA0 P1.0/TACLK NC P2.4/CA1/TA2 P2.3/CA0/TA1 NC P3.0/STE0 P3.1/SIMO0 P3.2/SOMI0 P3.3/UCLK0 P3.4/UTXD0 P3.5/URXD0 P3.6 P3.7 TEST VCC P2.5/ROSC VSS XOUT XIN RST/NMI P2.0/ACLK P2.1/INCLK P2.2/CAOUT/TA0 P3.0/STE0 P3.1/SIMO0 P3.2/SOMI0 P3.3/UCLK0 P2.5/ROSC NC VCC TEST P1.7/TA2/TDO/TDI P1.6/TA1/TDI/TCLK P1.5/TA0/TMS P1.4/SMCLK/TCK RHB PACKAGE (TOP VIEW) DW OR PW PACKAGE (TOP VIEW) Note: NC pins not internally connected Power Pad connection to VSS recommended functional block diagram XIN XOUT VCC VSS P1 RST/NMI JTAG ROSC Oscillator System Clock ACLK 8KB Flash SMCLK 4KB Flash 256B RAM P2 8 I/O Port 1 8 I/Os, with Interrupt Capability P3 6 8 I/O Port 2 6 I/Os, with Interrupt Capability I/O Port 3 8 I/Os MCLK Test MAB, 4 Bit MAB,MAB, 16 Bit16-Bit JTAG CPU TEST MCB Emulation Module Incl. 16 Reg. Bus Conv MDB, 16-Bit MDB, 16 Bit Watchdog Timer Timer_A3 MDB, 8 Bit POR 3 CC Reg POST OFFICE BOX 655303 USART0 UART Mode SPI Mode 15/16-Bit 2 Comparator A • DALLAS, TEXAS 75265 MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 Terminal Functions TERMINAL DW, PW RHB NO. NO. P1.0/TACLK 21 21 I/O General-purpose digital I/O pin/Timer_A, clock signal TACLK input P1.1/TA0 22 22 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit P1.2/TA1 23 23 I/O General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output P1.3/TA2 24 24 I/O General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output P1.4/SMCLK/TCK 25 25 I/O General-purpose digital I/O pin/SMCLK signal output/test clock, input terminal for device programming and test P1.5/TA0/TMS 26 26 I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output/test mode select, input terminal for device programming and test P1.6/TA1/TDI/TCLK 27 27 I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/test data input terminal or test clock input P1.7/TA2/TDO/TDI † 28 28 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/test data output terminal or data input during programming P2.0/ACLK 8 6 I/O General-purpose digital I/O pin/ACLK output P2.1/INCLK 9 7 I/O General-purpose digital I/O pin/Timer_A, clock signal at INCLK P2.2/CAOUT/TA0 10 8 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0B input/comparator_A, output/BSL receive P2.3/CA0/TA1 19 18 I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/comparator_A, input P2.4/CA1/TA2 20 19 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/comparator_A, input P2.5/ROSC 3 32 I/O General-purpose digital I/O pin/Input for external resistor that defines the DCO nominal frequency NAME DESCRIPTION P3.0/STE0 11 9 I/O General-purpose digital I/O pin/slave transmit enable—USART0/SPI mode P3.1/SIMO0 12 10 I/O General-purpose digital I/O pin/slave in/master out of USART0/SPI mode P3.2/SOMI0 13 11 I/O General-purpose digital I/O pin/slave out/master in of USART0/SPI mode P3.3/UCLK0 14 12 I/O General-purpose digital I/O pin/external clock input—USART0/UART or SPI mode, clock output—USART0/SPI mode clock input P3.4/UTXD0 15 13 I/O General-purpose digital I/O pin/transmit data out—USART0/UART mode P3.5/URXD0 16 14 I/O General-purpose digital I/O pin/receive data in—USART0/UART mode P3.6 17 15 I/O General-purpose digital I/O pin P3.7 18 16 I/O General-purpose digital I/O pin RST/NMI 7 5 I Reset or nonmaskable interrupt input TEST 1 29 I Selects test mode for JTAG pins on Port1 VCC 2 30 VSS 4 1 XIN 6 3 I Input terminal of crystal oscillator XOUT 5 2 O Output terminal of crystal oscillator NC QFN Pad † I/O Supply voltage Ground reference 4, 17, 20, 31 NA Package Pad No internal connection NA QFN package pad connection to VSS recommended. TDO or TDI is selected via JTAG instruction. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 short-form description CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. Program Counter PC/R0 Stack Pointer SP/R1 Status Register SR/CG1/R2 Constant Generator The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. instruction set The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 1 shows examples of the three types of instruction formats; the address modes are listed in Table 2. CG2/R3 General-Purpose Register R4 General-Purpose Register R5 General-Purpose Register R6 General-Purpose Register R7 General-Purpose Register R8 General-Purpose Register R9 General-Purpose Register R10 General-Purpose Register R11 General-Purpose Register R12 General-Purpose Register R13 General-Purpose Register R14 General-Purpose Register R15 Table 1. Instruction Word Formats Dual operands, source-destination e.g. ADD R4,R5 R4 + R5 −−−> R5 Single operands, destination only e.g. CALL PC −−>(TOS), R8−−> PC Relative jump, un/conditional e.g. JNE R8 Jump-on-equal bit = 0 Table 2. Address Mode Descriptions ADDRESS MODE Indirect D D D D D Indirect autoincrement Register Indexed Symbolic (PC relative) Absolute Immediate NOTE: S = source 4 S D D D D D SYNTAX EXAMPLE MOV Rs,Rd MOV R10,R11 MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) MOV EDE,TONI OPERATION R10 −−> R11 M(2+R5)−−> M(6+R6) M(EDE) −−> M(TONI) MOV &MEM,&TCDAT M(MEM) −−> M(TCDAT) MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) −−> M(Tab+R6) D MOV @Rn+,Rm MOV @R10+,R11 M(R10) −−> R11 R10 + 2−−> R10 D MOV #X,TONI MOV #45,TONI D = destination POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 #45 −−> M(TONI) MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 operating modes The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: D Active mode AM; − All clocks are active D Low-power mode 0 (LPM0); − CPU is disabled ACLK and SMCLK remain active. MCLK is disabled D Low-power mode 1 (LPM1); − CPU is disabled ACLK and SMCLK remain active. MCLK is disabled DCO’s dc-generator is disabled if DCO not used in active mode D Low-power mode 2 (LPM2); − CPU is disabled MCLK and SMCLK are disabled DCO’s dc-generator remains enabled ACLK remains active D Low-power mode 3 (LPM3); − CPU is disabled MCLK and SMCLK are disabled DCO’s dc-generator is disabled ACLK remains active D Low-power mode 4 (LPM4); − CPU is disabled ACLK is disabled MCLK and SMCLK are disabled DCO’s dc-generator is disabled Crystal oscillator is stopped POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 interrupt vector addresses The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh-0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY Power-up External reset Watchdog Flash memory WDTIFG (see Note1) KEYV (see Note 1) Reset 0FFFEh 15, highest NMI Oscillator fault Flash memory access violation NMIIFG (see Notes 1 and 4) OFIFG (see Notes 1 and 4) ACCVIFG (see Notes 1 and 4) (non)-maskable, (non)-maskable, (non)-maskable 0FFFCh 14 0FFFAh 13 0FFF8h 12 Comparator_A CAIFG maskable 0FFF6h 11 Watchdog timer WDTIFG maskable 0FFF4h 10 Timer_A3 TACCR0 CCIFG (see Note 2) maskable 0FFF2h 9 Timer_A3 TACCR1 and TACCR2 CCIFGs, TAIFG (see Notes 1 and 2) maskable 0FFF0h 8 USART0 receive URXIFG0 maskable 0FFEEh 7 USART0 transmit UTXIFG0 maskable 0FFECh 6 0FFEAh 5 0FFE8h 4 I/O Port P2 (eight flags − see Note 3) P2IFG.0 to P2IFG.7 (see Notes 1 and 2) maskable 0FFE6h 3 I/O Port P1 (eight flags) P1IFG.0 to P1IFG.7 (see Notes 1 and 2) maskable 0FFE4h 2 NOTES: 1. 2. 3. 4. 6 0FFE2h 1 0FFE0h 0, lowest Multiple source flags Interrupt flags are located in the module There are eight Port P2 interrupt flags, but only six Port P2 I/O pins (P2.0−5) are implemented on the ’12x devices. (non)-maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 special function registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits that are not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. interrupt enable 1 and 2 Address 7 6 0h 5 4 ACCVIE NMIIE rw-0 3 2 1 OFIE rw-0 0 WDTIE rw-0 rw-0 WDTIE: Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval timer mode. OFIE: Oscillator-fault-interrupt enable NMIIE: Nonmaskable-interrupt enable ACCVIE: Flash access violation interrupt enable Address 7 6 5 4 3 2 01h 1 UTXIE0 USART0: UART and SPI receive-interrupt enable UTXIE0: USART0: UART and SPI transmit-interrupt enable URXIE0 rw-0 rw-0 URXIE0: 0 interrupt flag register 1 and 2 Address 7 6 5 02h 4 3 2 NMIIFG 1 OFIFG rw-0 rw-1 0 WDTIFG rw-(0) WDTIFG: Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC power up or a reset condition at the RST/NMI pin in reset mode. OFIFG: Flag set on oscillator fault NMIIFG: Set via RST/NMI pin Address 7 6 5 4 3 03h 2 1 UTXIFG0 rw-0 URXIFG0: USART0: UART and SPI receive flag UTXIFG0: USART0: UART and SPI transmit flag POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0 URXIFG0 rw-0 7 MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 module enable registers 1 and 2 Address 7 6 5 4 3 2 1 7 6 5 4 3 2 1 0 04h Address 05h UTXE0 rw-0 URXE0: USART0: UART receive enable UTXE0: USART0: UART transmit enable USPIE0: USART0: SPI (synchronous peripheral interface) transmit and receive enable Legend 0 URXE0 USPIE0 rw: rw-0,1: rw-(0,1): rw-0 Bit can be read and written. Bit can be read and written. It is Reset or Set by PUC Bit can be read and written. It is Reset or Set by POR SFR bit is not present in device. memory organization MSP430F122 MSP430F123 Memory Main: interrupt vector Main: code memory Size Flash Flash 4KB Flash 0FFFFh−0FFE0h 0FFFFh−0F000h 8KB Flash 0FFFFh−0FFE0h 0FFFFh−0E000h Information memory Size Flash 256 Byte 010FFh − 01000h 256 Byte 010FFh − 01000h Boot memory Size ROM 1KB 0FFFh − 0C00h 1KB 0FFFh − 0C00h Size 256 Byte 02FFh − 0200h 256 Byte 02FFh − 0200h 16-bit 8-bit 8-bit SFR 01FFh − 0100h 0FFh − 010h 0Fh − 00h 01FFh − 0100h 0FFh − 010h 0Fh − 00h RAM Peripherals bootstrap loader (BSL) The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the Application report Features of the MSP430 Bootstrap Loader, Literature Number SLAA089. 8 BSL Function DW & PW Package Pins RHB Package Pins Data Transmit 22 - P1.1 22 - P1.1 Data Receive 10 - P2.2 8 - P2.2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 flash memory The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: D Flash memory has n segments of main memory and two segments of information memory (A and B) of 128 bytes each. Each segment in main memory is 512 bytes in size. D Segments 0 to n may be erased in one step, or each segment may be individually erased. D Segments A and B can be erased individually, or as a group with segments 0−n. Segments A and B are also called information memory. D New devices may have some bytes programmed in the information memory (needed for test during manufacturing). The user should perform an erase of the information memory prior to the first use. peripherals Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, see the MSP430x1xx Family User’s Guide, literature number SLAU049. oscillator and system clock The clock system in the MSP430x12x devices is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low-power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 μs. The basic clock module provides the following clock signals: D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal. D Main clock (MCLK), the system clock used by the CPU. D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules. digital I/O There are three 8-bit I/O ports implemented—ports P1, P2, and P3 (only six port P2 I/O signals are available on external pins): D D D D All individual I/O bits are independently programmable. Any combination of input, output, and interrupt conditions is possible. Edge-selectable interrupt input capability for all the eight bits of ports P1 and six bits of port P2. Read/write access to port-control registers is supported by all instructions. NOTE: Six bits of port P2, P2.0 to P2.5, are available on external pins − but all control and data bits for port P2 are implemented. Port P3 has no interrupt capability. watchdog timer The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 USART0 The MSP430x12x devices have one hardware universal synchronous/asynchronous receive transmit (USART0) peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels. timer_A3 Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Timer_A3 Signal Connections Output Pin Number Input Pin Number DW, PW RHB 21 - P1.0 21 - P1.0 Device Input Signal Module Input Name TACLK TACLK ACLK ACLK SMCLK SMCLK 9 - P2.1 7 - P2.1 INCLK INCLK 22 - P1.1 22 - P1.1 TA0 CCI0A 10 - P2.2 8 - P2.2 23 - P1.2 24 - P1.3 23 - P1.2 24 - P1.3 TA0 CCI0B DVSS GND DVCC VCC Module Block Module Output Signal Timer NA CCR0 DW, PW RHB 22 - P1.1 22 - P1.1 26 - P1.5 26 - P1.5 TA0 TA1 CCI1A 19 - P2.3 18 - P2.3 CAOUT (internal) CCI1B 23 - P1.2 23 - P1.2 DVSS GND 27 - P1.6 27 - P1.6 20 - P2.4 19 - P2.4 24 - P1.3 24 - P1.3 28 - P1.7 28 - P1.7 DVCC VCC TA2 CCI2A ACLK (internal) CCI2B DVSS GND DVCC VCC CCR1 CCR2 TA1 TA2 comparator_A The primary function of the comparator_A module is to support precision slope analog-to-digital conversions, battery-voltage supervision, and monitoring of external analog signals. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 peripheral file map PERIPHERALS WITH WORD ACCESS Timer_A Flash Memory Watchdog Reserved Reserved Reserved Reserved Capture/compare Capture/compare Capture/compare Timer_A register Reserved Reserved Reserved Reserved Capture/compare Capture/compare Capture/compare Timer_A control Timer_A interrupt register register register TACCR2 TACCR1 TACCR0 TAR control control control TACCTL2 TACCTL1 TACCTL0 TACTL TAIV 017Eh 017Ch 017Ah 0178h 0176h 0174h 0172h 0170h 016Eh 016Ch 016Ah 0168h 0166h 0164h 0162h 0160h 012Eh Flash control 3 Flash control 2 Flash control 1 FCTL3 FCTL2 FCTL1 012Ch 012Ah 0128h Watchdog/timer control WDTCTL 0120h vector PERIPHERALS WITH BYTE ACCESS USART0 Transmit buffer Receive buffer Baud rate Baud rate Modulation control Receive control Transmit control USART control U0TXBUF U0RXBUF U0BR1 U0BR0 U0MCTL U0RCTL U0TCTL U0CTL 077h 076h 075h 074h 073h 072h 071h 070h Comparator_A Comparator_A port disable Comparator_A control2 Comparator_A control1 CAPD CACTL2 CACTL1 05Bh 05Ah 059h Basic Clock Basic clock sys. control2 Basic clock sys. control1 DCO clock freq. control BCSCTL2 BCSCTL1 DCOCTL 058h 057h 056h Port P3 Port P3 selection Port P3 direction Port P3 output Port P3 input P3SEL P3DIR P3OUT P3IN 01Bh 01Ah 019h 018h Port P2 Port P2 selection Port P2 interrupt enable Port P2 interrupt edge select Port P2 interrupt flag Port P2 direction Port P2 output Port P2 input P2SEL P2IE P2IES P2IFG P2DIR P2OUT P2IN 02Eh 02Dh 02Ch 02Bh 02Ah 029h 028h Port P1 Port P1 selection Port P1 interrupt enable Port P1 interrupt edge select Port P1 interrupt flag Port P1 direction Port P1 output Port P1 input P1SEL P1IE P1IES P1IFG P1DIR P1OUT P1IN 026h 025h 024h 023h 022h 021h 020h POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 peripheral file map (continued) PERIPHERALS WITH BYTE ACCESS (CONTINUED) Special Function Module enable2 Module enable1 SFR interrupt flag2 SFR interrupt flag1 SFR interrupt enable2 SFR interrupt enable1 ME2 ME1 IFG2 IFG1 IE2 IE1 005h 004h 003h 002h 001h 000h absolute maximum ratings† Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V Voltage applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC+0.3 V Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA Storage temperature, Tstg (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C Storage temperature, Tstg (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TEST pin when blowing the JTAG fuse. recommended operating conditions MIN NOM MAX UNITS Supply voltage during program execution, execution VCC (see Note 1) 18 1.8 36 3.6 V Supply voltage during program/erase flash memory, VCC Supply voltage, VSS 2.7 3.6 V Operating free-air temperature range, TA −40 85 °C 0 LF mode selected, XTS=0 LFXT1 crystal t l ffrequency, f(LFXT1) (see Note 2) Watch crystal 32 768 Ceramic resonator XT1 selected mode, mode XTS=1 XTS 1 Processor frequency f(system) (MCLK signal) V Hz 450 8000 1000 8000 VCC = 1.8 V dc 4.15 VCC = 3.6 V dc 8 Crystal kHz MHz NOTES: 1. The LFXT1 oscillator in LF-mode requires a resistor of 5.1 MΩ from XOUT to VSS when VCC