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CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
CC430F613x, CC430F612x, CC430F513x MSP430™ SoC With RF Core
1 Device Overview
1.1
Features
1
• True System-on-Chip (SoC) for Low-Power
Wireless Communication Applications
• Wide Supply Voltage Range:
3.6 V Down to 1.8 V
• Ultra-Low Power Consumption
– CPU Active Mode (AM): 160 µA/MHz
– Standby Mode (LPM3 RTC Mode): 2.0 µA
– Off Mode (LPM4 RAM Retention): 1.0 µA
– Radio in RX: 15 mA, 250 kbps, 915 MHz
• MSP430™ System and Peripherals
– 16-Bit RISC Architecture, Extended Memory, up
to 20-MHz System Clock
– Wake up From Standby Mode in Less
Than 6 µs
– Flexible Power-Management System With SVS
and Brownout
– Unified Clock System With FLL
– 16-Bit Timer TA0, Timer_A With Five
Capture/Compare Registers
– 16-Bit Timer TA1, Timer_A With Three
Capture/Compare Registers
– Hardware Real-Time Clock (RTC)
– Two Universal Serial Communication Interfaces
(USCIs)
– USCI_A0 Supports UART, IrDA, SPI
– USCI_B0 Supports I2C, SPI
– 12-Bit Analog-to-Digital Converter (ADC) With
Internal Reference, Sample-and-Hold, and
Autoscan Features (CC430F613x and
CC430F513x Only)
– Comparator
– Integrated LCD Driver With Contrast Control for
up to 96 Segments (Only CC430F61xx)
– 128-Bit AES Security Encryption and Decryption
Coprocessor
– 32-Bit Hardware Multiplier
– 3-Channel Internal DMA
1.2
•
•
•
– Serial Onboard Programming, No External
Programming Voltage Needed
– Embedded Emulation Module (EEM)
• High-Performance Sub-1 GHz RF Transceiver
Core
– Same as in CC1101
– Wide Supply Voltage Range: 2 V to 3.6 V
– Frequency Bands: 300 MHz to 348 MHz,
389 MHz to 464 MHz, and 779 MHz to 928 MHz
– Programmable Data Rate From 0.6 kBaud to
500 kBaud
– High Sensitivity (–117 dBm at 0.6 kBaud,
–111 dBm at 1.2 kBaud, 315 MHz, 1% Packet
Error Rate)
– Excellent Receiver Selectivity and Blocking
Performance
– Programmable Output Power up to +12 dBm for
All Supported Frequencies
– 2-FSK, 2-GFSK, and MSK Supported, Also
OOK and Flexible ASK Shaping
– Flexible Support for Packet-Oriented Systems:
On-Chip Support for Sync Word Detection,
Address Check, Flexible Packet Length, and
Automatic CRC Handling
– Support for Automatic Clear Channel
Assessment (CCA) Before Transmitting (for
Listen-Before-Talk Systems)
– Digital RSSI Output
– Suited for Systems Targeting Compliance With
EN 300 220 (Europe) and
FCC CFR Part 15 (US)
– Suited for Systems Targeting Compliance With
Wireless M-Bus Standard EN 13757‑4:2005
– Support for Asynchronous and Synchronous
Serial Receive or Transmit Mode for Backward
Compatibility With Existing Radio
Communication Protocols
• Device Comparison Summarizes the Available
Family Members
Applications
Wireless Analog and Digital Sensor Systems
Heat Cost Allocators
Thermostats
•
•
AMR or AMI Metering
Smart Grid Wireless Networks
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
1.3
www.ti.com
Description
The TI CC430 family of ultra-low-power system-on-chip (SoC) microcontrollers with integrated RF
transceiver cores consists of several devices that feature different sets of peripherals targeted for a wide
range of applications. The architecture, combined with five low-power modes, is optimized to achieve
extended battery life in portable measurement applications. The devices feature the powerful MSP430
16‑bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The CC430 family provides a tight integration between the microcontroller core, its peripherals, software,
and the RF transceiver, making these true SoC solutions easy to use as well as improving performance.
The CC430F61xx series are microcontroller SoC configurations that combine the excellent performance of
the state-of-the-art CC1101 sub-1 GHz RF transceiver with the MSP430 CPUXV2, up to 32KB of insystem programmable flash memory, up to 4KB of RAM, two 16-bit timers, a high-performance 12-bit ADC
with eight external inputs plus internal temperature and battery sensors on CC430F613x devices, a
comparator, USCIs, a 128-bit AES security accelerator, a hardware multiplier, a DMA, an RTC module
with alarm capabilities, an LCD driver, and up to 44 I/O pins.
The CC430F513x series are microcontroller SoC configurations that combine the excellent performance of
the state-of-the-art CC1101 sub-1 GHz RF transceiver with the MSP430 CPUXV2, up to 32KB of insystem programmable flash memory, up to 4KB of RAM, two 16-bit timers, a high-performance 12-bit ADC
with six external inputs plus internal temperature and battery sensors, a comparator, USCIs, a 128-bit
AES security accelerator, a hardware multiplier, a DMA, an RTC module with alarm capabilities, and up to
30 I/O pins.
For complete module descriptions, see the CC430 Family User's Guide.
Device Information (1)
PACKAGE
BODY SIZE (2)
CC430F6137IRGC
VQFN (64)
9 mm × 9 mm
CC430F5137IRGZ
VQFN (48)
7 mm × 7 mm
PART NUMBER
(1)
(2)
2
For the most current part, package, and ordering information, see the Package Option Addendum in
Section 9, or see the TI website at www.ti.com.
The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 9.
Device Overview
Copyright © 2009–2018, Texas Instruments Incorporated
Submit Documentation Feedback
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
www.ti.com
1.4
SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
Functional Block Diagrams
Figure 1-1 shows the CC430F613x functional block diagram.
XIN
XOUT
MCLK
Unified
Clock
System
2x8
Comp_B
ADC12
SMCLK
Voltage
Reference
Bus
Control
Logic
2x8
I/O Ports
P1, P2
2x8 I/Os
I/O Ports
P3, P4
2x8 I/Os
PA
1x16 I/Os
PB
1x16 I/Os
REF
ACLK
DMA
Controller
3 Channel
P3.x,P4.x
P1.x,P2.x
(32 kHz)
RF_XIN
P5.x
1x8
I/O Ports
P5
1x8 I/Os
Digital RSSI
Carrier Sense
PQI,CA
LQI
MDB
Sub-1 GHz
Radio
(CC1101)
SYS
Flash
RAM
32KB
16KB
4KB
2KB
Watchdog
EEM
(S: 3+1)
CRC16
CPU Interface
MPY32
Port
Mapping
Controller
Modem
MDB
Spy-BiWire
Packet
Handler
MAB
CPUXV2
incl. 16
Registers
JTAG
Interface
RF_XOUT
(26 MHz)
MAB
Frequency
Synthesizer
Power
Mgmt
LDO,
SVM, SVS,
Brownout
TA0
TA1
5 CC
Registers
3 CC
Registers
RTC_A
USCI_A0
(UART,
IrDA, SPI)
USCI_B0
2
(SPI, I C )
LCD_B
96
Segments
1,2,3,4
Mux
AES128
Security
Encryption,
Decryption
RF, Analog
TX and RX
RF_P
RF_N
Copyright © 2017, Texas Instruments Incorporated
Figure 1-1. CC430F613x Functional Block Diagram
Device Overview
Copyright © 2009–2018, Texas Instruments Incorporated
Submit Documentation Feedback
3
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
www.ti.com
Figure 1-2 shows the CC430F612x functional block diagram.
XIN
XOUT
MCLK
Unified
Clock
System
2x8
Comp_B
Voltage
Reference
SMCLK
Bus
Control
Logic
2x8
I/O Ports
P1,P2
2x8 I/Os
I/O Ports
P3,P4
2x8 I/Os
PA
1x16 I/Os
PB
1x16 I/Os
REF
ACLK
DMA
Controller
3 Channel
P3.x,P4.x
P1.x,P2.x
(32 kHz)
RF_XIN
P5.x
1x8
I/O Ports
P5
1x8 I/Os
Digital RSSI
Carrier Sense
PQI, LQI
CCA
MDB
Sub-1 GHz
Radio
(CC1101)
SYS
EEM
(S: 3+1)
Flash
RAM
32KB
32KB
16KB
4KB
2KB
2KB
CRC16
Watchdog
CPU Interface
MPY32
Port
Mapping
Controller
Modem
MDB
Spy-BiWire
Packet
Handler
MAB
CPUXV2
incl. 16
Registers
JTAG
Interface
RF_XOUT
(26 MHz)
MAB
Frequency
Synthesizer
Power
Mgmt
LDO,
SVM, SVS,
Brownout
TA0
TA1
5 CC
Registers
3 CC
Registers
RTC_A
USCI_A0
(UART,
IrDA, SPI)
USCI_B0
2
(SPI, I C )
LCD_B
96
Segments
1,2,3,4
Mux
AES128
Security
Encryption,
Decryption
RF, Analog
TX and RX
RF_P
RF_N
Copyright © 2017, Texas Instruments Incorporated
Figure 1-2. CC430F612x Functional Block Diagram
4
Device Overview
Copyright © 2009–2018, Texas Instruments Incorporated
Submit Documentation Feedback
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
www.ti.com
SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
Figure 1-3 shows the CC430F513x functional block diagram.
XIN
XOUT
P1.x,P2.x
(32 kHz)
MCLK
Unified
Clock
System
2x8
Comp_B
ADC12
SMCLK
Voltage
Reference
DMA
Controller
3 Channel
Bus
Control
Logic
1x8
I/O Ports
P3
1x8 I/Os
I/O Ports
P1,P2
2x8 I/Os
REF
ACLK
RF_XIN
P5.x
P3.x
1x2
I/O Ports
P5
1x2 I/Os
PA
1x16 I/Os
Digital RSSI
Carrier Sense
PQI, LQI
CCA
MDB
Sub-1 GHz
Radio
(CC1101)
SYS
Flash
RAM
32KB
16KB
8KB
4KB
2KB
Watchdog
EEM
(S: 3+1)
CPU Interface
MPY32
CRC16
Port
Mapping
Controller
Modem
MDB
Spy-BiWire
Packet
Handler
MAB
CPUXV2
incl. 16
Registers
JTAG
Interface
RF_XOUT
(26 MHz)
MAB
Frequency
Synthesizer
Power
Mgmt
LDO,
SVM, SVS,
Brownout
TA0
TA1
5 CC
Registers
3 CC
Registers
RTC_A
USCI_A0
(UART,
IrDA, SPI)
USCI_B0
2
(SPI, I C)
AES128
Security
Encryption,
Decryption
RF, Analog
TX and RX
RF_P
RF_N
Copyright © 2017, Texas Instruments Incorporated
Figure 1-3. CC430F513x Functional Block Diagram
Device Overview
Copyright © 2009–2018, Texas Instruments Incorporated
Submit Documentation Feedback
5
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
www.ti.com
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from September 6, 2013 to September 17, 2018
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
6
Page
Document format and organization changes throughout, including addition of section numbering ....................... 1
Added Device Information table .................................................................................................... 2
Added Section 1.4 and moved all functional block diagrams to it .............................................................. 3
Added Section 3, Device Comparison, and moved Table 3-1 to it ............................................................. 7
Added Section 3.1, Related Products ............................................................................................. 7
Added Section 4, Terminal Configuration and Functions, and moved all pinouts and terminal functions tables to it ... 8
Added typical conditions statements at the beginning of Section 5, Specifications ....................................... 17
Added Section 5, Specifications, and moved all electrical and timing specifications to it ................................. 17
Added Section 5.2, ESD Ratings.................................................................................................. 17
Changed the MIN value of the V(DVCC_BOR_hys) parameter from 60 mV to 50 mV in Section 5.19, PMM, Brownout
Reset (BOR) ......................................................................................................................... 29
Updated notes (1) and (2) and added note (3) in Section 5.25,Wake-up Times From Low-Power Modes and
Reset ................................................................................................................................. 31
Removed ADC12DIV from the formula for the TYP value in the second row of the tCONVERT parameter in
Section 5.36, 12-Bit ADC, Timing Parameters (removed because ADC12CLK is after division)......................... 39
For the tEN_CMP parameter in Section 5.42, Comparator_B: Removed "CBPWRMD = 10" from the Test
Conditions in the first row; added second row with Test Conditions of "CBPWRMD = 10" and a MAX value of
100 µs................................................................................................................................. 44
Changed the test conditions "RF crystal oscillator only" and added note in Section 5.48, Current Consumption,
Reduced-Power Modes ............................................................................................................ 46
Corrected the link for DN013 Programming Output Power on CC1101 ..................................................... 56
Changed all instances of "bootstrap loader" to "bootloader" throughout document ........................................ 65
Corrected spelling of NMIIFG in Table 6-8, System Module Interrupt Vector Registers ................................... 70
Added Section 8, Device and Documentation Support, and moved Device Nomenclature, ESD Caution, and
Trademarks sections to it ......................................................................................................... 112
Added Section 9, Mechanical, Packaging, and Orderable Information ..................................................... 118
Revision History
Copyright © 2009–2018, Texas Instruments Incorporated
Submit Documentation Feedback
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
www.ti.com
SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
3 Device Comparison
Table 3-1 summarizes the available family members.
Table 3-1. Device Comparison (1) (2)
USCI
DEVICE
PROGRAM
(KB)
SRAM
(KB)
CC430F6137
32
4
5, 3
CC430F6135
16
2
5, 3
Timer_A
(3)
CHANNEL
A:
UART, LIN,
IrDA, SPI
CHANNEL
B:
SPI, I2C
96 seg
1
96 seg
1
LCD_B
ADC12_A
CHANNELS
COMP_B
CHANNELS
I/O
PACKAGE
1
8 ext,
4 int
8
44
64 RGC
1
8 ext,
4 int
8
44
64 RGC
(4)
CC430F6127
32
4
5, 3
96 seg
1
1
8
44
64 RGC
CC430F6126
32
2
5, 3
96 seg
1
1
N/A
8
44
64 RGC
CC430F6125
16
2
5, 3
96 seg
1
1
N/A
8
44
64 RGC
(4)
1
1
6 ext,
4 int
6
30
48 RGZ
CC430F5137
32
4
5, 3
CC430F5135
16
2
5, 3
N/A
1
1
6 ext,
4 int
6
30
48 RGZ
CC430F5133
8
2
5, 3
N/A
1
1
6 ext,
4 int
6
30
48 RGZ
(1)
(2)
(3)
(4)
3.1
N/A
N/A
For the most current device, package, and ordering information, see the Package Option Addendum in Section 9, or see the TI website
at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM
output generators available. For example, a number sequence of 5, 3 represents two instantiations of Timer_A, the first instantiation
having 5 capture/compare registers and PWM output generators, and the second instantiation having 3 capture/compare registers and
PWM output generators, respectively.
N/A = not available
Related Products
For information about other devices in this family of products or related products, see the following links.
Products for TI Microcontrollers TI's low-power and high-performance MCUs, with wired and wireless
connectivity options, are optimized for a broad range of applications.
Products for MSP430 Ultra-Low-Power Microcontrollers One platform. One ecosystem. Endless
possibilities. Enabling the connected world with innovations in ultra-low-power
microcontrollers with advanced peripherals for precise sensing and measurement.
Companion Products for CC430F6137 Review products that are frequently purchased or used in
conjunction with this product.
Reference Designs for CC430F6137 TI Designs Reference Design Library is a robust reference design
library that spans analog, embedded processor, and connectivity. Created by TI experts to
help you jump start your system design, all TI Designs include schematic or block diagrams,
BOMs, and design files to speed your time to market. Search and download designs at
ti.com/tidesigns.
Device Comparison
Copyright © 2009–2018, Texas Instruments Incorporated
Submit Documentation Feedback
7
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
www.ti.com
4 Terminal Configuration and Functions
4.1
Pin Diagrams
PJ.3/TCK
TEST/SBWTCK
RST/NMI/SBWTDIO
DVCC
AVSS
P5.1/XOUT
P5.0/XIN
AVCC
P2.6/PM_ACLK/CB6/A6
P2.7/PM_ADC12CLK/PM_DMAE0/CB7/A7
P2.5/PM_SVMOUT/CB5/A5/VREF+/VeREF+
P2.4/PM_RTCCLK/CB4/A4/VREF-/VeREF-
P2.3/PM_TA1CCR2A/CB3/A3
P2.1/PM_TA1CCR0A/CB1/A1
P2.2/PM_TA1CCR1A/CB2/A2
P2.0/PM_CBOUT1/PM_TA1CLK/CB0/A0
Figure 4-1 shows the pinout for the CC430F613x devices in the 64-pin RGC package.
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
PJ.2/TMS
P1.6/PM_UCA0TXD/PM_UCA0SIMO/R13/LCDREF
2
47
PJ.1/TDI/TCLK
P1.5/PM_UCA0RXD/PM_UCA0SOMI/R23
3
46
PJ.0/TDO
LCDCAP/R33
4
45
GUARD
R_BIAS
P1.7/PM_UCA0CLK/PM_UCB0STE/R03
5
44
6
43
AVCC_RF
P5.6/COM2/S25
7
42
AVCC_RF
P5.5/COM3/S24
8
41
P5.4/S23
9
40
RF_N
RF_P
VCORE
10
39
AVCC_RF
DVCC
11
38
AVCC_RF
P1.4/PM_UCB0CLK/PM_UCA0STE/S22
12
37
RF_XOUT
P1.3/PM_UCB0SIMO/PM_UCB0SDA/S21
13
36
RF_XIN
P1.2/PM_UCB0SOMI/PM_UCB0SCL/S20
14
35
P5.2/S0
P1.1/PM_RFGDO2/S19
15
34
P5.3/S1
P1.0/PM_RFGDO0/S18
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P4.0/S2
P4.2/S4
P4.3/S5
P4.4/S6
P4.5/S7
P4.6/S8
DVCC
P4.7/S9
P3.0/PM_CBOUT0/PM_TA0CLK/S10
P3.1/PM_TA0CCR0A/S11
P3.2/PM_TA0CCR1A/S12
P3.3/PM_TA0CCR2A/S13
P3.4/PM_TA0CCR3A/S14
P3.5/PM_TA0CCR4A/S15
P3.6/PM_RFGDO1/S16
P3.7/PM_SMCLK/S17
CC430F613x
P4.1/S3
COM0
P5.7/COM1/S26
VSS
Exposed die
attached pad
CAUTION: The LCDCAP/R33 must be connected to VSS if not used.
NOTE: The secondary digital functions on ports P1, P2, and P3 are fully mappable. This pinout shows only the default
mapping. See Table 6-6 for details.
Figure 4-1. 64-Pin RGC Package (Top View), CC430F613x
8
Terminal Configuration and Functions
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SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
PJ.3/TCK
TEST/SBWTCK
RST/NMI/SBWTDIO
DVCC
AVSS
P5.1/XOUT
P5.0/XIN
AVCC
P2.6/PM_ACLK/CB6
P2.7/PM_DMAE0/CB7
P2.5/PM_SVMOUT/CB5
P2.4/PM_RTCCLK/CB4
P2.3/PM_TA1CCR2A/CB3
P2.2/PM_TA1CCR1A/CB2
P2.1/PM_TA1CCR0A/CB1
P2.0/PM_CBOUT1/PM_TA1CLK/CB0
Figure 4-2 shows the pinout for the CC430F612x devices in the 64-pin RGC package.
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
PJ.2/TMS
P1.6/PM_UCA0TXD/PM_UCA0SIMO/R13/LCDREF
2
47
PJ.1/TDI/TCLK
P1.5/PM_UCA0RXD/PM_UCA0SOMI/R23
3
46
PJ.0/TDO
LCDCAP/R33
4
45
GUARD
R_BIAS
P1.7/PM_UCA0CLK/PM_UCB0STE/R03
5
44
6
43
AVCC_RF
P5.6/COM2/S25
7
42
AVCC_RF
P5.5/COM3/S24
8
41
P5.4/S23
9
40
RF_N
RF_P
VCORE
10
39
AVCC_RF
DVCC
11
38
AVCC_RF
P1.4/PM_UCB0CLK/PM_UCA0STE/S22
12
37
RF_XOUT
P1.3/PM_UCB0SIMO/PM_UCB0SDA/S21
13
36
RF_XIN
P1.2/PM_UCB0SOMI/PM_UCB0SCL/S20
14
35
P5.2/S0
P1.1/PM_RFGDO2/S19
15
34
P5.3/S1
P1.0/PM_RFGDO0/S18
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P4.0/S2
P4.2/S4
P4.3/S5
P4.4/S6
P4.5/S7
P4.6/S8
DVCC
P4.7/S9
P3.0/PM_CBOUT0/PM_TA0CLK/S10
P3.1/PM_TA0CCR0A/S11
P3.2/PM_TA0CCR1A/S12
P3.3/PM_TA0CCR2A/S13
P3.4/PM_TA0CCR3A/S14
P3.5/PM_TA0CCR4A/S15
P3.6/PM_RFGDO1/S16
P3.7/PM_SMCLK/S17
CC430F612x
P4.1/S3
COM0
P5.7/COM1/S26
VSS
Exposed die
attached pad
CAUTION: The LCDCAP/R33 must be connected to VSS if not used.
NOTE: The secondary digital functions on ports P1, P2, and P3 are fully mappable. This pinout shows only the default
mapping. See Table 6-6 for details.
Figure 4-2. 64-Pin RGC Package (Top View), CC430F612x
Terminal Configuration and Functions
Copyright © 2009–2018, Texas Instruments Incorporated
Submit Documentation Feedback
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CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
www.ti.com
PJ.2/TMS
TEST/SBWTCK
PJ.3/TCK
RST/NMI/SBWTDIO
AVSS
DVCC
P5.0/XIN
P5.1/XOUT
P2.5/PM_SVMOUT/CB5/A5/VREF+/VeREF+
AVCC
P2.3/PM_TA1CCR2A/CB3/A3
P2.4/PM_RTCCLK/CB4/A4/VREF-/VeREF-
Figure 4-3 shows the pinout for the CC430F513x devices in the 48-pin RGZ package.
1
44 43 42 41 40 39 38 37
36
P2.1/PM_TA1CCR0A/CB1/A1
2
35
PJ.0/TDO
P2.0/PM_CBOUT1/PM_TA1CLK/CB0/A0
3
34
GUARD
P1.7/PM_UCA0CLK/PM_UCB0STE
4
33
R_BIAS
48 47 46 45
P2.2/PM_TA1CCR1A/CB2/A2
PJ.1/TDI/TCLK
P1.6/PM_UCA0TXD/PM_UCA0SIMO
5
32
AVCC_RF
P1.5/PM_UCA0RXD/PM_UCA0SOMI
6
31
AVCC_RF
VCORE
7
30
RF_N
DVCC
8
29
RF_P
P1.4/PM_UCB0CLK/PM_UCA0STE
9
28
AVCC_RF
P1.3/PM_UCB0SIMO/PM_UCB0SDA
10
27
AVCC_RF
P1.2/PM_UCB0SOMI/PM_UCB0SCL
11
26
RF_XOUT
CC430F513x
P2.6/PM_ACLK
DVCC
P2.7/PM_ADC12CLK/PM_DMAE0
P3.1/PM_TA0CCR0A
P3.0/PM_CBOUT0/PM_TA0CLK
P3.2/PM_TA0CCR1A
P3.4/PM_TA0CCR3A
25
17 18 19 20 21 22 23 24
P3.3/PM_TA0CCR2A
P3.6/PM_RFGDO1
P3.5/PM_TA0CCR4A
P3.7/PM_SMCLK
12
13 14 15 16
P1.0/PM_RFGDO0
P1.1/PM_RFGDO2
RF_XIN
VSS
Exposed die
attached pad
NOTE: The secondary digital functions on ports P1, P2, and P3 are fully mappable. This pinout shows only the default
mapping. See Table 6-6 for details.
Figure 4-3. 48-Pin RGZ Package (Top View), CC430F513x
10
Terminal Configuration and Functions
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4.2
SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
Signal Descriptions
Table 4-1 describes the signals for the CC430F613x and CC430F612x devices. See Table 4-2 for the
CC430F513x devices.
Table 4-1. CC430F613x and CC430F612x Terminal Functions
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
P1.7/ PM_UCA0CLK/
PM_UCB0STE/ R03
1
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 clock input/output; USCI_B0 SPI slave transmit enable
Input/output port of lowest analog LCD voltage (V5)
P1.6/ PM_UCA0TXD/
PM_UCA0SIMO/ R13/LCDREF
2
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in master out
Input/output port of third most positive analog LCD voltage (V3 or V4)
External reference voltage input for regulated LCD voltage
P1.5/ PM_UCA0RXD/
PM_UCA0SOMI/ R23
3
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 UART receive data; USCI_A0 SPI slave out master in
Input/output port of second most positive analog LCD voltage (V2)
LCDCAP/ R33
4
I/O
LCD capacitor connection
Input/output port of most positive analog LCD voltage (V1)
CAUTION: Must be connected to VSS if not used.
COM0
5
O
LCD common output COM0 for LCD backplane
P5.7/ COM1/ S26
6
I/O
General-purpose digital I/O
LCD common output COM1 for LCD backplane
LCD segment output S26
P5.6/ COM2/ S25
7
I/O
General-purpose digital I/O
LCD common output COM2 for LCD backplane
LCD segment output S25
P5.5/ COM3/ S24
8
I/O
General-purpose digital I/O
LCD common output COM3 for LCD backplane
LCD segment output S24
P5.4/ S23
9
I/O
General-purpose digital I/O
LCD segment output S23
VCORE
10
Regulated core power supply
DVCC
11
Digital power supply
P1.4/ PM_UCB0CLK/
PM_UCA0STE/ S22
12
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 clock input/output
Default mapping: USCI_A0 SPI slave transmit enable
LCD segment output S22
P1.3/ PM_UCB0SIMO/
PM_UCB0SDA/ S21
13
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 SPI slave in master out
Default mapping: USCI_B0 I2C data
LCD segment output S21
P1.2/ PM_UCB0SOMI/
PM_UCB0SCL/ S20
14
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 SPI slave out master in
Default mapping: UCSI_B0 I2C clock
LCD segment output S20
P1.1/ PM_RFGDO2/ S19
15
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Radio GDO2 output
LCD segment output S19
P1.0/ PM_RFGDO0/ S18
16
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Radio GDO0 output
LCD segment output S18
P3.7/ PM_SMCLK/ S17
17
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: SMCLK output
LCD segment output S17
P3.6/ PM_RFGDO1/ S16
18
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: Radio GDO1 output
LCD segment output S16
(1)
I = input, O = output
Terminal Configuration and Functions
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Table 4-1. CC430F613x and CC430F612x Terminal Functions (continued)
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
P3.5/ PM_TA0CCR4A/ S15
19
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR4 compare output or capture input
LCD segment output S15
P3.4/ PM_TA0CCR3A/ S14
20
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR3 compare output or capture input
LCD segment output S14
P3.3/ PM_TA0CCR2A/ S13
21
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR2 compare output or capture input
LCD segment output S13
P3.2/ PM_TA0CCR1A/ S12
22
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR1 compare output or capture input
LCD segment output S12
P3.1/ PM_TA0CCR0A/ S11
23
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR0 compare output or capture input
LCD segment output S11
P3.0/ PM_CBOUT0/ PM_TA0CLK/
S10
24
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: Comparator_B output
Default mapping: TA0 clock input
LCD segment output S10
DVCC
25
P4.7/ S9
26
I/O
General-purpose digital I/O
LCD segment output S9
P4.6/ S8
27
I/O
General-purpose digital I/O
LCD segment output S8
P4.5/ S7
28
I/O
General-purpose digital I/O
LCD segment output S7
P4.4/ S6
29
I/O
General-purpose digital I/O
LCD segment output S6
P4.3/ S5
30
I/O
General-purpose digital I/O
LCD segment output S5
P4.2/ S4
31
I/O
General-purpose digital I/O
LCD segment output S4
P4.1/ S3
32
I/O
General-purpose digital I/O
LCD segment output S3
P4.0/ S2
33
I/O
General-purpose digital I/O
LCD segment output S2
P5.3/ S1
34
I/O
General-purpose digital I/O
LCD segment output S1
P5.2/ S0
35
I/O
General-purpose digital I/O
LCD segment output S0
RF_XIN
36
I
Input terminal for RF crystal oscillator, or external clock input
RF_XOUT
37
O
Output terminal for RF crystal oscillator
AVCC_RF
38
Radio analog power supply
AVCC_RF
39
Radio analog power supply
RF_P
40
RF
I/O
Positive RF input to LNA in receive mode
Positive RF output from PA in transmit mode
RF_N
41
RF
I/O
Negative RF input to LNA in receive mode
Negative RF output from PA in transmit mode
AVCC_RF
42
Radio analog power supply
AVCC_RF
43
Radio analog power supply
RBIAS
44
External bias resistor for radio reference current
GUARD
45
Power supply connection for digital noise isolation
PJ.0/ TDO
46
12
Digital power supply
I/O
General-purpose digital I/O
Test data output port
Terminal Configuration and Functions
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Table 4-1. CC430F613x and CC430F612x Terminal Functions (continued)
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
PJ.1/ TDI/ TCLK
47
I/O
General-purpose digital I/O
Test data input or test clock input
PJ.2/ TMS
48
I/O
General-purpose digital I/O
Test mode select
PJ.3/ TCK
49
I/O
General-purpose digital I/O
Test clock
TEST/ SBWTCK
50
I
RST/NMI/ SBWTDIO
51
I/O
DVCC
52
Digital power supply
AVSS
53
Analog ground supply for ADC12
P5.1/ XOUT
54
I/O
General-purpose digital I/O
Output terminal of crystal oscillator XT1
P5.0/ XIN
55
I/O
General-purpose digital I/O
Input terminal for crystal oscillator XT1
AVCC
56
Analog power supply
P2.7/ PM_ADC12CLK/
PM_DMAE0/ CB7 (/A7)
57
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: ADC12CLK output
Default mapping: DMA external trigger input
Comparator_B input CB7
Analog input A7 – 12-bit ADC (CC430F613x only)
P2.6/ PM_ACLK/ CB6 (/A6)
58
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: ACLK output
Comparator_B input CB6
Analog input A6 – 12-bit ADC (CC430F613x only)
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: SVM output
Comparator_B input CB5
Analog input A5 – 12-bit ADC (CC430F613x only)
Output of reference voltage to the ADC (CC430F613x only)
Input for an external reference voltage to the ADC (CC430F613x only)
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: RTCCLK output
Comparator_B input CB4
Analog input A4 – 12-bit ADC (CC430F613x only)
Negative terminal for the ADC reference voltage for both sources, the internal reference
voltage, or an external applied reference voltage (CC430F613x only)
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: TA1 CCR2 compare output or capture input
Comparator_B input CB3
Analog input A3 – 12-bit ADC (CC430F613x only)
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: TA1 CCR1 compare output or capture input
Comparator_B input CB2
Analog input A2 – 12-bit ADC (CC430F613x only)
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: TA1 CCR0 compare output or capture input
Comparator_B input CB1
Analog input A1 – 12-bit ADC (CC430F613x only)
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Comparator_B output
Default mapping: TA1 clock input
Comparator_B input CB0
Analog input A0 – 12-bit ADC (CC430F613x only)
P2.5/ PM_SVMOUT/ CB5
(/A5/ VREF+/ VeREF+)
P2.4/ PM_RTCCLK/ CB4
(/A4/ VREF-/ VeREF-)
P2.3/ PM_TA1CCR2A/ CB3 (/A3)
P2.2/ PM_TA1CCR1A/ CB2 (/A2)
P2.1/ PM_TA1CCR0A/ CB1 (/A1)
P2.0/ PM_CBOUT1/ PM_TA1CLK/
CB0 (/A0)
59
60
61
62
63
64
VSS, Exposed die attach pad
Test mode pin – select digital I/O on JTAG pins
Spy-Bi-Wire input clock
Reset input active low
Nonmaskable interrupt input
Spy-Bi-Wire data input/output
Ground supply
CAUTION: The exposed die attach pad must be connected to a solid ground plane as
this is the ground connection for the chip.
Terminal Configuration and Functions
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Table 4-2 describes the signals for the CC430F513x devices. See Table 4-1 for the CC430F613x and
CC430F612x devices.
Table 4-2. CC430F513x Terminal Functions
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
P2.2/ PM_TA1CCR1A/ CB2/ A2
1
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: TA1 CCR1 compare output or capture input
Comparator_B input CB2
Analog input A2 – 12-bit ADC
P2.1/ PM_TA1CCR0A/ CB1/ A1
2
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: TA1 CCR0 compare output or capture input
Comparator_B input CB1
Analog input A1 – 12-bit ADC
P2.0/ PM_CBOUT1/ PM_TA1CLK/
CB0/ A0
3
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Comparator_B output
Default mapping: TA1 clock input
Comparator_B input CB0
Analog input A0 – 12-bit ADC
P1.7/ PM_UCA0CLK/
PM_UCB0STE
4
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 clock input/output
Default mapping: USCI_B0 SPI slave transmit enable
P1.6/ PM_UCA0TXD/
PM_UCA0SIMO
5
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in master out
P1.5/ PM_UCA0RXD/
PM_UCA0SOMI
6
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 UART receive data
Default mapping: USCI_A0 SPI slave out master in
VCORE
7
Regulated core power supply
DVCC
8
Digital power supply
P1.4/ PM_UCB0CLK/
PM_UCA0STE
9
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 clock input/output
Default mapping: USCI_A0 SPI slave transmit enable
P1.3/ PM_UCB0SIMO/
PM_UCB0SDA
10
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 SPI slave in master out
Default mapping: USCI_B0 I2C data
P1.2/ PM_UCB0SOMI/
PM_UCB0SCL
11
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 SPI slave out master in
Default mapping: UCSI_B0 I2C clock
P1.1/ PM_RFGDO2
12
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Radio GDO2 output
P1.0/ PM_RFGDO0
13
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Radio GDO0 output
P3.7/ PM_SMCLK
14
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: SMCLK output
P3.6/ PM_RFGDO1
15
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: Radio GDO1 output
P3.5/ PM_TA0CCR4A
16
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR4 compare output or capture input
P3.4/ PM_TA0CCR3A
17
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR3 compare output or capture input
P3.3/ PM_TA0CCR2A
18
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR2 compare output or capture input
P3.2/ PM_TA0CCR1A
19
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR1 compare output or capture input
P3.1/ PM_TA0CCR0A
20
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR0 compare output or capture input
P3.0/ PM_CBOUT0/ PM_TA0CLK
21
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: Comparator_B output
Default mapping: TA0 clock input
(1)
14
I = input, O = output
Terminal Configuration and Functions
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Table 4-2. CC430F513x Terminal Functions (continued)
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
DVCC
22
P2.7/ PM_ADC12CLK/
PM_DMAE0
23
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: ADC12CLK output
Default mapping: DMA external trigger input
P2.6/ PM_ACLK
24
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: ACLK output
RF_XIN
25
I
Input terminal for RF crystal oscillator, or external clock input
RF_XOUT
26
O
Output terminal for RF crystal oscillator
AVCC_RF
27
Radio analog power supply
AVCC_RF
28
Radio analog power supply
RF_P
29
RF
I/O
Positive RF input to LNA in receive mode
Positive RF output from PA in transmit mode
RF_N
30
RF
I/O
Negative RF input to LNA in receive mode
Negative RF output from PA in transmit mode
AVCC_RF
31
Radio analog power supply
AVCC_RF
32
Radio analog power supply
RBIAS
33
External bias resistor for radio reference current
GUARD
34
Power supply connection for digital noise isolation
PJ.0/ TDO
35
I/O
General-purpose digital I/O
Test data output port
PJ.1/ TDI/ TCLK
36
I/O
General-purpose digital I/O
Test data input or test clock input
PJ.2/ TMS
37
I/O
General-purpose digital I/O
Test mode select
PJ.3/ TCK
38
I/O
General-purpose digital I/O
Test clock
TEST/ SBWTCK
39
I
RST/NMI/ SBWTDIO
40
I/O
DVCC
41
Digital power supply
AVSS
42
Analog ground supply for ADC12
P5.1/ XOUT
43
I/O
General-purpose digital I/O
Output terminal of crystal oscillator XT1
P5.0/ XIN
44
I/O
General-purpose digital I/O
Input terminal for crystal oscillator XT1
AVCC
45
Analog power supply
46
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: SVM output
Comparator_B input CB5
Analog input A5 – 12-bit ADC
Output of reference voltage to the ADC
Input for an external reference voltage to the ADC
P2.5/ PM_SVMOUT/ CB5/
A5/ VREF+/ VeREF+
Digital power supply
Test mode pin – select digital I/O on JTAG pins
Spy-Bi-Wire input clock
Reset input active low
Nonmaskable interrupt input
Spy-Bi-Wire data input/output
P2.4/ PM_RTCCLK/ CB4/
A4/ VREF-/ VeREF-
47
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: RTCCLK output
Comparator_B input CB4
Analog input A4 – 12-bit ADC
Negative terminal for the ADC reference voltage for both sources, the internal reference
voltage, or an external applied reference voltage
P2.3/ PM_TA1CCR2A/ CB3/ A3
48
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: TA1 CCR2 compare output or capture input
Comparator_B input CB3
Analog input A3 – 12-bit ADC
Terminal Configuration and Functions
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Table 4-2. CC430F513x Terminal Functions (continued)
TERMINAL
NAME
NO.
I/O (1)
VSS, Exposed die attach pad
16
DESCRIPTION
Ground supply
The exposed die attach pad must be connected to a solid ground plane as this is
the ground connection for the chip.
Terminal Configuration and Functions
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5 Specifications
All graphs in this section are for typical conditions, unless otherwise noted.
Typical (TYP) values are specified at VCC = 3.3 V and TA = 25°C, unless otherwise noted.
Absolute Maximum Ratings (1)
5.1
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
Voltage applied at DVCC and AVCC pins to VSS
–0.3
4.1
V
Voltage applied to any pin (excluding VCORE, RF_P, RF_N, and R_BIAS) (2)
–0.3
VCC + 0.3
(4.1 V Maximum)
V
–0.3
2.0
V
10
dBm
Voltage applied to VCORE, RF_P, RF_N, and R_BIAS
(2)
Input RF level at pins RF_P and RF_N
Diode current at any device terminal
Storage temperature, Tstg (3)
–55
Maximum junction temperature, TJ
(1)
(2)
(3)
UNIT
±2
mA
150
°C
95
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2
ESD Ratings
VALUE
V(ESD)
(1)
(2)
5.3
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±250
Recommended Operating Conditions
1.8
3.6
PMMCOREVx = 1
2.0
3.6
Supply voltage range applied at all DVCC and
AVCC pins (1) during program execution, flash
programming, and radio operation with PMM
default settings (2) (3)
PMMCOREVx = 2
2.2
3.6
PMMCOREVx = 3
2.4
3.6
PMMCOREVx = 2,
SVSHRVLx = SVSHRRRLx = 1
or SVSHE = 0
2.0
3.6
Supply voltage applied at the exposed die attach VSS and AVSS pin
TA
Operating free-air temperature
(4)
MAX
PMMCOREVx = 0
(default after POR)
VSS
(2)
(3)
NOM
Supply voltage range applied at all DVCC and
AVCC pins (1) during program execution and
flash programming with PMM default settings,
Radio is not operational with PMMCOREVx = 0
or 1 (2) (3)
Supply voltage range applied at all DVCC and
AVCC pins (1) during program execution, flash
programming and radio operation with
PMMCOREVx = 2, high-side SVS level lowered
(SVSHRVL = SVSMHRRL = 1) or high-side SVS
disabled (SVSHE = 0) (2) (3) (4)
(1)
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
MIN
VCC
UNIT
0
–40
UNIT
V
V
85
°C
TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the Section 5.21 threshold parameters for
the exact values and further details.
Lowering the high-side SVS level or disabling the high-side SVS might cause the LDO to operate out of regulation, but the core voltage
will still stay within its limits and is still supervised by the low-side SVS, ensuring reliable operation.
Specifications
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CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
www.ti.com
Recommended Operating Conditions (continued)
MIN
TJ
Operating junction temperature
Recommended capacitor at VCORE
CDVCC/
CVCORE
Capacitor ratio of capacitor at DVCC to capacitor at VCORE
PINT
470
Processor (MCLK) frequency (6) (see Figure 5-1)
8
PMMCOREVx = 1
0
12
PMMCOREVx = 2
0
16
PMMCOREVx = 3
0
Maximum allowed power dissipation, PMAX > PIO + PINT
MHz
20
Internal power dissipation
PMAX
°C
10
0
I/O power dissipation of I/O pins powered by DVCC
UNIT
nF
PMMCOREVx = 0
(default condition)
PIO
(5)
(6)
MAX
85
(5)
CVCORE
fSYSTEM
NOM
–40
VCC × IDVCC
W
(VCC – VIOH) ×
IIOH + VIOL × IIOL
W
(TJ – TA) / θJA
W
A capacitor tolerance of ±20% or better is required.
Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
System Frequency - MHz
20
3
16
2
2, 3
1
1, 2
1, 2, 3
0, 1
0, 1, 2
0, 1, 2, 3
12
8
0
0
1.8
2.0
2.2
2.4
3.6
Supply Voltage - V
NOTE: The numbers within the fields are the supported PMMCOREVx settings.
Figure 5-1. Maximum System Frequency
18
Specifications
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5.4
SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted) (1)
(2) (3)
FREQUENCY (fDCO = fMCLK = fSMCLK)
PARAMETER
IAM,
IAM,
(1)
(2)
(3)
(4)
(5)
5.5
Flash
RAM
(4)
(5)
EXECUTION
MEMORY
Flash
RAM
VCC
PMMCOREVx
3V
3V
1 MHz
8 MHz
12 MHz
TYP
MAX
TYP
MAX
0
0.23
0.26
1.35
1.60
1
0.25
0.28
2
0.27
3
0
16 MHz
TYP
MAX
TYP
MAX
1.55
2.30
2.65
0.30
1.75
2.60
3.45
3.90
0.28
0.32
1.85
0.18
0.20
0.95
2.75
3.65
1
0.20
0.22
1.10
1.60
2
0.21
0.24
1.20
1.80
2.40
3
0.22
0.25
1.30
1.90
2.50
20 MHz
TYP
UNIT
MAX
mA
4.55
5.10
1.10
1.85
mA
2.70
3.10
3.60
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
Characterized with program executing typical data processing.
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0.
Active mode supply current when program executes in flash at a nominal supply voltage of 3 V.
Active mode supply current when program executes in RAM at a nominal supply voltage of 3 V.
Typical Characteristics – Active Mode Supply Currents
5
IAM – Active Mode Supply Current – mA
VCC = 3.0 V
PMMVCOREx = 3
4
3
PMMVCOREx = 2
2
PMMVCOREx = 1
1
PMMVCOREx = 0
0
0
5
10
15
20
MCLK Frequency – MHz
Figure 5-2. Active Mode Supply Current vs MCLK Frequency
Specifications
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CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
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SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
5.6
www.ti.com
Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
(2)
TEMPERATURE (TA)
PARAMETER
VCC
ILPM0,1MHz
Low-power mode 0 (3)
(4)
ILPM2
Low-power mode 2 (5)
(4)
ILPM3,XT1LF
ILPM3,VLO
ILPM4
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
20
Low-power mode 3, crystal
mode (6) (4)
Low-power mode 3,
VLO mode (7) (4)
Low-power mode 4 (8)
–40°C
25°C
60°C
85°C
UNIT
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
2.2 V
0
80
100
80
100
80
100
80
100
3V
3
90
110
90
110
90
110
90
110
2.2 V
0
6.5
11
6.5
11
6.5
11
6.5
11
3V
3
7.5
12
7.5
12
7.5
12
7.5
12
0
1.8
2.0
2.6
3.0
4.0
4.4
5.9
1
1.9
2.1
3.2
4.8
2
2.0
2.2
3.4
5.1
3
2.0
2.2
2.9
3.5
4.8
5.3
7.4
0
0.9
1.1
2.3
2.1
3.7
3.5
5.6
1
1.0
1.2
2.3
3.9
2
1.1
1.3
2.5
4.2
3
1.1
1.3
2.6
2.6
4.5
4.4
7.1
0
0.8
1.0
2.2
2.0
3.6
3.4
5.5
1
0.9
1.1
2.2
3.8
2
1.0
1.2
2.4
4.1
3
1.0
1.2
3V
3V
(4)
PMMCOREVx
3V
2.5
2.5
4.4
4.3
µA
µA
µA
µA
µA
7.0
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz
Current for brownout, high-side supervisor (SVSH) normal mode included. Low-side supervisor (SVSL) and low-side monitor (SVML)
disabled. High-side monitor (SVMH) disabled. RAM retention enabled.
Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz, DCO setting =
1 MHz operation, DCO bias generator enabled.
Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
Current for watchdog timer and RTC clocked by ACLK included. ACLK = VLO.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
Specifications
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5.7
SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
Typical Characteristics – Low-Power Mode Supply Currents
5
5
VCC = 3.0 V
4
ILPM4 - LPM4 Supply Current - µA
ILPM3,XT1LF - LPM3 Supply Current - µA
VCC = 3.0 V
3
PMMCOREVx = 3
2
PMMCOREVx = 0
1
4
3
2
PMMCOREVx = 3
1
PMMCOREVx = 0
0
0
-40
-20
0
20
40
60
80
TA - Free-Air Temperature - °C
Figure 5-3. LPM3 Supply Current vs Temperature
-40
-20
0
20
40
60
80
TA - Free-Air Temperature - °C
Figure 5-4. LPM4 Supply Current vs Temperature
Specifications
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CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
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SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
5.8
www.ti.com
Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
(2)
TEMPERATURE (TA)
PARAMETER
VCC
PMMCOREVx
–40°C
TYP
ILPM3
LCD,
ext. bias
ILPM3
LCD,
int. bias
Low-power mode 3
(LPM3) current, LCD 4mux mode, external
biasing (3) (4)
Low-power mode 3
(LPM3) current, LCD 4mux mode, internal
biasing, charge pump
disabled (3) (5)
3V
3V
2.2 V
ILPM3
LCD,CP
(1)
(2)
(3)
(4)
(5)
(6)
5.9
Low-power mode 3
(LPM3) current, LCD 4mux mode, internal
biasing, charge pump
enabled (3) (6)
3V
MAX
25°C
TYP
60°C
MAX
TYP
85°C
MAX
0
2.2
2.4
3.5
4.9
1
2.3
2.5
3.7
5.3
2
2.4
2.6
3.9
5.6
3
2.4
2.6
4.0
5.8
0
3.1
3.3
4.3
5.8
1
3.2
3.4
4.5
6.2
2
3.3
3.5
4.7
6.5
3
3.3
3.5
4.8
6.7
0
4.0
1
4.1
2
4.2
0
4.2
1
4.3
2
4.5
3
4.5
4.0
4.3
UNIT
MAX
µA
7.4
µA
8.9
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
Current for brownout, high-side supervisor (SVSH) normal mode included. Low-side supervisor (SVSL) and low-side monitor (SVML)
disabled. High-side monitor (SVMH) disabled. RAM retention enabled.
LCDMx = 11 (4-mux mode), LCDREXT = 1, LCDEXTBIAS = 1 (external biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump
disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Current through external resistors not included (voltage levels are supplied by test equipment).
Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.
LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump
disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.
LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge pump
enabled), VLCDx = 1000 (VLCD = 3 V, typical), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.
Thermal Resistance Characteristics, CC430F51xx
PACKAGE
θJA
TYP
Junction-to-ambient thermal resistance, still air
Low-K board
High-K board
48 QFN (RGZ)
VALUE
98°C/W
28°C/W
5.10 Thermal Resistance Characteristics, CC430F61xx
PACKAGE
θJA
22
Junction-to-ambient thermal resistance, still air
Low-K board
High-K board
Specifications
64 QFN (RGC)
VALUE
83°C/W
26°C/W
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SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
5.11 Digital Inputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup or pulldown resistor
For pullup: VIN = VSS
For pulldown: VIN = VCC
CI
Input capacitance
VIN = VSS or VCC
Ilkg(Px.y)
High-impedance leakage current
See
t(int)
External interrupt timing (external trigger
pulse duration to set interrupt flag) (3)
Ports with interrupt capability [see
block diagram (Section 1.4) and
terminal function descriptions
(Section 4.2)]
(1)
(2)
(3)
(1) (2)
VCC
MIN
1.8 V
0.80
1.40
3V
1.50
2.10
1.8 V
0.45
1.00
3V
0.75
1.65
1.8 V
0.3
0.8
3V
0.4
1.0
20
TYP
35
MAX
1.8 V, 3 V
V
V
V
50
kΩ
±50
nA
5
1.8 V, 3 V
UNIT
pF
20
ns
The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int).
Specifications
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SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
www.ti.com
5.12 Digital Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –1 mA, PxDS.y = 0
High-level output voltage,
reduced drive strength (1)
VOH
VCC
(2)
1.8 V
I(OHmax) = –3 mA, PxDS.y = 0 (3)
I(OHmax) = –2 mA, PxDS.y = 0 (2)
3V
I(OHmax) = –6 mA, PxDS.y = 0 (3)
I(OLmax) = 1 mA, PxDS.y = 0
Low-level output voltage,
reduced drive strength (1)
VOL
(2)
1.8 V
I(OLmax) = 3 mA, PxDS.y = 0 (3)
I(OLmax) = 2 mA, PxDS.y = 0 (2)
3V
I(OLmax) = 6 mA, PxDS.y = 0 (3)
I(OHmax) = –3 mA, PxDS.y = 1 (2)
High-level output voltage,
full drive strength
VOH
1.8 V
I(OHmax) = –10 mA, PxDS.y = 1 (3)
I(OHmax) = –5 mA, PxDS.y = 1
(2)
3V
I(OHmax) = –15 mA, PxDS.y = 1 (3)
I(OLmax) = 3 mA, PxDS.y = 1 (2)
Low-level output voltage,
full drive strength
VOL
1.8 V
I(OLmax) = 10 mA, PxDS.y = 1 (3)
I(OLmax) = 5 mA, PxDS.y = 1
(2)
3V
I(OLmax) = 15 mA, PxDS.y = 1 (3)
Port output frequency
(with load)
fPx.y
fPort_CLK
(1)
(2)
(3)
(4)
(5)
24
Clock output frequency
CL = 20 pF, RL
CL = 20 pF (5)
(4) (5)
MIN
MAX
VCC – 0.25
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.60
VCC
UNIT
V
VSS VSS + 0.25
VSS VSS + 0.60
VSS VSS + 0.25
V
VSS VSS + 0.60
VCC – 0.25
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.60
VCC
V
VSS VSS + 0.25
VSS VSS + 0.60
VSS VSS + 0.25
V
VSS VSS + 0.60
VCC = 1.8 V,
PMMCOREVx = 0
16
VCC = 3 V,
PMMCOREVx = 2
25
VCC = 1.8 V,
PMMCOREVx = 0
16
VCC = 3 V,
PMMCOREVx = 2
25
MHz
MHz
Selecting reduced drive strength may reduce EMI.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
A resistive divider with 2 × R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For full
drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
Specifications
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SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
5.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
8
V CC = 3.0 V
P4.3
IOL - Typical Low-Level Output Current - mA
IOL - Typical Low-Level Output Current - mA
25
TA = 25°C
20
TA = 85°C
15
10
5
0
7
TA = 25°C
6
TA = 85°C
5
4
3
2
1
0
0
0.5
1
1.5
2
2.5
3
0
3.5
V OL - Low-Level Output Voltage - V
Figure 5-5. Typical Low-Level Output Current vs Low-Level
Output Voltage
0
IOH - Typical High-Level Output Current - mA
V CC = 3.0 V
P4.3
-5
-10
-15
TA = 85°C
-20
TA = 25°C
-25
0.5
1
1.5
2
V OL - Low-Level Output Voltage - V
Figure 5-6. Typical Low-Level Output Current vs Low-Level
Output Voltage
0
IOH - Typical High-Level Output Current - mA
V CC = 1.8 V
P4.3
V CC = 1.8 V
P4.3
-1
-2
-3
-4
-5
TA = 85°C
-6
TA = 25°C
-7
-8
0
0.5
1
1.5
2
2.5
3
3.5
V OH - High-Level Output Voltage - V
Figure 5-7. Typical High-Level Output Current vs High-Level
Output Voltage
0
0.5
1
1.5
2
V OH - High-Level Output Voltage - V
Figure 5-8. Typical High-Level Output Current vs High-Level
Output Voltage
Specifications
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www.ti.com
5.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
25
V CC = 3.0 V
P4.3
TA = 25°C
IOL - Typical Low-Level Output Current - mA
IOL - Typical Low-Level Output Current - mA
60
50
TA = 85°C
40
30
20
10
0
0.5
1
1.5
2
2.5
3
TA = 85°C
15
10
5
3.5
V OL - Low-Level Output Voltage - V
Figure 5-9. Typical Low-Level Output Current vs Low-Level
Output Voltage
0
0.5
1
1.5
2
V OL - Low-Level Output Voltage - V
Figure 5-10. Typical Low-Level Output Current vs Low-Level
Output Voltage
0
0
V CC = 3.0 V
P4.3
IOH - Typical High-Level Output Current - mA
IOH - Typical High-Level Output Current - mA
TA = 25°C
20
0
0
-10
-20
-30
-40
TA = 85°C
-50
TA = 25°C
-60
V CC = 1.8 V
P4.3
-5
-10
-15
TA = 85°C
-20
TA = 25°C
-25
0
0.5
1
1.5
2
2.5
3
3.5
V OH - High-Level Output Voltage - V
Figure 5-11. Typical High-Level Output Current vs High-Level
Output Voltage
26
V CC = 1.8 V
P4.3
0
0.5
1
1.5
2
V OH - High-Level Output Voltage - V
Figure 5-12. Typical High-Level Output Current vs High-Level
Output Voltage
Specifications
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SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
5.15 Crystal Oscillator, XT1, Low-Frequency Mode (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
TA = 25°C
ΔIDVCC.LF
Differential XT1 oscillator crystal
current consumption from lowest
drive setting, LF mode
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 2,
TA = 25°C
0.170
32768
XTS = 0, XT1BYPASS = 0
fXT1,LF,SW
XT1 oscillator logic-level squarewave input frequency, LF mode
XTS = 0, XT1BYPASS = 1 (2)
OALF
3V
0.290
XT1 oscillator crystal frequency,
LF mode
(3)
10
CL,eff
fFault,LF
tSTART,LF
210
XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,LF = 32768 Hz, CL,eff = 12 pF
300
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
12.0
Oscillator fault frequency,
LF mode (7)
XTS = 0 (8)
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
TA = 25°C, CL,eff = 6 pF
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C, CL,eff = 12 pF
µA
Hz
50
kHz
2
5.5
Duty cycle, LF mode
UNIT
kΩ
XTS = 0, XCAPx = 1
XTS = 0, Measured at ACLK,
fXT1,LF = 32768 Hz
Start-up time, LF mode
32.768
XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,LF = 32768 Hz, CL,eff = 6 pF
XTS = 0, XCAPx = 0 (6)
Integrated effective load
capacitance, LF mode (5)
MAX
0.075
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C
fXT1,LF0
Oscillation allowance for
LF crystals (4)
TYP
pF
30%
70%
10
10000
Hz
1000
3V
ms
500
To improve EMI on the XT1 oscillator, the following guidelines should be observed.
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-trigger Inputs section of this datasheet.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
• For XT1DRIVEx = 0, CL,eff ≤ 6 pF
• For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF
• For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF
• For XT1DRIVEx = 3, CL,eff ≥ 6 pF
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, the
effective load capacitance should always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies between the MIN and MAX specifications might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Specifications
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CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
www.ti.com
5.16 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
fVLO
VLO frequency
Measured at ACLK
1.8 V to 3.6 V
dfVLO/dT
VLO frequency temperature drift
Measured at ACLK (1)
1.8 V to 3.6 V
Measured at ACLK (2)
1.8 V to 3.6 V
Measured at ACLK
1.8 V to 3.6 V
dfVLO/dVCC VLO frequency supply voltage drift
Duty cycle
(1)
(2)
MIN
TYP
MAX
6
9.4
14
0.5
50%
kHz
%/°C
4
40%
UNIT
%/V
60%
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
5.17 Internal Reference, Low-Frequency Oscillator (REFO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
IREFO
REFO oscillator current consumption
TA = 25°C
1.8 V to 3.6 V
3
fREFO
REFO frequency calibrated
Measured at ACLK
1.8 V to 3.6 V
32768
Full temperature range
1.8 V to 3.6 V
±3.5%
3V
±1.5%
REFO absolute tolerance calibrated
dfREFO/dT
dfREFO/dVC
TA = 25°C
UNIT
µA
Hz
Measured at ACLK
(1)
1.8 V to 3.6 V
0.01
%/°C
REFO frequency supply voltage drift
Measured at ACLK
(2)
1.8 V to 3.6 V
1.0
%/V
Duty cycle
Measured at ACLK
1.8 V to 3.6 V
REFO start-up time
40%/60% duty cycle
1.8 V to 3.6 V
REFO frequency temperature drift
C
tSTART
(1)
(2)
40%
50%
60%
25
µs
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
5.18 DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(1)
MIN
TYP
MAX
UNIT
fDCO(0,0)
DCO frequency (0, 0)
DCORSELx = 0, DCOx = 0, MODx = 0
0.07
0.20
MHz
fDCO(0,31)
DCO frequency (0, 31) (1)
DCORSELx = 0, DCOx = 31, MODx = 0
0.70
1.70
MHz
fDCO(1,0)
DCO frequency (1, 0) (1)
DCORSELx = 1, DCOx = 0, MODx = 0
0.15
0.36
MHz
fDCO(1,31)
DCO frequency (1, 31) (1)
DCORSELx = 1, DCOx = 31, MODx = 0
1.47
3.45
MHz
(1)
fDCO(2,0)
DCO frequency (2, 0)
DCORSELx = 2, DCOx = 0, MODx = 0
0.32
0.75
MHz
fDCO(2,31)
DCO frequency (2, 31) (1)
DCORSELx = 2, DCOx = 31, MODx = 0
3.17
7.38
MHz
fDCO(3,0)
DCO frequency (3, 0) (1)
DCORSELx = 3, DCOx = 0, MODx = 0
0.64
1.51
MHz
(1)
fDCO(3,31)
DCO frequency (3, 31)
DCORSELx = 3, DCOx = 31, MODx = 0
6.07
14.0
MHz
fDCO(4,0)
DCO frequency (4, 0) (1)
DCORSELx = 4, DCOx = 0, MODx = 0
1.3
3.2
MHz
fDCO(4,31)
DCO frequency (4, 31) (1)
DCORSELx = 4, DCOx = 31, MODx = 0
12.3
28.2
MHz
(1)
fDCO(5,0)
DCO frequency (5, 0)
DCORSELx = 5, DCOx = 0, MODx = 0
2.5
6.0
MHz
fDCO(5,31)
DCO frequency (5, 31) (1)
DCORSELx = 5, DCOx = 31, MODx = 0
23.7
54.1
MHz
fDCO(6,0)
DCO frequency (6, 0) (1)
DCORSELx = 6, DCOx = 0, MODx = 0
4.6
10.7
MHz
fDCO(6,31)
DCO frequency (6, 31) (1)
DCORSELx = 6, DCOx = 31, MODx = 0
39.0
88.0
MHz
(1)
fDCO(7,0)
DCO frequency (7, 0)
DCORSELx = 7, DCOx = 0, MODx = 0
8.5
19.6
MHz
fDCO(7,31)
DCO frequency (7, 31) (1)
DCORSELx = 7, DCOx = 31, MODx = 0
60
135
MHz
SDCORSEL
Frequency step between range
DCORSEL and DCORSEL + 1
SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO)
1.2
2.3
ratio
(1)
28
When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within the
range of fDCO(n, 0),MAX ≤ fDCO ≤ fDCO(n, 31),MIN, where fDCO(n, 0),MAX represents the maximum frequency specified for the DCO frequency,
range n, tap 0 (DCOx = 0) and fDCO(n,31),MIN represents the minimum frequency specified for the DCO frequency, range n, tap 31
(DCOx = 31). This ensures that the target DCO frequency resides within the range selected. It should also be noted that if the actual
fDCO frequency for the selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the
selected range is at its minimum or maximum tap setting.
Specifications
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SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
DCO Frequency (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
SDCO
TEST CONDITIONS
MIN
Frequency step between tap DCO
and DCO + 1
SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO)
1.02
40%
TYP
50%
MAX
UNIT
1.12
ratio
Duty cycle
Measured at SMCLK
dfDCO/dT
DCO frequency temperature drift
fDCO = 1 MHz
0.1
60%
%/°C
dfDCO/dVCC
DCO frequency voltage drift
fDCO = 1 MHz
1.9
%/V
100
VCC = 3.0 V
TA = 25°C
fDCO – MHz
10
DCOx = 31
1
0.1
DCOx = 0
0
1
2
3
5
4
6
7
DCORSEL
Figure 5-13. Typical DCO Frequency
5.19 PMM, Brownout Reset (BOR)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V(DVCC_BOR_IT–)
BORH on voltage, DVCC falling level
| dDVCC/dt | < 3 V/s
V(DVCC_BOR_IT+)
BORH off voltage, DVCC rising level
| dDVCC/dt | < 3 V/s
V(DVCC_BOR_hys)
BORH hysteresis
tRESET
Pulse duration required at RST/NMI pin to accept a reset
MIN
0.80
TYP
1.30
50
MAX
UNIT
1.45
V
1.50
V
250
mV
2
µs
5.20 PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCORE3(AM)
Core voltage, active mode, PMMCOREV = 3
2.4 V ≤ DVCC ≤ 3.6 V
1.90
V
VCORE2(AM)
Core voltage, active mode, PMMCOREV = 2
2.2 V ≤ DVCC ≤ 3.6 V
1.80
V
VCORE1(AM)
Core voltage, active mode, PMMCOREV = 1
2 V ≤ DVCC ≤ 3.6 V
1.60
V
VCORE0(AM)
Core voltage, active mode, PMMCOREV = 0
1.8 V ≤ DVCC ≤ 3.6 V
1.40
V
VCORE3(LPM)
Core voltage, low-current mode, PMMCOREV = 3
2.4 V ≤ DVCC ≤ 3.6 V
1.94
V
VCORE2(LPM)
Core voltage, low-current mode, PMMCOREV = 2
2.2 V ≤ DVCC ≤ 3.6 V
1.84
V
VCORE1(LPM)
Core voltage, low-current mode, PMMCOREV = 1
2 V ≤ DVCC ≤ 3.6 V
1.64
V
VCORE0(LPM)
Core voltage, low-current mode, PMMCOREV = 0
1.8 V ≤ DVCC ≤ 3.6 V
1.44
V
Specifications
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CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
www.ti.com
5.21 PMM, SVS High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVSHE = 0, DVCC = 3.6 V
I(SVSH)
SVS current consumption
V(SVSH_IT+)
SVSH on voltage level (1)
SVSH off voltage level (1)
tpd(SVSH)
SVSH propagation delay
t(SVSH)
SVSH on or off delay time
dVDVCC/dt
DVCC rise time
(1)
MAX
0
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0
1.5
µA
SVSHE = 1, SVSHRVL = 0
1.53
1.60
1.67
SVSHE = 1, SVSHRVL = 1
1.73
1.80
1.87
SVSHE = 1, SVSHRVL = 2
1.93
2.00
2.07
SVSHE = 1, SVSHRVL = 3
2.03
2.10
2.17
SVSHE = 1, SVSMHRRL = 0
1.60
1.70
1.80
SVSHE = 1, SVSMHRRL = 1
1.80
1.90
2.00
SVSHE = 1, SVSMHRRL = 2
2.00
2.10
2.20
SVSHE = 1, SVSMHRRL = 3
2.10
2.20
2.30
SVSHE = 1, SVSMHRRL = 4
2.25
2.35
2.50
SVSHE = 1, SVSMHRRL = 5
2.52
2.65
2.78
SVSHE = 1, SVSMHRRL = 6
2.85
3.00
3.15
SVSHE = 1, SVSMHRRL = 7
2.85
3.00
3.15
SVSHE = 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1
2.5
SVSHE = 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0
20
SVSHE = 0 → 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1
12.5
SVSHE = 0 → 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0
100
0
UNIT
nA
200
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1
V(SVSH_IT–)
TYP
V
V
µs
µs
1000
V/s
The SVSH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the CC430 Family User's Guide on recommended settings and use.
5.22 PMM, SVM High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVMHE = 0, DVCC = 3.6 V
I(SVMH)
SVMH current consumption
SVMH on or off voltage level (1)
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 0
SVMH propagation delay
t(SVMH)
SVMH on or off delay time
(1)
30
UNIT
nA
200
1.5
µA
SVMHE = 1, SVSMHRRL = 0
1.60
1.70
1.80
SVMHE = 1, SVSMHRRL = 1
1.80
1.90
2.00
SVMHE = 1, SVSMHRRL = 2
2.00
2.10
2.20
SVMHE = 1, SVSMHRRL = 3
2.10
2.20
2.30
SVMHE = 1, SVSMHRRL = 4
2.25
2.35
2.50
SVMHE = 1, SVSMHRRL = 5
2.52
2.65
2.78
SVMHE = 1, SVSMHRRL = 6
2.85
3.00
3.15
SVMHE = 1, SVSMHRRL = 7
2.85
3.00
3.15
SVMHE = 1, SVMHOVPE = 1
tpd(SVMH)
MAX
0
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1
V(SVMH)
TYP
V
3.75
SVMHE = 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1
2.5
SVMHE = 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0
20
SVMHE = 0 → 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1
12.5
SVMHE = 0 → 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0
100
µs
µs
The SVMH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the CC430 Family User's Guide on recommended settings and use.
Specifications
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CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
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SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
5.23 PMM, SVS Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVSLE = 0, PMMCOREV = 2
I(SVSL)
SVSL current consumption
tpd(SVSL)
SVSL propagation delay
t(SVSL)
SVSL on or off delay time
TYP
MAX
0
UNIT
nA
SVSLE = 1, PMMCOREV = 2, SVSLFP = 0
200
nA
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1
1.5
µA
SVSLE = 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1
2.5
SVSLE = 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0
20
SVSLE = 0 → 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1
12.5
SVSLE = 0 → 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0
100
µs
µs
5.24 PMM, SVM Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVMLE = 0, PMMCOREV = 2
I(SVML)
SVML current consumption
tpd(SVML) SVML propagation delay
t(SVML)
SVML on or off delay time
TYP
MAX
0
UNIT
nA
SVMLE = 1, PMMCOREV = 2, SVMLFP = 0
200
nA
SVMLE = 1, PMMCOREV = 2, SVMLFP = 1
1.5
µA
SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1
2.5
SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0
20
SVMLE = 0 → 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1
12.5
SVMLE = 0 → 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0
100
µs
µs
5.25 Wake-up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tWAKE-UP-FAST
Wake-up time from LPM2, LPM3, or
LPM4 to active mode (1)
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 1
tWAKE-UP-SLOW
Wake-up time from LPM2, LPM3, or
LPM4 to active mode (2) (3)
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 0
tWAKE-UP-RESET
Wake-up time from RST or BOR
event to active mode (4)
(1)
(2)
(3)
(4)
MIN
TYP MAX
fMCLK ≥ 4.0 MHz
5
fMCLK < 4.0 MHz
6
UNIT
µs
150
165
µs
2
3
ms
This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance
mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-FAST is possible with SVSL and SVML in full performance
mode or disabled. For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode Selection section in
the Power Management Module and Supply Voltage Supervisor chapter of the CC430 Family User's Guide.
This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance
mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-SLOW is set with SVSL and SVML in normal mode (low
current mode). For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode Selection section in the
Power Management Module and Supply Voltage Supervisor chapter of the CC430 Family User's Guide.
The wake-up times from LPM0 and LPM1 to AM are not specified. They are proportional to MCLK cycle time but are not affected by the
performance mode settings as for LPM2, LPM3, and LPM4.
This value represents the time from the wake-up event to the reset vector execution.
5.26 Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTA
Timer_A input clock frequency
Internal: SMCLK or ACLK,
External: TACLK,
Duty cycle = 50% ±10%
tTA,cap
Timer_A capture timing
All capture inputs,
Minimum pulse duration required for capture
VCC
1.8 V, 3 V
1.8 V, 3 V
MIN
MAX
UNIT
25
MHz
20
Specifications
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CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
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5.27 USCI (UART Mode) Clock Frequency
PARAMETER
fUSCI
TEST CONDITIONS
MIN
Internal: SMCLK or ACLK,
External: UCLK,
Duty cycle = 50% ±10%
USCI input clock frequency
fBITCLK BITCLK clock frequency (equals baud rate in MBaud)
MAX
UNIT
fSYSTEM
MHz
1
MHz
UNIT
5.28 USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
(1)
VCC
UART receive deglitch time (1)
tτ
MIN
MAX
2.2 V
50
600
3V
50
600
ns
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
5.29 USCI (SPI Master Mode) Clock Frequency
PARAMETER
fUSCI
TEST CONDITIONS
MIN
Internal: SMCLK or ACLK,
Duty cycle = 50% ±10%
USCI input clock frequency
MAX
UNIT
fSYSTEM
MHz
5.30 USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (see Figure 5-14
and Figure 5-15)
PARAMETER
TEST CONDITIONS
PMMCOREVx
0
tSU,MI
SOMI input data setup time
3
0
tHD,MI
SOMI input data hold time
3
0
tVALID,MO
SIMO output data valid time (2)
UCLK edge to SIMO valid,
CL = 20 pF
3
0
tHD,MO
SIMO output data hold time
(3)
CL = 20 pF
3
(1)
(2)
(3)
32
VCC
MIN
1.8 V
55
3V
38
2.4 V
30
3V
25
1.8 V
0
3V
0
2.4 V
0
3V
0
MAX
ns
ns
1.8 V
20
3V
18
2.4 V
16
3V
1.8 V
UNIT
ns
15
–10
3V
–8
2.4 V
–10
3V
–8
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave))
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-14 and Figure 5-15.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 514 and Figure 5-15.
Specifications
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1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tHD,MO
tVALID,MO
SIMO
Figure 5-14. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tHD,MO
tVALID,MO
SIMO
Figure 5-15. SPI Master Mode, CKPH = 1
Specifications
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5.31 USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (see Figure 5-16
and Figure 5-17)
PARAMETER
TEST CONDITIONS
PMMCOREVx
0
tSTE,LEAD
STE lead time, STE low to clock
3
0
tSTE,LAG
STE lag time, Last clock to STE
high
3
0
tSTE,ACC
STE access time, STE low to
SOMI data out
3
0
STE disable time, STE high to
SOMI high impedance
tSTE,DIS
3
0
tSU,SI
SIMO input data setup time
3
0
tHD,SI
SIMO input data hold time
3
0
tVALID,SO
SOMI output data valid time (2)
UCLK edge to SOMI valid,
CL = 20 pF
3
0
tHD,SO
SOMI output data hold time (3)
CL = 20 pF
3
(1)
(2)
(3)
34
VCC
MIN
1.8 V
11
3V
8
2.4 V
7
3V
6
1.8 V
3
3V
3
2.4 V
3
3V
3
MAX
ns
ns
1.8 V
66
3V
50
2.4 V
36
3V
30
1.8 V
30
3V
23
2.4 V
16
3V
UNIT
ns
ns
13
1.8 V
5
3V
5
2.4 V
2
3V
2
1.8 V
5
3V
5
2.4 V
5
3V
5
ns
ns
1.8 V
76
3V
60
2.4 V
44
3V
40
1.8 V
18
3V
12
2.4 V
10
3V
8
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI))
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-16 and Figure 5-17.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-16
and Figure 5-17.
Specifications
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tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tSU,SI
tLO/HI
tHD,SI
SIMO
tHD,SO
tVALID,SO
tSTE,ACC
tSTE,DIS
SOMI
Figure 5-16. SPI Slave Mode, CKPH = 0
tSTE,LAG
tSTE,LEAD
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tHD,SI
tSU,SI
SIMO
tSTE,ACC
tHD,MO
tVALID,SO
tSTE,DIS
SOMI
Figure 5-17. SPI Slave Mode, CKPH = 1
Specifications
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5.32 USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-18)
PARAMETER
TEST CONDITIONS
VCC
MIN
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ±10%
MAX
UNIT
fSYSTEM
MHz
400
kHz
fUSCI
USCI input clock frequency
fSCL
SCL clock frequency
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
2.2 V, 3 V
0
ns
tSU,DAT
Data setup time
2.2 V, 3 V
250
ns
2.2 V, 3 V
fSCL ≤ 100 kHz
fSCL ≤ 100 kHz
fSCL ≤ 100 kHz
tSP
Pulse duration of spikes suppressed by input filter
tSU,STA
tHD,STA
4.7
µs
0.6
4.0
2.2 V, 3 V
fSCL > 100 kHz
µs
0.6
2.2 V, 3 V
fSCL > 100 kHz
Setup time for STOP
4.0
2.2 V, 3 V
fSCL > 100 kHz
tSU,STO
0
µs
0.6
2.2 V
50
600
3V
50
600
tHD,STA
ns
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 5-18. I2C Mode Timing
36
Specifications
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SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
5.33 LCD_B Operating Conditions
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
LCDCPEN = 1, 0000 < VLCDx ≤ 1111
(charge pump enabled, VLCD ≤ 3.6 V)
2.2
3.6
V
VCC,LCD_B,CP
en,3.6
Supply voltage range, charge
pump enabled, VLCD ≤ 3.6 V
VCC,LCD_B,CP
en,3.3
Supply voltage range, charge
pump enabled, VLCD ≤ 3.3 V
LCDCPEN = 1, 0000 < VLCDx ≤ 1100
(charge pump enabled, VLCD ≤ 3.3 V)
2.0
3.6
V
VCC,LCD_B,int. bias
Supply voltage range, internal
biasing, charge pump disabled
LCDCPEN = 0, VLCDEXT = 0
2.4
3.6
V
VCC,LCD_B,ext.
Supply voltage range, external
biasing, charge pump disabled
LCDCPEN = 0, VLCDEXT = 0
2.4
3.6
V
VCC,LCD_B,VLCDEXT
Supply voltage range, external
LCD voltage, internal or
external biasing, charge pump
disabled
LCDCPEN = 0, VLCDEXT = 1
2.0
3.6
V
VLCDCAP/R33
External LCD voltage at
LCDCAP/R33, internal or
external biasing, charge pump
disabled
LCDCPEN = 0, VLCDEXT = 1
2.4
3.6
V
CLCDCAP
Capacitor on LCDCAP when
charge pump enabled
LCDCPEN = 1, VLCDx > 0000 (charge
pump enabled)
4.7
10
µF
fFrame
LCD frame frequency range
fLCD = 2 × mux × fFRAME with
mux = 1 (static), 2, 3, 4
100
Hz
fACLK,in
ACLK input frequency range
CPanel
Panel capacitance
100-Hz frame frequency
VR33
Analog input voltage at R33
LCDCPEN = 0, VLCDEXT = 1
VR23,1/3bias
Analog input voltage at R23
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0
VR13
VR13,1/3bias
Analog input voltage at R13
with 1/3 biasing
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0
VR13,1/2bias
Analog input voltage at R13
with 1/2 biasing
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 1
VR03
Analog input voltage at R03
R0EXT = 1
VSS
VLCD – VR03
Voltage difference between
VLCD and R03
LCDCPEN = 0, R0EXT = 1
2.4
VLCDREF/R13
External LCD reference
voltage applied at
LCDREF/R13
VLCDREFx = 01
0.8
bias
4.7
0
30
32
40
kHz
10000
pF
VCC + 0.2
V
VR03 +
2/3 ×
(VR33 –
VR03)
VR33
V
VR03
VR03 +
1/3 ×
(VR33 –
VR03)
VR23
V
VR03
VR03 +
1/2 ×
(VR33 –
VR03)
VR33
V
2.4
V
1.2
VCC + 0.2
V
1.5
V
Specifications
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5.34 LCD_B Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VLCDx = 0000, VLCDEXT = 0
2.4 V to 3.6 V
VCC
LCDCPEN = 1, VLCDx = 0001
2 V to 3.6 V
2.54
LCDCPEN = 1, VLCDx = 0010
2 V to 3.6 V
2.60
LCDCPEN = 1, VLCDx = 0011
2 V to 3.6 V
2.66
LCDCPEN = 1, VLCDx = 0100
2 V to 3.6 V
2.72
LCDCPEN = 1, VLCDx = 0101
2 V to 3.6 V
2.78
LCDCPEN = 1, VLCDx = 0110
2 V to 3.6 V
2.84
LCDCPEN = 1, VLCDx = 0111
2 V to 3.6 V
2.90
LCDCPEN = 1, VLCDx = 1000
2 V to 3.6 V
2.96
LCDCPEN = 1, VLCDx = 1001
2 V to 3.6 V
3.02
LCDCPEN = 1, VLCDx = 1010
2 V to 3.6 V
3.08
LCDCPEN = 1, VLCDx = 1011
2 V to 3.6 V
3.14
LCDCPEN = 1, VLCDx = 1100
2 V to 3.6 V
3.20
LCDCPEN = 1, VLCDx = 1101
2.2 V to 3.6 V
3.26
LCDCPEN = 1, VLCDx = 1110
2.2 V to 3.6 V
3.32
LCDCPEN = 1, VLCDx = 1111
2.2 V to 3.6 V
3.38
ICC,Peak,CP
Peak supply currents due to
charge pump activities
LCDCPEN = 1, VLCDx = 1111
2.2 V
200
tLCD,CP,on
Time to charge CLCD when
discharged
CLCDCAP = 4.7µF,
LCDCPEN = 0→1,
VLCDx = 1111
2.2 V
100
ICP,Load
Maximum charge pump load
current
LCDCPEN = 1, VLCDx = 1111
2.2 V
RLCD,Seg
LCD driver output
impedance, segment lines
LCDCPEN = 1, VLCDx = 1000,
ILOAD = ±10 µA
2.2 V
10
kΩ
RLCD,COM
LCD driver output
impedance, common lines
LCDCPEN = 1, VLCDx = 1000,
ILOAD = ±10 µA
2.2 V
10
kΩ
VLCD
38
LCD voltage
Specifications
V
3.6
µA
500
50
ms
µA
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5.35 12-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
VCC
AVCC
Analog supply voltage,
full performance
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
V(Ax)
Analog input voltage range (2)
All ADC12 analog input pins Ax
IADC12_A
Operating supply current into
AVCC terminal (3)
fADC12CLK = 5.0 MHz, ADC12ON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0,
ADC12DIV = 0
CI
Input capacitance
Only one terminal Ax can be selected at
one time
RI
Input MUX ON resistance
0 V ≤ VAx ≤ AVCC
(1)
(2)
(3)
MIN
TYP
MAX
UNIT
2.2
3.6
V
0
AVCC
V
2.2 V
125
155
3V
150
220
2.2 V
20
25
pF
200
1900
Ω
10
µA
The leakage current is specified by the digital I/O input leakage.
The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. If the
reference voltage is supplied by an external source or if the internal reference voltage is used and REFOUT = 1, then decoupling
capacitors are required. See Section 5.40 and Section 5.41.
The internal reference supply current is not included in current consumption parameter IADC12_A.
5.36 12-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
For specified performance of ADC12 linearity
parameters using an external reference
voltage or AVCC as reference (1)
fADC12CLK
ADC conversion clock
For specified performance of ADC12 linearity
parameters using the internal reference (2)
2.2 V, 3 V
For specified performance of ADC12 linearity
parameters using the internal reference (3)
fADC12OSC
tCONVERT
tSample
(1)
(2)
(3)
(4)
(5)
Internal ADC12
oscillator (4)
Conversion time
Sampling time
MIN
TYP
MAX
0.45
4.8
5.0
0.45
2.4
4.0
0.45
2.4
2.7
4.8
5.4
ADC12DIV = 0, fADC12CLK = fADC12OSC
2.2 V, 3 V
4.2
REFON = 0, Internal oscillator,
fADC12OSC = 4.2 MHz to 5.4 MHz
2.2 V, 3 V
2.4
External fADC12CLK from ACLK, MCLK or
SMCLK, ADC12SSEL ≠ 0
RS = 400 Ω, RI = 1000 Ω, CI = 30 pF,
τ = (RS + RI) × CI (5)
UNIT
MHz
MHz
3.1
13 ×
µs
1 / fADC12CLK
2.2 V, 3 V
1000
ns
REFOUT = 0, external reference voltage: SREF2 = 0, SREF1 = 1, SREF0 = 0. AVCC as reference voltage: SREF2 = 0, SREF1 = 0,
SREF0 = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC. For other clock sources, the
specified performance of the ADC12 linearity is ensured with fADC12CLK maximum of 5.0 MHz.
SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 1
SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 0. The specified performance of the ADC12 linearity is ensured when
using the ADC12OSC divided by 2.
The ADC12OSC is sourced directly from MODOSC inside the UCS.
Approximately 10 Tau (τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) × (RS + RI) × CI + 800 ns, where n = ADC resolution = 12, RS = external source resistance
Specifications
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5.37 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as
Reference Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
EI
Integral linearity error (1)
ED
Differential linearity error (1)
EO
Offset error (3)
EG
Gain error (3)
ET
(1)
(2)
(3)
TEST CONDITIONS
1.4 V ≤ dVREF ≤ 1.6 V (2)
1.6 V < dVREF (2)
See
MIN
TYP
MAX
±2.0
2.2 V, 3 V
±1.7
2.2 V, 3 V
±1.0
dVREF ≤ 2.2 V (2)
2.2 V, 3 V
±1.0
±2.0
dVREF > 2.2 V (2)
2.2 V, 3 V
±1.0
±2.0
See
Total unadjusted error
(2)
VCC
(2)
2.2 V, 3 V
±1.0
±2.0
dVREF ≤ 2.2 V (2)
2.2 V, 3 V
±1.4
±3.5
dVREF > 2.2 V (2)
2.2 V, 3 V
±1.4
±3.5
UNIT
LSB
LSB
LSB
LSB
LSB
Parameters are derived using the histogram method.
The external reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 0. dVREF = VR+ – VR–, VR+ < AVCC, VR– > AVSS.
Unless otherwise mentioned, dVREF > 1.5 V. Impedance of the external reference voltage R < 100 Ω and two decoupling capacitors,
10 µF and 100 nF, should be connected to VREF+/VREF- to decouple the dynamic current. Also see the CC430 Family User's Guide.
Parameters are derived using a best fit curve.
5.38 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
EI
Integral linearity
error (2)
ED
Differential
linearity error (2)
EO
Offset error (3)
EG
Gain error (3)
ET
Total unadjusted
error
(1)
(2)
(3)
(4)
40
TEST CONDITIONS (1)
ADC12SR = 0, REFOUT = 1
fADC12CLK ≤ 4.0 MHz
ADC12SR = 0, REFOUT = 0
fADC12CLK ≤ 2.7 MHz
ADC12SR = 0, REFOUT = 1
fADC12CLK ≤ 4.0 MHz
ADC12SR = 0, REFOUT = 1
fADC12CLK ≤ 2.7 MHz
ADC12SR = 0, REFOUT = 0
fADC12CLK ≤ 2.7 MHz
ADC12SR = 0, REFOUT = 1
fADC12CLK ≤ 4.0 MHz
ADC12SR = 0, REFOUT = 0
fADC12CLK ≤ 2.7 MHz
ADC12SR = 0, REFOUT = 1
fADC12CLK ≤ 4.0 MHz
ADC12SR = 0, REFOUT = 0
fADC12CLK ≤ 2.7 MHz
ADC12SR = 0, REFOUT = 1
fADC12CLK ≤ 4.0 MHz
ADC12SR = 0, REFOUT = 0
fADC12CLK ≤ 2.7 MHz
VCC
MIN
TYP
±1.7
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
MAX
±2.5
–1.0
+2.0
–1.0
+1.5
–1.0
+2.5
±1.0
±2.0
±1.0
±2.0
±1.0
±2.0
UNIT
LSB
LSB
LSB
LSB
±1.5% (4) VREF
±1.4
±3.5
LSB
±1.5% (4) VREF
The internal reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 1. dVREF = VR+ – VR–.
Parameters are derived using the histogram method.
Parameters are derived using a best fit curve.
The gain error and total unadjusted error are dominated by the accuracy of the integrated reference module absolute accuracy. In this
mode the reference voltage used by the ADC12_A is not available on a pin.
Specifications
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5.39 12-Bit ADC, Temperature Sensor and Built-In VMID (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ADC12ON = 1, INCH = 0Ah,
TA = 0°C
VSENSOR
See
(2) (3)
TCSENSOR
See
(3)
tSENSOR(sample)
Sample time required if
channel 10 is selected (4)
ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
AVCC divider at channel 11,
VAVCC factor
ADC12ON = 1, INCH = 0Bh
AVCC divider at channel 11
ADC12ON = 1, INCH = 0Bh
Sample time required if
channel 11 is selected (5)
ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤1 LSB
ADC12ON = 1, INCH = 0Ah
VMID
tVMID(sample)
(1)
(2)
(3)
(4)
(5)
VCC
MIN
TYP
2.2 V
680
3V
680
2.2 V
2.25
3V
2.25
2.2 V
30
3V
30
MAX
UNIT
mV
mV/°C
µs
0.48
0.5
0.52 VAVCC
2.2 V
1.06
1.1
1.14
3V
1.44
1.5
1.56
2.2 V, 3 V
1000
V
ns
The temperature sensor is provided by the REF module. See the REF module parametric, IREF+, regarding the current consumption of
the temperature sensor.
The temperature sensor offset can be significant. TI recommends a single-point calibration to minimize the offset error of the built-in
temperature sensor.
The device descriptor structure contains calibration values for 30°C ±3°C and 85°C ±3°C for each of the available reference voltage
levels. The sensor voltage can be computed as VSENSE = TCSENSOR × (Temperature, °C) + VSENSOR, where TCSENSOR and VSENSOR can
be computed from the calibration values for higher accuracy.
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
The on time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
1000
Typical Temperature Sensor Voltage (mV)
950
900
850
800
750
700
650
600
550
500
-40 -30 -20 -10 0
10 20 30 40 50 60 70 80
Ambient Temperature (°C)
Figure 5-19. Typical Temperature Sensor Voltage
Specifications
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5.40 REF, External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VeREF+
Positive external reference
voltage input
VeREF+ > VREF–/VeREF– (2)
1.4
AVCC
V
VREF–/VeREF–
Negative external reference
voltage input
VeREF+ > VREF–/VeREF– (3)
0
1.2
V
(VeREF+ –
VREF–/VeREF–)
Differential external reference
VeREF+ > VREF–/VeREF– (4)
voltage input
1.4
AVCC
V
IVeREF+
IVREF–/VeREF-
CVREF+/(1)
(2)
(3)
(4)
(5)
42
Static input current
1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V,
fADC12CLK = 5 MHz, ADC12SHTx = 1h,
Conversion rate 200 ksps
2.2 V, 3 V
1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V,
fADC12CLK = 5 MHz, ADC12SHTx = 8h,
Conversion rate 20 ksps
2.2 V, 3 V
Capacitance at VREF+ or
VREF- terminal, external
reference (5)
±8.5
±26
µA
±1
10
µF
The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external
reference source if it is used for the ADC12_A. Also see the CC430 Family User's Guide.
Specifications
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5.41 REF, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
VREF+
AVCC(min)
Positive built-in reference
voltage output
AVCC minimum voltage,
Positive built-in reference
active
TEST CONDITIONS
VCC
Operating supply current into
AVCC terminal (2) (3)
2.41
±1.5%
REFVSEL = 1 for 2 V,
REFON = REFOUT = 1, IVREF+= 0 A
3V
1.93
±1.5%
REFVSEL = 0 for 1.5 V,
REFON = REFOUT = 1, IVREF+= 0 A
2.2 V, 3 V
1.45
±1.5%
REFVSEL = 0 for 1.5 V, reduced performance
1.8
REFVSEL = 0 for 1.5 V
2.2
REFVSEL = 1 for 2 V
2.3
µA
REFON = 1, REFOUT = 1, REFBURST = 0
3V
0.9
1.5
mA
REFON = REFOUT = 1
TCREF+
Temperature coefficient of
built-in reference (5)
IVREF+ = 0 A,
REFVSEL = 0, 1, or 2,
REFON = 1, REFOUT = 0 or 1
PSRR_DC
Power supply rejection ratio
(DC)
PSRR_AC
Power supply rejection ratio
(AC)
(4)
(5)
(6)
2.8
140
Capacitance at VREF+
terminals, internal reference
(3)
V
100
CVREF+
(2)
V
3V
Load-current regulation,
VREF+ terminal (4)
(1)
UNIT
REFON = 1, REFOUT = 0, REFBURST = 0
IL(VREF+)
Settling time of reference
voltage (6)
MAX
3V
REFVSEL = 0, 1, or 2,
IVREF+ = +10 µA or –1000 µA,
AVCC = AVCC(min) for each reference level,
REFON = REFOUT = 1
tSETTLE
TYP
REFVSEL = 2 for 2.5 V,
REFON = REFOUT = 1, IVREF+= 0 A
REFVSEL = 2 for 2.5 V
IREF+
MIN
2500 µV/mA
100
pF
30
50
ppm/
°C
AVCC = AVCC(min) to AVCC(max),
TA = 25 °C, REFVSEL = 0, 1, or 2,
REFON = 1, REFOUT = 0 or 1
120
300
µV/V
AVCC = AVCC(min) to AVCC(max)
TA = 25 °C, f = 1 kHz, ΔVpp = 100 mV,
REFVSEL = 0, 1, or 2,
REFON = 1, REFOUT = 0 or 1
6.4
AVCC = AVCC(min) to AVCC(max),
REFVSEL = 0, 1, or 2,
REFOUT = 0, REFON = 0 → 1
75
AVCC = AVCC(min) to AVCC(max),
CVREF = CVREF(maximum),
REFVSEL = 0, 1, or 2,
REFOUT = 1, REFON = 0 → 1
20
mV/V
µs
75
The reference is supplied to the ADC by the REF module and is buffered locally inside the ADC. The ADC uses two internal buffers, one
smaller and one larger for driving the VREF+ terminal. When REFOUT = 1, the reference is available at the VREF+ terminal, as well as,
used as the reference for the conversion and uses the larger buffer. When REFOUT = 0, the reference is only used as the reference for
the conversion and uses the smaller buffer.
The internal reference current is supplied from the AVCC terminal. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an analog-to-digital conversion. REFOUT = 0
represents the current contribution of the smaller buffer. REFOUT = 1 represents the current contribution of the larger buffer without
external load.
The temperature sensor is provided by the REF module. Its current is supplied from the AVCC terminal and is equivalent to IREF+ with
REFON = 1 and REFOUT = 0.
Contribution only due to the reference and buffer including package. This does not include resistance due to PCB trace or other causes.
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C – (–40°C)).
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load when REFOUT = 1.
Specifications
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5.42 Comparator_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
TEST CONDITIONS
VCC
Supply voltage
MIN
TYP
1.8
3.6
1.8 V
IAVCC_COMP
Comparator operating supply
current into AVCC, Excludes
reference resistor ladder
IAVCC_REF
Quiescent current of local reference
voltage amplifier into AVCC
VIC
Common mode input range
VOFFSET
Input offset voltage
CIN
Input capacitance
RSIN
Series input resistance
tPD
Propagation delay, response time
tPD,filter
Propagation delay with filter active
tEN_CMP
tEN_REF
Resistor reference enable time
VCB_REF
44
Comparator enable time, settling
time
Reference voltage for a given tap
CBPWRMD = 00
MAX
2.2 V
30
50
3V
40
65
2.2 V, 3 V
10
30
CBPWRMD = 10
2.2 V, 3 V
0.1
0.5
CBREFACC = 1, CBREFLx = 01
0
µA
VCC – 1
V
±20
CBPWRMD = 01 or 10
±10
5
On (switch closed)
3
30
450
600
CBPWRMD = 10, CBF = 0
50
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 00
0.35
0.6
1.0
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 01
0.6
1.0
1.8
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 10
1.0
1.8
3.4
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 11
1.8
3.4
6.5
1
2
ns
µs
µs
µs
CBON = 0 to CBON = 1,
CBPWRMD = 10
Specifications
kΩ
MΩ
CBPWRMD = 01, CBF = 0
VIN = reference into resistor ladder,
n = 0 to 31
mV
pF
4
CBPWRMD = 00, CBF = 0
CBON = 0 to CBON = 1
µA
22
CBPWRMD = 00
CBON = 0 to CBON = 1,
CBPWRMD = 00 or 01
V
40
CBPWRMD = 01
Off (switch open)
UNIT
100
0.3
VIN ×
(n + 1)
/ 32
1.5
µs
V
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5.43 Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TJ
DVCC(PGM/ERASE) Program and erase supply voltage
MIN
TYP
1.8
MAX
3.6
UNIT
V
IPGM
Average supply current from DVCC during program
3
5
mA
IERASE
Average supply current from DVCC during erase
2
6.5
mA
IMERASE, IBANK
Average supply current from DVCC during mass erase or bank erase
2
6.5
mA
tCPT
Cumulative program time
(1)
16
104
Program and erase endurance
tRetention
tWord
Data retention duration
ms
cycles
100
years
64
85
µs
0
Block program time for first byte or word (2)
49
65
µs
tBlock,
1–(N–1)
Block program time for each additional byte or word, except for last byte or
word (2)
37
49
µs
tBlock,
N
Block program time for last byte or word (2)
55
73
µs
tErase
Erase time for segment erase, mass erase, and bank erase when
available (2)
23
32
ms
fMCLK,MGR
MCLK frequency in marginal read mode
(FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1)
0
1
MHz
tBlock,
(1)
(2)
Word or byte program time
25°C
(2)
105
The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word write, individual byte write, and block write modes.
These values are hardwired into the state machine of the flash controller.
5.44 JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
PARAMETER
2.2 V, 3 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse duration
2.2 V, 3 V
0.025
15
µs
1
µs
15
100
0
5
MHz
10
MHz
80
kΩ
tSBW, En
Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)
tSBW,Rst
Spy-Bi-Wire return to normal operation time
fTCK
TCK input frequency, 4-wire JTAG (2)
Rinternal
Internal pulldown resistance on TEST
(1)
(2)
VCC
(1)
MIN
TYP
2.2 V, 3 V
2.2 V
3V
0
2.2 V, 3 V
45
60
µs
Tools that access the Spy-Bi-Wire interface need to wait for the minimum tSBW,En time after pulling the TEST/SBWTCK pin high before
applying the first SBWTCK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
Specifications
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5.45 RF1A CC1101-Based Radio Parameters
5.46 Recommended Operating Conditions
PARAMETER
TEST CONDITIONS
MIN
VCC
Supply voltage range during radio operation
PMMCOREVx
Core voltage range, PMMCOREVx setting during radio operation
3.6
2
3
V
348
464
779
928
2-FSK
0.6
500
2-GFSK, OOK, and ASK
0.6
250 kBaud
(Shaped) MSK (also known as differential offset QPSK) (2)
26
500
26
Total tolerance including initial tolerance, crystal loading, aging,
and temperature dependency. (3)
26
27
±40
RF crystal load capacitance
10
13
RF crystal effective series resistance
(1)
(2)
(3)
UNIT
300
RF crystal frequency
RF crystal tolerance
MAX
389 (1)
RF range
Data rate
TYP
2.0
MHz
MHz
ppm
20
pF
100
Ω
If using a 27-MHz crystal, the lower frequency limit for this band is 392 MHz.
If using optional Manchester encoding, the data rate in kbps is half the baud rate.
The acceptable crystal tolerance depends on frequency band, channel bandwidth, and spacing. Also see DN005 -- CC11xx Sensitivity
versus Frequency Offset and Crystal Accuracy.
5.47 RF Crystal Oscillator, XT2
TA = 25°C, VCC = 3 V (unless otherwise noted) (1)
PARAMETER
MIN
Start-up time (2)
Duty cycle
(1)
(2)
45%
TYP
MAX
UNIT
150
810
µs
50%
55%
All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 7-1).
The start-up time depends to a very large degree on the used crystal.
5.48 Current Consumption, Reduced-Power Modes
TA = 25°C, VCC = 3 V (unless otherwise noted) (1)
PARAMETER
Current consumption
(1)
(2)
(3)
46
TEST CONDITIONS
MIN
TYP
RF crystal oscillator only (2)
100
IDLE state (including RF crystal oscillator)
1.7
FSTXON state (only the frequency synthesizer is running) (3)
9.5
MAX
UNIT
µA
mA
All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 7-1).
To measure the current, follow this sequence:
• Enable XT2 with XOSC_FORCE_ON = 1.
• Set radio to sleep mode.
• Disable XT2 clock requests from any module.
This current consumption is also representative of other intermediate states when going from IDLE to RX or TX, including the calibration
state.
Specifications
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5.49 Current Consumption, Receive Mode
TA = 25°C, VCC = 3 V (unless otherwise noted) (1)
PARAMETER
FREQ (MHz)
DATA RATE
(kBaud)
(2)
TEST CONDITIONS
1.2
315
38.4
Register settings optimized for
reduced current
250
433
38.4
Register settings optimized for
reduced current
1.2
38.4
Register settings optimized for
reduced current (3)
250
(1)
(2)
(3)
17
Input at –40 dBm (well
above sensitivity limit)
16
Input at –100 dBm (close to
sensitivity limit)
17
Input at –40 dBm (well
above sensitivity limit)
16
Input at –100 dBm (close to
sensitivity limit)
18
UNIT
16.5
Input at –100 dBm (close to
sensitivity limit)
18
Input at –40 dBm (well
above sensitivity limit)
17
Input at –100 dBm (close to
sensitivity limit)
18
Input at –40 dBm (well
above sensitivity limit)
17
Input at –100 dBm (close to
sensitivity limit)
250
868, 915
Input at –100 dBm (close to
sensitivity limit)
Input at –40 dBm (well
above sensitivity limit)
1.2
Current
consumption, RX
TYP
mA
18.5
Input at –40 dBm (well
above sensitivity limit)
17
Input at –100 dBm (close to
sensitivity limit)
16
Input at –40 dBm (well
above sensitivity limit)
15
Input at –100 dBm (close to
sensitivity limit)
16
Input at –40 dBm (well
above sensitivity limit)
15
Input at –100 dBm (close to
sensitivity limit)
16
Input at –40 dBm (well
above sensitivity limit)
15
All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 7-1).
Reduced current setting (MDMCFG2.DEM_DCFILT_OFF = 1) gives a slightly lower current consumption at the cost of a reduction in
sensitivity. See Section 5.55 through Section 5.58 for additional details on current consumption and sensitivity.
For 868 or 915 MHz, see Figure 5-20 for current consumption with register settings optimized for sensitivity.
Specifications
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19
19
TA = 85°C
TA = 25°C
TA = 25°C
TA = -40°C
TA = -40°C
Radio Current (mA)
Radio Current (mA)
TA = 85°C
18
17
16
-100
-80
-60
-40
18
17
16
-100
-20
-80
Input Power (dBm)
-60
1.2 kBaud GFSK
19
TA = 85°C
TA = 85°C
TA = 25°C
TA = 25°C
TA = -40°C
TA = -40°C
Radio Current (mA)
Radio Current (mA)
-20
38.4 kBaud GFSK
19
18
17
16
-100
-40
Input Power (dBm)
-80
-60
-40
-20
18
17
16
-100
-80
-60
-40
-20
Input Power (dBm)
Input Power (dBm)
250 kBaud GFSK
500 kBaud MSK
Figure 5-20. Typical RX Current Consumption Over Temperature and Input Power Level, 868 MHz,
Sensitivity-Optimized Setting
48
Specifications
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5.50 Current Consumption, Transmit Mode
TA = 25°C, VCC = 3 V (unless otherwise noted) (1)
PARAMETER
(2)
FREQUENCY
[MHz}
PATABLE
SETTING
OUTPUT
POWER (dBm)
0xC0
maximum
26
0xC4
+10
25
0x51
0
15
315
433
Current consumption, TX
868
915
(1)
(2)
TYP
0x29
–6
15
0xC0
maximum
33
0xC6
+10
29
0x50
0
17
0x2D
–6
17
0xC0
maximum
36
0xC3
+10
33
0x8D
0
18
0x2D
–6
18
0xC0
maximum
35
0xC3
+10
32
0x8D
0
18
0x2D
–6
18
UNIT
mA
All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 7-1).
Reduced current setting (MDMCFG2.DEM_DCFILT_OFF = 1) gives a slightly lower current consumption at the cost of a reduction in
sensitivity. See Section 5.55 through Section 5.58 for additional details on current consumption and sensitivity.
Specifications
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5.51 Typical TX Current Consumption, 315 MHz
PARAMETER
Current consumption, TX
PATABLE
SETTING
OUTPUT
POWER
(dBm)
VCC
2V
3V
3.6 V
TA
25°C
25°C
25°C
0xC0
0xC4
maximum
27.5
26.4
28.1
+10
25.1
25.2
25.3
0x51
0
14.4
14.6
14.7
0x29
–6
14.2
14.7
15.0
VCC
2V
3V
3.6 V
TA
25°C
25°C
25°C
UNIT
mA
5.52 Typical TX Current Consumption, 433 MHz
PARAMETER
Current consumption, TX
PATABLE
SETTING
OUTPUT
POWER
(dBm)
0xC0
maximum
33.1
33.4
33.8
0xC6
+10
28.6
28.8
28.8
0x50
0
16.6
16.8
16.9
0x2D
–6
16.8
17.5
17.8
UNIT
mA
5.53 Typical TX Current Consumption, 868 MHz
PARAMETER
PATABLE
SETTING
OUTPUT
POWER
(dBm)
0xC0
Current
consumption, TX
VCC
TA
2V
3V
3.6 V
–40°C
25°C
85°C
–40°C
25°C
85°C
–40°C
25°C
85°C
maximum
36.7
35.2
34.2
38.5
35.5
34.9
37.1
35.7
34.7
0xC3
+10
34.0
32.8
32.0
34.2
33.0
32.5
34.3
33.1
32.2
0x8D
0
18.0
17.6
17.5
18.3
17.8
18.1
18.4
18.0
17.7
0x2D
–6
17.1
17.0
17.2
17.8
17.8
18.3
18.2
18.1
18.1
UNIT
mA
5.54 Typical TX Current Consumption, 915 MHz
PARAMETER
PATABLE
SETTING
OUTPUT
POWER
(dBm)
0xC0
0xC3
Current
consumption, TX
50
VCC
TA
2V
3V
3.6 V
–40°C
25°C
85°C
–40°C
25°C
85°C
–40°C
25°C
85°C
maximum
35.5
33.8
33.2
36.2
34.8
33.6
36.3
35.0
33.8
+10
33.2
32.0
31.0
33.4
32.1
31.2
33.5
32.3
31.3
0x8D
0
17.8
17.4
17.1
18.1
17.6
17.3
18.2
17.8
17.5
0x2D
–6
17.0
16.9
16.9
17.7
17.6
17.6
18.1
18.0
18.0
Specifications
UNIT
mA
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5.55 RF Receive, Overall
TA = 25°C, VCC = 3 V (unless otherwise noted) (1)
PARAMETER
Digital channel filter bandwidth
Spurious emissions (3)
RX latency
(1)
(2)
(3)
(4)
(5)
(4)
TEST CONDITIONS
MIN
(2)
TYP
58
MAX
UNIT
812
kHz
25 MHz to 1 GHz
–68
–57
Above 1 GHz
–66
–47
Serial operation (5)
9
dBm
bit
All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 7-1).
User programmable. The bandwidth limits are proportional to crystal frequency (given values assume a 26.0 MHz crystal)
Typical radiated spurious emission is –49 dBm measured at the VCO frequency
Maximum figure is the ETSI EN 300 220 limit
Time from start of reception until data is available on the receiver data output pin is equal to 9 bit.
5.56 RF Receive, 315 MHz
TA = 25°C, VCC = 3 V (unless otherwise noted) (1)
2-FSK, 1% packet error rate, 20-byte packet length, Sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF = 0 (unless
otherwise noted)
PARAMETER
Receiver sensitivity
(1)
(2)
(3)
(4)
DATA RATE
(kBaud)
TEST CONDITIONS
TYP
0.6
14.3-kHz deviation, 58-kHz digital channel filter bandwidth
–117
1.2
5.2-kHz deviation, 58-kHz digital channel filter bandwidth (2)
–111
38.4
20-kHz deviation, 100-kHz digital channel filter bandwidth (3)
250
127-kHz deviation, 540-kHz digital channel filter bandwidth
500
MSK, 812-kHz digital channel filter bandwidth (4)
(4)
–103
UNIT
dBm
–95
–86
All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 7-1).
Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF =1. The typical current consumption is then
reduced by approximately 2 mA close to the sensitivity limit. The sensitivity is typically reduced to –109 dBm.
Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF =1. The typical current consumption is then
reduced by approximately 2 mA close to the sensitivity limit. The sensitivity is typically reduced to –102 dBm.
MDMCFG2.DEM_DCFILT_OFF =1 cannot be used for data rates ≥ 250kBaud.
5.57 RF Receive, 433 MHz
TA = 25°C, VCC = 3 V (unless otherwise noted) (1)
2-FSK, 1% packet error rate, 20-byte packet length, Sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF = 0 (unless
otherwise noted)
PARAMETER
Receiver sensitivity
(1)
(2)
(3)
(4)
DATA RATE
(kBaud)
TEST CONDITIONS
TYP
0.6
14.3-kHz deviation, 58-kHz digital channel filter bandwidth
–114
1.2
5.2-kHz deviation, 58-kHz digital channel filter bandwidth (2)
–111
38.4
20-kHz deviation, 100-kHz digital channel filter bandwidth (3)
250
127-kHz deviation, 540-kHz digital channel filter bandwidth
500
MSK, 812-kHz digital channel filter bandwidth (4)
(4)
–104
UNIT
dBm
–93
–85
All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 7-1).
Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF =1. The typical current consumption is then
reduced by approximately 2 mA close to the sensitivity limit. The sensitivity is typically reduced to –109 dBm.
Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF =1. The typical current consumption is then
reduced by approximately 2 mA close to the sensitivity limit. The sensitivity is typically reduced to –101 dBm.
MDMCFG2.DEM_DCFILT_OFF =1 cannot be used for data rates ≥ 250kBaud.
Specifications
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CC430F5137, CC430F5135, CC430F5133
SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
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5.58 RF Receive, 868 or 915 MHz
TA = 25°C, VCC = 3 V (unless otherwise noted) (1)
1% packet error rate, 20-byte packet length, Sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF = 0 (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.6-kBaud data rate, 2-FSK, 14.3-kHz deviation, 58-kHz digital channel filter bandwidth (unless otherwise noted)
Receiver sensitivity
–115
dBm
1.2-kBaud data rate, 2-FSK, 5.2-kHz deviation, 58-kHz digital channel filter bandwidth (unless otherwise noted)
–109
Receiver sensitivity (2)
2-GFSK modulation by setting MDMCFG2.MOD_FORMAT = 2,
Gaussian filter with BT = 0.5
Saturation
FIFOTHR.CLOSE_IN_RX =0 (3)
Adjacent channel
rejection
Desired channel 3 dB above the sensitivity limit, 100kHz channel spacing (4)
Image channel rejection
IF 152 kHz, desired channel 3 dB above the sensitivity
limit
Blocking
Desired channel 3 dB above the sensitivity limit (5)
–109
–28
–100-kHz offset
39
+100-kHz offset
39
dBm
dBm
dB
29
dB
±2-MHz offset
–48
dBm
±10-MHz offset
–40
dBm
38.4-kBaud data rate, 2-FSK, 20-kHz deviation, 100-kHz digital channel filter bandwidth (unless otherwise noted)
–102
Receiver sensitivity (6)
2-GFSK modulation by setting MDMCFG2.MOD_FORMAT = 2,
Gaussian filter with BT = 0.5
Saturation
FIFOTHR.CLOSE_IN_RX =0 (3)
–19
–200-kHz offset
20
+200-kHz offset
25
Adjacent channel
rejection
Desired channel 3 dB above the sensitivity limit, 200kHz channel spacing (5)
Image channel rejection
IF 152 kHz, desired channel 3 dB above the sensitivity limit
Desired channel 3 dB above the sensitivity limit (5)
Blocking
–101
dBm
dBm
dB
23
dB
±2-MHz offset
–48
dBm
±10-MHz offset
–40
dBm
250-kBaud data rate, 2-FSK, 127-kHz deviation, 540-kHz digital channel filter bandwidth (unless otherwise noted)
–90
Receiver sensitivity
(7)
Saturation
2-GFSK modulation by setting MDMCFG2.MOD_FORMAT = 2,
Gaussian filter with BT = 0.5
–90
FIFOTHR.CLOSE_IN_RX =0 (3)
–19
–750-kHz offset
24
+750-kHz offset
30
Adjacent channel
rejection
Desired channel 3 dB above the sensitivity limit, 750kHz channel spacing (8)
Image channel rejection
IF 304 kHz, desired channel 3 dB above the sensitivity limit
Blocking
Desired channel 3 dB above the sensitivity limit (8)
dBm
dBm
dB
18
dB
±2-MHz offset
–53
dBm
±10-MHz offset
–39
dBm
–84
dBm
–2
dB
±2-MHz offset
–53
dBm
±10-MHz offset
–38
dBm
500-kBaud data rate, MSK, 812-kHz digital channel filter bandwidth (unless otherwise noted)
Receiver sensitivity (7)
Image channel rejection
IF 355 kHz, desired channel 3 dB above the sensitivity limit
Blocking
Desired channel 3 dB above the sensitivity limit (9)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
52
All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 7-1).
Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF =1. The typical current consumption is then
reduced by approximately 2 mA close to the sensitivity limit. The sensitivity is typically reduced to –107 dBm
See DN010 Close-in Reception with CC1101.
See Figure 5-21 for blocking performance at other offset frequencies.
See Figure 5-22 for blocking performance at other offset frequencies.
Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF =1. The typical current consumption is then
reduced by approximately 2 mA close to the sensitivity limit. The sensitivity is typically reduced to –100 dBm.
MDMCFG2.DEM_DCFILT_OFF = 1 cannot be used for data rates ≥ 250kBaud.
See Figure 5-23 for blocking performance at other offset frequencies.
See Figure 5-24 for blocking performance at other offset frequencies.
Specifications
Copyright © 2009–2018, Texas Instruments Incorporated
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SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
60
80
70
50
60
40
Selectivity (dB)
Blocking (dB)
50
40
30
20
10
30
20
10
0
0
-10
-20
-10
-40
-30
-20
-10
0
10
20
30
-1
40
-0.8 -0.6 -0.4 -0.2
Offset (MHz)
0
0.2
0.4 0.6
0.8
1
0.4 0.6
0.8
1
Offset (MHz)
NOTE: 868.3 MHz, 2-FSK, 5.2-kHz deviation, IF is 152.3 kHz, digital channel filter bandwidth is 58 kHz
Figure 5-21. Typical Selectivity at 1.2-kBaud Data Rate
50
80
70
40
60
30
Selectivity (dB)
Blocking (dB)
50
40
30
20
10
20
10
0
0
-10
-10
-20
-20
-40
-30
-20
-10
0
10
20
30
40
-1
-0.8 -0.6 -0.4 -0.2
Offset (MHz)
0
0.2
Offset (MHz)
NOTE: 868 MHz, 2-FSK, 20 kHz deviation, IF is 152.3 kHz, digital channel filter bandwidth is 100 kHz
Figure 5-22. Typical Selectivity at 38.4-kBaud Data Rate
Specifications
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CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
www.ti.com
50
80
70
40
60
30
Selectivity (dB)
Blocking (dB)
50
40
30
20
10
20
10
0
0
-10
-10
-20
-20
-40
-30
-20
-10
0
10
20
30
-3
40
-2
-1
0
1
2
3
Offset (MHz)
Offset (MHz)
NOTE: 868 MHz, 2-FSK, IF is 304 kHz, digital channel filter bandwidth is 540 kHz
Figure 5-23. Typical Selectivity at 250-kBaud Data Rate
50
80
70
40
60
30
Selectivity (dB)
Blocking (dB)
50
40
30
20
10
20
10
0
0
-10
-10
-20
-20
-40
-30
-20
-10
0
10
20
30
40
-3
-2
-1
0
1
2
3
Offset (MHz)
Offset (MHz)
NOTE: 868 MHz, 2-FSK, IF is 355 kHz, digital channel filter bandwidth is 812 kHz
Figure 5-24. Typical Selectivity at 500-kBaud Data Rate
54
Specifications
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CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
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SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
5.59 Typical Sensitivity, 315 MHz, Sensitivity Optimized Setting
PARAMETER
Sensitivity,
315 MHz
DATA RATE
(kBaud)
VCC
TA
2V
3V
3.6 V
–40°C
25°C
85°C
–40°C
25°C
85°C
–40°C
25°C
85°C
1.2
–112
–112
–110
–112
–111
–109
–112
–111
–108
38.4
–105
–105
–104
–105
–103
–102
–105
–104
–102
250
–95
–95
–92
–94
–95
–92
–95
–94
–91
UNIT
dBm
5.60 Typical Sensitivity, 433 MHz, Sensitivity Optimized Setting
PARAMETER
Sensitivity,
433 MHz
DATA RATE
(kBaud)
VCC
TA
2V
3V
3.6 V
–40°C
25°C
85°C
–40°C
25°C
85°C
–40°C
25°C
85°C
1.2
–111
–110
–108
–111
–111
–108
–111
–110
–107
38.4
–104
–104
–101
–104
–104
–101
–104
–103
–101
250
–93
–94
–91
–93
–93
–90
–93
–93
–90
UNIT
dBm
5.61 Typical Sensitivity, 868 MHz, Sensitivity Optimized Setting
PARAMETER
Sensitivity,
868 MHz
DATA RATE
(kBaud)
VCC
TA
2V
3V
3.6 V
–40°C
25°C
85°C
–40°C
25°C
85°C
–40°C
25°C
85°C
1.2
–109
–109
–107
–109
–109
–106
–109
–108
–106
38.4
–102
–102
–100
–102
–102
–99
–102
–101
–99
250
–90
–90
–88
–89
–90
–87
–89
–90
–87
500
–84
–84
–81
–84
–84
–80
–84
–84
-80
UNIT
dBm
5.62 Typical Sensitivity, 915 MHz, Sensitivity Optimized Setting
PARAMETER
Sensitivity,
915 MHz
DATA RATE
(kBaud)
VCC
TA
2V
3V
3.6 V
–40°C
25°C
85°C
–40°C
25°C
85°C
–40°C
25°C
85°C
1.2
–109
–109
–107
–109
–109
–106
–109
–108
–105
38.4
–102
–102
–100
–102
–102
–99
–103
–102
–99
250
–92
–92
–89
–92
–92
–88
–92
–92
–88
500
–87
–86
–81
–86
–86
–81
–86
–85
–80
Specifications
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UNIT
dBm
55
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
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5.63 RF Transmit
TA = 25°C, VCC = 3 V (unless otherwise noted) (1)
PTX = +10 dBm (unless otherwise noted)
PARAMETER
FREQUENCY
(MHz)
TEST CONDITIONS
TYP
315
Differential load impedance (2)
122 + j31
433
116 + j41
868, 915
86.5 + j43
315
Output power, highest
setting (3)
433
868
433
Harmonics, radiated (4) (5) (6)
868
915
315
433
Harmonics, conducted
868
915
315
Delivered to a 50-Ω single-ended load from CC430 reference
design RF matching network
Spurious emissions,
conducted, harmonics not
included (8)
868
TX latency (9)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
56
+11
Delivered to a 50-Ω single-ended load from CC430 reference
design RF matching network
–30
Second harmonic
–56
Third harmonic
–57
Second harmonic
–50
Third harmonic
–52
Second harmonic
–50
Third harmonic
dBm
+10 dBm CW
Frequencies above 960 MHz
Frequencies below 1 GHz
+10 dBm CW
Frequencies above 1 GHz
Second harmonic
+10 dBm CW
Other harmonics
Second harmonic
+11 dBm CW (7)
Other harmonics
Frequencies below 960 MHz
+10 dBm CW
Frequencies above 960 MHz
< –38
< –48
–45
< –48
–59
–53
< –47
< –58
< –53
+10 dBm CW
< –54
< –63
Frequencies below 1 GHz
< –46
Frequencies above 1 GHz
Serial operation
dBm
< –71
Frequencies from 47 to 74, 87.5 to 118,
174 to 230, 470 to 862 MHz
Frequencies above 960 MHz
dBm
< –54
Frequencies above 1 GHz
Frequencies below 960 MHz
dBm
–54
Frequencies below 960 MHz
+10 dBm CW
Frequencies from 47 to 74, 87.5 to 118,
174 to 230, 470 to 862 MHz
915
+13
+11
Frequencies below 1 GHz
433
Ω
+12
915
Output power, lowest
setting (3)
UNIT
dBm
< –59
< –56
+11 dBm CW
< –49
< –63
8
bits
All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 7-1).
Differential impedance as seen from the RF port (RF_P and RF_N) towards the antenna. Follow the CC430 reference designs available
from the TI website.
Output power is programmable, and the full range is available in all frequency bands. Output power may be restricted by regulatory
limits. Also see AN050 Using the CC1101 in the European 868MHz SRD Band and DN013 Programming Output Power on CC1101,
which gives the output power and harmonics when using multilayer inductors. The output power is then typically +10 dBm when
operating at 868 or 915 MHz.
The antennas used during the radiated measurements (SMAFF-433 from R.W.Badland and Nearson S331 868/915) play a part in
attenuating the harmonics.
Measured on EM430F6137RF900 with CW, maximum output power
All harmonics are below –41.2 dBm when operating in the 902 to 928 MHz band.
Requirement is –20 dBc under FCC 15.247.
All radiated spurious emissions are within the limits of ETSI. Also see DN017 CC11xx 868/915 MHz RF Matching.
Time from sampling the data on the transmitter data input pin until it is observed on the RF output ports
Specifications
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SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
5.64 Optimum PATABLE Settings for Various Output Power Levels and Frequency Bands
TA = 25°C, VCC = 3 V (unless otherwise noted) (1)
OUTPUT POWER (dBm)
(1)
PATABLE SETTING
315 MHz
433 MHz
868 MHz
915 MHz
–30
0x12
0x05
0x03
0x03
–12
0x33
0x26
0x25
0x25
–6
0x29
0x2D
0x2D
0x2D
0
0x51
0x50
0x8D
0x8D
10
0xC4
0xC4
0xC3
0xC3
Maximum
0xC0
0xC0
0xC0
0xC0
All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 7-1).
Specifications
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CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
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SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
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5.65 Typical Output Power, 315 MHz (1)
VCC
2V
3V
3.6 V
TA
25°C
25°C
25°C
0xC0 (maximum)
11.9
11.8
11.8
0xC4 (10 dBm)
10.3
10.3
10.3
PARAMETER
PATABLE SETTING
Output power, 315 MHz
(1)
0xC6 (default)
UNIT
9.3
dBm
0x51 (0 dBm)
0.7
0.6
0.7
0x29 (–6 dBm)
–6.8
–5.6
–5.3
All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 7-1).
5.66 Typical Output Power, 433 MHz (1)
VCC
2V
3V
3.6 V
TA
25°C
25°C
25°C
0xC0 (maximum)
12.6
12.6
12.6
0xC4 (10 dBm)
10.3
10.2
10.2
PARAMETER
PATABLE SETTING
Output power, 433 MHz
(1)
0xC6 (default)
UNIT
10.0
dBm
0x50 (0 dBm)
0.3
0.3
0.3
0x2D (–6 dBm)
–6.4
–5.4
–5.1
All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 7-1).
5.67 Typical Output Power, 868 MHz (1)
PARAMETER
Output power,
868 MHz
(1)
PATABLE SETTING
VCC
TA
2V
3V
3.6 V
–40°C
25°C
85°C
–40°C
25°C
85°C
–40°C
25°C
85°C
0xC0 (maximum)
11.9
11.2
10.5
11.9
11.2
10.5
11.9
11.2
10.5
0xC3 (10 dBm)
10.8
10.1
9.4
10.8
10.1
9.4
10.7
10.1
9.4
0x8D (0 dBm)
1.0
0.3
–0.3
1.1
0.3
–0.3
1.1
0.3
–0.3
0x2D (–6 dBm)
–6.5
–6.8
–7.3
–5.3
–5.8
–6.3
–4.9
–5.4
–6.0
0xC6 (default)
8.8
UNIT
dBm
All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 7-1).
5.68 Typical Output Power, 915 MHz (1)
PARAMETER
Output power,
915 MHz
(1)
58
PATABLE SETTING
VCC
TA
2V
3V
3.6 V
–40°C
25°C
85°C
–40°C
25°C
85°C
–40°C
25°C
85°C
0xC0 (maximum)
12.2
11.4
10.6
12.1
11.4
10.7
12.1
11.4
10.7
0xC3 (10 dBm)
11.0
10.3
9.5
11.0
10.3
9.5
11.0
10.3
9.6
0x8D (0 dBm)
1.9
1.0
0.3
1.9
1.0
0.3
1.9
1.1
0.3
0x2D (–6 dBm)
–5.5
–6.0
–6.5
–4.3
–4.8
–5.5
–3.9
–4.4
–5.1
0xC6 (default)
8.8
UNIT
dBm
All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 7-1).
Specifications
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CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
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SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
5.69 Frequency Synthesizer Characteristics
TA = 25°C, VCC = 3 V (unless otherwise noted) (1)
MIN figures are given using a 27MHz crystal. TYP and MAX figures are given using a 26MHz crystal.
PARAMETER
Programmed frequency resolution (2)
Synthesizer frequency tolerance
TEST CONDITIONS
26- to 27-MHz crystal
MIN
TYP
MAX
UNIT
397
fXOSC / 216
412
Hz
(3)
±40
50-kHz offset from carrier
–95
100-kHz offset from carrier
–94
200-kHz offset from carrier
–94
500-kHz offset from carrier
RF carrier phase noise
–98
1-MHz offset from carrier
–107
2-MHz offset from carrier
–112
5-MHz offset from carrier
–118
10-MHz offset from carrier
PLL turnon and hop time (4)
Crystal oscillator running
88.4
88.4
µs
9.6
9.6
µs
21.5
21.5
µs
721
µs
9.3
PLL TX to RX settling time (6)
20.7
PLL calibration time (7)
694
721
(1)
(2)
(3)
(4)
(5)
(6)
(7)
dBc/Hz
–129
85.1
(5)
PLL RX to TX settling time
ppm
All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 7-1).
The resolution (in Hz) is equal for all frequency bands.
Depends on crystal used. Required accuracy (including temperature and aging) depends on frequency band and channel bandwidth and
spacing.
Time from leaving the IDLE state until arriving in the RX, FSTXON, or TX state, when not performing calibration.
Settling time for the 1-IF step from RX to TX
Settling time for the 1-IF step from TX to RX
Calibration can be initiated manually or automatically before entering or after leaving RX or TX.
Specifications
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59
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
www.ti.com
5.70 Typical RSSI_offset Values
TA = 25°C, VCC = 3 V (unless otherwise noted) (1)
RSSI_OFFSET (dB)
DATA RATE (kBaud)
(1)
433 MHz
868 MHz
1.2
74
74
38.4
74
74
250
74
74
500
74
74
All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 7-1).
0
0
250kBaud
1.2kBaud
-20
38.4kBaud
-40
RSSI Readout (dBm)
RSSI Readout (dBm)
-20
-60
-80
-60
-80
-100
-100
-120
-120
500kBaud
-40
-100
-80
-60
-40
-20
0
-120
-120
Input Power (dBm)
-100
-80
-60
-40
-20
0
Input Power (dBm)
Figure 5-25. Typical RSSI Value vs Input Power Level for Different Data Rates at 868 MHz
60
Specifications
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CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
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SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
6 Detailed Description
6.1
Sub-1 GHz Radio
The implemented sub-1 GHz radio module is based on the industry-leading CC1101, requiring very few
external components. Figure 6-1 shows a high-level block diagram of the implemented radio.
RF_P
0
RF_N
Frequency
Synthesizer
90
BIAS
RC OSC
RBIAS
XOSC
RF_XIN
Modulator
PA
Interface to MCU
ADC
TX FIFO
LNA
Packet Handler
ADC
RX FIFO
Demodulator
Radio Control
RF_XOUT
Copyright © 2017, Texas Instruments Incorporated
Figure 6-1. Sub-1 GHz Radio Block Diagram
The radio features a low-IF receiver. The received RF signal is amplified by a low-noise amplifier (LNA)
and down-converted in quadrature to the intermediate frequency (IF). At IF, the I/Q signals are digitized.
Automatic gain control (AGC), fine channel filtering, demodulation bit, and packet synchronization are
performed digitally.
The transmitter part is based on direct synthesis of the RF. The frequency synthesizer includes a
completely on-chip LC VCO and a 90° phase shifter for generating the I and Q LO signals to the downconversion mixers in receive mode.
The 26-MHz crystal oscillator generates the reference frequency for the synthesizer, as well as clocks for
the ADC and the digital part.
A memory mapped register interface is used for data access, configuration, and status request by the
CPU.
The digital baseband includes support for channel configuration, packet handling, and data buffering.
For complete module descriptions, see the CC430 Family User's Guide.
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CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and
constant generator, respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses. The peripherals can be
managed with all instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word and
byte data.
6.3
Operating Modes
The CC430 has one active mode and five software-selectable low-power modes of operation. An interrupt
event can wake up the device from any of the low-power modes, service the request, and restore back to
the low-power mode on return from the interrupt program.
Software can configure the following operating modes:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– FLL loop control remains active
• Low-power mode 1 (LPM1)
– CPU is disabled
– FLL loop control is disabled
– ACLK and SMCLK remain active, MCLK is disabled
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK and FLL loop control and DCOCLK are disabled
– DC generator of the DCO remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO is disabled
– Crystal oscillator is stopped
– Complete data retention
62
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6.4
SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh–0FF80h
(see Table 6-1). The vector contains the 16-bit address of the appropriate interrupt-handler instruction
sequence.
asd
Table 6-1. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
System Reset
Power-Up
External Reset
Watchdog Time-out, Password
Violation
Flash Memory Password Violation
WDTIFG, KEYV (SYSRSTIV) (1) (2)
Reset
0FFFEh
63, highest
System NMI
PMM
Vacant Memory Access
JTAG Mailbox
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,
JMBOUTIFG (SYSSNIV) (1) (3)
(Non)maskable
0FFFCh
62
User NMI
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG, OFIFG, ACCVIFG (SYSUNIV) (1) (3)
(Non)maskable
0FFFAh
61
Comparator_B
Comparator_B Interrupt Flags (CBIV) (1)
Maskable
0FFF8h
60
Watchdog Interval Timer Mode
WDTIFG
Maskable
0FFF6h
59
USCI_A0 Receive or Transmit
UCA0RXIFG, UCA0TXIFG (UCA0IV) (1)
Maskable
0FFF4h
58
USCI_B0 Receive or Transmit
UCB0RXIFG, UCB0TXIFG, I2C Status Interrupt
Flags (UCB0IV) (1)
Maskable
0FFF2h
57
ADC12_A
(Reserved on CC430F612x)
ADC12IFG0 ... ADC12IFG15 (ADC12IV) (1)
Maskable
0FFF0h
56
TA0
TA0CCR0 CCIFG0
Maskable
0FFEEh
55
TA0
TA0CCR1 CCIFG1 ... TA0CCR4 CCIFG4,
TA0IFG (TA0IV) (1)
Maskable
0FFECh
54
RF1A CC1101-based Radio
Radio Interface Interrupt Flags (RF1AIFIV)
Radio Core Interrupt Flags (RF1AIV)
Maskable
0FFEAh
53
DMA
DMA0IFG, DMA1IFG, DMA2IFG (DMAIV) (1)
Maskable
0FFE8h
52
TA1
TA1CCR0 CCIFG0
Maskable
0FFE6h
51
TA1
TA1CCR1 CCIFG1 ... TA1CCR2 CCIFG2,
TA1IFG (TA1IV) (1)
Maskable
0FFE4h
50
I/O Port P1
P1IFG.0 to P1IFG.7 (P1IV)
(1)
Maskable
0FFE2h
49
I/O Port P2
P2IFG.0 to P2IFG.7 (P2IV) (1)
Maskable
0FFE0h
48
LCD_B
(Reserved on CC430F513x)
LCD_B Interrupt Flags (LCDBIV) (1)
Maskable
0FFDEh
47
RTC_A
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RT0PSIFG, RT1PSIFG (RTCIV) (1)
Maskable
0FFDCh
46
AES
AESRDYIFG
Maskable
0FFDAh
45
0FFD8h
44
⋮
⋮
0FF80h
0, lowest
Reserved
(1)
(2)
(3)
(4)
Reserved (4)
Multiple source flags
A reset is generated if the CPU tries to fetch instructions from within peripheral space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, reserve these locations.
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Memory Organization
Table 6-2 summarizes the memory map of the devices.
Table 6-2. Memory Organization
Main Memory
(flash)
CC430F6137
CC430F6127
CC430F5137 (1)
CC430F6126 (1)
CC430F6135
CC430F6125
CC430F5135 (1)
CC430F5133 (1)
32KB
32KB
16KB
8KB
00FFFFh–00FF80h
00FFFFh–00FF80h
00FFFFh–00FF80h
00FFFFh–00FF80h
32KB
00FFFFh–008000h
32KB
00FFFFh–008000h
16KB
00FFFFh–00C000h
8KB
00FFFFh–00E000h
4KB
2KB
2KB
2KB
Sect 1
2KB
002BFFh–002400h
not available
not available
not available
Sect 0
2KB
0023FFh–001C00h
2KB
0023FFh–001C00h
2KB
0023FFh–001C00h
2KB
0023FFh–001C00h
128 B
001AFFh–001A80h
128 B
001AFFh–001A80h
128 B
001AFFh–001A80h
128 B
001AFFh–001A80h
128 B
001A7Fh–001A00h
128 B
001A7Fh–001A00h
128 B
001A7Fh–001A00h
128 B
001A7Fh–001A00h
Info A
128 B
0019FFh–001980h
128 B
0019FFh–001980h
128 B
0019FFh–001980h
128 B
0019FFh–001980h
Info B
128 B
00197Fh–001900h
128 B
00197Fh–001900h
128 B
00197Fh–001900h
128 B
00197Fh–001900h
Info C
128 B
0018FFh–001880h
128 B
0018FFh–001880h
128 B
0018FFh–001880h
128 B
0018FFh–001880h
Info D
128 B
00187Fh–001800h
128 B
00187Fh–001800h
128 B
00187Fh–001800h
128 B
00187Fh–001800h
BSL 3
512 B
0017FFh–001600h
512 B
0017FFh–001600h
512 B
0017FFh–001600h
512 B
0017FFh–001600h
BSL 2
512 B
0015FFh–001400h
512 B
0015FFh–001400h
512 B
0015FFh–001400h
512 B
0015FFh–001400h
BSL 1
512 B
0013FFh–001200h
512 B
0013FFh–001200h
512 B
0013FFh–001200h
512 B
0013FFh–001200h
BSL 0
512 B
0011FFh–001000h
512 B
0011FFh–001000h
512 B
0011FFh–001000h
512 B
0011FFh–001000h
4KB
000FFFh–0h
4KB
000FFFh–0h
4KB
000FFFh–0h
4KB
000FFFh–0h
Total
Size
Main: Interrupt
vector
Main: code
memory
Bank 0
Total
Size
RAM
Device
Descriptor
Information
memory (flash)
Bootloader
(BSL) memory
(flash)
Peripherals
(1)
64
All memory regions not specified here are vacant memory, and any access to them causes a Vacant Memory Interrupt.
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6.6
SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
Bootloader (BSL)
The BSL enables users to program the flash memory or RAM using various serial interfaces. Table 6-3
lists the pin requirements. Access to the device memory through the BSL is protected by a user-defined
password. BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK
pins. For a complete description of the features of the BSL and its implementation, see MSP430
Programming With the Bootloader (BSL).
Table 6-3. UART BSL Pin Requirements and Functions
6.7
6.7.1
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
TEST/SBWTCK
Entry sequence signal
P1.6
Data transmit
P1.5
Data receive
VCC
Power supply
VSS
Ground supply
JTAG Operation
JTAG Standard Interface
The CC430 family supports the standard JTAG interface which requires four signals for sending and
receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to
enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with
MSP430 development tools and device programmers. Table 6-4 lists the JTAG pin requirements. For
further details on interfacing to development tools and device programmers, see the MSP430 Hardware
Tools User's Guide. For a complete description of the features of the JTAG interface and its
implementation, see MSP430 Programming With the JTAG Interface.
Table 6-4. JTAG Pin Requirements and Functions
DEVICE SIGNAL
DIRECTION
FUNCTION
PJ.3/TCK
IN
JTAG clock input
PJ.2/TMS
IN
JTAG state control
PJ.1/TDI/TCLK
IN
JTAG data input, TCLK input
PJ.0/TDO
OUT
JTAG data output
TEST/SBWTCK
IN
Enable JTAG pins
RST/NMI/SBWTDIO
IN
External reset
VCC
Power supply
VSS
Ground supply
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Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the CC430 family supports the two wire Spy-Bi-Wire interface.
Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. Table 6-5
lists the Spy-Bi-Wire interface pin requirements. For further details on interfacing to development tools and
device programmers, see the MSP430 Hardware Tools User's Guide. For a complete description of the
features of the JTAG interface and its implementation, see MSP430 Programming With the JTAG
Interface.
Table 6-5. Spy-Bi-Wire Pin Requirements and Functions
6.8
DEVICE SIGNAL
DIRECTION
FUNCTION
TEST/SBWTCK
IN
Spy-Bi-Wire clock input
RST/NMI/SBWTDIO
IN, OUT
Spy-Bi-Wire data input/output
VCC
Power supply
VSS
Ground supply
Flash Memory
The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), or in-system by the
CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features
of the flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (Info A to
Info D) of 128 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments Info A to Info D can be erased individually, or as a group with the main memory segments.
Segments Info A to Info D are also called information memory.
• Segment A can be locked separately.
6.9
RAM
The RAM is made up of n sectors. Each sector can be completely powered down to save leakage;
however, all data are lost. Features of the RAM include:
• RAM has n sectors of 2KB each.
• Each sector 0 to n can be completely disabled; however, data retention is lost.
• Each sector 0 to n automatically enters low power retention mode when possible.
66
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6.10 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. The peripherals can be
managed using all instructions. For complete module descriptions, see the CC430 Family User's Guide.
6.10.1 Oscillator and System Clock
The Unified Clock System (UCS) module includes support for a 32768-Hz watch crystal oscillator, an
internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator
(REFO), an integrated internal digitally controlled oscillator (DCO), and a high-frequency crystal oscillator.
The UCS module is designed to meet the requirements of both low system cost and low-power
consumption. The UCS module features digital frequency locked loop (FLL) hardware that, in conjunction
with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal
frequency. The internal DCO provides a fast turnon clock source and stabilizes in less than 5 µs. The UCS
module provides the following clock signals:
• Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high-frequency crystal, the internal
low-frequency oscillator (VLO), or the trimmed low-frequency oscillator (REFO).
• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made
available to ACLK.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be
sourced by same sources made available to ACLK.
• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
6.10.2 Power-Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device and
contains programmable output levels to provide for power optimization. The PMM also includes supply
voltage supervisor (SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection.
The brownout circuit is implemented to provide the proper internal reset signal to the device during poweron and power-off. The SVS/SVM circuitry detects if the supply voltage drops below a user-selectable level
and supports both supply voltage supervision (the device is automatically reset) and supply voltage
monitoring (the device is not automatically reset). SVS and SVM circuitry is available on the primary
supply and core supply.
6.10.3 Digital I/O
Up to five 8-bit I/O ports are implemented: ports P1 through P5.
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports.
• Programmable drive strength on all ports.
• Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
• Read and write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise (P1 through P5) or word-wise in pairs (PA and PB).
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6.10.4 Port Mapping Controller
The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port pins
of ports P1 through P3 (see Table 6-6). Table 6-7 lists the default settings for all pins that support port
mapping.
Table 6-6. Port Mapping, Mnemonics and Functions
VALUE
PxMAPy MNEMONIC
INPUT PIN FUNCTION
(PxDIR.y = 0)
OUTPUT PIN FUNCTION
(PxDIR.y = 1)
0
PM_NONE
None
DVSS
PM_CBOUT0
–
Comparator_B output (on TA0 clock
input)
PM_TA0CLK
TA0 clock input
–
PM_CBOUT1
–
Comparator_B output (on TA1 clock
input)
PM_TA1CLK
TA1 clock input
–
PM_ACLK
None
ACLK output
4
PM_MCLK
None
MCLK output
5
PM_SMCLK
None
SMCLK output
6
PM_RTCCLK
None
RTCCLK output
PM_ADC12CLK
–
ADC12CLK output
PM_DMAE0
DMA external trigger input
–
8
PM_SVMOUT
None
SVM output
9
PM_TA0CCR0A
TA0 CCR0 capture input CCI0A
TA0 CCR0 compare output Out0
10
PM_TA0CCR1A
TA0 CCR1 capture input CCI1A
TA0 CCR1 compare output Out1
11
PM_TA0CCR2A
TA0 CCR2 capture input CCI2A
TA0 CCR2 compare output Out2
12
PM_TA0CCR3A
TA0 CCR3 capture input CCI3A
TA0 CCR3 compare output Out3
13
PM_TA0CCR4A
TA0 CCR4 capture input CCI4A
TA0 CCR4 compare output Out4
14
PM_TA1CCR0A
TA1 CCR0 capture input CCI0A
TA1 CCR0 compare output Out0
15
PM_TA1CCR1A
TA1 CCR1 capture input CCI1A
TA1 CCR1 compare output Out1
16
PM_TA1CCR2A
TA1 CCR2 capture input CCI2A
TA1 CCR2 compare output Out2
1 (1)
2 (1)
3
7 (1)
17 (2)
18 (2)
19 (3)
20 (4)
21 (4)
(4)
(5)
68
USCI_A0 UART RXD (direction controlled by USCI – input)
PM_UCA0SOMI
USCI_A0 SPI slave out master in (direction controlled by USCI)
PM_UCA0TXD
USCI_A0 UART TXD (direction controlled by USCI – output)
PM_UCA0SIMO
USCI_A0 SPI slave in master out (direction controlled by USCI)
PM_UCA0CLK
USCI_A0 clock input/output (direction controlled by USCI)
PM_UCB0STE
USCI_B0 SPI slave transmit enable (direction controlled by USCI – input)
PM_UCB0SOMI
USCI_B0 SPI slave out master in (direction controlled by USCI)
PM_UCB0SCL
USCI_B0 I2C clock (open drain and direction controlled by USCI)
PM_UCB0SIMO
USCI_B0 SPI slave in master out (direction controlled by USCI)
PM_UCB0SDA
USCI_B0 I2C data (open drain and direction controlled by USCI)
PM_UCB0CLK
USCI_B0 clock input/output (direction controlled by USCI)
PM_UCA0STE
USCI_A0 SPI slave transmit enable (direction controlled by USCI – input)
23
PM_RFGDO0
Radio GDO0 (direction controlled by Radio)
24
PM_RFGDO1
Radio GDO1 (direction controlled by Radio)
25
PM_RFGDO2
Radio GDO2 (direction controlled by Radio)
22 (5)
(1)
(2)
(3)
PM_UCA0RXD
Input or output function is selected by the corresponding setting in the port direction register PxDIR.
UART or SPI functionality is determined by the selected USCI mode.
UCA0CLK function takes precedence over UCB0STE function. If the mapped pin is required as UCA0CLK input or output, USCI_B0 is
forced to 3-wire SPI mode even if 4-wire mode is selected.
SPI or I2C functionality is determined by the selected USCI mode. In case the I2C functionality is selected the output of the mapped pin
drives only the logical 0 to VSS level.
UCB0CLK function takes precedence over UCA0STE function. If the mapped pin is required as UCB0CLK input or output, USCI_A0 is
forced to 3-wire SPI mode even if 4-wire mode is selected.
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Table 6-6. Port Mapping, Mnemonics and Functions (continued)
VALUE
PxMAPy MNEMONIC
INPUT PIN FUNCTION
(PxDIR.y = 0)
OUTPUT PIN FUNCTION
(PxDIR.y = 1)
26
Reserved
None
DVSS
27
Reserved
None
DVSS
28
Reserved
None
DVSS
29
Reserved
None
DVSS
30
Reserved
None
DVSS
31 (0FFh) (6)
(6)
Disables the output driver and the input Schmitt-trigger to prevent parasitic
cross currents when applying analog signals.
PM_ANALOG
The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are ignored,
resulting in a read value of 31.
Table 6-7. Default Mapping
PIN
PxMAPy MNEMONIC
INPUT PIN FUNCTION
(PxDIR.y = 0)
OUTPUT PIN FUNCTION
(PxDIR.y = 1)
P1.0/P1MAP0
PM_RFGDO0
None
Radio GDO0
P1.1/P1MAP1
PM_RFGDO2
None
Radio GDO2
P1.2/P1MAP2
PM_UCB0SOMI/PM_UCB0SCL
USCI_B0 SPI slave out master in (direction controlled by USCI),
USCI_B0 I2C clock (open drain and direction controlled by USCI)
P1.3/P1MAP3
PM_UCB0SIMO/PM_UCB0SDA
USCI_B0 SPI slave in master out (direction controlled by USCI),
USCI_B0 I2C data (open drain and direction controlled by USCI)
P1.4/P1MAP4
PM_UCB0CLK/PM_UCA0STE
USCI_B0 clock input/output (direction controlled by USCI),
USCI_A0 SPI slave transmit enable (direction controlled by USCI – input)
P1.5/P1MAP5
PM_UCA0RXD/PM_UCA0SOMI
USCI_A0 UART RXD (direction controlled by USCI – input),
USCI_A0 SPI slave out master in (direction controlled by USCI)
P1.6/P1MAP6
PM_UCA0TXD/PM_UCA0SIMO
USCI_A0 UART TXD (direction controlled by USCI – output),
USCI_A0 SPI slave in master out (direction controlled by USCI)
P1.7/P1MAP7
PM_UCA0CLK/PM_UCB0STE
USCI_A0 clock input/output (direction controlled by USCI),
USCI_B0 SPI slave transmit enable (direction controlled by USCI – input)
P2.0/P2MAP0
PM_CBOUT1/PM_TA1CLK
TA1 clock input
Comparator_B output
P2.1/P2MAP1
PM_TA1CCR0A
TA1 CCR0 capture input CCI0A
TA1 CCR0 compare output Out0
P2.2/P2MAP2
PM_TA1CCR1A
TA1 CCR1 capture input CCI1A
TA1 CCR1 compare output Out1
P2.3/P2MAP3
PM_TA1CCR2A
TA1 CCR2 capture input CCI2A
TA1 CCR2 compare output Out2
P2.4/P2MAP4
PM_RTCCLK
None
RTCCLK output
P2.5/P2MAP5
PM_SVMOUT
None
SVM output
P2.6/P2MAP6
PM_ACLK
None
ACLK output
P2.7/P2MAP7
PM_ADC12CLK/PM_DMAE0
DMA external trigger input
ADC12CLK output
P3.0/P3MAP0
PM_CBOUT0/PM_TA0CLK
TA0 clock input
Comparator_B output
P3.1/P3MAP1
PM_TA0CCR0A
TA0 CCR0 capture input CCI0A
TA0 CCR0 compare output Out0
P3.2/P3MAP2
PM_TA0CCR1A
TA0 CCR1 capture input CCI1A
TA0 CCR1 compare output Out1
P3.3/P3MAP3
PM_TA0CCR2A
TA0 CCR2 capture input CCI2A
TA0 CCR2 compare output Out2
P3.4/P3MAP4
PM_TA0CCR3A
TA0 CCR3 capture input CCI3A
TA0 CCR3 compare output Out3
P3.5/P3MAP5
PM_TA0CCR4A
TA0 CCR4 capture input CCI4A
TA0 CCR4 compare output Out4
P3.6/P3MAP6
PM_RFGDO1
None
Radio GDO1
P3.7/P3MAP7
PM_SMCLK
None
SMCLK output
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6.10.5 System Module (SYS)
The SYS module handles many of the system functions within the device. These functions include power
on reset and power up clear handling, NMI source selection and management, reset interrupt vector
generators (see Table 6-8), bootloader entry mechanisms, and configuration management (device
descriptors). SYS also includes a data exchange mechanism through JTAG called a JTAG mailbox that
can be used in the application.
Table 6-8. System Module Interrupt Vector Registers
INTERRUPT VECTOR REGISTER
SYSRSTIV, System Reset
SYSSNIV, System NMI
SYSUNIV, User NMI
70
ADDRESS
019Eh
019Ch
019Ah
INTERRUPT EVENT
VALUE
No interrupt pending
00h
Brownout (BOR)
02h
RST/NMI (POR)
04h
PMMSWBOR (BOR)
06h
Reserved
08h
Security violation (BOR)
0Ah
SVSL (POR)
0Ch
SVSH (POR)
0Eh
SVML_OVP (POR)
10h
SVMH_OVP (POR)
12h
PMMSWPOR (POR)
14h
WDT time-out (PUC)
16h
WDT password violation (PUC)
18h
KEYV flash password violation (PUC)
1Ah
Reserved
1Ch
Peripheral area fetch (PUC)
1Eh
PMM password violation (PUC)
20h
Reserved
22h to 3Eh
No interrupt pending
00h
SVMLIFG
02h
SVMHIFG
04h
DLYLIFG
06h
DLYHIFG
08h
VMAIFG
0Ah
JMBINIFG
0Ch
JMBOUTIFG
0Eh
VLRLIFG
10h
VLRHIFG
12h
Reserved
14h to 1Eh
No interrupt pending
00h
NMIIFG
02h
OFIFG
04h
ACCVIFG
06h
Reserved
08h to 1Eh
Detailed Description
PRIORITY
Highest
Lowest
Highest
Lowest
Highest
Lowest
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6.10.6 DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU
intervention. Using the DMA controller can increase the throughput of peripheral modules. The DMA
controller reduces system power consumption by allowing the CPU to remain in sleep mode, without
having to awaken to move data to or from a peripheral. Table 6-9 lists the available triggers for DMA
operation.
Table 6-9. DMA Trigger Assignments (1)
CHANNEL
TRIGGER
(1)
(2)
0
1
2
0
DMAREQ
DMAREQ
DMAREQ
1
TA0CCR0 CCIFG
TA0CCR0 CCIFG
TA0CCR0 CCIFG
2
TA0CCR2 CCIFG
TA0CCR2 CCIFG
TA0CCR2 CCIFG
3
TA1CCR0 CCIFG
TA1CCR0 CCIFG
TA1CCR0 CCIFG
4
TA1CCR2 CCIFG
TA1CCR2 CCIFG
TA1CCR2 CCIFG
5
Reserved
Reserved
Reserved
6
Reserved
Reserved
Reserved
7
Reserved
Reserved
Reserved
8
Reserved
Reserved
Reserved
9
Reserved
Reserved
Reserved
10
Reserved
Reserved
Reserved
11
Reserved
Reserved
Reserved
12
Reserved
Reserved
Reserved
13
Reserved
Reserved
Reserved
14
Reserved
Reserved
Reserved
15
Reserved
Reserved
Reserved
16
UCA0RXIFG
UCA0RXIFG
UCA0RXIFG
17
UCA0TXIFG
UCA0TXIFG
UCA0TXIFG
18
UCB0RXIFG
UCB0RXIFG
UCB0RXIFG
19
UCB0TXIFG
UCB0TXIFG
UCB0TXIFG
20
Reserved
Reserved
Reserved
21
Reserved
Reserved
Reserved
22
Reserved
Reserved
Reserved
23
Reserved
Reserved
(2)
ADC12IFGx
Reserved
(2)
ADC12IFGx (2)
24
ADC12IFGx
25
Reserved
Reserved
Reserved
26
Reserved
Reserved
Reserved
27
Reserved
Reserved
Reserved
28
Reserved
Reserved
Reserved
29
MPY ready
MPY ready
MPY ready
30
DMA2IFG
DMA0IFG
DMA1IFG
31
DMAE0
DMAE0
DMAE0
Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers will not
cause any DMA trigger event when selected.
Only on CC430F613x and CC430F513x. Reserved on CC430F612x.
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6.10.7 Watchdog Timer (WDT_A)
The primary function of the watchdog timer is to perform a controlled system restart after a software
problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function
is not needed in an application, the timer can be configured as an interval timer and can generate
interrupts at selected time intervals.
6.10.8 CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used
for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
6.10.9 Hardware Multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs
operations with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication
as well as signed and unsigned multiply-and-accumulate operations.
6.10.10 AES128 Accelerator
The AES accelerator module performs encryption and decryption of 128-bit data with 128-bit keys
according to the Advanced Encryption Standard (AES) (FIPS PUB 197) in hardware.
6.10.11 Universal Serial Communication Interface (USCI)
The USCI module is used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3-pin or 4-pin) and I2C, and asynchronous communication
protocols such as UART, enhanced UART with automatic baud-rate detection, and IrDA.
The USCI_An module provides support for SPI (3-pin or 4-pin), UART, enhanced UART, and IrDA.
The USCI_Bn module provides support for SPI (3-pin or 4-pin) and I2C.
One USCI_A0 and one USCI_B0 modules are implemented.
72
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6.10.12 TA0
TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. TA0 can support multiple
capture/compares, PWM outputs, and interval timing. TA0 also has extensive interrupt capabilities (see
Table 6-10). Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 6-10. TA0 Signal Connections
DEVICE INPUT SIGNAL
MODULE INPUT NAME
PM_TA0CLK
TACLK
(1)
(2)
MODULE BLOCK
MODULE OUTPUT
SIGNAL
Timer
NA
DEVICE OUTPUT
SIGNAL
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
RFCLK/192 (1)
INCLK
PM_TA0CCR0A
CCI0A
DVSS
CCI0B
DVSS
GND
DVCC
VCC
PM_TA0CCR1A
CCI1A
PM_TA0CCR1A
CBOUT (internal)
CCI1B
ADC12 (internal) (2)
ADC12SHSx = {1}
DVSS
GND
DVCC
VCC
PM_TA0CCR2A
CCI2A
ACLK (internal)
CCI2B
DVSS
GND
DVCC
VCC
PM_TA0CCR3A
CCI3A
GDO1 from Radio
(internal)
CCI3B
DVSS
GND
DVCC
VCC
PM_TA0CCR4A
CCI4A
GDO2 from Radio
(internal)
CCI4B
DVSS
GND
DVCC
VCC
PM_TA0CCR0A
CCR0
CCR1
TA0
TA1
PM_TA0CCR2A
CCR2
TA2
PM_TA0CCR3A
CCR3
TA3
PM_TA0CCR4A
CCR4
TA4
If a different RFCLK divider setting is selected for a radio GDO output, this divider setting is also used for the Timer_A INCLK.
Only on CC430F613x and CC430F513x
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6.10.13 TA1
TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA1 can support
multiple capture/compares, PWM outputs, and interval timing (see Table 6-11). TA1 also has extensive
interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each
of the capture/compare registers.
Table 6-11. TA1 Signal Connections
DEVICE INPUT SIGNAL
PM_TA1CLK
(1)
MODULE INPUT NAME
MODULE BLOCK
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
PZ
TACLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
RFCLK/192 (1)
INCLK
PM_TA1CCR0A
CCI0A
RF Async. Output
(internal)
CCI0B
DVSS
GND
DVCC
VCC
PM_TA1CCR1A
CCI1A
CBOUT (internal)
CCI1B
DVSS
GND
DVCC
VCC
PM_TA1CCR2A
CCI2A
ACLK (internal)
CCI2B
DVSS
GND
DVCC
VCC
Timer
NA
PM_TA1CCR0A
CCR0
TA0
RF Async. Input (internal)
PM_TA1CCR1A
CCR1
TA1
PM_TA1CCR2A
CCR2
TA2
If a different RFCLK divider setting is selected for a radio GDO output, this divider setting is also used for the Timer_A INCLK.
6.10.14 Real-Time Clock (RTC_A)
The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated
real-time clock (RTC) (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit
timers that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by
software. Calendar mode integrates an internal calendar which compensates for months with less than
31 days and includes leap year correction. The RTC_A also supports flexible alarm functions and offsetcalibration hardware.
6.10.15 Voltage Reference (REF)
REF generates all of the critical reference voltages that can be used by the various analog peripherals in
the device. These peripherals include the ADC12_A, LCD_B, and COMP_B modules.
6.10.16 LCD_B (Only CC430F613x and CC430F612x)
The LCD_B driver generates the segment and common signals required to drive a liquid crystal display
(LCD). The LCD_B controller has dedicated data memories to hold segment drive information. Common
and segment signals are generated as defined by the mode. Static, 2-, 3-, and 4-mux LCDs are
supported. The module can provide a LCD voltage independent of the supply voltage with its integrated
charge pump. It is possible to control the level of the LCD voltage and thus contrast by software. The
module also provides an automatic blinking capability for individual segments.
74
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6.10.17 Comparator_B
The primary function of the Comparator_B module is to support precision slope analog-to-digital
conversions, battery voltage supervision, and monitoring of external analog signals.
6.10.18 ADC12_A (Only CC430F613x and CC430F513x)
The ADC12_A module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit
SAR core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored
without any CPU intervention.
6.10.19 Embedded Emulation Module (EEM) (S Version)
The EEM supports real-time in-system debugging. The S version of the EEM has the following features:
• Three hardware triggers or breakpoints on memory access
• One hardware trigger or breakpoint on CPU register write access
• Up to four hardware triggers can be combined to form complex triggers or breakpoints
• One cycle counter
• Clock control on module level
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6.10.20 Peripheral File Map
Table 6-12 lists the base address for the registers of each peripheral.
Table 6-12. Peripherals
76
MODULE NAME
BASE ADDRESS
OFFSET ADDRESS
RANGE
Special Functions (see Table 6-13)
0100h
000h–01Fh
PMM (see Table 6-14)
0120h
000h–00Fh
Flash Control (see Table 6-15)
0140h
000h–00Fh
CRC16 (see Table 6-16)
0150h
000h–007h
RAM Control (see Table 6-17)
0158h
000h–001h
Watchdog (see Table 6-18)
015Ch
000h–001h
UCS (see Table 6-19)
0160h
000h–01Fh
SYS (see Table 6-20)
0180h
000h–01Fh
Shared Reference (see Table 6-21)
01B0h
000h–001h
Port Mapping Control (see Table 6-22)
01C0h
000h–007h
Port Mapping Port P1 (see Table 6-23)
01C8h
000h–007h
Port Mapping Port P2 (see Table 6-24)
01D0h
000h–007h
Port Mapping Port P3 (see Table 6-25)
01D8h
000h–007h
Port P1, P2 (see Table 6-26)
0200h
000h–01Fh
Port P3, P4 (see Table 6-27)
(P4 not available on CC430F513x)
0220h
000h–01Fh
Port P5 (see Table 6-28)
0240h
000h–01Fh
Port PJ (see Table 6-29)
0320h
000h–01Fh
TA0 (see Table 6-30)
0340h
000h–03Fh
TA1 (see Table 6-31)
0380h
000h–03Fh
RTC_A (see Table 6-32)
04A0h
000h–01Fh
32-Bit Hardware Multiplier (see Table 6-33)
04C0h
000h–02Fh
DMA Module Control (see Table 6-34)
0500h
000h–00Fh
DMA Channel 0 (see Table 6-35)
0510h
000h–00Fh
DMA Channel 1 (see Table 6-36)
0520h
000h–00Fh
DMA Channel 2 (see Table 6-37)
0530h
000h–00Fh
USCI_A0 (see Table 6-38)
05C0h
000h–01Fh
USCI_B0 (see Table 6-39)
05E0h
000h–01Fh
ADC12 (see Table 6-40)
(only CC430F613x and CC430F513x)
0700h
000h–03Fh
Comparator_B (see Table 6-41)
08C0h
000h–00Fh
AES Accelerator (see Table 6-42)
09C0h
000h–00Fh
LCD_B (see Table 6-43)
(only CC430F613x and CC430F612x)
0A00h
000h–05Fh
Radio Interface (see Table 6-44)
0F00h
000h–03Fh
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Table 6-13. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
SFR interrupt enable
SFRIE1
00h
SFR interrupt flag
SFRIFG1
02h
SFR reset pin control
SFRRPCR
04h
Table 6-14. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
PMM control 0
PMMCTL0
00h
PMM control 1
PMMCTL1
02h
SVS high side control
SVSMHCTL
04h
SVS low side control
SVSMLCTL
06h
PMM interrupt flags
PMMIFG
0Ch
PMM interrupt enable
PMMIE
0Eh
PMM power mode 5 control
PM5CTL0
10h
Table 6-15. Flash Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
Flash control 1
FCTL1
00h
Flash control 3
FCTL3
04h
Flash control 4
FCTL4
06h
Table 6-16. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
CRC data input
CRC16DI
00h
CRC initialization and result
CRCINIRES
04h
Table 6-17. RAM Control Registers (Base Address: 0158h)
REGISTER DESCRIPTION
RAM control 0
ACRONYM
RCCTL0
OFFSET
00h
Table 6-18. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
Watchdog timer control
ACRONYM
WDTCTL
OFFSET
00h
Table 6-19. UCS Registers (Base Address: 0160h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
UCS control 0
UCSCTL0
00h
UCS control 1
UCSCTL1
02h
UCS control 2
UCSCTL2
04h
UCS control 3
UCSCTL3
06h
UCS control 4
UCSCTL4
08h
UCS control 5
UCSCTL5
0Ah
UCS control 6
UCSCTL6
0Ch
UCS control 7
UCSCTL7
0Eh
UCS control 8
UCSCTL8
10h
Detailed Description
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Table 6-20. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
System control
SYSCTL
00h
Bootloader configuration area
SYSBSLC
02h
JTAG mailbox control
SYSJMBC
06h
JTAG mailbox input 0
SYSJMBI0
08h
JTAG mailbox input 1
SYSJMBI1
0Ah
JTAG mailbox output 0
SYSJMBO0
0Ch
JTAG mailbox output 1
SYSJMBO1
0Eh
Bus error vector generator
SYSBERRIV
18h
User NMI vector generator
SYSUNIV
1Ah
System NMI vector generator
SYSSNIV
1Ch
Reset vector generator
SYSRSTIV
1Eh
Table 6-21. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
Shared reference control
ACRONYM
REFCTL
OFFSET
00h
Table 6-22. Port Mapping Control Registers (Base Address: 01C0h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
Port mapping key
PMAPKEYID
00h
Port mapping control
PMAPCTL
02h
Table 6-23. Port Mapping Port P1 Registers (Base Address: 01C8h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
Port P1.0 mapping
P1MAP0
00h
Port P1.1 mapping
P1MAP1
01h
Port P1.2 mapping
P1MAP2
02h
Port P1.3 mapping
P1MAP3
03h
Port P1.4 mapping
P1MAP4
04h
Port P1.5 mapping
P1MAP5
05h
Port P1.6 mapping
P1MAP6
06h
Port P1.7 mapping
P1MAP7
07h
Table 6-24. Port Mapping Port P2 Registers (Base Address: 01D0h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
Port P2.0 mapping
P2MAP0
00h
Port P2.1 mapping
P2MAP1
01h
Port P2.2 mapping
P2MAP2
02h
Port P2.3 mapping
P2MAP3
03h
Port P2.4 mapping
P2MAP4
04h
Port P2.5 mapping
P2MAP5
05h
Port P2.6 mapping
P2MAP6
06h
Port P2.7 mapping
P2MAP7
07h
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Table 6-25. Port Mapping Port P3 Registers (Base Address: 01D8h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
Port P3.0 mapping
P3MAP0
00h
Port P3.1 mapping
P3MAP1
01h
Port P3.2 mapping
P3MAP2
02h
Port P3.3 mapping
P3MAP3
03h
Port P3.4 mapping
P3MAP4
04h
Port P3.5 mapping
P3MAP5
05h
Port P3.6 mapping
P3MAP6
06h
Port P3.7 mapping
P3MAP7
07h
Table 6-26. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
Port P1 input
P1IN
00h
Port P1 output
P1OUT
02h
Port P1 direction
P1DIR
04h
Port P1 pullup/pulldown enable
P1REN
06h
Port P1 drive strength
P1DS
08h
Port P1 selection
P1SEL
0Ah
Port P1 interrupt vector word
P1IV
0Eh
Port P1 interrupt edge select
P1IES
18h
Port P1 interrupt enable
P1IE
1Ah
Port P1 interrupt flag
P1IFG
1Ch
Port P2 input
P2IN
01h
Port P2 output
P2OUT
03h
Port P2 direction
P2DIR
05h
Port P2 pullup/pulldown enable
P2REN
07h
Port P2 drive strength
P2DS
09h
Port P2 selection
P2SEL
0Bh
Port P2 interrupt vector word
P2IV
1Eh
Port P2 interrupt edge select
P2IES
19h
Port P2 interrupt enable
P2IE
1Bh
Port P2 interrupt flag
P2IFG
1Dh
Table 6-27. Port P3, P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
Port P3 input
P3IN
00h
Port P3 output
P3OUT
02h
Port P3 direction
P3DIR
04h
Port P3 pullup/pulldown enable
P3REN
06h
Port P3 drive strength
P3DS
08h
Port P3 selection
P3SEL
0Ah
Port P4 input
P4IN
01h
Port P4 output
P4OUT
03h
Port P4 direction
P4DIR
05h
Port P4 pullup/pulldown enable
P4REN
07h
Port P4 drive strength
P4DS
09h
Port P4 selection
P4SEL
0Bh
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Table 6-28. Port P5 Registers (Base Address: 0240h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
Port P5 input
P5IN
00h
Port P5 output
P5OUT
02h
Port P5 direction
P5DIR
04h
Port P5 pullup/pulldown enable
P5REN
06h
Port P5 drive strength
P5DS
08h
Port P5 selection
P5SEL
0Ah
Table 6-29. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
Port PJ input
PJIN
00h
Port PJ output
PJOUT
02h
Port PJ direction
PJDIR
04h
Port PJ pullup/pulldown enable
PJREN
06h
Port PJ drive strength
PJDS
08h
Table 6-30. TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
TA0 control
TA0CTL
00h
Capture/compare control 0
TA0CCTL0
02h
Capture/compare control 1
TA0CCTL1
04h
Capture/compare control 2
TA0CCTL2
06h
Capture/compare control 3
TA0CCTL3
08h
Capture/compare control 4
TA0CCTL4
0Ah
TA0 counter
TA0R
10h
Capture/compare 0
TA0CCR0
12h
Capture/compare 1
TA0CCR1
14h
Capture/compare 2
TA0CCR2
16h
Capture/compare 3
TA0CCR3
18h
Capture/compare 4
TA0CCR4
1Ah
TA0 expansion 0
TA0EX0
20h
TA0 interrupt vector
TA0IV
2Eh
Table 6-31. TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
TA1 control
TA1CTL
00h
Capture/compare control 0
TA1CCTL0
02h
Capture/compare control 1
TA1CCTL1
04h
Capture/compare control 2
TA1CCTL2
06h
TA1 counter
TA1R
10h
Capture/compare 0
TA1CCR0
12h
Capture/compare 1
TA1CCR1
14h
Capture/compare 2
TA1CCR2
16h
TA1 expansion 0
TA1EX0
20h
TA1 interrupt vector
TA1IV
2Eh
80
Detailed Description
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Table 6-32. Real-Time Clock Registers (Base Address: 04A0h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
RTC control 0
RTCCTL0
00h
RTC control 1
RTCCTL1
01h
RTC control 2
RTCCTL2
02h
RTC control 3
RTCCTL3
03h
RTC prescaler 0 control
RTCPS0CTL
08h
RTC prescaler 1 control
RTCPS1CTL
0Ah
RTC prescaler 0
RTCPS0
0Ch
RTC prescaler 1
RTCPS1
0Dh
RTC interrupt vector word
RTCIV
0Eh
RTC seconds/counter 1
RTCSEC/RTCNT1
10h
RTC minutes/counter 2
RTCMIN/RTCNT2
11h
RTC hours/counter 3
RTCHOUR/RTCNT3
12h
RTC day of week/counter 4
RTCDOW/RTCNT4
13h
RTC days
RTCDAY
14h
RTC month
RTCMON
15h
RTC year low
RTCYEARL
16h
RTC year high
RTCYEARH
17h
RTC alarm minutes
RTCAMIN
18h
RTC alarm hours
RTCAHOUR
19h
RTC alarm day of week
RTCADOW
1Ah
RTC alarm days
RTCADAY
1Bh
Table 6-33. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
16-bit operand 1 – multiply
MPY
00h
16-bit operand 1 – signed multiply
MPYS
02h
16-bit operand 1 – multiply accumulate
MAC
04h
16-bit operand 1 – signed multiply accumulate
MACS
06h
16-bit operand 2
OP2
08h
16 × 16 result low word
RESLO
0Ah
16 × 16 result high word
RESHI
0Ch
16 × 16 sum extension
SUMEXT
0Eh
32-bit operand 1 – multiply low word
MPY32L
10h
32-bit operand 1 – multiply high word
MPY32H
12h
32-bit operand 1 – signed multiply low word
MPYS32L
14h
32-bit operand 1 – signed multiply high word
MPYS32H
16h
32-bit operand 1 – multiply accumulate low word
MAC32L
18h
32-bit operand 1 – multiply accumulate high word
MAC32H
1Ah
32-bit operand 1 – signed multiply accumulate low word
MACS32L
1Ch
32-bit operand 1 – signed multiply accumulate high word
MACS32H
1Eh
32-bit operand 2 – low word
OP2L
20h
32-bit operand 2 – high word
OP2H
22h
32 × 32 result 0 – least significant word
RES0
24h
32 × 32 result 1
RES1
26h
32 × 32 result 2
RES2
28h
32 × 32 result 3 – most significant word
RES3
2Ah
MPY32 control 0
MPY32CTL0
2Ch
Detailed Description
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Table 6-34. DMA Module Control Registers (Base Address: 0500h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
DMA module control 0
DMACTL0
00h
DMA module control 1
DMACTL1
02h
DMA module control 2
DMACTL2
04h
DMA module control 3
DMACTL3
06h
DMA module control 4
DMACTL4
08h
DMA interrupt vector
DMAIV
0Ah
Table 6-35. DMA Channel 0 Registers (Base Address: 0510h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
DMA channel 0 control
DMA0CTL
00h
DMA channel 0 source address low
DMA0SAL
02h
DMA channel 0 source address high
DMA0SAH
04h
DMA channel 0 destination address low
DMA0DAL
06h
DMA channel 0 destination address high
DMA0DAH
08h
DMA channel 0 transfer size
DMA0SZ
0Ah
Table 6-36. DMA Channel 1 Registers (Base Address: 0520h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
DMA channel 1 control
DMA1CTL
00h
DMA channel 1 source address low
DMA1SAL
02h
DMA channel 1 source address high
DMA1SAH
04h
DMA channel 1 destination address low
DMA1DAL
06h
DMA channel 1 destination address high
DMA1DAH
08h
DMA channel 1 transfer size
DMA1SZ
0Ah
Table 6-37. DMA Channel 2 Registers (Base Address: 0530h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
DMA channel 2 control
DMA2CTL
00h
DMA channel 2 source address low
DMA2SAL
02h
DMA channel 2 source address high
DMA2SAH
04h
DMA channel 2 destination address low
DMA2DAL
06h
DMA channel 2 destination address high
DMA2DAH
08h
DMA channel 2 transfer size
DMA2SZ
0Ah
82
Detailed Description
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Table 6-38. USCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
USCI control 1
UCA0CTL1
00h
USCI control 0
UCA0CTL0
01h
USCI baud rate 0
UCA0BR0
06h
USCI baud rate 1
UCA0BR1
07h
USCI modulation control
UCA0MCTL
08h
USCI status
UCA0STAT
0Ah
USCI receive buffer
UCA0RXBUF
0Ch
USCI transmit buffer
UCA0TXBUF
0Eh
USCI LIN control
UCA0ABCTL
10h
USCI IrDA transmit control
UCA0IRTCTL
12h
USCI IrDA receive control
UCA0IRRCTL
13h
USCI interrupt enable
UCA0IE
1Ch
USCI interrupt flags
UCA0IFG
1Dh
USCI interrupt vector word
UCA0IV
1Eh
Table 6-39. USCI_B0 Registers (Base Address: 05E0h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
USCI synchronous control 1
UCB0CTL1
00h
USCI synchronous control 0
UCB0CTL0
01h
USCI synchronous bit rate 0
UCB0BR0
06h
USCI synchronous bit rate 1
UCB0BR1
07h
USCI synchronous status
UCB0STAT
0Ah
USCI synchronous receive buffer
UCB0RXBUF
0Ch
USCI synchronous transmit buffer
UCB0TXBUF
0Eh
USCI I2C own address
UCB0I2COA
10h
USCI I2C slave address
UCB0I2CSA
12h
USCI interrupt enable
UCB0IE
1Ch
USCI interrupt flags
UCB0IFG
1Dh
USCI interrupt vector word
UCB0IV
1Eh
Detailed Description
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Table 6-40. ADC12_A Registers (Base Address: 0700h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
Control 0
ADC12CTL0
00h
Control 1
ADC12CTL1
02h
Control 2
ADC12CTL2
04h
Interrupt flag
ADC12IFG
0Ah
Interrupt enable
ADC12IE
0Ch
Interrupt vector word
ADC12IV
0Eh
ADC memory-control 0
ADC12MCTL0
10h
ADC memory-control 1
ADC12MCTL1
11h
ADC memory-control 2
ADC12MCTL2
12h
ADC memory-control 3
ADC12MCTL3
13h
ADC memory-control 4
ADC12MCTL4
14h
ADC memory-control 5
ADC12MCTL5
15h
ADC memory-control 6
ADC12MCTL6
16h
ADC memory-control 7
ADC12MCTL7
17h
ADC memory-control 8
ADC12MCTL8
18h
ADC memory-control 9
ADC12MCTL9
19h
ADC memory-control 10
ADC12MCTL10
1Ah
ADC memory-control 11
ADC12MCTL11
1Bh
ADC memory-control 12
ADC12MCTL12
1Ch
ADC memory-control 13
ADC12MCTL13
1Dh
ADC memory-control 14
ADC12MCTL14
1Eh
ADC memory-control 15
ADC12MCTL15
1Fh
Conversion memory 0
ADC12MEM0
20h
Conversion memory 1
ADC12MEM1
22h
Conversion memory 2
ADC12MEM2
24h
Conversion memory 3
ADC12MEM3
26h
Conversion memory 4
ADC12MEM4
28h
Conversion memory 5
ADC12MEM5
2Ah
Conversion memory 6
ADC12MEM6
2Ch
Conversion memory 7
ADC12MEM7
2Eh
Conversion memory 8
ADC12MEM8
30h
Conversion memory 9
ADC12MEM9
32h
Conversion memory 10
ADC12MEM10
34h
Conversion memory 11
ADC12MEM11
36h
Conversion memory 12
ADC12MEM12
38h
Conversion memory 13
ADC12MEM13
3Ah
Conversion memory 14
ADC12MEM14
3Ch
Conversion memory 15
ADC12MEM15
3Eh
84
Detailed Description
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Table 6-41. Comparator_B Registers (Base Address: 08C0h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
Comp_B control 0
CBCTL0
00h
Comp_B control 1
CBCTL1
02h
Comp_B control 2
CBCTL2
04h
Comp_B control 3
CBCTL3
06h
Comp_B interrupt
CBINT
0Ch
Comp_B interrupt vector word
CBIV
0Eh
Table 6-42. AES Accelerator Registers (Base Address: 09C0h)
REGISTER DESCRIPTION
AES accelerator control 0
ACRONYM
AESACTL0
Reserved
OFFSET
00h
02h
AES accelerator status
AESASTAT
04h
AES accelerator key
AESAKEY
06h
AES accelerator data in
AESADIN
008h
AES accelerator data out
AESADOUT
00Ah
Table 6-43. LCD_B Registers (Base Address: 0A00h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
LCD_B control 0
LCDBCTL0
000h
LCD_B control 1
LCDBCTL1
002h
LCD_B blinking control
LCDBBLKCTL
004h
LCD_B memory control
LCDBMEMCTL
006h
LCD_B voltage control
LCDBVCTL
008h
LCD_B port control 0
LCDBPCTL0
00Ah
LCD_B port control 1
LCDBPCTL1
00Ch
LCD_B charge pump control
LCDBCTL0
012h
LCD_B interrupt vector word
LCDBIV
01Eh
LCD_B memory 1
LCDM1
020h
LCD_B memory 2
LCDM2
021h
LCD_B memory 14
LCDM14
02Dh
LCD_B blinking memory 1
LCDBM1
040h
LCD_B blinking memory 2
LCDBM2
041h
LCDBM14
04Dh
...
...
LCD_B blinking memory 14
Detailed Description
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Table 6-44. Radio Interface Registers (Base Address: 0F00h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
Radio interface control 0
RF1AIFCTL0
00h
Radio interface control 1
RF1AIFCTL1
02h
Radio interface error flag
RF1AIFERR
06h
Radio interface error vector word
RF1AIFERRV
0Ch
Radio interface interrupt vector word
RF1AIFIV
0Eh
Radio instruction word
RF1AINSTRW
10h
Radio instruction word, 1-byte auto-read
RF1AINSTR1W
12h
Radio instruction word, 2-byte auto-read
RF1AINSTR2W
14h
Radio data in
RF1ADINW
16h
Radio status word
RF1ASTATW
20h
Radio status word, 1-byte auto-read
RF1ASTAT1W
22h
Radio status word, 2-byte auto-read
RF1AISTAT2W
24h
Radio data out
RF1ADOUTW
28h
Radio data out, 1-byte auto-read
RF1ADOUT1W
2Ah
Radio data out, 2-byte auto-read
RF1ADOUT2W
2Ch
Radio core signal input
RF1AIN
30h
Radio core interrupt flag
RF1AIFG
32h
Radio core interrupt edge select
RF1AIES
34h
Radio core interrupt enable
RF1AIE
36h
Radio core interrupt vector word
RF1AIV
38h
86
Detailed Description
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6.11 Input/Output Diagrams
6.11.1 Port P1 (P1.0 to P1.4) Input/Output With Schmitt Trigger
Figure 6-2 shows the port diagram. Table 6-45 summarizes the selection of the pin functions.
S18...S22
(not available on CC430F513x)
LCDS18...LCDS22
Pad Logic
P1REN.x
P1MAP.x = PMAP_ANALOG
P1DIR.x
0
from Port Mapping
1
P1OUT.x
0
from Port Mapping
1
DVSS
0
DVCC
1
Direction
0: Input
1: Output
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1IN.x
P1.0/P1MAP0(/S18)
P1.1/P1MAP1(/S19)
P1.2/P1MAP2(/S20)
P1.3/P1MAP3(/S21)
P1.4/P1MAP4(/S22)
Bus
Keeper
EN
to Port Mapping
1
D
P1IE.x
EN
P1IRQ.x
Q
P1IFG.x
P1SEL.x
P1IES.x
Set
Interrupt
Edge
Select
CC430F513x devices do not provide LCD functionality on port P1 pins.
Figure 6-2. Port P1 (P1.0 to P1.4) Diagram
Detailed Description
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Table 6-45. Port P1 (P1.0 to P1.4) Pin Functions
CONTROL BITS OR SIGNALS (1)
PIN NAME (P1.x)
x
FUNCTION
P1.0 (I/O)
P1.0/P1MAP/S18
0
Mapped secondary digital function – see Table 6-6
1
2
(1)
(2)
(3)
88
4
0
X
0
0; 1
(3)
1
≤ 30
(3)
0
0
S18 (not available on CC430F513x)
X
X
X
1
I: 0; O: 1
0
X
0
0; 1 (3)
1
≤ 30 (3)
0
Output driver and input Schmitt trigger disabled
X
1
= 31
0
S19 (not available on CC430F513x)
X
X
X
1
I: 0; O: 1
0
X
0
0; 1 (3)
1
≤ 30 (3)
0
X
1
= 31
0
Mapped secondary digital function – see Table 6-6
Mapped secondary digital function – see Table 6-6
Output driver and input Schmitt trigger disabled
Mapped secondary digital function – see Table 6-6
X
X
X
1
I: 0; O: 1
0
X
0
0; 1 (3)
1
≤ 30 (3)
0
Output driver and input Schmitt trigger disabled
X
1
= 31
0
S21 (not available on CC430F513x)
X
X
X
1
I: 0; O: 1
0
X
0
0; 1 (3)
1
≤ 30 (3)
0
P1.4 (I/O)
P1.4/P1MAP4/S22
I: 0; O: 1
= 31
P1.3 (I/O)
3
LCDS18 to
LCDS22 (2)
1
S22 (not available on CC430F513x)
P1.3/P1MAP3/S21
P1MAPx
X
P1.2 (I/O)
P1.2/P1MAP2/S20
P1SEL.x
Output driver and input Schmitt trigger disabled
P1.1 (I/O)
P1.1/P1MAP1/S19
P1DIR.x
Mapped secondary digital function – see Table 6-6
Output driver and input Schmitt trigger disabled
X
1
= 31
0
S22 (not available on CC430F513x)
X
X
X
1
X = don't care
LCDSx not available in CC430F513x.
According to mapped function – see Table 6-6.
Detailed Description
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6.11.2 Port P1 (P1.5 to P1.7) Input/Output With Schmitt Trigger
Figure 6-3 shows the port diagram. Table 6-46 summarizes the selection of the pin functions.
to LCD_B
(n/a CC430F513x)
Pad Logic
P1REN.x
P1MAP.x = PMAP_ANALOG
P1DIR.x
0
from Port Mapping
1
P1OUT.x
0
from Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1.5/P1MAP5(/R23)
P1.6/P1MAP6(/R13)
P1.7/P1MAP7(/R03)
P1IN.x
Bus
Keeper
EN
to Port Mapping
D
P1IE.x
EN
P1IRQ.x
Q
P1IFG.x
Set
P1SEL.x
Interrupt
Edge
Select
P1IES.x
CC430F513x devices do not provide LCD functionality on port P1 pins.
Figure 6-3. Port P1 (P1.5 to P1.7) Diagram
Detailed Description
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Table 6-46. Port P1 (P1.5 to P1.7) Pin Functions
PIN NAME (P1.x)
x
FUNCTION
P1.5 (I/O)
P1.5/P1MAP5/R23
5
Mapped secondary digital function – see Table 6-6
R23 (3) (not available on CC430F513x)
P1.6 (I/O)
P1.6/P1MAP6/R13/
LCDREF
6
Mapped secondary digital function – see Table 6-6
R13/LCDREF (3) (not available on CC430F513x)
P1.7 (I/O)
P1.7/P1MAP7/R03
7
Mapped secondary digital function – see Table 6-6
R03 (3) (not available on CC430F513x)
(1)
(2)
(3)
90
CONTROL BITS OR SIGNALS (1)
P1DIR.x
P1SEL.x
I: 0; O: 1
0
P1MAPx
X
0; 1 (2)
1
≤ 30 (2)
= 31
X
1
I: 0; O: 1
0
X
0; 1 (2)
1
≤ 30 (2)
= 31
X
1
I: 0; O: 1
0
X
0; 1 (2)
1
≤ 30 (2)
X
1
= 31
X = don't care
According to mapped function – see Table 6-6.
Setting P1SEL.x bit together with P1MAPx = PM_ANALOG disables the output driver and the input Schmitt trigger.
Detailed Description
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6.11.3 Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
Figure 6-4 through Figure 6-6 show the port diagrams. Table 6-47 summarizes the selection of the pin
functions.
Pad Logic
To ADC12
(n/a CC430F612x)
INCHx = x
To Comparator_B
from Comparator_B
CBPD.x
P2REN.x
P2MAP.x = PMAP_ANALOG
P2DIR.x
0
from Port Mapping
1
P2OUT.x
0
from Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2.0/P2MAP0/CB0(/A0)
P2.1/P2MAP2/CB1(/A1)
P2.2/P2MAP2/CB2(/A2)
P2.3/P2MAP3/CB3(/A3)
P2IN.x
Bus
Keeper
EN
to Port Mapping
D
P2IE.x
EN
P2IRQ.x
Q
P2IFG.x
Set
P2SEL.x
Interrupt
Edge
Select
P2IES.x
Figure 6-4. Port P2 (P2.0 to P2.3) Diagram
Detailed Description
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Pad Logic
To or from Reference
(not available on CC430F612x)
To ADC12
(not available on CC430F612x)
INCHx = x
To Comparator_B
from Comparator_B
CBPD.x
P2REN.x
P2MAP.x = PMAP_ANALOG
P2DIR.x
0
from Port Mapping
1
P2OUT.x
0
from Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2.4/P2MAP4/CB4(/A4/VREF-/VeREF-)
P2.5/P2MAP5/CB5(/A5/VREF+/VeRF+)
P2IN.x
Bus
Keeper
EN
to Port Mapping
D
P2IE.x
EN
P2IRQ.x
Q
P2IFG.x
P2SEL.x
P2IES.x
Set
Interrupt
Edge
Select
Figure 6-5. Port P2 (P2.4 and P2.5) Diagram
92
Detailed Description
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Pad Logic
To ADC12
(n/a CC430F513x)
INCHx = x
To Comparator_B
(n/a CC430F513x)
from Comparator_B
CBPD.x
(n/a CC430F513x)
P2REN.x
P2MAP.x = PMAP_ANALOG
P2DIR.x
0
from Port Mapping
1
P2OUT.x
0
from Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2.6/P2MAP6(/CB6/A6)
P2.7/P2MAP7(/CB7/A7)
P2IN.x
Bus
Keeper
EN
to Port Mapping
D
P2IE.x
EN
P2IRQ.x
Q
P2IFG.x
P2SEL.x
P2IES.x
Set
Interrupt
Edge
Select
CC430F513x devices do not provide analog functionality on port P2.6 and P2.7 pins.
Figure 6-6. Port P2 (P2.6 and P2.7) Diagram
Detailed Description
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Table 6-47. Port P2 (P2.0 to P2.7) Pin Functions
PIN NAME (P2.x)
x
CONTROL BITS OR SIGNALS (1)
FUNCTION
P2.0 (I/O)
P2.0/P2MAP0/CB0
(/A0)
0
Mapped secondary digital function – see Table 6-6
A0 (not available on CC430F612x)
(3)
CB0 (4)
P2.1 (I/O)
P2.1/P2MAP1/CB1
(/A1)
1
Mapped secondary digital function – see Table 6-6
2
3
(1)
(2)
(3)
(4)
94
= 31
X
X
X
1
I: 0; O: 1
0
X
(2)
1
≤ 30
0
(2)
0
X
1
I: 0; O: 1
0
X
0
0; 1 (2)
1
≤ 30 (2)
0
A2 (not available on CC430F612x) (3)
X
1
= 31
X
CB2 (4)
X
X
X
1
I: 0; O: 1
0
X
0
0; 1 (2)
1
≤ 30 (2)
0
X
1
= 31
X
Mapped secondary digital function – see Table 6-6
Mapped secondary digital function – see Table 6-6
A3 (not available on CC430F612x) (3)
Mapped secondary digital function – see Table 6-6
A4/VREF-/VeREF- (not available on CC430F612x)
(3)
Mapped secondary digital function – see Table 6-6
A5/VREF+/VeREF+ (not available on CC430F612x)
(3)
Mapped secondary digital function – see Table 6-6
X
X
X
1
I: 0; O: 1
0
X
0
0; 1 (2)
1
≤ 30 (2)
0
X
1
= 31
X
X
X
X
1
I: 0; O: 1
0
X
0
0; 1 (2)
1
≤ 30 (2)
0
X
1
= 31
X
X
X
X
1
I: 0; O: 1
0
X
0; 1
(2)
1
≤ 30
0
(2)
0
A6 (not available on CC430F612x and
CC430F513x) (3)
X
1
= 31
X
CB6 (not available on CC430F513x) (4)
X
X
X
1
I: 0; O: 1
0
X
0
0; 1 (2)
1
≤ 30 (2)
0
A7 (not available on CC430F612x and
CC430F513x) (3)
X
1
= 31
X
CB7 (not available on CC430F513x) (4)
X
X
X
1
Mapped secondary digital function – see Table 6-6
7
1
X
X
P2.7 (I/O)
P2.7/P2MAP7(/CB7)
(/A7)
X
X
P2.6 (I/O)
6
0
CB1 (4)
CB5 (4)
P2.6/P2MAP6(/CB6)
(/A6)
≤ 30 (2)
X
P2.5 (I/O)
5
1
= 31
CB4 (4)
P2.5/P2MAP5/CB5
(/A5/VREF+/VeREF+)
0
0; 1 (2)
1
P2.4 (I/O)
4
CBPD.x
X
X
CB3 (4)
P2.4/P2MAP4/CB4
(/A4/VREF-/VeREF-)
P2MAPx
0
0; 1
P2.3 (I/O)
P2.3/P2MAP3/CB3
(/A3)
P2SEL.x
A1 (not available on CC430F612x) (3)
P2.2 (I/O)
P2.2/P2MAP2/CB2
(/A2)
P2DIR.x
I: 0; O: 1
X = don't care
According to mapped function – see Table 6-6.
Setting P2SEL.x bit together with P2MAPx = PM_ANALOG disables the output driver and the input Schmitt trigger.
Setting the CBPD.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals. Selecting the CBx input pin to the comparator multiplexer with the CBx bits automatically disables output driver and input buffer
for that pin, regardless of the state of the associated CBPD.x bit.
Detailed Description
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SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
6.11.4 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
Figure 6-7 shows the port diagram. Table 6-48 summarizes the selection of the pin functions.
S10...S17
(n/a CC430F513x)
LCDS10...LCDS17
Pad Logic
P3REN.x
P3MAP.x = PMAP_ANALOG
P3DIR.x
0
from Port Mapping
1
P3OUT.x
0
from Port Mapping
1
DVSS
0
DVCC
1
Direction
0: Input
1: Output
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3IN.x
Bus
Keeper
EN
to Port Mapping
1
P3.0/P3MAP0(/S10)
P3.1/P3MAP1(/S11)
P3.2/P3MAP2(/S12)
P3.3/P3MAP3(/S13)
P3.4/P3MAP4(/S14)
P3.5/P3MAP5(/S15)
P3.6/P3MAP6(/S16)
P3.7/P3MAP7(/S17)
D
CC430F513x devices do not provide LCD functionality on port P3 pins.
Figure 6-7. Port P3 (P3.0 to P3.7) Diagram
Detailed Description
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Table 6-48. Port P3 (P3.0 to P3.7) Pin Functions
CONTROL BITS OR SIGNALS (1)
PIN NAME (P3.x)
x
FUNCTION
P3.0 (I/O)
P3.0/P3MAP0/S10
0
Mapped secondary digital function – see Table 6-6
1
2
4
5
6
(1)
(2)
(3)
96
7
0; 1
1
≤ 30
0
0
X
1
I: 0; O: 1
0
X
0
0; 1 (3)
1
≤ 30 (3)
0
Output driver and input Schmitt trigger disabled
X
1
= 31
0
S11 (not available on CC430F513x)
X
X
X
1
I: 0; O: 1
0
X
0
0; 1 (3)
1
≤ 30 (3)
0
X
1
= 31
0
Mapped secondary digital function – see Table 6-6
Mapped secondary digital function – see Table 6-6
Output driver and input Schmitt trigger disabled
Mapped secondary digital function – see Table 6-6
X
X
X
1
I: 0; O: 1
0
X
0
0; 1 (3)
1
≤ 30 (3)
0
Output driver and input Schmitt trigger disabled
X
1
= 31
0
S13 (not available on CC430F513x)
X
X
X
1
I: 0; O: 1
0
X
0
0; 1 (3)
1
≤ 30 (3)
0
Mapped secondary digital function – see Table 6-6
Output driver and input Schmitt trigger disabled
X
1
= 31
0
S14 (not available on CC430F513x)
X
X
X
1
I: 0; O: 1
0
X
Mapped secondary digital function – see Table 6-6
0; 1
(3)
1
≤ 30
0
(3)
0
Output driver and input Schmitt trigger disabled
X
1
= 31
0
S15 (not available on CC430F513x)
X
X
X
1
I: 0; O: 1
0
X
0
0; 1 (3)
1
≤ 30 (3)
0
Output driver and input Schmitt trigger disabled
X
1
= 31
0
S16 (not available on CC430F513x)
X
X
X
1
I: 0; O: 1
0
X
0
0; 1 (3)
1
≤ 30 (3)
0
Output driver and input Schmitt trigger disabled
X
1
= 31
0
S17 (not available on CC430F513x)
X
X
X
1
Mapped secondary digital function – see Table 6-6
P3.7 (I/O)
P3.7/P3MAP7/S17
0
(3)
X
P3.6 (I/O)
P3.6/P3MAP6/S16
X
X
P3.5 (I/O)
P3.5/P3MAP5/S15
0
(3)
S10 (not available on CC430F513x)
P3.4 (I/O)
P3.4/P3MAP4/S14
I: 0; O: 1
= 31
P3.3 (I/O)
3
LCDS10 to
LCDS17 (2)
1
S12 (not available on CC430F513x)
P3.3/P3MAP3/S13
P3MAPx
X
P3.2 (I/O)
P3.2/P3MAP7/S12
P3SEL.x
Output driver and input Schmitt trigger disabled
P3.1 (I/O)
P3.1/P3MAP1/S11
P3DIR.x
Mapped secondary digital function – see Table 6-6
X = don't care
LCDSx not available in CC430F513x.
According to mapped function – see Table 6-6.
Detailed Description
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SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
6.11.5 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger (CC430F613x and
CC430F612x Only)
Figure 6-8 shows the port diagram. Table 6-49 summarizes the selection of the pin functions.
S2...S9
LCDS2...LCDS9
Pad Logic
P4REN.x
P4DIR.x
0
0
DVSS
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P4OUT.x
DVSS
P4.0/S2
P4.1/S3
P4.2/S4
P4.3/S5
P4.4/S6
P4.5/S7
P4.6/S8
P4.7/S9
P4DS.x
0: Low drive
1: High drive
P4SEL.x
P4IN.x
EN
Not Used
Bus
Keeper
D
Figure 6-8. Port P4 (P4.0 to P4.7) Diagram (CC430F613x and CC430F612x Only)
Detailed Description
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Table 6-49. Port P4 (P4.0 to P4.7) Pin Functions (CC430F613x and CC430F612x Only)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P4.x)
x
FUNCTION
P4DIR.x
P4SEL.x
LCDS2 to
LCDS9
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S2
X
X
1
P4.0 (I/O)
P4.0/P4MAP0/S2
0
P4.1 (I/O)
P4.1/P4MAP1/S3
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S3
X
X
1
P4.2 (I/O)
P4.2/P4MAP7/S4
2
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S4
P4.3 (I/O)
P4.3/P4MAP3/S5
3
N/A
4
5
6
(1)
98
7
1
0
1
1
0
X
1
I: 0; O: 1
0
0
0
1
0
N/A
DVSS
1
1
0
S6
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S7
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S8
X
X
1
P4.7 (I/O)
P4.7/P4MAP7/S9
0
0
X
P4.6 (I/O)
P4.6/P4MAP6/S8
1
0
S5
P4.5 (I/O)
P4.5/P4MAP5/S7
X
DVSS
P4.4 (I/O)
P4.4/P4MAP4/S6
X
I: 0; O: 1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S9
X
X
1
X = don't care
Detailed Description
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SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
6.11.6 Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
Figure 6-9 and Figure 6-10 show the port diagrams. Table 6-50 summarizes the selection of the pin
functions.
Pad Logic
to XT1
P5REN.0
P5DIR.0
DVSS
0
DVCC
1
1
0
1
P5OUT.0
0
Module X OUT
1
P5DS.x
0: Low drive
1: High drive
P5SEL.0
P5.0/XIN
P5IN.0
Bus
Keeper
EN
Module X IN
D
Figure 6-9. Port P5 (P5.0) Diagram
Detailed Description
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Pad Logic
to XT1
P5REN.1
P5DIR.1
DVSS
0
DVCC
1
1
0
1
P5OUT.1
0
Module X OUT
1
P5.1/XOUT
P5DS.x
0: Low drive
1: High drive
P5SEL.0
XT1BYPASS
P5IN.1
Bus
Keeper
EN
Module X IN
D
Figure 6-10. Port P5 (P5.1) Diagram
Table 6-50. Port P5 (P5.0 and P5.1) Pin Functions
PIN NAME (P5.x)
x
FUNCTION
P5DIR.x
P5SEL.0
P5SEL.1
XT1BYPASS
I: 0; O: 1
0
X
X
X
1
X
0
X
1
X
1
I: 0; O: 1
0
X
X
XOUT crystal mode (3)
X
1
X
0
P5.1 (I/O) (3)
X
1
X
1
P5.0 (I/O)
P5.0/XIN
0
XIN crystal mode
(2)
XIN bypass mode (2)
P5.1 (I/O)
P5.1/XOUT
(1)
(2)
(3)
100
1
CONTROL BITS OR SIGNALS (1)
X = don't care
Setting P5SEL.0 causes the general-purpose I/O to be disabled. Pending the setting of XT1BYPASS, P5.0 is configured for crystal
mode or bypass mode.
Setting P5SEL.0 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.1 can be used as
general-purpose I/O.
Detailed Description
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SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
6.11.7 Port P5 (P5.2 to P5.4) Input/Output With Schmitt Trigger (CC430F613x and
CC430F612x Only)
Figure 6-11 shows the port diagram. Table 6-51 and Table 6-52 summarize the selection of the pin
functions.
S0(P5.2)/S1(P5.3)/S23(P5.4)
LCDS0(P5.2)/LCDS1(P5.3)/LCDS23(P5.4)
Pad Logic
P5REN.x
P5DIR.x
DVSS
0
DVCC
1
1
0
1
P5OUT.x
0
DVSS
1
P5.2/S0
P5.3/S1
P5.4/S23
P5DS.x
0: Low drive
1: High drive
P5SEL.x
P5IN.x
Bus
Keeper
EN
Not Used
D
Figure 6-11. Port P5 (P5.2 to P5.4) Diagram (CC430F613x and CC430F612x Only)
Detailed Description
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Table 6-51. Port P5 (P5.2 to P5.3) Pin Functions (CC430F613x and CC430F612x Only)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P5.x)
x
FUNCTION
P5DIR.x
P5SEL.x
LCDS0 to
LCDS1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S0
X
X
1
P5.2 (I/O)
P5.2/S0
2
P5.3 (I/O)
P5.3/S1
(1)
3
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S1
X
X
1
X = don't care
Table 6-52. Port P5 (P5.4) Pin Functions (CC430F613x and CC430F612x Only)
PIN NAME (P5.x)
x
FUNCTION
P5.4 (I/O)
P5.4/S23
(1)
102
4
CONTROL BITS OR SIGNALS (1)
P5DIR.x
P5SEL.x
LCDS23
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S23
X
X
1
X = don't care
Detailed Description
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SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
6.11.8 Port P5 (P5.5 to P5.7) Input/Output With Schmitt Trigger (CC430F613x and
CC430F612x Only)
Figure 6-12 shows the port diagram. Table 6-53 summarizes the selection of the pin functions.
S24(P5.5)/S25(P5.6)/S26(P5.7)
LCDS24(P5.5)/LCDS25(P5.6)/LCDS26(P5.7)
COM3(P5.5)/COM2(P5.6)/COM1(P5.7)
Pad Logic
P5REN.x
DVSS
0
DVCC
1
1
P5DIR.x
P5OUT.x
P5.5/COM3/S24
P5.6/COM2/S25
P5.7/COM1/S26
P5DS.x
0: Low drive
1: High drive
P5SEL.x
P5IN.x
Bus
Keeper
Figure 6-12. Port P5 (P5.5 to P5.7) Diagram (CC430F613x and CC430F612x Only)
Table 6-53. Port P5 (P5.5 to P5.7) Pin Functions (CC430F613x and CC430F612x Only)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P5.x)
x
FUNCTION
P5DIR.x
P5SEL.x
LCDS24 to
LCDS26
I: 0; O: 1
0
0
X
1
X
X
0
1
I: 0; O: 1
0
0
X
1
X
X
0
1
P5.7 (I/O)
I: 0; O: 1
0
0
COM1 (2)
X
1
X
S26 (2)
X
0
1
P5.5 (I/O)
P5.5/COM3/S24
5
COM3
(2)
S24 (2)
P5.6 (I/O)
P5.6/COM2/S25
6
COM2
(2)
S25 (2)
P5.7/COM1/S26
(1)
(2)
7
X = don't care
Setting P5SEL.x bit disables the output driver and the input Schmitt trigger.
Detailed Description
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6.11.9 Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
Figure 6-13 shows the port diagram. Table 6-54 summarizes the selection of the pin functions.
Pad Logic
PJREN.0
PJDIR.0
0
DVCC
1
PJOUT.0
0
From JTAG
1
DVSS
0
DVCC
1
PJDS.0
0: Low drive
1: High drive
From JTAG
1
PJ.0/TDO
PJIN.0
Figure 6-13. Port PJ (PJ.0) Diagram
104
Detailed Description
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SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
6.11.10 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt
Trigger or Output
Figure 6-14 shows the port diagram. Table 6-54 summarizes the selection of the pin functions.
Pad Logic
PJREN.x
PJDIR.x
0
DVSS
1
PJOUT.x
0
From JTAG
1
DVSS
0
DVCC
1
1
PJDS.x
0: Low drive
1: High drive
From JTAG
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
PJIN.x
EN
D
To JTAG
Figure 6-14. Port PJ (PJ.1 to PJ.3) Diagram
Table 6-54. Port PJ (PJ.0 to PJ.3) Pin Functions
PIN NAME (PJ.x)
x
FUNCTION
CONTROL BITS OR
SIGNALS (1)
PJDIR.x
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
(1)
(2)
(3)
(4)
0
1
2
3
PJ.0 (I/O) (2)
I: 0; O: 1
TDO (3)
X
PJ.1 (I/O)
(2)
TDI/TCLK (3)
I: 0; O: 1
(4)
X
PJ.2 (I/O) (2)
TMS (3)
I: 0; O: 1
(4)
X
PJ.3 (I/O) (2)
TCK (3)
I: 0; O: 1
(4)
X
X = don't care
Default condition
The pin direction is controlled by the JTAG module.
In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care.
Detailed Description
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6.12 Device Descriptor
Table 6-55 lists the content of the device descriptor tag-length-value (TLV) structure for CC430F613x and
CC430F513x device types.
Table 6-56 lists the content of the device descriptor tag-length-value (TLV) structure for CC430F612x
device types.
Table 6-55. Device Descriptor Table (CC430F613x and CC430F513x)
Info Block
Die Record
ADC12
Calibration
REF
Calibration
Peripheral
Descriptor
(PD)
106
VALUE
ADDRESS
SIZE
(bytes)
F6137
F6135
F5137
F5135
F5133
Info length
01A00h
1
06h
06h
06h
06h
06h
CRC length
01A01h
1
06h
06h
06h
06h
06h
CRC value
01A02h
2
Per unit
Per unit
Per unit
Per unit
Per unit
Device ID
01A04h
1
61h
61h
51h
51h
51h
Device ID
01A05h
1
37h
35h
37h
35h
33h
Hardware revision
01A06h
1
Per unit
Per unit
Per unit
Per unit
Per unit
Firmware revision
01A07h
1
Per unit
Per unit
Per unit
Per unit
Per unit
Die record tag
01A08h
1
08h
08h
08h
08h
08h
Die record length
01A09h
1
0Ah
0Ah
0Ah
0Ah
0Ah
DESCRIPTION
Lot/wafer ID
01A0Ah
4
Per unit
Per unit
Per unit
Per unit
Per unit
Die X position
01A0Eh
2
Per unit
Per unit
Per unit
Per unit
Per unit
Die Y position
01A10h
2
Per unit
Per unit
Per unit
Per unit
Per unit
Test results
01A12h
2
Per unit
Per unit
Per unit
Per unit
Per unit
11h
ADC12 calibration tag
01A14h
1
11h
11h
11h
11h
ADC12 calibration length
01A15h
1
10h
10h
10h
10h
10h
ADC gain factor
01A16h
2
Per unit
Per unit
Per unit
Per unit
Per unit
ADC offset
01A18h
2
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 1.5-V reference
Temperature sensor 30°C
01A1Ah
2
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 1.5-V reference
Temperature sensor 85°C
01A1Ch
2
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 2.0-V reference
Temperature sensor 30°C
01A1Eh
2
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 2.0-V reference
Temperature sensor 85°C
01A20h
2
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 2.5-V reference
Temperature sensor 30°C
01A22h
2
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 2.5-V reference
Temperature sensor 85°C
01A24h
2
Per unit
Per unit
Per unit
Per unit
Per unit
REF calibration tag
01A26h
1
12h
12h
12h
12h
12h
REF calibration length
01A27h
1
06h
06h
06h
06h
06h
1.5-V reference factor
01A28h
2
Per unit
Per unit
Per unit
Per unit
Per unit
2.0-V reference factor
01A2Ah
2
Per unit
Per unit
Per unit
Per unit
Per unit
2.5-V reference factor
01A2Ch
2
Per unit
Per unit
Per unit
Per unit
Per unit
Peripheral descriptor tag
01A2Eh
1
02h
02h
02h
02h
02h
Peripheral descriptor length
01A2Fh
1
57h
57h
55h
55h
55h
Peripheral descriptors
01A30h
PD Length
...
...
...
...
...
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Table 6-56. Device Descriptor Table (CC430F612x)
Info Block
Die Record
Empty Descriptor
REF Calibration
Peripheral Descriptor
(PD)
VALUE
ADDRESS
SIZE
(bytes)
F6127
F6126
F6125
Info length
01A00h
1
06h
06h
06h
CRC length
01A01h
1
06h
06h
06h
CRC value
01A02h
2
Per unit
Per unit
Per unit
Device ID
01A04h
1
61h
61h
61h
Device ID
01A05h
1
27h
26h
25h
Hardware revision
01A06h
1
Per unit
Per unit
Per unit
Firmware revision
01A07h
1
Per unit
Per unit
Per unit
Die record tag
01A08h
1
08h
08h
08h
Die record length
01A09h
1
0Ah
0Ah
0Ah
Lot/wafer ID
01A0Ah
4
Per unit
Per unit
Per unit
Die X position
01A0Eh
2
Per unit
Per unit
Per unit
Die Y position
01A10h
2
Per unit
Per unit
Per unit
Test results
01A12h
2
Per unit
Per unit
Per unit
Empty tag
01A14h
1
05h
05h
05h
Empty tag length
01A15h
1
10h
10h
10h
DESCRIPTION
01A16h
16
undefined
undefined
undefined
REF calibration l
01A26h
1
12h
12h
12h
REF calibration length
01A27h
1
06h
06h
06h
1.5-V reference factor
01A28h
2
Per unit
Per unit
Per unit
2.0-V reference factor
01A2Ah
2
Per unit
Per unit
Per unit
2.5-V reference factor
01A2Ch
2
Per unit
Per unit
Per unit
Peripheral descriptor tag
01A2Eh
1
02h
02h
02h
Peripheral descriptor length
01A2Fh
1
55h
55h
55h
Peripheral descriptors
01A30h
PD Length
...
...
...
Detailed Description
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7 Applications, Implementation, and Layout
NOTE
Information in the following Applications section is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI's customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
7.1
Application Circuits
Figure 7-1 shows a typical application circuit for the CC430F61xx. Table 7-1 lists the bill of materials.
108
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L1
C6
C7
C3
C8
C9
VDD
34
15
C10
C11
10
DVCC
C19
VDD
VCORE
9
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
35
RF_XIN
36
13
14
37
12
RF_XOUT
AVCC_RF
AVCC_RF
38
39
11
RF_P
40
41
8
CC430F61xx
42
7
AVCC_RF
43
6
RF_N
44
5
AVCC_RF
45
4
R_BIAS
46
3
GUARD
AVDD
TDO
TMS
TDI/TCLK
47
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
AVCC
C12
AVSS
C13
2
C20
DVCC
C14
nRST/NMI/SBWTDIO
C15
R2
TEST/SBWTCK
VDD
C21
R1
26MHz
C22
C4
C1
C5
C2
(May be added close to the respective pins
to reduce emissions at 5GHz to levels
required by ETSI.)
C16
C18
(JTAG / SBW signals)
TCK
AVDD
DVCC
C17
L2
L4
C23
C25
C24
L3
C26
C27
L5
L6
C28
L7
C29
SMA STRAIGHT JACK, SMT
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Copyright © 2017, Texas Instruments Incorporated
For a complete reference design including layout, see the CC430 wireless development tools and the MSP430
Hardware Tools User's Guide.
Figure 7-1. Typical Application Circuit CC430F61xx
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L1
C7
C6
C5
C2
C1
C8
C9
VDD
RF_XIN
C10
C11
C19
VDD
25
12
13 14 15 16 17 18 19 20 21 22 23 24
RF_XOUT
26
11
AVCC_RF
AVCC_RF
27
28
RF_P
9
10
30
29
8
7
AVCC
VCORE
DVCC
CC430F51xx
31
RF_N
AVCC_RF
32
5
6
AVCC_RF
R_BIAS
34
33
3
4
GUARD
35
2
AVSS
C12
C21
26MHz
C22
C4
R1
TDI/TCLK
DVCC
C14
nRST/NMI/SBWTDIO
C15
48 47 46 45 44 43 42 41 40 39 38 37
36
R2
TEST/SBWTCK
C13
1
C20
TCK
VDD
TDO
AVDD
C16
(May be added close to the respective pins
to reduce emissions at 5GHz to levels
required by ETSI.)
C18
(JTAG / SBW signals)
TMS
AVDD
DVCC
C17
C3
L2
L4
C23
C25
C24
L3
C26
C27
L5
L6
C28
L7
C29
SMA STRAIGHT JACK, SMT
Figure 7-2 shows a typical application circuit for the CC430F51xx. Table 7-1 lists the bill of materials.
Copyright © 2017, Texas Instruments Incorporated
For a complete reference design including layout, see the CC430 wireless development tools and the MSP430
Hardware Tools User's Guide.
Figure 7-2. Typical Application Circuit CC430F51xx
110
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Table 7-1. Bill of Materials
Components
For 315 MHz
For 433 MHz
For 868 or 915 MHz
Comment
C1, C3, C4, C5, C7,
C9, C11, C13, C15
100 nF
Decoupling capacitors
C8, C10, C12, C14
10 µF
Decoupling capacitors
C2, C6, C16, C17,
C18
2 pF
Decoupling capacitors
C19
470 nF
VCORE capacitor
C20
2.2 nF
RST decoupling cap (optimized for SBW)
C21, C22
27 pF
Load capacitors for 26 MHz crystal (1)
R1
56 kΩ
R_BIAS (±1% required)
R2
47 kΩ
RST pullup
L1, L2
Capacitors: 220 pF
0.016 µH
0.012 µH
L3, L4
0.033 µH
0.027 µH
0.018 µH
L5
0.033 µH
0.047 µH
0.015 µH
L6
(1)
(2)
dnp
(2)
dnp
(2)
0.0022 µH
L7
0.033 µH
0.051 µH
0.015 µH
C23
dnp (2)
2.7 pF
1 pF
C24
220 pF
220 pF
100 pF
C25
6.8 pF
3.9 pF
1.5 pF
C26
6.8 pF
3.9 pF
1.5 pF
C27
220 pF
220 pF
1.5 pF
C28
10 pF
4.7 pF
8.2 pF
C29
220 pF
220 pF
1.5 pF
The load capacitance CL seen by the crystal is CL = 1 / ((1 / C21) + (1 / C22)) + Cparasitic. The parasitic capacitance Cparasitic includes pin
capacitance and PCB stray capacitance. It can typically be estimated to be approximately 2.5 pF.
dnp = do not populate
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8 Device and Documentation Support
8.1
Getting Started and Next Steps
For an introduction to the MSP430™ family of devices and the tools and libraries that are available to help
with your development, visit the Getting Started page.
8.2
Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS.
These prefixes represent evolutionary stages of product development from engineering prototypes (XMS)
through fully qualified production devices (MSP).
XMS – Experimental device that is not necessarily representative of the final device's electrical
specifications
MSP – Fully qualified production device
XMS devices are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices have been characterized fully, and the quality and reliability of the device have been
demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production
devices. TI recommends that these devices not be used in any production system because their expected
end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
temperature range, package type, and distribution format. Figure 8-1 provides a legend for reading the
complete device name.
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MSP 430 F 5 438 A I ZQW T -EP
Processor Family
Optional: Additional Features
MCU Platform
Optional: Tape and Reel
Device Type
Packaging
Series
Feature Set
Processor Family
Optional: Temperature Range
Optional: A = Revision
CC = Embedded RF Radio
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
430 = MSP430 low-power microcontroller platform
MCU Platform
Device Type
Memory Type
C = ROM
F = Flash
FR = FRAM
G = Flash or FRAM (Value Line)
L = No Nonvolatile Memory
Specialized Application
AFE = Analog Front End
BQ = Contactless Power
CG = ROM Medical
FE = Flash Energy Meter
FG = Flash Medical
FW = Flash Electronic Flow Meter
Series
1 = Up to 8 MHz
2 = Up to 16 MHz
3 = Legacy
4 = Up to 16 MHz with LCD
5 = Up to 25 MHz
6 = Up to 25 MHz with LCD
0 = Low-Voltage Series
Feature Set
Various levels of integration within a series
Optional: A = Revision
N/A
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging
http://www.ti.com/packaging
Optional: Tape and Reel
T = Small reel
R = Large reel
No markings = Tube or tray
Optional: Additional Features -EP = Enhanced Product (–40°C to 105°C)
-HT = Extreme Temperature Parts (–55°C to 150°C)
-Q1 = Automotive Q100 Qualified
Figure 8-1. Device Nomenclature
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8.3
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Tools and Software
The CC430 microcontrollers are supported by a wide variety of software and hardware development tools.
Tools are available from TI and various third parties.
Design Kits and Evaluation Modules
CC430 Sub-GHz RF Experimenter's Board The MSP-EXPCC430RFx Experimenter Kit is a complete
sub-GHz development platform for the CC430 devices from the MSP430 family of ultra-lowpower microcontrollers. The kit provides two sub-GHz wireless modules: the MSPEXP430F6137Rx Base Board with the CC430F6137, and the MSP-EXP430F5137Rx
Satellite Board with the CC430F5137.
Chronos: Wireless Development Tool in a Watch The eZ430-Chronos is a highly integrated, wearable
wireless development system based for the CC430 in a sports watch. It may be used as a
reference platform for watch systems, a personal display for personal area networks, or as a
wireless sensor node for remote data collection.
Sub-1 GHz RF Spectrum Analyzer Tool The MSP-SA430-SUB1GHZ Spectrum Analyzer is CC430based reference design that can be used to implement an easy and affordable tool to
jumpstart RF development in the sub-GHz frequency range. More and more electronic
devices include a built-in RF link. RF transceivers are inexpensive - but the equipment to
design and debug such systems is not. The CC430-based spectrum analyzer provides an
affordable development tool that reduces the time needed on expensive measurement
equipment.
Software
MSP430Ware™ Software MSP430Ware software is a collection of code examples, data sheets, and
other design resources for all MSP430 devices delivered in a convenient package. In
addition to providing a complete collection of existing MSP430 design resources,
MSP430Ware software also includes a high-level API called MSP Driver Library. This library
makes it easy to program MSP430 hardware. MSP430Ware software is available as a
component of CCS or as a stand-alone package.
CC430F613x Code Examples C Code examples that configure each of the integrated peripherals for
various application needs.
ULP (Ultra-Low Power) Advisor ULP (Ultra-Low Power) Advisor is a tool for guiding developers to write
more efficient code to fully utilize the unique ultra-low power features of MSP430 and
MSP432 microcontrollers. Aimed at both experienced and new microcontroller developers,
ULP Advisor checks your code against a thorough ULP checklist to squeeze every last nano
amp out of your application.
Development Tools
Code Composer Studio™ Integrated Development Environment for MSP Microcontrollers
Code
Composer Studio is an integrated development environment (IDE) that supports all MSP
microcontroller devices. Code Composer Studio comprises a suite of embedded software
utilities used to develop and debug embedded applications. It includes an optimizing C/C++
compiler, source code editor, project build environment, debugger, profiler, and many other
features.
GCC - Open Source Compiler for MSP430 Microcontrollers TI has partnered with Red Hat to bring
you a new and fully supported open source compiler as the successor to the community
driven MSPGCC. This free GCC 4.9 compiler supports all MSP430 devices and has no code
size limit. In addition, this compiler can be used stand-alone or selected within Code
Composer Studio v6.0 or later.
MSP MCU Programmer and Debugger The MSP-FET is a powerful emulation development tool – often
called a debug probe – which allows users to quickly begin application development on MSP
low-power microcontrollers (MCU).
MSP-GANG Production Programmer The MSP Gang Programmer is a device programmer that can
program up to eight identical devices at the same time. The MSP Gang Programmer
connects to a host PC using a standard RS-232 or USB connection and provides flexible
programming options that allow the user to fully customize the process.
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8.4
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Documentation Support
The following documents describe the CC430F613x, CC430F612x, and CC430F513x devices. Copies of
these documents are available on the Internet at www.ti.com.
Receiving Nofication of Document Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for
your device on ti.com (for links to the product folder, see Section 8.5). In the upper right corner, click the
"Alert me" button. This registers you to receive a weekly digest of product information that has changed (if
any). For change details, check the revision history of any revised document.
Errata
CC430F6137 Device Erratasheet Describes the known exceptions to the functional specifications.
CC430F6135 Device Erratasheet Describes the known exceptions to the functional specifications.
CC430F6127 Device Erratasheet Describes the known exceptions to the functional specifications.
CC430F6126 Device Erratasheet Describes the known exceptions to the functional specifications.
CC430F6125 Device Erratasheet Describes the known exceptions to the functional specifications.
CC430F5137 Device Erratasheet Describes the known exceptions to the functional specifications.
CC430F5135 Device Erratasheet Describes the known exceptions to the functional specifications.
CC430F5133 Device Erratasheet Describes the known exceptions to the functional specifications.
User's Guides
CC430 Family User's Guide
device family.
Detailed information on the modules and peripherals available in this
Code Composer Studio for MSP430 User's Guide This user's guide describes how to use the TI Code
Composer Studio IDE with the MSP430 ultra-low-power microcontrollers.
MSP430™ Flash Device Bootloader (BSL) User's Guide The MSP430 bootloader (BSL, formerly
known as the bootstrap loader) allows users to communicate with embedded memory in the
MSP430 microcontroller during the prototyping phase, final production, and in service. Both
the programmable memory (flash memory) and the data memory (RAM) can be modified as
required. Do not confuse the bootloader with the bootstrap loader programs found in some
digital signal processors (DSPs) that automatically load program code (and data) from
external memory to the internal memory of the DSP.
MSP430 Programming With the JTAG Interface This document describes the functions that are
required to erase, program, and verify the memory module of the MSP430 flash-based and
FRAM-based microcontroller families using the JTAG communication port. In addition, it
describes how to program the JTAG access security fuse that is available on all MSP430
devices. This document describes device access using both the standard 4-wire JTAG
interface and the 2-wire JTAG interface, which is also referred to as Spy-Bi-Wire (SBW).
MSP430 Hardware Tools User's Guide This manual describes the hardware of the TI MSP-FET430
Flash Emulation Tool (FET). The FET is the program development tool for the MSP430 ultralow-power microcontroller. Both available interface types, the parallel port interface and the
USB interface, are described.
Application Reports
MSP430 32-kHz Crystal Oscillators Selection of the right crystal, correct load circuit, and proper board
layout are important for a stable crystal oscillator. This application report summarizes crystal
oscillator function and explains the parameters to select the correct crystal for MSP430 ultralow-power operation. In addition, hints and examples for correct board layout are given. The
document also contains detailed information on the possible oscillator tests to ensure stable
oscillator operation in mass production.
MSP430 System-Level ESD Considerations System-Level ESD has become increasingly demanding
with silicon technology scaling towards lower voltages and the need for designing costeffective and ultra-low-power components. This application report addresses three different
ESD topics to help board designers and OEMs understand and design robust system-level
designs: (1) Component-level ESD testing and system-level ESD testing, their differences
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and why component-level ESD rating does not ensure system-level robustness. (2) General
design guidelines for system-level ESD protection at different levels including enclosures,
cables, PCB layout, and on-board ESD protection devices. (3) Introduction to System
Efficient ESD Design (SEED), a co-design methodology of on-board and on-chip ESD
protection to achieve system-level ESD robustness, with example simulations and test
results. A few real-world system-level ESD protection design examples and their results are
also discussed.
DN005 CC11xx Sensitivity versus Frequency Offset and Crystal Accuracy This design note provides
plots of CC11xx (CC1100, CC1100E, CC1101, CC1110, and CC1111) sensitivity versus
frequency offset for different data rates. The required crystal accuracy is calculated from
these plots. The results are also applicable for CC430.
AN050 Using the CC1101 in the European 868 MHz SRD Band The CC1101 is a truly low cost, highly
integrated, and very flexible RF transceiver. The CC1101 is primarily designed for use in
low-power applications in the 315, 433, 868 and 915 MHz SRD/ISM bands. This application
note describes how to use the CC1101 in the European 863 – 870 MHz SRD frequency
bands in order to comply with EN 300 220 requirements. The application note is also
applicable for CC1110, CC1111, and CC430 SoCs as they use the same radio as CC1101.
DN010 Close-in Reception with CC1101 This document describes how the CC1100E and CC1101 can
be used in close-range applications. The chips have a saturation limit of approximately −15
dBm at 250 kbps, which might be a challenge for some short-range applications. Two
suggested solutions are presented, the first is a double-transmit scheme and the second is
to shift the receivers dynamic range during close-range reception.
DN013 Programming Output Power on CC1101 The CC1101 RF output power level is set by the
PATABLE register setting. This register setting also influences the power levels at the
different harmonics and the current consumption for the device. These parameters must
therefore be considered when choosing the optimal register settings. This document gives
complete CC1101 PA tables with typical output power, harmonics, and current consumption
for the different register settings at 25°C and 3.0 V supply voltage.
DN017 CC11xx 868/915 MHz RF Matching This design note gives a short introduction to RF matching
and important aspects when designing products using the CC11xx parts. Because all of the
CC11xx parts have the same RF front end, the same matching network can be used
between the radio and the antenna. TI provides a reference design for all CC11xx products.
These reference designs show recommended placement and values for decoupling
capacitors and components in the matching network.
116
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CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
www.ti.com
8.5
SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
Related Links
Table 8-1 lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 8-1. Related Links
8.6
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
CC430F6137
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CC430F6135
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CC430F6127
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CC430F6126
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CC430F6125
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CC430F5137
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CC430F5135
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CC430F5133
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Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At
e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow
engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
8.7
Trademarks
MSP430, MSP430Ware, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
8.8
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.9
Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
authorization from U.S. Department of Commerce and other competent Government authorities to the
extent required by those laws.
8.10 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
Device and Documentation Support
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117
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018
www.ti.com
9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
118
Mechanical, Packaging, and Orderable Information
Submit Documentation Feedback
Copyright © 2009–2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
CC430F5133IRGZ
ACTIVE
VQFN
RGZ
48
52
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
CC430
F5133
CC430F5133IRGZR
ACTIVE
VQFN
RGZ
48
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
CC430
F5133
CC430F5133IRGZT
ACTIVE
VQFN
RGZ
48
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
CC430
F5133
CC430F5135IRGZ
ACTIVE
VQFN
RGZ
48
52
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
CC430
F5135
CC430F5135IRGZR
ACTIVE
VQFN
RGZ
48
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
CC430
F5135
CC430F5135IRGZT
ACTIVE
VQFN
RGZ
48
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
CC430
F5135
CC430F5137IRGZ
ACTIVE
VQFN
RGZ
48
52
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
CC430
F5137
CC430F5137IRGZR
ACTIVE
VQFN
RGZ
48
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
CC430
F5137
CC430F5137IRGZT
ACTIVE
VQFN
RGZ
48
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
CC430
F5137
CC430F6125IRGCR
ACTIVE
VQFN
RGC
64
2000
RoHS & Green NIPDAU | NIPDAUAG
Level-3-260C-168 HR
-40 to 85
CC430F6125
CC430F6126IRGCR
ACTIVE
VQFN
RGC
64
2000
RoHS & Green NIPDAU | NIPDAUAG
Level-3-260C-168 HR
-40 to 85
CC430F6126
CC430F6127IRGCR
ACTIVE
VQFN
RGC
64
2000
RoHS & Green NIPDAU | NIPDAUAG
Level-3-260C-168 HR
-40 to 85
CC430F6127
CC430F6127IRGCT
ACTIVE
VQFN
RGC
64
250
RoHS & Green NIPDAU | NIPDAUAG
Level-3-260C-168 HR
-40 to 85
CC430F6127
CC430F6135IRGCR
ACTIVE
VQFN
RGC
64
2000
RoHS & Green NIPDAU | NIPDAUAG
Level-3-260C-168 HR
-40 to 85
CC430F6135
CC430F6137IRGCR
ACTIVE
VQFN
RGC
64
2000
RoHS & Green NIPDAU | NIPDAUAG
Level-3-260C-168 HR
-40 to 85
CC430F6137
CC430F6137IRGCT
ACTIVE
VQFN
RGC
64
250
RoHS & Green NIPDAU | NIPDAUAG
Level-3-260C-168 HR
-40 to 85
CC430F6137
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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