MSP-TS430L092

MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 MIXED SIGNAL MICROCONTROLLER FEATURES 1 • • • • • • • • Ultra-Low Supply Voltage (ULV) Range – 0.9 V to 1.5 V (1 MHz) – 1.5 V to 1.65 V (4 MHz) Low Power Consumption – Active Mode (AM): 45 µA/MHz (1.3 V) – Standby Mode (LPM3, WDT_A Mode): 6 µA – Off Mode (LPM4): 3 µA Wake-Up From LPMx in Less Than 5 µs 16-Bit RISC Architecture – Extended Instructions – Up to 4-MHz System Clock Compact Clock System – 1-MHz Internal Trimmable High-Frequency Clock – 20-kHz Internal Low-Frequency Clock Source – External Clock Input 16-Bit Timer0_A3 With Three Capture/Compare Registers 16-Bit Timer1_A3 With Three Capture/Compare Registers ULV Analog Pool Modes – 8-Bit Analog-to-Digital Converter (ADC) – 8-Bit Digital-to-Analog Converter (DAC) – Programmable Comparator (COMP) – Supply Voltage Monitor (SVM) – Temperature Sensor – Internal Reference Voltage Source • • • • • • • • ULV Port Logic – VOL Better Than 0.15 V at 2.5 mA – VOH Better Than VCC – 0.15 V at 1 mA – Timer0 PWM Signal Available on All Ports – Timer1 PWM Signal Available on All Ports ULV Brownout Circuit (BOR) ULV RAM Retention Voltage Below BOR Level 32-Bit Watchdog Timer (WDT-A) Bootstrap Loader in MSP430L092 Development/Prototyping Device Full Four-Wire JTAG Debug Interface Family Members Include – MSP430C091 – 1KB ROM Memory – 128 Bytes RAM + 96 Bytes CRAM (Lockable) – MSP430C092 – 2KB ROM Memory – 128 Bytes RAM + 96 Bytes CRAM (Lockable) – MSP430L092 – 2KB Loader ROM With Service Functions – 2KB RAM (1792 + 128 + 96 Bytes Lockable) For Complete Module Descriptions, See the MSP430x09x Family User’s Guide (SLAU321) DESCRIPTION The Texas Instruments MSP430 family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled internal oscillators allow wake-up from low-power modes to active mode in less than 5 µs. The MSP430C09x and MSP430L092 series are microcontroller configurations with two 16-bit timers, an ultra-low-voltage 8-bit analog-to-digital (A/D) converter, an 8-bit digital-to-analog (D/A) converter, and up to 11 I/O pins. Typical applications for this device include single-cell systems requiring a full analog signal chain. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com ORDERING INFORMATION (1) PACKAGED DEVICES (2) PLASTIC 14-PIN TSSOP (PW) TA MSP430C091SPW 0ºC to 50ºC MSP430C092SPW MSP430L092SPW (1) (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/package. Pin Designation, MSP430C091PW, MSP430C092PW PW PACKAGE (TOP VIEW) TCK/P2.0/TA 0.2/TA1.2/TA1.1 TMS/P2.1/TA 0.2/TA1.2/TA0.1 TDI/P2.2/TA0.2/TA1.2/CxOUT/CCI0.0 TDO/P2.3/TA0.2/TA 1.2/CCI1.0 RST/NMI/SVMOUT P1.0/TA0.2/TA1.2/ACLK/CCI0.1/A2/CLKIN P1.1/TA0.2/TA1.2/SMCLK/CCI1.1/A1/TA0CLK 1 2 3 4 5 6 7 14 13 12 11 10 9 8 P1.6/TA0.2/TA1.2/TA 1.1 P1.5/TA0.2/TA1.2/TA 0.1 P1.4/TA0.2/TA1.2/MCLK/A0/TA1CLK VCC VSS/GND P1.3/TA0.2/TA1.2/CxOUT/CCI1.0/VREF/A3 P1.2/TA0.2/TA1.2/ACLK/CCI0.0/AOUT/A3 Functional Block Diagram, MSP430C092PW, MSP430C091PW RST/NMI/SVMOUT VCC GND/VSS P1.0...P1.6 P2.0...P2.3 128B RAM +96B CRAM I/O Port P1L 7 I/Os with Interrupt Capability I/O Port P2L 4 I/Os with Interrupt Capability Timer0_A3 Timer1_A3 AnalogPool LF-OSC HF-OSC CLKIN Clock System ACLK Reset Int-Logic 2/(1)KB ROM SMCLK MCLK CPU & Working Registers TMS, TCK, TDI, TDO 4W-JTAG Debug support CORE VREF 2 Submit Documentation Feedback ULV Brownout Watchdog WDTA 32/16-Bit 3 CC Registers 3 CC Register ULV-Ref., 8-Bit ADC, 8-Bit DAC, Comparator, SVS Copyright © 2010, Texas Instruments Incorporated MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 Pin Designation, MSP430L092PW PW PACKAGE (TOP VIEW) SPI_CS/TCK/P2.0/TA0.2/TA1.2/TA1.1 SPI_MOSI/TMS/P2.1/TA0.2/TA1.2/TA0.1 SPI_CLK/TDI/P2.2/TA0.2/TA1.2/CxOUT/CCI0.0 SPI_MISO/TDO/P2.3/TA0.2/TA1.2/CCI1.0 RST/NMI/SVMOUT P1.0/TA0.2/TA1.2/ACLK/CCI0.1/A2/CLKIN P1.1/TA0.2/TA1.2/SMCLK/CCI1.1/A1/TA0CLK 14 13 12 11 10 9 8 1 2 3 4 5 6 7 P1.6/TA0.2/TA1.2/TA1.1 P1.5/TA0.2/TA1.2/TA0.1 P1.4/TA0.2/TA1.2/MCLK/A0/TA1CLK VCC VSS/GND P1.3/TA0.2/TA1.2/CxOUT/CCI1.0/VREF/A3 P1.2/TA0.2/TA1.2/ACLK/CCI0.0/AOUT/A3/BOOST Functional Block Diagram, MSP430L092PW RST/NMI/SVMOUT VCC GND/VSS P1.0...P1.6 P2.0...P2.3 2kB RAM (128B+1792B +96B) I/O Port P1L 7 I/Os with Interrupt Capability I/O Port P2L 4 I/Os with Interrupt Capability Timer0_A3 Timer1_A3 AnalogPool LF-OSC HF-OSC CLKIN Clock System ACLK Reset Int-Logic 2KB ROM (Loader) SMCLK MCLK CPU & Working Registers TMS, TCK, TDI, TDO 4W-JTAG Debug support CORE VREF Copyright © 2010, Texas Instruments Incorporated ULV Brownout Watchdog WDTA 32/16-Bit 3 CC Registers 3 CC Register ULV-Ref., 8-Bit ADC, 8-Bit DAC, Comparator, SVS Submit Documentation Feedback 3 MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com Table 1. Terminal Functions TERMINAL NAME NO. I/O (1) DESCRIPTION JTAG test clock General-purpose digital I/O Timer0_A3 Out2 output TCK/P2.0/TA0.2/TA1.2/TA1.1 1 I/O Timer1_A3 Out2 output Timer1_A3 Out1 output Timer0_A3 CCR2 capture: CCI2A input, compare Timer1_A3 CCR2 capture: CCI2A input, compare JTAG test mode select General-purpose digital I/O Timer0_A3 Out2 output TMS/P2.1/TA0.2/TA1.2/TA0.1 2 I/O Timer1_A3 Out2 output Timer0_A3 Out1 output Timer0_A3 CCR2 capture: CCI2B input, compare Timer1_A3 CCR2 capture: CCI2B input, compare JTAG test data input General-purpose digital I/O Timer0_A3 Out2 output TDI/P2.2/TA0.2/TA1.2/CCI0.0/CxOUT 3 I/O Timer1_A3 Out2 output Comparator output Timer0_A3 CCR0 capture: CCI0A input, compare Test clock input JTAG test data output General-purpose digital I/O TDO/P2.3/TA0.2/TA1.2/CCI1.0 4 I/O Timer0_A3 Out2 output Timer1_A3 Out2 output Timer1_A3 CCR0 capture: CCI0A input, compare Reset input active low RST/NMI/SVMOUT 5 I/O Non-maskable interrupt input SVM output General-purpose digital I/O Timer0_A3 Out2 output Timer1_A3 Out2 output P1.0//TA0.2/TA1.2/ACLK/CCI0.1/A2/CLKIN 6 I/O ACLK output Timer0_A3 CCR1 capture: CCI1B input, compare Analog input A2 – A-Pool Input terminal for external clock General-purpose digital I/O Timer0_A3 Out2 output Timer1_A3 Out2 output P1.1/TA0.2/TA1.2/SMCLK/CCI1.1/A1/TA0CLK 7 I/O SMCLK output Timer1_A3 CCR1 capture: CCI1B input, compare Analog input A1 – A-Pool Timer0_A3 clock signal TACLK input (1) 4 I = input, O = output, N/A = not available on this package offering Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 Table 1. Terminal Functions (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION General-purpose digital I/O Timer0_A3 Out2 output Timer1_A3 Out2 output P1.2/TA0.2/TA1.2/ACLK/CCI0.0/AOUT/A3 8 I/O ACLK output Timer0_A3 CCR0 capture: CCI0B input, compare Analog input A3 – A-Pool Analog output – A-Pool General-purpose digital I/O Timer0_A3 Out2 output Timer1_A3 Out2 output P1.3/TA0.2/TA1.2/CxOUT/CCI1.0/VREF/A3 9 I/O Comparator output Timer1_A3 CCR0 capture: CCI0B input, compare Analog input A3 – A-Pool Reference voltage input / output VSS/GND 10 Analog and digital power supply ground reference VCC 11 Analog and digital power supply General-purpose digital I/O Timer0_A3 Out2 output P1.4/TA0.2/TA1.2/MCLK/A0/TA1CLK 12 I/O Timer1_A3 Out2 output MCLK Output Analog input A0 – A-Pool General-purpose digital I/O Timer0_A3 Out2 output P1.5/TA0.2/TA1.2/TA0.1 13 I/O Timer1_A3 OUT2 output Timer0_A3 OUT1 output Timer0_A3 CCR1 capture: CCI1A input, compare General-purpose digital I/O Timer0_A3 Out2 output P1.6/TA0.2/TA1.2/TA1.1 14 I/O Timer1_A3 OUT2 output Timer1_A3 OUT1 output Timer1_A1 CCR1 capture: CCI1A input, compare Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 5 MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com SHORT-FORM DESCRIPTION CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. Program Counter PC/R0 Stack Pointer SP/R1 Status Register Constant Generator SR/CG1/R2 CG2/R3 General-Purpose Register R4 General-Purpose Register R5 General-Purpose Register R6 General-Purpose Register R7 General-Purpose Register R8 General-Purpose Register R9 General-Purpose Register R10 Instruction Set General-Purpose Register R11 The instruction set consists of the original 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 2 shows examples of the three types of instruction formats, Table 3 shows the address modes. General-Purpose Register R12 General-Purpose Register R13 General-Purpose Register R14 General-Purpose Register R15 The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. Table 2. Instruction Word Formats Dual operands, source-destination e.g., ADD R4,R5 R4 + R5 → R5 Single operands, destination only e.g., CALL R8 PC→(TOS), R8 →PC Relative jump, un/conditional e.g., JNE Jump-on-equal bit = 0 Table 3. Address Mode Descriptions ADDRESS MODE (1) 6 S (1) D (1) SYNTAX EXAMPLE Register ● ● MOV Rs, Rd MOV R10, R11 OPERATION R10 → R11 Indexed ● ● MOV X(Rn), Y(Rm) MOV 2(R5), 6(R6) M(2+R5)→ M(6+R6) Symbolic (PC relative) ● ● MOV EDE, TONI Absolute ● ● MOV & MEM, & TCDAT Indirect ● MOV @Rn, Y(Rm) MOV @R10, Tab(R6) M(R10) → M(Tab+R6) Indirect autoincrement ● MOV @Rn+, Rm MOV @R10+, R11 M(R10) → R11 R10 + 2→ R10 Immediate ● MOV #X, TONI MOV #45, TONI #45 → M(TONI) M(EDE) → M(TONI) M(MEM) → M(TCDAT) S = source D = destination Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 Operating Modes The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: • Active mode (AM) – All clocks are active • Low-power mode 0 (LPM0) – CPU is disabled – ACLK and SMCLK remain active for all sources – MCLK is disabled • Low-power mode 1 (LPM1) – CPU is disabled – ACLK and SMCLK remain active (for LF oscillator and CLKIN as source, HF oscillator is mapped to LF oscillator as source) – MCLK is disabled • Low-power mode 2 (LPM2) – CPU is disabled – MCLK is disabled – SMCLK is disabled – ACLK remains active for all sources • Low-power mode 3 (LPM3) – CPU is disabled – MCLK is disabled – SMCLK is disabled – ACLK remains active (for LF oscillator and CLKIN as source, HF oscillator is mapped to LF oscillator as source) • Low-power mode 4 (LPM4) – CPU is disabled – MCLK is disabled – SMCLK is disabled – ACLK is disabled – Oscillators are stopped LPM2 vs LPM3 If only MCLK is feed by the HF oscillator (SELA ≠ 00, SELS ≠ 00, SELM = 00 of CCSCTL4 register) the following behavior is implemented: • Entering LPM2 turns off the HF oscillator and starts again with the HF oscillator selected for MCLK • Entering LPM3 turns off the HF oscillator and starts again with the LF oscillator selected for MCLK The only difference between LPM2 and LPM3 is the selection of the source for MCLK when re-entering active mode and, therefore, and the level of power savings. Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 7 MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com Interrupt Vector Addresses The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 4. Interrupt Sources, Flags, and Vectors INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY System Reset Power-Up External Reset Watchdog WDTIFG (1) Reset 0x0FFFE 15, highest System NMI Vacant memory access SVMIFG, VMAIFG (1) (Non)maskable 0x0FFFC 14 User NMI NMI NMIIFG (1) (2) (Non)maskable 0x0FFFA 13 Timer1_A3 TA1CCR0 CCIFG0 (3) Maskable 0x0FFF8 12 Timer1_A3 Maskable 0x0FFF6 11 Watchdog Timer_A Interval Timer Mode WDTIFG Maskable 0x0FFF4 10 A-Pool CxIFG Maskable 0x0FFF2 9 I/O Port P1 (1) (2) (3) (4) 8 TA1CCR1 CCIFG1 (1) (3) P1IFG.0 to P1IFG.6 (1) (3) Maskable 0x0FFF0 8 Timer0_A3 TA0CCR0 CCIFG0 (3) Maskable 0x0FFEE 7 Timer0_A3 TA0CCR1 CCIFG1 (1) (3) Maskable 0x0FFEC 6 I/O Port P2 P2IFG.0 to P2IFG.3 (1) (3) Maskable 0x0FFEA 5 0x0FFE8 4 Reserved Reserved (4) ⋮ ⋮ 0x0FFE0 0 Multiple source flags A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it. Interrupt flags are located in the module. Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain compatibility with other devices, it is recommended to reserve these locations. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 Special Function Registers (SFRs) The MSP430 SFRs are located in the lowest address space and can be accessed via word or byte formats. Legend rw: rw-0,1: rw-(0,1): Bit can be read and written. Bit can be read and written. It is reset or set by PUC. Bit can be read and written. It is reset or set by POR. SFR bit is not present in device. Interrupt Enable 1 15 14 13 12 11 10 9 8 SVMIE r0 r0 r0 r0 r0 r0 r0 rw-0 7 6 5 4 3 2 1 0 JMBOUTIE JMBINIE NMIIE VMAIE OFIE WDTIE rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 SVMIE JMBOUTIE JMBINIE NMIIE VMAIE OFIE WDTIE r0 r0 SVM interrupt enable Nonmaskable-interrupt enable Vacant memory access interrupt enable Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured as a general-purpose timer. Interrupt Enable 2 15 14 13 12 11 10 9 8 SVMIFG r0 r0 r0 5 7 6 JMBOUTIFG JMBINIFG rw-0 rw-0 SVMIFG JMBOUTIFG JMBINIFG NMIIFG VMAIFG OFIFG WDTIFG r0 r0 r0 r0 2 4 3 NMIIFG VMAIFG rw-0 rw-0 r0 r0 rw-0 1 0 OFIFG WDTIFG rw-0 rw-0 Set by SVM when voltage falls below set voltage Set via RST/NMI pin Set on vacant memory access Set on watchdog timer overflow (in watchdog mode) or security key violation Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 9 MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com Reset Pin Control Register 15 14 13 12 11 10 9 8 r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 r0 SYSRSTRE SYSRSTUP SYSNMIES SYSNMI r0 r0 3 2 1 0 SYSRSTRE SYSRSTUP SYSNMIES SYSNMI r1 r1 r1 rw-0 r0 Indicates resistor present on RST pin Indicates pullup on RST pin Indicates NMI edge select NMI enable on RST/NMI pin Memory Organization Table 5. Memory Organization TYPE Primary interrupt vectors ROM Secondary interrupt vectors RAM Lockable Application ROM memory ROM Boot Code (BC) / Loader Code ROM (by TI) RAM memory RAM LRAM memory (lockable) RAM CRAM memory (lockable) RAM Peripherals (1) (2) (3) Size MSP430C091 MSP430C092 MSP430L092 MSP430L092 (EMU) (1) 32 B 32 B 32 B 32 B 0x0FFE0 (2) – 0x0FFFF 0x0FFE0 (2) – 0x0FFFF 0x0FFE0 (2) – 0x0FFFF 0x0FFE0 (2) – 0x0FFFF 0x01C60 – 0x01C7F 864 B 1888 B 0x0FC80 – 0x0FFDF 0x0F880 – 0x0FFDF ROM not available 128 B (BC) 128 B (BC) 2016 B (Loader) Config/loading by tool 0x0F800 – 0x0F87F 0x0F800 – 0x0F87F 0x0F800 – 0x0FFDF 0x0F800 – 0x0F87F 128B 128B 128 B 128 B 0x02380 – 0x023FF 0x02380 – 0x023FF 0x02380 – 0x023FF 0x02380 – 0x023FF 1792 B 1760 B 0x01C80 – 0x0237F 0xF900 – 0xFFDF 96 B 96 B 96 B 128 B (3) 0x01C00 – 0x01C5F 0x01C00 – 0x01C5F 0x01C00 – 0x01C5F 0x0F880 – 0x0F8FF 4 kB 4 kB 4 kB 4 kB 0x00000 – 0x00FFF 0x00000 – 0x00FFF 0x00000 – 0x00FFF 0x00000 – 0x00FFF The MSP430L092 emulates the MSP430C092 device (MSP430C091 emulation via tool and software). Not the whole interrupt vector range of CSYS is used on MSP430x09x devices (see Table 4). Resets and interrupt redirections in RAM with alternate interrupt vectors cannot be emulated . Start-Up Code (SUC) The MSP430C09x start-up code checks the password and releases control to the application or enables JTAG on password match, enters LPM4, and waits for a debug session. The behavior of the SUC is described in the MSP430L092 Loader Code User's Guide (SLAU324). Loader Code (Loader) The MSP430L092 loader checks the presence of an external SPI/I2C memory device containing a valid code signature, loads validated code into the application LRAM, and starts the application. The loader program uses P1.2 with an external circuit to pump up the voltage required for SPI memory device readout. For complete description of the features of the loader and its implementation, see the MSP430L092 Loader Code User's Guide (SLAU324). 10 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 RAM Memory The RAM memory is split into three ranges for different purposes: application memory, lockable application memory, and calibration memory. Lockable application memory and calibration memory can be protected against accidental erasure by setting a dedicated lock bit in the special functions register (System Maintenance Register). Peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x09x Family User's Guide (SLAU321). Digital I/O There are two I/O ports implemented: P1 (7 I/O lines) and P2 (4 I/O lines). • All individual I/O bits are independently programmable. • Any combination of input, output, and interrupt conditions is possible. • Programmable pullup or pulldown on all ports. • Edge-selectable interrupt input capability for all ports on P1 and P2. • Read/write access to port-control registers is supported by all instructions. • Ports can be accessed byte-wise (P1 and P2) or word-wise in pairs (P1/P2 combo). Oscillator and System Clock The clock system in the MSP430x09x family of devices is supported by the Compact Clock System (CCS) module that includes support for an internal 20-kHz current-controlled low-frequency oscillator (LF-OSC), an internal adjustable 1-MHz current-controlled high-frequency oscillator (HF-OSC), and an external clock input from CLKIN; however, a missing CLKIN signal does not trigger an oscillator failsafe mechanism in this family. The CCS module is designed to meet the requirements of both low system cost and low power consumption. The CCS provides a fast turn-on of the oscillators, less than 1 ms. The CCS module provides the following clock signals: • Auxiliary clock (ACLK), sourced from the 20-kHz internal LF-OSC, the 1-MHz internal HF-OSC, or CLKIN. • Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made available to ACLK. • Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by same sources made available to ACLK. • VLOCLK is an ultra-low-power low-frequency clock that is available as long the device is powered. Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 11 MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com OSCOFF SELAx ACLK enable logic DIVAx 3 00 01 10 11 HF – OSC Divider /1/2/4/8/16/32 0 1 1 ACLK SCG0 SELMx CPUOFF MCLK enable logic LF-OSC DIVMx 3 00 01 10 11 0 CLKIN /2 Divider /1/2/4/8/16/32 0 1 1 SELSx 1 MCLK SCG1 SMCLK enable logic DIVSx DIVCLK 00 01 10 11 3 Divider /1/2/4/8/16/32 0 1 1 SMCLK VLOCLK Figure 1. Compact Clock System (CCS) Block Diagram Watchdog Timer (WDT_A) The primary function of the watchdog timer (WDT_A) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. Table 6. WDT_A Signal Connections DEVICE CLOCK SIGNAL MODULE CLOCK SIGNAL ACLK ACLK SMCLK SMCLK LF-OSC-CLK VLOCLK LF-OSC-CLK X-CLK Compact System Module (C-SYS) The Compact SYS module handles many of the system functions within the device. These include power-on reset and power-up clear handling, NMI source selection and management, reset interrupt vector generators, and configuration management. It also includes a data exchange mechanism via JTAG called a JTAG mailbox that can be used in the application. 12 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 RST/NMI/SVMOUT System The reset system of the MSP430x09x family features the functions reset input, reset output, NMI input, SVM output, and SVS input. ... Interrupt signals maskable/ unmaskable Interrupt Logic CPU irq nmi Resetsignals and violations PUC ... Reset Logic POR BOR SWBOR RST/NMI/ SVMOUT SWPOR RSTNMI Brownout Circuit & Delay clr from SVM logic SVMOE PortsOn SVSEN SVMPD set SVMPO Figure 2. RST/NMI/SVMOUT and PortsOn Logic Block Diagram Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 13 MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com Table 7. System Module Interrupt Vector Registers INTERRUPT VECTOR REGISTER SYSRSTIV, System Reset SYSSNIV, System NMI SYSUNIV, User NMI SYSBERRIV, Bus Error 14 Submit Documentation Feedback INTERRUPT VECTOR WORD ADDRESS OFFSET No interrupt pending 00h Brownout (BOR) 02h SVMBOR (BOR) 04h RST/NMI (BOR) 06h DoBOR (BOR) 08h Security violation (BOR) 0Ah DoPOR(POR) 019Eh WDT timeout (PUC) 0Eh 10h CCS key violation 12h PMM key violation 14h Peripheral area fetch (PUC) 16h Reserved 18h-3Eh No interrupt pending 00h SVMIFG 02h VMAIFG 04h 019Ch 08h Reserved 0Ah-3Eh No interrupt pending 00h NMIFG 02h 019Ah 06h Reserved 08h-3Eh Reserved 0198h Highest Lowest Highest 04h BERR No interrupt pending Lowest 06h JMBOUTIFG OFIFG Highest 0Ch WDT key violation (PUC) JMBINIFG PRIORITY Lowest 00h 02h-3Eh Lowest Copyright © 2010, Texas Instruments Incorporated MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 Timer0_A3 Timer0_A3 is a 16-bit timer/counter with three capture/compare registers. Timer0_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer0_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 8. Timer0_A3 Signal Connections INPUT PIN NUMBER PW 7 – P1.1 DEVICE INPUT SIGNAL MODULE INPUT SIGNAL TA0CLK TACLK ACLK ACLK SMCLK SMCLK 7 – P1.1 TA0CLK TACLK 3 – P2.2 CCI0.0 CCI0A 8 – P1.2 CCI0.0 CCI0B VSS GND MODULE BLOCK MODULE DEVICE OUTPUT OUTPUT SIGNAL SIGNAL Timer NA NA CCR0 TA0 TA0.0 OUTPUT PIN NUMBER PW VCC VCC 13 – P1.5 TA0.1 CCI1A 2 – P2.1 6 – P1.0 CCI0.1 CCI1B 13 – P1.5 VSS GND VCC VCC 1 – P2.0 TA0.2 CCI2A 2 – P2.1 TA0.2 CCI2B VSS GND VCC VCC Copyright © 2010, Texas Instruments Incorporated CCR1 TA1 TA0.1 1-4 – P2.0-P2.3 CCR2 TA2 TA0.2 6-9 – P1.0-P1.3 12-14 – P1.4-P1.6 Submit Documentation Feedback 15 MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com Timer1_A3 Timer1_A3 is a 16-bit timer/counter with three capture/compare registers. Timer1_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer1_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 9. Timer1_A3 Signal Connections INPUT PIN NUMBER PW 12 – P1.4 16 DEVICE INPUT SIGNAL MODULE INPUT SIGNAL TA1CLK TACLK ACLK ACLK SMCLK SMCLK 12 – P1.4 TA1CLK TACLK 4 – P2.3 CCI1.0 CCI0A 9 – P1.3 CCI1.0 CCI0B VSS GND VCC VCC 14 – P1.6 TA1.1 CCI1A 7 – P1.1 CCI1.1 CCI1B VSS GND VCC VCC 1 – P2.0 TA1.2 CCI2A 2 – P2.1 TA1.2 CCI2B VSS GND VCC VCC Submit Documentation Feedback MODULE BLOCK MODULE DEVICE OUTPUT OUTPUT SIGNAL SIGNAL Timer NA CCR0 TA0 OUTPUT PIN NUMBER PW NA TA1.0 1 – P2.0 CCR1 TA1 TA1.1 14 – P1.6 1-4 – P2.0-P2.3 CCR2 TA2 TA1.2 6-9 – P1.0-P1.3 12-14 – P1.4-P1.6 Copyright © 2010, Texas Instruments Incorporated MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 A-Pool The analog functions pool (A-Pool) provides a series of functions that can be configured to a digital-to-analog converter (DAC), multichannel analog-to-digital converter (ADC), supply voltage supervisor (SVS), and comparator. Input voltage dividers and an internal reference source allow a wide range of combined analog functions. PSELx VREF REFON Reference 256mV CMPON + OSEL NSELx Vcc Vcc 6R OSWP DFSETx CxIFG logic 0 DeGlitching 1 xCLK from AZ-logic DBON ODEN Aout 1 CLKSEL EOCIFG logic 2 VLOCLK MCLK SMCLK 00 01 10 11 CBSTP SBSTP TBSTP TA0.1 Pre-Scaler ? by 1/2/4/8/16/32 R D/A-8 R CxOUT SVMIFG logic SLOPE 0 4 0000 0001 0010 0011 0100 0101 0110 0111 A0 A1 A2 A3 AZ EN CT VREFEN 4 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 Clock CLKDIVx Logic xCLK 8 ADC-DAC-SAR-REG Up-Dn Counter sEOC TA0.0 TA0EN TA1EN TA1.0 clr Run/ Stop set Start Stop Logic APVDIV Register CONVON SLOPE SAREN MDB and buffer register Figure 3. A-Pool Block Diagram Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 17 MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com Versatile I/O Port P1, P2 The versatile I/O ports P1 and P2 feature device-dependent reset values. The reset values for the MSP430x09x devices are shown in Table 10. Table 10. Versatile Port Reset Values PORT NUMBER PxOUT PxDIR PxREN PxSEL0 PxSEL1 RESET PORTS ON COMMENT P1.0 0 0 0 0 0 PUC yes P1.0, input P1.1 0 0 0 0 0 PUC yes P1.1, input P1.2 0 0 0 0 0 PUC yes P1.2, input P1.3 0 0 0 0 0 PUC yes P1.3, input P1.4 0 0 0 0 0 PUC yes P1.4, input P1.5 0 0 0 0 0 PUC yes P1.5, input P1.6 0 0 0 0 0 PUC yes P1.6, input P1.7 - - - - - - - - P2.0 1 0 1 1 1 BOR no JTAG TCK, input, pullup P2.1 1 0 1 1 1 BOR no JTAG TMS, input, pullup P2.2 1 0 1 1 1 BOR no JTAG TDI, input, pullup P2.3 0 1 0 1 1 BOR no JTAG TDO, output, pullup Peripheral File Map Table 11. Peripherals MODULE NAME REGISTER DESCRIPTION Timer1_A interrupt vector Timer1_A3 OFFSET TA1IV 2Eh TA1CCR2 16h Capture/compare register 1 TA1CCR1 14h Capture/compare register 0 TA1CCR0 Timer1_A register TA1R 12h 0380h 10h Capture/compare control 2 TA1CCTL2 06h Capture/compare control 1 TA1CCTL1 04h Capture/compare control 0 TA1CCTL0 02h TA1CTL 00h Timer0_A interrupt vector TA0IV 2Eh Capture/compare register 2 TA0CCR2 16h Capture/compare register 1 TA0CCR1 14h Capture/compare register 0 TA0CCR0 12h Timer1_A register TA0R 0340h 10h Capture/compare control 2 TA0CCTL2 06h Capture/compare control 1 TA0CCTL1 04h Capture/compare control 0 TA0CCTL0 02h TA0CTL 00h Timer1_A control 18 BASE ADDRESS Capture/compare register 2 Timer1_A control Timer0_A3 REGISTER Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 Table 11. Peripherals (continued) MODULE NAME REGISTER DESCRIPTION Port P2 interrupt Flag Port P2 interrupt enable Port P2 interrupt edge select Port P2 interrupt vector word Port P2 P2IFG 1Dh P2IE 1Bh P2IES 19h P2IV 1Eh 0Dh Port P2 selection 0 P2SEL0 Port P2 pullup/pulldown enable P2REN 07h Port P2 direction P2DIR 05h Port P2 output P2OUT 03h P2IN 01h P1IFG 1Ch P1IE 1Ah P1IES 18h Port P1 interrupt enable Port P1 interrupt edge select Port P1 interrupt vector word 0200h 0Bh P1IV 0Eh Port P1 selection 1 P1SEL1 0Ch Port P1 selection 0 P1SEL0 Port P1 pullup/pulldown enable P1REN 06h Port P1 direction P1DIR 04h Port P1 output P1OUT 02h Port P1 input P1IN 00h Analog pool interrupt vector register APIV 1Eh Analog pool interrupt enable register APIE 1Ch Analog pool interrupt flag register APIFG 1Ah Analog pool fractional value buffer APFRACTB 16h Analog pool fractional value register Analog pool integer value buffer Analog pool integer value register 0200h APFRACT APINTB 0Ah 14h 01A0h 12h APINT 10h Analog pool voltage divider register APVDIV 06h Analog pool operation mode register APOMR 04h Analog pool control register APCTL 02h Analog pool configuration register APCNF 00h SYSRSTIV 1Eh SYSSNIV 1Ch User NMI vector generator SYSUNIV 1Ah Bus error vector generator SYSBERRIV 18h SYSCNF 10h Reset vector generator System NMI vector generator System Configuration register CSYS OFFSET P2SEL1 Port P1 interrupt Flag A-POOL BASE ADDRESS Port P2 selection 1 Port P2 input Port P1 REGISTER JTAG mailbox output register #1 SYSJMBO1 JTAG mailbox output register #0 SYSJMBO0 0Ch JTAG mailbox input register #1 SYSJMBI1 0Ah JTAG mailbox input register #0 SYSJMBI0 08h JTAG mailbox control register SYSJMBC 06h SYSCTL 00h System control register Copyright © 2010, Texas Instruments Incorporated 0180h 0Eh Submit Documentation Feedback 19 MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com Table 11. Peripherals (continued) MODULE NAME REGISTER DESCRIPTION REGISTER BASE ADDRESS OFFSET CCS control 15 register CCSCTL15 CCS control 8 register CCSCTL8 10h CCS control 7 register CCSCTL7 0Eh CCS control 5 register CCSCTL5 CCS control 4 register CCSCTL4 CCS control 2 register CCSCTL2 04h CCS control 1 register CCSCTL1 02h CCS control 0 register CCSCTL0 WDT_A Watchdog timer control WDTCTL 0150h 0Ch PMM PMM control 0 PMMCTL0 0120h 00h ET-Wrapper ET Key and select ETKEYSEL 0110h 00h SFR Reset pin control register SFRRPCR CCS Special Functions SFR interrupt flag register SFR interrupt enable register 20 Submit Documentation Feedback SFRIFG1 SFRIE1 1Eh 0160h 0Ah 08h 00h 04h 0100h 02h 00h Copyright © 2010, Texas Instruments Incorporated MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 Absolute Maximum Ratings (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) Voltage applied at VCC referenced to VSS (VAMR) –0.3 V to 1.90 V –0.3 V to VCC + 0.3 V Voltage applied to any pin (references to VSS) –0.3 V to 1.90 V Diode current at any device pin (2) ±2.5 mA Current derating factor when I/O ports are switched in parallel electrically and logically (3) 0.9 Storage temperature range (4) –55°C to 150°C ESD tolerance, Human-Body Model (HBM) (1) (2) (3) (4) 2000 V Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages referenced to VSS. The diode current increases to ±4.5 mA when two pins are connected, ± 6.75 mA for three pins. Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. Recommended Operating Conditions over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) MIN VCC Supply voltage during program execution VSS Supply voltage (GND reference) TA Operating free-air temperature CVCC Capacitor on VCC fSYSTEM (1) ( System operating frequency 2) (1) (2) NOM 0.9 MAX UNIT 1.65 V 0 0 V 50 470 °C nF VCC > 0.9 V, tLOW ≥ 450 ns, tHIGH ≥ 450 ns 1 MHz VCC > 1.5 V, tLOW ≥ 113 ns, tHIGH ≥ 113 ns 4 MHz The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency. Modules may have a different maximum input clock specification. Refer to the specification of the respective module in this data sheet. Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 21 MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com Active Mode Supply Current (Into VCC) Excluding External Current (1) (2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC fMCLK = fSMCLK = 1 MHz, fACLK = 20 kHz, Program executes in RAM, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 IAM,1MHz 1.3 V MAX 59 68 84 86 101 59 68 72 84 1.65 V 86 101 0.9 V 60 70 74 87 1.65 V 88 105 0.9 V 31 35 33 38 1.65 V 37 42 0.9 V 31 35 33 38 37 42 32 37 35 41 40 48 1.3 V 1.3 V fMCLK = fSMCLK = 125 kHz, fACLK = 20 kHz Program executes in RAM CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 TYP 72 1.3 V 1.3 V 30°C 50°C 0°C 30°C 1.65 V 0.9 V fMCLK = fSMCLK = 125 kHz, fACLK = 20 kHz, Program executes in RAM, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (1) (2) 0°C 0.9 V fMCLK = fSMCLK = 1 MHz, fACLK = 20 kHz, Program executes in RAM, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 fMCLK = fSMCLK = 125 kHz, fACLK = 20 kHz, Program executes in RAM, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 IAM/MHz MIN 1.65 V fMCLK = fSMCLK = 1 MHz, fACLK = 20 kHz, Program executes in RAM, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 IAM,125kHz TA 0.9 V 1.3 V 50°C 1.65 V fMCLK = fSMCLK : 1 to 5 MHz, fACLK = 20 kHz Program executes in RAM, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 1.3 V 30°C UNIT µA µA µA/ MHz 45 All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. Characterized with program executing typical data processing "Type2". Low-Power Mode Supply Current (Into VCC) Excluding External Current (1) (2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA 0.9 V 1.3 V 0°C 1.65 V 0.9 V ILPM0 fMCLK = fSMCLK = 1 MHz, fACLK = 20 kHz CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 7.6 9 8.6 11 9 1.65 V 9.5 12 0.9 V 8.9 12 11 14 1.65 V 12 17 0.9 V 6.6 8 7.6 9 1.65 V 8.6 11 0.9 V 7 9 8.3 11 9,5 12 8.9 12 11 14 12 17 1.3 V 50°C 0°C 30°C 0.9 V 1.3 V 1.65 V 22 8 11 30°C 1.65 V (1) (2) MAX 6.6 7 1.3 V fMCLK = fSMCLK = 1 MHz, fACLK = 20 kHz CPUOFF = 1, SCG0 = 1, SCG1 = 0, OSCOFF = 0 TYP 8.3 1.3 V 1.3 V ILPM1 MIN 50°C UNIT µA µA Current for WDT clocked by ACLK included. Current for Brownout included. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 Low-Power Mode Supply Current (Into VCC) Excluding External Current(1)(2) (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA MIN 0.9 V 1.3 V ILPM2,1MHz fMCLK = fSMCLK = 1MHz, fACLK = 1MHz CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 fMCLK = fSMCLK = fACLK = 20 kHz CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 32 29 33 0.9 V 28 32 30 35 1.65 V 32 38 0.9 V 6.6 8 7.6 10 1.65 V 8.6 11 0.9 V 7 10 8.3 12 1.65 V 9.5 13 0.9 V 8.9 13 11 15 12 17 6.6 8 1.3 V 1.3 V 50°C 0°C 30°C 50°C 1.65 V 0.9 V 1.3 V 0°C 1.65 V 0.9 V ILPM3 fMCLK = fSMCLK = fACLK = 20 kHz CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 1.3 V 30°C 1.65 V 0.9 V 1.3 V fMCLK = fSMCLK = fACLK = 20 kHz CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 9 8.6 11 7.1 9 8.3 11 9.5 12 8.9 12 11 14 12 17 0.9 V 3.2 4.7 5.1 6.3 0°C 1.65 V 6.5 8 0.9 V 4 5.7 6 7.9 1.65 V 1.3 V 7.8 10 0.9 V 6 8.9 8.6 12 11 16 1.3 V 1.65 V Copyright © 2010, Texas Instruments Incorporated 50°C 7.6 1.65 V 1.3 V ILPM4 30 28 1.3 V ILPM2,20kHz MAX 26 1.65 V 1.3 V 0°C to 30°C TYP 30°C 50°C Submit Documentation Feedback UNIT µA µA µA µA 23 MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com Ports P1 and P2, RST/NMI/SVMOUT over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS VCC – 0.25 VCC = 1.65 V, IOH = –1 mA (1) for ports P1, P2 VCC – 0.15 VCC = 0.9 V, IOH = –300 µA (1) for ports P1, P2 VCC – 0.15 VIH VHYS Δt/Δv 0.2 (2) UNIT V 0.15 for ports P1, P2 V 0.07 VCC = 1.65 V 0.3 × VCC VCC = 0.9 V 0.25 × VCC VCC = 1.65 V 0.7 × VCC VCC = 0.9 V 0.75 × VCC Intrinsic hysteresis mV VCC = 0.9 V, CL = 15 pF || RL = 750 Ω to VSS on VOH for ports P1, P2 75 VCC = 0.9 V, CL = 15 pF || RL = 320 Ω to VCC on VOL for ports P1, P2 75 VCC = 1.65 V, CL = 25 pF || RL = 1600 Ω to VSS on VOH for ports P1, P2 75 VCC = 1.65 V, CL = 25 pF || RL = 600 Ω to VSS on VOL for ports P1, P2 75 VCC = 0.9 V to 1.65 V for ports P1, P2 –1 VCC = 0.9 V to 1.65 V for ports P1, P2 2.5 ILKG VCC = 0.9 V to 1.65 V (at 50°C) tINT P0.x, VCC = 0.9 V to 1.65 V RPULL For pullup: VIN = VSS, For pulldown: VIN = VCC for ports P1, P2 30 RRST Pullup on RST/NMI/SVMOUT 30 REXT External pullup resistor on RST terminal (optional) CI VIN = VSS or VCC V V 150 IOL 24 MAX VCC = 1.65 V, IOL = 2.5 mA (2) for ports P1, P2 IOH (1) (2) TYP VCC = 0.9 V, IOL = 2.5 mA (2) for ports P1, P2 VCC = 0.9 V, IOL = 300 µA VIL MIN VCC = 0.9 V, IOH = –1 mA (1) for ports P1, P2 ns/V mA mA ±100 nA 35 40 kΩ 35 40 kΩ 200 ns 680 kΩ 7 pF The maximum total current IOH, for all outputs combined should not exceed 5 mA to hold the maximum voltage drop specified. The maximum total current IOL, for all outputs combined should not exceed 15 mA to hold the maximum voltage drop specified. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 Typical Characteristics – Outputs TYPICAL LOW-LEVEL OUTPUT VOLTAGE vs OUTPUT CURRENT TYPICAL HIGH-LEVEL OUTPUT VOLTAGE vs OUTPUT CURRENT 0 VCC = 0.9 V IOH – Typical High-Level Output Current – mA IOL – Typical Low-Level Output Current – mA 3 0°C, 30°C, 50°C 2.5 2 1.5 1 0.5 0.05 VOL – Low-Level Output Voltage – V 0.1 -0.4 -0.6 -0.8 -1 0°C, 30°C, 50°C 0.85 0.875 VOH – High-Level Output Voltage – V Figure 4. Figure 5. TYPICAL LOW-LEVEL OUTPUT VOLTAGE vs OUTPUT CURRENT TYPICAL HIGH-LEVEL OUTPUT VOLTAGE vs OUTPUT CURRENT 0.9 0 VCC = 1.65 V IOH – Typical High-Level Output Current – mA 3 IOL – Typical Low-Level Output Current – mA -0.2 -1.2 0.825 0 0 VCC = 0.9 V 0°C, 30°C, 50°C 2.5 2 1.5 1 0.5 VCC = 1.65 V -0.2 -0.4 -0.6 -0.8 -1 0°C, 30°C, 50°C -1.2 0 0 0.01 0.02 0.03 0.04 VOL – Low-Level Output Voltage – V Figure 6. Copyright © 2010, Texas Instruments Incorporated 0.05 1.6 1.61 1.62 1.63 1.64 VOH – High-Level Output Voltage – V 1.65 Figure 7. Submit Documentation Feedback 25 MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com Typical Characteristics – Outputs (continued) TYPICAL LOW-LEVEL OUTPUT VOLTAGE vs LARGE SIGNAL OUTPUT CURRENT TYPICAL HIGH-LEVEL OUTPUT VOLTAGE vs LARGE SIGNAL OUTPUT CURRENT 0 IOH – Typical High-Level Output Current – mA IOL – Typical Low-Level Output Current – mA 16 VCC = 1.65 V 14 12 10 30°C 8 6 4 2 0 VCC = 1.65 V -2 -4 -6 30°C -8 -10 -12 -14 -16 0 0.05 0.1 0.15 0.2 0.25 0.8 VOL – Low-Level Output Voltage – V Figure 8. Figure 9. TYPICAL LOW-LEVEL INPUT VOLTAGE vs SUPPLY VOLTAGE TYPICAL LOW-LEVEL INPUT VOLTAGE vs SUPPLY VOLTAGE 0.6 0.55 0.5 0.45 0.4 50°C 30°C 0°C 0°C 30°C 50°C 0.75 0.7 0.65 0.6 0.55 0.5 0.3 0.8 1 1.2 1.4 VCC – Supply Voltage – V Figure 10. 26 1.8 0.8 VIH – Typical High-Level Input Voltage – V VIL – Typical Low-Level Input Voltage – V 0.65 0.35 1 1.2 1.4 1.6 VOH – High-Level Output Voltage – V Submit Documentation Feedback 1.6 1.8 0.8 1 1.2 1.4 1.6 1.8 VCC – Supply Voltage – V Figure 11. Copyright © 2010, Texas Instruments Incorporated MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 High-Frequency Oscillator over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) MIN TYP MAX UNIT fHFOSC PARAMETER VCC = 0.9 V to 1.65 V (minimum trim range via register) 0.75 1 1.25 MHz fHFOSC VCC = 0.9 V to 1.65 V (trimmed at 30°C) 0.92 1 1.08 MHz Duty cycle VCC = 0.9 V to 1.65 V 45 50 55 % tSTART VCC = 0.9 V to 1.65 V 20 µs ΔfHFOSC/DT VCC = 0.9 V to 1.65 V, fHFOSC = 1 MHz ΔfHFOSC/ΔVCC VCC = 1.0 V to 1.65 V, fHFOSC = 1 MHz ΔfHFOSC/ΔVCC VCC = 0.90 V to 1.0 V, fHFOSC = 1 MHz ΔfHFOSC/CALSTEP (1) VCC = 0.9 V to 1.65 V, fHFOSC = 1 MHz, ±64 calibration steps IOSC VCC = 0.9 V to 1.65 V, fHFOSC = 1 MHz (1) TEST CONDITIONS ±0.07 ±0.15 %/°C ±1 %/V ±1 ±2.5 %/V 1 4 %/ Step 0.1 22 µA Normalized to typical frequency Typical Characteristics – High-Frequency Oscillator FREQUENCY vs TRIM SETTING 2500 Frequency – kHz VCC = 1.3 V 2000 1500 1000 500 0 16 32 48 64 80 Value in CCSCTL2 Register 96 112 128 Figure 12. FREQUENCY vs TEMPERATURE Frequency / Frequency30°C 1.02 1.01 VCC 0.9 V 1 1.3 V 1.65 V 0.99 0.98 0 10 20 30 TA – Temperature – °C 40 50 Figure 13. Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 27 MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com Low-Frequency Oscillator over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) MIN TYP MAX fLFOSC PARAMETER VCC = 0.9 V to 1.65 V TEST CONDITIONS 6 20 45 Duty cycle VCC = 0.9 V to 1.65 V 45 50 tSTART VCC = 0.9 V to 1.65 V IOSC VCC = 0.9 V to 1.65 V, fLFOSC = 20 kHz UNIT kHz 55 % 500 µs 0.6 µA Typical Characteristics – Low-Frequency Oscillator FREQUENCY vs TEMPERATURE 40.0 VCC Frequency – kHz 0.9 V 30.0 1.0 V 1.3 V 1.65 V 20.0 10.0 0 10 20 30 40 TA – Temperature – °C 50 60 Figure 14. Brown-Out Reset (BOR) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VBOR(Start) MIN V(BOR_IT+) VCC rising, ΔVCC/Δt < 3 V/s 1095 V(BOR_IT–) VCC falling, ΔVCC/Δt < 3 V/s 860 Vhys(BOR) VMARGIN (2) 28 MAX VMARGIN = V(BOR-IT–) – VCRIT, (VCRIT < 820 mV) (1) UNIT mV 1150 mV 900 mV 200 mV 40 mV 3000 (2 td(BOR) (1) TYP 490 ) µs VCRIT is a temperature depending voltage where the single components of the device become unreliable (the 'L092 provides a safety margin to ensure overall device function). Strongly depends on voltage ramp in system (actually a maximum typical value). Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 A-POOL, External Reference Source over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VCC = 0.9 V to 1.65 V, ADC / DAC operational VREF VCC = 0.9 V to 1.65 V, ADC / DAC not operational IREF(Input) VCC = 0.9 V to 1.65 V, load to external sinks CREF REFON = 0 TYP 100 0 MAX UNIT 275 mV VCC 3 20 V µA 50 pF A-POOL, Built-In Reference Source over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX VREF VCC = 0.9 V to 1.65 V (±1.5%, overall 3%) IREF VCC = 0.9 V to 1.65 V CREF REFON = 1 TREF VCC = 0.9 V to 1.65 V (ΔV/ΔT × VREF referenced to 25°C) ±250 tSETTLE VCC = 0.9 V to 1.65 V, REFON = 1, CREF = CREF(max) (1) 900 (1) µs IREF(Output) VCC = 0.9 V to 1.65 V, REFON = 1, CREF = CREF(max) 2 µA (1) 256 UNIT mV 10 20 µA 50 pF ppm/ °C As the actual on reference enable signal is synchronized with the LF oscillator. Typical Characteristics – A-POOL Built-In Reference Source VOLTAGE vs TEMPERATURE VREF – Reference Voltage (TYP = 256 mV) 258 257 256 VCC 1.65 V 1.3 V 255 1.0 V 0.9 V 254 0 10 20 30 40 TA – Temperature – °C 50 60 Figure 15. Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 29 MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com A-POOL, Temperature Sensor over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP ISENSOR VCC = 0.9 V to 1.65 V TCSENSOR VCC = 0.9 V to 1.65 V, TA = 0°C to 50°C (ΔV/ΔT referenced to 30°C) 464 VOFFSET25 VCC = 0.9 V to 1.65 V at TA = 30°C 179 tSETTLE VCC = 0.9 V to 1.65 V (before start of conversion) VSENSOR (1) VCC = 0.9 V to 1.65 V, TA = 0°C to 50°C (1) MAX 2 UNIT µA µV/°C mV 15 179 µs mV This formula can be used to calculate the temperature sensor output voltage: VSENSOR = VOFFSET25 + TCSENSOR × (TA – 30°C). A-POOL, Input Voltage Dividers over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER ΔRx/Rx TEST CONDITIONS MIN Any Rx in dividers ΔIVCC MAX ±1.5 Any Rx across switches and internal supply voltage divider (by 4, by 8) On A0/A1 , VA0/VA1 = 0.5V, ADIV0/ADIV1 = 1 (500-mV range) RIN TYP % ±2 120 200 300 On A2/A3 , VA2/VA3 = 0.5V, ADIV2/ADIV4 = 1 (1-V range) 80 133 190 On A2/A3 , VA2/VA3 = 0.5V, ADIV2+ADIV3/ADIV4+ADIV5 = 1 (2-V range) 70 114 150 ADIV7 = 1 (supply voltage divider on) UNIT 2 kΩ µA A-POOL, DAC-8 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VREF TEST CONDITIONS MIN VCC = 0.9 V to 1.65 V MAX 256 On ±1 LSB steps (6t), VCC = 0.9 V to 1.65 V, external VREF tSETTLE TYP mV 2 Between all codes > 20 on AOUT (6t), VCC = 0.9 V to 1.65 V, external VREF UNIT µs 14 EI VCC = 0.9 V to 1.65 V, external VREF, add ±7 mV for VOUT offset (1) for codes > 7 ±3 LSB ED VCC = 0.9 V to 1.65 V, external VREF, add ±7 mV for VOUT offset (1) for codes > 7 ±1 LSB MAX UNIT 275 mV (1) This offset can be compensated using software. A-POOL, Comparator over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VIN TEST CONDITIONS MIN VCC = 0.9 V to 1.65 V tpd TYP 0 Overdrive = 20 mV 0.5 Overdrive = 5 mV 0.5 Overdrive = 1 mV 1 µs A-POOL, AOUT Terminal over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER | ILOAD | tSETTLE 30 TEST CONDITIONS VCC = 0.9 V to 1.65 V, CLOAD = 25 pF MIN VOUT > 50 mV (accuracy ±1% of VOUT) 5 VOUT > 20 mV (accuracy ±1% of VOUT) 2 MAX UNIT µA VCC = 0.9 V to 1.65 V, CLOAD = 25 pF, ± 1% (6t) (for AOUT 20 to 256 mV) Submit Documentation Feedback TYP 4 µs Copyright © 2010, Texas Instruments Incorporated MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 A-POOL, ADC-8 Counter over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fCNT VCC = 0.9 V to 1.65 V tCONV Full conversion (all codes), fCNT = 1 MHz MIN TYP MAX UNIT 1 MHz 256 µs RAM over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TEST CONDITIONS MIN VOP PARAMETER Operating temperature 0°C to 70°C, fCPU = 1MHz 900 mV VRET Operating temperature 0°C to 70°C (tracks BOL level) 700 mV Copyright © 2010, Texas Instruments Incorporated TYP MAX Submit Documentation Feedback UNIT 31 MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com PORT SCHEMATICS Port P1, P1.0 Input/Output Pad Logic to Clock System to A-Pool PSELx=y # NSELx=y P1REN.x P1DIR.x Vss Vcc 00 01 10 11 0 1 PortsOn P1OUT.x TA 0.2 TA 1.2 SMCLK 00 01 10 11 P1.0/TA0.2/TA1.2/ACLK/CCI0.1/A2/CLKIN P1SEL 0.x P1SEL 1.x P1IN.x # EN1 EN2 Module X IN D P1IES.x Set Q P1IFG.x P1IE.x P1IRQ.x Table 12. Port P1 (P1.0) Pin Functions CONTROL BITS/SIGNALS (1) PIN NAME (P1.x) x FUNCTION P1.0 (I/O) P1.0/TA0.2/TA1.2/ACLK/ CCI0.1/A2/CLKIN (1) 32 0 P1DIR.x P1SEL1.x P1SEL0.x RSELx/ASE Lx I:0, O:1 0 0 0 Timer_A0.2 1 0 1 0 Timer_A1.2 1 1 0 0 ACLK 1 1 1 0 Timer A0, CCI1B 0 ≠0 ≠0 X A2 X X X 2 CLKIN (via Bypass) X X X X X = Don't care Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 Port P1, P1.1 and P1.4 Input/Output Pad Logic to A-Pool PSELx=y # NSELx=y P1REN.x P1DIR.x Vss Vcc 00 01 10 11 0 1 PortsOn P1OUT.x TA 0.2 TA 1.2 from Module 00 01 10 11 P1.1/TA0.2/TA1.2/SMCLK/CCI1.1/A1/TA0CLK P1.4/TA0.2/TA1.2/MCLK/A0/TA1CLK P1SEL 0.x P1SEL 1.x P1IN.x # EN1 EN2 Module X IN D P1IES.x Set Q P1IRQ.x Copyright © 2010, Texas Instruments Incorporated P1IFG.x P1IE.x Submit Documentation Feedback 33 MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com Table 13. Port P1 (P1.1, P1.4) Pin Functions CONTROL BITS/SIGNALS (1) PIN NAME (P1.x) x FUNCTION P1.1 (I/O) P1.1/TA0.2/TA1.2/SMCLK/ CCI1.1/A1/TA0CLK 1 (1) 34 P1SEL0.x RSELx/ASE Lx I:0, O:1 0 0 0 1 0 1 0 Timer_A1.2 1 1 0 0 0 SMCLK 1 1 1 A1 X X X 1 TimerA0 CLK X ≠0 ≠0 X 0 ≠0 ≠0 X I:0, O:1 0 0 0 Timer_A0.2 1 0 1 0 Timer_A1.2 1 1 0 0 0 P1.4 (I/O) 4 P1SEL1.x Timer_A0.2 Timer A1, CCI1B P1.4/TA0.2/TA1.2/MCLK/ A0/TA1CLK P1DIR.x MCLK 1 1 1 A0 X X X 0 TimerA1 CLK 0 ≠0 ≠0 X X = Don't care Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 Port P1, P1.2 and P1.3 Input/Output Pad Logic to A-Pool PSELx=y # NSELx=y from A -Pool from A -Pool P1REN .x P1DIR.x Vss Vcc 00 01 10 11 0 1 PortsOn P1OUT .x TA 0.2 TA 1.2 from Module 00 01 10 11 P1.2/TA0.2/TA1.2/ACLK/CCI0.0/AOUT/A3 P1.3/TA0.2/TA1.2/CxOUT/CCI1.0/VREF/A3 P1SEL0.x P1SEL1.x P1IN.x # EN1 EN2 Module X IN D P1IES.x Set Q P1IRQ.x P1IFG .x P1IE.x Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 35 MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com Table 14. Port P1 (P1.2, P1.3) Pin Functions CONTROL BITS/SIGNALS (1) PIN NAME (P1.x) x FUNCTION P1.2 (I/O) P1.2/TA0.2/TA1.2/ACLK/ CCI0.0/AOUT/A3 2 36 RSELx/ASE Lx Analog Out 0 0 0 0 1 0 1 0 0 Timer_A1.2 1 1 0 0 0 ACLK 1 1 1 0 0 Timer A0, CCI0B 0 ≠0 ≠0 X X A3 X X X 3 X (2) X X X X 1 I:0, O:1 0 0 0 0 Timer_A0.2 1 0 1 0 0 Timer_A1.2 1 1 0 0 0 CxOUT 1 1 1 0 0 Timer A1, CCI0B 0 ≠0 ≠0 X X A3 X X X 3 X X X X X 1 VREF (1) (2) P1SEL0.x I:0, O:1 P1.3 (I/O) 3 P1SEL1.x Timer_A0.2 AOUT P1.3/TA0.2/TA1.2/CxOUT/ CCI1.0//VREF/A3 P1DIR.x (2) X = Don't care An analog output enable overrides the digital output control. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 Port P1, P1.5 and P1.6 Input/Output Pad Logic P1REN.x P1DIR.x Vss Vcc 00 01 10 11 0 1 PortsOn P1OUT.x TA 0.2 TA 1.2 Module X OUT 00 01 10 11 P1.5/TA 0.2/TA1.2/TA0.1 P1.6/TA 0.2/TA1.2/TA1.1 P1SEL0.x P1SEL1.x P1IN.x # EN1 EN2 Module X IN D P1IES.x Set Q P1IFG.x P1IE.x P1IRQ.x Table 15. Port P1 (P1.5, P1.6) Pin Functions PIN NAME (P1.x) x FUNCTION P1DIR.x P1SEL1.x P1SEL0.x I:0, O:1 0 0 Timer_A0.2 1 0 1 Timer_A1.2 1 1 0 Timer A0.1 1 1 1 Timer_A0.CCI1A 0 ≠0 ≠0 P1.5 (I/O) P1.5/TA0.2/TA1.2/TA0.1 5 P1.6 (I/O) P1.6/TA0.2/TA1.2/TA1.1 (1) 6 CONTROL BITS/SIGNALS (1) I:0, O:1 0 0 Timer_A0.2 1 0 1 Timer_A1.2 1 1 0 Timer A1.1 1 1 1 Timer_A1.CCI1A 0 ≠0 ≠0 X = Don't care Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 37 MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com Port P2, P2.0 to P2.2, Input/Output Pad Logic P2REN.x P2DIR.x Vss Vcc 00 01 10 11 0 1 PortsOn P2OUT.x TA 0.2 TA 1.2 Module X OUT 00 01 10 11 TCK/P2.0/TA0.2/TA1.2/TA 1.1 TMS/P2.1/TA0.2/TA 1.2/TA0.1 TDI/P2.2/TA0.2/TA 1.2/CxOUT/CCI0.0 P2SEL0.x P2SEL1.x P2IN.x to JTAG from JTAG # EN1 EN2 Module X IN D P2IES.x Set Q P2IRQ.x 38 Submit Documentation Feedback P2IFG.x P2IE.x Copyright © 2010, Texas Instruments Incorporated MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 Table 16. Port P2 (P2.0 to P2.2) Pin Functions PIN NAME (P2.x) x FUNCTION P2.0 (I/O) TCK/P2.0/TA0.2/ TA1.2/TA1.1 0 1 2 P2SEL0.x JTAG Mode 0 0 0 1 0 1 0 Timer_A1.2 1 1 0 0 Timer_A1.1 1 1 1 0 Timer_A0.CCI2A and Timer_A1.CCI2A 0 ≠0 ≠0 0 JTAG-TCK (2) (3) (4) X X X 1 I:0, O:1 0 0 0 Timer_A0.2 1 0 1 0 Timer_A1.2 1 1 0 0 Timer_A0.1 1 1 1 0 Timer_A0.CCI2B and Timer_A1.CCI2B 0 ≠0 ≠0 0 JTAG-TMS (2) (3) (4) X X X 1 I:0, O:1 0 0 0 Timer_A0.2 1 0 1 0 Timer_A1.2 1 1 0 0 CxOUT 1 1 1 0 Timer_A0.CCI0A 0 ≠0 ≠0 0 (2) (3) (4) X X X 1 JTAG-TDI (1) (2) (3) (4) P2SEL1.x I:0, O:1 P2.2 (I/O) TDI/P2.2/TA0.2/TA1.2/ CxOUT/CCI0.0 P2DIR.x Timer_A0.2 P2.1 (I/O) TMS/P2.1/TA0.2/ TA1.2/TA0.1 CONTROL BITS/SIGNALS (1) X = Don't care JTAG signals TMS,TCK and TDI read as "1" when nor configured as explicit JTAG terminals JTAG overrides digital output control when configured as explicit JTAG terminals JTAG function with enabled pullup resistors is default after power up Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 39 MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com Port P2, P2.3, Input/Output Pad Logic P2REN.x P2DIR.x Vss Vcc 00 01 10 11 from JTAG 0 1 PortsOn P2OUT.x TA 0.2 TA 1.2 TDO from JTAG 00 01 10 11 TDO/P2.3/TA0.2/TA 1.2/CCI1.0 P2SEL0.x P2SEL1.x P2IN.x to JTAG # EN1 EN2 Module X IN D P2IES.x Set Q P2IFG.x P2IE.x P2IRQ.x Table 17. Port P2 (P2.3) Pin Functions PIN NAME (P2.x) x FUNCTION P2DIR.x P2SEL1.x P2SEL0.x I:0, O:1 0 0 Timer_A0.2 1 0 1 Timer_A1.2 1 1 0 JTAG-TDO(2)(3) 1 1 1 Timer_A1.CCI0A 0 ≠0 ≠0 P2.0 (I/O) TDO/P2.0/TA0.2/TA1.2/ CCI1.0 (1) 40 3 CONTROL BITS/SIGNALS (1) X = Don't care Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) MSP430L092SPW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 50 L092S MSP430L092SPWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 50 L092S (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of