MSP4301103IPWR

Product Folder Order Now Tools & Software Technical Documents Support & Community Reference Design MSP430AFE253, MSP430AFE252, MSP430AFE251 MSP430AFE233, MSP430AFE232, MSP430AFE231 MSP430AFE223, MSP430AFE222, MSP430AFE221 SLAS701B – NOVEMBER 2010 – REVISED JUNE 2018 MSP430AFE2x3, MSP430AFE2x2, MSP430AFE2x1 Mixed-Signal Microcontrollers 1 Device Overview 1.1 Features 1 • Low Supply Voltage Range: 1.8 V to 3.6 V • Ultra-Low Power Consumption – Active Mode: 220 µA at 1 MHz, 2.2 V – Standby Mode: 0.5 µA – Off Mode (RAM Retention): 0.1 µA • Five Power-Saving Modes • Ultra-Fast Wake-up From Standby Mode in Less Than 1 µs • 16-Bit RISC Architecture, up to 12-MHz System Clock • Basic Clock Module Configurations – Internal Frequencies up to 12 MHz With Two Calibrated Frequencies – Internal Very-Low-Power Low-Frequency (LF) Oscillator – High-Frequency (HF) Crystal up to 16 MHz – Resonator – External Digital Clock Source 1.2 • • Applications Single-Phase Electricity Meters Digital Power Monitoring 1.3 • Up to Three 24-Bit Sigma-Delta Analog-to-Digital Converters (ADCs) With Differential PGA Inputs • 16-Bit Timer_A With Three Capture/Compare Registers • Serial Communication Interface (USART), Asynchronous UART or Synchronous SPI Selectable by Software • 16-Bit Hardware Multiplier • Brownout Detector • Supply Voltage Supervisor and Monitor With Programmable Level Detection • Serial Onboard Programming, No External Programming Voltage Needed Programmable Code Protection by Security Fuse • On-Chip Emulation Module • Device Comparison Summarizes the Available Family Members • For Complete Module Descriptions, See the MSP430x2xx Family User's Guide • Sensor Applications Description The TI MSP family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from low-power modes to active mode in less than 1 µs. The MSP430AFE2x3 devices are ultra-low-power mixed signal microcontrollers integrating three independent 24-bit sigma-delta ADCs, one 16-bit timer, one 16-bit hardware multiplier, USART communication interface, watchdog timer, and 11 I/O pins. The MSP430AFE2x2 devices are identical to the MSP430AFE2x3, except that there are only two 24-bit sigma-delta ADCs integrated. The MSP430AFE2x1 devices are identical to the MSP430AFE2x3, except that there is only one 24-bit sigma-delta ADC integrated. Device Information (1) PART NUMBER MSP430AFE253IPW (1) PACKAGE BODY SIZE TSSOP (24) 7.8 mm × 4.4 mm For more information, see Section 8, Mechanical Packaging and Orderable Information. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. MSP430AFE253, MSP430AFE252, MSP430AFE251 MSP430AFE233, MSP430AFE232, MSP430AFE231 MSP430AFE223, MSP430AFE222, MSP430AFE221 SLAS701B – NOVEMBER 2010 – REVISED JUNE 2018 1.4 www.ti.com Functional Block Diagram Figure 1-1 shows the functional block diagram. XT2IN XT2OUT DVCC DVSS AVCC AVSS ACLK Basic Clock System+ SMCLK MCLK 12-MHz CPU MAB WIth 16 Registers MDB P1.x 8 Hardware Multiplier (16x16) 16KB 8KB 4KB 512B 512B 256B Flash RAM BOR Watchdog WDT+ SD24_A (WIthout BUF) 15 or 16 Bit 3 Converters 2 Converters 1 Converter MPY, MPYS, MAC, MACS P2.x 3 Port P1 Port P2 8 I/Os, Interrupt capability, Pullup or pulldown resistors 3 I/Os, Interrupt capability, Pullup or pulldown resistors Timer_A3 USART0 3 CC Registers UART or SPI Function Emulation 2BP JTAG Interface Spy-BiWire SVS and SVM RST/NMI Figure 1-1. Functional Block Diagram 2 Device Overview Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430AFE253 MSP430AFE252 MSP430AFE251 MSP430AFE233 MSP430AFE232 MSP430AFE231 MSP430AFE223 MSP430AFE222 MSP430AFE221 MSP430AFE253, MSP430AFE252, MSP430AFE251 MSP430AFE233, MSP430AFE232, MSP430AFE231 MSP430AFE223, MSP430AFE222, MSP430AFE221 www.ti.com SLAS701B – NOVEMBER 2010 – REVISED JUNE 2018 Table of Contents 1 2 3 Device Overview ......................................... 1 5.26 SD24_A, Input Range ............................... 23 1.1 Features .............................................. 1 1.2 Applications ........................................... 1 5.27 5.28 1.3 Description ............................................ 1 SD24_A, Performance .............................. 24 SD24_A, Temperature Sensor and Built-In VCC Sense................................................ 24 1.4 Functional Block Diagram ............................ 2 5.29 SD24_A, Built-In Voltage Reference ................ 24 Revision History ......................................... 4 Device Comparison ..................................... 5 5.30 SD24_A, Reference Output Buffer .................. 25 5.31 SD24_A, External Reference Input Related Products ..................................... 5 5.32 USART0 ............................................. 25 Terminal Configuration and Functions .............. 6 5.33 Timer_A3 ............................................ 25 Pin Diagrams ......................................... 6 5.34 Flash Memory ....................................... 26 Signal Descriptions ................................... 7 5.35 RAM ................................................. 26 ............................................ Absolute Maximum Ratings .......................... ESD Ratings .......................................... Recommended Operating Conditions ............... 9 5.36 JTAG and Spy-Bi-Wire Interface .................... 27 9 5.37 JTAG Fuse .......................................... 27 3.1 4 4.1 4.2 5 Specifications 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 Thermal Resistance Characteristics for PW-24 Package ............................................. Active Mode Supply Current (Into DVCC and AVCC) Excluding External Current ................. Typical Characteristics – Active-Mode Supply Current (Into DVCC and AVCC) .................... Low-Power-Mode Supply Currents (Into VCC) Excluding External Current.......................... ............ Schmitt-Trigger Inputs (Ports Px and RST/NMI) ... Leakage Current (Ports Px) ......................... Outputs (Ports Px) .................................. Output Frequency (Ports Px) ....................... Typical Characteristics – Outputs ................... POR, BOR .......................................... Typical Characteristics – POR, BOR ............... Typical Characteristics – LPM4 Current 9 Instruction Set ....................................... 29 6.3 Operating Modes .................................... 30 6.4 Interrupt Vector Addresses.......................... 31 6.5 Special Function Registers.......................... 32 6.6 Memory Organization ............................... 34 6.7 Flash Memory ....................................... 34 12 6.8 Peripherals 12 6.9 Oscillator and System Clock ........................ 35 13 6.10 Brownout, Supply Voltage Supervisor 13 6.11 Digital I/O ............................................ 35 13 6.12 Watchdog Timer (WDT+) 13 6.13 Timer_A3 ............................................ 36 14 6.14 USART0 ............................................. 36 10 11 11 DCO Frequency ..................................... 19 5.19 5.20 Calibrated DCO Frequencies – Tolerance .......... Wake-up Times From Lower-Power Modes (LPM3, LPM4) .............................................. Typical Characteristics – DCO Clock Wake-up Time ................................................. Internal Very-Low-Power Low-Frequency Oscillator (VLO) ............................................... 20 ............................. Typical Characteristics – XT2 Oscillator ............ SD24_A, Power Supply ............................. 21 5.24 5.25 Crystal Oscillator (XT2) 19 7 20 20 21 22 23 8 .......................................... .............. ........................... ................................. 6.16 SD24_A ............................................. 6.17 Peripheral File Map ................................. 6.18 I/O Port Schematics ................................. Device and Documentation Support ............... 7.1 Getting Started ...................................... 7.2 Device Nomenclature ............................... 7.3 Tools and Software ................................. 7.4 Documentation Support ............................. 7.5 Related Links ........................................ 7.6 Community Resources .............................. 7.7 Trademarks.......................................... 7.8 Electrostatic Discharge Caution ..................... 7.9 Glossary ............................................. 6.15 15 Main DCO Characteristics 5.23 ................................................. CPU 5.18 5.22 Detailed Description ................................... 28 6.2 16 Supply Voltage Supervisor (SVS), Supply Voltage Monitor (SVM) ...................................... 17 .......................... Hardware Multiplier 28 35 35 36 36 37 37 39 48 48 48 50 51 52 52 52 53 53 Mechanical, Packaging, and Orderable Information .............................................. 54 Table of Contents Submit Documentation Feedback Product Folder Links: MSP430AFE253 MSP430AFE252 MSP430AFE251 MSP430AFE233 MSP430AFE232 MSP430AFE231 MSP430AFE223 MSP430AFE222 MSP430AFE221 Copyright © 2010–2018, Texas Instruments Incorporated 25 6.1 9 5.17 5.21 6 ................. 3 MSP430AFE253, MSP430AFE252, MSP430AFE251 MSP430AFE233, MSP430AFE232, MSP430AFE231 MSP430AFE223, MSP430AFE222, MSP430AFE221 SLAS701B – NOVEMBER 2010 – REVISED JUNE 2018 www.ti.com 2 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from March 21, 2011 to June 11, 2018 • • • • • • • • • • 4 Page Format changes throughout document, including addition of section numbering ........................................... 1 Added Section 1.2, Applications .................................................................................................... 1 Added Section 1.4, Functional Block Diagram, and moved functional block diagram to it ................................. 2 Added Section 3.1, Related Products .............................................................................................. 5 Added Section 5, Specifications, and moved all electrical specifications to it ................................................ 9 Added Section 5.2, ESD Ratings ................................................................................................... 9 Added Section 5.4, Thermal Resistance Characteristics ...................................................................... 10 Removed figure Oscillation Allowance vs Crystal Frequency ................................................................. 22 Added Section 7, Device and Documentation Support......................................................................... 48 Added Section 8, Mechanical Packaging and Orderable Information ........................................................ 54 Revision History Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430AFE253 MSP430AFE252 MSP430AFE251 MSP430AFE233 MSP430AFE232 MSP430AFE231 MSP430AFE223 MSP430AFE222 MSP430AFE221 MSP430AFE253, MSP430AFE252, MSP430AFE251 MSP430AFE233, MSP430AFE232, MSP430AFE231 MSP430AFE223, MSP430AFE222, MSP430AFE221 www.ti.com SLAS701B – NOVEMBER 2010 – REVISED JUNE 2018 3 Device Comparison Table 3-1 summarizes the available family members. Table 3-1. Device Comparison (1) DEVICE FLASH (KB) SRAM (Byte) EEM SD24_A CONVERTERS 16-BIT MPY Timer_A (2) USART (UART, SPI) CLOCKS I/O PACKAGE MSP430AFE253IPW 16 512 1 3 1 3 1 HF, DCO, VLO 11 24-TSSOP MSP430AFE233IPW 8 512 1 3 1 3 1 HF, DCO, VLO 11 24-TSSOP MSP430AFE223IPW 4 256 1 3 1 3 1 HF, DCO, VLO 11 24-TSSOP MSP430AFE252IPW 16 512 1 2 1 3 1 HF, DCO, VLO 11 24-TSSOP MSP430AFE232IPW 8 512 1 2 1 3 1 HF, DCO, VLO 11 24-TSSOP MSP430AFE222IPW 4 256 1 2 1 3 1 HF, DCO, VLO 11 24-TSSOP MSP430AFE251IPW 16 512 1 1 1 3 1 HF, DCO, VLO 11 24-TSSOP MSP430AFE231IPW 8 512 1 1 1 3 1 HF, DCO, VLO 11 24-TSSOP MSP430AFE221IPW 4 256 1 1 1 3 1 HF, DCO, VLO 11 24-TSSOP (1) (2) 3.1 For the most current package and ordering information, see the Package Option Addendum in Section 8, or see the TI website at www.ti.com. Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively. Related Products For information about other devices in this family of products or related products, see the following links. Products for MSP430 ultra-low-power sensing and measurement MCUs ecosystem. Endless possibilities. One platform. One Products for MSP430 ultra-low-power MCUs MCUs for metrology, monitoring, system control, and communications Companion Products for MSP430AFE253 Review products that are frequently purchased or used in conjunction with this product. Reference Designs for MSP430AFE253 TI reference designs leverage the best in TI technology – from analog and power management to embedded processors. All designs include a schematic, test data, and design files. Search and download designs at ti.com/tidesigns. Device Comparison Submit Documentation Feedback Product Folder Links: MSP430AFE253 MSP430AFE252 MSP430AFE251 MSP430AFE233 MSP430AFE232 MSP430AFE231 MSP430AFE223 MSP430AFE222 MSP430AFE221 Copyright © 2010–2018, Texas Instruments Incorporated 5 MSP430AFE253, MSP430AFE252, MSP430AFE251 MSP430AFE233, MSP430AFE232, MSP430AFE231 MSP430AFE223, MSP430AFE222, MSP430AFE221 SLAS701B – NOVEMBER 2010 – REVISED JUNE 2018 www.ti.com 4 Terminal Configuration and Functions 4.1 Pin Diagrams Figure 4-1 shows the pinout of the MSP430AFE2x3 devices in the 24-pin PW (TSSOP) package. A0.0+ 1 24 P2.0/STE0/TA0/TDI/TCLK A0.0- 2 23 P1.7/UCLK0/TA1/TDO/TDI A1.0+ 3 22 P1.6/SOMI0/TA2/TCK A1.0- 4 21 P1.5/SIMO0/SVSOUT/TMS AVCC 5 20 P1.4/URXD0/SD2DO AVSS 6 19 P1.3/UTXD0/SD1DO VREF 7 18 P1.2/TA0/SD0DO A2.0+ 8 17 P1.1/TA1/SDCLK A2.0- 9 16 DVCC MSP430AFE2x3 TEST/SBWTCK 10 15 P2.7/XT2OUT RST/NMI/SBWTDIO 11 14 P2.6/XT2IN P1.0/SVSIN/TACLK/SMCLK/TA2 12 13 DVSS Figure 4-1. 24-Pin PW Package (Top View), MSP430AFE2x3 Figure 4-2 shows the pinout of the MSP430AFE2x2 devices in the 24-pin PW (TSSOP) package. A0.0+ 1 24 P2.0/STE0/TA0/TDI/TCLK A0.0- 2 23 P1.7/UCLK0/TA1/TDO/TDI A1.0+ 3 22 P1.6/SOMI0/TA2/TCK A1.0- 4 21 P1.5/SIMO0/SVSOUT/TMS AVCC 5 20 P1.4/URXD0 AVSS 6 19 P1.3/UTXD0/SD1DO VREF 7 18 P1.2/TA0/SD0DO NC 8 17 P1.1/TA1/SDCLK NC 9 16 DVCC TEST/SBWTCK 10 15 P2.7/XT2OUT RST/NMI/SBWTDIO 11 14 P2.6/XT2IN P1.0/SVSIN/TACLK/SMCLK/TA2 12 13 DVSS MSP430AFE2x2 NOTE: Connect NC pins to analog ground (AVSS) Figure 4-2. 24-Pin PW Package (Top View), MSP430AFE2x2 6 Terminal Configuration and Functions Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430AFE253 MSP430AFE252 MSP430AFE251 MSP430AFE233 MSP430AFE232 MSP430AFE231 MSP430AFE223 MSP430AFE222 MSP430AFE221 MSP430AFE253, MSP430AFE252, MSP430AFE251 MSP430AFE233, MSP430AFE232, MSP430AFE231 MSP430AFE223, MSP430AFE222, MSP430AFE221 www.ti.com SLAS701B – NOVEMBER 2010 – REVISED JUNE 2018 Figure 4-3 shows the pinout of the MSP430AFE2x1 devices in the 24-pin PW (TSSOP) package. A0.0+ 1 24 P2.0/STE0/TA0/TDI/TCLK A0.0- 2 23 P1.7/UCLK0/TA1/TDO/TDI NC 3 22 P1.6/SOMI0/TA2/TCK NC 4 21 P1.5/SIMO0/SVSOUT/TMS AVCC 5 20 P1.4/URXD0 AVSS 6 19 P1.3/UTXD0 VREF 7 18 P1.2/TA0/SD0DO NC 8 17 P1.1/TA1/SDCLK NC 9 16 DVCC MSP430AFE2x1 TEST/SBWTCK 10 15 P2.7/XT2OUT RST/NMI/SBWTDIO 11 14 P2.6/XT2IN P1.0/SVSIN/TACLK/SMCLK/TA2 12 13 DVSS NOTE: Connect NC pins to analog ground (AVSS) Figure 4-3. 24-Pin PW Package (Top View), MSP430AFE2x1 4.2 Signal Descriptions Table 4-1 describes the signals for all device variants. Table 4-1. Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION A0.0+ 1 I SD24_A positive analog input A0.0 (1) A0.0- 2 I SD24_A negative analog input A0.0 (1) A1.0+ 3 I SD24_A positive analog input A1.0 (not available on MSP430AFE2x1) (1) A1.0- 4 I SD24_A negative analog input A1.0 (not available on MSP430AFE2x1) (1) AVCC 5 Analog supply voltage, positive terminal. Must not power up prior to DVCC. AVSS 6 Analog supply voltage, negative terminal VREF 7 I/O A2.0+ 8 I SD24_A positive analog input A2.0 (not available on MSP430AFE2x2 and MSP430AFE2x1) (1) A2.0- 9 I SD24_A negative analog input A2.0 (not available on MSP430AFE2x2 and MSP430AFE2x1) (1) TEST/SBWTCK 10 I Selects test mode for JTAG pins on P1.5 to P1.7 and P2.0. The device protection fuse is connected to TEST. Spy-Bi-Wire test clock input for device programming and test. RST/NMI/SBWTDIO 11 I Reset or nonmaskable interrupt input Spy-Bi-Wire test data input/output for device programming and test. General-purpose digital I/O pin Analog input to supply voltage supervisor Timer_A3, clock signal TACLK input SMCLK signal output Timer_A3, compare: Out2 Output P1.0/SVSIN/TACLK/SMCLK/TA2 12 DVSS 13 P2.6/XT2IN 14 I/O Input terminal of crystal oscillator General-purpose digital I/O pin P2.7/XT2OUT 15 I/O Output terminal of crystal oscillator General-purpose digital I/O pin (1) I/O Input for an external reference voltage output for internal reference voltage (can be used as mid-voltage) Digital supply voltage, negative terminal TI recommends shorting unused analog input pairs and connecting them to analog ground. Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430AFE253 MSP430AFE252 MSP430AFE251 MSP430AFE233 MSP430AFE232 MSP430AFE231 MSP430AFE223 MSP430AFE222 MSP430AFE221 Copyright © 2010–2018, Texas Instruments Incorporated 7 MSP430AFE253, MSP430AFE252, MSP430AFE251 MSP430AFE233, MSP430AFE232, MSP430AFE231 MSP430AFE223, MSP430AFE222, MSP430AFE221 SLAS701B – NOVEMBER 2010 – REVISED JUNE 2018 www.ti.com Table 4-1. Terminal Functions (continued) TERMINAL NAME NO. I/O DESCRIPTION DVCC 16 P1.1/TA1/SDCLK 17 I/O General-purpose digital I/O pin Timer_A3, capture: CCI1A and CCI1B inputs, compare: Out1 output SD24_A bit stream clock output P1.2/TA0/SD0DO 18 I/O General-purpose digital I/O pin Timer_A3, capture: CCI0A and CCI0B inputs, compare: Out0 output SD24_A bit stream data output for channel 0 P1.3/UTXD0/SD1DO 19 I/O General-purpose digital I/O pin Transmit data out - USART0 in UART mode SD24_A bit stream data output for channel 1 (not available on MSP430AFE2x1) I/O General-purpose digital I/O pin Receive data in - USART0 in UART mode SD24_A bit stream data output for channel 2 (not available on MSP430AFE2x2 and MSP430AFE2x1) P1.4/URXD0/SD2DO 20 Digital supply voltage, positive terminal. P1.5/SIMO0/SVSOUT/TMS 21 I/O General-purpose digital I/O Slave in/master out of USART0 in SPI mode SVS: output of SVS comparator JTAG test mode select. TMS is used as an input port for device programming and test. P1.6/SOMI0/TA2/TCK 22 I/O General-purpose digital I/O pin Slave out/master in of USART0 in SPI mode Timer_A3, compare: Out2 output JTAG test clock. TCK is the clock input port for device programming and test. I/O General-purpose digital I/O pin External clock input - USART0 in UART or SPI mode, clock output - USART0/SPI mode. Timer_A3, compare: Out1 output JTAG test data output port. TDO/TDI data output or programming data input terminal. I/O General-purpose digital I/O pin Slave transmit enable - USART0 in SPI mode. Timer_A3, compare: Out0 output JTAG test data input or test clock input for device programming and test. P1.7/UCLK0/TA1/TDO/TDI P2.0/STE0/TA0/TDI/TCLK 8 23 24 Terminal Configuration and Functions Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430AFE253 MSP430AFE252 MSP430AFE251 MSP430AFE233 MSP430AFE232 MSP430AFE231 MSP430AFE223 MSP430AFE222 MSP430AFE221 MSP430AFE253, MSP430AFE252, MSP430AFE251 MSP430AFE233, MSP430AFE232, MSP430AFE231 MSP430AFE223, MSP430AFE222, MSP430AFE221 www.ti.com SLAS701B – NOVEMBER 2010 – REVISED JUNE 2018 5 Specifications Absolute Maximum Ratings (1) 5.1 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) MIN MAX –0.3 4.1 –0.3 VCC + 0.3 –2 2 Unprogrammed device –55 150 Programmed device –40 85 Voltage applied at VCC to VSS Voltage applied to any pin (2) Diode current at any device terminal Storage temperature, Tstg (1) (2) V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±1000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±250 UNIT V Recommended Operating Conditions (1) (2) MIN VCC Supply voltage VSS Supply voltage TA Operating free-air temperature fSYSTEM Processor frequency (maximum MCLK frequency) (1) (2) (see Figure 5-1) (2) (3) °C JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±1000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V may actually have higher performance. 5.3 (1) V mA ESD Ratings VALUE (2) V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TEST pin when blowing the JTAG fuse. 5.2 (1) UNIT AVCC = DVCC = VCC (1) NOM MAX During program execution (3) 1.8 3.6 During program or erase of flash memory 2.2 3.6 UNIT V AVSS = DVSS = VSS 0 V –40 85 VCC = 1.8 V, Duty cycle = 50% ±10% dc 4.15 VCC = 2.7 V, Duty cycle = 50% ±10% dc 9 VCC ≥ 3.3 V, Duty cycle = 50% ±10% dc 12 °C MHz The MSP430 CPU is clocked directly with MCLK. Both the high and low phases of MCLK must not exceed the pulse duration of the specified maximum frequency. Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet. The operating voltage range for SD24_A is 2.5 V to 3.6 V Specifications Submit Documentation Feedback Product Folder Links: MSP430AFE253 MSP430AFE252 MSP430AFE251 MSP430AFE233 MSP430AFE232 MSP430AFE231 MSP430AFE223 MSP430AFE222 MSP430AFE221 Copyright © 2010–2018, Texas Instruments Incorporated 9 MSP430AFE253, MSP430AFE252, MSP430AFE251 MSP430AFE233, MSP430AFE232, MSP430AFE231 MSP430AFE223, MSP430AFE222, MSP430AFE221 SLAS701B – NOVEMBER 2010 – REVISED JUNE 2018 www.ti.com Legend : System Frequency −MHz 12 MHz Supply voltage range during flash memory programming 9 MHz Supply voltage range during program execution 6.5 MHz 4.15 MHz 1.8 V 2.2 V 2.7 V 3.3 V 3.6 V Supply Voltage − V A. B. Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V. If high frequency crystal used is above 12 MHz and selected to source CPU clock then MCLK divider should be programmed appropriately to run CPU below 8 MHz. Figure 5-1. Operating Area 5.4 Thermal Resistance Characteristics for PW-24 Package THERMAL METRIC (1) (2) VALUE (3) UNIT RθJA Junction-to-ambient thermal resistance, still air 76.4 °C/W RθJC(TOP) Junction-to-case (top) thermal resistance 21.1 °C/W RθJC(BOT) Junction-to-case (bottom) thermal resistance 31.7 °C/W RθJB Junction-to-board thermal resistance 31.1 °C/W ΨJB Junction-to-board thermal characterization parameter 1.0 °C/W ΨJT Junction-to-top thermal characterization parameter N/A °C/W (1) (2) (3) 10 For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics. These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RθJC] value, which is based on a JEDEC-defined 1S0P system) and will change based on environment and application. For more information, see these EIA/JEDEC standards: • JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air) • JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages • JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages • JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements N/A = Not applicable Specifications Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430AFE253 MSP430AFE252 MSP430AFE251 MSP430AFE233 MSP430AFE232 MSP430AFE231 MSP430AFE223 MSP430AFE222 MSP430AFE221 MSP430AFE253, MSP430AFE252, MSP430AFE251 MSP430AFE233, MSP430AFE232, MSP430AFE231 MSP430AFE223, MSP430AFE222, MSP430AFE221 www.ti.com SLAS701B – NOVEMBER 2010 – REVISED JUNE 2018 Active Mode Supply Current (Into DVCC and AVCC) Excluding External Current (1) 5.5 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER IAM, IAM, (1) TEST CONDITIONS VCC 1MHz Active mode (AM) current at 1 MHz fDCO = fMCLK = fSMCLK = DCO default frequency (approximately 1 MHz), fACLK = fVLO = 12 kHz, Program executes in flash, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 12MHz Active mode (AM) current at 12 MHz fDCO = fMCLK = fSMCLK = 12 MHz, fACLK = fVLO = 12 kHz, Program executes in flash, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 MIN TYP 2.2 V 220 3V 350 3.3 V 4.0 MAX UNIT µA 4.5 mA All inputs are tied to 0 V or VCC. Outputs do not source or sink any current. 5.6 Typical Characteristics – Active-Mode Supply Current (Into DVCC and AVCC) 4 5 fDCO = 12 MHz 3.5 4 Active Mode Supply Current - mA Active Mode Supply Current - mA 4.5 3.5 fDCO = 8 MHz 3 2.5 2 1.5 1 fDCO = 1 MHz 0.5 VCC = 3 V, TA = 85°C 3 VCC = 3 V, TA = 25°C 2.5 VCC = 2.2 V, TA = 85°C 2 1.5 1 VCC = 2.2 V, TA = 25°C 0.5 0 0 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 4 6 8 10 fDCO - DCO Frequency - MHz Figure 5-3. Active-Mode Current vs DCO Frequency 12 Specifications Submit Documentation Feedback Product Folder Links: MSP430AFE253 MSP430AFE252 MSP430AFE251 MSP430AFE233 MSP430AFE232 MSP430AFE231 MSP430AFE223 MSP430AFE222 MSP430AFE221 11 VCC - Supply Voltage - V Figure 5-2. Active-Mode Current vs VCC, TA = 25°C Copyright © 2010–2018, Texas Instruments Incorporated 0 2 MSP430AFE253, MSP430AFE252, MSP430AFE251 MSP430AFE233, MSP430AFE232, MSP430AFE231 MSP430AFE223, MSP430AFE222, MSP430AFE221 SLAS701B – NOVEMBER 2010 – REVISED JUNE 2018 www.ti.com Low-Power-Mode Supply Currents (Into VCC) Excluding External Current (1) 5.7 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TA VCC Low-power mode 0 (LPM0) current (2) fMCLK = 0 MHz, fSMCLK = fDCO = DCO default frequency (approximately 1 MHz), fACLK = fVLO = 12 kHz, CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 25°C 2.2 V 65 µA ILPM2 Low-power mode 2 (LPM2) current (3) fMCLK = fSMCLK = 0 MHz, fDCO = DCO default frequency (approximately 1 MHz), fACLK = fVLO = 12 kHz, CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 25°C 2.2 V 22 µA ILPM3,VLO Low-power mode 3 (LPM3) current (3) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = fVLO = 12 kHz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 25°C 2.2 V 0.5 1.0 0.7 Low-power mode 4 (LPM4) current (4) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = fVLO = 0 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 0.1 ILPM4 1.1 2.5 ILPM0 (1) (2) (3) (4) 5.8 TEST CONDITIONS MIN 25°C 2.2 V 85°C TYP MAX UNIT µA µA All inputs are tied to 0 V or VCC. Outputs do not source or sink any current. Current for brownout and WDT clocked by SMCLK included. Current for brownout and WDT clocked by ACLK included. Current for brownout included. Typical Characteristics – LPM4 Current 6.0 VCC = 3.6 V VCC = 3 V ILPM4 - Low-power Mode Current - µA 5.0 VCC = 2.2 V VCC = 1.8 V 4.0 3.0 2.0 1.0 0.0 -40 -20 0 20 40 60 80 100 120 TA - Temperature - °C Figure 5-4. ILPM4 -- LPM4 Current vs Temperature 12 Specifications Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430AFE253 MSP430AFE252 MSP430AFE251 MSP430AFE233 MSP430AFE232 MSP430AFE231 MSP430AFE223 MSP430AFE222 MSP430AFE221 MSP430AFE253, MSP430AFE252, MSP430AFE251 MSP430AFE233, MSP430AFE232, MSP430AFE231 MSP430AFE223, MSP430AFE222, MSP430AFE221 www.ti.com 5.9 SLAS701B – NOVEMBER 2010 – REVISED JUNE 2018 Schmitt-Trigger Inputs (Ports Px and RST/NMI) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VIT+ Positive-going input threshold voltage VIT- Negative-going input threshold voltage Vhys Input voltage hysteresis (VIT+ – VIT–) RPull Pullup or pulldown resistor (not RST/NMI pin) For pullup: VIN = VSS, For pulldown: VIN = VCC CI Input capacitance VIN = VSS or VCC VCC MIN TYP MAX 0.45 VCC 0.75 VCC 1.35 2.25 3V UNIT V 0.25 VCC 0.55 VCC 3V 0.75 1.65 3V 0.3 1.0 V 3V 20 50 kΩ 35 V 5 pF 5.10 Leakage Current (Ports Px) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER Ilkg(Px.y) (1) (2) TEST CONDITIONS High-impedance leakage current See VCC (1) (2) MIN 3V MAX UNIT ±50 nA The leakage current is measured with VSS or VCC applied to the corresponding pin, unless otherwise noted. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is disabled. 5.11 Outputs (Ports Px) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS (1) VOH High-level output voltage IOH(max) = –6 mA VOL Low-level output voltage IOL(max) = 6 mA (1) (1) VCC MIN TYP MAX UNIT 3V VCC – 0.2 V 3V VSS + 0.2 V The maximum total current (IOH(max) and IOL(max)) for all outputs combined cannot exceed ±48 mA to hold the maximum voltage drop specified. 5.12 Output Frequency (Ports Px) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT fPx.y Port output frequency (with load) Px.y, CL = 20 pF, RL = 1 kΩ (1) (2) 3V 12 MHz fPort_CLK Clock output frequency Px.y, CL = 20 pF (2) 3V 16 MHz (1) (2) A resistive divider with two 0.5-kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap of the divider. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency. Specifications Submit Documentation Feedback Product Folder Links: MSP430AFE253 MSP430AFE252 MSP430AFE251 MSP430AFE233 MSP430AFE232 MSP430AFE231 MSP430AFE223 MSP430AFE222 MSP430AFE221 Copyright © 2010–2018, Texas Instruments Incorporated 13 MSP430AFE253, MSP430AFE252, MSP430AFE251 MSP430AFE233, MSP430AFE232, MSP430AFE231 MSP430AFE223, MSP430AFE222, MSP430AFE221 SLAS701B – NOVEMBER 2010 – REVISED JUNE 2018 www.ti.com 5.13 Typical Characteristics – Outputs One output loaded at a time. 50.0 VCC = 2.2 V P1.0 TA = 25°C 20.0 I OL − Typical Low-Level Output Current − mA I OL − Typical Low-Level Output Current − mA 25.0 TA = 85°C 15.0 10.0 5.0 0.0 0.0 0.5 1.0 1.5 2.0 I OH − Typical High-Level Output Current − mA I OH − Typical High-Level Output Current − mA 30.0 20.0 10.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.0 VCC = 2.2 V P1.0 −5.0 −10.0 −15.0 TA = 85°C TA = 25°C −25.0 0.0 0.5 1.0 1.5 2.0 2.5 VOH − High-Level Output V oltage − V Figure 5-7. Typical High-Level Output Current vs High-Level Output Voltage 14 TA = 85°C VOL − Low-Level Output V oltage − V Figure 5-6. Typical Low-Level Output Current vs Low-Level Output Voltage 0.0 −20.0 TA = 25°C 40.0 0.0 0.0 2.5 VOL − Low-Level Output V oltage − V Figure 5-5. Typical Low-Level Output Current vs Low-Level Output Voltage VCC = 3 V P1.0 Specifications VCC = 3 V P1.0 −10.0 −20.0 −30.0 −40.0 −50.0 0.0 TA = 85°C TA = 25°C 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOH − High-Level Output V oltage − V Figure 5-8. Typical High-Level Output Current vs High-Level Output Voltage Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430AFE253 MSP430AFE252 MSP430AFE251 MSP430AFE233 MSP430AFE232 MSP430AFE231 MSP430AFE223 MSP430AFE222 MSP430AFE221 MSP430AFE253, MSP430AFE252, MSP430AFE251 MSP430AFE233, MSP430AFE232, MSP430AFE231 MSP430AFE223, MSP430AFE222, MSP430AFE221 www.ti.com SLAS701B – NOVEMBER 2010 – REVISED JUNE 2018 5.14 POR, BOR (1) (2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VCC(start) See Figure 5-9 dVCC/dt ≤ 3 V/s 0.7 × V(B_IT-) V(B_IT-) See Figure 5-9 through Figure 5-11 dVCC/dt ≤ 3 V/s 1.42 V Vhys(B_IT-) See Figure 5-9 dVCC/dt ≤ 3 V/s 120 mV td(BOR) See Figure 5-9 2000 µs t(reset) Pulse duration needed at RST/NMI pin to accepted reset internally (1) (2) 3V 2 V µs The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT-) + Vhys(B_IT- ) is ≤ 1.8 V. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT-) + Vhys(B_IT-). The default DCO settings must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency. VCC Vhys(B_IT−) V(B_IT−) VCC(start) 1 0 t d(BOR) Figure 5-9. POR, BOR vs Supply Voltage Specifications Submit Documentation Feedback Product Folder Links: MSP430AFE253 MSP430AFE252 MSP430AFE251 MSP430AFE233 MSP430AFE232 MSP430AFE231 MSP430AFE223 MSP430AFE222 MSP430AFE221 Copyright © 2010–2018, Texas Instruments Incorporated 15 MSP430AFE253, MSP430AFE252, MSP430AFE251 MSP430AFE233, MSP430AFE232, MSP430AFE231 MSP430AFE223, MSP430AFE222, MSP430AFE221 SLAS701B – NOVEMBER 2010 – REVISED JUNE 2018 www.ti.com 5.15 Typical Characteristics – POR, BOR VCC 3V 2 VCC(drop) − V VCC = 3 V Typical Conditions t pw 1.5 1 VCC(drop) 0.5 0 0.001 1 1000 1 ns t pw − Pulse Width − µs 1 ns t pw − Pulse Width − µs Figure 5-10. VCC(drop) Level With a Square Voltage Drop to Generate a POR or BOR Signal VCC 2 t pw 3V VCC(drop) − V VCC = 3 V 1.5 Typical Conditions 1 VCC(drop) 0.5 0 0.001 tf = tr 1 t pw − Pulse Width − µs 1000 tf tr t pw − Pulse Width − µs Figure 5-11. VCC(drop) Level With a Triangular Voltage Drop to Generate a POR or BOR Signal 16 Specifications Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430AFE253 MSP430AFE252 MSP430AFE251 MSP430AFE233 MSP430AFE232 MSP430AFE231 MSP430AFE223 MSP430AFE222 MSP430AFE221 MSP430AFE253, MSP430AFE252, MSP430AFE251 MSP430AFE233, MSP430AFE232, MSP430AFE231 MSP430AFE223, MSP430AFE222, MSP430AFE221 www.ti.com SLAS701B – NOVEMBER 2010 – REVISED JUNE 2018 5.16 Supply Voltage Supervisor (SVS), Supply Voltage Monitor (SVM) (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER t(SVSR) TEST CONDITIONS MIN dVCC/dt > 30 V/ms (see Figure 5-12) SVS on, switch from VLD = 0 to VLD ≠ 0, VCC =3 V tsettle VLD ≠ 0 (2) V(SVSstart) VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 5-12) VCC/dt ≤ 3 V/s (see Figure 5-12) Vhys(SVS_IT-) VCC/dt ≤ 3 V/s (see Figure 5-12), external voltage applied on SVSIN 15 VLD = 15 10 1.8 2.1 VLD = 3 2.2 2.5 VLD = 7 2.65 VLD = 8 2.8 2.69 (3) 2.9 3.2 VLD = 12 3.35 VLD = 15 V mV 2.05 2.6 V 3.13 3.05 VLD = 11 3.24 3.5 3.76 (3) 3.7 (3) VLD = 14 (1) (2) 2.4 VLD = 6 VLD = 13 1.7 2.3 2.24 VLD = 10 VLD ≠ 0, VCC = 3 V 1.9 VLD = 2 VLD = 9 ICC(SVS) (1) µs VLD = 2 to 14 VLD = 5 VCC/dt ≤ 3 V/s (see Figure 5-12), external voltage applied on SVSIN µs 12 120 VLD = 4 VCC/dt ≤ 3V/s (see Figure 5-12) 100 1.55 VLD = 1 UNIT µs 2000 VLD = 1 V(SVS_IT-) MAX 100 dVCC/dt ≤ 30 V/ms td(SVSon) TYP 1.1 1.2 1.3 12 17 µA The current consumption of the SVS module is not included in the ICC current consumption data. tsettle is the settling time that the comparator operational amplifier needs to have a stable level after VLD is switched from VLD ≠ 0 to a different VLD value between 2 and 15. The overdrive is assumed to be greater than 50 mV. The recommended operating voltage range is limited to 3.6 V. Specifications Submit Documentation Feedback Product Folder Links: MSP430AFE253 MSP430AFE252 MSP430AFE251 MSP430AFE233 MSP430AFE232 MSP430AFE231 MSP430AFE223 MSP430AFE222 MSP430AFE221 Copyright © 2010–2018, Texas Instruments Incorporated 17 MSP430AFE253, MSP430AFE252, MSP430AFE251 MSP430AFE233, MSP430AFE232, MSP430AFE231 MSP430AFE223, MSP430AFE222, MSP430AFE221 SLAS701B – NOVEMBER 2010 – REVISED JUNE 2018 www.ti.com Software sets VLD > 0: SVS is active AVCC Vhys(SVS_IT-- ) V(SVS_IT-- ) V(SVSstart) Vhys(B_IT-- ) V(B_IT-- ) VCC(start) Brownout Region Brownout Region Brownout 1 0 SVS out t d(BOR) SVS CircuitisActiveFromVLD>toV 1 0 td(SVSon) Set POR 1 CC td(BOR) < V(B_IT-- ) td(SVSR) undefined 0 Figure 5-12. SVS Reset (SVSR) vs Supply Voltage VCC 3V t pw 2 Rectangular Drop VCC(min) VCC(min) -- V 1.5 Triangular Drop 1 1 ns 1ns VCC 3V 0.5 t pw 0 1 10 100 1000 tpw – Pulse Width – µs VCC(min) tf = tr tf tr t – Pulse Width – µs Figure 5-13. VCC(min) With a Square Voltage Drop and a Triangular Voltage Drop to Generate an SVS Signal 5.17 Main DCO Characteristics 18 Specifications Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430AFE253 MSP430AFE252 MSP430AFE251 MSP430AFE233 MSP430AFE232 MSP430AFE231 MSP430AFE223 MSP430AFE222 MSP430AFE221 MSP430AFE253, MSP430AFE252, MSP430AFE251 MSP430AFE233, MSP430AFE232, MSP430AFE231 MSP430AFE223, MSP430AFE222, MSP430AFE221 www.ti.com • • • SLAS701B – NOVEMBER 2010 – REVISED JUNE 2018 All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15. DCO control bits DCOx have a step size as defined by parameter SDCO. Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to: faverage = 32 × fDCO(RSEL,DCO) × fDCO(RSEL,DCO+1) MOD × fDCO(RSEL,DCO) + (32 – MOD) × fDCO(RSEL,DCO+1) 5.18 DCO Frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX RSELx < 14 1.8 3.6 RSELx = 14 2.2 3.6 UNIT VCC Supply voltage range fDCO(0,0) DCO frequency (0, 0) RSELx = 0, DCOx = 0, MODx = 0 3.3 V fDCO(0,3) DCO frequency (0, 3) RSELx = 0, DCOx = 3, MODx = 0 3.3 V 0.12 MHz fDCO(1,3) DCO frequency (1, 3) RSELx = 1, DCOx = 3, MODx = 0 3.3 V 0.15 MHz fDCO(2,3) DCO frequency (2, 3) RSELx = 2, DCOx = 3, MODx = 0 3.3 V 0.21 MHz fDCO(3,3) DCO frequency (3, 3) RSELx = 3, DCOx = 3, MODx = 0 3.3 V 0.30 MHz fDCO(4,3) DCO frequency (4, 3) RSELx = 4, DCOx = 3, MODx = 0 3.3 V 0.41 MHz fDCO(5,3) DCO frequency (5, 3) RSELx = 5, DCOx = 3, MODx = 0 3.3 V 0.58 MHz fDCO(6,3) DCO frequency (6, 3) RSELx = 6, DCOx = 3, MODx = 0 3.3 V 0.80 MHz fDCO(7,3) DCO frequency (7, 3) RSELx = 7, DCOx = 3, MODx = 0 3.3 V 1.15 MHz fDCO(8,3) DCO frequency (8, 3) RSELx = 8, DCOx = 3, MODx = 0 3.3 V 1.60 MHz fDCO(9,3) DCO frequency (9, 3) RSELx = 9, DCOx = 3, MODx = 0 3.3 V 2.30 MHz fDCO(10,3) DCO frequency (10, 3) RSELx = 10, DCOx = 3, MODx = 0 3.3 V 3.40 MHz fDCO(11,3) DCO frequency (11, 3) RSELx = 11, DCOx = 3, MODx = 0 3.3 V 4.25 MHz fDCO(12,3) DCO frequency (12, 3) RSELx = 12, DCOx = 3, MODx = 0 3.3 V 5.80 M Hz fDCO(13,3) DCO frequency (13, 3) RSELx = 13, DCOx = 3, MODx = 0 3.3 V 7.80 fDCO(14,3) DCO frequency (14, 3) RSELx = 14, DCOx = 3, MODx = 0 3.3 V fDCO(15,3) DCO frequency (15, 3) RSELx = 15, DCOx = 3, MODx = 0 3.3 V 15.30 MHz fDCO(15,7) DCO frequency (15, 7) RSELx = 15, DCOx = 7, MODx = 0 3.3 V 21.00 MHz SRSEL Frequency step between range RSEL and RSEL+1 SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO) 3.3 V 1.35 ratio SDCO Frequency step between tap DCO and DCO+1 SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO) 3.3 V 1.08 ratio Duty cycle Measured at SMCLK output 3.3 V 50 RSELx = 15 3.0 0.06 8.6 3.6 0.10 11.25 0.14 MHz MHz 13.9 Specifications Submit Documentation Feedback Product Folder Links: MSP430AFE253 MSP430AFE252 MSP430AFE251 MSP430AFE233 MSP430AFE232 MSP430AFE231 MSP430AFE223 MSP430AFE222 MSP430AFE221 Copyright © 2010–2018, Texas Instruments Incorporated V MHz % 19 MSP430AFE253, MSP430AFE252, MSP430AFE251 MSP430AFE233, MSP430AFE232, MSP430AFE231 MSP430AFE223, MSP430AFE222, MSP430AFE221 SLAS701B – NOVEMBER 2010 – REVISED JUNE 2018 www.ti.com 5.19 Calibrated DCO Frequencies – Tolerance over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX UNIT 8-MHz tolerance over temperature (1) BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, calibrated at 30°C and 3.3 V 0°C to 85°C 3.3 V 7.76 8 8.24 MHz 8-MHz tolerance over VCC BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, calibrated at 30°C and 3.3 V 30°C 2.7 V to 3.6 V 7.76 8 8.24 MHz 8-MHz tolerance overall BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, calibrated at 30°C and 3.3 V –40°C to 85°C 2.7 V to 3.6 V 7.52 8 8.48 MHz 12-MHz tolerance over temperature (1) BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, calibrated at 30°C and 3.3 V 0°C to 85°C 3.3 V 11.64 12 12.36 MHz 12-MHz tolerance over VCC BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, calibrated at 30°C and 3.3 V 30°C 3.3 V to 3.6 V 11.64 12 12.36 MHz 12-MHz tolerance overall BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, calibrated at 30°C and 3.3 V –40°C to 85°C 3.3 V to 3.6 V 11.28 12 12.72 MHz TYP MAX UNIT (1) This is the frequency change from the measured frequency at 30°C over temperature. 5.20 Wake-up Times From Lower-Power Modes (LPM3, LPM4) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC tDCO,LPM3/4 DCO clock wake-up time from LPM3 fDCO = DCO default frequency or LPM4 (1) (approximately 1 MHz) tCPU,LPM3/4 CPU wake-up time from LPM3 or LPM4 (2) (1) (2) 3V MIN 1.5 µs 1 / fMCLK + tDCO,LPM3/4 µs The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, a port interrupt) to the first clock edge observable externally on a clock pin (MCLK or SMCLK). Parameter applicable only if DCOCLK is used for MCLK. 5.21 Typical Characteristics – DCO Clock Wake-up Time DCO Wake Time − us 10.00 RSELx = 0...11 RSELx = 12...15 1.00 0.10 0.10 1.00 10.00 DCO Frequency − MHz Figure 5-14. Clock Wake-up Time From LPM3 vs DCO Frequency 20 Specifications Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430AFE253 MSP430AFE252 MSP430AFE251 MSP430AFE233 MSP430AFE232 MSP430AFE231 MSP430AFE223 MSP430AFE222 MSP430AFE221 MSP430AFE253, MSP430AFE252, MSP430AFE251 MSP430AFE233, MSP430AFE232, MSP430AFE231 MSP430AFE223, MSP430AFE222, MSP430AFE221 www.ti.com SLAS701B – NOVEMBER 2010 – REVISED JUNE 2018 5.22 Internal Very-Low-Power Low-Frequency Oscillator (VLO) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TA VCC MIN 4 fVLO VLO frequency –40°C to 85°C 3V dfVLO/dT VLO frequency temperature drift (1) –40°C to 85°C 3V dfVLO/dVCC VLO frequency supply voltage drift (2) 25°C 1.8 V to 3.6 V (1) (2) TYP MAX 12 22 UNIT kHz 0.5 %/°C 4 %/V Calculated using the box method: [MAX(–40°C to 85°C) – MIN(–40°C to 85°C)] / MIN(–40°C to 85°C) / [85°C – (–40°C)] Calculated using the box method: [MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)] / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V) 5.23 Crystal Oscillator (XT2) (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN XT2OFF = 0, XT2Sx = 0 1.8 V to 3.6 V XT2 oscillator crystal frequency, HF mode 1 XT2OFF = 0, XT2Sx = 1 XT2 oscillator crystal frequency, HF mode 2 XT2OFF = 0, XT2Sx = 2 fXT2,HF0 XT2 oscillator crystal frequency, HF mode 0 fXT2,HF1 fXT2,HF2 fXT2,HF,logic OAHF CL,eff XT2 oscillator logic-level square-wave input frequency, HF mode Oscillation allowance for HF crystals (see Figure 5-15) Integrated effective load capacitance, HF mode (2) (1) (2) (3) (4) (5) Oscillator fault frequency MAX UNIT 0.4 1 MHz 1.8 V to 3.6 V 1 4 MHz 1.8 V to 2.2 V 2 10 2.2 V to 3.0 V 2 12 3.0 V to 3.6 V 2 16 1.8 V to 2.2 V 0.4 10 2.2 V to 3.0 V 0.4 12 3.0 V to 3.6 V 0.4 16 XT2OFF = 0, XT2Sx = 0 fXT2,HF = 1 MHz, CL,eff = 15 pF 2700 XT2OFF = 0, XT2Sx = 1 fXT2,HF = 4 MHz, CL,eff = 15 pF 800 XT2OFF = 0, XT2Sx = 2 fXT2,HF = 16 MHz, CL,eff = 15 pF 300 XT2OFF = 0 (3) XT2OFF = 0, Measured at P1.0/SVSIN/TACLK/SMCLK/TA2, fXT2,HF = 10 MHz Duty cycle fFault,HF XT2OFF = 0, XT2Sx = 3 XT2OFF = 0, Measured at P1.0/SVSIN/TACLK/SMCLK/TA2, fXT2,HF = 16 MHz (4) TYP XT2OFF = 0, XT2Sx = 3 (5) 50 pF 60 3V % 40 3V MHz Ω 1 40 MHz 30 50 60 300 kHz To improve EMI on the XT2 oscillator, observe the following guidelines: • Keep the trace between the device and the crystal as short as possible. • Design a good ground plane around the oscillator pins. • Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT. • Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins. • Use assembly materials and processes that avoid any parasitic load on the oscillator XT2IN and XT2OUT pins. • If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins. Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal. Requires external capacitors at both terminals. Values are specified by crystal manufacturers. Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and frequencies in between might set the flag. Measured with logic-level input frequency, but also applies to operation with crystals. Specifications Submit Documentation Feedback Product Folder Links: MSP430AFE253 MSP430AFE252 MSP430AFE251 MSP430AFE233 MSP430AFE232 MSP430AFE231 MSP430AFE223 MSP430AFE222 MSP430AFE221 Copyright © 2010–2018, Texas Instruments Incorporated 21 MSP430AFE253, MSP430AFE252, MSP430AFE251 MSP430AFE233, MSP430AFE232, MSP430AFE231 MSP430AFE223, MSP430AFE222, MSP430AFE221 SLAS701B – NOVEMBER 2010 – REVISED JUNE 2018 www.ti.com 5.24 Typical Characteristics – XT2 Oscillator 1800.0 LFXT1Sx = 2 XT Oscillator Supply Current − uA 1600.0 1400.0 1200.0 1000.0 800.0 600.0 400.0 LFXT1Sx = 1 200.0 0.0 0.0 LFXT1Sx = 0 4.0 8.0 12.0 16.0 20.0 Crystal Frequency − MHz TA = 25°C CL,eff = 15 pF Figure 5-15. XT2 Oscillator Supply Current vs Crystal Frequency 22 Specifications Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430AFE253 MSP430AFE252 MSP430AFE251 MSP430AFE233 MSP430AFE232 MSP430AFE231 MSP430AFE223 MSP430AFE222 MSP430AFE221 MSP430AFE253, MSP430AFE252, MSP430AFE251 MSP430AFE233, MSP430AFE232, MSP430AFE231 MSP430AFE223, MSP430AFE222, MSP430AFE221 www.ti.com SLAS701B – NOVEMBER 2010 – REVISED JUNE 2018 5.25 SD24_A, Power Supply over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER AVCC ISD24 fSD24 Analog supply voltage Analog supply current: 1 active SD24_A channel including internal reference Analog front-end input clock frequency TEST CONDITIONS VCC MIN AVCC = DVCC AVSS = DVSS = 0 V TYP 2.5 SD24LP = 0, fSD24 = 1 MHz, SD24OSR = 256 3.6 GAIN: 1, 2 800 GAIN: 4, 8, 16 900 GAIN: 32 SD24LP = 1, fSD24 = 0.5 MHz, SD24OSR = 256 3V 800 GAIN: 32 900 3V SD24LP = 1 (low-power mode enabled) 0.03 1 0.03 0.5 UNIT V 1100 1200 GAIN: 1 SD24LP = 0 (low-power mode disabled) MAX µA 1.1 MHz 5.26 SD24_A, Input Range (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VID,FSR VID Differential full-scale input voltage range Differential input voltage range for specified performance (2) TEST CONDITIONS VCC Bipolar mode, SD24UNI = 0 Unipolar mode, SD24UNI = 1 SD24REFON = 1 MIN TYP –VREF / 2GAIN +VREF / 2GAIN 0 +VREF / 2GAIN SD24GAINx = 1 ±500 SD24GAINx = 2 ±250 SD24GAINx = 4 ±125 SD24GAINx = 8 ±62 SD24GAINx = 16 ±31 SD24GAINx = 32 ±15 SD24GAINx = 1 MAX UNIT mV mV 200 ZI Input impedance (one input pin to AVSS) fSD24 = 1 MHz ZID Differential input impedance (IN+ to IN-) fSD24 = 1 MHz VI Absolute input voltage range AVSS – 1 AVCC V VIC Common-mode input voltage range AVSS – 1 AVCC V (1) (2) SD24GAINx = 32 SD24GAINx = 1 SD24GAINx = 32 3V 3V kΩ 75 300 400 100 150 kΩ All parameters pertain to each SD24_A channel. The full-scale range is defined by VFSR+ = +(VREF / 2) / GAIN and VFSR– = –(VREF / 2) / GAIN. If VREF is sourced externally, the analog input range cannot exceed 80% of VFSR+ or VFSR–; that is, VID = 0.8 × VFSR– to 0.8 × VFSR+. If VREF is sourced internally, the given VID ranges apply. Specifications Submit Documentation Feedback Product Folder Links: MSP430AFE253 MSP430AFE252 MSP430AFE251 MSP430AFE233 MSP430AFE232 MSP430AFE231 MSP430AFE223 MSP430AFE222 MSP430AFE221 Copyright © 2010–2018, Texas Instruments Incorporated 23 MSP430AFE253, MSP430AFE252, MSP430AFE251 MSP430AFE233, MSP430AFE232, MSP430AFE231 MSP430AFE223, MSP430AFE222, MSP430AFE221 SLAS701B – NOVEMBER 2010 – REVISED JUNE 2018 www.ti.com 5.27 SD24_A, Performance fSD24 = 1 MHz, SD24OSRx = 256, SD24REFON = 1, over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER G Nominal gain EOS Offset error ΔEOS/ΔT Offset error temperature coefficient CMRR Common-mode rejection ratio TEST CONDITIONS VCC MIN TYP SD24GAINx = 1 1 SD24GAINx = 2 1.96 SD24GAINx = 4 7.62 SD24GAINx = 16 15.04 SD24GAINx = 32 28.35 SD24GAINx = 1 ±0.2 3V SD24GAINx = 32 SD24GAINx = 1 ±1.5 3V SD24GAINx = 32 SD24GAINx = 1, Common-mode input signal: VID = 500 mV, fIN = 50 Hz or 100 Hz UNIT 3.86 3V SD24GAINx = 8 MAX ±4 ±20 ±20 ±100 %FSR ppm FSR/°C >90 SD24GAINx = 32, Common-mode input signal: VID = 16 mV, fIN = 50 Hz or 100 Hz 3V dB >75 AC PSRR AC power supply rejection ratio SD24GAINx = 1, VCC = 3 V ±100 mV, fVCC = 50 Hz 3V >80 dB XT Crosstalk SD24GAINx = 1, VID = 500 mV, fIN = 50 Hz or 100 Hz 3V