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MSP430F149, MSP430F148, MSP430F147
MSP430F1491, MSP430F1481, MSP430F1471
MSP430F135, MSP430F133
SLAS272H – JULY 2000 – REVISED MAY 2018
MSP430F14x, MSP430F14x1, MSP430F13x Mixed-Signal Microcontrollers
1 Device Overview
1.1
Features
1
• Low Supply Voltage Range, 1.8 V to 3.6 V
• Ultra-Low Power Consumption:
– Active Mode: 280 µA at 1 MHz, 2.2 V
– Standby Mode: 1.6 µA
– Off Mode (RAM Retention): 0.1 µA
• Five Power-Saving Modes
• Wakeup From Standby Mode in Less Than 6 µs
• 16-Bit RISC Architecture, 125-ns Instruction Cycle
Time
• 12-Bit Analog-to-Digital Converter (ADC) With
Internal Reference, Sample-and-Hold, and
Autoscan Feature
• 16-Bit Timer_B With Seven Capture/CompareWith-Shadow Registers
• 16-Bit Timer_A With Three Capture/Compare
Registers
• On-Chip Comparator
• Serial Onboard Programming, No External
Programming Voltage Needed, Programmable
Code Protection by Security Fuse
1.2
•
•
Applications
Sensor Systems
Industrial Controls
1.3
• Serial Communication Interface (USART),
Functions as Asynchronous UART or Synchronous
SPI Interface
– Two USARTs (USART0, USART1) On
MSP430F14x and MSP430F14x1 Devices
– One USART (USART0) On MSP430F13x
Devices
• Family Members (Also See Device Comparison)
– MSP430F133
– 8KB + 256 Bytes of Flash Memory,
256 Bytes of RAM
– MSP430F135
– 16KB + 256 Bytes of Flash Memory,
512 Bytes of RAM
– MSP430F147, MSP430F1471
– 32KB + 256 Bytes of Flash Memory,
1KB of RAM
– MSP430F148, MSP430F1481
– 48KB + 256 Bytes of Flash Memory,
2KB of RAM
– MSP430F149, MSP430F1491
– 60KB + 256 Bytes of Flash Memory,
2KB of RAM
•
Hand-Held Meters
Description
The Texas Instruments MSP430™ family of ultra-low-power microcontrollers (MCUs) consist of several
devices featuring different sets of peripherals targeted for various applications. The architecture, combined
with five low-power modes is optimized to achieve extended battery life in portable measurement
applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators
that attribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from
low-power modes to active mode in less than 6 µs.
The MSP430F13x, MSP430F14x, and MSP430F14x1 MCUs support two built-in 16-bit timers, a fast 12-bit
ADC on the MSP430F13x and the MSP430F14x devices, one USART on the MSP430F13x devices or
two USARTs on the MSP430F14x and MSP430F14x1 devices, and 48 I/O pins. The hardware multiplier
enhances the performance and offers a broad code and hardware-compatible family solution.
For complete module descriptions, see the MSP430x1xx Family User’s Guide.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430F149, MSP430F148, MSP430F147
MSP430F1491, MSP430F1481, MSP430F1471
MSP430F135, MSP430F133
SLAS272H – JULY 2000 – REVISED MAY 2018
www.ti.com
Device Information (1)
PACKAGE
BODY SIZE (2)
LQFP (64)
10 mm × 10 mm
MSP430F149IPAG
TQFP (64)
10 mm × 10 mm
MSP430F1491IRTD
VQFN (64)
9 mm × 9 mm
PART NUMBER
MSP430F149IPM
(1)
For the most current device, package, and ordering information, see the Package Option Addendum in Section 8, or see the TI website
at www.ti.com.
The sizes shown here are approximations. For the package dimensions with tolerances, see the Mechanical Data in Section 8.
(2)
1.4
Functional Block Diagrams
Figure 1-1 shows the functional block diagram for the MSP430F13x MCUs.
XIN
XOUT
DVCC
DVSS
AV CC
AV SS
P1
RST/NMI
P2
8
ROSC
Oscillator
XT2IN
System
Clock
XT2OUT
ACLK
16KB Flash
512B RAM
ADC12
SMCLK
8KB Flash
256B RAM
12-Bit
8 Channels
VVREF-/VeREF- (3)
VVeREF+ −
VVREF-/VeREF-
Differential external reference input voltage VVeREF+ > VVREF-/VeREF- (4)
IVeREF+
Static input current, VeREF+
0 V ≤ VVeREF+ ≤ VAVCC
IVREF-/VeREF-
Static input current, VeREF−
0 V ≤ VVeREF− ≤ VAVCC
(1)
(2)
(3)
(4)
VCC
(2)
MIN
MAX
1.4 VAVCC
0
UNIT
V
1.2
V
1.4 VAVCC
V
2.2 V, 3 V
±1
µA
2.2 V, 3 V
±1
µA
The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the
dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
The accuracy requirements limit the minimum positive external reference voltage. Lower reference voltage levels may be applied with
reduced accuracy requirements
The accuracy requirements limit the maximum negative external reference voltage. Higher reference voltage levels may be applied with
reduced accuracy requirements.
The accuracy requirements limit the minimum external differential reference voltage. Lower differential reference voltage levels may be
applied with reduced accuracy requirements.
Specifications
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27
MSP430F149, MSP430F148, MSP430F147
MSP430F1491, MSP430F1481, MSP430F1471
MSP430F135, MSP430F133
SLAS272H – JULY 2000 – REVISED MAY 2018
www.ti.com
5.25 12-Bit ADC, Built-In Reference
over recommended operating supply voltage and free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Positive built-in reference
voltage output
VREF+
AVCC(min)
VCC
MIN
TYP
MAX
REF2_5V = 1 for 2.5 V,
IVREF+ ≤ IVREF+(max)
3V
2.4
2.5
2.6
REF2_5V = 0 for 1.5 V,
IVREF+ ≤ IVREF+(max)
2.2 V, 3 V
1.44
1.5
1.56
V
REF2_5V = 0, IVREF+ ≤ 1 mA
AVCC minimum voltage,
positive built-in reference
active
IL(VREF)+
2.2
REF2_5V = 1, IVREF+ ≤ 0.5 mA
VREF+ + 0.15
REF2_5V = 1, IVREF+ ≤ 1 mA
VREF+ + 0.15
2.2 V
Load current out of VREF+
terminal
IVREF+
IVREF+ = 500 µA ±100 µA,
Analog input voltage ≈ 0.75 V,
REF2_5V = 0
Load-current regulation, VREF+
terminal (1)
IVREF+ = 500 µA ±100 µA,
Analog input voltage ≈ 1.25 V,
REF2_5V = 1
0.01
–0.5
mA
–1
2.2 V
±2
3V
±2
3V
±2
LSB
3V
20
ns
Load-current regulation,
VREF+ terminal (2)
IVREF+ = 100 µA to 90 µA,
CVREF+ = 5 µF, VAx ≈ 0 5 × VREF+,
Error of conversion result ≤ 1 LSB
CVREF+
Capacitance at VREF+
terminal (3)
REFON = 1,
0 mA ≤ IVREF+ ≤ IVREF+(max)
2.2 V, 3 V
TREF+
Temperature coefficient of
built-in reference (1)
IVREF+ is constant in the range of
0 mA ≤ IVREF+ ≤ 1 mA
2.2 V, 3 V
tREFON
Settling time of reference
voltage (4) (1) (see Figure 5-13)
IVREF+ = 0.5 mA, CVREF+ = 10 µF,
VVREF+ = 1.5 V, VAVCC = 2.2 V
(4)
V
3V
IDL(VREF)+
(1)
(2)
(3)
UNIT
5
LSB
10
µF
±100 ppm/°C
17
ms
Not production tested, limits characterized
Not production tested, limits verified by design
The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses two
capacitors between pins VREF+ and AVSS and VREF−/VeREF− and AVSS: 10-µF tantalum and 100-nF ceramic.
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load.
CVREF+, Capacitance at VREF+
100 µF
10 µF
tREFON ≈ 0.66 × CVREF+ [ms], with CVREF+ in µF
1 µF
0
1 ms
10 ms
100 ms
tREFON. Setting Time
Figure 5-13. Typical Settling Time of Internal Reference (tREFON) vs External Capacitor on VREF+
28
Specifications
Copyright © 2000–2018, Texas Instruments Incorporated
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MSP430F1491, MSP430F1481, MSP430F1471
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SLAS272H – JULY 2000 – REVISED MAY 2018
DVCC
From power supply
+
−
10 µF
100 nF
AVCC
+
−
10 µF
Apply external reference (VeREF+)
or use internal reference (VREF+)
100 nF
100 nF
Apply external reference
VREF−/VeREF−
+
−
10 µF
AVSS
VREF+ or VeREF+
+
−
10 µF
DVSS
100 nF
Figure 5-14. Supply Voltage and Reference Voltage Design, VREF−/VeREF− External Supply
DVCC
From power supply
+
−
10 µF
100 nF
AVCC
+
−
10 µF
Apply external reference (VeREF+)
or use internal reference (VREF+)
100 nF
AVSS
VREF+ or VeREF+
+
−
10 µF
Reference is internally
switched to AVSS
DVSS
100 nF
VREF−/VeREF−
Figure 5-15. Supply Voltage and Reference Voltage Design, VREF-/VeREF- = AVSS, Internally Connected
Specifications
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29
MSP430F149, MSP430F148, MSP430F147
MSP430F1491, MSP430F1481, MSP430F1471
MSP430F135, MSP430F133
SLAS272H – JULY 2000 – REVISED MAY 2018
www.ti.com
5.26 12-Bit ADC, Timing Parameters
over recommended operating supply voltage and free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
For specified performance of ADC12 linearity
parameters
fADC12CLK
ADC clock frequency
fADC12OSC
Internal ADC12 oscillator ADC12DIV = 0, fADC12CLK = fADC12OSC
CVREF+ ≥ 5 µF, internal oscillator,
fADC12OSC = 3.7 MHz to 6.3 MHz
tCONVERT
Conversion time
tADC12ON
Turn-on settling time of
the ADC (1)
See
tSample
Sampling time (1)
RS = 400 Ω, RI = 1000 Ω, CI = 30 pF,
τ = [RS + RI] × CI (3)
(1)
(2)
(3)
VCC
MIN
TYP
MAX
UNIT
2.2 V, 3 V
0.45
5
6.3
MHz
2.2 V, 3 V
3.7
6.3
MHz
2.2 V, 3 V
2.06
3.51
External fADC12CLK from ACLK, MCLK or
SMCLK, ADC12SSEL ≠ 0
µs
13 ×
1/fADC12CLK
(2)
100
3V
1220
2.2 V
1400
ns
ns
Not production tested, limits verified by design
The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signal are already
settled.
Approximately 10 Tau (τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) × (RS + RI) × CI + 800 ns, where n = ADC resolution = 12, RS = external source resistance
5.27 12-Bit ADC, Linearity Parameters
over recommended operating supply voltage and free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
EI
Integral
linearity error
1.4 V ≤ (VVeREF+ – VVREF-/VeREF-)min ≤ 1.6 V
ED
Differential
linearity error
(VVeREF+ – VVREF-/VeREF-)min ≤ (VVeREF+ – VVREF-/VeREF-),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
2.2 V, 3 V
EO
Offset error
(VVeREF+ – VVREF-/VeREF-)min ≤ (VVeREF+ – VVREF-/VeREF-),
Internal impedance of source RS < 100 Ω,
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
2.2 V, 3 V
EG
Gain error
(VVeREF+ – VVREF-/VeREF-)min ≤ (VVeREF+ – VVREF-/VeREF-),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
ET
Total unadjusted
error
(VVeREF+ – VVREF-/VeREF-)min ≤ (VVeREF+ – VVREF-/VeREF-),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
30
Specifications
1.6 V < (VVeREF+ – VVREF-/VeREF-)min ≤ VAVCC
MIN
TYP
MAX
±2
2.2 V, 3 V
±1.7
UNIT
LSB
±1
LSB
±2
±4
LSB
2.2 V, 3 V
±1.1
±2
LSB
2.2 V, 3 V
±2
±5
LSB
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MSP430F1491, MSP430F1481, MSP430F1471
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SLAS272H – JULY 2000 – REVISED MAY 2018
5.28 12-Bit ADC, Temperature Sensor and Built-In VMID
over recommended operating supply voltage and free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
ISENSOR
Operating supply current into REFON = 0, INCH = 0Ah,
AVCC terminal (1)
ADC12ON = N/A, TA = 25°C
2.2 V
40
120
3V
60
160
VSENSOR
Sensor output voltage (2)
ADC12ON = 1, INCH = 0Ah,
TA = 0°C
2.2 V
986
986 ±5%
3V
986
986 ±5%
TCSENSOR
Temperature coefficient of
sensor output voltage (2)
ADC12ON = 1, INCH = 0Ah
2.2 V
3.55
3.55 ±3%
3V
3.55
3.55 ±3%
tSENSOR(sample)
Sample time required if
channel 10 is selected (2) (3)
ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
IVMID
Current into divider at
channel 11 (4)
ADC12ON = 1, INCH = 0Bh
VMID
AVCC divider at channel 11
ADC12ON = 1, INCH = 0Bh,
VMID ≈ 0.5 × VAVCC
2.2 V
1.1
1.1 ±0.04
3V
1.5
1.5 ±0.04
tVMID(sample)
Sample time required if
channel 11 is selected (6)
ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
2.2 V
1400
3V
1220
(1)
(2)
(3)
(4)
(5)
(6)
2.2 V
30
3V
30
UNIT
µA
mV
mV/°C
µs
N/A (5)
2.2 V
3V
N/A
µA
V
ns
The sensor current ISENSOR is consumed if (ADC12ON = 1 and REFON = 1), or (ADC12ON = 1 AND INCH = 0Ah and sample signal is
high). Therefore, it includes the constant current through the sensor and the reference.
Not production tested, limits characterized
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor on-time, tSENSOR(on).
No additional current is needed. The VMID is used during sampling.
N/A = Not applicable
The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
5.29 Flash Memory
over recommended operating supply voltage and free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC(PGM/ERASE)
Program and erase supply voltage
2.7
3.6
V
fFTG
Flash timing generator frequency
257
476
kHz
IPGM
Supply current from DVCC during program
VCC = 2.7 V or 3.6 V
3
5
mA
IERASE
Supply current from DVCC during erase
VCC = 2.7 V or 3.6 V
3
7
mA
4
ms
(1)
tCPT
Cumulative program time
tCMErase
Cumulative mass erase time (2)
VCC = 2.7 V or 3.6 V
VCC = 2.7 V or 3.6 V
Program and erase endurance (3)
200
104
ms
105
cycles
tRetention
Data retention duration (3)
tWord
Word or byte program time (3)
35
tFTG
tBlock,
Block program time for first byte or word (3)
30
tFTG
21
tFTG
6
tFTG
0
tBlock, 1-63
Block program time for each additional byte or word
tBlock,
Block program end-sequence wait time (3)
End
TJ = 25°C
(3)
100
years
tMass Erase
Mass erase time (3)
5297
tFTG
tSeg Erase
Segment erase time (3)
4819
tFTG
(1)
(2)
(3)
The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word or byte write and block write modes.
The mass erase duration generated by the flash timing generator is at least 11.1 ms ( = 5297 × 1/fFTG, maximum = 5297 × 1/476 kHz).
To achieve the required cumulative mass erase time the flash controller mass erase operation can be repeated until this time is met. A
worst case minimum of 19 cycles are required.
These values are hardwired into the flash controller state machine (tFTG = 1/fFTG).
Specifications
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5.30 JTAG Interface
over recommended operating supply voltage and free-air temperature (unless otherwise noted)
PARAMETER
fTCK
TCK input frequency (1)
Rinternal
Internal pullup resistance on TMS, TCK, TDI/TCLK
(1)
VCC
MIN
TYP
MAX
2.2 V
0
5
3V
0
10
2.2 V, 3 V
25
60
90
UNIT
MHz
kΩ
fTCK may be restricted to meet the timing requirements of the module selected.
5.31 JTAG Fuse
(1)
over recommended operating supply voltage and free-air temperature (unless otherwise noted)
PARAMETER
VCC(FB)
Supply voltage during fuse blow
VFB
Voltage level on TDI/TCLK for fuse blow
IFB
Supply current into TDI/TCLK during fuse blow
tFB
Time to blow fuse
(1)
32
TA
MIN
25°C
2.5
MAX
UNIT
V
6
7
V
100
mA
1
ms
After the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched to
bypass mode.
Specifications
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MSP430F1491, MSP430F1481, MSP430F1471
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SLAS272H – JULY 2000 – REVISED MAY 2018
6 Detailed Description
6.1
CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are
dedicated as program counter, stack pointer, status register, and constant generator, respectively. The
remaining registers are general-purpose registers (see Figure 6-1).
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word and
byte data.
Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
Constant Generator
SR/CG1/R2
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Figure 6-1. CPU Registers
Detailed Description
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6.2
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Instruction set
The instruction set consists of 51 instructions with three formats and seven address modes. Each
instruction can operate on word and byte data. Table 6-1 lists examples of the three types of instruction
formats, and Table 6-2 lists the address modes.
Table 6-1. Instruction Word Formats
EXAMPLE
OPERATION
Dual operands, source-destination
INSTRUCTION FORMAT
ADD R4, R5
R4 + R5 → R5
Single operands, destination only
CALL R8
PC → (TOS), R8 → PC
JNE
Jump-on-equal bit = 0
Relative jump, unconditional or conditional
Table 6-2. Address Mode Descriptions
S (1)
D (1)
SYNTAX
EXAMPLE
Register
✓
✓
MOV Rs, Rd
MOV R10, R11
R10 → R11
Indexed
✓
✓
MOV X(Rn), Y(Rm)
MOV 2(R5), 6(R6)
M(2+R5) → M(6+R6)
Symbolic (PC relative)
✓
✓
MOV EDE, TONI
Absolute
✓
✓
MOV &MEM, &TCDAT
Indirect
✓
MOV @Rn, Y(Rm)
MOV @R10, Tab(R6)
M(R10) → M(Tab+R6)
Indirect autoincrement
✓
MOV @Rn+, Rm
MOV @R10+, R11
M(R10) → R11
R10 + 2 → R10
Immediate
✓
MOV #X, TONI
MOV #45, TONI
#45 → M(TONI)
ADDRESS MODE
(1)
6.3
OPERATION
M(EDE) → M(TONI)
M(MEM) → M(TCDAT)
S = source, D = destination
Operating Modes
The MSP430F13x, MSP430F14x, and MSP430F14x1 MCUs support one active mode and five softwareselectable low-power modes of operation. An interrupt event can wake up the MCU from any of the lowpower modes, service the request, and restore back to the low-power mode on return from the interrupt
program.
The following operating modes can be configured by software:
•
•
•
34
Active mode (AM)
– All clocks are active
Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active
– MCLK is disabled
Low-power mode 1 (LPM1)
– CPU is disabled
– ACLK and SMCLK remain active
– MCLK is disabled
– DC generator of the DCO is disabled if
DCO not used in active mode
Detailed Description
•
•
•
Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK and SMCLK are disabled
– DC generator of the DCO remains
enabled
– ACLK remains active
Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK and SMCLK are disabled
– DC generator of the DCO is disabled
– ACLK remains active
Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK and SMCLK are disabled
– DC generator of the DCO is disabled
– Crystal oscillator is stopped
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6.4
SLAS272H – JULY 2000 – REVISED MAY 2018
Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are in the address range 0FFFFh to 0FFE0h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 6-3. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
Power up
External reset
Watchdog
Flash memory
WDTIFG
KEYV (1)
Reset
0FFFEh
15, highest
NMI
Oscillator fault
Flash memory access violation
NMIIFG
OFIFG
ACCVIFG (1)
(Non)maskable (2)
0FFFCh
14
Timer_B7 (3)
TBCCR0 CCIFG (4)
Maskable
0FFFAh
13
Timer_B7 (3)
TBCCR1 to 6 CCIFGs,
TBIFG (1) (4)
Maskable
0FFF8h
12
Comparator_A
CAIFG
Maskable
0FFF9h
11
Watchdog timer
WDTIFG
Maskable
0FFF4h
10
USART0 receive
URXIFG0
Maskable
0FFF2h
9
USART0 transmit
UTXIFG0
Maskable
0FFF0h
8
ADC12 (5)
ADC12IFG (1) (4)
Maskable
0FFEEh
7
Timer_A3
TACCR0 CCIFG
Maskable
0FFECh
6
Timer_A3
TACCR1 CCIFG,
TACCR2 CCIFG,
TAIFG (1) (4)
Maskable
0FFEAh
5
I/O port P1 (eight flags)
P1IFG.0 to P1IFG.7 (1) (4)
Maskable
0FFE8h
4
USART1 receive
URXIFG1
Maskable
0FFE6h
3
USART1 transmit
UTXIFG1
Maskable
0FFE4h
2
Maskable
0FFE2h
1
–
0FFE0h
0, lowest
I/O port P2 (eight flags)
P2IFG.0 to P2IFG.7
–
(1)
(2)
(3)
(4)
(5)
6.5
(4)
(1) (4)
–
Multiple source flags
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disable it.
Timer_B7 in the MSP430F14x(1) MCUs has 7 CCRs, and Timer_B3 in the MSP430F13x MCUs has 3 CCRs. In Timer_B3, there are
only interrupt flags TBCCR0, TBCCR1, and TBCCR2 CCIFGs and the interrupt-enable bits TBCCTL0, TBCCTL1, and TBCCTL2 CCIEs.
Interrupt flags are located in the module.
ADC12 is not implemented on the MSP430F14x1 devices.
Bootloader (BSL)
The MSP430 BSL lets users program the flash memory or RAM using a UART serial interface. Access to
the MSP430 memory through the BSL is protected by a user-defined password. For complete description
of the features of the BSL and its implementation, see the MSP430™ Flash Device Bootloader (BSL)
User's Guide. Table 6-4 lists the pin requirements for the BSL.
Table 6-4. BSL Pin Requirements and Functions
BSL FUNCTION
PM, PAG, AND RTD PACKAGE
PINS
Data transmit
13 - P1.1
Data receive
22 - P2.2
Detailed Description
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6.6
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JTAG Fuse Check Mode
MSP430 MCUs that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the
continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When
activated, a fuse check current (ITF) of 1 mA at 3 V or 2.5 mA at 5 V can flow from the TDI/TCLK pin to
ground if the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode
and increasing overall system power consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if
the TMS is being held low during power up. The second positive edge on the TMS pin deactivates the
fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs.
After each POR the fuse check mode has the potential to be activated.
The fuse check current flows only when the fuse check mode is active and the TMS pin is in a low state
(see Figure 6-2). Therefore, the additional current flow can be prevented by holding the TMS pin high
(default condition).
Time TMS goes low after POR
TMS
ITF
ITDI/TCLK
Figure 6-2. Fuse Check Mode Current
6.7
Memory
Table 6-5 summarizes the memory map of all device variants.
Table 6-5. Memory Organization
MSP430F133
Memory (flash)
MSP430F135
MSP430F147
MSP430F1471
MSP430F148
MSP430F1481
MSP430F149
MSP430F149
Size
8KB
16KB
32KB
48KB
60KB
Main: interrupt vector
Flash
0FFFFh to
0FFE0h
0FFFFh to
0FFE0h
0FFFFh to
0FFE0h
0FFFFh to
0FFE0h
0FFFFh to
0FFE0h
Main: code memory
Flash
0FFFFh to
0E000h
0FFFFh to
0C000h
0FFFFh to
08000h
0FFFFh to
04000h
0FFFFh to
01100h
Size
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
Information memory
Boot memory
RAM
Peripherals
Flash 010FFh to 01000h 010FFh to 01000h 010FFh to 01000h 010FFh to 01000h 010FFh to 01000h
Size
1KB
1KB
1KB
1KB
1KB
Flash
0FFFh to 0C00h
0FFFh to 0C00h
0FFFh to 0C00h
0FFFh to 0C00h
0FFFh to 0C00h
Size
256 bytes
512 bytes
1KB
2KB
2KB
RAM
02FFh to 0200h
03FFh to 0200h
05FFh to 0200h
09FFh to 0200h
09FFh to 0200h
16-bit
01FFh to 0100h
01FFh to 0100h
01FFh to 0100h
01FFh to 0100h
01FFh to 0100h
8-bit
0FFh to 010h
0FFh to 010h
0FFh to 010h
0FFh to 010h
0FFh to 010h
0Fh to 00h
0Fh to 00h
0Fh to 00h
0Fh to 00h
0Fh to 00h
8-bit SFR
36
Detailed Description
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6.7.1
SLAS272H – JULY 2000 – REVISED MAY 2018
Flash Memory
The flash memory can be programmed through the JTAG port, the bootloader, or in-system by the CPU.
The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash
memory include:
• Flash memory has n segments of main memory and two segments of information memory (A and B) of
128 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A and B can be erased individually, or as a group with segments 0 to n. Segments A and B
are also called information memory.
• New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
8KB
16KB
32KB
48KB
60KB
0FFFFh
0FFFFh
0FFFFh
0FFFFh
0FFFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
0FC00h
0FBFFh
0FC00h
0FBFFh
0FC00h
0FBFFh
0FC00h
0FBFFh
0FC00h
0FBFFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
Segment 0
with interrupt vectors
Segment 1
Segment 2
Main memory
0E400h
0E3FFh
0C400h
0C3FFh
08400h
083FFh
04400h
043FFh
01400h
013FFh
0E200h
0E1FFh
0C200h
0C1FFh
08200h
081FFh
04200h
041FFh
01200h
011FFh
0E000h
010FFh
0C000h
010FFh
08000h
010FFh
04000h
010FFh
01100h
010FFh
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01000h
01000h
01000h
01000h
01000h
Segment n-1
Segment n
Segment A
Information memory
Segment B
Figure 6-3. Flash Memory
Detailed Description
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6.7.2
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Special Function Registers
Most interrupt and module-enable bits are collected in the lowest address space. Special-function register
bits not allocated to a functional purpose are not physically present in the device. This arrangement
provides simple software access.
Figure 6-4. Interrupt Enable 1 Bit Register
7
UTXIE0
R/W-0
6
URXIE0
R/W-0
5
ACCVIE
R/W-0
4
NMIIE
R/W-0
3
2
1
OFIE
R/W-0
Reserved
R-0
0
WDTIE
R/W-0
Table 6-6. Interrupt Enable 1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
UTXIE0
R/W
0
USART0: UART and SPI transmit interrupt enable
6
URXIE0
R/W
0
USART0: UART and SPI receive interrupt enable
5
ACCVIE
R/W
0
Flash access violation interrupt enable
4
NMIIE
R/W
0
Nonmaskable interrupt enable
3-2
Reserved
R
0
1
OFIE
R/W
0
Oscillator-fault interrupt enable
0
WDTIE
R/W
0
Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog
timer is configured in interval timer mode.
Figure 6-5. Interrupt Enable 2 Bit Register
7
6
5
UTXIE1
R/W-0
Reserved
R-0
4
URXIE1
R/W-0
3
2
1
0
1
OFIFG
R/W-1
0
WDTIFG
R/W-(0)
Reserved
R-0
Table 6-7. Interrupt Enable 2 Register Field Descriptions
Bit
Field
Type
Reset
7-6
Reserved
R
0
5
UTXIE1
R/W
0
USART1: UART and SPI receive interrupt enable
4
URXIE1
R/W
0
USART1: UART and SPI transmit interrupt enable
Reserved
R/W
0
3-0
Description
Figure 6-6. Interrupt Flag 1 Bit Register
7
UTXIFG0
R/W-1
6
URXIFG0
R/W-0
5
Reserved
R-0
4
NMIIFG
R/W-0
3
2
Reserved
R-0
Table 6-8. Interrupt Flag 1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
UTXIFG0
R/W
1
USART0: UART and SPI transmit flag
6
URXIFG0
R/W
0
USART0: UART and SPI receive flag
5
Reserved
R
0
4
NMIIFG
R/W
0
Reserved
R
0
1
OFIFG
R/W
1
Flag set on oscillator fault
0
WDTIFG
R/W
(0)
Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC
power up or a reset condition at the RST/NMI pin in reset mode.
3-2
38
Detailed Description
Set by RST/NMI pin
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Figure 6-7. Interrupt Flag 2 Bit Register
7
6
5
UTXIFG1
R/W-1
Reserved
R-0
4
URXIFG1
R/W-0
3
2
1
0
1
0
Reserved
R-0
Table 6-9. Interrupt Flag 2 Register Field Descriptions
Bit
Field
Type
Reset
7-6
Reserved
R
0
Description
5
UTXIFG1
R/W
1
USART1: UART and SPI transmit flag
4
URXIFG1
R/W
0
USART1: UART and SPI receive flag
3-0
Reserved
R
0
Figure 6-8. Module Enable 1 Bit Register
7
6
URXE0
USPIE0
R/W-0
UTXE0
R/W-0
5
4
3
2
Reserved
R-0
Table 6-10. Module Enable 1 Bit Register Field Descriptions
Bit
Field
Type
Reset
Description
7
UTXE0
R/W
0
USART0: UART transmit enable
6
URXE0
USPIE0
R/W
0
USART0: UART receive enable
USART0: SPI (synchronous peripheral interface) transmit and receive enable
Reserved
R
0
5-0
Figure 6-9. Module Enable 2 Bit Register
7
6
5
Reserved
UTXE1
R-0
R/W-0
4
URXE1
USPIE1
R/W-0
3
2
1
0
Reserved
R-0
Table 6-11. Module Enable 2 Bit Register Field Descriptions
Bit
Field
Type
Reset
7-6
Reserved
R
0
R/W
0
USART1: UART transmit enable
URXE1
USPIE1
R/W
0
USART1: UART receive enable
USART1: SPI (synchronous peripheral interface) transmit and receive enable
Reserved
R
0
5
4
3-0
Description
Detailed Description
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6.8
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Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using
all instructions. For complete module descriptions, see the MSP430x1xx Family User’s Guide.
6.8.1
Digital I/O
Six 8-bit I/O ports are implemented: ports P1 to P6:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
• Read and write access to port-control registers is supported by all instructions.
6.8.2
Oscillator and System Clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch
crystal oscillator, an internal digitally controlled oscillator (DCO), and a high-frequency crystal oscillator.
The basic clock module is designed to meet the requirements of both low system cost and low power
consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 µs. The
basic clock module provides the following clock signals:
• Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal
• Main clock (MCLK), the system clock used by the CPU
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules
6.8.3
Watchdog Timer (WDT)
The primary function of the WDT module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not
needed in an application, the module can be configured as an interval timer and can generate interrupts at
selected time intervals.
6.8.4
Hardware Multiplier (MSP430F14x and MSP430F14x1 Only)
The multiplication operation is supported by a dedicated peripheral module. The module performs 16 × 16,
16 × 8, 8 × 16, and 8 × 8 bit operations. The module is capable of supporting signed and unsigned
multiplication as well as signed and unsigned multiply and accumulate operations. The result of an
operation can be accessed immediately after the operands have been loaded into the peripheral registers.
No additional clock cycles are required.
6.8.5
USART0
The hardware universal synchronous/asynchronous receive transmit (USART0) peripheral module is used
for serial data communication. The USART supports synchronous SPI (3 or 4 pin) and asynchronous
UART communication protocols, using double-buffered transmit and receive channels.
6.8.6
USART1 (MSP430F14x and MSP430F14x1 Only)
The MSP430F14x(1) has a second hardware universal synchronous/asynchronous receive transmit
(USART1) peripheral module that is used for serial data communication. The USART supports
synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered
transmit and receive channels. Operation of USART1 is identical to USART0.
6.8.7
Comparator_A
The primary function of the Comparator_A module is to support precision slope analog-to-digital
conversions, battery-voltage supervision, and monitoring of external analog signals.
40
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6.8.8
SLAS272H – JULY 2000 – REVISED MAY 2018
ADC12 (MSP430F14x and MSP430F13x Only)
The ADC12 module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit
SAR core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored
without CPU intervention.
6.8.9
Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing (see Table 6-12). Timer_A3 also has extensive
interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each
of the capture/compare registers.
Table 6-12. Timer_A3 Signal Connections
INPUT PIN NUMBER
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
12 - P1.0
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
21 - P2.1
TAINCLK
INCLK
13 - P1.1
TA0
CCI0A
22 - P2.2
TA0
CCI0B
DVSS
GND
14 - P1.2
15 - P1.3
DVCC
VCC
TA1
CCI1A
CAOUT (internal)
CCI1B
DVSS
GND
DVCC
VCC
TA2
CCI2A
ACLK (internal)
CCI2B
DVSS
GND
DVCC
VCC
MODULE BLOCK
MODULE OUTPUT
SIGNAL
Timer
NA
OUTPUT PIN
NUMBER
13 - P1.1
CCR0
TA0
CCR1
TA1
CCR2
TA2
17 - P1.5
27 - P2.7
6.8.10 Timer_B3 (MSP430F13x Only)
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing (see Table 6-13). Timer_B3 also has extensive
interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each
of the capture/compare registers.
6.8.11 Timer_B7 (MSP430F14x and MSP430F14x1 Only)
Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple
capture/compares, PWM outputs, and interval timing (see Table 6-13). Timer_B7 also has extensive
interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each
of the capture/compare registers.
Detailed Description
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Table 6-13. Timer_B3 and Timer_B7 Signal Connections (1)
INPUT PIN NUMBER
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
43 - P4.7
TBCLK
TBCLK
ACLK
ACLK
SMCLK
SMCLK
43 - P4.7
TBCLK
INCLK
36 - P4.0
TB0
CCI0A
TB0
CCI0B
DVSS
GND
36 - P4.0
37 - P4.1
37 - P4.1
CCI1A
TB1
CCI1B
GND
DVCC
VCC
38 - P4.2
TB2
CCI2A
38 - P4.2
TB2
CCI2B
DVSS
GND
DVCC
VCC
39 - P4.3
TB3
CCI3A
39 - P4.3
TB3
CCI3B
DVSS
GND
DVCC
VCC
40 - P4.4
TB4
CCI4A
40 - P4.4
TB4
CCI4B
DVSS
GND
41 - P4.5
DVCC
VCC
TB5
CCI5A
TB5
CCI5B
DVSS
GND
DVCC
VCC
TB6
CCI6A
ACLK (internal)
CCI6B
DVSS
GND
DVCC
VCC
42 - P4.6
42
VCC
TB1
DVSS
41 - P4.5
(1)
DVCC
MODULE BLOCK
MODULE OUTPUT
SIGNAL
Timer
NA
OUTPUT PIN
NUMBER
36 - P4.0
CCR0
TB0
ADC12 (internal)
37 - P4.1
CCR1
TB1
ADC12 (internal)
38 - P4.2
CCR2
TB2
39 - P4.3
CCR3
TB3
40 - P4.4
CCR4
TB4
41 - P4.5
CCR5
TB5
42 - P4.6
CCR6
TB6
Timer_B3 implements three capture/compare blocks (CCR0, CCR1 and CCR2).
Detailed Description
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6.8.12 Peripheral File Map
Table 6-14 lists the peripheral register that support word access. See Table 6-15 for the regsiters with byte
access.
Table 6-14. Peripherals With Word Access
MODULE
Watchdog
REGISTER NAME
0120h
Timer_B interrupt vector
TBIV
011Eh
TBCTL
0180h
Timer_B capture/compare control 0
TBCCTL0
0182h
Timer_B capture/compare control 1
TBCCTL1
0184h
Timer_B capture/compare control 2
TBCCTL2
0186h
Timer_B capture/compare control 3 (1)
TBCCTL3
0188h
Timer_B capture/compare control 4 (1)
TBCCTL4
018Ah
Timer_B capture/compare control 5 (1)
TBCCTL5
018Ch
(1)
TBCCTL6
018Eh
TBR
0190h
Timer_B capture/compare 0
TBCCR0
0192h
Timer_B capture/compare 1
TBCCR1
0194h
Timer_B capture/compare 2
TBCCR2
0196h
Timer_B capture/compare 3 (1)
TBCCR3
0198h
(1)
TBCCR4
019Ah
Timer_B capture/compare 5 (1)
TBCCR5
019Ch
Timer_B capture/compare 6 (1)
TBCCR6
019Eh
TAIV
012Eh
Timer_B capture/compare control 6
Timer_B counter
Timer_B capture/compare 4
Timer_A interrupt vector
Timer_A control
Timer_A3
TACTL
0160h
Timer_A capture/compare control 0
TACCTL0
0162h
Timer_A capture/compare control 1
TACCTL1
0164h
Timer_A capture/compare control 2
TACCTL2
0166h
Reserved
0168h
Reserved
016Ah
Reserved
016Ch
Reserved
Timer_A counter
016Eh
TAR
0170h
Timer_A capture/compare 0
TACCR0
0172h
Timer_A capture/compare 1
TACCR1
0174h
Timer_A capture/compare 2
TACCR2
0176h
Reserved
(1)
ADDRESS
WDTCTL
Timer_B control
Timer_B7, Timer_B3
ACRONYM
Watchdog timer control
0178h
Reserved
017Ah
Reserved
017Ch
Reserved
017Eh
Timer_B7 only, reserved for Timer_B3
Detailed Description
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MSP430F149, MSP430F148, MSP430F147
MSP430F1491, MSP430F1481, MSP430F1471
MSP430F135, MSP430F133
SLAS272H – JULY 2000 – REVISED MAY 2018
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Table 6-14. Peripherals With Word Access (continued)
MODULE
REGISTER NAME
ACRONYM
ADDRESS
SUMEXT
013Eh
Result high word
RESHI
013Ch
Result low word
RESLO
013Ah
OP2
0138h
MACS
0136h
MAC
0134h
MPYS
0132h
Sum extend
Hardware multiplier
(MSP430F14x and
MSP430F14x1 only)
Operand 2
Multiply signed and accumulate operand 1
Multiply and accumulate operand 1
Multiply signed operand 1
Multiply unsigned operand 1
Flash
44
Detailed Description
MPY
0130h
Flash control 3
FCTL1
012Ch
Flash control 2
FCTL2
012Ah
Flash control 1
FCTL1
0128h
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MSP430F1491, MSP430F1481, MSP430F1471
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SLAS272H – JULY 2000 – REVISED MAY 2018
Table 6-14. Peripherals With Word Access (continued)
MODULE
ACRONYM
ADDRESS
Conversion memory 15
REGISTER NAME
ADC12MEM15
015Eh
Conversion memory 14
ADC12MEM14
015Ch
Conversion memory 13
ADC12MEM13
015Ah
Conversion memory 12
ADC12MEM12
0158h
Conversion memory 11
ADC12MEM11
0156h
Conversion memory 10
ADC12MEM10
0154h
Conversion memory 9
ADC12MEM9
0152h
Conversion memory 8
ADC12MEM8
0150h
Conversion memory 7
ADC12MEM7
014Eh
Conversion memory 6
ADC12MEM6
014Ch
Conversion memory 5
ADC12MEM5
014Ah
Conversion memory 4
ADC12MEM4
0148h
Conversion memory 3
ADC12MEM3
0146h
Conversion memory 2
ADC12MEM2
0144h
Conversion memory 1
ADC12MEM1
0142h
Conversion memory 0
ADC12MEM0
0140h
ADC12IV
01A8h
Interrupt vector word
Interrupt enable
ADC12 (not in MSP430F14x1)
ADC12IE
01A6h
ADC12IFG
01A4h
ADC control 1
ADC12CTL1
01A2h
ADC control 0
ADC12CTL0
01A0h
Interrupt flag
ADC memory control 15
ADC12MCTL15
08Fh
ADC memory control 14
ADC12MCTL14
08Eh
ADC memory control 13
ADC12MCTL13
08Dh
ADC memory control 12
ADC12MCTL12
08Ch
ADC memory control 11
ADC12MCTL11
08Bh
ADC memory control 10
ADC12MCTL10
08Ah
ADC memory control 9
ADC12MCTL9
089h
ADC memory control 8
ADC12MCTL8
088h
ADC memory control 7
ADC12MCTL7
087h
ADC memory control 6
ADC12MCTL6
086h
ADC memory control 5
ADC12MCTL5
085h
ADC memory control 4
ADC12MCTL4
084h
ADC memory control 3
ADC12MCTL3
083h
ADC memory control 2
ADC12MCTL2
082h
ADC memory control 1
ADC12MCTL1
081h
ADC memory control 0
ADC12MCTL0
080h
Detailed Description
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MSP430F1491, MSP430F1481, MSP430F1471
MSP430F135, MSP430F133
SLAS272H – JULY 2000 – REVISED MAY 2018
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Table 6-15 lists the peripheral register that support byte access. See Table 6-14 for the regsiters with word
access.
Table 6-15. Peripherals With Byte Access
MODULE
REGISTER NAME
USART0
07Fh
Receive buffer
U1RXBUF
07Eh
U1BR1
07Dh
Baud rate 0
U1BR0
07Ch
Modulation control
U1MCTL
07Bh
Receive control
U1RCTL
07Ah
Transmit control
U1TCTL
079h
USART control
U1CTL
078h
Transmit buffer
U0TXBUF
077h
Receive buffer
U0RXBUF
076h
Baud rate 1
U0BR1
075h
Baud rate 0
U0BR0
074h
Modulation control
U0MCTL
073h
Receive control
U0RCTL
072h
Transmit control
U0TCTL
071h
USART control
U0CTL
070h
Comparator_A port disable
Comparator_A
Basic Clock
CAPD
05Bh
Comparator_A control 2
CACTL2
05Ah
Comparator_A control 1
CACTL1
059h
Basic clock system control 2
BCSCTL2
058h
Basic clock system control 1
BCSCTL1
057h
DCO clock frequency control
DCOCTL
056h
P6SEL
037h
Port P6 direction
P6DIR
036h
Port P6 output
P6OUT
035h
P6IN
034h
Port P5 selection
P5SEL
033h
Port P5 direction
P5DIR
032h
Port P5 output
P5OUT
031h
Port P6 selection
Port P6
Port P6 input
Port P5
Port P5 input
Port P4 selection
Port P4
Detailed Description
030h
01Fh
P4DIR
01Eh
Port P4 output
P4OUT
01Dh
P4IN
01Ch
Port P3 selection
P3SEL
01Bh
Port P3 direction
P3DIR
01Ah
Port P3 output
P3OUT
019h
P3IN
018h
Port P3 input
46
P5IN
P4SEL
Port P4 direction
Port P4 input
Port P3
ADDRESS
U1TXBUF
Baud rate 1
USART1 (MSP430F14x and
MSP430F14x1 only)
ACRONYM
Transmit buffer
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MSP430F1491, MSP430F1481, MSP430F1471
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SLAS272H – JULY 2000 – REVISED MAY 2018
Table 6-15. Peripherals With Byte Access (continued)
MODULE
REGISTER NAME
Port P2 selection
Port P2 interrupt enable
Port P2
02Eh
P2IE
02Dh
P2IES
02Ch
Port P2 interrupt flag
P2IFG
02Bh
Port P2 direction
P2DIR
02Ah
Port P2 output
P2OUT
029h
P2IN
028h
P1SEL
026h
P1IE
025h
Port P1 interrupt edge select
P1IES
024h
Port P1 interrupt flag
P1IFG
023h
Port P1 direction
P1DIR
022h
Port P1 output
P1OUT
021h
Port P1 input
P1IN
020h
SFR module enable 2
ME2
005h
SFR module enable 1
ME1
004h
SFR interrupt flag 2
IFG2
003h
SFR interrupt flag 1
Port P1 selection
Port P1 interrupt enable
Special Functions
ADDRESS
P2SEL
Port P2 interrupt edge select
Port P2 input
Port P1
ACRONYM
IFG1
002h
SFR interrupt enable 2
IE2
001h
SFR interrupt enable 1
IE1
000h
Detailed Description
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MSP430F1491, MSP430F1481, MSP430F1471
MSP430F135, MSP430F133
SLAS272H – JULY 2000 – REVISED MAY 2018
6.9
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Input/Output Diagrams
6.9.1
Port P1, Input/Output With Schmitt Trigger
P1SEL.x
0
P1DIR.x
Direction Control
From Module
1
Pad Logic
0
P1OUT.x
Module X OUT
1
P1.0/TACLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
P1.5/TA0
P1.6/TA1
P1.7/TA2
P1IN.x
EN
Module X IN
D
P1IRQ.x
P1IE.x
Q
P1IFG.x
EN
Set
Interrupt
Flag
Interrupt
Edge
Select
P1IES.x
P1SEL.x
Figure 6-10. Port P1 (P1.0 to P1.7) Diagram
Table 6-16. Port P1 (P1.0 to P1.7) Pin Functions
PnSel.x
PnDIR.x
DIRECTION
CONTROL
FROM
MODULE
PnOUT.x
MODULE X
OUT
PnIN.x
MODULE X IN
PnIE.x
PnIFG.x
PnIES.x
P1Sel.0
P1DIR.0
P1DIR.0
P1OUT.0
DVSS
P1IN.0
TACLK (1)
P1IE.0
P1IFG.0
P1IES.0
(1)
P1IN.1
CCI0A (1)
P1IE.1
P1IFG.1
P1IES.1
P1IN.2
CCI1A (1)
P1IE.2
P1IFG.2
P1IES.2
P1IN.3
(1)
P1Sel.1
P1DIR.1
P1DIR.1
P1OUT.1
Out0 signal
P1Sel.2
P1DIR.2
P1DIR.2
P1OUT.2
Out1 signal (1)
(1)
P1Sel.3
P1DIR.3
P1DIR.3
P1OUT.3
P1IE.3
P1IFG.3
P1IES.3
P1Sel.4
P1DIR.4
P1DIR.4
P1OUT.4
Out2 signal
SMCLK
P1IN.4
unused
P1IE.4
P1IFG.4
P1IES.4
P1Sel.5
P1DIR.5
P1DIR.5
P1OUT.5
Out0 signal (1)
P1IN.5
unused
P1IE.5
P1IFG.5
P1IES.5
(1)
P1IN.6
unused
P1IE.6
P1IFG.6
P1IES.6
P1IN.7
unused
P1IE.7
P1IFG.7
P1IES.7
P1Sel.6
P1DIR.6
P1DIR.6
P1OUT.6
Out1 signal
P1Sel.7
P1DIR.7
P1DIR.7
P1OUT.7
Out2 signal (1)
(1)
Signal from or to Timer_A
48
Detailed Description
CCI2A
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MSP430F1491, MSP430F1481, MSP430F1471
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6.9.2
SLAS272H – JULY 2000 – REVISED MAY 2018
Port P2, Input/Output With Schmitt Trigger
P2SEL.x
0
P2DIR.x
Direction Control
From Module
0: Input
1: Output
1
0
P2OUT.x
Module X OUT
1
P2.0/ACLK
P2.1/TAINCLK
P2.2/CAOUT/TA0
P2.6/ADC12CLK
P2.7/TA0
Pad Logic
P2IN.x
EN
Module X IN
Bus Keeper
D
P2IE.x
P2IRQ.x
P2IFG.x
CAPD.X
Interrupt
Edge
Select
EN
Q
Set
Interrupt
Flag
P2IES.x
P2SEL.x
Figure 6-11. Port P2 (P2.0 to P2.2, P2.6, and P2.7) Diagram
Table 6-17. Port P2 (P2.0 to P2.2, P2.6, and P2.7) Pin Functions
PnSel.x
PnDIR.x
DIRECTION
CONTROL
FROM
MODULE
PnOUT.x
MODULE X
OUT
PnIN.x
P2Sel.0
P2DIR.0
P2DIR.0
P2OUT.0
ACLK
P2Sel.1
P2DIR.1
P2DIR.1
P2OUT.1
DVSS
P2Sel.2
P2DIR.2
P2DIR.2
P2OUT.2
CAOUT (2)
MODULE X IN
PnIE.x
PnIFG.x
PnIES.x
P2IN.0
unused
P2IE.0
P2IFG.0
P2IES.0
P2IN.1
INCLK (1)
P2IE.1
P2IFG.1
P2IES.1
P2IN.2
CCI0B (1)
P2IE.2
P2IFG.2
P2IES.2
(3)
P2IN.6
unused
P2IE.6
P2IFG.6
P2IES.6
P2IN.7
unused
P2IE.7
P2IFG.7
P2IES.7
P2Sel.6
P2DIR.6
P2DIR.6
P2OUT.6
ADC12CLK
P2Sel.7
P2DIR.7
P2DIR.7
P2OUT.7
Out0 signal (4)
(1)
(2)
(3)
(4)
Signal to Timer_A
Signal from Comparator_A
ADC12CLK signal is output of the 12-bit ADC module
Signal from Timer_A
Detailed Description
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MSP430F149, MSP430F148, MSP430F147
MSP430F1491, MSP430F1481, MSP430F1471
MSP430F135, MSP430F133
SLAS272H – JULY 2000 – REVISED MAY 2018
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P2SEL.3
0: Input
1: Output
0
P2DIR.3
Direction Control
From Module
1
Pad Logic
P2.3/CA0/TA1
0
P2OUT.3
Module X OUT
1
P2IN.3
EN
Module X IN
Bus Keeper
D
P2IRQ.3
P2IE.3
P2IFG.3
EN
Set
Q
Interrupt
Flag
Interrupt
Edge
Select
P2IES.3
P2SEL.3
CAPD.3
Comparator_A
CAEX
P2CA
CAREF
CAF
+
CCI1B
To Timer_A3
−
Interrupt
Flag
P2IFG.4
P2IRQ.4
Set
EN
Q
P2IE.4
P2SEL.4
P2IES.4
CAREF
Reference Block
Interrupt
Edge
Select
CAPD.4
D
Module X IN
Bus Keeper
EN
P2IN.4
1
Module X OUT
P2OUT.4
0
From Module
Direction Control
P2DIR.4
1
P2.4/CA1/TA2
Pad Logic
1: Output
0: Input
0
P2SEL.4
Figure 6-12. Port P2 (P2.3 and P2.4) Diagram
Table 6-18. Port P2 (P2.3 and P2.4) Pin Functions
PnSel.x
PnDIR.x
DIRECTION
CONTROL
FROM
MODULE
PnOUT.x
MODULE X
OUT
PnIN.x
MODULE X IN
PnIE.x
PnIFG.x
PnIES.x
P2Sel.3
P2DIR.3
P2DIR.3
P2OUT.3
Out1 signal (1)
P2IN.3
unused
P2IE.3
P2IFG.3
P2IES.3
P2Sel.4
P2DIR.4
P2DIR.4
P2OUT.4
Out2 signal (1)
P2IN.4
unused
P2IE.4
P2IFG.4
P2IES.4
(1)
50
Signal from Timer_A
Detailed Description
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MSP430F1491, MSP430F1481, MSP430F1471
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SLAS272H – JULY 2000 – REVISED MAY 2018
0: Input
1: Output
P2SEL.5
0
P2DIR.5
Direction Control
From Module
Pad Logic
1
0
P2OUT.5
Module X OUT
1
P2.5/ROSC
Bus Keeper
P2IN.5
EN
Module X IN
P2IRQ.5
D
P2IE.5
EN
Q
Set
P2IFG.5
Interrupt
Flag
VCC
Edge
Select
Interrupt
P2IES.5
P2SEL.5
Internal to
Basic Clock
Module
0
1
to
DCOR
DC Generator
CAPD.5
DCOR: Control bit from Basic Clock module. If it is set, P2.5 is disconnected from P2.5 pad.
Figure 6-13. Port P2 (P2.5) Diagram
Table 6-19. Port P2 (P2.5) Pin Functions
PnSel.x
PnDIR.x
DIRECTION
CONTROL
FROM
MODULE
PnOUT.x
MODULE X
OUT
PnIN.x
MODULE X
IN
PnIE.x
PnIFG.x
PnIES.x
P2Sel.5
P2DIR.5
P2DIR.5
P2OUT.5
DVSS
P2IN.5
unused
P2IE.5
P2IFG.5
P2IES.5
Detailed Description
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MSP430F149, MSP430F148, MSP430F147
MSP430F1491, MSP430F1481, MSP430F1471
MSP430F135, MSP430F133
SLAS272H – JULY 2000 – REVISED MAY 2018
6.9.3
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Port P3, Input/Output With Schmitt Trigger
P3SEL.x
0: Input
1: Output
0
P3DIR.x
Direction Control
From Module
1
Pad Logic
0
P3OUT.x
Module X OUT
1
P3.0/STE0
P3.4/UTXD0
P3.5/URXD0
P3.6/UTXD1
P3.7/URXD1
P3IN.x
EN
D
Module X IN
Figure 6-14. Port P3 (P3.0 and 3.4 to 3.7) Diagram
Table 6-20. Port P3 (P3.0 and 3.4 to 3.7) Pin Functions
(1)
(2)
(3)
(4)
DIRECTION
CONTROL FROM
MODULE
PnOUT.x
P3DIR.0
DVSS
P3DIR.4
DVCC
P3Sel.5
P3DIR.5
P3Sel.6
P3Sel.7
PnSel.x
PnDIR.x
MODULE X OUT
PnIN.x
P3Sel.0
P3Sel.4
MODULE X IN
P3OUT.0
DVSS
P3IN.0
STE0
P3OUT.4
UTXD0 (1)
P3IN.4
Unused
DVSS
P3OUT.5
DVSS
P3IN.5
URXD0 (2)
P3DIR.6
DVCC
P3OUT.6
UTXD1 (3)
P3IN.6
unused
P3DIR.7
DVSS
P3OUT.7
DVSS
P3IN.7
URXD1 (4)
Output from USART0 module
Input to USART0 module
Output from USART1 module in MSP430F14x and MSP430F14x1 devices, DVSS in MSP430F13x devices
Input to USART1 module in MSP430F14x and MSP430F14x1 devices, unused in MSP430F13x devices
P3SEL.1
SYNC
MM
STC
STE
0
P3DIR.1
0: Input
1: Output
1
DCM_SIMO
Pad Logic
0
P3OUT1
(SI)MO0
From USART0
1
P3.1/SIMO0
P3IN.1
EN
SI(MO)0
To USART0
D
Figure 6-15. Port P3 (P3.1) Diagram
52
Detailed Description
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MSP430F1491, MSP430F1481, MSP430F1471
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SLAS272H – JULY 2000 – REVISED MAY 2018
P3SEL.2
SYNC
MM
STC
STE
0
P3DIR.2
0: Input
1: Output
1
DCM_SOMI
Pad Logic
0
P3OUT.2
SO(MI)0
From USART0
1
P3.2/SOMI0
P3IN.2
EN
(SO)MI0
To USART0
D
Figure 6-16. Port P3 (P3.2) Diagram
P3SEL.3
SYNC
MM
STC
STE
0
P3DIR.3
0: Input
1: Output
1
DCM_UCLK
Pad Logic
0
P3OUT.3
UCLK.0
From USART0
1
P3.3/UCLK0
P3IN.3
EN
UCLK0
D
To USART0
NOTE: UART mode: The UART clock can only be an input. If UART mode and UART function are selected, P3.3/UCLK0 is
always an input.
SPI slave mode: The clock applied to UCLK0 is used to shift data in and out.
SPI master mode: The clock to shift data in and out is supplied to connected devices on pin P3.3/UCLK0 (in slave
mode).
Figure 6-17. Port P3 (P3.3) Diagram
Detailed Description
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MSP430F149, MSP430F148, MSP430F147
MSP430F1491, MSP430F1481, MSP430F1471
MSP430F135, MSP430F133
SLAS272H – JULY 2000 – REVISED MAY 2018
6.9.4
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Port P4, Input/Output With Schmitt Trigger
0: Input
1: Output
P4SEL.x
0
P4DIR.x
Direction Control
From Module
1
Module X IN
Pad Logic
P5SEL.7
0
P4OUT.x
Module X OUT
1
P4.0/TB0
P4.1/TB1
P4.2/TB2
P4.3/TB3
P4.4/TB4
P4.5/TB5
P4.6/TB6
TBOUTH
Bus Keeper
P4IN.x
EN
Module X IN
D
Figure 6-18. Port P4 (P4.0 to P4.6) Diagram
Table 6-21. Port P4 (P4.0 to P4.6) Pin Functions
PnSel.x
PnDIR.x
DIRECTION
CONTROL FROM
MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
P4Sel.0
P4DIR.0
P4DIR.0
P4OUT.0
Out0 signal (1)
P4IN.0
CCI0A / CCI0B (2)
P4Sel.1
P4DIR.1
P4DIR.1
P4OUT.1
Out1 signal (1)
P4IN.1
CCI1A / CCI1B (2)
P4OUT.2
Out2 signal
(1)
P4IN.2
CCI2A / CCI2B (2)
Out3 signal
(1)
P4IN.3
CCI3A / CCI3B (2)
(1)
P4IN.4
CCI4A / CCI4B (2)
P4Sel.2
P4DIR.2
P4Sel.3
P4DIR.3
P4DIR.3
P4OUT.3
P4Sel.4
P4DIR.4
P4DIR.4
P4OUT.4
Out4 signal
P4Sel.5
P4DIR.5
P4DIR.5
P4OUT.5
Out5 signal (1)
P4IN.5
CCI5A / CCI5B (2)
P4OUT.6
(1)
P4IN.6
CCI6A (2)
P4Sel.6
(1)
(2)
P4DIR.2
P4DIR.6
P4DIR.6
Out6 signal
Signal from Timer_B
Signal to Timer_B
P4SEL.7
0
P4DIR.7
0: Input
1: Output
1
Pad Logic
0
P4OUT.7
DVSS
1
P4.7/TBCLK
P4IN.7
EN
Timer_B,
TBCLK
D
Figure 6-19. Port P4 (P4.7) Diagram
54
Detailed Description
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MSP430F1491, MSP430F1481, MSP430F1471
MSP430F135, MSP430F133
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6.9.5
SLAS272H – JULY 2000 – REVISED MAY 2018
Port P5, Input/Output With Schmitt Trigger
P5SEL.x
0: Input
1: Output
0
P5DIR.x
Direction Control
From Module
1
Pad Logic
0
P5OUT.x
Module X OUT
1
P5.0/STE1
P5.4/MCLK
P5.5/SMCLK
P5.6/ACLK
P5.7/TBOUTH
P5IN.x
EN
Module X IN
D
Figure 6-20. Port P5 (P5.0 and P5.4 to P5.7) Diagram
Table 6-22. Port P5 (P5.0 and P5.4 to P5.7) Pin Functions
(1)
DIRECTION
CONTROL FROM
MODULE
PnOUT.x
P5DIR.0
DVSS
P5DIR.4
DVCC
P5Sel.5
P5DIR.5
P5Sel.6
P5DIR.6
P5Sel.7
P5DIR.7
PnSel.x
PnDIR.x
P5Sel.0
P5Sel.4
MODULE X OUT
PnIN.x
MODULE X IN
P5OUT.0
DVSS
P5IN.0
STE.1
P5OUT.4
MCLK
P5IN.4
unused
DVCC
P5OUT.5
SMCLK
P5IN.5
unused
DVCC
P5OUT.6
ACLK
P5IN.6
unused
DVSS
P5OUT.7
DVSS
P5IN.7
TBOUTH (1)
The TBOUTH signal is used by port module P4, pins P4.0 to P4.6. The function of TBOUTH is most useful when used with Timer_B7.
P5SEL.1
SYNC
MM
STC
STE
0
P5DIR.1
0: Input
1: Output
1
DCM_SIMO
Pad Logic
0
P5OUT.1
(SI)MO1
From USART1
1
P5.1/SIMO1
P5IN.1
EN
SI(MO)1
To USART1
D
Figure 6-21. Port P5 (P5.1) Diagram
Detailed Description
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P5SEL.2
SYNC
MM
STC
STE
0
P5DIR.2
0: Input
1: Output
1
DCM_SOMI
Pad Logic
0
P5OUT.2
SO(MI)1
From USART1
1
P5.2/SOMI1
P5IN.2
EN
(SO)MI1
To USART1
D
Figure 6-22. Port P5 (P5.2) Diagram
P5SEL.3
SYNC
MM
STC
STE
0
P5DIR.3
0: Input
1: Output
1
DCM_SIMO
Pad Logic
0
P5OUT.3
UCLK1
From USART1
1
P5.3/UCLK1
P5IN.3
EN
D
UCLK1
To USART1
NOTE: UART mode: The UART clock can only be an input. If UART mode and UART function are selected, P5.3/UCLK1 is
always an input.
SPI slave mode: The clock applied to UCLK1 is used to shift data in and out.
SPI master mode: The clock to shift data in and out is supplied to connected devices on pin P5.3/UCLK1 (in slave
mode).
Figure 6-23. Port P5 (P5.3) Diagram
56
Detailed Description
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MSP430F1491, MSP430F1481, MSP430F1471
MSP430F135, MSP430F133
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6.9.6
SLAS272H – JULY 2000 – REVISED MAY 2018
Port P6, Input/Output With Schmitt Trigger
P6SEL.x
0
P6DIR.x
Direction Control
From Module
1
0: Input
1: Output
Pad Logic
0
P6OUT.x
Module X OUT
1
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
Bus Keeper
P6IN.x
EN
Module X IN
D
From ADC
To ADC
Note: Not implemented in the MSP430F14x1 devices
NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The
throughput current flows if the analog signal is in the range of transitions 0→1 or 1→0. The value of the throughput
current depends on the driving capability of the gate. For MSP430 MCUs, the current is approximately 100 µA.
Use P6SEL.x = 1 to prevent throughput current. P6SEL.x should be set, even if the signal at the pin is not being used
by the ADC12.
Figure 6-24. Port P6 (P6.0 to P6.7) Diagram
Table 6-23. Port P6 (P6.0 to P6.7) Pin Functions (1)
(1)
PnSel.x
PnDIR.x
DIRECTION
CONTROL FROM
MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
P6Sel.0
P6DIR.0
P6DIR.0
P6OUT.0
DVSS
P6IN.0
unused
P6Sel.1
P6DIR.1
P6DIR.1
P6OUT.1
DVSS
P6IN.1
unused
P6Sel.2
P6DIR.2
P6DIR.2
P6OUT.2
DVSS
P6IN.2
unused
P6Sel.3
P6DIR.3
P6DIR.3
P6OUT.3
DVSS
P6IN.3
unused
P6Sel.4
P6DIR.4
P6DIR.4
P6OUT.4
DVSS
P6IN.4
unused
P6Sel.5
P6DIR.5
P6DIR.5
P6OUT.5
DVSS
P6IN.5
unused
P6Sel.6
P6DIR.6
P6DIR.6
P6OUT.6
DVSS
P6IN.6
unused
P6Sel.7
P6DIR.7
P6DIR.7
P6OUT.7
DVSS
P6IN.7
unused
The signal at pins P6.x/Ax is used by the 12-bit ADC module.
Detailed Description
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MSP430F149, MSP430F148, MSP430F147
MSP430F1491, MSP430F1481, MSP430F1471
MSP430F135, MSP430F133
SLAS272H – JULY 2000 – REVISED MAY 2018
6.9.7
www.ti.com
Port JTAG (TMS, TCK, TDI/TCLK, TDO/TDI), Input/Output With Schmitt Trigger
TDO
Controlled by JTAG
Controlled by JTAG
TDO/TDI
Controlled
by JTAG
DVCC
DVCC
TDI
JTAG
Fuse
Burn and
Test Fuse
Test and
Emulation
Module
TDI/TCLK
DVCC
TMS
TMS
DVCC
TCK
TCK
During programming activity and during blowing of the fuse, the TDO/TDI pin is used
to apply the test input data for JTAG circuitry.
Figure 6-25. JTAG (TMS, TCK, TDI/TCLK, TDO/TDI) Diagram
58
Detailed Description
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MSP430F1491, MSP430F1481, MSP430F1471
MSP430F135, MSP430F133
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SLAS272H – JULY 2000 – REVISED MAY 2018
7 Device and Documentation Support
7.1
Getting Started and Next Steps
For more information on the MSP430 family of devices and the tools and libraries that are available to
help with your development, visit the Getting Started page.
7.2
Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS.
These prefixes represent evolutionary stages of product development from engineering prototypes (XMS)
through fully qualified production devices (MSP).
XMS – Experimental device that is not necessarily representative of the final device's electrical
specifications
MSP – Fully qualified production device
XMS devices are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices have been characterized fully, and the quality and reliability of the device have been
demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production
devices. TI recommends that these devices not be used in any production system because their expected
end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
temperature range, package type, and distribution format. Figure 7-1 provides a legend for reading the
complete device name.
Device and Documentation Support
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MSP430F149, MSP430F148, MSP430F147
MSP430F1491, MSP430F1481, MSP430F1471
MSP430F135, MSP430F133
SLAS272H – JULY 2000 – REVISED MAY 2018
www.ti.com
MSP 430 F 5 438 A I ZQW T -EP
Processor Family
Optional: Additional Features
MCU Platform
Optional: Tape and Reel
Device Type
Packaging
Series
Feature Set
Processor Family
MCU Platform
Optional: Temperature Range
Optional: A = Revision
CC = Embedded RF Radio
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
430 = MSP430 low-power microcontroller platform
Device Type
Memory Type
C = ROM
F = Flash
FR = FRAM
G = Flash or FRAM (Value Line)
L = No Nonvolatile Memory
Specialized Application
AFE = Analog Front End
BQ = Contactless Power
CG = ROM Medical
FE = Flash Energy Meter
FG = Flash Medical
FW = Flash Electronic Flow Meter
Series
1 = Up to 8 MHz
2 = Up to 16 MHz
3 = Legacy
4 = Up to 16 MHz with LCD
5 = Up to 25 MHz
6 = Up to 25 MHz with LCD
0 = Low-Voltage Series
Feature Set
Various levels of integration within a series
Optional: A = Revision
N/A
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging
http://www.ti.com/packaging
Optional: Tape and Reel
T = Small reel
R = Large reel
No markings = Tube or tray
Optional: Additional Features -EP = Enhanced Product (–40°C to 105°C)
-HT = Extreme Temperature Parts (–55°C to 150°C)
-Q1 = Automotive Q100 Qualified
NOTE: This figure does not represent a complete list of the available features and options, and it does not indicate that all of
these features and options are available for a given device or family.
Figure 7-1. Device Nomenclature – Part Number Decoder
60
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MSP430F135 MSP430F133
MSP430F149, MSP430F148, MSP430F147
MSP430F1491, MSP430F1481, MSP430F1471
MSP430F135, MSP430F133
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7.3
SLAS272H – JULY 2000 – REVISED MAY 2018
Tools and Software
Table 7-1 lists the debug features supported by the MSP430F14x, MSP430F14x1, and MSP430F13x
microcontrollers. See the Code Composer Studio for MSP430 User's Guide for details on the available
features.
Table 7-1. Hardware Features
MSP430
ARCHITECTURE
4-WIRE
JTAG
2-WIRE
JTAG
BREAKPOINTS
RANGE
BREAKPOINTS
CLOCK
CONTROL
STATE
SEQUENCER
TRACE
BUFFER
LPMx.5
DEBUGGING
SUPPORT
MSP430
Yes
No
3
Yes
No
No
No
No
Design Kits and Evaluation Modules
64-pin Target Development Board and MSP-FET Programmer Bundle - MSP430F1x, MSP430F2x,
MSP430F4x MCUs The MSP-FET430U64 is a powerful flash emulation tool that includes
the hardware and software required to quickly begin application development on the
MSP430 MCU. It includes a ZIF socket target board (MSP-TS430PM64) and a USB
debugging interface (MSP-FET) used to program and debug the MSP430 in-system through
the JTAG interface. The flash memory can be erased and programmed in seconds with only
a few keystrokes, and because the MSP430 flash is ultra-low power, no external power
supply is required.
MSP-TS430PM64 - 64-pin Target Development Board for MSP430F1x, MSP430F2x and MSP430F4x
MCUs
The MSP-TS430PM64 is a standalone ZIF socket target board used to program and debug
the MSP430 MCU in-system through the JTAG interface.
Software
MSP430Ware™ Software MSP430Ware software is a collection of code examples, data sheets, and
other design resources for all MSP430 devices delivered in a convenient package. In
addition to providing a complete collection of existing MSP430 MCU design resources,
MSP430Ware software also includes a high-level API called MSP Driver Library. This library
makes it easy to program MSP430 hardware. MSP430Ware software is available as a
component of CCS or as a stand-alone package.
MSP430F13x, MSP430F14x, MSP430F15x, MSP430F16x Code Examples C Code examples are
available for every MSP device that configures each of the integrated peripherals for various
application needs.
Bootloader (BSL) for MSP low-power microcontrollers The bootloader (BSL) is an application built into
MSP low-power microcontrollers. It lets the user communicate with the device to read from
and write to its memory. This feature is primarily used for programming the device, during
prototyping, final production, and in service. Both the programmable memory (flash memory)
and the data memory (RAM) can be modified as required.
Fixed Point Math Library for MSP The MSP IQmath and Qmath Libraries are a collection of highly
optimized and high-precision mathematical functions for C programmers to seamlessly port a
floating-point algorithm into fixed-point code on MSP430 and MSP432 devices. These
routines are typically used in computationally intensive real-time applications where optimal
execution speed, high accuracy, and ultra-low energy are critical. By using the IQmath and
Qmath libraries, it is possible to achieve execution speeds considerably faster and energy
consumption considerably lower than equivalent code written using floating-point math.
Development Tools
Code Composer Studio™ Integrated Development Environment for MSP Microcontrollers
Code
Composer Studio (CCS) integrated development environment (IDE) supports all MSP
microcontroller devices. CCS comprises a suite of embedded software utilities used to
develop and debug embedded applications. CCS includes an optimizing C/C++ compiler,
source code editor, project build environment, debugger, profiler, and many other features.
Command-Line Programmer MSP Flasher is an open-source shell-based interface for programming
MSP microcontrollers through a FET programmer or eZ430 using JTAG or Spy-Bi-Wire
(SBW) communication. MSP Flasher can download binary files (.txt or .hex) directly to the
MSP microcontroller without an IDE.
Device and Documentation Support
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MSP430F135, MSP430F133
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www.ti.com
MSP MCU Programmer and Debugger The MSP-FET is a powerful emulation development tool – often
called a debug probe – which lets users quickly begin application development on MSP lowpower MCUs. Creating MCU software usually requires downloading the resulting binary
program to the MSP device for validation and debugging.
MSP-GANG Production Programmer The MSP Gang Programmer is an MSP430 or MSP432 device
programmer that can program up to eight identical MSP430 or MSP432 flash or FRAM
devices at the same time. The MSP Gang Programmer connects to a host PC using a
standard RS-232 or USB connection and provides flexible programming options that let the
user fully customize the process.
7.4
Documentation Support
The following documents describe the MSP430F14x, MSP430F14x1, and MSP430F13x MCUs. Copies of
these documents are available on the Internet at www.ti.com.
Receiving Notification of Document Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for
your device on ti.com (for links to product folders, see Section 7.5). In the upper right corner, click the
"Alert me" button. This registers you to receive a weekly digest of product information that has changed (if
any). For change details, check the revision history of any revised document.
Errata
MSP430F149 Device Erratasheet Describes the known exceptions to the functional specifications.
MSP430F1491 Device Erratasheet Describes the known exceptions to the functional specifications.
MSP430F148 Device Erratasheet Describes the known exceptions to the functional specifications.
MSP430F1481 Device Erratasheet Describes the known exceptions to the functional specifications.
MSP430F147 Device Erratasheet Describes the known exceptions to the functional specifications.
MSP430F1471 Device Erratasheet Describes the known exceptions to the functional specifications.
MSP430F135 Device Erratasheet Describes the known exceptions to the functional specifications.
MSP430F133 Device Erratasheet Describes the known exceptions to the functional specifications.
User's Guides
MSP430x1xx Family User's Guide Detailed description of all modules and peripherals available in this
device family.
MSP430 Flash Device Bootloader (BSL) User's Guide The MSP430™ bootloader (BSL) lets users
communicate with embedded memory in the MSP430 microcontroller (MCU) during the
prototyping phase, final production, and in service. Both the programmable memory (flash
memory) and the data memory (RAM) can be modified as required.
MSP430 Programming With the JTAG Interface This document describes the functions that are
required to erase, program, and verify the memory module of the MSP430 flash-based and
FRAM-based microcontroller families using the JTAG communication port. In addition, it
describes how to program the JTAG access security fuse that is available on all MSP430
devices. This document describes device access using both the standard 4-wire JTAG
interface and the 2-wire JTAG interface, which is also referred to as Spy-Bi-Wire (SBW).
MSP430 Hardware Tools User's Guide This manual describes the hardware of the TI MSP-FET430
Flash Emulation Tool (FET). The FET is the program development tool for the MSP430 ultralow-power microcontroller. Both available interface types, the parallel port interface and the
USB interface, are described.
62
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MSP430F1491, MSP430F1481, MSP430F1471
MSP430F135, MSP430F133
www.ti.com
SLAS272H – JULY 2000 – REVISED MAY 2018
Application Reports
MSP430 32-kHz Crystal Oscillators Selection of the right crystal, correct load circuit, and proper board
layout are important for a stable crystal oscillator. This application report summarizes crystal
oscillator function and explains the parameters to select the correct crystal for MSP430 ultralow-power operation. In addition, hints and examples for correct board layout are given. The
document also contains detailed information on the possible oscillator tests to ensure stable
oscillator operation in mass production.
Software Coding Techniques for MSP430™ MCUs
This application report describes
techniques and related topics of interest to programmers of MSP430 MCUs.
software
General Oversampling of MSP ADCs for Higher Resolution
Multiple
MSP430
ultra-low-power
microcontrollers offer ADCs to convert physical quantities into digital numbers, a function that
is widely used across numerous applications. There are times, however, when a customer
design demands a higher resolution than the ADC of the selected MSP can offer. This
application report describes how an oversampling method can be incorporated to increase
ADC resolution past the currently available number of bits.
MSP430 System-Level ESD Considerations System-Level ESD has become increasingly demanding
with silicon technology scaling towards lower voltages and the need for designing costeffective and ultra-low-power components. This application report addresses three different
ESD topics to help board designers and OEMs understand and design robust system-level
designs.
7.5
Related Links
Table 7-2 lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 7-2. Related Links
7.6
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
MSP430F149
Click here
Click here
Click here
Click here
Click here
MSP430F1491
Click here
Click here
Click here
Click here
Click here
MSP430F148
Click here
Click here
Click here
Click here
Click here
MSP430F1481
Click here
Click here
Click here
Click here
Click here
MSP430F147
Click here
Click here
Click here
Click here
Click here
MSP430F1471
Click here
Click here
Click here
Click here
Click here
MSP430F135
Click here
Click here
Click here
Click here
Click here
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At
e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow
engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
7.7
Trademarks
MSP430, MSP430Ware, Code Composer Studio, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
Device and Documentation Support
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MSP430F135, MSP430F133
SLAS272H – JULY 2000 – REVISED MAY 2018
7.8
www.ti.com
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
7.9
Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
authorization from U.S. Department of Commerce and other competent Government authorities to the
extent required by those laws.
7.10 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
64
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MSP430F1491, MSP430F1481, MSP430F1471
MSP430F135, MSP430F133
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SLAS272H – JULY 2000 – REVISED MAY 2018
8 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Mechanical, Packaging, and Orderable Information
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MSP430F135 MSP430F133
Copyright © 2000–2018, Texas Instruments Incorporated
65
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
MSP430F133IPAG
ACTIVE
TQFP
PAG
64
160
RoHS & Green
NIPDAU
Level-4-260C-72 HR
-40 to 85
M430F133
Samples
MSP430F133IPM
ACTIVE
LQFP
PM
64
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F133
Samples
MSP430F133IPMR
ACTIVE
LQFP
PM
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F133
Samples
MSP430F133IRTDT
ACTIVE
VQFN
RTD
64
250
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
M430F133
Samples
MSP430F135IPAG
ACTIVE
TQFP
PAG
64
160
RoHS & Green
NIPDAU
Level-4-260C-72 HR
-40 to 85
M430F135
REV #
Samples
MSP430F135IPM
ACTIVE
LQFP
PM
64
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F135
REV #
Samples
MSP430F135IPMR
ACTIVE
LQFP
PM
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F135
REV #
Samples
MSP430F135IRTDR
ACTIVE
VQFN
RTD
64
2500
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
M430F135
Samples
MSP430F135IRTDT
ACTIVE
VQFN
RTD
64
250
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
M430F135
Samples
MSP430F1471IPM
ACTIVE
LQFP
PM
64
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F1471
REV #
Samples
MSP430F1471IPMR
ACTIVE
LQFP
PM
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F1471
REV #
Samples
MSP430F1471IRTDT
ACTIVE
VQFN
RTD
64
250
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
M430F1471
Samples
MSP430F147IPAG
ACTIVE
TQFP
PAG
64
160
RoHS & Green
NIPDAU
Level-4-260C-72 HR
-40 to 85
M430F147
REV #
Samples
MSP430F147IPM
ACTIVE
LQFP
PM
64
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F147
REV #
Samples
MSP430F147IPMR
ACTIVE
LQFP
PM
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F147
REV #
Samples
MSP430F147IPMR-KAM
ACTIVE
LQFP
PM
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F147
REV #
Samples
MSP430F147IPMRG4
ACTIVE
LQFP
PM
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F147
REV #
Samples
MSP430F147IRTDR
ACTIVE
VQFN
RTD
64
2500
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
M430F147
Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
14-Oct-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
MSP430F147IRTDT
ACTIVE
VQFN
RTD
64
250
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
M430F147
Samples
MSP430F1481IPM
ACTIVE
LQFP
PM
64
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F1481
Samples
MSP430F1481IPMR
ACTIVE
LQFP
PM
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F1481
Samples
MSP430F1481IRTDT
ACTIVE
VQFN
RTD
64
250
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
M430F1481
Samples
MSP430F148IPAG
ACTIVE
TQFP
PAG
64
160
RoHS & Green
NIPDAU
Level-4-260C-72 HR
-40 to 85
M430F148
Samples
MSP430F148IPM
ACTIVE
LQFP
PM
64
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F148
REV #
Samples
MSP430F148IPMR
ACTIVE
LQFP
PM
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F148
REV #
Samples
MSP430F148IRTDR
ACTIVE
VQFN
RTD
64
2500
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
M430F148
Samples
MSP430F148IRTDT
ACTIVE
VQFN
RTD
64
250
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
M430F148
Samples
MSP430F1491IPM
ACTIVE
LQFP
PM
64
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F1491
Samples
MSP430F1491IPMR
ACTIVE
LQFP
PM
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F1491
Samples
MSP430F1491IRTDR
ACTIVE
VQFN
RTD
64
2500
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
M430F1491
Samples
MSP430F1491IRTDT
ACTIVE
VQFN
RTD
64
250
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
M430F1491
Samples
MSP430F149IPAG
ACTIVE
TQFP
PAG
64
160
RoHS & Green
NIPDAU
Level-4-260C-72 HR
-40 to 85
M430F149
REV #
Samples
MSP430F149IPAGR
ACTIVE
TQFP
PAG
64
1500
RoHS & Green
NIPDAU
Level-4-260C-72 HR
-40 to 85
M430F149
REV #
Samples
MSP430F149IPM
ACTIVE
LQFP
PM
64
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F149
REV #
Samples
MSP430F149IPMG4
ACTIVE
LQFP
PM
64
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F149
REV #
Samples
MSP430F149IPMR
ACTIVE
LQFP
PM
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F149
REV #
Samples
MSP430F149IPMRG4
ACTIVE
LQFP
PM
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F149
REV #
Samples
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
14-Oct-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
MSP430F149IRTDR
ACTIVE
VQFN
RTD
64
2500
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
M430F149
Samples
MSP430F149IRTDT
ACTIVE
VQFN
RTD
64
250
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
M430F149
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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