MSP430F21x2
SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012
www.ti.com
MIXED SIGNAL MICROCONTROLLER
FEATURES
1
•
•
2
•
•
•
•
•
•
•
Low Supply Voltage Range: 1.8 V to 3.6 V
Ultra-Low Power Consumption
– Active Mode: 250 µA at 1 MHz, 2.2 V
– Standby Mode: 0.7 µA
– Off Mode (RAM Retention): 0.1 µA
Ultra-Fast Wake-Up From Standby Mode in
Less Than 1 µs
16-Bit RISC Architecture, 62.5-ns Instruction
Cycle Time
Basic Clock Module Configurations
– Internal Frequencies up to 16 MHz With
Four Calibrated Frequencies to ±1%
– Internal Very-Low-Power Low-Frequency
Oscillator
– 32-kHz Crystal
– High-Frequency (HF) Crystal up to 16 MHz
– Resonator
– External Digital Clock Source
– External Resistor
16-Bit Timer0_A3 With Three Capture/Compare
Registers
16-Bit Timer1_A2 With Two Capture/Compare
Registers
On-Chip Comparator for Analog Signal
Compare Function or Slope Analog-to-Digital
(A/D) Conversion
10-Bit 200-ksps A/D Converter With Internal
Reference, Sample-and-Hold, Autoscan, and
Data Transfer Controller
•
•
•
•
•
•
•
•
Universal Serial Communication Interface
– Enhanced UART Supporting Auto-Baudrate
Detection (LIN)
– IrDA Encoder and Decoder
– Synchronous SPI
– I2C™
Brownout Detector
Serial Onboard Programming, No External
Programming Voltage Needed, Programmable
Code Protection by Security Fuse
Bootstrap Loader
On-Chip Emulation Module
Family Members Include:
– MSP430F2132
– 8KB + 256B Flash Memory
– 512B RAM
– MSP430F2122
– 4KB + 256B Flash Memory
– 512B RAM
– MSP430F2112
– 2KB + 256B Flash Memory
– 256B RAM
Available in 28-Pin TSSOP (PW) and 32-Pin
QFN (RHB or RTV) Packages (See Table 1)
For Complete Module Descriptions, See the
MSP430x2xx Family User's Guide, Literature
Number SLAU144
DESCRIPTION
The Texas Instruments MSP430™ family of ultra-low-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs.
The MSP430F21x2 series is an ultra-low-power microcontroller with two built-in 16-bit timers, a fast 10-bit A/D
converter with integrated reference and a data transfer controller (DTC), a comparator, built-in communication
capability using the universal serial communication interface, and up to 24 I/O pins.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MSP430 is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2012, Texas Instruments Incorporated
MSP430F21x2
SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Table 1. Available Options
TA
PACKAGED DEVICES (1) (2)
PLASTIC 28-PIN TSSOP (PW)
PLASTIC 32-PIN QFN (RHB)
PLASTIC 32-PIN QFN (RTV)
MSP430F2112IPW
MSP430F2112IRHB
MSP430F2112IRTV
MSP430F2122IPW
MSP430F2122IRHB
MSP430F2122IRTV
-40°C to 85°C
-40°C to 105°C
(1)
(2)
MSP430F2132IPW
MSP430F2132IRHB
MSP430F2132IRTV
MSP430F2112TPW
MSP430F2112TRHB
MSP430F2112TRTV
MSP430F2122TPW
MSP430F2122TRHB
MSP430F2122TRTV
MSP430F2132TPW
MSP430F2132TRHB
MSP430F2132TRTV
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Development Tool Support
All MSP430 microcontrollers include an Embedded Emulation Module (EEM) that allows advanced debugging
and programming through easy-to-use development tools. Recommended hardware options include:
• Debugging and Programming Interface
– MSP-FET430UIF (USB)
– MSP-FET430PIF (Parallel Port)
• Debugging and Programming Interface with Target Board
– MSP-FET430U28 (PW package)
• Production Programmer
– MSP-GANG430
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MSP430F21x2
SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012
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Device Pinout, PW Package
TEST/SBWTCK
DVCC
P2.5/ROSC/CA5
DVSS
XOUT/P2.7/CA7
XIN/P2.6/CA6
RST/NMI/SBWTDIO
P2.0/ACLK/A0/CA2
P2.1/TAINCLK/SMCLK/A1/CA3
P2.2/TA0.0/A2/CA4/CAOUT
P3.0/UCB0STE/UCA0CLK/A5
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P1.7/TA0.2/TDO/TDI
P1.6/TA0.1/TDI/TCLK
P1.5/TA0.0/TMS
P1.4/SMCLK/TCK
P1.3/TA0.2
P1.2/TA0.1
P1.1/TA0.0/TA1.0
P1.0/TACLK/ADC10CLK/CAOUT
P2.4/TA0.2/A4/VREF+/VeREF+/CA1
P2.3/TA0.1/A3/VREF-/VeREF-/CA0
P3.7/TA1.1/A7
P3.6/TA1.0/A6
P3.5/UCA0RXD/UCA0SOMI
P3.4/UCA0TXD/UCA0SIMO
28
27
26
25
24
23
22
21
20
19
18
17
16
15
P2.5/ROSC/CA5
NC
DVCC
TEST/SBWTCK
P1.7/TA0.2/TDO/TDI
P1.6/TA0.1/TDI/TCLK
P1.5/TA0.0/TMS
P1.4/SMCLK/TCK
Device Pinout, RHB or RTV Package
32 31 30 29 28 27 26 25
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9 10 11 12 13 14 15 16
P1.3/TA0.2
P1.2/TA0.1
P1.1/TA0.0/TA1.0
P1.0/TACLK/ADC10CLK/CAOUT
NC
P2.4/TA0.2/A4/VREF+/VeREF+/CA1
P2.3/TA0.1/A3/VREF-/VeREF-/CA0
NC
P3.0/UCB0STE/UCA0CLK/A5
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
P3.6/TA1.0/A6
P3.7/TA1.1/A7
DVSS
XOUT/P2.7/CA7
XIN/P2.6/CA6
NC
RST/NMI/SBWTDIO
P2.0/ACLK/A0/CA2
P2.1/TAINCLK/SMCLK/A1/CA3
P2.2/TA0.0/A2/CA4/CAOUT
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Functional Block Diagram
XOUT
XIN
DVCC
D/AVSS
AVCC
P3.x
P2.x
P1.x
8
8
8
ACLK
Basic Clock
System+
SMCLK
Flash
RAM
8kB
4kB
2kB
512B
512B
256B
MCLK
16MHz
CPU
incl. 16
Registers
ADC10
10-bit
8 Channels
Autoscan
DTC
Port P1
Port P2
Port P3
8 I/O
Interrupt
capability
pullup/down
resistors
8 I/O
Interrupt
capability
pullup/down
resistors
pullup/
pulldown
resistors
MAB
MDB
Emulation
2BP
JTAG
Interface
8 I/O
Brownout
Protection
Comp_A+
Watchdog
WDT+
15-Bit
Timer0_A3
Timer1_A2
3 CC
Registers
2 CC
Registers
USCI A0
UART/LIN,
IrDA, SPI
USCI B0
SPI, I2C
Spy-Bi Wire
RST/NMI
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MSP430F21x2
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Table 2. Terminal Functions
TERMINAL
NO.
NAME
PW
I/O
DESCRIPTION
RHB,
RTV
General-purpose digital I/O pin
Timer0_A3, clock signal TACLK input
P1.0/TACLK/ADC10CLK/CAOUT
21
21
I/O
Timer1_A2, clock signal TACLK input
ADC10, conversion clock
Comparator_A+ output
General-purpose digital I/O pin
P1.1/TA0.0/TA1.0
22
22
I/O
Timer0_A3, capture: CCI0A input, compare: Out0 Output
Timer1_A2, capture: CCI0A input
P1.2/TA0.1
23
23
I/O
P1.3/TA0.2
24
24
I/O
P1.4/SMCLK/TCK
25
25
I/O
General-purpose digital I/O pin
Timer0_A3, capture: CCI1A input, compare: Out1 Output
General-purpose digital I/O pin
Timer0_A3, capture: CCI2A input, compare: Out2 Output
General-purpose digital I/O pin
SMCLK signal output
Test Clock input for device programming and test
General-purpose digital I/O pin
P1.5/TA0.0/TMS
26
26
I/O
Timer0_A3, compare: Out0 Output
JTAG test mode select, input terminal for device programming and test
General-purpose digital I/O pin
P1.6/TA0.1/TDI/TCLK
27
27
I/O
Timer0_A3, compare: Out1 Output
JTAG test data input or test clock input in programming an test
General-purpose digital I/O pin
P1.7/TA0.2/TDO/TDI
28
28
I/O
Timer0_A3, compare: Out2 Output
JTAG test data output terminal or test data input in programming an test
General-purpose digital I/O pin
P2.0/ACLK/A0/CA2
8
6
I/O
ACLK signal output
ADC10 analog input A0
Comparator_A+ input
General-purpose digital I/O pin
SMCLK signal output
P2.1/TAINCLK/SMCLK/A1/CA3
9
7
I/O
Timer0_A3, clock signal TACLK input
Timer1_A2, clock signal TACLK input
ADC10 analog input A1
Comparator_A+ input
General-purpose digital I/O pin
Timer0_A3, capture: CCI0B input, compare: Out0 Output
P2.2/TA0.0/A2/CA4/CAOUT
10
8
I/O
ADC10 analog input A2
Comparator_A+ input
Comparator_A+ output
General-purpose digital I/O pin
P2.3/TA0.1/A3/VREF-/VeREF-/CA0
19
18
I/O
Timer0_A3, compare: Out1 Output
ADC10 analog input A3 / negative reference
Comparator_A+ input
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Table 2. Terminal Functions (continued)
TERMINAL
NO.
NAME
PW
I/O
DESCRIPTION
RHB,
RTV
General-purpose digital I/O pin
P2.4/TA0.2/A4/VREF+/VeREF+/CA1
20
19
I/O
Timer0_A3, compare: Out2 Output
ADC10 analog input A4 / positive reference
Comparator_A+ input
Input terminal of crystal oscillator
XIN/P2.6/CA6
6
3
I/O
General-purpose digital I/O pin
Comparator_A+ input
Output terminal of crystal oscillator
XOUT/P2.7/CA7
5
2
I/O
General-purpose digital I/O pin
Comparator_A+ input
General-purpose digital I/O pin
P3.0/UCB0STE/UCA0CLK/A5
11
9
I/O
USCI_B0 slave transmit enable/USCI_A0 clock input/output
ADC10 analog input A5
P3.1/UCB0SIMO/UCB0SDA
12
10
I/O
P3.2/UCB0SOMI/UCB0SCL
13
11
I/O
P3.3/UCB0CLK/UCA0STE
14
12
I/O
P3.4/UCA0TXD/UCA0SIMO
15
13
I/O
P3.5/UCA0RXD/UCA0SOMI
16
14
I/O
P3.6/TA1.0/A6
17
15
I/O
General-purpose digital I/O pin
USCI_B0 slave in/master out in SPI mode, SDA I2C data in I2C mode
General-purpose digital I/O pin
USCI_B0 slave out/master in in SPI mode, SCL I2C clock in I2C mode
General-purpose digital I/O
USCI_B0 clock input/output, USCI_A0 slave transmit enable
General-purpose digital I/O pin
USCI_A0 transmit data output in UART mode, slave data in/master out
in SPI mode
General-purpose digital I/O pin
USCI_A0 receive data input in UART mode, slave data out/master in in
SPI mode
General-purpose digital I/O pin
Timer1_A2, capture: CCI0B input, compare: Out0 Output
ADC10 analog input A6
General-purpose digital I/O pin
P3.7/TA1.1/A7
18
16
I/O
Timer1_A2, capture: CCI1A input, compare: Out1 Output
ADC10 analog input A7
RST/NMI/SBWTDIO
7
5
I
TEST/SBWTCK
1
29
I
P2.5/ROSC/CA5
3
32
I/O
Reset or nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
Selects test mode for JTAG pins on Port 1. The device protection fuse is
connected to TEST.
General-purpose digital I/O pin
Input for external resistor defining the DCO nominal frequency
Comparator_A+ input
DVCC
2
30
Digital supply voltage
DVSS
4
1
Digital supply voltage
NC
NA
4, 17, 20,
31
QFN Pad
NA
Pad
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Not connected internally. Connection to VSS is recommended.
QFN package pad (RHB, RTV packages). Connection to DVSS is
recommended.
Copyright © 2007–2012, Texas Instruments Incorporated
MSP430F21x2
SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012
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SHORT-FORM DESCRIPTION
CPU
The MSP430™ CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
SR/CG1/R2
Status Register
Constant Generator
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
Instruction Set
General-Purpose Register
R11
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 3 shows examples of the three types of
instruction formats; Table 4 shows the address
modes.
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
The CPU is integrated with 16 registers that provide
reduced
instruction
execution
time.
The
register-to-register operation execution time is one
cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator respectively. The remaining
registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses and can be handled with
all instructions.
Table 3. Instruction Word Formats
EXAMPLE
OPERATION
Dual operands, source-destination
INSTRUCTION FORMAT
ADD R4,R5
R4 + R5 → R5
Single operands, destination only
CALL R8
PC → (TOS), R8 → PC
JNE
Jump-on-equal bit = 0
Relative jump, unconditional/conditional
Table 4. Address Mode Descriptions
ADDRESS MODE
D
(2)
SYNTAX
EXAMPLE
OPERATION
Register
✓
✓
MOV Rs,Rd
MOV R10,R11
R10 → R11
Indexed
✓
✓
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
M(2+R5) → M(6+R6)
Symbolic (PC relative)
✓
✓
MOV EDE,TONI
M(EDE) → M(TONI)
Absolute
✓
✓
MOV &MEM,&TCDAT
M(MEM) → M(TCDAT)
Indirect
✓
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) → M(Tab+R6)
Indirect autoincrement
✓
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) → R11
R10 + 2 → R10
Immediate
✓
MOV #X,TONI
MOV #45,TONI
#45 → M(TONI)
(1)
(2)
S
(1)
S = source
D = destination
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Operating Modes
The MSP430 microcontrollers have one active mode and five software-selectable low-power modes of operation.
An interrupt event can wake up the device from any of the five low-power modes, service the request, and
restore back to the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
• Active mode (AM)
– All clocks are active.
• Low-power mode 0 (LPM0)
– CPU is disabled.
– ACLK and SMCLK remain active. MCLK is disabled.
• Low-power mode 1 (LPM1)
– CPU is disabled ACLK and SMCLK remain active. MCLK is disabled.
– DCO dc-generator is disabled if DCO not used in active mode.
• Low-power mode 2 (LPM2)
– CPU is disabled.
– MCLK and SMCLK are disabled.
– DCO dc-generator remains enabled.
– ACLK remains active.
• Low-power mode 3 (LPM3)
– CPU is disabled.
– MCLK and SMCLK are disabled.
– DCO dc-generator is disabled.
– ACLK remains active.
• Low-power mode 4 (LPM4)
– CPU is disabled.
– ACLK is disabled.
– MCLK and SMCLK are disabled.
– DCO dc-generator is disabled.
– Crystal oscillator is stopped.
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Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range of 0xFFFF to 0xFFC0.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0xFFFE) contains 0xFFFF (for example, if flash is not programmed), the
CPU goes into LPM4 immediately after power up.
Table 5. Interrupt Vector Addresses
INTERRUPT SOURCE
INTERRUPT FLAG
Power-up
PORIFG
External reset
RSTIFG
Watchdog
WDTIFG
Flash key violation
KEYV (1)
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Reset
0xFFFE
31, highest
0xFFFC
30
PC out of range (2)
NMI
NMIIFG
(Non)maskable
Oscillator fault
OFIFG
(Non)maskable
Flash memory access violation
ACCVIFG (1) (3)
(Non)maskable
Timer1_A2
TA1CCR0 CCIFG (4)
Maskable
0xFFFA
29
Maskable
0xFFF8
28
CAIFG
Maskable
0xFFF6
27
Watchdog timer
WDTIFG
Maskable
0xFFF4
26
Timer0_A3
TA0CCR0 CCIFG (4)
Maskable
0xFFF2
25
Maskable
0xFFF0
24
UCA0RXIFG,
UCB0RXIFG (1) (5)
Maskable
0xFFEE
23
USCI_B0 I2C receive/transmit
UCA0TXIFG,
UCB0TXIFG (1) (6)
Maskable
0xFFEC
22
ADC10
ADC10IFG (4)
Maskable
0xFFEA
21
0xFFE8
20
I/O port P2 (eight flags)
P2IFG.0 to P2IFG.7 (1) (4)
Maskable
0xFFE6
19
I/O port P1 (eight flags)
P1IFG.0 to P1IFG.7 (1) (4)
Maskable
0xFFE4
18
0xFFE2
17
0xFFE0
16
Timer1_A2
Comparator_A+
TA1CCR1 CCIFG,
TA1CTL TAIFG (1) (4)
TA0CCR1 CCIFG,
Timer0_A3
TA0CCR2 CCIFG,
TA0CTL TAIFG
USCI_A0/USCI_B0 receive
USCI_B0 I2C status
USCI_A0/USCI_B0 transmit
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(1) (4)
See
(7)
0xFFDE
15
See
(8)
0xFFDC to 0xFFC0
14 to 0, lowest
Multiple source flags
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0x0000 to 0x01FF) or
from within unused address range.
(non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.
Interrupt flags are located in the module.
In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG
In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG
This location is used as bootstrap loader security key (BSLSKEY).
A 0xAA55 at this location disables the BSL completely.
A zero (0x0) disables the erasure of the flash if an invalid password is supplied.
The interrupt vectors at addresses 0xFFDC to 0xFFC0 are not used in this device and can be used for regular program code if
necessary.
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Special Function Registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
Legend
rw
rw-0, 1
rw-(0), (1)
Bit can be read and written.
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device.
Table 6. Interrupt Enable 1
Address
7
6
00h
WDTIE
OFIE
NMIIE
ACCVIE
5
4
1
0
ACCVIE
NMIIE
3
2
OFIE
WDTIE
rw-0
rw-0
rw-0
rw-0
Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval
timer mode.
Oscillator fault interrupt enable
(Non)maskable interrupt enable
Flash access violation interrupt enable
Table 7. Interrupt Enable 2
Address
7
6
5
4
01h
UCA0RXIE
UCA0TXIE
UCB0RXIE
UCB0TXIE
3
2
1
0
UCB0TXIE
UCB0RXIE
UCA0TXIE
UCA0RXIE
rw-0
rw-0
rw-0
rw-0
USCI_A0 receive-interrupt enable
USCI_A0 transmit-interrupt enable
USCI_B0 receive-interrupt enable
USCI_B0 transmit-interrupt enable
Table 8. Interrupt Flag Register 1
Address
7
6
5
02h
WDTIFG
OFIFG
RSTIFG
PORIFG
NMIIFG
4
3
2
1
0
NMIIFG
RSTIFG
PORIFG
OFIFG
WDTIFG
rw-0
rw-(0)
rw-(1)
rw-1
rw-(0)
Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
Flag set on oscillator fault
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power up.
Power-on reset interrupt flag. Set on VCC power up.
Set via RST/NMI pin
Table 9. Interrupt Flag Register 2
Address
7
6
03h
UCA0RXIFG
UCA0TXIFG
UCB0RXIFG
UCB0TXIFG
10
5
4
3
2
1
0
UCB0TXIFG
UCB0RXIFG
UCA0TXIFG
UCA0RXIFG
rw-1
rw-0
rw-1
rw-0
USCI_A0 receive-interrupt flag
USCI_A0 transmit-interrupt flag
USCI_B0 receive-interrupt flag
USCI_B0 transmit-interrupt flag
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Memory Organization
Table 10. Memory Organization
MSP430F2112
Memory
MSP430F2122
MSP430F2132
Size
2 KB
4 KB
8 KB
Main: interrupt vector
Flash
0xFFFF to 0xFFC0
0xFFFF to 0xFFC0
0xFFFF to 0xFFC0
Main: code memory
Flash
0xFFFF to 0xF800
0xFFFF to 0xF000
0xFFFF to 0xE000
Information memory
Boot memory
RAM
Size
256 Byte
256 Byte
256 Byte
Flash
0x10FFh to 0x1000
0x10FFh to 0x1000
0x10FFh to 0x1000
Size
1 KB
1 KB
1 KB
ROM
0x0FFF to 0x0C00
0x0FFF to 0x0C00
0x0FFF to 0x0C00
Size
Peripherals
256 B
512 Byte
512 Byte
0x02FF to 0x0200
0x03FF to 0x0200
0x03FF to 0x0200
16-bit
0x01FF to 0x0100
0x01FF to 0x0100
0x01FF to 0x0100
8-bit
0x00FF to 0x0010
0x00FF to 0x0010
0x00FF to 0x0010
8-bit SFR
0x000F to 0x0000
0x000F to 0x0000
0x000F to 0x0000
Bootstrap Loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the MSP430 Programming Via the Bootstrap
Loader User’s Guide, literature number SLAU319.
Table 11. BSL Function Pins
BSL FUNCTION
PW PACKAGE PINS
RHB, RTV PACKAGE PINS
Data transmit
22 - P1.1
22 - P1.1
Data receive
10 - P2.2
8 - P2.2
Flash Memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually, or as a group with segments 0 to n.
Segments A to D are also called information memory.
• Segment A contains calibration data. After reset, segment A is protected against programming and erasing. It
can be unlocked, but care should be taken not to erase this segment if the device-specific calibration data is
required.
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Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
Oscillator and System Clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very-low-power low-frequency oscillator, an internal digitally-controlled oscillator (DCO), and
a high-frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low
system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in
less than 1 µs. The basic clock module provides the following clock signals:
• Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high-frequency crystal, or the internal
very-low-power LF oscillator.
• Main clock (MCLK), the system clock used by the CPU.
• Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A.
Calibration Data Stored in Information Memory Segment A
Calibration data is stored for both the DCO and for ADC10 organized in a tag-length-value (TLV) structure.
Table 12. Tags Used by the ADC Calibration Tags
ADDRESS
VALUE
TAG_DCO_30
NAME
0x10F6
0x01
DCO frequency calibration at VCC = 3 V and TA = 30°C at calibration
TAG_ADC10_1
0x10DA
0x08
ADC10_1 calibration tag
-
0xFE
Identifier for empty memory areas
TAG_EMPTY
DESCRIPTION
Table 13. Labels Used by the ADC Calibration Tags
LABEL
CONDITION AT CALIBRATION / DESCRIPTION
SIZE
ADDRESS
OFFSET
0x0010
CAL_ADC_25T85
INCHx = 0x1010, REF2_5 = 1, TA = 85°C
word
CAL_ADC_25T30
INCHx = 0x1010, REF2_5 = 1, TA = 30°C
word
0x000E
CAL_ADC_25VREF_FACTOR
REF2_5 = 1, TA = 30°C, IVREF+ = 1 mA
word
0x000C
CAL_ADC_15T85
INCHx = 0x1010, REF2_5 = 0, TA = 85°C
word
0x000A
CAL_ADC_15T30
INCHx = 0x1010, REF2_5 = 0, TA = 30°C
word
0x0008
CAL_ADC_15VREF_FACTOR
REF2_5 = 0, TA = 30°C, IVREF+ = 0.5 mA
word
0x0006
CAL_ADC_OFFSET
External VREF = 1.5 V, fADC10CLK = 5 MHz
word
0x0004
CAL_ADC_GAIN_FACTOR
External VREF = 1.5 V, fADC10CLK = 5 MHz
word
0x0002
CAL_BC1_1MHz
-
byte
0x0009
CAL_DCO_1MHz
-
byte
0x0008
CAL_BC1_8MHz
-
byte
0x0007
CAL_DCO_8MHz
-
byte
0x0006
CAL_BC1_12MHz
-
byte
0x0005
CAL_DCO_12MHz
-
byte
0x0004
CAL_BC1_16MHz
-
byte
0x0003
CAL_DCO_16MHz
-
byte
0x0002
12
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Brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and
power off.
Digital I/O
There are three 8-bit I/O ports implemented—ports P1, P2, and P3:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt condition is possible.
• Edge-selectable interrupt input capability for all eight bits of port P1 and P2.
• Read/write access to port-control registers is supported by all instructions.
• Each I/O has an individually programmable pullup/pulldown resistor.
The MSP430F21x2 devices provide up to 24 total port I/O pins available externally. See the device pinout for
more information.
Watchdog Timer (WDT+)
The primary function of the WDT+ module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be disabled or configured as an interval timer and can generate interrupts at
selected time intervals.
ADC10
The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion
result handling allowing ADC samples to be converted and stored without any CPU intervention.
Comparator_A+
The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
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Timer0_A3
Timer0_A3 is a 16-bit timer/counter with three capture/compare registers. Timer0_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer0_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 14. Timer0_A3 Signal Connections
INPUT PIN NUMBER
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
NA
CCR0
TA0
PW
RHB, RTV
21 - P1.0
21 - P1.0
TACLK
TACLK
ACLK
ACLK
OUTPUT PIN NUMBER
PW
RHB, RTV
SMCLK
SMCLK
9 - P2.1
7 - P2.1
TAINCLK
INCLK
22 - P1.1
22 - P1.1
TA0
CCI0A
22 - P1.1
22 - P1.1
10 - P2.2
8 - P2.2
TA0
CCI0B
26 - P1.5
26 - P1.5
DVSS
GND
10 - P2.2
8 - P2.2
DVCC
VCC
ADC10
(internal)
ADC10
(internal)
23 - P1.2
23 - P1.2
23 - P1.2
24 - P1.3
23 - P1.2
TA1
CCI1A
CAOUT
(internal)
CCI1B
27 - P1.6
27 - P1.6
DVSS
GND
19 - P2.3
18 - P2.3
DVCC
VCC
ADC10
(internal)
ADC10
(internal)
TA2
CCI2A
24 - P1.3
24 - P1.3
ACLK (internal)
CCI2B
28 - P1.7
28 - P1.7
DVSS
GND
20 - P2.4
19 - P2.4
VCC
ADC10
(internal)
ADC10
(internal)
24 - P1.3
DVCC
14
MODULE
INPUT NAME
DEVICE INPUT
SIGNAL
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CCR1
CCR2
TA1
TA2
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Timer1_A2
Timer1_A2 is a 16-bit timer/counter with two capture/compare registers. Timer1_A2 can support multiple
capture/compares, PWM outputs, and interval timing. Timer1_A2 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 15. Timer1_A2 Signal Connections
INPUT PIN NUMBER
MODULE
INPUT NAME
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
NA
CCR0
CCR1
PW
RHB, RTV
DEVICE INPUT
SIGNAL
21 - P1.0
21 - P1.0
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
9 - P2.1
7 - P2.1
TAINCLK
INCLK
22 - P1.1
22 - P1.1
TA0
CCI0A
17 - P3.6
15 - P3.6
TA0
CCI0B
DVSS
GND
18 - P3.7
16 - P3.7
DVCC
VCC
TA1
CCI1A
CAOUT
(internal)
CCI1B
DVSS
GND
DVCC
VCC
OUTPUT PIN NUMBER
PW
RHB, RTV
TA0
17 - P3.6
15 - P3.6
TA1
18 - P3.7
16 - P3.7
Universal Serial Communications Interface (USCI)
The USCI module is used for serial data communication. The USCI module supports synchronous
communication protocols like SPI (3 or 4 pin), I2C and asynchronous communication protocols such as UART,
enhanced UART with automatic baudrate detection (LIN), and IrDA.
USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA.
USCI_B0 provides support for SPI (3 or 4 pin) and I2C.
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Peripheral File Map
Table 16. Peripherals With Word Access
MODULE
ADC10
REGISTER NAME
SHORT NAME
ADDRESS OFFSET
ADC10SA
0x01BC
ADC memory
ADC10MEM
0x01B4
ADC control register 1
ADC10CTL1
0x01B2
ADC control register 0
ADC10CTL0
0x01B0
ADC analog enable 0
ADC10AE0
0x004A
ADC analog enable 1
ADC10AE1
0x004B
ADC data transfer control register 1
ADC10DTC1
0x0049
ADC data transfer control register 0
ADC10DTC0
0x0048
Capture/compare register
TA0CCR2
0x0176
Capture/compare register
TA0CCR1
0x0174
Capture/compare register
TA0CCR0
0x0172
TA0R
0x0170
Capture/compare control
TA0CCTL2
0x0166
Capture/compare control
TA0CCTL1
0x0164
Capture/compare control
TA0CCTL0
0x0162
TA0CTL
0x0160
Timer0_A3 interrupt vector
TA0IV
0x012E
Capture/compare register
TA1CCR1
0x0194
Capture/compare register
TA1CCR0
0x0192
ADC data transfer start address
Timer0_A3
Timer0_A3 register
Timer0_A3 control
Timer1_A2
Timer1_A2 register
TA1R
0x0190
Capture/compare control
TA1CCTL1
0x0184
Capture/compare control
TA1CCTL0
0x0182
Timer1_A2 control
Flash Memory
TA1CTL
0x0180
Timer1_A2 interrupt vector
TA1IV
0x011E
Flash control 3
FCTL3
0x012C
Flash control 2
FCTL2
0x012A
Flash control 1
Watchdog Timer+
Watchdog/timer control
FCTL1
0x0128
WDTCTL
0x0120
SHORT NAME
ADDRESS OFFSET
Table 17. Peripherals With Byte Access
MODULE
USCI_B0
REGISTER NAME
USCI_B0 transmit buffer
UCB0TXBUF
0x06F
USCI_B0 receive buffer
UCB0RXBUF
0x06E
UCB0STAT
0x06D
USCI B0 I2C Interrupt enable
UCB0CIE
0x06C
USCI_B0 bit rate control 1
UCB0BR1
0x06B
USCI_B0 bit rate control 0
UCB0BR0
0x06A
USCI_B0 control 1
UCB0CTL1
0x069
USCI_B0 control 0
USCI_B0 status
16
UCB0CTL0
0x068
USCI_B0 I2C slave address
UCB0SA
0x011A
USCI_B0 I2C own address
UCB0OA
0x0118
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Table 17. Peripherals With Byte Access (continued)
MODULE
USCI_A0
SHORT NAME
ADDRESS OFFSET
USCI_A0 transmit buffer
REGISTER NAME
UCA0TXBUF
0x0067
USCI_A0 receive buffer
UCA0RXBUF
0x0066
USCI_A0 status
UCA0STAT
0x0065
USCI_A0 modulation control
UCA0MCTL
0x0064
USCI_A0 baud rate control 1
UCA0BR1
0x0063
USCI_A0 baud rate control 0
UCA0BR0
0x0062
USCI_A0 control 1
UCA0CTL1
0x0061
USCI_A0 control 0
Comparator_A+
Basic Clock System+
Port P3
UCA0CTL0
0x0060
USCI_A0 IrDA receive control
UCA0IRRCTL
0x005F
USCI_A0 IrDA transmit control
UCA0IRTCTL
0x005E
USCI_A0 auto baud rate control
UCA0ABCTL
0x005D
Comparator_A port disable
CAPD
0x005B
Comparator_A control 2
CACTL2
0x005A
Comparator_A control 1
CACTL1
0x0059
Basic clock system control 3
BCSCTL3
0x0053
Basic clock system control 2
BCSCTL2
0x0058
Basic clock system control 1
BCSCTL1
0x0057
DCO clock frequency control
DCOCTL
0x0056
Port P3 resistor enable
P3REN
0x0010
Port P3 selection
P3SEL
0x001B
Port P3 direction
P3DIR
0x001A
Port P3 output
P3OUT
0x0019
P3IN
0x0018
Port P2 selection 2
P2SEL2
0x0042
Port P2 resistor enable
P2REN
0x002F
Port P2 selection
P2SEL
0x002E
P2IE
0x002D
Port P2 interrupt edge select
P2IES
0x002C
Port P2 interrupt flag
P2IFG
0x002B
Port P2 direction
P2DIR
0x002A
Port P2 output
P2OUT
0x0029
Port P3 input
Port P2
Port P2 interrupt enable
Port P2 input
Port P1
P2IN
0x0028
Port P1 selection 2 register
P1SEL2
0x0041
Port P1 resistor enable
P1REN
0x0027
Port P1 selection
P1SEL
0x0026
P1IE
0x0025
P1IES
0x0024
Port P1 interrupt flag
P1IFG
0x0023
Port P1 direction
P1DIR
0x0022
Port P1 output
P1OUT
0x0021
Port P1 input
P1IN
0x0020
SFR interrupt flag 2
IFG2
0x0003
SFR interrupt flag 1
IFG1
0x0002
SFR interrupt enable 2
IE2
0x0001
SFR interrupt enable 1
IE1
0x0000
Port P1 interrupt enable
Port P1 interrupt edge select
Special Function
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Absolute Maximum Ratings (1)
Voltage applied at VCC to VSS
Voltage applied to any pin
-0.3 V to 4.1 V
(2)
-0.3 V to VCC + 0.3 V
±2 mA
Diode current at any device terminal
Storage temperature, Tstg
(1)
(3)
Unprogrammed device
-55°C to 150°C
Programmed device
-55°C to 150°C
Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditionsis not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TEST pin when blowing the JTAG fuse.
Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak
reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
(2)
(3)
Recommended Operating Conditions (1)
MIN
VCC
Supply voltage, AVCC = DVCC = VCC
VSS
Supply voltage
TA
Operating free-air temperature
fSYSTEM
Processor frequency (maximum MCLK
frequency) (2) (1)
(see Figure 1)
(1)
(2)
NOM
MAX
During program execution
1.8
3.6
During flash memory programming
2.2
3.6
0
0
AVSS = DVSS = VSS
I version
-40
85
T version
-40
105
VCC = 1.8 V, Duty cycle = 50% ±10%
dc
6
VCC = 2.7 V, Duty cycle = 50% ±10%
dc
12
VCC ≥ 3.3 V, Duty cycle = 50% ±10%
dc
16
UNIT
V
V
°C
MHz
Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
Legend :
System Frequency −MHz
16 MHz
Supply voltage range
during flash memory
programming
12 MHz
Supply voltage range
during program execution
6 MHz
1.8 V
2.2 V
2.7 V
3.3 V
3.6 V
Supply Voltage − V
NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC
of 2.2 V.
Figure 1. Operating Area
18
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Active Mode Supply Current (into DVCC + AVCC ) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)
PARAMETER
IAM,1MHz
IAM,1MHz
IAM,4kHz
IAM,100kHz
(1)
(2)
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX
2.2 V
250
340
Active mode (AM)
current (1 MHz)
fDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 32768 Hz,
Program executes in flash,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
3V
350
450
2.2 V
220
Active mode (AM)
current (1 MHz)
fDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 32768 Hz,
Program executes in RAM,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
3V
300
-40°C to 85°C
Active mode (AM)
current (4 kHz)
fMCLK = fSMCLK = fACLK = 32768 Hz / 8
= 4096 Hz,
fDCO = 0 Hz,
Program executes in flash,
SELMx = 11, SELS = 1,
DIVMx = DIVSx = DIVAx = 11,
CPUOFF = 0, SCG0 = 1, SCG1 = 0,
OSCOFF = 0
fMCLK = fSMCLK = fDCO(0, 0) ≈ 100 kHz,
fACLK = 0 Hz,
Program executes in flash,
RSELx = 0, DCOx = 0, CPUOFF = 0,
SCG0 = 0, SCG1 = 0, OSCOFF = 1
-40°C to 85°C
Active mode (AM)
current (100 kHz)
105°C
105°C
5
6
-40°C to 85°C
3
7
3V
105°C
60
85
90
72
3V
105°C
µA
9
2.2 V
-40°C to 85°C
µA
µA
2
2.2 V
UNIT
95
µA
100
All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
Typical Characteristics - Active-Mode Supply Current (Into DVCC + AVCC )
ACTIVE-MODE CURRENT
vs
SUPPLY VOLTAGE
TA = 25°C
ACTIVE-MODE CURRENT
vs
DCO FREQUENCY
5.0
8.0
f DCO = 16 MHz
7.0
TA = 85°C
6.0
Active Mode Current − mA
Active Mode Current − mA
4.0
f DCO = 12 MHz
5.0
4.0
f DCO = 8 MHz
3.0
2.0
TA = 25°C
3.0
VCC = 3 V
TA = 85°C
2.0
TA = 25°C
1.0
1.0
0.0
1.5
VCC = 2.2 V
f DCO = 1 MHz
2.0
2.5
3.0
VCC − Supply Voltage − V
Figure 2.
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3.5
4.0
0.0
0.0
4.0
8.0
12.0
16.0
f DCO − DCO Frequency − MHz
Figure 3.
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Low-Power-Mode Supply Currents (Into VCC ) Excluding External Current
(1) (2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ILPM0, 1MHz
ILPM0,
Low-power mode 0
(LPM0) current (3)
Low-power mode 0
(LPM0) current (3)
100kHz
Low-power mode 2
(LPM2) current (4)
ILPM2
TEST CONDITIONS
TA
VCC
fMCLK = 0 MHz,
fSMCLK = fDCO = 1 MHz,
fACLK = 32768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
-40°C to 85°C
fMCLK = 0 MHz,
fSMCLK = fDCO(0, 0) ≈ 100 kHz,
fACLK = 0 Hz,
RSELx = 0, DCOx = 0,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 1
-40°C to 85°C
fMCLK = fSMCLK = 0 MHz,
fDCO = 1 MHz,
fACLK = 32768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 1,
OSCOFF = 0
-40°C to 85°C
105°C
2.2 V
-40°C to 85°C
ILPM3,
Low-power mode 3
(LPM3) current (4)
LFXT1
105°C
2.2 V
-40°C to 85°C
ILPM4
(1)
(2)
(3)
(4)
(5)
20
Low-power mode 3
current, (LPM3) (4)
Low-power mode 4
(LPM4) current (5)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
66
105°C
2.2 V
-40°C to 85°C
85°C
33
105°C
-40°C to 25°C
85°C
3V
85°C
2.2 V
105°C
-40°C to 25°C
3V
42
46
20
25
27
27
0.7
1.2
1.6
2.3
3
6
0.9
1.9
1.6
2.8
3
7
0.3
0.7
1.2
1.9
2
5
0.7
0.8
1.4
2.1
6
-40°C
0.1
0.5
0.1
0.5
0.8
1.5
2
4
105°C
2.2 V/ 3 V
µA
31
2.5
85°C
µA
48
105°C
25°C
µA
44
22
2.2 V
83
90
3V
105°C
UNIT
68
3V
105°C
85°C
55
37
-40°C to 25°C
ILPM3, VLO
MAX
3V
105°C
105°C
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK from internal LF oscillator
(VLO),
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
TYP
70
-40°C to 25°C
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 32768 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
MIN
µA
µA
µA
All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
Current for brownout and WDT clocked by SMCLK included.
Current for brownout and WDT clocked by ACLK included.
Current for brownout included.
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Typical Characteristics - LPM4 Current
LPM4 CURRENT
vs
TEMPERATURE
ILPM4 − Low-Power Mode Current − µA
2.4
VCC = 3.6 V
2.2
VCC = 3 V
2.0
VCC = 2.2 V
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
−40.0 −20.0
VCC = 1.8 V
0.0
20.0
40.0
60.0
80.0 100.0
TA − Temperature − °C
Figure 4.
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Schmitt-Trigger Inputs (Ports P1, P2, P3, JTAG, RST/NMI, XIN (1))
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VIT+
TEST CONDITIONS
Positive-going input threshold voltage
VCC
MIN
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ - VIT- )
RPull
Pullup/pulldown resistor
For pullup: VIN = VSS,
For pulldown: VIN = VCC
CI
Input capacitance
VIN = VSS or VCC
(1)
XIN only in bypass mode
MAX
0.45 VCC
0.75 VCC
1
1.65
1.35
2.25
0.25 VCC
0.55 VCC
2.2 V
0.55
1.20
3V
0.75
1.65
2.2 V
0.2
1
3V
0.3
1
2.2 V
3V
VIT-
TYP
20
35
UNIT
V
V
V
50
kΩ
5
pF
Inputs (Ports P1, P2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
t(int)
(1)
External interrupt timing
TEST CONDITIONS
Port P1, P2: P1.x to P2.x, External trigger
pulse width to set interrupt flag (1)
VCC
2.2 V/3 V
MIN
TYP
MAX
UNIT
20
ns
An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set with trigger signals
shorter than t(int).
Leakage Current (Ports P1, P2, P3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Px.y)
(1)
(2)
22
High-impedance leakage current
TEST CONDITIONS
(1) (2)
VCC
2.2 V/3 V
MIN
TYP
MAX
UNIT
±50
nA
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
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Outputs (Ports P1, P2, P3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH(max) = -1.5 mA
VOH
High-level output voltage
IOH(max) = -6 mA
(2)
IOH(max) = -1.5 mA (1)
IOH(max) = -6 mA (2)
IOL(max) = 1.5 mA
VOL
Low-level output voltage
(2)
2.2 V
3V
(1)
2.2 V
IOL(max) = 6 mA (2)
IOL(max) = 1.5 mA (1)
IOL(max) = 6 mA (2)
(1)
VCC
(1)
3V
MIN
MAX
VCC - 0.25
VCC
VCC - 0.6
VCC
VCC - 0.25
VCC
VCC - 0.6
VCC
VSS
VSS + 0.25
VSS
VSS + 0.6
VSS
VSS + 0.25
VSS
VSS + 0.6
UNIT
V
V
The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to hold the maximum voltage drop
specified.
The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
Output Frequency (Ports P1, P2, P3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fPx.y
Port output frequency (with load)
P1.4/SMCLK, CL = 20 pF, RL = 1 kΩ (1) (2)
fPort°CLK
Clock output frequency
P2.0/ACLK, P1.4/SMCLK, CL = 20 pF (2)
(1)
(2)
VCC
MIN
TYP
MAX
2.2 V
7.5
3V
12
2.2 V
7.5
3V
16
UNIT
MHz
MHz
Alternatively, a resistive divider with two 0.5-kΩ resistors between VCC and VSS is used as load. The output is connected to the center
tap of the divider.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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Typical Characteristics - Outputs
One output loaded at a time.
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
50.0
VCC = 2.2 V
P2.4
TA = 25°C
20.0
I OL − Typical Low-Level Output Current − mA
I OL − Typical Low-Level Output Current − mA
25.0
TA = 85°C
15.0
10.0
5.0
0.0
0.0
0.5
1.0
1.5
2.0
VCC = 3 V
P2.4
40.0
TA = 85°C
30.0
20.0
10.0
0.0
0.0
2.5
VOL − Low-Level Output Voltage − V
1.0
1.5
2.0
2.5
3.0
Figure 5.
Figure 6.
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
−5.0
−10.0
−15.0
−20.0
−25.0
0.0
3.5
0.0
VCC = 2.2 V
P2.4
I OH − Typical High-Level Output Current − mA
I OH − Typical High-Level Output Current − mA
0.5
VOL − Low-Level Output Voltage − V
0.0
TA = 85°C
TA = 25°C
0.5
1.0
1.5
2.0
VOH − High-Level Output Voltage − V
Figure 7.
24
TA = 25°C
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2.5
VCC = 3 V
P2.4
−10.0
−20.0
−30.0
−40.0
−50.0
0.0
TA = 85°C
TA = 25°C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOH − High-Level Output Voltage − V
Figure 8.
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MSP430F21x2
SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012
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POR/Brownout Reset (BOR) (1) (2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC(start)
See Figure 9
dVCC /dt ≤ 3 V/s
V(B_IT-)
See Figure 9 through Figure 11
dVCC /dt ≤ 3 V/s
Vhys(B_IT-)
See Figure 9
dVCC /dt ≤ 3 V/s
td(BOR)
See Figure 9
t(reset)
Pulse length needed at RST/NMI pin
to accepted reset internally
(1)
(2)
VCC
MIN
TYP
MAX
0.7 ×
V(B_IT-)
70
2.2 V/3 V
130
UNIT
V
1.71
V
210
mV
2000
µs
2
µs
The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level
V(B_IT-) + Vhys(B_IT-) is ≤ 1.8 V.
During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT-) + Vhys(B_IT-). The default DCO settings
must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency.
VCC
Vhys(B_IT−)
V(B_IT−)
VCC(start)
1
0
t d(BOR)
Figure 9. POR/Brownout Reset (BOR) vs Supply Voltage
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Typical Characteristics - POR/Brownout Reset (BOR)
VCC
3V
2
VCC(drop) − V
VCC = 3 V
Typical Conditions
t pw
1.5
1
VCC(drop)
0.5
0
0.001
1
1000
1 ns
t pw − Pulse Width − µs
1 ns
t pw − Pulse Width − µs
Figure 10. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC
2
t pw
3V
VCC(drop) − V
VCC = 3 V
1.5
Typical Conditions
1
VCC(drop)
0.5
0
0.001
tf = tr
1
t pw − Pulse Width − µs
1000
tf
tr
t pw − Pulse Width − µs
Figure 11. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
26
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Main DCO Characteristics
•
•
•
All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
DCO control bits DCOx have a step size as defined by parameter SDCO.
Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to:
faverage =
32 × fDCO(RSEL,DCO) × fDCO(RSEL,DCO+1)
MOD × fDCO(RSEL,DCO) + (32 – MOD) × fDCO(RSEL,DCO+1)
DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
RSELx < 14
1.8
3.6
RSELx = 14
2.2
3.6
UNIT
VCC
Supply voltage range
3.0
3.6
fDCO(0,0)
DCO frequency (0, 0)
RSELx = 0, DCOx = 0, MODx = 0
2.2 V/3 V
0.06
0.14
MHz
fDCO(0,3)
DCO frequency (0, 3)
RSELx = 0, DCOx = 3, MODx = 0
2.2 V/3 V
0.07
0.17
MHz
fDCO(1,3)
DCO frequency (1, 3)
RSELx = 1, DCOx = 3, MODx = 0
2.2 V/3 V
0.10
0.20
MHz
fDCO(2,3)
DCO frequency (2, 3)
RSELx = 2, DCOx = 3, MODx = 0
2.2 V/3 V
0.14
0.28
MHz
fDCO(3,3)
DCO frequency (3, 3)
RSELx = 3, DCOx = 3, MODx = 0
2.2 V/3 V
0.20
0.40
MHz
fDCO(4,3)
DCO frequency (4, 3)
RSELx = 4, DCOx = 3, MODx = 0
2.2 V/3 V
0.28
0.54
MHz
fDCO(5,3)
DCO frequency (5, 3)
RSELx = 5, DCOx = 3, MODx = 0
2.2 V/3 V
0.39
0.77
MHz
fDCO(6,3)
DCO frequency (6, 3)
RSELx = 6, DCOx = 3, MODx = 0
2.2 V/3 V
0.54
1.06
MHz
fDCO(7,3)
DCO frequency (7, 3)
RSELx = 7, DCOx = 3, MODx = 0
2.2 V/3 V
0.80
1.50
MHz
fDCO(8,3)
DCO frequency (8, 3)
RSELx = 8, DCOx = 3, MODx = 0
2.2 V/3 V
1.10
2.10
MHz
fDCO(9,3)
DCO frequency (9, 3)
RSELx = 9, DCOx = 3, MODx = 0
2.2 V/3 V
1.60
3.00
MHz
fDCO(10,3)
DCO frequency (10, 3)
RSELx = 10, DCOx = 3, MODx = 0
2.2 V/3 V
2.50
4.30
MHz
fDCO(11,3)
DCO frequency (11, 3)
RSELx = 11, DCOx = 3, MODx = 0
2.2 V/3 V
3.00
5.50
MHz
fDCO(12,3)
DCO frequency (12, 3)
RSELx = 12, DCOx = 3, MODx = 0
2.2 V/3 V
4.30
7.30
MHz
fDCO(13,3)
DCO frequency (13, 3)
RSELx = 13, DCOx = 3, MODx = 0
2.2 V/3 V
6.00
9.60
MHz
fDCO(14,3)
DCO frequency (14, 3)
RSELx = 14, DCOx = 3, MODx = 0
2.2 V/3 V
8.60
13.9
MHz
fDCO(15,3)
DCO frequency (15, 3)
RSELx = 15, DCOx = 3, MODx = 0
3V
12.0
18.5
MHz
fDCO(15,7)
DCO frequency (15, 7)
RSELx = 15, DCOx = 7, MODx = 0
3V
16.0
26.0
MHz
SRSEL
Frequency step between
range RSEL and RSEL+1
SRSEL = fDCO(RSEL+1,DCO) /fDCO(RSEL,DCO)
2.2 V/3 V
1.55
ratio
SDCO
Frequency step between tap
DCO and DCO+1
SDCO = fDCO(RSEL,DCO+1) /fDCO(RSEL,DCO)
2.2 V/3 V
1.05
1.08
1.12
ratio
Duty cycle
Measured at P1.4/SMCLK
2.2 V/3 V
40
50
60
RSELx = 15
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%
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Calibrated DCO Frequencies - Tolerance at Calibration
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Frequency tolerance at calibration
TA
VCC
MIN
TYP
MAX
UNIT
25°C
3V
-1
±0.2
+1
25°C
3V
0.990
1
1.010
MHz
%
fCAL(1MHz)
1-MHz calibration value
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
fCAL(8MHz)
8-MHz calibration value
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
25°C
3V
7.920
8
8.080
MHz
fCAL(12MHz)
12-MHz calibration value
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
25°C
3V
11.88
12
12.12
MHz
fCAL(16MHz)
16-MHz calibration value
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms
25°C
3V
15.84
16
16.16
MHz
MAX
UNIT
Calibrated DCO Frequencies - Tolerance Over Temperature 0°C to 85°C
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fCAL(1MHz)
fCAL(8MHz)
fCAL(12MHz)
fCAL(16MHz)
28
TA
VCC
1-MHz tolerance over
temperature
0°C to 85°C
3V
-2.5
±0.5
+2.5
%
8-MHz tolerance over
temperature
0°C to 85°C
3V
-2.5
±1
+2.5
%
12-MHz tolerance over
temperature
0°C to 85°C
3V
-2.5
±1
+2.5
%
16-MHz tolerance over
temperature
0°C to 85°C
3V
-3
±2
+3
%
2.2 V
0.97
1
1.03
3V
0.975
1
1.025
3.6 V
0.97
1
1.03
2.2 V
7.76
8
8.4
3V
7.8
8
8.2
3.6 V
7.6
8
8.24
2.2 V
11.64
12
12.36
3V
11.64
12
12.36
3.6 V
11.64
12
12.36
3V
15.52
16
16.48
15
16
16.48
1-MHz calibration value
8-MHz calibration value
12-MHz calibration value
16-MHz calibration value
TEST CONDITIONS
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
0°C to 85°C
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
0°C to 85°C
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
0°C to 85°C
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms
0°C to 85°C
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MIN
TYP
MHz
MHz
MHz
MHz
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Calibrated DCO Frequencies - Tolerance Over Supply Voltage VCC
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX
1-MHz tolerance over VCC
25°C
8-MHz tolerance over VCC
25°C
12-MHz tolerance over VCC
16-MHz tolerance over VCC
UNIT
1.8 V to 3.6 V
-3
±2
+3
%
1.8 V to 3.6 V
-3
±2
+3
%
25°C
2.2 V to 3.6 V
-3
±2
+3
%
25°C
3 V to 3.6 V
-6
±2
+3
%
fCAL(1MHz)
1-MHz calibration value
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
25°C
1.8 V to 3.6 V
0.97
1
1.03
MHz
fCAL(8MHz)
8-MHz calibration value
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
25°C
1.8 V to 3.6 V
7.76
8
8.24
MHz
fCAL(12MHz)
12-MHz calibration value
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
25°C
2.2 V to 3.6 V
11.64
12
12.36
MHz
fCAL(16MHz)
16-MHz calibration value
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms
25°C
3 V to 3.6 V
15
16
16.48
MHz
MIN
TYP
MAX
UNIT
Calibrated DCO Frequencies - Overall Tolerance
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
VCC
1-MHz tolerance
overall
-40°C to 105°C
1.8 V to 3.6 V
-5
±2
+5
%
8-MHz tolerance
overall
-40°C to 105°C
1.8 V to 3.6 V
-5
±2
+5
%
12-MHz tolerance
overall
-40°C to 105°C
2.2 V to 3.6 V
-5
±2
+5
%
16-MHz tolerance
overall
-40°C to 105°C
3 V to 3.6 V
-6
±3
+6
%
fCAL(1MHz)
1-MHz calibration
value
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
-40°C to 105°C
1.8 V to 3.6 V
0.95
1
1.05
MHz
fCAL(8MHz)
8-MHz calibration
value
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
-40°C to 105°C
1.8 V to 3.6 V
7.6
8
8.4
MHz
fCAL(12MHz)
12-MHz calibration
value
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
-40°C to 105°C
2.2 V to 3.6 V
11.4
12
12.6
MHz
fCAL(16MHz)
16-MHz calibration
value
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms
-40°C to 105°C
3 V to 3.6 V
15
16
17
MHz
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Typical Characteristics - Calibrated 1-MHz DCO Frequency
CALIBRATED 1-MHz FREQUENCY
vs
SUPPLY VOLTAGE
1.03
TA = 85 °C
1.02
Frequency − MHz
TA = 25 °C
1.01
TA = 105 °C
1.00
TA = −40 °C
0.99
0.98
0.97
1.5
2.0
2.5
3.0
3.5
4.0
VCC − Supply Voltage − V
Figure 12.
30
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Wake-Up From Lower-Power Modes (LPM3/4)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ
tDCO,LPM3/4
(1)
(2)
UNIT
2
BCSCTL1 = CALBC1_8MHZ,
DCO clock wake-up time DCOCTL = CALDCO_8MHZ
from LPM3/4 (1)
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ
2.2 V/3 V
1.5
µs
1
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ
tCPU,LPM3/4
MAX
3V
1
CPU wake-up time from
LPM3/4 (2)
1 / fMCLK +
tClock,LPM3/4
The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, a port interrupt) to the first clock
edge observable externally on a clock pin (MCLK or SMCLK).
Parameter applicable only if DCOCLK is used for MCLK.
Typical Characteristics - DCO Clock Wake-Up Time From LPM3/4
CLOCK WAKE-UP TIME FROM LPM3
vs
DCO FREQUENCY
DCO Wake Time − µs
10.00
RSELx = 0 to 11
RSELx = 12 to 15
1.00
0.10
0.10
1.00
10.00
DCO Frequency − MHz
Figure 13.
DCO With External Resistor ROSC (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
1.8
3V
1.95
UNIT
fDCO,ROSC
DCO output frequency with ROSC
DT
Temperature drift
DCOR = 1,
RSELx = 4, DCOx = 3, MODx = 0
2.2 V/3 V
±0.1
%/°C
DV
Drift with VCC
DCOR = 1,
RSELx = 4, DCOx = 3, MODx = 0
2.2 V/3 V
10
%/V
(1)
2.2 V
MAX
DCOR = 1,
RSELx = 4, DCOx = 3, MODx = 0,
TA = 25°C
MHz
ROSC = 100 kΩ. Metal film resistor, type 0257, 0.6 W with 1% tolerance and TK = ±50 ppm/°C.
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Typical Characteristics - DCO With External Resistor ROSC
DCO FREQUENCY
vs
ROSC
VCC = 2.2 V, TA = 25°C
DCO FREQUENCY
vs
ROSC
VCC = 3 V, TA = 25°C
10.00
DCO Frequency − MHz
DCO Frequency − MHz
10.00
1.00
0.10
RSELx = 4
0.01
10.00
100.00
1000.00
1.00
0.10
RSELx = 4
0.01
10.00
10000.00
ROSC − External Resistor − kW
Figure 15.
DCO FREQUENCY
vs
TEMPERATURE
VCC = 3 V
DCO FREQUENCY
vs
SUPPLY VOLTAGE
TA = 25°C
2.25
DCO Frequency − MHz
ROSC = 100k
2.00
DCO Frequency − MHz
10000.00
2.50
2.25
1.75
1.50
1.25
1.00
ROSC = 270k
0.75
ROSC = 100k
2.00
1.75
1.50
1.25
1.00
ROSC = 270k
0.75
0.50
0.50
ROSC = 1M
0.25
−25
0
25
50
TA − Temperature − °C
Figure 16.
32
1000.00
Figure 14.
2.50
0.00
−50
100.00
ROSC − External Resistor − kW
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ROSC = 1M
0.25
100
0.00
2.0
2.5
3.0
3.5
4.0
VCC − Supply Voltage − V
Figure 17.
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MSP430F21x2
SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012
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Crystal Oscillator LFXT1, Low-Frequency Mode (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fLFXT1,LF
LFXT1 oscillator crystal
frequency, LF mode 0, 1
fLFXT1,LF,logic
LFXT1 oscillator logic level
square wave input frequency, XTS = 0, XCAPx = 0, LFXT1Sx = 3
LF mode
OALF
Oscillation allowance for
LF crystals
CL,eff
fFault,LF
(1)
(2)
(3)
(4)
Integrated effective load
capacitance, LF mode (2)
XTS = 0, LFXT1Sx = 0 or 1
VCC
MIN
TYP
1.8 V to 3.6 V
1.8 V to 3.6 V
MAX
32768
10000
32768
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 6 pF
500
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 12 pF
200
UNIT
Hz
50000
Hz
kΩ
XTS = 0, XCAPx = 0
1
XTS = 0, XCAPx = 1
5.5
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
11
Duty cycle, LF mode
XTS = 0, Measured at P2.0/ACLK,
fLFXT1,LF = 32768 Hz
2.2 V/3 V
30
Oscillator fault frequency,
LF mode (3)
XTS = 0, XCAPx = 0,
LFXT1Sx = 3 (4)
2.2 V/3 V
10
50
pF
70
%
10000
Hz
To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the crystal that is used.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fVLO
VLO frequency
dfVLO/dT
VLO frequency temperature drift (1)
dfVLO/dVCC
VLO frequency supply voltage drift (2)
(1)
(2)
TA
-40°C to 85°C
105°C
VCC
2.2 V/3 V
2.2 V/3 V
1.8 V to 3.6 V
MIN
TYP
MAX
4
12
20
22
UNIT
kHz
0.5
%/°C
4
%/V
Calculated using the box method:
I version: [MAX(-40...85°C) - MIN(-40...85°C)]/MIN(-40...85°C)/[85°C - (-40°C)]
T version: [MAX(-40...105°C) - MIN(-40...105°C)]/MIN(-40...105°C)/[105°C - (-40°C)]
Calculated using the box method: [MAX(1.8...3.6 V) - MIN(1.8...3.6 V)]/MIN(1.8...3.6 V)/(3.6 V - 1.8 V)
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Crystal Oscillator LFXT1, High-Frequency Mode (1)
PARAMETER
VCC
MIN
XTS = 1, XCAPx = 0, LFXT1Sx = 0
1.8 V to 3.6 V
LFXT1 oscillator crystal
frequency, HF mode 1
XTS = 1, XCAPx = 0, LFXT1Sx = 1
LFXT1 oscillator crystal
frequency, HF mode 2
XTS = 1, XCAPx = 0, LFXT1Sx = 2
fLFXT1,HF0
LFXT1 oscillator crystal
frequency, HF mode 0
fLFXT1,HF1
fLFXT1,HF2
TEST CONDITIONS
MAX
UNIT
0.4
1
MHz
1.8 V to 3.6 V
1
4
MHz
1.8 V to 3.6 V
2
10
2.2 V to 3.6 V
2
12
3 V to 3.6 V
fLFXT1,HF,logic
OAHF
CL,eff
LFXT1 oscillator logic-level
square-wave input
frequency, HF mode
Oscillation allowance for HF
crystals (see Figure 18 and
Figure 19)
Integrated effective load
capacitance, HF mode (2)
(1)
(2)
(3)
(4)
(5)
34
Oscillator fault frequency
2
16
1.8 V to 3.6 V
0.4
10
2.2 V to 3.6 V
0.4
12
3 V to 3.6 V
0.4
16
XTS = 1, XCAPx = 0, LFXT1Sx = 0,
fLFXT1,HF = 1 MHz, CL,eff = 15 pF
2700
XTS = 1, XCAPx = 0, LFXT1Sx = 1,
fLFXT1,HF = 4 MHz, CL,eff = 15 pF
800
XTS = 1, XCAPx = 0, LFXT1Sx = 2,
fLFXT1,HF = 16 MHz, CL,eff = 15 pF
300
XTS = 1, XCAPx = 0 (3)
XTS = 1, XCAPx = 0,
Measured at P2.0/ACLK,
fLFXT1,HF = 10 MHz
Duty cycle, HF mode
fFault,HF
XTS = 1, XCAPx = 0, LFXT1Sx = 3
XTS = 1, XCAPx = 0,
Measured at P2.0/ACLK,
fLFXT1,HF = 16 MHz
(4)
TYP
XTS = 1, XCAPx = 0, LFXT1Sx = 3 (5)
50
pF
60
2.2 V/3 V
%
40
2.2 V/3 V
MHz
Ω
1
40
MHz
30
50
60
300
kHz
To improve EMI on the XT2 oscillator the following guidelines should be observed:
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it is
recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should
always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and
frequencies in between might set the flag.
Measured with logic-level input frequency, but also applies to operation with crystals.
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Typical Characteristics - LFXT1 Oscillator in HF Mode (XTS = 1)
OSCILLATION ALLOWANCE
vs
CRYSTAL FREQUENCY
CL,eff = 15 pF, TA = 25°C
OSCILLATOR SUPPLY CURRENT
vs
CRYSTAL FREQUENCY
CL,eff = 15 pF, TA = 25°C
100000.00
1800.0
LFXT1Sx = 2
10000.00
1000.00
LFXT1Sx = 2
100.00
XT Oscillator Supply Current − uA
Oscillation Allowance − Ohms
1600.0
1400.0
1200.0
1000.0
800.0
600.0
400.0
LFXT1Sx = 1
LFXT1Sx = 1
200.0
LFXT1Sx = 0
10.00
0.10
1.00
10.00
100.00
0.0
0.0
Crystal Frequency − MHz
LFXT1Sx = 0
4.0
8.0
12.0
16.0
20.0
Crystal Frequency − MHz
Figure 18.
Figure 19.
Timer0_A3
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTA
Timer0_A3 clock frequency
Internal: SMCLK, ACLK
External: TACLK, INCLK
Duty cycle = 50% ± 10%
tTA,cap
Timer0_A3 capture timing
TA0.0, TA0.1, TA0.2
VCC
MIN
TYP
MAX
2.2 V
10
3V
16
2.2 V/3 V
20
UNIT
MHz
ns
Timer1_A2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTB
Timer1_A2 clock frequency
Internal: SMCLK, ACLK
External: TACLK, INCLK
Duty cycle = 50% ± 10%
tTB,cap
Timer1_A2 capture timing
TA1.0, TA1.1
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VCC
MIN
TYP
MAX
2.2 V
10
3V
16
2.2 V/3 V
20
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UNIT
MHz
ns
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USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fUSCI
USCI input clock frequency
fmax,BITCLK
Maximum BITCLK clock frequency
(equals baud rate in MBaud) (1)
tτ
UART receive deglitch time (2)
(1)
(2)
CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
2.2 V/3 V
2
2.2 V
50
150
3V
50
100
MAX
UNIT
fSYSTEM
MHz
MHz
ns
The DCO wake-up time must be considered in LPM3/4 for baudrates above 1 MHz.
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
USCI (SPI Master Mode) (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Figure 20 and Figure 21)
PARAMETER
fUSCI
USCI input clock frequency
tSU,MI
SOMI input data setup time
tHD,MI
SOMI input data hold time
tVALID,MO
SIMO output data valid time
(1)
TEST CONDITIONS
VCC
MIN
TYP
SMCLK, ACLK
Duty cycle = 50% ± 10%
UCLK edge to SIMO valid,
CL = 20 pF
2.2 V
110
3V
75
2.2 V
0
3V
0
MAX
UNIT
fSYSTEM
MHz
ns
ns
2.2 V
30
3V
20
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).
For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
USCI (SPI Slave Mode) (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Figure 22 and Figure 23)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
tSTE,LEAD
STE lead time, STE low to clock
2.2 V/3 V
tSTE,LAG
STE lag time, Last clock to STE high
2.2 V/3 V
tSTE,ACC
STE access time, STE low to SOMI data out
2.2 V/3 V
50
ns
tSTE,DIS
STE disable time, STE high to SOMI high
impedance
2.2 V/3 V
50
ns
tSU,SI
SIMO input data setup time
tHD,SI
SIMO input data hold time
tVALID,SO
SOMI output data valid time
(1)
36
UCLK edge to SOMI valid,
CL = 20 pF
50
UNIT
ns
10
2.2 V
20
3V
15
2.2 V
10
3V
10
ns
ns
ns
2.2 V
75
110
3V
50
75
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)).
For the master's parameters tSU,MI(Master) and tVALID,MO(Master) refer to the SPI parameters of the attached slave.
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1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
Figure 20. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
Figure 21. SPI Master Mode, CKPH = 1
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tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,SI
tHD,SI
SIMO
tSTE,ACC
tVALID,SO
tSTE,DIS
SOMI
Figure 22. SPI Slave Mode, CKPH = 0
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tHD,SI
tSU,SI
SIMO
tSTE,ACC
tVALID,SO
tSTE,DIS
SOMI
Figure 23. SPI Slave Mode, CKPH = 1
38
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USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 24)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
MAX
UNIT
fSYSTEM
MHz
400
kHz
fUSCI
USCI input clock frequency
fSCL
SCL clock frequency
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
2.2 V/3 V
0
tSU,DAT
Data setup time
2.2 V/3 V
250
ns
tSU,STO
Setup time for STOP
2.2 V/3 V
4
µs
tSP
Pulse width of spikes suppressed by input filter
2.2 V
50
150
600
3V
50
100
600
2.2 V/3 V
fSCL ≤ 100 kHz
fSCL > 100 kHz
fSCL ≤ 100 kHz
fSCL > 100 kHz
tHD,STA
2.2 V/3 V
2.2 V/3 V
0
4
µs
0.6
4.7
µs
0.6
ns
ns
tSU,STA tHD,STA
SDA
1/fSCL
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 24. I2C Mode Timing
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Comparator_A+ (1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(DD)
CAON = 1, CARSEL = 0, CAREF = 0
I(Refladder/RefDiode)
CAON = 1, CARSEL = 0, CAREF = 1/2/3,
No load at P1.0/CA0 and P1.1/CA1
VCC
MIN
TYP
MAX
2.2 V
25
40
3V
45
60
2.2 V
30
50
3V
45
71
UNIT
µA
µA
VIC
Common-mode input voltage
range
CAON = 1
2.2 V/3 V
0
V(Ref025)
Voltage at 0.25 VCC node /
VCC
PCA0 = 1, CARSEL = 1, CAREF = 1,
No load at P1.0/CA0 and P1.1/CA1
2.2 V/3 V
0.23
0.24
0.25
V(Ref050)
Voltage at 0.5 VCC node /
VCC
PCA0 = 1, CARSEL = 1, CAREF = 2,
No load at P1.0/CA0 and P1.1/CA1
2.2 V/3 V
0.47
0.48
0.5
390
480
540
See Figure 28 and Figure 29
PCA0 = 1, CARSEL = 1, CAREF = 3,
No load at P1.0/CA0 and P1.1/CA1;
TA = 85°C
2.2 V
V(RefVT)
3V
400
490
550
V(offset)
Offset voltage (2)
2.2 V/3 V
-30
30
mV
Vhys
Input hysteresis
2.2 V/3 V
0
0.7
1.4
mV
TA = 25°C, Overdrive 10 mV,
Without filter: CAF = 0 (3)
(see Figure 25 and Figure 26)
2.2 V
80
165
300
3V
70
120
240
TA = 25°C, Overdrive 10 mV,
With filter: CAF = 1 (3)
(see Figure 25 and Figure 26)
2.2 V
1.4
1.9
2.8
3V
0.9
1.5
2.2
t(response)
(1)
(2)
(3)
40
Response time
(low-high and high-low)
CAON = 1
VCC - 1
V
mV
ns
µs
The leakage current for the Comparator_A+ terminals is identical to Ilkg(Px.y) specification.
The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements. The
two successive measurements are then summed together.
Response time measured at P2.2/TA0.0/A2/CA4/CAOUT. If the Comparator_A+ is enabled a settling time of 60 ns (typical) is added to
the response time.
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0V
VCC
0
1
CAF
CAON
To Internal
Modules
Low-Pass Filter
+
_
V+
V−
0
0
1
1
CAOUT
Set CAIFG
Flag
τ ≈ 2.0 µs
Figure 25. Comparator_A+ Module Block Diagram
VCAOUT
Overdrive
V−
400 mV
t (response)
V+
Figure 26. Overdrive Definition
CASHORT
CA0
CA1
1
VIN
+
−
Comparator_A+
CASHORT = 1
IOUT = 10µA
Figure 27. Comparator_A+ Short Resistance Test Condition
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Typical Characteristics - Comparator_A+
V(RefVT)
vs
TEMPERATURE
VCC = 2.2 V
V(RefVT)
vs
TEMPERATURE
VCC = 2.2 V
650
650.0
VCC = 2.2 V
V(REFVT) − Reference Volts − mV
V(REFVT) − Reference Volts − mV
VCC = 3 V
600.0
Typical
550.0
500.0
450.0
400.0
−45.0 −25.0 −5.0 15.0 35.0 55.0
600
Typical
550
500
450
400
−45
75.0 95.0 115.0
−25
TA − Free-Air Temperature − °C
−5
15
35
55
75
95
115
TA − Free-Air Temperature − °C
Figure 28.
Figure 29.
SHORT RESISTANCE
vs
VIN/VCC
Short Resistance − kW
100.00
VCC = 1.8V
VCC = 2.2V
10.00
VCC = 3.0V
VCC = 3.6V
1.00
0.0
0.2
0.4
0.6
0.8
1.0
VIN/VCC − Normalized Input Voltage − V/V
Figure 30.
42
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10-Bit ADC, Power Supply and Input Range Conditions (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
VCC
VAx
IADC10
IREF+
TEST CONDITIONS
Analog supply voltage
VSS = 0 V
Analog input voltage
range (2)
All Ax terminals,
Analog inputs selected in
ADC10AE register
ADC10 supply current
(3)
Reference supply
current, reference buffer
disabled (4)
fADC10CLK = 5 MHz,
ADC10ON = 1, REFON = 0,
ADC10SHT0 = 1,
ADC10SHT1 = 0,
ADC10DIV = 0
fADC10CLK = 5 MHz,
ADC10ON = 0, REF2_5V = 0,
REFON = 1, REFOUT = 0
fADC10CLK = 5 MHz,
ADC10ON = 0, REF2_5V = 1,
REFON = 1, REFOUT = 0
TA
I: -40°C to 85°C
T: -40°C to 105°C
MIN
TYP
MAX
UNIT
2.2
3.6
V
0
VCC
V
2.2 V
0.52
1.05
3V
0.6
1.2
2.2 V/3 V
0.25
0.4
I: -40°C to 85°C
T: -40°C to 105°C
fADC10CLK = 5 MHz
ADC10ON = 0, REFON = 1,
REF2_5V = 0, REFOUT = 1,
ADC10SR = 0
-40°C to 85°C
Reference buffer supply
IREFB,1 current with
ADC10SR = 1 (4)
fADC10CLK = 5 MHz,
ADC10ON = 0, REFON = 1,
REF2_5V = 0, REFOUT = 1,
ADC10SR = 1
-40°C to 85°C
CI
Input capacitance
Only one terminal Ax selected at
a time
I: -40°C to 85°C
T: -40°C to 105°C
RI
Input MUX ON
resistance
0 V ≤ VAx ≤ VCC
I: -40°C to 85°C
T: -40°C to 105°C
105°C
105°C
mA
mA
3V
Reference buffer supply
IREFB,0 current with
ADC10SR = 0 (4)
(1)
(2)
(3)
(4)
VCC
0.25
0.4
1.1
1.4
2.2 V/3 V
1.8
0.5
2.2 V/3 V
2.2 V/3 V
mA
0.7
0.8
mA
27
pF
2000
Ω
The leakage current is defined in the leakage current table with Px.x/Ax parameter.
The analog input voltage range must be within the selected reference voltage range VR+ to VR- for valid conversion results.
The internal reference supply current is not included in current consumption parameter IADC10.
The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables the built-in reference. The reference voltage must be allowed to settle before an A/D
conversion is started.
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10-Bit ADC, Built-In Voltage Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC,REF+
TEST CONDITIONS
IVREF+ ≤ 1 mA, REF2_5V = 0
Positive built-in
reference analog
IVREF+ ≤ 0.5 mA, REF2_5V = 1
supply voltage range
IVREF+ ≤ 1 mA, REF2_5V = 1
VREF+
Positive built-in
reference voltage
ILD,VREF+
Maximum VREF+
load current
VREF+ load
regulation
2.2 V/3 V
1.41
1.5
1.59
IVREF+ ≤ IVREF+max, REF2_5V = 1
3V
2.35
2.5
2.65
2.2 V
±0.5
3V
±1
IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≈ 0.75 V,
REF2_5V = 0
2.2 V/3 V
±2
IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≈ 1.25 V,
REF2_5V = 1
3V
IVREF+ ≤ ±1 mA, REFON = 1, REFOUT = 1
TCREF+
Temperature
coefficient
IVREF+ = constant with
0 mA ≤ IVREF+ ≤ 1 mA (2)
tREFON
Settling time of
internal reference
voltage (3)
IVREF+ = 0.5 mA, REF2_5V = 0,
REFON = 0 to 1
44
UNIT
V
IVREF+ ≤ IVREF+max, REF2_5V = 0
Maximum
capacitance at pin
VREF+ (1)
(2)
(3)
MAX
2.9
CVREF+
(1)
TYP
2.8
IVREF+ = 100 µA to 900 µA,
VAx ≈ 0.5 x VREF+,
Error of conversion result
≤1 LSB
Settling time of
reference buffer (3)
MIN
2.2
VREF+ load
regulation response
time
tREFBURST
VCC
-40°C to 85°C
-40°C to 105°C
IVREF+ = 0.5 mA,
REF2_5V = 0,
REFON = 1,
REFBURST = 1
ADC10SR = 0
IVREF+ = 0.5 mA,
REF2_5V = 1,
REFON = 1,
REFBURST = 1
ADC10SR = 0
ADC10SR = 1
ADC10SR = 1
mA
LSB
ADC10SR = 0
ADC10SR = 1
V
±2
400
3V
2.2 V/3 V
2.2 V/3 V
3.6 V
2000
100
±100
±110
30
ns
pF
ppm/°C
µs
1
2.2 V
2.5
2
3V
µs
4.5
The capacitance applied to the internal buffer operational amplifier, if switched to terminal P2.4/TA2/A4/VREF+/VeREF+ (REFOUT = 1),
must be limited; otherwise, the reference buffer may become unstable.
Calculated using the box method: ((MAX(VREF(T)) -- MIN(VREF(T))) / MIN(VREF(T)) / (TMAX - TMIN)
The condition is that the error in a conversion started after tREFON or tRefBuf is less than ±0.5 LSB.
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10-Bit ADC, External Reference (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VeREF+
TEST CONDITIONS
Positive external reference input
voltage range (2)
MIN
MAX
VeREF+ > VeREF-,
SREF1 = 1, SREF0 = 0
1.4
VCC
VeREF- ≤ VeREF+ ≤ (VCC - 0.15 V),
SREF1 = 1, SREF0 = 1 (3)
1.4
3
0
1.2
V
1.4
VCC
V
VeREF-
Negative external reference input
voltage range (4)
VeREF+ > VeREF-
ΔVeREF
Differential external reference
input voltage range
ΔVeREF = VeREF+ - VeREF-
VeREF+ > VeREF- (5)
IVeREF+
IVeREF(1)
(2)
(3)
(4)
(5)
0 V ≤ VeREF+ ≤ VCC,
SREF1 = 1, SREF0 = 0
Static input current into VeREF+
UNIT
V
±1
0 V ≤ VeREF+ ≤ VCC - 0.15 V ≤ 3 V,
SREF1 = 1, SREF0 = 1 (3)
0 V ≤ VeREF- ≤ VCC
Static input current into VeREF-
VCC
µA
2.2 V/3 V
0
±1
2.2 V/3 V
µA
The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the
dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
Under this condition, the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply
current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
10-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ADC10SR = 0
fADC10CLK
ADC10 input clock
frequency
For specified performance of
ADC10 linearity parameters
fADC10OSC
ADC10 built-in oscillator
frequency
ADC10DIVx = 0, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
ADC10 built-in oscillator, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
tCONVERT
Conversion time
tADC10ON
Turn on settling time of
the ADC
(1)
ADC10SR = 1
fADC10CLK from ACLK, MCLK or SMCLK,
ADC10SSELx ≠ 0
See
(1)
VCC
MIN
TYP
MAX
0.45
6.3
0.45
1.5
2.2 V/3 V
3.7
6.3
2.2 V/3 V
2.06
3.51
2.2 V/3 V
13 × ADC10DIVx ×
1 / fADC10CLK
100
UNIT
MHz
MHz
µs
ns
The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.
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10-Bit ADC, Linearity Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
EI
Integral linearity error
2.2 V/3 V
±1
LSB
ED
Differential linearity error
2.2 V/3 V
±1
LSB
EO
Offset error
2.2 V/3 V
±1
LSB
EG
Gain error
ET
(1)
Total unadjusted error
Source impedance RS < 100 Ω
SREFx = 010, unbuffered external reference,
VeREF+ = 1.5 V
2.2 V
±1.1
±2
SREFx = 010, unbuffered external reference,
VeREF+ = 2.5 V
3V
±1.1
±2
SREFx = 011, buffered external reference (1),
VeREF+ = 1.5 V
2.2 V
±1.1
±4
SREFx = 011, buffered external reference (1),
VeREF+ = 2.5 V
3V
±1.1
±3
SREFx = 010, unbuffered external reference,
VeREF+ = 1.5 V
2.2 V
±2
±5
SREFx = 010, unbuffered external reference,
VeREF+ = 2.5 V
3V
±2
±5
SREFx = 011, buffered external reference (1),
VeREF+ = 1.5 V
2.2 V
±2
±7
SREFx = 011, buffered external reference (1),
VeREF+ = 2.5 V
3V
±2
±6
TYP
MAX
2.2 V
40
120
3V
60
160
LSB
LSB
The reference buffer offset adds to the gain and total unadjusted error.
10-Bit ADC, Temperature Sensor and Built-In VMID
(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ISENSOR
Temperature sensor supply
current (1)
VCC
REFON = 0, INCHx = 0Ah,
ADC10ON = 1, TA = 25°C
ADC10ON = 1, INCHx = 0Ah (2)
TCSENSOR
VOffset,Sensor
TEST CONDITIONS
Sensor offset voltage
ADC10ON = 1, INCHx = 0Ah
2.2 V/3 V
(2)
Sensor output voltage (3)
3.55
-100
Temperature sensor voltage at
TA = 105°C (T version only)
VSENSOR
MIN
+100
1365
1465
1195
1295
1395
Temperature sensor voltage at TA = 25°C
985
1085
1185
Temperature sensor voltage at TA = 0°C
895
995
1095
2.2 V/3 V
tSENSOR(sample)
Sample time required if
channel 10 is selected (4)
ADC10ON = 1, INCHx = 0Ah,
Error of conversion result ≤ 1 LSB
IVMID
Current into divider at
channel 11 (4)
ADC10ON = 1, INCHx = 0Bh
VMID
VCC divider at channel 11
ADC10ON = 1, INCHx = 0Bh,
VMID ≈ 0.5 × VCC
2.2 V
1.06
1.1
1.14
3V
1.46
1.5
1.54
tVMID(sample)
Sample time required if
channel 11 is selected (5)
ADC10ON = 1, INCHx = 0Bh,
Error of conversion result ≤ 1 LSB
2.2 V
1400
3V
1220
(1)
(2)
(3)
(4)
(5)
46
2.2 V/3 V
µA
mV/°C
1265
Temperature sensor voltage at TA = 85°C
UNIT
mV
mV
µs
30
2.2 V
N/A (4)
3V
N/A (4)
µA
V
ns
The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is
high). When REFON = 1, ISENSOR is included in IREF+.When REFON = 0, ISENSOR applies during conversion of the temperature sensor
input (INCH = 0Ah).
The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ = TCSensor ( 273 + T [°C] ) + VOffset,sensor [mV] or
VSensor,typ = TCSensor T [°C] + VSensor(TA = 0°C) [mV]
Results based on characterization and/or production test, not TCSensor or VOffset,sensor.
No additional current is needed. The VMID is used during sampling.
The on time, tVMID(on), is included in the sampling time, tVMID(sample); no additional on time is needed.
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Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VCC (PGM/ERASE)
Program and erase supply voltage
2.2
3.6
V
fFTG
Flash timing generator frequency
257
476
kHz
IPGM
Supply current from VCC during program
2.2 V/3.6 V
1
5
mA
IERASE
Supply current from VCC during erase
2.2 V/3.6 V
1
7
mA
10
ms
(1)
tCPT
Cumulative program time
tCMErase
Cumulative mass erase time
2.2 V/3.6 V
2.2 V/3.6 V
20
104
Program/erase endurance
ms
105
cycles
tRetention
Data retention duration
TJ = 25°C
tWord
Word or byte program time
See
(2)
30
tFTG
tBlock,
0
Block program time for first byte or word
See
(2)
25
tFTG
tBlock,
1-63
Block program time for each additional
byte or word
See
(2)
18
tFTG
Block program end-sequence wait time
See
(2)
6
tFTG
Mass erase time
See
(2)
10593
tFTG
See
(2)
4819
tFTG
tBlock,
End
tMass Erase
tSeg Erase
(1)
(2)
Segment erase time
100
years
The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
These values are hardwired into the flash controller's state machine (tFTG = 1/fFTG).
RAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
V(RAMh)
(1)
RAM retention supply voltage
(1)
TEST CONDITIONS
CPU halted
MIN
MAX
UNIT
1.6
V
This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
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JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
2.2 V/3 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse length
2.2 V/3 V
0.025
15
µs
tSBW,En
Spy-Bi-Wire enable time
(TEST high to acceptance of first clock edge (1))
2.2 V/3 V
1
µs
tSBW,Ret
Spy-Bi-Wire return to normal operation time
2.2 V/3 V
15
100
2.2 V
0
5
MHz
3V
0
10
MHz
2.2 V/3 V
25
90
kΩ
fTCK
TCK input frequency (2)
RInternal
Internal pulldown resistance on TEST
(1)
(2)
60
µs
Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before
applying the first SBWCLK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
JTAG Fuse (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC(FB)
Supply voltage during fuse-blow condition
VFB
Voltage level on TEST for fuse blow
IFB
Supply current into TEST during fuse blow
tFB
Time to blow fuse
(1)
48
TEST CONDITIONS
TA = 25°C
MIN
MAX
UNIT
2.5
6
V
7
V
100
mA
1
ms
Once the fuse is blown, no further access to the JTAG/Test and emulation features is possible, and the JTAG block is switched to
bypass mode.
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APPLICATION INFORMATION
Port P1 Pin Schematic: P1.0, Input/Output With Schmitt Trigger
Pad Logic
P1REN.0
0
P1DIR.0
P1SEL2.0
0
from
Comparator
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
ADC10CLK
DVSS
1
P1OUT.0
0
P1.0/TACLK/
ADC10CLK/CAOUT
Bus
Keeper
EN
P1SEL.0
P1IN.0
EN
Module X IN
D
P1IE.x
EN
P1IRQ.0
Q
Set
P1IFG.x
P1SEL.0
P1IES.0
Interrupt
Edge Select
Table 18. Port P1 (P1.0) Pin Functions
PIN NAME (P1.x)
x
FUNCTION
P1SEL.x
P1SEL2.x
I: 0, O: 1
0
0
Timer0_A3.TACLK, Timer1_A2.TACLK
0
1
0
ADC10CLK
1
1
0
CAOUT
1
1
1
P1.0 (I/O)
P1.0/TACLK/
ADC10CLK/CAOUT
0
CONTROL BITS / SIGNALS
P1DIR.x
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Port P1 Pin Schematic: P1.1 to P1.3, Input/Output With Schmitt Trigger
Pad Logic
P1REN.x
0
P1DIR.x
1
P1OUT.x
0
0
DVCC
1
1
Direction
0: Input
1: Output
1
Timer0_A3
output
DVSS
P1.1/TA0_0/TA0_1
P1.2/TA1_0
P1.3/TA2_0
Bus
Keeper
P1SEL.x
EN
P1IN.x
EN
Module X IN
D
P1IE.x
P1IRQ.x
EN
Q
Set
P1IFG.x
P1SEL.x
Interrupt
Edge Select
P1IES.x
Table 19. Port P1 (P1.1 to P1.3) Pin Functions
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
P1SEL2.x
I: 0; O: 1
0
0
Timer0_A3.CCI0A, Timer1_A2.CCI0A
0
1
0
Timer0_A3.TA0
1
1
0
I: 0; O: 1
0
0
Timer0_A3.CCI1A
0
1
0
Timer0_A3.TA1
1
1
0
I: 0; O: 1
0
0
Timer0_A3.CCI2A
0
1
0
Timer0_A3.TA2
1
1
0
P1.1 (I/O)
P1.1/TA0.0/TA1.0
1
P1.2 (I/O)
P1.2/TA0.1
2
P1.3 (I/O)
P1.3/TA0.2
50
3
CONTROL BITS / SIGNALS
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Port P1 Pin Schematic: P1.4
P1REN.4
Pad Logic
P1DIR.4
0
1
P1OUT.x
0
0
DVCC
1
1
Direction
0: Input
1: Output
1
SMCLK
DVSS
P1.4/SMCLK/TCK
Bus
Keeper
EN
P1SEL.4
P1IN.4
EN
Module X IN
D
P1IE.x
P1IRQ.4
EN
Q
Set
P1IFG.x
P1SEL.x
P1IES.x
Interrupt
Edge Select
To JTAG
From JTAG
Table 20. Port P1 (P1.4) Pin Functions
CONTROL BITS / SIGNALS (1)
PIN NAME (P1.x)
x
FUNCTION
P1.4 (I/O)
P1.4/SMCLK/TCK
(1)
(2)
4
P1DIR.x
P1SEL.x
P1SEL2.x=0
JTAG Mode
I: 0; O: 1
0
0
SMCLK
1
1
0
TCK (2)
X
X
1
X = Don't care
In JTAG mode, the internal pullup/pulldown resistors are disabled.
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Port P1 Pin Schematic: P1.5 to P1.7
P1REN.x
Pad Logic
P1DIR.x
0
1
P1OUT.x
0
0
DVCC
1
1
Direction
0: Input
1: Output
1
Module X Out
DVSS
P1.5/TA0.0/TMS
P1.6/TA0.1/TCLK
P1.7/TA0.2/TDO/TDI
Bus
Keeper
EN
P1SEL.x
P1IN.x
EN
Module X In
D
P1IE.x
EN
P1IRQ.x
Q
Set
P1IFG.x
P1SEL.x
Interrupt
Edge Select
P1IES.x
To JTAG
From JTAG
Table 21. Port P1 (P1.5 to P1.7) Pin Functions
CONTROL BITS / SIGNALS (1)
PIN NAME (P1.x)
x
FUNCTION
P1.5 (I/O)
P1.5/TA0.0/TMS
5
6
(1)
(2)
52
7
JTAG Mode
I: 0; O: 1
0
0
1
1
0
TMS (2)
X
X
1
I: 0; O: 1
0
0
Timer0_A3.TA1
1
1
0
TDI/TCLK (2)
X
X
1
I: 0; O: 1
0
0
Timer0_A3.TA2
1
1
0
TDO/TDI (2)
X
X
1
P1.6 (I/O)
P1.7/TA0.2/TDO/TDI
P1SEL.x
P1SEL2.x=0
Timer0_A3.TA0
P1.6 (I/O)
P1.6/TA0.1/TDI/TCLK
P1DIR.x
X = Don't care
In JTAG mode, the internal pullup/pulldown resistors are disabled.
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MSP430F21x2
SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012
www.ti.com
Port P2 Pin Schematic: P2.0 and P2.1, Input/Output With Schmitt Trigger
Pad Logic
To ADC10
INCHx = y
To
Comparator_A
From
Comparator_A
CAPD.x
ADC10AE0.y
P2REN.x
DVSS
0
DVCC
1
1
P2DIR.x
0
Direction
0: Input
1: Output
1
P2OUT.x
0
Module X OUT
1
P2.0/ACLK/A0/CA2
P2.1/TAINCLK/
SMCLK/A1/CA3
Bus
Keeper
EN
P2SEL.x
P2IN.x
EN
Module X IN
D
P2IE.x
P2IRQ.x
EN
Q
P2IFG.x
P2SEL.x
P2IES.x
Set
Interrupt
Edge Select
Table 22. Port P2 (P2.0 and P2.1) Pin Functions
CONTROL BITS / SIGNALS (1)
PIN NAME (P2.x)
P2.0/ACLK/A0/CA2
P2.1/TAINCLK/
SMCLK/A1/CA3
(1)
x
0
1
FUNCTION
ADC10AE0.y
CAPD.x
P2DIR.x
P2SEL.x
P2SEL2.x = 0
P2.0 (I/O)
0
0
I: 0; O: 1
0
ACLK
0
0
1
1
A0
1
0
X
X
CA2
0
1
X
X
P2.1 (I/O)
0
0
I: 0; O: 1
0
Timer0_A3.TAINCLK, Timer1_A2.TAINCLK
0
0
0
1
SMCLK
0
0
1
1
A1
1
0
X
X
CA3
0
1
X
X
X = Don't care
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MSP430F21x2
SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012
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Port P2 Pin Schematic: P2.2, Input/Output With Schmitt Trigger
Pad Logic
To ADC10
INCHx = y
To Comparator_A
From Comparator_A
CAPD.x
ADC10AE0.y
P2REN.x
DVSS
0
DVCC
1
1
P2DIR.2
0
P2SEL2.2
1
Module output
0
From Comparator
1
Direction
0: Input
1: Output
1
0
P2OUT.2
P2.2/TA0.0/A2/CA4/CAOUT
Bus
Keeper
EN
P2SEL.2
P2IN.2
EN
Module X IN
D
P2IE.x
EN
P2IRQ.2
Q
Set
P2IFG.x
P2SEL.x
Interrupt
Edge Select
P2IES.x
Table 23. Port P2 (P2.2) Pin Functions
PIN NAME (P2.x)
P2.2/TA0.0/A2/CA4/CAOUT
(1)
54
x
2
FUNCTION
CONTROL BITS / SIGNALS (1)
ADC10AE0.x
CAPD.x
P2DIR.x
P2SEL.x
P2SEL2.x
P2.0 (I/O)
0
0
I: 0; O: 1
0
0
Timer0_A3.TA0
0
0
1
1
0
Timer0_A3.CCI0B
0
0
0
1
0
A2
1
0
X
X
X
CA4
0
1
X
X
X
CAOUT
0
0
1
1
1
X = Don't care
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MSP430F21x2
SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012
www.ti.com
Port P2 Pin Schematic: P2.3 and P2.4, Input/Output With Schmitt Trigger
Pad Logic
To/from ADC10
Reference
To ADC10
INCHx = y
To
Comparator_A
From
Comparator_A
CAPD.x
ADC10AE0.y
P2REN.x
DVSS
0
DVCC
1
1
P2DIR.x
0
Direction
0: Input
1: Output
1
P2OUT .x
Module X OUT
0
1
P2.3/TA0.1/A3/
VREF−/VeREF−/CA0
Bus
Keeper
EN
P2SEL.x
P2IN.x
P2.4/TA0.2/A4/
VREF+/VeREF+/CA1
EN
Module X IN
D
P2IE.x
P2IRQ.x
EN
Q
Set
P2IFG.x
P2SEL.x
Interrupt
Edge Select
P2IES.x
Table 24. Port P2 (P2.3 and P2.4) Pin Functions
CONTROL BITS / SIGNALS (1)
PIN NAME (P2.x)
P2.3/TA0.1/A3/
VREF-/VeREF-/CA0
(1)
x
3
FUNCTION
ADC10AE0.y
CAPD.x
P2DIR.x
P2SEL.x
P2SEL2.x = 0
P2.3 (I/O)
0
0
I: 0; O: 1
0
Timer0_A3.TA1
0
0
1
1
A3/VREF-/VeREF-
1
0
X
X
CA0
0
1
X
X
X = Don't care
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MSP430F21x2
SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012
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Table 24. Port P2 (P2.3 and P2.4) Pin Functions (continued)
CONTROL BITS / SIGNALS (1)
PIN NAME (P2.x)
P2.4/TA0.2/A4/
VREF+/VeREF+/CA1
56
x
4
FUNCTION
ADC10AE0.y
CAPD.x
P2DIR.x
P2SEL.x
P2SEL2.x = 0
P2.4 (I/O)
0
0
I: 0; O: 1
0
Timer0_A3.TA2
0
0
1
1
A4/VREF+/VeREF+
1
0
X
X
CA1
0
1
X
X
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MSP430F21x2
SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012
www.ti.com
Port P2 Pin Schematic: P2.5, Input/Output With Schmitt Trigger
Pad Logic
To Comparator
From Comparator
CAPD.x
To DCO
DCOR
in DCO
P2REN.x
P2DIR.5
0
P2OUT.5
0
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
Module X OUT
DVSS
P2.5/ROSC/CA5
Bus
Keeper
EN
P2SEL.x
P2IN.5
EN
Module X IN
D
P2IE.5
P2IRQ.5
EN
Q
P2IFG.5
P2SEL.5
P2IES.5
Set
Interrupt
Edge Select
Table 25. Port P2 (P2.5) Pin Functions
CONTROL BITS / SIGNALS (1)
PIN NAME (P2.x)
P2.5/ROSC/CA5
(1)
(2)
x
5
FUNCTION
P2SEL.5
P2SEL2.x = 0
CAPD.5
DCOR
P2DIR.5
P2.5 (I/O)
0
0
I: 0, O: 1
0
ROSC
0
1
X
X
DVSS
0
0
1
1
CA5 (2)
1
0
X
X
X = Don't care
Setting the CAPD.x bit disables the output driver as well as the input to prevent parasitic cross currents when applying analog signals.
Selecting the CAx input to the comparator multiplexer with the P2CAx bits automatically disables the input buffer for that pin, regardless
of the state of the associated CAPD.x bit.
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MSP430F21x2
SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012
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Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger
BCSCTL3.LFXT1Sx = 11
P2.7/XOUT/CA7
LFXT1 off
0
LFXT1CLK
1
Pad Logic
To Comparator
From
Comparator
P2SEL.7
CAPD.6
P2REN.6
P2DIR.6
0
0
Module X OUT
1
0
1
1
Direction
0: Input
1: Output
1
P2OUT.6
DVSS
DVCC
P2.6/XIN/CA6
Bus
Keeper
EN
P2SEL.6
P2IN.6
EN
Module X IN
D
P2IE.6
P2IRQ.6
EN
Q
P2IFG.6
P2SEL.6
P2IES.6
Set
Interrupt
Edge Select
Table 26. Port P2 (P2.6) Pin Functions
CONTROL BITS / SIGNALS (1)
PIN NAME (P2.x)
P2.6/XIN/CA6
(1)
(2)
58
x
6
FUNCTION
CAPD.6
P2DIR.6
P2SEL.6
P2SEL2.x = 0
P2.6 (I/O)
0
I: 0; O: 1
0
XIN (default)
X
1
1
CA6 (2)
1
X
0
X = Don't care
Setting the CAPD.x bit disables the output driver as well as the input to prevent parasitic cross currents when applying analog signals.
Selecting the CAx input to the comparator multiplexer with the P2CAx bits automatically disables the input buffer for that pin, regardless
of the state of the associated CAPD.x bit.
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MSP430F21x2
SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012
www.ti.com
Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger
BCSCTL3.LFXT1Sx = 11
P2.6/XIN/CA6
LFXT1 off
0
LFXT1CLK
From P2.6/XIN
1
Pad Logic
To Comparator
From
Comparator
P2SEL.6
CAPD.7
P2REN.7
P2DIR.7
0
0
Module X OUT
1
0
1
1
Direction
0: Input
1: Output
1
P2OUT.7
DVSS
DVCC
P2.7/XOUT/CA7
Bus
Keeper
EN
P2SEL.7
P2IN.7
EN
Module X IN
D
P2IE.7
P2IRQ.7
EN
Q
P2IFG.7
Set
Interrupt
Edge Select
P2SEL.7
P2IES.7
Table 27. Port P2 (P2.7) Pin Functions
CONTROL BITS / SIGNALS (1)
PIN NAME (P2.x)
P2.7/XOUT/CA7
(1)
(2)
x
7
FUNCTION
CAPD.7
P2DIR.7
P2SEL.7
P2SEL2.x = 0
P2.7 (I/O)
0
I: 0, O: 1
0
XOUT (default)
X
1
1
CA7 (2)
1
X
0
X = Don't care
Setting the CAPD.x bit disables the output driver as well as the input to prevent parasitic cross currents when applying analog signals.
Selecting the CAx input to the comparator multiplexer with the P2CAx bits automatically disables the input buffer for that pin, regardless
of the state of the associated CAPD.x bit.
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MSP430F21x2
SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012
www.ti.com
Port P3 Pin Schematic: P3.0, Input/Output With Schmitt Trigger
Pad Logic
To ADC10
INCHx = y
ADC10AE0.y
P3REN.x
P3DIR.x
Module
direction
0
P3OUT.x
0
Module X OUT
1
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P3.0/UCB0STE/
UCA0CLK/A5
Bus
Keeper
EN
P3SEL.x
P3IN.x
Table 28. Port P3 (P3.0) Pin Functions
CONTROL BITS / SIGNALS (1)
PIN NAME (P3.x)
P3.0/UCB0STE/
UCA0CLK/A5
(1)
(2)
60
x
0
FUNCTION
ADC10AE0.y
P3DIR.x
P3SEL.x
P3SEL2.x = 0
P3.0 (I/O)
0
I: 0; O: 1
0
UCB0STE/UCA0CLK (2)
0
X
1
A5 (2)
1
X
X
X = Don't care
The pin direction is controlled by the USCI module.
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MSP430F21x2
SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012
www.ti.com
Port P3 Pin Schematic: P3.1 to P3.5, Input/Output With Schmitt Trigger
Pad Logic
P3REN.x
P3DIR.x
Module
direction
0
P3OUT.x
0
Module X OUT
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
1
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
Bus
Keeper
EN
P3SEL.x
P3IN.x
EN
Module X IN
D
Table 29. Port P3 (P3.1 to P3.5) Pin Functions
PIN NAME (P3.x)
P3.1/UCB0SIMO/
UCB0SDA
P3.2/UCB0SOMI/
UCB0SCL
P3.3/UCB0CLK/
UCA0STE
P3.4/UCA0TXD/
UCA0SIMO
P3.5/UCA0RXD/
UCA0SOMI
(1)
(2)
(3)
x
1
2
3
4
5
FUNCTION
P3.1 (I/O)
UCB0SIMO/UCB0SDA (2) (3)
P3.2 (I/O)
UCB0SOMI/UCB0SCL (2) (3)
P3.3 (I/O)
UCB0CLK/UCA0STE (2)
P3.4 (I/O)
UCA0TXD/UCA0SIMO (2)
P3.5 (I/O)
UCA0RXD/UCA0SOMI
(2)
CONTROL BITS / SIGNALS (1)
P3DIR.x
P3SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
X = Don't care
The pin direction is controlled by the USCI module.
If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
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MSP430F21x2
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Port P3 Pin Schematic: P3.6 and P3.7, Input/Output With Schmitt Trigger
Pad Logic
To ADC10
INCHx = y
ADC10AE0.y
P3REN.x
0
P3DIR.x
P3OUT.x
0
1
0
DVCC
1
Direction
0: Input
1: Output
1
Module X OUT
DVSS
P3.6/TA0_1/A6
P3.7/TA1_1/A7
Bus
Keeper
EN
P3SEL.x
P3IN.x
Table 30. Port P3 (P3.6 and P3.7) Pin Functions
PIN NAME (P3.x)
P3.6/TA1.0/A6
P3.7/TA1.1/A7
(1)
62
x
6
7
FUNCTION
CONTROL BITS / SIGNALS (1)
ADC10AE0.y
P3DIR.x
P3SEL.x
P3.6 (I/O)
0
I: 0; O: 1
0
Timer1_A2.TA0
0
1
1
Timer1_A2.CCI0B
0
0
1
A6
1
X
X
P3.7 (I/O)
0
I: 0; O: 1
0
Timer1_A2.TA1
0
1
1
Timer1_A2.CCI1A
0
0
1
A7
1
X
X
X = Don't care
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MSP430F21x2
SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012
www.ti.com
JTAG Fuse Check Mode
MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the
fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care
must be taken to avoid accidentally activating the fuse check mode and increasing overall system power
consumption.
When the TEST pin is again taken low after a test or programming session, the fuse check mode and sense
currents are terminated.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS is
being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode.
After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse
check mode has the potential to be activated.
The fuse check current flows only when the fuse check mode is active and the TMS pin is in a low state (see
Figure 31). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
Time TMS Goes Low After POR
TMS
ITF
ITEST
Figure 31. Fuse Check Mode Current
NOTE
The CODE and RAM data protection is ensured if the JTAG fuse is blown and the 256-bit
bootloader access key is used. Also, see the Bootstrap Loader section for more
information.
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MSP430F21x2
SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012
www.ti.com
REVISION HISTORY
LITERATURE
NUMBER
SUMMARY
SLAS578
Product Preview data sheet release
SLAS578A
Production Data data sheet release
SLAS578B
Corrected timer pin names throughout: TA0_0 changed to TA0.0, TA0_1 changed to TA1.0, TA1_0 changed to TA0.1,
TA2_0 changed to TA0.2, TA1_1 changed to TA1.1
Added development tool information (page 2).
SLAS578C
Corrected TAG_ADC10_1 value from 0x10 to 0x08 (page 14).
Corrected all address offsets in Labels Used By The ADC Calibration Tags table (page 14).
Changed JTAG fuse check mode section (page 73).
Corrected parametric values in active mode supply current (into VCC) excluding external current table (page 20).
SLAS578D
Corrected parametric values and temperature ranges in low-power mode supply currents (into VCC) excluding external
current table (page 22).
SLAS578E
Corrected TAx.y pin names on RHB pinout drawing (page 3).
Changed TDI/TCLK to TEST in Note 2 of absolute maximum ratings table (page 19).
SLAS578F
Changed lower limit of Storage temperature, Programmed device from -40°C to -55°C in absolute maximum ratings table
(page 19).
In the Labels Used By The ADC Calibration Tags table, changed the Address Offset of CAL_ADC_15T30 from 0x0006 to
0x0008 and the Address Offset of CAL_ADC_15VREF_FACTOR from 0x0005 to 0x0006 (page 14).
Changed TDI/TCLK to TEST in the Parameter description for IFB in the JTAG fuse table (page 52).
Updated Port P1 pin schematic: P1.0, input/output with Schmitt trigger (page 53).
Updated Port P1 pin schematic: P1.1 to P1.3, input/output with Schmitt trigger (page 54).
Updated Port P1 (P1.1 to P1.3) pin functions table (page 54).
SLAS578G
Removed Timer0_A3.CCU0B row from Port P1 (P1.5 to P1.7) pin functions table (page 56).
Updated Port P3 pin schematic: P3.1 to P3.5, input/output with Schmitt trigger (page 69).
Removed P3SEL2.x = 0 from Port P3 (P3.1 to P3.5) pin functions table header row (page 69).
Removed P3SEL2 = 0 from Port P3 (P3.6 and P3.7) pin functions table header row (page 70).
Removed JTAG pins: TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger (page 71).
Updated JTAG fuse check mode section (page 72).
SLAS578H
Corrected schematic drawings for Port 1 and Port 2 (pages 54, 55, 56, 59, 61)
Add information for RTV package options
SLAS578I
Changed Storage temperature range limit in Absolute Maximum Ratings
SLAS578J
Changed note (4) on 10-Bit ADC, Power Supply and Input Range Conditions.
64
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
MSP430F2112IPW
ACTIVE
TSSOP
PW
28
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
M430F2112
MSP430F2112IPWR
ACTIVE
TSSOP
PW
28
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
M430F2112
MSP430F2112IRHBR
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
MSP430
F2112
MSP430F2112IRHBT
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
MSP430
F2112
MSP430F2112TPW
ACTIVE
TSSOP
PW
28
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 105
430F2112T
MSP430F2112TPWR
ACTIVE
TSSOP
PW
28
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 105
430F2112T
MSP430F2112TRHBR
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
MSP430
F2112T
MSP430F2112TRHBT
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
MSP430
F2112T
MSP430F2122IPW
ACTIVE
TSSOP
PW
28
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
M430F2122
MSP430F2122IPWR
ACTIVE
TSSOP
PW
28
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
M430F2122
MSP430F2122IRHBR
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
MSP430
F2122
MSP430F2122IRHBT
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
MSP430
F2122
MSP430F2122TPW
ACTIVE
TSSOP
PW
28
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 105
430F2122T
MSP430F2122TPWR
ACTIVE
TSSOP
PW
28
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 105
430F2122T
MSP430F2122TRHBR
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
MSP430
F2122T
MSP430F2122TRHBT
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
MSP430
F2122T
MSP430F2122TRTVT
ACTIVE
WQFN
RTV
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
MSP430
F2122T
MSP430F2132IPW
ACTIVE
TSSOP
PW
28
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
M430F2132
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
10-Dec-2020
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
MSP430F2132IPWR
ACTIVE
TSSOP
PW
28
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
M430F2132
MSP430F2132IRHBR
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
MSP430
F2132
MSP430F2132IRHBT
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
MSP430
F2132
MSP430F2132IRTVT
ACTIVE
WQFN
RTV
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
MSP430
F2132
MSP430F2132TPW
ACTIVE
TSSOP
PW
28
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 105
430F2132T
MSP430F2132TPWR
ACTIVE
TSSOP
PW
28
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 105
430F2132T
MSP430F2132TRHBR
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
MSP430
F2132T
MSP430F2132TRHBT
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
MSP430
F2132T
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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