MSP430F2410TPMR

厂商：
BURR-BROWN(德州仪器)
封装：
LQFP-64
描述：
IC MCU 16BIT 56KB FLASH 64LQFP

数据手册：

下载MSP430F2410TPMR.pdf

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数据手册
价格&库存

MSP430F2410TPMR 数据手册

MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 MIXED SIGNAL MICROCONTROLLER FEATURES 1 • • 23 • • • • • • • Low Supply-Voltage Range, 1.8 V to 3.6 V Ultra-Low Power Consumption – Active Mode: 270 µA at 1 MHz, 2.2 V – Standby Mode (VLO): 0.3 µA – Off Mode (RAM Retention): 0.1 µA Ultra-Fast Wake-Up From Standby Mode in Less Than 1 µs 16-Bit RISC Architecture, 62.5-ns Instruction Cycle Time Basic Clock Module Configurations: – Internal Frequencies up to 16 MHz – Internal Very Low-Power LF Oscillator – 32-kHz Crystal – Internal Frequencies up to 16 MHz With Four Calibrated Frequencies to ±1% – Resonator – External Digital Clock Source – External Resistor 12-Bit Analog-to-Digital (A/D) Converter With Internal Reference, Sample-and-Hold, and Autoscan Feature 16-Bit Timer_A With Three Capture/Compare Registers 16-Bit Timer_B With Seven Capture/Compare With Shadow Registers Four Universal Serial Communication Interfaces (USCI) – USCI_A0 and USCI_A1 – Enhanced UART Supporting Auto-Baudrate Detection – IrDA Encoder and Decoder – Synchronous SPI – USCI_B0 and USCI_B1 – I2C™ – Synchronous SPI • • • • • • • • (1) On-Chip Comparator Supply Voltage Supervisor/Monitor With Programmable Level Detection Brownout Detector Bootstrap Loader Serial Onboard Programming, No External Programming Voltage Needed, Programmable Code Protection by Security Fuse Family Members Include: – MSP430F233 – 8KB+256B Flash Memory, – 1KB RAM – MSP430F235 – 16KB+256B Flash Memory – 2KB RAM – MSP430F247, MSP430F2471 (1) – 32KB+256B Flash Memory – 4KB RAM – MSP430F248, MSP430F2481 – 48KB+256B Flash Memory – 4KB RAM – MSP430F249, MSP430F2491 – 60KB+256B Flash Memory – 2KB RAM – MSP430F2410 – 56KB+256B Flash Memory – 4KB RAM Available in 64-Pin QFP and 64-Pin QFN Packages (See Available Options) For Complete Module Descriptions, See MSP430x2xx Family User’s Guide (SLAU144) The MSP430F24x1 devices are identical to the MSP430F24x devices, with the exception that the ADC12 module is not implemented on the MSP430F24x1. 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. MSP430 is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DESCRIPTION The Texas Instruments MSP430™ family of ultra-low power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The calibrated digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs. The MSP430F23x, MSP430F24x(1), and MSP430F2410 series are microcontroller configurations with two builtin 16-bit timers, a fast 12-bit A/D converter (not MSP430F24x1), a comparator, four (two in MSP430F23x) universal serial communication interface (USCI) modules, and up to 48 I/O pins. The MSP430F24x1 devices are identical to the MSP430F24x devices, with the exception that the ADC12 module is not implemented. The MSP430F23x devices are identical to the MSP430F24x devices, with the exception that a reduced Timer_B, one USCI module, and less RAM are integrated. Typical applications include sensor systems, industrial control applications, and hand-held meters. Table 1. Available Options TA -40°C to 105°C (1) (2) PACKAGED DEVICES (1) (2) PLASTIC 64-PIN QFP (PM) PLASTIC 64-PIN QFN (RGC) MSP430F233TPM MSP430F233TRGC MSP430F235TPM MSP430F235TRGC MSP430F247TPM MSP430F247TRGC MSP430F2471TPM MSP430F2471TRGC MSP430F248TPM MSP430F248TRGC MSP430F2481TPM MSP430F2481TRGC MSP430F249TPM MSP430F249TRGC MSP430F2491TPM MSP430F2491TRGC MSP430F2410TPM MSP430F2410TRGC For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Development Tool Support All MSP430 microcontrollers include an Embedded Emulation Module (EEM) allowing advanced debugging and programming through easy to use development tools. Recommended hardware options include the following: • Debugging and Programming Interface – MSP-FET430UIF (USB) – MSP-FET430PIF (Parallel Port) • Debugging and Programming Interface with Target Board – MSP-FET430U64 (PM package) • Standalone Target Board – MSP-TS430PM64 (PM package) • Production Programmer – MSP-GANG430 2 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 AVCC DVSS AVSS P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P5.7/TBOUTH/SVSOUT P5.6/ACLK P5.5/SMCLK Device Pinout, MSP430F23x PM OR RGC PACKAGE (TOP VIEW) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 2 47 3 46 4 5 45 6 43 7 42 44 8 41 MSP430F23x 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P5.4/MCLK P5.3 P5.2 P5.1 P5.0 P4.7/TBCLK P4.6 P4.5 P4.4 P4.3 P4.2/TB2 P4.1/TB1 P4.0/TB0 P3.7 P3.6 P3.5/UCA0RXD/UCA0SOMI P1.5/TA0 P1.6/TA1 P1.7/TA2 P2.0/ACLK/CA2 P2.1/TAINCLK/CA3 P2.2/CAOUT/TA0/CA4 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.5/ROSC/CA5 P2.6/ADC12CLK/CA6 P2.7/TA0/CA7 P3.0/UCB0STE/UCA0CLK P3.1/UCB0SIMO/UCB0SDA P3.2/UCB0SOMI/UCB0SCL P3.3/UCB0CLK/UCA0STE P3.4/UCA0TXD/UCA0SIMO DVCC P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6 P6.7/A7/SVSIN VREF+ XIN XOUT VeREF+ VREF-/VeREFP1.0/TACLK/CAOUT P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 3 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com AVCC DVSS AVSS P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P5.7/TBOUTH/SVSOUT P5.6/ACLK P5.5/SMCLK Device Pinout, MSP430F24x, MSP430F2410 PM OR RGC PACKAGE (TOP VIEW) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 2 47 3 46 4 5 45 6 43 7 42 44 8 MSP430F2410, MSP430F24x 9 41 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P5.4/MCLK P5.3/UCB1CLK/UCA1STE P5.2/UCB1SOMI/UCB1SCL P5.1/UCB1SIMO/UCB1SDA P5.0/UCB1STE/UCA1CLK P4.7/TBCLK P4.6/TB6 P4.5/TB5 P4.4/TB4 P4.3/TB3 P4.2/TB2 P4.1/TB1 P4.0/TB0 P3.7/UCA1RXD/UCA1SOMI P3.6/UCA1TXD/UCA1SIMO P3.5/UCA0RXD/UCA0SOMI P1.5/TA0 P1.6/TA1 P1.7/TA2 P2.0/ACLK/CA2 P2.1/TAINCLK/CA3 P2.2/CAOUT/TA0/CA4 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.5/ROSC/CA5 P2.6/ADC12CLK/CA6 P2.7/TA0/CA7 P3.0/UCB0STE/UCA0CLK P3.1/UCB0SIMO/UCB0SDA P3.2/UCB0SOMI/UCB0SCL P3.3/UCB0CLK/UCA0STE P3.4/UCA0TXD/UCA0SIMO DVCC P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6 P6.7/A7/SVSIN VREF+ XIN XOUT VeREF+ VREF-/VeREFP1.0/TACLK/CAOUT P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK 4 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 AVCC DVSS AVSS P6.2 P6.1 P6.0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P5.7/TBOUTH/SVSOUT P5.6/ACLK P5.5/SMCLK Device Pinout, MSP430F24x1 PM OR RGC PACKAGE (TOP VIEW) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 2 47 3 46 4 5 45 6 43 7 42 44 8 41 MSP430F24x1 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P5.4/MCLK P5.3/UCB1CLK/UCA1STE P5.2/UCB1SOMI/UCB1SCL P5.1/UCB1SIMO/UCB1SDA P5.0/UCB1STE/UCA1CLK P4.7/TBCLK P4.6/TB6 P4.5/TB5 P4.4/TB4 P4.3/TB3 P4.2/TB2 P4.1/TB1 P4.0/TB0 P3.7/UCA1RXD/UCA1SOMI P3.6/UCA1TXD/UCA1SIMO P3.5/UCA0RXD/UCA0SOMI P1.5/TA0 P1.6/TA1 P1.7/TA2 P2.0/ACLK/CA2 P2.1/TAINCLK/CA3 P2.2/CAOUT/TA0/CA4 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.5/ROSC/CA5 P2.6/ADC12CLK/CA6 P2.7/TA0/CA7 P3.0/UCB0STE/UCA0CLK P3.1/UCB0SIMO/UCB0SDA P3.2/UCB0SOMI/UCB0SCL P3.3/UCB0CLK/UCA0STE P3.4/UCA0TXD/UCA0SIMO DVCC P6.3 P6.4 P6.5 P6.6 P6.7/A7/SVSIN VREF+ XIN XOUT DVSS DVSS P1.0/TACLK/CAOUT P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 5 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Functional Block Diagram, MSP430F23x XIN/ XT2IN XOUT/ XT2OUT 2 DVCC DVSS AVCC AVSS 2 P1.x/P2.x P3.x/P4.x P5.x/P6.x 2x8 4x8 ACLK Oscillators Basic Clock SMCLK System+ Flash RAM 16kB 8kB 2kB 1kB MCLK 16MHz CPU incl. 16 Registers 8 Channels Ports P1/P2 Ports P3/P4 P5/P6 2x8 I/O Interrupt capability 4x8 I/O MAB MDB Emulation JTAG Interface ADC12 12-Bit Hardware Multiplier BOR SVS/SVM MPY, MPYS, MAC, MACS Timer_B3 Watchdog WDT+ 15/16-Bit Timer_A3 3 CC Registers 3 CC Registers, Shadow Reg USCI A0 UART/LIN, IrDA, SPI Comp_A+ USCI B0 SPI, I2C RST/NMI 6 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Functional Block Diagram, MSP430F24x, MSP430F2410 XIN/ XT2IN XOUT/ XT2OUT 2 DVCC DVSS AVCC AVSS 2 P1.x/P2.x P3.x/P4.x P5.x/P6.x 2x8 4x8 ACLK Oscillators Basic Clock SMCLK System+ MCLK 16MHz CPU incl. 16 Registers Flash RAM 60kB 56kB 48kB 32kB 2kB 4kB 4kB 4kB 2x8 I/O Interrupt capability 8 Channels Ports P3/P4 P5/P6 4x8 I/O MAB MDB Emulation JTAG Interface Ports P1/P2 ADC12 12-Bit Hardware Multiplier BOR SVS/SVM MPY, MPYS, MAC, MACS Timer_B7 Watchdog WDT+ 15/16-Bit Timer_A3 3 CC Registers 7 CC Registers, Shadow Reg USCI A0 UART/LIN, IrDA, SPI USCI A1 UART/LIN, IrDA, SPI USCI B0 SPI, I2C USCI B1 SPI, I2C Comp_A+ RST/NMI Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 7 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Functional Block Diagram, MSP430F24x1 XIN/ XT2IN XOUT/ XT2OUT 2 DVCC DVSS AVCC AVSS 2 P1.x/P2.x P3.x/P4.x P5.x/P6.x 2x8 4x8 ACLK Oscillators Basic Clock SMCLK System+ MCLK 16MHz CPU incl. 16 Registers Flash RAM 60kB 48kB 32kB 2kB 4kB 4kB Ports P3/P4 P5/P6 2x8 I/O Interrupt capability 4x8 I/O MAB MDB Emulation JTAG Interface Ports P1/P2 Hardware Multiplier BOR SVS/SVM MPY, MPYS, MAC, MACS Timer_B7 Watchdog WDT+ 15/16-Bit Timer_A3 3 CC Registers 7 CC Registers, Shadow Reg USCI A0 UART/LIN, IrDA, SPI USCI A1 UART/LIN, IrDA, SPI USCI B0 SPI, I2C USCI B1 SPI, I2C Comp_A+ RST/NMI 8 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Table 2. Terminal Functions, MSP430F23x TERMINAL NAME NO. I/O DESCRIPTION AVCC 64 Analog supply voltage, positive. Supplies only the analog portion of ADC12. AVSS 62 Analog supply voltage, negative. Supplies only the analog portion of ADC12. DVCC 1 Digital supply voltage, positive. Supplies all digital parts. DVSS 63 P1.0/TACLK/CAOUT 12 I/O General-purpose digital I/O / Timer_A, clock signal TACLK input/Comparator_A output P1.1/TA0 13 I/O General-purpose digital I/O / Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit P1.2/TA1 14 I/O General-purpose digital I/O / Timer_A, capture: CCI1A input, compare: Out1 output P1.3/TA2 15 I/O General-purpose digital I/O / Timer_A, capture: CCI2A input, compare: Out2 output P1.4/SMCLK 16 I/O General-purpose digital I/O / SMCLK signal output P1.5/TA0 17 I/O General-purpose digital I/O / Timer_A, compare: Out0 output P1.6/TA1 18 I/O General-purpose digital I/O / Timer_A, compare: Out1 output P1.7/TA2 19 I/O General-purpose digital I/O / Timer_A, compare: Out2 output P2.0/ACLK/CA2 20 I/O General-purpose digital I/O / ACLK output/Comparator_A input P2.1/TAINCLK/CA3 21 I/O General-purpose digital I/O / Timer_A, clock signal at INCLK P2.2/CAOUT/TA0/CA4 22 I/O General-purpose digital I/O / Timer_A, capture: CCI0B input/Comparator_A output/BSL receive/Comparator_A input P2.3/CA0/TA1 23 I/O General-purpose digital I/O / Timer_A, compare: Out1 output/Comparator_A input P2.4/CA1/TA2 24 I/O General-purpose digital I/O / Timer_A, compare: Out2 output/Comparator_A input P2.5/ROSC/CA5 25 I/O General-purpose digital I/O / input for external resistor defining the DCO nominal frequency/Comparator_A input P2.6/ADC12CLK/CA6 26 I/O General-purpose digital I/O / conversion clock - 12-bit ADC/Comparator_A input P2.7/TA0/CA7 27 I/O General-purpose digital I/O / Timer_A, compare: Out0 output/Comparator_A input P3.0/UCB0STE/ UCA0CLK 28 I/O General-purpose digital I/O / USCI_B0 slave transmit enable/USCI A0 clock input/output P3.1/UCB0SIMO/UCB0SDA 29 I/O General-purpose digital I/O / USCI_B0 slave in/master out in SPI mode, SDA I2C data in I2C mode P3.2/UCB0SOMI/ UCB0SCL 30 I/O General-purpose digital I/O / USCI_B0 slave out/master in in SPI mode, SCL I2C clock in I2C mode P3.3/UCB0CLK/UCA0STE 31 I/O General-purpose digital I/O / USCI_B0 clock input/output, USCI A0 slave transmit enable P3.4/UCA0TXD/ UCA0SIMO 32 I/O General-purpose digital I/O / USCI_A0 transmit data output in UART mode, slave data in/master out in SPI mode P3.5/UCA0RXD/ UCA0SOMI 33 I/O General-purpose digital I/O / USCI_A0 receive data input in UART mode, slave data out/master in in SPI mode P3.6 34 I/O General-purpose digital I/O P3.7 35 I/O General-purpose digital I/O P4.0/TB0 36 I/O General-purpose digital I/O / Timer_B, capture: CCI0A/B input, compare: Out0 output P4.1/TB1 37 I/O General-purpose digital I/O / Timer_B, capture: CCI1A/B input, compare: Out1 output P4.2/TB2 38 I/O General-purpose digital I/O / Timer_B, capture: CCI2A/B input, compare: Out2 output P4.3 39 I/O General-purpose digital I/O P4.4 40 I/O General-purpose digital I/O P4.5 41 I/O General-purpose digital I/O P4.6 42 I/O General-purpose digital I/O P4.7/TBCLK 43 I/O General-purpose digital I/O / Timer_B, clock signal TBCLK input P5.0 44 I/O General-purpose digital I/O P5.1 45 I/O General-purpose digital I/O P5.2 46 I/O General-purpose digital I/O P5.3 47 I/O General-purpose digital I/O P5.4/MCLK 48 I/O General-purpose digital I/O / main system clock MCLK output P5.5/SMCLK 49 I/O General-purpose digital I/O / submain system clock SMCLK output P5.6/ACLK 50 I/O General-purpose digital I/O / auxiliary clock ACLK output P5.7/TBOUTH/SVSOUT 51 I/O General-purpose digital I/O / switch all PWM digital output ports to high impedance - Timer_B TB0 to TB6/SVS comparator output P6.0/A0 59 I/O General-purpose digital I/O / analog input A0 - 12-bit ADC P6.1/A1 60 I/O General-purpose digital I/O / analog input A1 - 12-bit ADC P6.2/A2 61 I/O General-purpose digital I/O / analog input A2 - 12-bit ADC Digital supply voltage, negative. Supplies all digital parts. Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 9 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Table 2. Terminal Functions, MSP430F23x (continued) TERMINAL NAME NO. I/O DESCRIPTION P6.3/A3 2 I/O General-purpose digital I/O / analog input A3 - 12-bit ADC P6.4/A4 3 I/O General-purpose digital I/O / analog input A4 - 12-bit ADC P6.5/A5 4 I/O General-purpose digital I/O / analog input A5 - 12-bit ADC P6.6/A6 5 I/O General-purpose digital I/O / analog input A6 - 12-bit ADC P6.7/A7/SVSIN 6 I/O General-purpose digital I/O / analog input A7 - 12-bit ADC/SVS input XT2OUT 52 O Output terminal of crystal oscillator XT2 XT2IN 53 I Input port for crystal oscillator XT2 RST/NMI 58 I Reset input, nonmaskable interrupt input, or bootstrap loader start (in flash devices) TCK 57 I Test clock (JTAG). TCK is the clock input port for device programming test and bootstrap loader start. TDI/TCLK 55 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK. TDO/TDI 54 I/O TMS 56 I Test mode select. TMS is used as an input port for device programming and test. VeREF+ 10 I Input for an external reference voltage VREF+ 7 O Output of positive terminal of the reference voltage in the ADC12 VREF-/VeREF- 11 I Negative terminal for the reference voltage for both sources, the internal reference voltage, or an external applied reference voltage XIN 8 I Input for crystal oscillator XT1. Standard or watch crystals can be connected. XOUT 9 O Output for crystal oscillator XT1. Standard or watch crystals can be connected. NA NA QFN Pad 10 Submit Documentation Feedback Test data output. TDO/TDI data output or programming data input terminal. QFN package pad connection to DVSS recommended Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Table 3. Terminal Functions, MSP430F24x, MSP430F2410 TERMINAL NAME NO. I/O DESCRIPTION AVCC 64 Analog supply voltage, positive terminal. Supplies only the analog portion of ADC12. AVSS 62 Analog supply voltage, negative terminal. Supplies only the analog portion of ADC12. DVCC 1 Digital supply voltage, positive terminal. Supplies all digital parts. DVSS 63 P1.0/TACLK/CAOUT 12 I/O General-purpose digital I/O / Timer_A, clock signal TACLK input/Comparator_A output P1.1/TA0 13 I/O General-purpose digital I/O / Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit P1.2/TA1 14 I/O General-purpose digital I/O / Timer_A, capture: CCI1A input, compare: Out1 output P1.3/TA2 15 I/O General-purpose digital I/O / Timer_A, capture: CCI2A input, compare: Out2 output P1.4/SMCLK 16 I/O General-purpose digital I/O / SMCLK signal output P1.5/TA0 17 I/O General-purpose digital I/O / Timer_A, compare: Out0 output P1.6/TA1 18 I/O General-purpose digital I/O / Timer_A, compare: Out1 output P1.7/TA2 19 I/O General-purpose digital I/O / Timer_A, compare: Out2 output P2.0/ACLK/CA2 20 I/O General-purpose digital I/O / ACLK output/Comparator_A input P2.1/TAINCLK/CA3 21 I/O General-purpose digital I/O / Timer_A, clock signal at INCLK P2.2/CAOUT/TA0/CA4 22 I/O General-purpose digital I/O / Timer_A, capture: CCI0B input / Comparator_A output/BSL receive/Comparator_A input P2.3/CA0/TA1 23 I/O General-purpose digital I/O / Timer_A, compare: Out1 output / Comparator_A input P2.4/CA1/TA2 24 I/O General-purpose digital I/O / Timer_A, compare: Out2 output / Comparator_A input P2.5/ROSC/CA5 25 I/O General-purpose digital I/O / Input for external resistor defining the DCO nominal frequency / Comparator_A input P2.6/ADC12CLK/CA6 26 I/O General-purpose digital I/O / Conversion clock - 12-bit ADC / Comparator_A input P2.7/TA0/CA7 27 I/O General-purpose digital I/O / Timer_A, compare: Out0 output / Comparator_A input P3.0/UCB0STE/ UCA0CLK 28 I/O General-purpose digital I/O / USCI_B0 slave transmit enable / USCI A0 clock input/output P3.1/UCB0SIMO/UCB0SDA 29 I/O General-purpose digital I/O / USCI_B0 slave in/master out in SPI mode, SDA I2C data in I2C mode P3.2/UCB0SOMI/ UCB0SCL 30 I/O General-purpose digital I/O / USCI_B0 slave out/master in in SPI mode, SCL I2C clock in I2C mode P3.3/UCB0CLK/UCA0STE 31 I/O General-purpose digital I/O / USCI_B0 clock input/output, USCI A0 slave transmit enable P3.4/UCA0TXD/UCA0SIMO 32 I/O General-purpose digital I/O / USCI_A- transmit data output in UART mode, slave data in/master out in SPI mode P3.5/UCA0RXD/ UCA0SOMI 33 I/O General-purpose digital I/O / USCI_A0 receive data input in UART mode, slave data out/master in in SPI mode P3.6/UCA1TXD/UCA1SIMO 34 I/O General-purpose digital I/O / USCI_A1 transmit data output in UART mode, slave data in/master out in SPI mode P3.7/UCA1RXD/ UCA1SOMI 35 I/O General-purpose digital I/O / USCI_A1 receive data input in UART mode, slave data out/master in in SPI mode P4.0/TB0 36 I/O General-purpose digital I/O / Timer_B, capture: CCI0A/B input, compare: Out0 output P4.1/TB1 37 I/O General-purpose digital I/O / Timer_B, capture: CCI1A/B input, compare: Out1 output P4.2/TB2 38 I/O General-purpose digital I/O / Timer_B, capture: CCI2A/B input, compare: Out2 output P4.3/TB3 39 I/O General-purpose digital I/O / Timer_B, capture: CCI3A/B input, compare: Out3 output P4.4/TB4 40 I/O General-purpose digital I/O / Timer_B, capture: CCI4A/B input, compare: Out4 output P4.5/TB5 41 I/O General-purpose digital I/O / Timer_B, capture: CCI5A/B input, compare: Out5 output P4.6/TB6 42 I/O General-purpose digital I/O / Timer_B, capture: CCI6A input, compare: Out6 output P4.7/TBCLK 43 I/O General-purpose digital I/O / Timer_B, clock signal TBCLK input P5.0/UCB1STE/UCA1CLK 44 I/O General-purpose digital I/O / USCI_B1 slave transmit enable / USCI_A1 clock input/output P5.1/UCB1SIMO/UCB1SDA 45 I/O General-purpose digital I/O / USCI_B1 slave in/master out in SPI mode, SDA I2C data in I2C mode P5.2/UCB1SOMI/UCB1SCL 46 I/O General-purpose digital I/O / USCI_B1 slave out/master in in SPI mode, SCL I2C clock in I2C mode P5.3/UCB1CLK/UCA1STE 47 I/O General-purpose digital I/O / USCI_B1 clock input/output, USCI_A1 slave transmit enable P5.4/MCLK 48 I/O General-purpose digital I/O / main system clock MCLK output P5.5/SMCLK 49 I/O General-purpose digital I/O / submain system clock SMCLK output P5.6/ACLK 50 I/O General-purpose digital I/O / auxiliary clock ACLK output P5.7/TBOUTH/SVSOUT 51 I/O General-purpose digital I/O / switch all PWM digital output ports to high impedance - Timer_B TB0 to TB6/SVS comparator output P6.0/A0 59 I/O General-purpose digital I/O / analog input A0 - 12-bit ADC Digital supply voltage, negative terminal. Supplies all digital parts. Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 11 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Table 3. Terminal Functions, MSP430F24x, MSP430F2410 (continued) TERMINAL NAME NO. I/O DESCRIPTION P6.1/A1 60 I/O General-purpose digital I/O / analog input A1 - 12-bit ADC P6.2/A2 61 I/O General-purpose digital I/O / analog input A2 - 12-bit ADC P6.3/A3 2 I/O General-purpose digital I/O / analog input A3 - 12-bit ADC P6.4/A4 3 I/O General-purpose digital I/O / analog input A4 - 12-bit ADC P6.5/A5 4 I/O General-purpose digital I/O / analog input A5 - 12-bit ADC P6.6/A6 5 I/O General-purpose digital I/O / analog input A6 - 12-bit ADC P6.7/A7/SVSIN 6 I/O General-purpose digital I/O / analog input A7 - 12-bit ADC/SVS input XT2OUT 52 O Output of crystal oscillator XT2 XT2IN 53 I Input for crystal oscillator XT2 RST/NMI 58 I Reset input, nonmaskable interrupt input, or bootstrap loader start (in flash devices) TCK 57 I Test clock (JTAG). TCK is the clock input port for device programming test and bootstrap loader start. TDI/TCLK 55 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK. TDO/TDI 54 I/O TMS 56 I Test mode select. TMS is used as an input port for device programming and test. VeREF+ 10 I Input for an external reference voltage VREF+ 7 O Positive output of the reference voltage in the ADC12 VREF-/VeREF- 11 I Negative input for the reference voltage for both sources, the internal reference voltage, or an external applied reference voltage XIN 8 I Input for crystal oscillator XT1. Standard or watch crystals can be connected. XOUT 9 O Output for crystal oscillator XT1. Standard or watch crystals can be connected. NA NA QFN Pad 12 Submit Documentation Feedback Test data output. TDO/TDI data output or programming data input terminal. QFN package pad connection to DVSS recommended (RGC package only) Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Table 4. Terminal Functions, MSP430F24x1 TERMINAL NAME NO. I/O DESCRIPTION AVCC 64 Analog supply voltage, positive. Supplies only the analog portion of ADC12. AVSS 62 Analog supply voltage, negative. Supplies only the analog portion of ADC12. DVCC 1 Digital supply voltage, positive. Supplies all digital parts. DVSS 63 P1.0/TACLK/CAOUT 12 I/O General-purpose digital I/O / Timer_A, clock signal TACLK input / Comparator_A output P1.1/TA0 13 I/O General-purpose digital I/O / Timer_A, capture: CCI0A input, compare: Out0 output / BSL transmit P1.2/TA1 14 I/O General-purpose digital I/O / Timer_A, capture: CCI1A input, compare: Out1 output P1.3/TA2 15 I/O General-purpose digital I/O / Timer_A, capture: CCI2A input, compare: Out2 output P1.4/SMCLK 16 I/O General-purpose digital I/O / SMCLK signal output P1.5/TA0 17 I/O General-purpose digital I/O / Timer_A, compare: Out0 output P1.6/TA1 18 I/O General-purpose digital I/O / Timer_A, compare: Out1 output P1.7/TA2 19 I/O General-purpose digital I/O / Timer_A, compare: Out2 output P2.0/ACLK/CA2 20 I/O General-purpose digital I/O / ACLK output/Comparator_A input P2.1/TAINCLK/CA3 21 I/O General-purpose digital I/O / Timer_A, clock signal at INCLK P2.2/CAOUT/TA0/CA4 22 I/O General-purpose digital I/O / Timer_A, capture: CCI0B input / Comparator_A output/BSL receive/Comparator_A input P2.3/CA0/TA1 23 I/O General-purpose digital I/O / Timer_A, compare: Out1 output / Comparator_A input P2.4/CA1/TA2 24 I/O General-purpose digital I/O / Timer_A, compare: Out2 output / Comparator_A input P2.5/ROSC/CA5 25 I/O General-purpose digital I/O / input for external resistor defining the DCO nominal frequency / Comparator_A input P2.6/ADC12CLK/CA6 26 I/O General-purpose digital I/O / conversion clock - 12-bit ADC / Comparator_A input P2.7/TA0/CA7 27 I/O General-purpose digital I/O / Timer_A, compare: Out0 output/Comparator_A input P3.0/UCB0STE/ UCA0CLK 28 I/O General-purpose digital I/O / USCI_B0 slave transmit enable/USCI A0 clock input/output P3.1/UCB0SIMO/UCB0SDA 29 I/O General-purpose digital I/O / USCI_B0 slave in/master out in SPI mode, SDA I2C data in I2C mode P3.2/UCB0SOMI/ UCB0SCL 30 I/O General-purpose digital I/O / USCI_B0 slave out/master in in SPI mode, SCL I2C clock in I2C mode P3.3/UCB0CLK/UCA0STE 31 I/O General-purpose digital I/O / USCI_B0 clock input/output, USCI A0 slave transmit enable P3.4/UCA0TXD/UCA0SIMO 32 I/O General-purpose digital I/O / USCI_A0 transmit data output in UART mode, slave data in/master out in SPI mode P3.5/UCA0RXD/ UCA0SOMI 33 I/O General-purpose digital I/O / USCI_A0 receive data input in UART mode, slave data out/master in in SPI mode P3.6/UCA1TXD/UCA1SIMO 34 I/O General-purpose digital I/O / USCI_A1 transmit data output in UART mode, slave data in/master out in SPI mode P3.7/UCA1RXD/ UCA1SOMI 35 I/O General-purpose digital I/O / USCI_A1 receive data input in UART mode, slave data out/master in in SPI mode P4.0/TB0 36 I/O General-purpose digital I/O / Timer_B, capture: CCI0A/B input, compare: Out0 output P4.1/TB1 37 I/O General-purpose digital I/O / Timer_B, capture: CCI1A/B input, compare: Out1 output P4.2/TB2 38 I/O General-purpose digital I/O / Timer_B, capture: CCI2A/B input, compare: Out2 output P4.3/TB3 39 I/O General-purpose digital I/O / Timer_B, capture: CCI3A/B input, compare: Out3 output P4.4/TB4 40 I/O General-purpose digital I/O / Timer_B, capture: CCI4A/B input, compare: Out4 output P4.5/TB5 41 I/O General-purpose digital I/O / Timer_B, capture: CCI5A/B input, compare: Out5 output P4.6/TB6 42 I/O General-purpose digital I/O / Timer_B, capture: CCI6A input, compare: Out6 output P4.7/TBCLK 43 I/O General-purpose digital I/O / Timer_B, clock signal TBCLK input P5.0/UCB1STE/UCA1CLK 44 I/O General-purpose digital I/O / USCI_B1 slave transmit enable/USCI_A1 clock input/output P5.1/UCB1SIMO/UCB1SDA 45 I/O General-purpose digital I/O / USCI_B1 slave in/master out in SPI mode, SDA I2C data in I2C mode P5.2/UCB1SOMI/UCB1SCL 46 I/O General-purpose digital I/O / USCI_B1 slave out/master in in SPI mode, SCL I2C clock in I2C mode P5.3/UCB1CLK/UCA1STE 47 I/O General-purpose digital I/O / USCI_B1 clock input/output, USCI_A1 slave transmit enable P5.4/MCLK 48 I/O General-purpose digital I/O / main system clock MCLK output P5.5/SMCLK 49 I/O General-purpose digital I/O / submain system clock SMCLK output P5.6/ACLK 50 I/O General-purpose digital I/O / auxiliary clock ACLK output P5.7/TBOUTH/SVSOUT 51 I/O General-purpose digital I/O / switch all PWM digital output ports to high impedance - Timer_B TB0 to TB6/SVS comparator output P6.0 59 I/O General-purpose digital I/O Digital supply voltage, negative. Supplies all digital parts. Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 13 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Table 4. Terminal Functions, MSP430F24x1 (continued) TERMINAL NAME NO. I/O DESCRIPTION P6.1 60 I/O General-purpose digital I/O P6.2 61 I/O General-purpose digital I/O P6.3 2 I/O General-purpose digital I/O P6.4 3 I/O General-purpose digital I/O P6.5 4 I/O General-purpose digital I/O P6.6 5 I/O General-purpose digital I/O P6.7/SVSIN 6 I/O General-purpose digital I/O / SVS input XT2OUT 52 O Output terminal of crystal oscillator XT2 XT2IN 53 I Input port for crystal oscillator XT2 RST/NMI 58 I Reset input, nonmaskable interrupt input, or bootstrap loader start (in flash devices). TCK 57 I Test clock (JTAG). TCK is the clock input for device programming test and bootstrap loader start. TDI/TCLK 55 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK. TDO/TDI 54 I/O TMS 56 I Test mode select. TMS is used as an input port for device programming and test. DVSS 10 I Connected to DVSS Reserved 7 O Reserved, do not connect externally DVSS 11 I Connected to DVSS XIN 8 I Input for crystal oscillator XT1. Standard or watch crystals can be connected. XOUT 9 O Output for crystal oscillator XT1. Standard or watch crystals can be connected. NA NA QFN Pad 14 Submit Documentation Feedback Test data output. TDO/TDI data output or programming data input terminal. QFN package pad connection to DVSS recommended (RGC package only) Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 SHORT-FORM DESCRIPTION CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. Program Counter PC/R0 Stack Pointer SP/R1 SR/CG1/R2 Status Register Constant Generator CG2/R3 General-Purpose Register R4 General-Purpose Register R5 General-Purpose Register R6 General-Purpose Register R7 General-Purpose Register R8 General-Purpose Register R9 General-Purpose Register R10 Instruction Set General-Purpose Register R11 The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 5 shows examples of the three types of instruction formats; Table 6 shows the address modes. General-Purpose Register R12 General-Purpose Register R13 General-Purpose Register R14 General-Purpose Register R15 The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. Table 5. Instruction Word Formats EXAMPLE OPERATION Dual operands, source-destination INSTRUCTION FORMAT ADD R4,R5 R4 + R5 → R5 Single operands, destination only CALL R8 PC → (TOS), R8 → PC JNE Jump-on-equal bit = 0 Relative jump, unconditional/conditional Table 6. Address Mode Descriptions ADDRESS MODE D (2) SYNTAX EXAMPLE OPERATION Register ✓ ✓ MOV Rs,Rd MOV R10,R11 R10 → R11 Indexed ✓ ✓ MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) → M(6+R6) Symbolic (PC relative) ✓ ✓ MOV EDE,TONI M(EDE) → M(TONI) Absolute ✓ ✓ MOV &MEM,&TCDAT M(MEM) → M(TCDAT) Indirect ✓ MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) → M(Tab+R6) Indirect autoincrement ✓ MOV @Rn+,Rm MOV @R10+,R11 M(R10) → R11 R10 + 2 → R10 Immediate ✓ MOV #X,TONI MOV #45,TONI #45 → M(TONI) (1) (2) S (1) S = source D = destination Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 15 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Operating Modes The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: • Active mode (AM) – All clocks are active. • Low-power mode 0 (LPM0) – CPU is disabled. – ACLK and SMCLK remain active. MCLK is disabled. • Low-power mode 1 (LPM1) – CPU is disabled ACLK and SMCLK remain active. MCLK is disabled. – DCO dc-generator is disabled if DCO not used in active mode. • Low-power mode 2 (LPM2) – CPU is disabled. – MCLK and SMCLK are disabled. – DCO dc-generator remains enabled. – ACLK remains active. • Low-power mode 3 (LPM3) – CPU is disabled. – MCLK and SMCLK are disabled. – DCO dc-generator is disabled. – ACLK remains active. • Low-power mode 4 (LPM4) – CPU is disabled. – ACLK is disabled. – MCLK and SMCLK are disabled. – DCO dc-generator is disabled. – Crystal oscillator is stopped. 16 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Interrupt Vector Addresses The interrupt vectors and the power-up starting address are located in the address range 0xFFFF to 0xFFC0. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. If the reset vector (0xFFFE) contains 0xFFFF (for example, if flash is not programmed) the CPU enters LPM4 after powerup. Table 7. Interrupt Vector Addresses INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY Power-up External reset Watchdog Flash key violation PC out of range (1) PORIFG WDTIFG RSTIFG KEYV (see (2)) Reset 0xFFFE 31, highest NMI Oscillator fault Flash memory access violation NMIIFG OFIFG ACCVIFG (2) (3) (Non)maskable (Non)maskable (Non)maskable 0xFFFC 30 Timer_B7 (4) TBCCR0 CCIFG (5) Maskable 0xFFFA 29 TBCCR1 to TBCCR6 CCIFGs, TBIFG (2) (5) Maskable 0xFFF8 28 CAIFG Maskable 0xFFF6 27 Watchdog timer+ WDTIFG Maskable 0xFFF4 26 Timer_A3 TACCR0 CCIFG (5) Maskable 0xFFF2 25 Timer_A3 TACCR1 CCIFG TACCR2 CCIFG TAIFG (2) (5) Maskable 0xFFF0 24 USCI_A0/USCI_B0 receive USCI_B0 I2C status UCA0RXIFG, UCB0RXIFG (2) (6) Maskable 0xFFEE 23 USCI_A0/USCI_B0 transmit USCI_B0 I2C receive / transmit UCA0TXIFG, UCB0TXIFG (2) (7) Maskable 0xFFEC 22 Maskable 0xFFEA 21 0xFFE8 20 Timer_B7 (4) Comparator_A+ ADC12 (8) ADC12IFG (2) (5) I/O port P2 (eight flags) P2IFG.0 to P2IFG.7 (2) (5) Maskable 0xFFE6 19 I/O port P1 (eight flags) P1IFG.0 to P1IFG.7 (2) (5) Maskable 0xFFE4 18 (2) (6) Maskable 0xFFE2 17 UCA1TXIFG, UCB1TXIFG (2) (7) Maskable 0xFFE0 16 0xFFDE to 0xFFC0 15 to 0, lowest USCI_A1/USCI_B1 receive USCI_B1 I2C status USCI_A1/USCI_B1 transmit USCI_B1 I2C receive / transmit Reserved (9) (10) UCA1RXIFG, UCB1RXIFG Reserved (1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0x0000 to 0x01FF) or from within unused address range. (2) Multiple source flags (3) (Non)maskable: The individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot. (4) Timer_B7 in MSP430F24x(1)/MSP430F2410 family has seven CCRs, Timer_B3 in MSP430F23x family has three CCRs. In Timer_B3, there are only interrupt flags TBCCR0 CCIFG, TBCCR1 CCIFG, and TBCCR2 CCIFG, and the interrupt enable bits TBCCTL0 CCIE, TBCCTL1 CCIE, and TBCCTL2 CCIE. (5) Interrupt flags are located in the module. (6) In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG. (7) In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG. (8) ADC12 is not implemented in the MSP430F24x1 family. (9) The address 0xFFDE is used as bootstrap loader security key (BSLSKEY). A 0xAA55 at this location disables the BSL completely. A zero disables the erasure of the flash if an invalid password is supplied. (10) The interrupt vectors at addresses 0xFFDE to 0xFFC0 are not used in this device and can be used for regular program code if necessary. Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 17 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Special Function Registers Most interrupt enable bits are collected in the lowest address space. Special-function register bits not allocated to a functional purpose are not physically present in the device. This arrangement provides simple software access. Legend rw rw-0, 1 rw-(0), (1) Bit can be read and written. Bit can be read and written. It is Reset or Set by PUC. Bit can be read and written. It is Reset or Set by POR. SFR bit is not present in device. Table 8. Interrupt Enable 1 Address 7 6 00h WDTIE OFIE NMIIE ACCVIE 5 4 ACCVIE rw-0 3 2 1 0 NMIIE OFIE WDTIE rw-0 rw-0 rw-0 Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval timer mode. Oscillator fault interrupt enable (Non)maskable interrupt enable Flash access violation interrupt enable Table 9. Interrupt Enable 2 Address 7 6 5 4 01h UCA0RXIE UCA0TXIE UCB0RXIE UCB0TXIE 3 2 1 0 UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE rw-0 rw-0 rw-0 rw-0 USCI_A0 receive-interrupt enable USCI_A0 transmit-interrupt enable USCI_B0 receive-interrupt enable USCI_B0 transmit-interrupt enable Table 10. Interrupt Flag Register 1 Address 7 6 5 02h WDTIFG OFIFG RSTIFG PORIFG NMIIFG 4 3 2 1 0 NMIIFG RSTIFG PORIFG OFIFG WDTIFG rw-0 rw-(0) rw-(1) rw-1 rw-(0) Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode. Flag set on oscillator fault External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power up. Power-on reset interrupt flag. Set on VCC power up. Set via RST/NMI pin Table 11. Interrupt Flag Register 2 Address 7 6 03h UCA0RXIFG UCA0TXIFG UCB0RXIFG UCB0TXIFG 18 5 4 3 2 1 0 UCB0TXIFG UCB0RXIFG UCA0TXIFG UCA0RXIFG rw-1 rw-0 rw-1 rw-0 USCI_A0 receive-interrupt flag USCI_A0 transmit-interrupt flag USCI_B0 receive-interrupt flag USCI_B0 transmit-interrupt flag Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Memory Organization Table 12. Memory Organization MSP430F233 MSP430F235 MSP430F249 MSP430F2491 Size Flash Flash 8KB 0xFFFF to 0xFFC0 0xFFFF to 0xE000 16KB 0xFFFF to 0xFFC0 0xFFFF to 0xC000 60KB 0xFFFF to 0xFFC0 0xFFFF to 0x1100 Size 1KB 0x05FF to 0x0200 2KB 0x09FF to 0x0200 2KB 0x09FF to 0x0200 Information memory Size Flash 256 Byte 0x10FF to 0x1000 256 Byte 0x10FF to 0x1000 256 Byte 0x10FF to 0x1000 Boot memory Size ROM 1KB 0x0FFF to 0x0C00 1KB 0x0FFF to 0x0C00 1KB 0x0FFF to 0x0C00 Size 1KB 0x05FF to 0x0200 2KB 0x09FF to 0x0200 2KB 0x09FF to 0x0200 16 bit 8 bit SFR 0x01FF to 0x0100 0x00FF to 0x0010 0x000F to 0x0000 0x01FF to 0x0100 0x00FF to 0x0010 0x000F to 0x0000 0x01FF to 0x0100 0x00FF to 0x0010 0x000F to 0x0000 MSP430F247 MSP430F2471 MSP430F248 MSP430F2481 MSP430F2410 Size Flash Flash 32KB 0xFFFF to 0xFFC0 0xFFFF to 0x8000 48KB 0xFFFF to 0xFFC0 0xFFFF to 0x4000 56KB 0xFFFF to 0xFFC0 0xFFFF to 0x2100 RAM (total) Size 4KB 0x20FF to 0x1100 4KB 0x20FF to 0x1100 4KB 0x20FF to 0x1100 Extended Size 2KB 0x20FF to 0x1900 2KB 0x20FF to 0x1900 2KB 0x20FF to 0x1900 Mirrored Size 2KB 0x18FF to 0x1100 2KB 0x18FF to 0x1100 2KB 0x18FF to 0x1100 Information memory Size Flash 256 Byte 0x10FF to 0x1000 256 Byte 0x10FF to 0x1000 256 Byte 0x10FF to 0x1000 Boot memory Size ROM 1KB 0x0FFF to 0x0C00 1KB 0x0FFF to 0x0C00 1KB 0x0FFF to 0x0C00 Size 2KB 0x09FF to 0x0200 2KB 0x09FF to 0x0200 2KB 0x09FF to 0x0200 16 bit 8 bit SFR 0x01FF to 0x0100 0x00FF to 0x0010 0x000F to 0x0000 0x01FF to 0x0100 0x00FF to 0x0010 0x000F to 0x0000 0x01FF to 0x0100 0x00FF to 0x0010 0x000F to 0x0000 Memory Main: interrupt vector Main: code memory RAM (Total) RAM Peripherals Memory Main: interrupt vector Main: code memory RAM (mirrored at 0x18FF to 0x1100) Peripherals Bootstrap Loader (BSL) The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the MSP430 Programming Via the Bootstrap Loader User’s Guide (SLAU319). Table 13. BSL Function Pins BSL FUNCTION PM, RGC PACKAGE PINS Data transmit 13 - P1.1 Data receive 22 - P2.2 Flash Memory The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: • Flash memory has n segments of main memory and four segments of information memory (A to D) of Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 19 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 • • • 20 www.ti.com 64 bytes each. Each segment in main memory is 512 bytes in size. Segments 0 to n may be erased in one step, or each segment may be individually erased. Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also called information memory. Segment A contains calibration data. After reset, segment A is protected against programming and erasing. It can be unlocked, but care should be taken not to erase this segment if the device-specific calibration data is required. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144). Oscillator and System Clock The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal very-low-power low-frequency oscillator, an internal digitally-controlled oscillator (DCO), and a high-frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic clock module provides the following clock signals: • Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high-frequency crystal, or the internal verylow-power LF oscillator. • Main clock (MCLK), the system clock used by the CPU. • Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules. Calibration Data Stored in Information Memory Segment A Calibration data is stored for the DCO and for the ADC12. It is organized in a tag-length-value (TLV) structure. Table 14. Tags Used by the ADC Calibration Tags NAME ADDRESS VALUE TAG_DCO_30 0x10F6 0x01 DCO frequency calibration at VCC = 3 V andTA = 25°C at calibration TAG_ADC12_1 0x10DA 0x10 ADC12_1 calibration tag - 0xFE Identifier for empty memory areas TAG_EMPTY DESCRIPTION Table 15. Labels Used by the ADC Calibration Tags LABEL CONDITION AT CALIBRATION / DESCRIPTION SIZE ADDRESS OFFSET CAL_ADC_25T85 INCHx = 0x1010, REF2_5 = 1, TA = 85°C word 0x000E CAL_ADC_25T30 INCHx = 0x1010, REF2_5 = 1, TA = 30°C word 0x000C CAL_ADC_25VREF_FACTOR REF2_5 = 1, TA = 30°C, IVREF+ = 1.0 mA word 0x000A CAL_ADC_15T85 INCHx = 0x1010, REF2_5 = 0, TA = 85°C word 0x0008 CAL_ADC_15T30 INCHx = 0x1010, REF2_5 = 0, TA = 30°C word 0x0006 CAL_ADC_15VREF_FACTOR REF2_5 = 0, TA = 30°C, IVREF+ = 0.5 mA word 0x0004 CAL_ADC_OFFSET External Vref = 1.5 V, fADC12CLK = 5 MHz word 0x0002 CAL_ADC_GAIN_FACTOR External Vref = 1.5 V, fADC12CLK = 5 MHz word 0x0000 CAL_BC1_1MHZ - byte 0x0007 CAL_DCO_1MHZ - byte 0x0006 CAL_BC1_8MHZ - byte 0x0005 CAL_DCO_8MHZ - byte 0x0004 CAL_BC1_12MHZ - byte 0x0003 CAL_DCO_12MHZ - byte 0x0002 CAL_BC1_16MHZ - byte 0x0001 CAL_DCO_16MHZ - byte 0x0000 Brownout, Supply Voltage Supervisor (SVS) The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. The SVS circuitry detects if the supply voltage drops below a user-selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset). The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not have ramped to VCC(min) at that time. The user must ensure that the default DCO settings are not changed until VCC reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min). Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 21 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Digital I/O There are up to six 8-bit I/O ports implemented—ports P1 through P6: • All individual I/O bits are independently programmable. • Any combination of input, output, and interrupt condition is possible. • Edge-selectable interrupt input capability for all eight bits of port P1 and P2. • Read/write access to port-control registers is supported by all instructions. • Each I/O has an individually programmable pullup/pulldown resistor. Watchdog Timer (WDT+) The primary function of the WDT+ module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be disabled or configured as an interval timer and can generate interrupts at selected time intervals. Hardware Multiplier The multiplication operation is supported by a dedicated peripheral module. The module performs 16x16, 16x8, 8x16, and 8x8 bit operations. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are required. Timer_A3 Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 16. Timer_A3 Signal Connections INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT NAME 12 - P1.0 TACLK TACLK ACLK ACLK SMCLK SMCLK 21 - P2.1 TAINCLK INCLK 13 - P1.1 TA0 CCI0A 22 - P2.2 TA0 CCI0B 14 - P1.2 15 - P1.3 (1) 22 DVSS GND DVCC VCC TA1 CCI1A CAOUT (internal) CCI1B MODULE BLOCK MODULE OUTPUT SIGNAL Timer NA OUTPUT PIN NUMBER 13 - P1.1 CCR0 TA0 17 - P1.5 27 - P2.7 14 - P1.2 CCR1 TA1 18 - P1.6 DVSS GND DVCC VCC ADC12 (1) (internal) TA2 CCI2A 15 - P1.3 ACLK (internal) CCI2B DVSS GND DVCC VCC CCR2 TA2 23 - P2.3 19 - P1.7 24 - P2.4 Not available in the MSP430F24x1 devices. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Timer_B7 (MSP430F24x(1) and MSP430F2410 Devices) Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 17. Timer_B7 Signal Connections INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT NAME 43 - P4.7 TBCLK TBCLK MODULE OUTPUT SIGNAL Timer NA OUTPUT PIN NUMBER ACLK ACLK SMCLK SMCLK 43 - P4.7 TBCLK INCLK 36 - P4.0 TB0 CCI0A 36 - P4.0 36 - P4.0 TB0 CCI0B ADC12 (1) (internal) DVSS GND CCR0 TB0 DVCC VCC 37 - P4.1 TB1 CCI1A 37 - P4.1 37 - P4.1 TB1 CCI1B ADC12 (2) (internal) DVSS GND 38 - P4.2 38 - P4.2 DVCC VCC TB2 CCI2A TB2 CCI2B DVSS GND DVCC VCC 39 - P4.3 TB3 CCI3A 39 - P4.3 TB3 CCI3B DVSS GND DVCC VCC 40 - P4.4 TB4 CCI4A 40 - P4.4 TB4 CCI4B DVSS GND DVCC VCC 41 - P4.5 TB5 CCI5A 41 - P4.5 TB5 CCI5B DVSS GND 42 - P4.6 (1) (2) MODULE BLOCK DVCC VCC TB6 CCI6A ACLK (internal) CCI6B DVSS GND DVCC VCC CCR1 TB1 38 - P4.2 CCR2 TB2 39 - P4.3 CCR3 TB3 40 - P4.4 CCR4 TB4 41 - P4.5 CCR5 TB5 42 - P4.6 CCR6 TB6 Not available in the MSP430F24x1 devices. Not available in the MSP430F24x1 devices. Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 23 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Timer_B3 (MSP430F23x Devices) Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 18. Timer_B3 Signal Connections INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT NAME 43 - P4.7 TBCLK TBCLK MODULE BLOCK MODULE OUTPUT SIGNAL Timer NA OUTPUT PIN NUMBER ACLK ACLK SMCLK SMCLK 43 - P4.7 TBCLK INCLK 36 - P4.0 TB0 CCI0A 36 - P4.0 36 - P4.0 TB0 CCI0B ADC12 (internal) DVSS GND CCR0 TB0 DVCC VCC 37 - P4.1 TB1 CCI1A 37 - P4.1 37 - P4.1 TB1 CCI1B ADC12 (internal) DVSS GND 38 - P4.2 38 - P4.2 DVCC VCC TB2 CCI2A TB2 CCI2B DVSS GND DVCC VCC CCR1 TB1 38 - P4.2 CCR2 TB2 Universal Serial Communications Interface (USCI) The USCI modules are used for serial data communication. The USCI module supports synchronous communication protocols, such as SPI (3 or 4 pin) or I2C, and asynchronous combination protocols, such as UART, enhanced UART with automatic baudrate detection (LIN), and IrDA. The USCI A module provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA. The USCI B module provides support for SPI (3 or 4 pin) and I2C. Comparator_A+ The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions, battery-voltage supervision, and monitoring of external analog signals. ADC12 (MSP430F23x, MSP430F24x, and MSP430F2410 Devices) The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The conversionand-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention. 24 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Peripheral File Map Table 19. Peripheral File Map MODULE ADC12 (MSP430F24x, MSP430F2410, and MSP430F23x) REGISTER NAME SHORT FORM ADDRESS Interrupt-vector-word register ADC12IV 0x01A8 Interrupt-enable register ADC12IE 0x01A6 Interrupt-flag register ADC12IFG 0x01A4 Control register 1 ADC12CTL1 0x01A2 Control register 0 ADC12CTL0 0x01A0 Conversion memory 15 ADC12MEM15 0x015E Conversion memory 14 ADC12MEM14 0x015C Conversion memory 13 ADC12MEM13 0x015A Conversion memory 12 ADC12MEM12 0x0158 Conversion memory 11 ADC12MEM11 0x0156 Conversion memory 10 ADC12MEM10 0x0154 Conversion memory 9 ADC12MEM9 0x0152 Conversion memory 8 ADC12MEM8 0x0150 Conversion memory 7 ADC12MEM7 0x014E Conversion memory 6 ADC12MEM6 0x014C Conversion memory 5 ADC12MEM5 0x014A Conversion memory 4 ADC12MEM4 0x0148 Conversion memory 3 ADC12MEM3 0x0146 Conversion memory 2 ADC12MEM2 0x0144 Conversion memory 1 ADC12MEM1 0x0142 Conversion memory 0 ADC12MEM0 0x0140 ADC memory-control register15 ADC12MCTL15 0x008F ADC memory-control register14 ADC12MCTL14 0x008E ADC memory-control register13 ADC12MCTL13 0x008D ADC memory-control register12 ADC12MCTL12 0x008C ADC memory-control register11 ADC12MCTL11 0x008B ADC memory-control register10 ADC12MCTL10 0x008A ADC memory-control register9 ADC12MCTL9 0x0089 ADC memory-control register8 ADC12MCTL8 0x0088 ADC memory-control register7 ADC12MCTL7 0x0087 ADC memory-control register6 ADC12MCTL6 0x0086 ADC memory-control register5 ADC12MCTL5 0x0085 ADC memory-control register4 ADC12MCTL4 0x0084 ADC memory-control register3 ADC12MCTL3 0x0083 ADC memory-control register2 ADC12MCTL2 0x0082 ADC memory-control register1 ADC12MCTL1 0x0081 ADC memory-control register0 ADC12MCTL0 0x0080 Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 25 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Table 19. Peripheral File Map (continued) MODULE Timer_B7 (MSP430F24x(1) and MSP430F2410) Timer_B3 (MSP430F23x) Timer_A3 Hardware Multiplier 26 REGISTER NAME SHORT FORM ADDRESS Capture/compare register 6 TBCCR6 0x019E Capture/compare register 5 TBCCR5 0x019C Capture/compare register 4 TBCCR4 0x019A Capture/compare register 3 TBCCR3 0x0198 Capture/compare register 2 TBCCR2 0x0196 Capture/compare register 1 TBCCR1 0x0194 Capture/compare register 0 TBCCR0 0x0192 Timer_B register TBR 0x0190 Capture/compare control 6 TBCCTL6 0x018E Capture/compare control 5 TBCCTL5 0x018C Capture/compare control 4 TBCCTL4 0x018A Capture/compare control 3 TBCCTL3 0x0188 Capture/compare control 2 TBCCTL2 0x0186 Capture/compare control 1 TBCCTL1 0x0184 Capture/compare control 0 TBCCTL0 0x0182 Timer_B control TBCTL 0x0180 Timer_B interrupt vector TBIV 0x011E Capture/compare register 2 TBCCR2 0x0196 Capture/compare register 1 TBCCR1 0x0194 Capture/compare register 0 TBCCR0 0x0192 Timer_B register TBR 0x0190 Capture/compare control 2 TBCCTL2 0x0186 Capture/compare control 1 TBCCTL1 0x0184 Capture/compare control 0 TBCCTL0 0x0182 Timer_B control TBCTL 0x0180 Timer_B interrupt vector TBIV 0x011E Capture/compare register 2 TACCR2 0x0176 Capture/compare register 1 TACCR1 0x0174 Capture/compare register 0 TACCR0 0x0172 Timer_A register TAR 0x0170 Reserved 0x016E Reserved 0x016C Reserved 0x016A Reserved 0x0168 Capture/compare control 2 TACCTL2 0x0166 Capture/compare control 1 TACCTL1 0x0164 Capture/compare control 0 TACCTL0 0x0162 Timer_A control TACTL 0x0160 Timer_A interrupt vector TAIV 0x012E Sum extend SUMEXT 0x013E Result high word RESHI 0x013C Result low word RESLO 0x013A Second operand OP2 0x0138 Multiply signed + accumulate/operand1 MACS 0x0136 Multiply + accumulate/operand1 MAC 0x0134 Multiply signed/operand1 MPYS 0x0132 Multiply unsigned/operand1 MPY 0x0130 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Table 19. Peripheral File Map (continued) MODULE Flash REGISTER NAME SHORT FORM ADDRESS Flash control 4 FCTL4 0x01BE Flash control 3 FCTL3 0x012C Flash control 2 FCTL2 0x012A Flash control 1 FCTL1 0x0128 Watchdog Watchdog Timer control WDTCTL 0x0120 USCI A0/B0 USCI A0 auto baud rate control UCA0ABCTL 0x005D USCI A0 transmit buffer UCA0TXBUF 0x0067 USCI A0 receive buffer UCA0RXBUF 0x0066 USCI A0 status UCA0STAT 0x0065 USCI A0 modulation control UCA0MCTL 0x0064 USCI A0 baud rate control 1 UCA0BR1 0x0063 USCI A0 baud rate control 0 UCA0BR0 0x0062 USCI A0 control 1 UCA0CTL1 0x0061 USCI A0 control 0 UCA0CTL0 0x0060 USCI A0 IrDA receive control UCA0IRRCTL 0x005F USCI A0 IrDA transmit control UCA0IRTCLT 0x005E USCI B0 transmit buffer UCB0TXBUF 0x006F USCI B0 receive buffer UCB0RXBUF 0x006E USCI B0 status UCB0STAT 0x006D USCI B0 I2C Interrupt enable UCB0CIE 0x006C USCI B0 baud rate control 1 UCB0BR1 0x006B USCI B0 baud rate control 0 UCB0BR0 0x006A USCI B0 control 1 UCB0CTL1 0x0069 USCI B0 control 0 UCB0CTL0 0x0068 USCI B0 I2C slave address UCB0SA 0x011A USCI B0 I2C own address UCB0OA 0x0118 Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 27 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Table 19. Peripheral File Map (continued) MODULE USCI A1/B1 (MSP430F24x(1) and MSP430F2410) REGISTER NAME SHORT FORM ADDRESS USCI A1 auto baud rate control UCA1ABCTL 0x00CD USCI A1 transmit buffer UCA1TXBUF 0x00D7 USCI A1 receive buffer UCA1RXBUF 0x00D6 USCI A1 status UCA1STAT 0x00D5 USCI A1 modulation control UCA1MCTL 0x00D4 USCI A1 baud rate control 1 UCA1BR1 0x00D3 USCI A1 baud rate control 0 UCA1BR0 0x00D2 USCI A1 control 1 UCA1CTL1 0x00D1 USCI A1 control 0 UCA1CTL0 0x00D0 USCI A1 IrDA receive control UCA1IRRCTL 0x00CF USCI A1 IrDA transmit control UCA1IRTCLT 0x00CE USCI B1 transmit buffer UCB1TXBUF 0x00DF USCI B1 receive buffer UCB1RXBUF 0x00DE USCI B1 status UCB1STAT 0x00DD USCI B1 I2C Interrupt enable UCB1CIE 0x00DC USCI B1 baud rate control 1 UCB1BR1 0x00DB USCI B1 baud rate control 0 UCB1BR0 0x00DA USCI B1 control 1 UCB1CTL1 0x00D9 USCI B1 control 0 UCB1CTL0 0x00D8 USCI B1 I2C slave address UCB1SA 0x017E USCI B1 I2C own address UCB1OA 0x017C USCI A1/B1 interrupt enable UC1IE 0x0006 USCI A1/B1 interrupt flag UC1IFG 0x0007 Comparator_A port disable CAPD 0x005B Comparator_A control2 CACTL2 0x005A Comparator_A control1 CACTL1 0x0059 Basic clock system control3 BCSCTL3 0x0053 Basic clock system control2 BCSCTL2 0x0058 Basic clock system control1 BCSCTL1 0x0057 DCO clock frequency control DCOCTL 0x0056 Brownout, SVS SVS control register (reset by brownout signal) SVSCTL 0x0055 Port P6 Port P6 resistor enable P6REN 0x0013 Port P6 selection P6SEL 0x0037 Port P6 direction P6DIR 0x0036 Port P6 output P6OUT 0x0035 Port P6 input P6IN 0x0034 Port P5 resistor enable P5REN 0x0012 Port P5 selection P5SEL 0x0033 Port P5 direction P5DIR 0x0032 Port P5 output P5OUT 0x0031 Port P5 input P5IN 0x0030 Port P4 resistor enable P4REN 0x0011 Port P4 selection P4SEL 0x001F Port P4 direction P4DIR 0x001E Port P4 output P4OUT 0x001D Port P4 input P4IN 0x001C Comparator_A+ Basic Clock Port P5 Port P4 28 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Table 19. Peripheral File Map (continued) MODULE Port P3 Port P2 Port P1 Special Functions REGISTER NAME SHORT FORM ADDRESS Port P3 resistor enable P3REN 0x0010 Port P3 selection P3SEL 0x001B Port P3 direction P3DIR 0x001A Port P3 output P3OUT 0x0019 Port P3 input P3IN 0x0018 Port P2 resistor enable P2REN 0x002F Port P2 selection P2SEL 0x002E Port P2 interrupt enable P2IE 0x002D Port P2 interrupt-edge select P2IES 0x002C Port P2 interrupt flag P2IFG 0x002B Port P2 direction P2DIR 0x002A Port P2 output P2OUT 0x0029 Port P2 input P2IN 0x0028 Port P1 resistor enable P1REN 0x0027 Port P1 selection P1SEL 0x0026 Port P1 interrupt enable P1IE 0x0025 Port P1 interrupt-edge select P1IES 0x0024 Port P1 interrupt flag P1IFG 0x0023 Port P1 direction P1DIR 0x0022 Port P1 output P1OUT 0x0021 Port P1 input P1IN 0x0020 SFR interrupt flag2 IFG2 0x0003 SFR interrupt flag1 IFG1 0x0002 SFR interrupt enable2 IE2 0x0001 SFR interrupt enable1 IE1 0x0000 Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 29 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Absolute Maximum Ratings (1) Voltage applied at VCC to VSS Voltage applied to any pin -0.3 V to 4.1 V (2) -0.3 V to VCC + 0.3 V Diode current at any device terminal Storage temperature, Tstg (1) ±2 mA (3) Unprogrammed device -55°C to 150°C Programmed device -55°C to 150°C Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditionsis not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TEST pin when blowing the JTAG fuse. Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. (2) (3) Recommended Operating Conditions (1) (2) Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted) MIN Supply voltage (3) VCC VSS Operating free-air temperature fSYSTEM Processor frequency (maximum MCLK frequency) (1) (2) (see Figure 1) (1) (2) (3) UNIT 3.6 V During program or erase flash memory 2.2 3.6 V I version -40 85 T version -40 105 VCC = 1.8 V, Duty cycle = 50% ± 10% dc 4.15 VCC = 2.7 V, Duty cycle = 50% ± 10% dc 12 VCC ≥ 3.3 V, Duty cycle = 50% ± 10% dc 16 AVSS = DVSS = VSS TA MAX 1.8 AVCC = DVCC = VCC Supply voltage NOM During program execution 0 V °C MHz The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the specified maximum frequency. Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet. It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be tolerated during power-up. Legend : System Frequency −MHz 16 MHz Supply voltage range during flash memory programming 12 MHz Supply voltage range during program execution 7.5 MHz 4.15 MHz 1.8 V 2.2 V 2.7 V 3.3 V 3.6 V Supply Voltage −V NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V. Figure 1. Operating Area 30 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Active Mode Supply Current (Into DVCC and AVCC) Excluding External Current (1) (2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER IAM,1MHz IAM,1MHz IAM,4kHz IAM,100kHz (1) (2) Active mode (AM) current (1 MHz) Active mode (AM) current (1 MHz) Active mode (AM) current (4 kHz) Active mode (AM) current (100 kHz) TEST CONDITIONS TA fDCO = fMCLK = fSMCLK = 1 MHz, fACLK = 32768 Hz, Program executes in flash, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 -40°C to 85°C fDCO = fMCLK = fSMCLK = 1 MHz, fACLK = 32768 Hz, Program executes in RAM, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 -40°C to 85°C fMCLK = fSMCLK = fACLK = 32768 Hz/8 = 4096 Hz, fDCO = 0 Hz, Program executes in flash, SELMx = 11, SELS = 1, DIVMx = DIVSx = DIVAx = 11, CPUOFF = 0, SCG0 = 1, SCG1 = 0, OSCOFF = 0 -40°C to 85°C fMCLK = fSMCLK = fDCO(0, 0) ≈ 100 kHz, fACLK = 0 Hz, Program executes in flash, RSELx = 0, DCOx = 0, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 1 -40°C to 85°C 105°C VCC 2.2 V -40°C to 85°C 105°C 105°C 3V 2.2 V -40°C to 85°C 105°C 105°C 3.3 V 2.2 V -40°C to 85°C 105°C 105°C -40°C to 85°C 105°C 3V 2.2 V 3V MIN TYP MAX 275 312 295 318 386 445 417 449 230 261 248 267 321 366 344 370 1.5 3.8 6 10.5 2 4.7 7 12.2 55 72 70 81 67 89 84 100 UNIT µA µA µA µA All inputs are tied to 0 V or VCC. Outputs do not source or sink any current. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9 pF. Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 31 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Typical Characteristics - Active-Mode Supply Current (Into DVCC and AVCC ) ACTIVE-MODE CURRENT vs SUPPLY VOLTAGE TA = 25°C ACTIVE-MODE CURRENT vs DCO FREQUENCY 5.0 8.0 f DCO = 16 MHz 7.0 TA = 85 °C Active Mode Current − mA Active Mode Current − mA 4.0 6.0 f DCO = 12 MHz 5.0 f DCO = 8 MHz 4.0 3.0 2.0 TA = 25 °C 3.0 VCC = 3 V 2.0 TA = 85 °C TA = 25 °C 1.0 0.0 1.5 2.0 2.5 3.0 VCC − Supply Voltage − V Figure 2. 32 VCC = 2.2 V f DCO = 1 MHz 1.0 Submit Documentation Feedback 3.5 4.0 0.0 0.0 4.0 8.0 12.0 16.0 f DCO − DCO Frequency − MHz Figure 3. Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Low-Power-Mode Supply Currents (Into VCC) Excluding External Current (1) (2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER ILPM0,1MHz ILPM0,100kHz ILPM2 ILPM3,LFXT1 Low-power mode 0 (LPM0) current (3) Low-power mode 0 (LPM0) current (3) Low-power mode 2 (LPM2) current (4) Low-power mode 3 (LPM3) current (4) TEST CONDITIONS TA TYP MAX 60 65 63 72 75 90 80 95 33 38 36 43 36 42 40 47 20 25 25 30 23 30 28 35 -40°C 0.8 1.2 25°C 0.9 1.3 2.4 3 fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz, fACLK = 32768 Hz, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 -40°C to 85°C fMCLK = 0 MHz, fSMCLK = fDCO(0, 0) ≈ 100 kHz, fACLK = 0 Hz, RSELx = 0, DCOx = 0, CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 1 -40°C to 85°C fMCLK = fSMCLK = 0 MHz, fDCO = 1 MHz, fACLK = 32768 Hz, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 -40°C to 85°C fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 105°C 105°C 105°C ILPM3,VLO 105°C 105°C ILPM4 (1) (2) (3) (4) (5) Low-power mode 4 (LPM4) current (5) 2.2 V 3V 2.2 V -40°C to 85°C 105°C 85°C 3V 2.2 V MIN 105°C 6 13 -40°C 0.9 1.3 1 1.4 3.9 4.3 25°C 3V 105°C 10 15 -40°C 0.3 0.9 0.3 0.9 85°C 2.2 V 1.8 2.4 105°C 5.5 13 -40°C 0.4 1 0.4 1 25°C 85°C fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 0 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 3V -40°C to 85°C 25°C fDCO = fMCLK = fSMCLK = 0 MHz, fACLK from internal LF oscillator (VLO), CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 2.2 V -40°C to 85°C 85°C Low-power mode 3 current, (LPM3) (4) VCC 3V 2 3 105°C 9 15 -40°C 0.1 0.5 0.1 0.5 1.6 2.5 6.5 13 25°C 85°C 105°C 2.2 V, 3 V UNIT µA µA µA µA µA µA All inputs are tied to 0 V or VCC . Outputs do not source or sink any current. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9 pF. Current for Brownout and WDT+ is included. The WDT+ is clocked by SMCLK. Current for Brownout and WDT+ is included. The WDT+ is clocked by ACLK. Current for Brownout is included. Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 33 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Typical Characteristics - LPM4 Current LPM4 CURRENT vs TEMPERATURE ILPM4 − Low−power mode current − µA 10.0 9.0 8.0 7.0 6.0 5.0 VCC = 3.6 V 4.0 VCC = 3 V 3.0 Vcc = 2.2V 2.0 1.0 0.0 −40.0 −20.0 0.0 Vcc = 1.8 V 20.0 40.0 60.0 80.0 100.0 120.0 TA − Temperature − °C Figure 4. 34 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Schmitt-Trigger Inputs (Ports P1, P2, P3, P4, P5, P6, RST/NMI, JTAG, XIN, XT2IN) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VIT+ TEST CONDITIONS Positive-going input threshold voltage VCC MIN Negative-going input threshold voltage Vhys Input voltage hysteresis (VIT+ - VIT-) RPull Pullup/pulldown resistor For pullup: VIN = VSS, For pulldown: VIN = VCC CI Input capacitance VIN = VSS or VCC MAX 0.45 VCC 0.75 VCC 1 1.65 1.35 2.25 0.25 VCC 0.55 VCC 2.2 V 0.55 1.20 3V 0.75 1.65 2.2 V 0.2 1 3V 0.3 1 3V 20 2.2 V 3V VIT- TYP 35 50 5 UNIT V V V kΩ pF Inputs (Ports P1, P2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS t(int) External interrupt timing tcap Timer_A Timer_B capture timing fTAext, fTBext Timer_A, Timer_B clock frequency externally applied to pin TACLK, TBCLK, INCLK: t(H) = t(L) fTAint, fTBint Timer_A, Timer_B clock frequency SMCLK or ACLK signal selected (1) VCC Port P1, P2: P1.x to P2.x, External trigger pulse width to set interrupt flag (1) MIN 2.2 V, 3 V 20 2.2 V 62 3V 50 TA0, TA1, TA2 TB0, TB1, TB2, TB3, TB4, TB5, TB6 MAX UNIT ns ns 2.2 V 8 3V 10 2.2 V 8 3V 10 MHz MHz An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set even with trigger signals shorter than t(int) . Leakage Current (Ports P1, P2, P3, P4, P5, P6) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER Ilkg(Px.y) (1) (2) High-impedance leakage current TEST CONDITIONS See VCC (1) (2) MIN 2.2 V, 3 V MAX UNIT ±50 nA The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled. Standard Inputs (RST/NMI) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) VCC MIN MAX VIL Low-level input voltage PARAMETER 2.2 V, 3 V VSS VSS + 0.6 V VIH High-level input voltage 2.2 V, 3 V 0.8 VCC VCC V Copyright © 2007–2012, Texas Instruments Incorporated TEST CONDITIONS Submit Documentation Feedback UNIT 35 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Outputs (Ports P1, P2, P3, P4, P5, P6) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS IOH(max) = -1.5 mA VOH High-level output voltage IOH(max) = -6 mA VCC (1) 2.2 V (2) IOH(max) = -1.5 mA (1) 3V IOH(max) = -6 mA (2) IOL(max) = 1.5 mA VOL Low-level output voltage (2) MAX VCC - 0.25 VCC VCC - 0.6 VCC VCC - 0.25 VCC VCC - 0.6 VCC VSS VSS + 0.25 (1) 2.2 V IOL(max) = 6 mA (2) IOL(max) = 1.5 mA (1) 3V IOL(max) = 6 mA (2) (1) MIN VSS VSS + 0.6 VSS VSS + 0.25 VSS VSS + 0.6 UNIT V V The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to hold the maximum voltage drop specified. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop specified. Output Frequency (Ports P1, P2, P3, P4, P5, P6) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fPx.y Port output frequency with load P1.4/SMCLK, CL = 20 pF, RL = 1 kΩ (1) (2) fPort°CLK Clock output frequency P2.0/ACLK/CA2, P1.4/SMCLK, CL = 20 pF (2) t(Xdc) Duty cycle of output frequency 36 TYP MAX 2.2 V DC 10 3V DC 12 2.2 V DC 12 3V DC 16 30% 50% 70% P1.0/TACLK/CAOUT, CL = 20 pF, XT1 mode 40% 50% 60% P1.1/TA0, CL = 20 pF, XT1 mode P1.1/TA0, CL = 20 pF, DCO P1.4/SMCLK, CL = 20 pF, DCO (2) MIN P1.0/TACLK/CAOUT, CL = 20 pF, LF mode P1.4/SMCLK, CL = 20 pF, XT2 mode (1) VCC 40% 60% 50% – 15 ns 50% 50% + 15 ns 40% 60% 50% – 15 ns 50% + 15 ns UNIT MHz MHz A resistive divider with two 0.5-kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap of the divider. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Typical Characteristics - Outputs One output loaded at a time. TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 50.0 VCC = 2.2 V P4.5 TA = 25°C 20.0 I OL − Typical Low-Level Output Current − mA I OL − Typical Low-Level Output Current − mA 25.0 TA = 85°C 15.0 10.0 5.0 0.0 0.0 0.5 1.0 1.5 2.0 VCC = 3 V P4.5 40.0 TA = 85°C 30.0 20.0 10.0 0.0 0.0 2.5 0.5 1.0 1.5 2.0 2.5 3.0 Figure 5. Figure 6. TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 0.0 0.0 I OH − Typical High-Level Output Current − mA VCC = 2.2 V P4.5 −5.0 −10.0 −15.0 TA = 85°C −20.0 −25.0 0.0 3.5 VOL − Low-Level Output Voltage − V VOL − Low-Level Output Voltage − V I OH − Typical High-Level Output Current − mA TA = 25°C TA = 25°C 0.5 1.0 1.5 2.0 VOH − High-Level Output Voltage − V Figure 7. Copyright © 2007–2012, Texas Instruments Incorporated 2.5 VCC = 3 V P4.5 −10.0 −20.0 −30.0 TA = 85°C −40.0 −50.0 0.0 TA = 25°C 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOH − High-Level Output Voltage − V Figure 8. Submit Documentation Feedback 37 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com POR and Brownout Reset (BOR) (1) (2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VCC(start) Operating voltage dVCC /dt ≤ 3 V/s 0.7 × V(B_IT-) V(B_IT-) Negative going VCC reset threshold voltage dVCC /dt ≤ 3 V/s 1.71 V Vhys(B_IT-) VCC reset threshold hysteresis dVCC /dt ≤ 3 V/s 210 mV td(BOR) BOR reset release delay time 2000 µs t(reset) Pulse duration needed at RST/NMI pin to accepted reset internally (1) (2) 70 2.2 V, 3 V 2 130 V µs The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT-) + Vhys(B_IT-) is ≤ 1.8 V. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT-) + Vhys(B_IT-) . The default DCO settings must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency. VCC Vhys(B_IT−) V(B_IT−) VCC(start) 1 0 t d(BOR) Figure 9. POR/Brownout Reset (BOR) vs Supply Voltage 38 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Typical Characteristics - POR/Brownout Reset (BOR) VCC 3V 2 VCC(drop) − V VCC = 3 V Typical Conditions t pw 1.5 1 VCC(drop) 0.5 0 0.001 1 1000 1 ns t pw − Pulse Width − µs 1 ns t pw − Pulse Width − µs Figure 10. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal VCC 2 t pw 3V VCC(drop) − V VCC = 3 V 1.5 Typical Conditions 1 VCC(drop) 0.5 0 0.001 t f = tr 1 t pw − Pulse Width − µs 1000 tf tr t pw − Pulse Width − µs Figure 11. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 39 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com SVS (Supply Voltage Supervisor and Supply Voltage Monitor) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER t(SVSR) TEST CONDITIONS MIN dVCC/dt > 30 V/ms (see Figure 12) TYP 1 150 dVCC/dt ≤ 30 V/ms td(SVSon) SVSon, switch from VLD = 0 to VLD ≠ 0, VCC = 3 V tsettle VLD ≠ 0 (1) V(SVSstart) VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 12) 2000 150 VLD = 1 VCC/dt ≤ 3 V/s (see Figure 12) Vhys(SVS_IT-) VCC/dt ≤ 3 V/s (see Figure 12), external voltage applied on A7 V(SVS_IT-) VCC/dt ≤ 3V/s (see Figure 12 and Figure 13) VCC/dt ≤ 3 V/s (see Figure 12 and Figure 13), external voltage applied on A7 ICC(SVS) (1) (2) (3) 40 (3) VLD ≠ 0, VCC = 2.2 V, 3 V MAX 70 µs 300 µs 12 µs 1.55 1.7 V 120 155 mV 0.001 × V(SVS_IT-) 0.016 × V(SVS_IT-) VLD = 15 4.4 20 VLD = 1 1.8 1.9 2.05 VLD = 2 1.94 2.1 2.25 VLD = 3 2.05 2.2 2.37 VLD = 4 2.14 2.3 2.48 VLD = 5 2.24 2.4 2.6 VLD = 6 2.33 2.5 2.71 VLD = 7 2.46 2.65 2.86 VLD = 8 2.58 2.8 3 VLD = 9 2.69 2.9 3.13 VLD = 10 2.83 3.05 3.29 VLD = 11 2.94 3.2 3.42 VLD = 12 3.11 3.35 3.61 (2) VLD = 13 3.24 3.5 3.76 (2) VLD = 14 3.43 3.7 (2) 3.99 (2) VLD = 15 1.1 1.2 1.3 10 15 VLD = 2 to 14 UNIT mV V µA tsettle is the settling time that the comparator output needs to have a stable level after VLD is switched from VLD ≠ 0 to a different VLD value somewhere between 2 and 15. The overdrive is assumed to be > 50 mV. The recommended operating voltage range is limited to 3.6 V. The current consumption of the SVS module is not included in the ICC current consumption data. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Software sets VLD >0: SVS is active AVCC V(SVS_IT−) V(SVSstart) Vhys(SVS_IT−) Vhys(B_IT−) V(B_IT−) VCC(start) Brownout Region Brownout Region Brownout 1 0 SVS out t d(BOR) t d(BOR) SVS Circuit is Active From VLD > to V CC < V( B_IT−) 1 0 td(SVSon) Set POR 1 td(SVSR) undefined 0 Figure 12. SVS Reset (SVSR) vs Supply Voltage VCC 3V t pw 2 Rectangular Drop VCC(min) VCC(min) − V 1.5 Triangular Drop 1 1 ns 1 ns VCC 0.5 t pw 3V 0 1 10 100 1000 t pw − Pulse Width − µs VCC(min) t f = tr tf tr t − Pulse Width − µs Figure 13. VCC(min): Square Voltage Drop and Triangle Voltage Drop to Generate an SVS Signal (VLD = 1) Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 41 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Main DCO Characteristics • • • All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15. DCO control bits DCOx have a step size as defined by parameter SDCO . Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to: faverage = 32 × fDCO(RSEL,DCO) × fDCO(RSEL,DCO+1) MOD × fDCO(RSEL,DCO) + (32 – MOD) × fDCO(RSEL,DCO+1) DCO Frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX RSELx < 14 1.8 3.6 RSELx = 14 2.2 3.6 UNIT VCC Supply voltage range 3.0 3.6 fDCO(0,0) DCO frequency (0, 0) RSELx = 0, DCOx = 0, MODx = 0 2.2 V, 3 V 0.06 0.14 MHz fDCO(0,3) DCO frequency (0, 3) RSELx = 0, DCOx = 3, MODx = 0 2.2 V, 3 V 0.07 0.17 MHz fDCO(1,3) DCO frequency (1, 3) RSELx = 1, DCOx = 3, MODx = 0 2.2 V, 3 V 0.10 0.20 MHz fDCO(2,3) DCO frequency (2, 3) RSELx = 2, DCOx = 3, MODx = 0 2.2 V, 3 V 0.14 0.28 MHz fDCO(3,3) DCO frequency (3, 3) RSELx = 3, DCOx = 3, MODx = 0 2.2 V, 3 V 0.20 0.40 MHz fDCO(4,3) DCO frequency (4, 3) RSELx = 4, DCOx = 3, MODx = 0 2.2 V, 3 V 0.28 0.54 MHz fDCO(5,3) DCO frequency (5, 3) RSELx = 5, DCOx = 3, MODx = 0 2.2 V, 3 V 0.39 0.77 MHz fDCO(6,3) DCO frequency (6, 3) RSELx = 6, DCOx = 3, MODx = 0 2.2 V, 3 V 0.54 1.06 MHz fDCO(7,3) DCO frequency (7, 3) RSELx = 7, DCOx = 3, MODx = 0 2.2 V, 3 V 0.80 1.50 MHz fDCO(8,3) DCO frequency (8, 3) RSELx = 8, DCOx = 3, MODx = 0 2.2 V, 3 V 1.10 2.10 MHz fDCO(9,3) DCO frequency (9, 3) RSELx = 9, DCOx = 3, MODx = 0 2.2 V, 3 V 1.60 3.00 MHz fDCO(10,3) DCO frequency (10, 3) RSELx = 10, DCOx = 3, MODx = 0 2.2 V, 3 V 2.50 4.30 MHz fDCO(11,3) DCO frequency (11, 3) RSELx = 11, DCOx = 3, MODx = 0 2.2 V, 3 V 3.00 5.50 MHz fDCO(12,3) DCO frequency (12, 3) RSELx = 12, DCOx = 3, MODx = 0 2.2 V, 3 V 4.30 7.30 MHz fDCO(13,3) DCO frequency (13, 3) RSELx = 13, DCOx = 3, MODx = 0 2.2 V, 3 V 6.00 9.60 MHz fDCO(14,3) DCO frequency (14, 3) RSELx = 14, DCOx = 3, MODx = 0 2.2 V, 3 V 8.60 13.9 MHz fDCO(15,3) DCO frequency (15, 3) RSELx = 15, DCOx = 3, MODx = 0 3V 12.0 18.5 MHz fDCO(15,7) DCO frequency (15, 7) RSELx = 15, DCOx = 7, MODx = 0 3V 16.0 26.0 MHz SRSEL Frequency step between range RSEL and RSEL+1 SRSEL = fDCO(RSEL+1,DCO) /fDCO(RSEL,DCO) 2.2 V, 3 V 1.55 ratio SDCO Frequency step between tap DCO SDCO = fDCO(RSEL,DCO+1) /fDCO(RSEL,DCO) and DCO+1 2.2 V, 3 V 1.05 1.08 1.12 ratio Duty cycle 2.2 V, 3 V 40 50 60 RSELx = 15 42 Submit Documentation Feedback Measured at P1.4/SMCLK V % Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Calibrated DCO Frequencies - Tolerance at Calibration over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS Frequency tolerance at calibration TA VCC MIN TYP MAX UNIT 25°C 3V -1 ±0.2 +1 % 25°C 3V 0.990 1 1.010 MHz fCAL(1MHz) 1-MHz calibration value BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, Gating time: 5 ms fCAL(8MHz) 8-MHz calibration value BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, Gating time: 5 ms 25°C 3V 7.920 8 8.080 MHz fCAL(12MHz) 12-MHz calibration value BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, Gating time: 5 ms 25°C 3V 11.88 12 12.12 MHz fCAL(16MHz) 16-MHz calibration value BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, Gating time: 2 ms 25°C 3V 15.84 16 16.16 MHz MAX UNIT Calibrated DCO Frequencies - Tolerance Over Temperature 0°C to 85°C over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fCAL(1MHz) fCAL(8MHz) fCAL(12MHz) fCAL(16MHz) TA VCC 1-MHz tolerance over temperature 0°C to 85°C 3V -2.5 ±0.5 2.5 % 8-MHz tolerance over temperature 0°C to 85°C 3V -2.5 ±1.0 2.5 % 12-MHz tolerance over temperature 0°C to 85°C 3V -2.5 ±1.0 2.5 % 16-MHz tolerance over temperature 0°C to 85°C 3V -3 ±2.0 3 % 2.2 V 0.97 1 1.03 3V 0.975 1 1.025 3.6 V 0.97 1 1.03 2.2 V 7.76 8 8.4 3V 7.8 8 8.2 3.6 V 7.6 8 8.24 2.2 V 11.64 12 12.36 3V 11.64 12 12.36 3.6 V 11.64 12 12.36 3V 15.52 16 16.48 15 16 16.48 1-MHz calibration value 8-MHz calibration value 12-MHz calibration value 16-MHz calibration value TEST CONDITIONS BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, Gating time: 5 ms 0°C to 85°C BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, Gating time: 5 ms 0°C to 85°C BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, Gating time: 5 ms 0°C to 85°C BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, Gating time: 2 ms 0°C to 85°C Copyright © 2007–2012, Texas Instruments Incorporated 3.6 V MIN TYP Submit Documentation Feedback MHz MHz MHz MHz 43 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Calibrated DCO Frequencies - Tolerance Over Supply Voltage VCC over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX 1-MHz tolerance over VCC 25°C 8-MHz tolerance over VCC 25°C 12-MHz tolerance over VCC 16-MHz tolerance over VCC UNIT 1.8 V to 3.6 V -3 ±2 +3 % 1.8 V to 3.6 V -3 ±2 +3 % 25°C 2.2 V to 3.6 V -3 ±2 +3 % 25°C 3 V to 3.6 V -6 ±2 +3 % fCAL(1MHz) 1-MHz calibration value BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, Gating time: 5 ms 25°C 1.8 V to 3.6 V 0.97 1 1.03 MHz fCAL(8MHz) 8-MHz calibration value BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, Gating time: 5 ms 25°C 1.8 V to 3.6 V 7.76 8 8.24 MHz fCAL(12MHz) 12-MHz calibration value BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, Gating time: 5 ms 25°C 2.2 V to 3.6 V 11.64 12 12.36 MHz fCAL(16MHz) 16-MHz calibration value BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, Gating time: 2 ms 25°C 3 V to 3.6 V 15 16 16.48 MHz MIN TYP MAX UNIT Calibrated DCO Frequencies - Overall Tolerance over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TA VCC 1-MHz tolerance overall -40°C to 105°C 1.8 V to 3.6 V -5 ±2 +5 % 8-MHz tolerance overall -40°C to 105°C 1.8 V to 3.6 V -5 ±2 +5 % 12-MHz tolerance overall -40°C to 105°C 2.2 V to 3.6 V -5 ±2 +5 % 16-MHz tolerance overall -40°C to 105°C 3 V to 3.6 V -6 ±3 +6 % fCAL(1MHz) BCSCTL1 = CALBC1_1MHZ, 1-MHz DCOCTL = CALDCO_1MHZ, calibration value Gating time: 5 ms -40°C to 105°C 1.8 V to 3.6 V 0.95 1 1.05 MHz fCAL(8MHz) BCSCTL1 = CALBC1_8MHZ, 8-MHz DCOCTL = CALDCO_8MHZ, calibration value Gating time: 5 ms -40°C to 105°C 1.8 V to 3.6 V 7.6 8 8.4 MHz fCAL(12MHz) BCSCTL1 = CALBC1_12MHZ, 12-MHz DCOCTL = CALDCO_12MHZ, calibration value Gating time: 5 ms -40°C to 105°C 2.2 V to 3.6 V 11.4 12 12.6 MHz fCAL(16MHz) BCSCTL1 = CALBC1_16MHZ, 16-MHz DCOCTL = CALDCO_16MHZ, calibration value Gating time: 2 ms -40°C to 105°C 3 V to 3.6 V 15 16 17 MHz 44 TEST CONDITIONS Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Typical Characteristics - Calibrated DCO Frequency CALIBRATED 1-MHz FREQUENCY vs SUPPLY VOLTAGE CALIBRATED 8-MHz FREQUENCY vs SUPPLY VOLTAGE 8.20 1.04 8.15 1.03 Frequency − MHz Frequency − MHz 8.10 1.02 TA = −40 °C 1.01 TA = 25 °C TA = −40 °C TA = 85 °C 8.05 8.00 TA = 25 °C 7.95 7.90 1.00 TA = 85 °C 7.85 TA = 105 °C 0.99 1.5 2.0 2.5 3.0 3.5 7.80 1.5 4.0 TA = 105 °C 2.0 Figure 15. CALIBRATED 12-MHz FREQUENCY vs SUPPLY VOLTAGE CALIBRATED 16-MHz FREQUENCY vs SUPPLY VOLTAGE 16.0 TA = −40 °C TA = 25 °C TA = −40 °C Frequency − MHz Frequency − MHz 4.0 16.1 12.3 TA = 25 °C TA = 85 °C TA = 105 °C 11.7 11.5 1.5 3.5 Figure 14. 12.5 11.9 3.0 VCC − Supply Voltage − V VCC − Supply Voltage − V 12.1 2.5 15.9 15.8 TA = 85 °C 15.7 TA = 105 °C 15.6 2.0 2.5 3.0 VCC − Supply Voltage − V Figure 16. Copyright © 2007–2012, Texas Instruments Incorporated 3.5 4.0 15.5 1.5 2.0 2.5 3.0 3.5 4.0 VCC − Supply Voltage − V Figure 17. Submit Documentation Feedback 45 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Wake-Up From Lower-Power Modes (LPM3/4) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ tDCO,LPM3/4 BCSCTL1 = CALBC1_8MHZ, DCO clock wake-up time DCOCTL = CALDCO_8MHZ from LPM3/4 (1) BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ (1) (2) UNIT 2 2.2 V, 3 V 1.5 µs 1 BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ tCPU,LPM3/4 MAX 3V CPU wake-up time from LPM3/4 (2) 1 1 / fMCLK + tClock,LPM3/4 The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, a port interrupt) to the first clock edge observable externally on a clock pin (MCLK or SMCLK). Parameter applicable only if DCOCLK is used for MCLK. Typical Characteristics - DCO Clock Wake-Up Time From LPM3/4 CLOCK WAKE-UP TIME FROM LPM3 vs DCO FREQUENCY DCO Wake Time − µs 10.00 RSELx = 0 to 11 1.00 0.10 0.10 RSELx = 12 to 15 1.00 10.00 DCO Frequency − MHz Figure 18. 46 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 DCO With External Resistor ROSC (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fDCO,ROSC DCO output frequency with ROSC DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0, TA = 25°C DT Temperature drift DV Drift with VCC (1) VCC TYP UNIT 2.2 V 1.8 3V 1.95 DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0 2.2 V, 3 V ±0.1 %/°C DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0 2.2 V, 3 V 10 %/V MHz ROSC = 100 kΩ. Metal film resistor, type 0257, 0.6 W with 1% tolerance and TK = ±50 ppm/°C. Typical Characteristics - DCO With External Resistor ROSC DCO FREQUENCY vs ROSC VCC = 2.2 V, TA = 25°C DCO FREQUENCY vs ROSC VCC = 3 V, TA = 25°C 10.00 DCO Frequency − MHz DCO Frequency − MHz 10.00 1.00 RSELx = 4 0.10 0.01 10.00 100.00 1000.00 1.00 RSELx = 4 0.10 0.01 10.00 10000.00 ROSC − External Resistor − kW 10000.00 ROSC − External Resistor − kW Figure 20. DCO FREQUENCY vs TEMPERATURE VCC = 3 V DCO FREQUENCY vs SUPPLY VOLTAGE TA = 25°C 2.50 2.25 ROSC = 100k 2.00 1.75 1.50 1.25 1.00 ROSC = 270k 0.75 DCO Frequency − MHz 2.25 DCO Frequency − MHz 1000.00 Figure 19. 2.50 ROSC = 100k 2.00 1.75 1.50 1.25 1.00 ROSC = 270k 0.75 0.50 0.50 ROSC = 1M 0.25 0.00 −50.0 −25.0 100.00 0.0 25.0 50.0 75.0 TA − Temperature − C Figure 21. Copyright © 2007–2012, Texas Instruments Incorporated 100.0 ROSC = 1M 0.25 0.00 2.0 2.5 3.0 3.5 4.0 VCC − Supply Voltage − V Figure 22. Submit Documentation Feedback 47 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Crystal Oscillator LFXT1, Low-Frequency Mode (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fLFXT1,LF LFXT1 oscillator crystal frequency, LF mode 0, 1 fLFXT1,LF,logic LFXT1 oscillator logic level square wave input frequency, XTS = 0, LFXT1Sx = 3, XCAPx = 0 LF mode OALF Oscillation allowance for LF crystals Integrated effective load capacitance, LF mode (2) CL,eff fFault,LF (1) (2) (3) (4) XTS = 0, LFXT1Sx = 0 or 1 VCC MIN TYP 1.8 V to 3.6 V 1.8 V to 3.6 V MAX 32768 10000 32768 XTS = 0, LFXT1Sx = 0, fLFXT1,LF = 32768 Hz, CL,eff = 6 pF 500 XTS = 0, LFXT1Sx = 0, fLFXT1,LF = 32768 Hz, CL,eff = 12 pF 200 UNIT Hz 50000 Hz kΩ XTS = 0, XCAPx = 0 1 XTS = 0, XCAPx = 1 5.5 XTS = 0, XCAPx = 2 8.5 XTS = 0, XCAPx = 3 11 Duty cycle, LF mode XTS = 0, Measured at P2.0/ACLK, fLFXT1,LF = 32768 Hz 2.2 V, 3 V 30 Oscillator fault frequency, LF mode (3) XTS = 0, LFXT1Sx = 3, XCAPx = 0 (4) 2.2 V, 3 V 10 50 pF 70 % 10000 Hz To improve EMI on the XT1 oscillator, the following guidelines should be observed. (a) Keep the trace between the device and the crystal as short as possible. (b) Design a good ground plane around the oscillator pins. (c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. (d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. (e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. (f) If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins. (g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter. Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the crystal that is used. Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag. Measured with logic-level input frequency but also applies to operation with crystals. Internal Very-Low-Power Low-Frequency Oscillator (VLO) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC fVLO VLO frequency dfVLO/dT VLO frequency temperature drift dfVLO/dVCC VLO frequency supply voltage drift (1) (2) 48 2.2 V, 3 V (1) 2.2 V, 3 V (2) 1.8 V to 3.6 V MIN TYP MAX 4 12 20 UNIT kHz 0.5 %/°C 4 %/V Calculated using the box method: I version: (MAX(-40 to 85°C) - MIN(-40 to 85°C))/MIN(-40 to 85°C)/(85°C - (-40°C)) T version: (MAX(-40 to 105°C) - MIN(-40 to 105°C))/MIN(-40 to 105°C)/(105°C - (-40°C)) Calculated using the box method: (MAX(1.8 to 3.6 V) - MIN(1.8 to 3.6 V))/MIN(1.8 to 3.6 V)/(3.6 V - 1.8 V) Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Crystal Oscillator LFXT1, High-Frequency Mode (1) PARAMETER VCC MIN XTS = 1, LFXT1Sx = 0, XCAPx = 0 1.8 V to 3.6 V LFXT1 oscillator crystal frequency, HF mode 1 XTS = 1, LFXT1Sx = 1, XCAPx = 0 LFXT1 oscillator crystal frequency, HF mode 2 XTS = 1, LFXT1Sx = 2, XCAPx = 0 fLFXT1,HF0 LFXT1 oscillator crystal frequency, HF mode 0 fLFXT1,HF1 fLFXT1,HF2 TEST CONDITIONS MAX UNIT 0.4 1 MHz 1.8 V to 3.6 V 1 4 MHz 1.8 V to 3.6 V 2 10 2.2 V to 3.6 V 2 12 3 V to 3.6 V fLFXT1,HF,logic OAHF CL,eff LFXT1 oscillator logic-level square-wave input frequency, HF mode Oscillation allowance for HF crystals (see Figure 23 and Figure 24) Integrated effective load capacitance, HF mode (2) (1) (2) (3) (4) (5) Oscillator fault frequency 2 16 1.8 V to 3.6 V 0.4 10 2.2 V to 3.6 V 0.4 12 3 V to 3.6 V 0.4 16 XTS = 1, XCAPx = 0, LFXT1Sx = 0, fLFXT1,HF = 1 MHz, CL,eff = 15 pF 2700 XTS = 1, XCAPx = 0, LFXT1Sx = 1, fLFXT1,HF = 4 MHz, CL,eff = 15 pF 800 XTS = 1, XCAPx = 0, LFXT1Sx = 2, fLFXT1,HF = 16 MHz, CL,eff = 15 pF 300 XTS = 1, XCAPx = 0 (3) XTS = 1, XCAPx = 0, Measured at P1.4/SMCLK, fLFXT1,HF = 10 MHz Duty cycle, HF mode fFault,HF XTS = 1, LFXT1Sx = 3, XCAPx = 0 XTS = 1, XCAPx = 0, Measured at P1.4/SMCLK, fLFXT1,HF = 16 MHz (4) TYP XTS = 1, LFXT1Sx = 3, XCAPx = 0 (5) 50 pF 60 2.2 V, 3 V % 40 2.2 V, 3 V MHz Ω 1 40 MHz 30 50 60 300 kHz To improve EMI on the XT2 oscillator the following guidelines should be observed: (a) Keep the trace between the device and the crystal as short as possible. (b) Design a good ground plane around the oscillator pins. (c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. (d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. (e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. (f) If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins. (g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter. Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal. Requires external capacitors at both terminals. Values are specified by crystal manufacturers. Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and frequencies in between might set the flag. Measured with logic-level input frequency, but also applies to operation with crystals. Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 49 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Typical Characteristics - LFXT1 Oscillator in HF Mode (XTS = 1) OSCILLATION ALLOWANCE vs CRYSTAL FREQUENCY CL,eff = 15 pF, TA = 25°C Oscillation Allowance − W 100000.00 10000.00 1000.00 LFXT1Sx = 2 100.00 LFXT1Sx = 0 10.00 0.10 1.00 LFXT1Sx = 1 10.00 100.00 Crystal Frequency − MHz Figure 23. XT Oscillator Supply Current − µA OSCILLATOR SUPPLY CURRENT vs CRYSTAL FREQUENCY CL,eff = 15 pF, TA = 25°C 1600.0 1500.0 1400.0 1300.0 1200.0 1100.0 1000.0 900.0 800.0 700.0 600.0 500.0 400.0 300.0 200.0 100.0 0.0 0.0 LFXT1Sx = 2 LFXT1Sx = 1 LFXT1Sx = 0 4.0 8.0 12.0 16.0 20.0 Crystal Frequency − MHz Figure 24. 50 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Crystal Oscillator XT2 (1) PARAMETER VCC MIN XT2Sx = 0 1.8 V to 3.6 V XT2 oscillator crystal frequency, mode 1 XT2Sx = 1 XT2 oscillator crystal frequency, mode 2 XT2Sx = 2 fXT2 XT2 oscillator crystal frequency, mode 0 fXT2 fXT2 XT2 oscillator logic-level square-wave XT2Sx = 3 input frequency fXT2 Oscillation allowance (see Figure 25 and Figure 26) OA CL,eff Integrated effective load capacitance, HF mode (2) Duty cycle fFault (1) (2) (3) (4) (5) TEST CONDITIONS TYP MAX UNIT 0.4 1 MHz 1.8 V to 3.6 V 1 4 MHz 1.8 V to 2.2 V 2 10 2.2 V to 3.0 V 2 12 3.0 V to 3.6 V 2 16 1.8 V to 2.2 V 0.4 10 2.2 V to 3.0 V 0.4 12 3.0 V to 3.6 V 0.4 16 XT2Sx = 0, fXT2 = 1 MHz, CL,eff = 15 pF 2700 XT2Sx = 1, fXT2 = 4 MHz, CL,eff = 15 pF 800 XT2Sx = 2, fXT2 = 16 MHz, CL,eff = 15 pF 300 See (3) Measured at P1.4/SMCLK, fXT2 = 10 MHz Measured at P1.4/SMCLK, fXT2 = 16 MHz Oscillator fault frequency, HF mode (4) XT2Sx = 3 (5) MHz Ω 1 pF 40 50 60 40 50 60 2.2 V, 3 V 2.2 V, 3 V MHz % 30 300 kHz To improve EMI on the XT2 oscillator the following guidelines should be observed: (a) Keep the trace between the device and the crystal as short as possible. (b) Design a good ground plane around the oscillator pins. (c) Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT. (d) Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins. (e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XT2IN and XT2OUT pins. (f) If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins. Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal. Requires external capacitors at both terminals. Values are specified by crystal manufacturers. Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and frequencies in between might set the flag. Measured with logic-level input frequency, but also applies to operation with crystals. Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 51 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Typical Characteristics - XT2 Oscillator OSCILLATION ALLOWANCE vs CRYSTAL FREQUENCY CL,eff = 15 pF, TA = 25°C Oscillation Allowance − W 100000.00 10000.00 1000.00 XT2Sx = 2 100.00 XT2Sx = 1 XT2Sx = 0 10.00 0.10 1.00 10.00 100.00 Crystal Frequency − MHz Figure 25. XT Oscillator Supply Current − µA OSCILLATOR SUPPLY CURRENT vs CRYSTAL FREQUENCY CL,eff = 15 pF, TA = 25°C 1600.0 1500.0 1400.0 1300.0 1200.0 1100.0 1000.0 900.0 800.0 700.0 600.0 500.0 400.0 300.0 200.0 100.0 0.0 0.0 XT2Sx = 2 XT2Sx = 1 XT2Sx = 0 4.0 8.0 12.0 16.0 20.0 Crystal Frequency − MHz Figure 26. 52 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Timer_A over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fTA Timer_A clock frequency Internal: SMCLK, ACLK External: TACLK, INCLK Duty cycle = 50% ± 10% tTA,cap Timer_A capture timing TA0, TA1, TA2 VCC MIN TYP MAX 2.2 V 10 3V 16 2.2 V, 3 V 20 UNIT MHz ns Timer_B over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fTB Timer_B clock frequency Internal: SMCLK, ACLK External: TACLK, INCLK Duty cycle = 50% ± 10% tTB,cap Timer_B capture timing TB0, TB1, TB2 Copyright © 2007–2012, Texas Instruments Incorporated VCC MIN TYP MAX 2.2 V 10 3V 16 2.2 V, 3 V 20 Submit Documentation Feedback UNIT MHz ns 53 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com USCI (UART Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fUSCI USCI input clock frequency fBITCLK BITCLK clock frequency (equals baud rate in MBaud) (1) tτ UART receive deglitch time (2) (1) (2) CONDITIONS VCC MIN TYP Internal: SMCLK, ACLK External: UCLK Duty cycle = 50% ± 10% 2.2 V, 3 V 2.2 V 50 150 3V 50 100 MAX UNIT fSYSTEM MHz 1 MHz ns The DCO wake-up time must be considered in LPM3/4 for baudrates above 1 MHz. Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. USCI (SPI Master Mode) (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 27 and Figure 28) PARAMETER fUSCI USCI input clock frequency tSU,MI SOMI input data setup time tHD,MI SOMI input data hold time tVALID,MO SIMO output data valid time (1) TEST CONDITIONS VCC MIN TYP SMCLK, ACLK Duty cycle = 50% ± 10% UCLK edge to SIMO valid, CL = 20 pF 2.2 V 110 3V 75 2.2 V 0 3V 0 MAX UNIT fSYSTEM MHz ns ns 2.2 V 30 3V 20 ns fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)). For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave. USCI (SPI Slave Mode) (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 29 and Figure 30) PARAMETER TEST CONDITIONS VCC MIN TYP MAX tSTE,LEAD STE lead time, STE low to clock 2.2 V, 3 V tSTE,LAG STE lag time, Last clock to STE high 2.2 V, 3 V tSTE,ACC STE access time, STE low to SOMI data out 2.2 V, 3 V 50 ns tSTE,DIS STE disable time, STE high to SOMI high impedance 2.2 V, 3 V 50 ns tSU,SI SIMO input data setup time tHD,SI SIMO input data hold time tVALID,SO SOMI output data valid time (1) 54 UCLK edge to SOMI valid, CL = 20 pF 50 UNIT ns 10 2.2 V 20 3V 15 2.2 V 10 3V 10 ns ns ns 2.2 V 75 110 3V 50 75 ns fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)). For the master's parameters tSU,MI(Master) and tVALID,MO(Master) see the SPI parameters of the attached slave. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tVALID,MO SIMO Figure 27. SPI Master Mode, CKPH = 0 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tVALID,MO SIMO Figure 28. SPI Master Mode, CKPH = 1 Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 55 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU,SI tHD,SI SIMO tSTE,ACC tVALID,SO tSTE,DIS SOMI Figure 29. SPI Slave Mode, CKPH = 0 tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tHD,SI tSU,SI SIMO tSTE,ACC tVALID,SO tSTE,DIS SOMI Figure 30. SPI Slave Mode, CKPH = 1 56 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 USCI (I2C Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 31) PARAMETER TEST CONDITIONS VCC MIN TYP Internal: SMCLK, ACLK External: UCLK Duty cycle = 50% ± 10% MAX UNIT fSYSTEM MHz 400 kHz fUSCI USCI input clock frequency fSCL SCL clock frequency tHD,STA Hold time (repeated) START tSU,STA Setup time for a repeated START tHD,DAT Data hold time 2.2 V, 3 V 0 tSU,DAT Data setup time 2.2 V, 3 V 250 ns tSU,STO Setup time for STOP 2.2 V, 3 V 4 µs tSP Pulse width of spikes suppressed by input filter 2.2 V 50 150 600 3V 50 100 600 2.2 V, 3 V fSCL ≤ 100 kHz fSCL > 100 kHz fSCL ≤ 100 kHz fSCL > 100 kHz tHD,STA 2.2 V, 3 V 2.2 V, 3 V 0 4 µs 0.6 4.7 µs 0.6 ns ns tSU,STA tHD,STA SDA 1/fSCL tSP SCL tSU,DAT tSU,STO tHD,DAT Figure 31. I2C Mode Timing Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 57 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Comparator_A+ (1) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS I(DD) CAON = 1, CARSEL = 0, CAREF = 0 I(Refladder/RefDiode) CAON = 1, CARSEL = 0, CAREF = 1/2/3, No load at P2.3/CA0/TA1 and P2.4/CA1/TA2 VCC MIN TYP MAX 2.2 V 25 40 3V 45 60 2.2 V 30 50 3V 45 71 UNIT µA µA VIC Common-mode input voltage range CAON = 1 2.2 V, 3 V 0 V(Ref025) Voltage at 0.25 VCC node / VCC PCA0 = 1, CARSEL = 1, CAREF = 1, No load at P2.3/CA0/TA1 and P2.4/CA1/TA2 2.2 V, 3 V 0.23 0.24 0.25 V(Ref050) Voltage at 0.5 VCC node / PCA0 = 1, CARSEL = 1, CAREF = 2, VCC No load at P2.3/CA0/TA1 and P2.4/CA1/TA2 2.2 V, 3 V 0.47 0.48 0.5 See Figure 36 and Figure 37 2.2 V 390 480 540 V(RefVT) 3V 400 490 550 V(offset) Offset voltage (2) 2.2 V, 3 V -30 30 mV Vhys Input hysteresis 2.2 V, 3 V 0 0.7 1.4 mV TA = 25°C, Overdrive 10 mV, Without filter: CAF = 0 (3) (see Figure 32 and Figure 33) 2.2 V 80 165 300 3V 70 120 240 TA = 25°C, Overdrive 10 mV, Without filter: CAF = 1 (3) (see Figure 32 and Figure 33) 2.2 V 1.4 1.9 2.8 3V 0.9 1.5 2.2 t(response) (1) (2) (3) 58 Response time (low-to-high and high-tolow) PCA0 = 1, CARSEL = 1, CAREF = 3, No load at P2.3/CA0/TA1 and P2.4/CA1/TA2, TA = 85°C CAON = 1 VCC - 1 V mV ns µs The leakage current for the Comparator_A+ terminals is identical to Ilkg(Px.y) specification. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements. The two successive measurements are then summed together. The response time is measured at P2.2/CAOUT/TA0/CA4 with an input voltage step, with Comparator_A+ already enabled (CAON = 1). If CAON is set at the same time, a settling time of up to 300 ns is added to the response time. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 0V VCC 0 1 CAF CAON To Internal Modules Low Pass Filter + _ V+ V− 0 0 1 1 CAOUT Set CAIFG Flag τ ≈ 2.0 µs Figure 32. Comparator_A+ Block Diagram VCAOUT Overdrive V− 400 mV t (response) V+ Figure 33. Comparator_A+ Overdrive Definition Figure 34. Comparator_A+ Short Resistance Test Condition CASHORT CA0 CA1 1 VIN + − Comparator_A+ CASHORT = 1 IOUT = 10µA Figure 35. Comparator_A+ Short Resistance Test Condition Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 59 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Typical Characteristics, Comparator_A+ V(RefVT) vs TEMPERATURE (VCC = 3 V) 650 V(RefVT) vs TEMPERATURE (VCC = 2.2 V) 650 VCC = 2.2 V 600 V(REFVT) − Reference Volts −mV V(REFVT) − Reference Volts −mV VCC = 3 V Typical 550 500 450 400 −45 −25 −5 15 35 55 75 600 Typical 550 500 450 400 −45 95 −25 TA − Free-Air Temperature − °C −5 15 35 55 75 95 TA − Free-Air Temperature − °C Figure 1. V(RefVT) vs Temperature, V CC = 3 V Figure 36. Figure 37. SHORT RESISTANCE vs VIN/VCC Short Resistance − kW 100.00 VCC = 1.8 V VCC = 2.2V 10.00 VCC = 3 V VCC = 3.6 V 1.00 0.0 0.2 0.4 0.6 0.8 1.0 VIN/VCC − Normalized Input Voltage − V/V Figure 38. 60 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 12-bit ADC, Power Supply and Input Range Conditions (1) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC AVCC Analog supply voltage AVCC and DVCC are connected together AVSS and DVSS are connected together V(AVSS) = V(DVSS) = 0 V V(P6.x/Ax) Analog input voltage range (2) All P6.0/A0 to P6.7/A7 terminals, Analog inputs selected in ADC12MCTLx register, P6Sel.x = 1, 0 ≤ × ≤ 7, V(AVSS) ≤ VP6.x/Ax ≤ V(AVCC) IADC12 Operating supply current into AVCC terminal (3) fADC12CLK = 5 MHz, ADC12ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC12DIV = 0 IREF+ Operating supply current into AVCC terminal (4) CI Input capacitance (5) Only one terminal can be selected at one time, P6.x/Ax RI Input MUX ON resistance (5) 0 V ≤ VAx ≤ VAVCC (1) (2) (3) (4) (5) TYP MAX UNIT 2.2 3.6 V 0 VAVCC V 2.2 V 0.65 0.8 3V 0.8 1 3V 0.5 0.7 2.2 V 0.5 0.7 3V 0.5 0.7 fADC12CLK = 5 MHz, ADC12ON = 0, REFON = 1, REF2_5V = 1 fADC12CLK = 5 MHz, ADC12ON = 0, REFON = 1, REF2_5V = 0 MIN 2.2 V 3V mA mA mA 40 pF 2000 Ω The leakage current is defined in the leakage current table with P6.x/Ax parameter. The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. The internal reference supply current is not included in current consumption parameter IADC12. The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a conversion is active. The REFON bit enables settling of the built-in reference before starting an A/D conversion. Not production tested, limits verified by design. 12-Bit ADC, External Reference (1) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VeREF+ Positive external reference voltage input VeREF+ > VREF–/VeREF– (2) VREF–/VeREF– Negative external reference voltage input VeREF+ > VREF–/VeREF– (3) (4) VCC MIN MAX 1.4 VAVCC 0 UNIT V 1.2 V 1.4 VAVCC V (VeREF+ – VREF–/VeREF–) Differential external reference voltage input VeREF+ > VREF–/VeREF– IVeREF+ Static leakage current 0 V ≤ VeREF+ ≤ VAVCC 2.2 V, 3 V ±1 µA IVREF–/VeREF– Static leakage current 0 V ≤ VeREF– ≤ VAVCC 2.2 V, 3 V ±1 µA (1) (2) (3) (4) The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements. Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 61 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com 12-Bit ADC, Built-In Reference over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS Positive built-in reference voltage output VREF+ AVCC(min) AVCC minimum voltage, positive built-in reference active TA REF2_5V = 1 for 2.5 V, IVREF+max ≤ IVREF+ ≤ IVREF+min -40°C to 85°C REF2_5V = 0 for 1.5 V, IVREF+max ≤ IVREF+ ≤ IVREF+min -40°C to 85°C 105°C 105°C Load-current regulation, VREF+ terminal (1) IL(VREF)+ 3V 2.2 V, 3 V 2.4 2.5 2.6 2.5 2.64 1.44 1.5 1.56 1.42 1.5 1.57 2.8 REF2_5V = 1, -1 mA ≤ IVREF+ ≤ IVREF+min 2.9 IVREF+ = 500 µA ± 100 µA, Analog input voltage ≈ 0.75 V, REF2_5V = 0 MAX 2.37 REF2_5V = 1, -0.5 mA ≤ IVREF+ ≤ IVREF+min UNIT V V 2.2 V 0.01 -0.5 3V 0.01 -1 mA 2.2 V ±2 3V ±2 IVREF+ = 500 µA ± 100 µA, Analog input voltage ≈ 1.25 V, REF2_5V = 1 3V ±2 LSB 3V 20 ns Load current regulation, VREF+ terminal (2) IVREF+ = 100 µA → 900 µA, CVREF+ = 5 µF, ax ≈ 0.5 × VREF+, Error of conversion result ≤ 1 LSB CVREF+ Capacitance at pin VREF+ (3) REFON = 1, 0 mA ≤ IVREF+ ≤ IVREF+max 2.2 V, 3 V TREF+ Temperature coefficient of built-in reference (2) IVREF+ is a constant in the range of 0 mA ≤ IVREF+ ≤ 1 mA 2.2 V, 3 V tREFON Settle time of internal reference voltage (see Figure 39 ) (4) (2) IVREF+ = 0.5 mA, CVREF+ = 10 µF, VREF+ = 1.5 V, VAVCC = 2.2 V 2.2 V (4) NOM 2.2 IDL(VREF) + (1) (2) (3) MIN REF2_5V = 0, IVREF+max ≤ IVREF+ ≤ IVREF+min Load current out of VREF+ terminal IVREF+ VCC 5 10 LSB µF ±100 17 ppm/°C ms Not production tested, limits characterized. Not production tested, limits verified by design. The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses two capacitors between pins VREF+ and AVSS and VREF-–/VeREF– and AVSS: 10 µF tantalum and 100 nF ceramic. The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external capacitive load. CVREF+ 100 µF t REFON ≈ .66 x CVREF+ [ms] with C VREF+ in µF 10 µF 1 µF 0 1 ms 10 ms 100 ms t REFON Figure 39. Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF+ 62 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 From Power Supply DVCC + − DVSS 10 µ F 100 nF AVCC + − AVSS Apply External Reference [VeREF+] or Use Internal Reference [VREF+] 10 µ F 100 nF VREF+ or V eREF+ + − 10 µ F 100 nF Apply External Reference VREF−/VeREF− + − 10 µ F 100 nF Figure 40. Supply Voltage and Reference Voltage Design VREF–/VeREF– External Supply DVCC From Power Supply + − DVSS 10 µ F 100 nF AVCC + − AVSS 10 µ F Apply External Reference [VeREF+] or Use Internal Reference [VREF+] VREF+ or V eREF+ + − 10 µ F Reference Is Internally Switched to AVSS 100 nF 100 nF VREF−/VeREF− Figure 41. Supply Voltage and Reference Voltage Design VREF–/VeREF– = AVSS, Internally Connected Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 63 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com 12-Bit ADC, Timing Parameters over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS fADC12CLK fADC12OSC tCONVERT Internal ADC12 oscillator Conversion time VCC MIN For specified performance of ADC12 linearity parameters 2.2 V, 3 V 0.45 5 6.3 MHz ADC12DIV = 0, fADC12CLK = fADC12OSC 2.2 V, 3 V 3.7 5 6.3 MHz CVREF+ ≥ 5 µF, Internal oscillator, fADC12OSC = 3.7 MHz to 6.3 MHz 2.2 V, 3 V 2.06 External fADC12CLK from ACLK, MCLK, or SMCLK, ADC12SSEL ≉ 0 tADC12ON Turn-on settling time of the ADC (1) See tSample Sampling time (1) RS = 400 Ω,RI = 1000 Ω, CI = 30 pF, τ = [RS +RI] × CI (3) (1) (2) (3) NOM MAX UNIT 3.51 13 × ADC12DIV × 1/fADC12CLK (2) µs 100 3V 1220 2.2 V 1400 µs ns ns Limits verified by design The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signal are already settled. Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB: tSample = ln(2n+1) × (RS + RI) × CI + 800 ns, where n = ADC resolution = 12, RS = external source resistance 12-Bit ADC, Linearity Parameters over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS 1.4 V ≤ (VeREF+ – VREF–/VeREF–) min ≤ 1.6 V VCC EI Integral linearity error ED Differential linearity (VeREF+ – VREF–/VeREF–) min ≤ (VeREF+ – VREF–/VeREF–), error CVREF+ = 10 µF (tantalum) and 100 nF (ceramic) 2.2 V, 3 V EO Offset error (VeREF+ – VREF–/VeREF–) min ≤ (VeREF+ – VREF–/VeREF–), Internal impedance of source RS < 100 Ω, CVREF+ = 10 µF (tantalum) and 100 nF (ceramic) 2.2 V, 3 V EG Gain error (VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–), CVREF+ = 10 µF (tantalum) and 100 nF (ceramic) ET Total unadjusted error (VeREF+ -– VREF–/VeREF– )min ≤ (VeREF+ –VREF–/VeREF–), CVREF+ = 10 µF (tantalum) and 100 nF (ceramic) 64 1.6 V < (VeREF+ – VREF–/VeREF–) min ≤ VAVCC Submit Documentation Feedback MIN NOM MAX ±2 2.2 V, 3 V ±1.7 UNIT LSB ±1 LSB ±2 ±4 LSB 2.2 V, 3 V ±1.1 ±2 LSB 2.2 V, 3 V ±2 ±5 LSB Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 12-Bit ADC, Temperature Sensor and Built-In VMID over recommended operating free-air temperature range (unless otherwise noted) PARAMETER ISENSOR Operating supply current into AVCC terminal (1) TEST CONDITIONS REFON = 0, INCH = 0Ah, ADC12ON = 1, TA = 25°C VSENSOR (2) (3) ADC12ON = 1, INCH = 0Ah, TA = 0°C TCSENSOR (3) ADC12ON = 1, INCH = 0Ah VCC MIN TYP MAX 2.2 V 40 120 3V 60 160 2.2 V 986 3V 986 2.2 V 3.55 3.55 ± 3% 3V 3.55 3.55 ± 3% Sample time required if channel 10 is selected (4) IVMID Current into divider ADC12ON = 1, INCH = 0Bh at channel 11 (5) 2.2 V NA 3V NA VMID AVCC divider at channel 11 ADC12ON = 1, INCH = 0Bh, VMID is ~0.5 × VAVCC 2.2 V 1.1 1.1 ± 0.04 3V 1.5 1.5 ± 0.04 tVMID(sample) Sample time required if channel 11 is selected (6) ADC12ON = 1, INCH = 0Bh, Error of conversion result ≤ 1 LSB (1) (2) (3) (4) (5) (6) 2.2 V 30 3V 30 2.2 V 1400 3V 1220 µA mV tSENSOR(sample) (3) ADC12ON = 1, INCH = 0Ah, Error of conversion result ≤ 1 LSB UNIT mV/°C µs µA V ns The sensor current ISENSOR is consumed if (ADC12ON = 1 and REFON = 1), or (ADC12ON = 1 AND INCH = 0Ah and sample signal is high). Therefore it includes the constant current through the sensor and the reference. The temperature sensor offset can be as much as ±20°C. A single-point calibration is recommended to minimize the offset error of the built-in temperature sensor. Limits characterized The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on) No additional current is needed. The VMID is used during sampling. The on-time tVMID(on) is included in the sampling time tVMID(sample), no additional on time is needed. Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 65 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Flash Memory over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VCC (PGM/ERASE) Program and erase supply voltage 2.2 3.6 V fFTG Flash timing generator frequency 257 476 kHz IPGM Supply current from VCC during program 2.2 V/3.6 V 1 5 mA IERASE Supply current from VCC during erase 2.2 V/3.6 V 1 7 mA 10 ms (1) tCPT Cumulative program time tCMErase Cumulative mass erase time 2.2 V/3.6 V 2.2 V/3.6 V 20 ms 104 Program/Erase endurance 105 cycles tRetention Data retention duration TJ = 25°C tWord Word or byte program time (2) 30 tFTG tBlock, Block program time for first byte or word (2) 25 tFTG Block program time for each additional byte or word (2) 18 tFTG Block program end-sequence wait time (2) 6 tFTG Mass erase time (2) 10593 tFTG Segment erase time (2) 4819 tFTG 0 tBlock, 1-63 tBlock, End tMass Erase tSeg Erase (1) (2) 100 years The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming methods: individual word/byte write and block write modes. These values are hardwired into the flash controller's state machine (tFTG = 1/fFTG). RAM over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER V(RAMh) (1) RAM retention supply voltage TEST CONDITIONS (1) MIN CPU halted MAX UNIT 1.6 V This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should happen during this supply voltage condition. JTAG Interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fTCK TCK input frequency See (1) RInternal Internal pulldown resistance on TEST See (2) (1) (2) VCC MIN TYP MAX 2.2 V 0 5 3V 0 10 2.2 V, 3 V 25 60 90 MIN MAX UNIT MHz kΩ fTCK may be restricted to meet the timing requirements of the module selected. TMS, TDI/TCLK, and TCK pullup resistors are implemented in all versions. JTAG Fuse (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC(FB) Supply voltage during fuse-blow condition VFB Voltage level on TEST for fuse blow IFB Supply current into TEST during fuse blow tFB Time to blow fuse (1) 66 TEST CONDITIONS TA = 25°C 2.5 6 UNIT V 7 V 100 mA 1 ms Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to bypass mode. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 APPLICATION INFORMATION Port P1 Pin Schematic: P1.0 to P1.7, Input/Output With Schmitt Trigger P1REN.x P1DIR.x Pad Logic 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P1OUT.x DVSS P1.0/TACLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK P1.5/TA0 P1.6/TA1 P1.7/TA2 P1SEL.x P1IN.x EN Module X IN D P1IE.x P1IRQ.x EN Q Set P1IFG.x P1SEL.x P1IES.x Interrupt Edge Select Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 67 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Table 20. Port P1.0 to P1.7 Pin Functions PIN NAME (P1.x) x FUNCTION P1.0 (I/O) P1.0/TACLK 0 1 2 0 0 1 CAOUT 1 1 I: 0; O: 1 0 Timer_A3.CCI0A 0 1 Timer_A3.TA0 1 1 I: 0; O: 1 0 Timer_A3.CCI1A 0 1 Timer_A3.TA1 1 1 I: 0; O: 1 0 Timer_A3.CCI2A 0 1 Timer_A3.TA2 1 1 I: 0; O: 1 0 1 1 I: 0; O: 1 0 1 1 I: 0; O: 1 0 P1.3 (I/O) P1.3/TA2 3 P1.4/SMCLK 4 P1.5/TA0 5 P1.6/TA1 P1.7/TA2 68 6 7 P1SEL.x I: 0; O: 1 P1.2 (I/O) P1.2/TA1 P1DIR.x Timer_A3.TACLK P1.1 (I/O) P1.1/TA0 CONTROL BITS / SIGNALS P1.4 (I/O) SMCLK P1.5 (I/O) Timer_A3.TA0 P1.6 (I/O) Timer_A3.TA1 P1.7 (I/O) Timer_A3.TA2 Submit Documentation Feedback 1 1 I: 0; O: 1 0 1 1 Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Port P2 Pin Schematic: P2.0 to P2.4, P2.6, and P2.7, Input/Output With Schmitt Trigger Pad Logic To Comparator_A From Comparator_A CAPD.x P2REN.x P2DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.x DVSS Bus Keeper EN P2SEL.x P2IN.x EN Module X IN P2.0/ACLK/CA2 P2.1/TAINCLK/CA3 P2.2/CAOUT/TA0/CA4 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.6/ADC12CLK/CA6 P2.7/TA0/CA7 D P2IE.x P2IRQ.x EN Q P2IFG.x P2SEL.x P2IES.x Set Interrupt Edge Select Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 69 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Table 21. Port P2.0 to P2.4, P2.6, and P2.7 Pin Functions PIN NAME (P2.x) x 0 P2.0/ACLK/CA2 1 P2.1/TAINCLK/CA3 2 P2.2/CAOUT/TA0/CA4 3 P2.3/CA0/TA1 4 P2.4/CA1/TA2 6 P2.6/ADC12CLK (2)/CA6 7 P2.7/TA0/CA7 (1) (2) 70 FUNCTION CONTROL BITS / SIGNALS (1) CAPD.x P2DIR.x P2SEL.x P2.0 (I/O) 0 I: 0; O: 1 0 ACLK 0 1 1 CA2 1 X X P2.1 (I/O) 0 I: 0; O: 1 0 Timer_A3.INCLK 0 0 1 DVSS 0 1 1 CA3 1 X X P2.2 (I/O) 0 I: 0; O: 1 0 CAOUT 0 1 1 TA0 0 0 1 CA4 1 X X P2.3 (I/O) 0 I: 0; O: 1 0 Timer_A3.TA1 0 1 1 CA0 1 X X P2.4 (I/O) 0 I: 0; O: 1 0 Timer_A3.TA2 0 1 X CA1 1 X 1 P2.6 (I/O) 0 I: 0; O: 1 0 ADC12CLK (2) 0 1 1 CA6 1 X X P2.7 (I/O) 0 I: 0; O: 1 0 Timer_A3.TA0 0 1 1 CA7 1 X X X = Don't care MSP430F24x and MSP430F23x devices only Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Port P2 Pin Schematic: P2.5, Input/Output With Schmitt Trigger Pad Logic To Comparator From Comparator CAPD.5 To DCO DCOR in DCO P2REN.5 P2DIR.5 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.5 DVSS P2.5/ROSC/CA5 Bus Keeper EN P2SEL.5 P2IN.5 EN Module X IN D P2IE.5 P2IRQ.5 EN Q Set P2IFG.5 P2SEL.5 P2IES.5 Interrupt Edge Select Table 22. Port P2.5 Pin Functions PIN NAME (P2.x) P2.5/ROSC/CA5 (1) x 5 FUNCTION CONTROL BITS / SIGNALS (1) CAPD DCOR P2DIR.5 P2SEL.5 P2.5 (I/O) 0 0 I: 0; O: 1 0 ROSC 0 1 X X DVSS 0 0 1 1 CA5 1 or selected 0 X X X = Don't care Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 71 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Port P3 Pin Schematic: P3.0 to P3.7, Input/Output With Schmitt Trigger Pad Logic P3REN.x P3DIR.x Module direction P3OUT.x Module X OUT 0 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output 1 0 1 P3.0/UCB0STE/UCA0CLK P3.1/UCB0SIMO/UCB0SDA P3.2/UCB0SOMI/UCB0SCL P3.3/UCB0CLK/UCA0STE P3.4/UCA0TXD/UCA0SIMO P3.5/UCA0RXD/UCA0SOMI P3.6/UCA1TXD/UCA1SIMO P3.7/UCA1RXD/UCA1SOMI P3SEL.x P3IN.x EN Module X IN D Table 23. Port P3.0 to P3.7 Pin Functions PIN NAME (P3.x) P3.0/UCB0STE/UCA0CLK x 0 P3.1/UCB0SIMO/UCB0SDA 1 P3.2/UCB0SOMI/UCB0SCL 2 P3.3/UCB0CLK/UCA0STE 3 P3.4/UCA0TXD/UCA0SIMO 4 P3.5/UCA0RXD/UCA0SOMI 5 P3.6/UCA1TXD (5)/UCA1SIMO (5) 6 P3.7/UCA1RXD (5)/UCA1SOMI (5) 7 (1) (2) (3) (4) (5) 72 FUNCTION P3.0 (I/O) UCB0STE/UCA0CLK (2) (3) P3.1 (I/O) UCB0SIMO/UCB0SDA (2) (4) P3.2 (I/O) UCB0SOMI/UCB0SCL (2) (4) P3.3 (I/O) UCB0CLK/UCA0STE (2) P3.4 (I/O) UCA0TXD/UCA0SIMO (2) P3.5 (I/O) UCA0RXD/UCA0SOMI (2) P3.6 (I/O) UCA1TXD (5)/UCA1SIMO (5) (2) P3.7 (I/O) UCA1RXD (5)/UCA1SOMI (5) (2) CONTROL BITS / SIGNALS (1) P3DIR.x P3SEL.x I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 X = Don't care The pin direction is controlled by the USCI module. UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI A/B0 is forced to 3-wire SPI mode if 4-wire SPI mode is selected. If I2C functionality is selected, the output drives only the logical 0 to VSS level. MSP430F24x and MSP430F24x1 devices only Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Port P4 Pin Schematic: P4.0 to P4.7, Input/Output With Schmitt Trigger Pad Logic P4REN.x 0 P4DIR.x 0 Module X OUT 1 0 DVCC 1 P4.0/TB0 P4.1/TB1 P4.2/TB2 P4.3/TB3 P4.4/TB4 P4.5/TB5 P4.6/TB6 P4.7/TBCLK P4SEL.x P4IN.x EN Module X IN 1 Direction 0: Input 1: Output 1 P4OUT.x DVSS D Table 24. Port P4.0 to P4.7 Pin Functions PIN NAME (P4.x) x FUNCTION P4.0 (I/O) P4.0/TB0 0 1 2 0 0 1 Timer_B7.TB0 1 1 I: 0; O: 1 0 Timer_B7.CCI1A and Timer_B7.CCI1B 0 1 Timer_B7.TB1 1 1 I: 0; O: 1 0 Timer_B7.CCI2A and Timer_B7.CCI2B 0 1 Timer_B7.TB2 1 1 I: 0; O: 1 0 0 1 1 1 I: 0; O: 1 0 0 1 1 1 I: 0; O: 1 0 0 1 1 1 I: 0; O: 1 0 0 1 P4.3 (I/O) P4.3/TB3 (1) 3 Timer_B7.CCI3A and Timer_B7.CCI3B (1) Timer_B7.TB3 (1) P4.4 (I/O) P4.4/TB4 (1) 4 Timer_B7.CCI4A and Timer_B7.CCI4B (1) Timer_B7.TB4 (1) P4.5 (I/O) P4.5/TB5 (1) 5 Timer_B7.CCI5A and Timer_B7.CCI5B (1) Timer_B7.TB5 (1) P4.6 (I/O) P4.6/TB6 (1) 6 Timer_B7.CCI6A and Timer_B7.CCI6B (1) Timer_B7.TB6 P4.7/TBCLK (1) 7 P4SEL.x I: 0; O: 1 P4.2 (I/O) P4.2/TB2 P4DIR.x Timer_B7.CCI0A and Timer_B7.CCI0B P4.1 (I/O) P4.1/TB1 CONTROL BITS / SIGNALS (1) P4.7 (I/O) Timer_B7.TBCLK 1 1 I: 0; O: 1 0 0 1 MSP430F24x and MSP430F24x1 devices only Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 73 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Port P5 Pin Schematic: P5.0 to P5.3, Input/Output With Schmitt Trigger Pad Logic P5REN.x P5DIR.x 0 Module Direction 1 P5OUT.x 0 Module X OUT DVSS 0 DVCC 1 1 Direction 0: Input 1: Output 1 P5.0/UCB1STE/UCA1CLK P5.1/UCB1SIMO/UCB1SDA P5.2/UCB1SOMI/UCB1SCL P5.3/UCB1CLK/UCA1STE P5SEL.x P5IN.x EN Module X IN D Table 25. Port P5.0 to P5.3 Pin Functions PIN NAME (P5.x) P5.0/UCB1STE (2)/UCA1CLK (2) P5.1/UCB1SIMO (2)/UCB1SDA (2) P5.2/UCB1SOMI (2)/UCB1SCL (2) P5.3/UCB1CLK (2)/UCA1STE (2) (1) (2) (3) (4) (5) 74 x 0 FUNCTION P5.0 (I/O) UCB1STE (2)/UCA1CLK (2) (3) (4) 1 P5.1 (I/O) UCB1SIMO (2)/UCB1SDA (2) (3) (5) 2 P5.2 (I/O) (2) UCB1SOMI /UCB1SCL 3 (2) (3) (5) P5.3 (I/O) UCB1CLK (2)/UCA1STE (2) (3) CONTROL BITS / SIGNALS (1) P5DIR.x P5SEL.x I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 X = Don't care MSP430F24x and MSP430F24x1 devices only The pin direction is controlled by the USCI module. UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI A/B0 is forced to 3-wire SPI mode if 4-wire SPI mode is selected. If I2C functionality is selected, the output drives only the logical 0 to VSS level. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Port P5 Pin Schematic: P5.4 to P5.7, Input/Output With Schmitt Trigger Pad Logic P5REN.x P5DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P5OUT.x DVSS P5.4/MCLK P5.5/SMCLK P5.6/ACLK P5.7/TBOUTH/SVSOUT P5SEL.x P5IN.x EN D Module X IN Table 26. Port P5.4 to P5.7 Pin Functions PIN NAME (P5.x) P5.4/MCLK P5.5/SMCLK x 4 5 P5.6/ACLK 6 P5.7/TBOUTH/SVSOUT 7 FUNCTION P5.4 (I/O) MCLK P5.5 (I/O) SMCLK P5.6 (I/O) ACLK P5.7 (I/O) CONTROL BITS / SIGNALS P5DIR.x P5SEL.x I: 0; O: 1 0 1 1 I: 0; O: 1 0 1 1 I: 0; O: 1 0 1 1 I: 0; O: 1 0 Timer_B7.TBOUTH 0 1 SVSOUT 1 1 Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 75 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Port P6 Pin Schematic: P6.0 to P6.6, Input/Output With Schmitt Trigger Pad Logic ADC12 Ax From ADC12 P6REN.x P6DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P6OUT.x DVSS P6.0/A0 P6.1/A1 P6.2/A2 P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6 Bus Keeper EN P6SEL.x P6IN.x EN Module X IN D Table 27. Port P6.0 to P6.6 Pin Functions PIN NAME (P6.x) P6.0/A0 (2) P6.1/A1 (2) P6.2/A2 (2) x 0 1 2 P6.3/A3 (2) 3 P6.4/A4 (2) 4 P6.5/A5 (2) P6.6/A6 (2) (1) (2) 76 5 6 FUNCTION P5.0 (I/O) A0 (2) P5.1 (I/O) A1 (2) P5.2 (I/O) A2 (2) P5.3 (I/O) A3 (2) P5.4 (I/O) A4 (2) P5.5 (I/O) A5 (2) P6.6 (I/O) A6 (2) CONTROL BITS / SIGNALS (1) P6DIR.x P6SEL.x I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 X = Don't care MSP430F24x and MSP430F23x devices only Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Port P6 Pin Schematic: P6.7, Input/Output With Schmitt Trigger Pad Logic To SVS Mux VLD = 15 ADC12 A7 From ADC12 P6REN.7 P6DIR.7 0 P6OUT.7 0 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 Module X OUT DVSS P6.7/A7/SVSIN Bus Keeper EN P6SEL.7 P6IN.7 EN Module X IN D Table 28. Port P6.7 Pin Functions PIN NAME (P6.x) x FUNCTION P6.7 (I/O) P6.7/A7/SVSIN (1) (2) 7 CONTROL BITS / SIGNALS (1) P6DIR.x P6SEL.x INCHy I: 0; O: 1 0 0 DVSS 1 1 0 A7 (2) X X 1 (y = 7) SVSIN (VLD = 15) X X 1 X = Don't care MSP430F24x and MSP430F23x devices only Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 77 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com JTAG Pins (TMS, TCK, TDI/TCLK, TDO/TDI), Input/Output With Schmitt Trigger TDO Controlled by JTAG Controlled by JTAG JTAG TDO/TDI Controlled by JTAG DVCC DVCC TDI Fuse Burn & T est Fuse Test TDI/TCLK and Emulation Module DVCC TMS TMS DVCC During Programming Activity and During Blowing of the Fuse, Pin TDO/TDI Is Used to Apply the Test Input Data for JTAG Circuitry TCK TCK 78 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 JTAG Fuse Check Mode MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. When the TEST pin is again taken low after a test or programming session, the fuse check mode and sense currents are terminated. Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse check mode has the potential to be activated. The fuse check current flows only when the fuse check mode is active and the TMS pin is in a low state (see Figure 42). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition). Time TMS Goes Low After POR TMS ITF ITDI/TCLK Figure 42. Fuse Check Mode Current NOTE The CODE and RAM data protection is ensured if the JTAG fuse is blown and the 256-bit bootloader access key is used. Also, see the Bootstrap Loader section for more information. Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 79 MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com REVISION HISTORY LITERATURE NUMBER SUMMARY SLAS547 Product Preview release SLAS547A Production Data release SLAS547B Corrected terminal names and descriptions for pins 34 and 35 in "Terminal Functions - MSP430F23x" (page 9) Corrected terminal names for pins 13, 14, and 15 in "Terminal Functions - MSP430F24x1" (page 13) Corrected interrupt source and flag entries for USCI_A1/USCI_B1 in "interrupt vector addresses" table (page 17) Changed index values from 1-3 to 0-2 in Figures 23 to 26 (pages 52 and 54) Changed fmax,BITCLK and tτ parameters in "USCI (UART mode)" table (page 56) Corrected "Port P1.0 to P1.7 pin functions" table (page 72) Removed incorrect CAPD.x column in "Port P6.0 to P6.6 pin functions" table (page 80) SLAS547C Added Development Tool Support section (page 2) Updated parametric values in "low-power mode supply current into VCC excluding external current" table (page 34) SLAS547D Updated notes and tCMErase MIN value "flash memory" table (page 34) SLAS547E Changed limits on td(SVSon) parameter (page 41) SLAS547F Changed "Port 6.0 to 6.6 Pin Functions" table (page 77) Changed "Port 6.7 Pin Functions" table (page 78) SLAS547G Changed Tstg, Programmed device, to -55°C to 150°C in Absolute Maximum Ratings SLAS547H Corrected formatting error of TA column in Active Mode Supply Current (both IAM,1MHz parameters) and in Low-PowerMode Supply Currents (ILPM0,1MHz and ILPM0,100kHz parameters) SLAS547I Corrected number of capture/compare registers in description in Timer_B3 (MSP430F23x Devices). Added typical test conditions in Recommended Operating Conditions. Removed "Timer_A3.CCIxA" entries from P1.5 through P1.7 in Table 20. 80 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) MSP430F233TPM ACTIVE LQFP PM 64 160 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F233T REV # MSP430F233TPMR ACTIVE LQFP PM 64 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F233T REV # MSP430F233TRGCR ACTIVE VQFN RGC 64 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F233T MSP430F233TRGCT ACTIVE VQFN RGC 64 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F233T MSP430F235TPM ACTIVE LQFP PM 64 160 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F235T REV # MSP430F235TPMR ACTIVE LQFP PM 64 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F235T REV # MSP430F235TRGCR ACTIVE VQFN RGC 64 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F235T MSP430F235TRGCT ACTIVE VQFN RGC 64 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F235T MSP430F2410TPM ACTIVE LQFP PM 64 160 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F2410T REV # MSP430F2410TPMR ACTIVE LQFP PM 64 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F2410T REV # MSP430F2410TRGCR ACTIVE VQFN RGC 64 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F2410T MSP430F2410TRGCT ACTIVE VQFN RGC 64 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F2410T MSP430F2471TPM ACTIVE LQFP PM 64 160 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F2471T REV # MSP430F2471TPMR ACTIVE LQFP PM 64 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F2471T REV # MSP430F2471TRGCR ACTIVE VQFN RGC 64 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F2471T MSP430F2471TRGCT ACTIVE VQFN RGC 64 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F2471T MSP430F247TPM ACTIVE LQFP PM 64 160 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F247T REV # MSP430F247TPMR ACTIVE LQFP PM 64 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F247T REV # Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 10-Dec-2020 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) MSP430F247TRGCR ACTIVE VQFN RGC 64 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F247T MSP430F247TRGCT ACTIVE VQFN RGC 64 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F247T MSP430F2481TPM ACTIVE LQFP PM 64 160 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F2481T REV # MSP430F2481TPMR ACTIVE LQFP PM 64 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F2481T REV # MSP430F2481TRGCR ACTIVE VQFN RGC 64 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F2481T MSP430F2481TRGCT ACTIVE VQFN RGC 64 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F2481T MSP430F248TPM ACTIVE LQFP PM 64 160 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F248T REV # MSP430F248TPMR ACTIVE LQFP PM 64 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F248T REV # MSP430F248TRGCR ACTIVE VQFN RGC 64 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F248T MSP430F248TRGCT ACTIVE VQFN RGC 64 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F248T MSP430F2491TPM ACTIVE LQFP PM 64 160 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F2491T REV # MSP430F2491TPMR ACTIVE LQFP PM 64 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F2491T REV # MSP430F2491TRGCR ACTIVE VQFN RGC 64 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F2491T MSP430F2491TRGCT ACTIVE VQFN RGC 64 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F2491T MSP430F249TPM ACTIVE LQFP PM 64 160 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F249T REV # MSP430F249TPMR ACTIVE LQFP PM 64 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F249T REV # MSP430F249TRGCR ACTIVE VQFN RGC 64 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F249T MSP430F249TRGCT ACTIVE VQFN RGC 64 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 M430F249T (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of

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