MSP430F2619, MSP430F2618, MSP430F2617, MSP430F2616
MSP430F2419, MSP430F2418, MSP430F2417, MSP430F2416
SLAS541M – JUNE 2007 – REVISED MARCH 2022
MSP430F261x, MSP430F241x Mixed-Signal Microcontrollers
1 Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Low supply voltage range: 1.8 V to 3.6 V
Ultra-low power consumption
– Active mode: 365 µA at 1 MHz, 2.2 V
– Standby mode (VLO): 0.5 µA
– Off mode (RAM retention): 0.1 µA
Wake up from standby mode in less than 1 µs
16-bit RISC architecture, 62.5-ns instruction cycle
time
Three-channel internal DMA (MSP430F261x only)
12-bit analog-to-digital converter (ADC) with
internal reference, sample-and-hold, and autoscan
feature
Dual 12-bit digital-to-analog converters (DACs)
with synchronization (MSP430F261x only)
16-bit Timer_A with three capture/compare
registers
16-bit Timer_B with seven capture/compare
registers with shadow registers
On-chip comparator
Four universal serial communication interfaces
(USCIs)
– USCI_A0 and USCI_A1
• Enhanced UART supporting automatic
baud-rate detection
• IrDA encoder and decoder
• Synchronous SPI
– USCI_B0 and USCI_B1
• I2C
• Synchronous SPI
Supply voltage supervisor and monitor with
programmable level detection
Brownout detector
Bootloader (BSL)
•
•
•
Serial onboard programming, no external
programming voltage needed, programmable code
protection by security fuse
Family members (also see Device Comparison)
– MSP430F2416
• 92KB + 256 bytes flash memory
• 4KB RAM
– MSP430F2417
• 92KB + 256 bytes flash memory
• 8KB RAM
– MSP430F2418
• 116KB + 256 bytes flash memory
• 8KB RAM
– MSP430F2419
• 120KB + 256 bytes flash memory
• 4KB RAM
– MSP430F2616
• 92KB + 256 bytes flash memory
• 4KB RAM
– MSP430F2617
• 92KB + 256 bytes flash memory
• 8KB RAM
– MSP430F2618
• 116KB + 256 bytes flash memory
• 8KB RAM
– MSP430F2619
• 120KB + 256 bytes flash memory
• 4KB RAM
Available in 80-pin quad flat pack (LQFP), 64-pin
LQFP, and 113-pin ball grid array (nFBGA)
2 Applications
•
•
•
•
Sensor systems
Industrial control applications
Hand-held meters
Medical imaging applications
3 Description
The Texas Instruments MSP430™ family of ultra-low-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes is optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The calibrated digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 1 µs.
The MSP430F261x and MSP430F241x series are microcontroller configurations with two built-in 16-bit timers,
a fast 12-bit ADC, a comparator, two 12-bit DACs, four USCI modules, DMA, and up to 64 I/O pins. The
MSP430F241x devices are identical to the MSP430F261x devices, with the exception that the DAC12 and the
DMA modules are not implemented.
The LQFP-64 package is also available as a nonmagnetic package for medical imaging applications.
For complete module descriptions, see the MSP430F2xx and MSP430G2xx Family User's Guide.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430F2619, MSP430F2618, MSP430F2617, MSP430F2616
MSP430F2419, MSP430F2418, MSP430F2417, MSP430F2416
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
Device Information
(1)
(2)
(3)
2
PART NUMBER(1)
PACKAGE
BODY SIZE(2)
MSP430F2619TPN
LQFP (80)
12 mm × 12 mm
MSP430F2619TPM
LQFP (64)
10 mm × 10 mm
MSP430F2619TZCA
nFBGA (113)
7 mm × 7 mm
MSP430F2619TZQW(3)
Junior™
7 mm × 7 mm
MicroStar
BGA (113)
For the most current part, package, and ordering information, see the Package Option Addendum
in Section 11, or see the TI website at www.ti.com.
The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 11.
All orderable part numbers in the ZQW (MicroStar Junior BGA) package have been changed to a
status of Last Time Buy. Visit the Product life cycle page for details on this status.
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MSP430F2419, MSP430F2418, MSP430F2417, MSP430F2416
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
4 Functional Block Diagrams
Figure 4-1 through Figure 4-4 show the functional block diagrams.
XIN,
XT2IN
DVCC1,
DVCC2
XOUT,
XT2OUT
2
2
ACLK
Oscillators
Basic Clock SMCLK
System+
MCLK
16MHz
CPU
1MB
incl. 16
Registers
DVSS1,
DVSS2
Flash
RAM
120KB
116KB
92KB
92KB
4KB
8KB
8KB
4KB
AVCC
AVSS
P3.x, P4.x
P5.x, P6.x
2x8
4x8
P1.x, P2.x
Ports
P1, P2
ADC12
12 bit
2x8 I/O
Interrupt
capability
8
channels
Ports
P3, P4
P5, P6
4x8 I/O
P7.x, P8.x
2x8, 1x16
Ports
P7, P8
2x8/1x16
I/O
USCI A0
UART,
LIN,
IrDA, SPI
USCI B0
2
SPI, I C
MAB
MDB
Brownout
Protection
Emulation
JTAG
Interface
SVS,
SVM
Hardware
Multiplier
Timer_B7
Watchdog
WDT+
MPY,
MPYS,
MAC,
MACS
15-Bit
Timer_A3
3 CC
Registers
Comp_A+
7 CC
Registers,
Shadow
Reg
8
Channels
USCI A1
UART,
LIN,
IrDA, SPI
USCI B1
2
SPI, I C
RST/NMI
Figure 4-1. MSP430F241x Functional Block Diagram, PN or ZCA or ZQW Package
XIN, XOUT,
XT2IN XT2OUT
2
2
DVCC
ACLK
Oscillators
Basic Clock SMCLK
System+
MCLK
16MHz
CPU
1MB
incl. 16
Registers
DVSS
Flash
RAM
120KB
116KB
92KB
92KB
4KB
8KB
8KB
4KB
AVCC
AVSS
P3.x, P4.x
P5.x, P6.x
2x8
4x8
P1.x, P2.x
Ports
P1, P2
ADC12
12 bit
2x8 I/O
Interrupt
capability
8
channels
Ports
P3, P4
P5, P6
USCI A0
UART,
LIN,
IrDA, SPI
4x8 I/O
USCI B0
SPI, I2C
MAB
MDB
Emulation
Brownout
Protection
JTAG
Interface
SVS,
SVM
Hardware
Multiplier
MPY,
MPYS,
MAC,
MACS
Timer_B7
Watchdog
WDT+
15-Bit
Timer_A3
3 CC
Registers
Comp_A+
7 CC
Registers,
Shadow
Reg
8
Channels
USCI A1
UART,
LIN,
IrDA, SPI
USCI B1
SPI, I2C
RST/NMI
Figure 4-2. MSP430F241x Functional Block Diagram, PM Package
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
XIN,
XOUT,
XT2IN XT2OUT
2
2
DVCC1,
DVCC2
ACLK
Oscillators
Basic Clock SMCLK
System+
MCLK
16-MHz
CPU
1MB
incl. 16
Registers
Flash
120KB
116KB
92KB
92KB
56KB
DVSS1,
DVSS2
AVCC
RAM
4KB
8KB
8KB
4KB
4KB
ADC12
12 bit
8
channels
AVSS
DAC12
12 bit
2
channels,
Voltage
output
P3.x, P4.x
P5.x, P6.x
4x8
2x8
P1.x, P2.x
Ports
P3, P4
P5, P6
Ports
P1, P2
2x8 I/O
Interrupt
capability
4x8 I/O
P7.x, P8.x
2x8, 1x16
Ports
P7, P8
2x8, 1x16
I/O
USCI A0
UART,
LIN,
IrDA, SPI
USCI B0
2
SPI, I C
MAB
MDB
Emulation
Brownout
Protection
JTAG
Interface
SVS,
SVM
Hardware
Multiplier
MPY,
MPYS,
MAC,
MACS
DMA
Controller
3
Channels
Timer_B7
Watchdog
WDT+
15-Bit
Comp_A+
Timer_A3
3 CC
Registers
7 CC
Registers,
Shadow
Reg
8
Channels
USCI A1
UART,
LIN,
IrDA, SPI
USCI B1
2
SPI, I C
RST/NMI
Figure 4-3. MSP430F261x Functional Block Diagram, PN or ZCA Package
XIN,
XT2IN
XOUT,
XT2OUT
2
2
DVCC
ACLK
Oscillators
Basic Clock SMCLK
System+
MCLK
16-MHz
CPU
1MB
incl. 16
Registers
Emulation
JTAG
Interface
Flash
120KB
116KB
92KB
92KB
56KB
DVSS
AVCC
RAM
4KB
8KB
8KB
4KB
4KB
ADC12
12 bit
8
channels
AVSS
DAC12
12 bit
2
channels,
Voltage
output
P3.x, P4.x
P5.x, P6.x
2x8
4x8
P1.x, P2.x
Ports
P1, P2
2x8 I/O
Interrupt
capability
Ports
P3, P4
P5, P6
USCI A0
UART,
LIN,
IrDA, SPI
4x8 I/O
USCI B0
2
SPI, I C
MAB
MDB
Brownout
Protection
SVS,
SVM
Hardware
Multiplier
MPY,
MPYS,
MAC,
MACS
DMA
Controller
3
Channels
Timer_B7
Watchdog
WDT+
15-Bit
Timer_A3
3 CC
Registers
Comp_A+
7 CC
Registers,
Shadow
Reg
8
Channels
USCI A1
UART,
LIN,
IrDA, SPI
USCI B1
SPI, I2C
RST/NMI
Figure 4-4. MSP430F261x Functional Block Diagram, PM Package
4
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Functional Block Diagrams............................................ 3
5 Revision History.............................................................. 6
6 Device Comparison......................................................... 8
6.1 Related Products........................................................ 8
7 Terminal Configuration and Functions..........................9
7.1 Pin Diagrams.............................................................. 9
7.2 Signal Descriptions................................................... 14
8 Specifications................................................................ 19
8.1 Absolute Maximum Ratings...................................... 19
8.2 ESD Ratings............................................................. 19
8.3 Recommended Operating Conditions.......................19
8.4 Active Mode Supply Current Into VCC Excluding
External Current.......................................................... 21
8.5 Typical Characteristics – Active Mode Supply
Current (Into VCC)........................................................21
8.6 Low-Power Mode Supply Currents (Into VCC)
Excluding External Current..........................................22
8.7 Typical Characteristics – LPM4 Current....................23
8.8 Schmitt-Trigger Inputs (Ports P1 to P8, RST/
NMI, JTAG, XIN, and XT2IN)...................................... 24
8.9 Inputs (Ports P1 and P2)...........................................24
8.10 Leakage Current (Ports P1 to P8)...........................24
8.11 Standard Inputs ( RST/NMI)....................................24
8.12 Outputs (Ports P1 to P8).........................................25
8.13 Output Frequency (Ports P1 to P8).........................25
8.14 Typical Characteristics – Outputs........................... 26
8.15 POR and Brownout Reset (BOR)........................... 27
8.16 Typical Characteristics – POR and BOR................ 28
8.17 Supply Voltage Supervisor (SVS), Supply
Voltage Monitor (SVM)................................................ 29
8.18 Main DCO Characteristics...................................... 31
8.19 DCO Frequency...................................................... 31
8.20 Calibrated DCO Frequencies – Tolerance at
Calibration................................................................... 32
8.21 Calibrated DCO Frequencies – Tolerance Over
Temperature 0°C to 85°C............................................ 32
8.22 Calibrated DCO Frequencies – Tolerance Over
Supply Voltage VCC .................................................... 33
8.23 Calibrated DCO Frequencies – Overall Tolerance..33
8.24 Typical Characteristics – Calibrated DCO
Frequency................................................................... 34
8.25 Wake-up Times From Lower-Power Modes
(LPM3, LPM4)............................................................. 35
8.26 Typical Characteristics – DCO Clock Wake-up
Time From LPM3 or LPM4.......................................... 35
8.27 DCO With External Resistor ROSC ......................... 36
8.28 Typical Characteristics – DCO With External
Resistor ROSC .............................................................36
8.29 Crystal Oscillator LFXT1, Low-Frequency Mode.... 37
8.30 Internal Very-Low-Power Low-Frequency
Oscillator (VLO)...........................................................37
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8.31 Crystal Oscillator LFXT1, High-Frequency Mode... 38
8.32 Typical Characteristics – LFXT1 Oscillator in
HF Mode (XTS = 1)..................................................... 39
8.33 Crystal Oscillator XT2............................................. 40
8.34 Typical Characteristics – XT2 Oscillator................. 41
8.35 Timer_A...................................................................42
8.36 Timer_B...................................................................42
8.37 USCI (UART Mode)................................................ 42
8.38 USCI (SPI Master Mode)........................................ 42
8.39 USCI (SPI Slave Mode).......................................... 43
8.40 USCI (I2C Mode).....................................................45
8.41 Comparator_A+...................................................... 46
8.42 Typical Characteristics – Comparator_A+.............. 48
8.43 12-Bit ADC Power Supply and Input Range
Conditions .................................................................. 49
8.44 12-Bit ADC External Reference.............................. 49
8.45 12-Bit ADC Built-In Reference................................ 50
8.46 12-Bit ADC Timing Parameters...............................52
8.47 12-Bit ADC Linearity Parameters............................52
8.48 12-Bit ADC Temperature Sensor and Built-In
VMID ............................................................................ 53
8.49 12-Bit DAC Supply Specifications...........................53
8.50 12-Bit DAC Linearity Specifications........................ 54
8.51 Typical Characteristics, 12-Bit DAC Linearity
Specifications.............................................................. 55
8.52 12-Bit DAC Output Specifications........................... 55
8.53 12-Bit DAC Reference Input Specifications............ 56
8.54 12-Bit DAC Dynamic Specifications........................56
8.55 Flash Memory......................................................... 58
8.56 RAM........................................................................ 58
8.57 JTAG Interface........................................................ 58
8.58 JTAG Fuse.............................................................. 58
9 Detailed Description......................................................59
9.1 CPU.......................................................................... 59
9.2 Instruction Set........................................................... 60
9.3 Operating Modes...................................................... 61
9.4 Interrupt Vector Addresses....................................... 62
9.5 Special Function Registers (SFRs)...........................63
9.6 Memory Organization................................................65
9.7 Bootloader (BSL)...................................................... 65
9.8 Flash Memory........................................................... 65
9.9 Peripherals................................................................66
9.10 Port Diagrams......................................................... 76
10 Device and Documentation Support..........................95
10.1 Getting Started........................................................95
10.2 Device Nomenclature..............................................95
10.3 Tools and Software................................................. 97
10.4 Documentation Support.......................................... 98
10.5 Support Resources............................................... 100
10.6 Trademarks........................................................... 100
10.7 Electrostatic Discharge Caution............................100
10.8 Glossary................................................................100
11 Mechanical, Packaging, and Orderable
Information.................................................................. 100
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from revision L to revision M
Changes from May 2, 2020 to March 31, 2022
Page
• Updated the numbering format for tables, figures, and cross references throughout the document..................1
• Changed the fADC12CLK MAX value to 7 MHz in Section 8.46 12-Bit ADC Timing Parameters ....................... 52
• Changed the fADC12OSC MAX value to 7 MHz in Section 8.46 12-Bit ADC Timing Parameters .......................52
• Changed the tCONVERT MIN value to 1.86 μs in Section 8.46 12-Bit ADC Timing Parameters ........................52
• Removed ADC12DIV from the formula for the TYP value of conversion time because ADC12CLK is after this
division in Section 8.46 12-Bit ADC Timing Parameters ..................................................................................52
• Added a link to additional information in Section 9.7, Bootloader (BSL) ......................................................... 65
• Updated Section 10.5, Support Resources ................................................................................................... 100
Changes from revision K to revision L
Changes from November 9, 2012 to May 1, 2020
Page
• Format changes throughout document, including addition of section numbering...............................................1
• Throughout the document, added the ZCA package..........................................................................................1
• Added the Device Information table....................................................................................................................1
• Changed the status of all orderable part numbers in the ZQW package............................................................1
• Added Section 4 and moved functional block diagrams to it.............................................................................. 3
• Added Section 6, Device Comparison ............................................................................................................... 8
• Added Section 8 and moved all electrical specifications to it........................................................................... 19
• Added Section 8.2, ESD Ratings .....................................................................................................................19
• Removed "I version" row from TA row in Section 8.3 (all available devices are "T version" temperature range)
..........................................................................................................................................................................19
• Added separate rows for Information memory segments to Table 9-8, Memory Organization ........................65
• Changed all instances of "bootstrap loader" to "bootloader"............................................................................ 65
• Changed all instances of "INCHx = 0x1010" to "INCHx = 1010b", and corrected all values in the ADDRESS
OFFSET column in Table 9-11, Labels Used by the ADC Calibration Tags .................................................... 66
• Corrected P4DIR.x value (changed from 1 to 0) for Timer_B7.TBCLK entry in Table 9-19, Port P4 (P4.0 to
P4.7) Pin Functions ......................................................................................................................................... 83
• Added Section 10 and moved Trademarks and Electrostatic Discharge Caution sections to it....................... 95
• Added Section 11, Mechanical, Packaging, and Orderable Information ........................................................100
Changes from initial release to revision K
REVISION
6
COMMENTS
SLAS541K
November 2012
Changed P8.6/XT2OUT and P8.7/XT2IN to I/O in Signal Descriptions
SLAS541J
December 2011
Added nonmagnetic package option
SLAS541I
July 2011
Changed Tstg, Programmed device, to -55°C to 150°C in Section 8.1
SLAS541H
May 2011
Changed Control Bits/Signals in Table 9-21, Table 9-22, and Table 9-23
Changed crystal signal names in Table 9-26 and Table 9-27
SLAS541G
March 2011
Changed limits on td(SVSon) parameter
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
REVISION
SLAS541F
December 2009
SLAS541E
January 2009
SLAS541D
November 2008
COMMENTS
Renamed Tags Used by the ADC Calibration Tags table to Tags used by the TLV Structure
Changed value of TAG_ADC12_1 from 0x10 to 0x08 in Tags used by the TLV Structure
Added CAOUT to P1.0/TACLK, Changed Timer_A3.CCI0A to Timer_A3.CCI1A and Timer_A3.TA0 to Timer_A3.TA1 in
P1.2/TA1 row, Changed Timer_A3.CCI0A to Timer_A3.CCI2A and Timer_A3.TA0 to Timer_A3.TA2 in P1.3/TA2 row in
Port P1 (P1.0 to P1.7) pin functions table
Changed TA0 to Timer_A3.CCI0B in P2.2/CAOUT/TA0/CA4 row of Port P2.0, P2.3, P2.4, P2.6 and P2.7 pin functions
table
Corrected LFXT1Sx values in Figures 23 and 24
Corrected XT2Sx values in Figures 25 and 26
Corrected tCMErase MIN value from 200 ms to 20 ms and removed two notes in the flash memory table
Added the ESD disclaimer
Added reserved BGA pins to the terminal function list
Corrected the references in the output port parameters
Corrected the cumulative program time of the flash
SLAS541C
June 2008
Release to market of MSP430F261x BGA devices
SLAS541B
May 2008
Added preview of MSP430F261x BGA devices
SLAS541A
October 2007
SLAS541
June 2007
PRODUCTION DATA release
Corrected the format and the content shown on the first page
Corrected pin number of P3.6 and P3.7 in 64-pin package in the terminal function list
Corrected the port schematics
Corrected "calibration data" section: typos and formatting corrected
Added the figure "typical characteristics - LPM4 current"
PRODUCT PREVIEW release
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
6 Device Comparison
Table 6-1 summarizes the available family members.
Table 6-1. Device Comparison
DEVICE
430F2619
MSP430F2618
MSP430F2617
MSP430F2616
MSP430F2419
MSP430F2418
MSP430F2417
MSP430F2416
FLASH
(KB)
120
116
92
92
120
116
92
92
RAM
(KB)
4
8
8
4
4
8
8
4
Timer_A
1x TA3
1x TA3
1x TA3
1x TA3
1x TA3
1x TA3
1x TA3
1x TA3
Timer_B
1x TB7
1x TB7
1x TB7
1x TB7
1x TB7
1x TB7
1x TB7
1x TB7
Comp_A+
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
ADC12
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
DAC12
Yes
Yes
Yes
Yes
No
No
No
No
DMA
Yes
Yes
Yes
Yes
No
No
No
No
USCI_A
2
2
2
2
2
2
2
2
USCI_B
2
2
2
2
2
2
2
2
I/O
PACKAGE
48
PM 64
64
PN 80
64
ZCA 113
64
ZQW 113
48
PM 64
64
PN 80
64
ZCA 113
64
ZQW 113
48
PM 64
64
PN 80
64
ZCA 113
64
ZQW 113
48
PM 64
64
PN 80
64
ZCA 113
64
ZQW 113
48
PM 64
64
PN 80
64
ZCA 113
64
ZQW 113
48
PM 64
64
PN 80
64
ZCA 113
64
ZQW 113
48
PM 64
64
PN 80
64
ZCA 113
64
ZQW 113
48
PM 64
64
PN 80
64
ZCA 113
64
ZQW 113
6.1 Related Products
For information about other devices in this family of products or related products, see the following links.
Overview of 16-bit and 32-bit microcontrollers
High-performance, low-power solutions to enable the autonomous future
Products for MSP430 ultra-low-power sensing & measurement MCUs
One platform. One ecosystem. Endless possibilities.
Reference designs
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
7 Terminal Configuration and Functions
7.1 Pin Diagrams
P8.5
P8.4
P8.3
P8.2
P8.1
P8.0
P7.7
AV CC
DVSS1
AV SS
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
P8.7/XT2IN
P8.6/XT2OUT
Figure 7-1 shows the pinout of the 80-pin PN package for the MSP430F241x devices.
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
DVCC1
P6.3/A3
1
2
60
59
P7.6
P7.5
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7/SVSIN
3
4
5
6
58
57
56
55
P7.4
P7.3
P7.2
P7.1
VREF+
XIN
XOUT
Ve REF+
VREF-/VeREF-
7
8
9
10
11
54
53
52
51
50
P7.0
DVSS2
DVCC2
P5.7/TBOUTH/SVSOUT
P5.6/ACLK
P1.0/TACLK/CAOUT
P1.1/TA0
P1.2/TA1
P1.3/TA2
12
13
14
15
49
48
47
46
P5.5/SMCLK
P5.4/MCLK
P5.3/UCB1CLK/UCA1STE
P5.2/UCB1SOMI/UCB1SCL
P1.4/SMCLK
P1.5/TA0
P1.6/TA1
P1.7/TA2
16
45
17
18
19
44
43
42
P5.1/UCB1SIMO/UCB1SDA
P5.0/UCB1STE/UCA1CLK
P4.7/TBCLK
P4.6/TB6
P2.0/ACLK/CA2
20
41
P4.5/TB5
P2.1/TAINCLK/CA3
P2.2/CAOUT/TA0/CA4
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.5/ROSC/CA5
P2.6/ADC12CLK/CA6
P2.7/TA0/CA7
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
P3.6/UCA1TXD/UCA1SIMO
P3.7/UCA1RXD/UCA1SOMI
P4.0/TB0
P4.1/TB1
P4.2/TB2
P4.3/TB3
P4.4/TB4
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Figure 7-1. 80-Pin PN Package, MSP430F241x (Top View)
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
AV CC
DVSS1
AV SS
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
XT2IN
XT2OUT
P5.7/TBOUTH/SVSOUT
P5.6/ACLK
P5.5/SMCLK
Figure 7-2 shows the pinout of the 64-pin PM package for the MSP430F241x devices.
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
P5.4/MCLK
P5.3/UCB1CLK/UCA1STE
VREF-/VeREF-
1
2
3
4
5
6
7
8
9
10
11
P1.0/TACLK/CAOUT
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
12
13
14
15
16
37
36
35
34
33
P4.1/TB1
P4.0/TB0
P3.7/UCA1RXD/UCA1SOMI
P3.6/UCA1TXD/UCA1SIMO
P3.5/UCA0RXD/UCA0SOMI
DVCC1
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7/SVSIN
VREF+
XIN
XOUT
Ve REF+
P5.2/UCB1SOMI/UCB1SCL
P5.1/UCB1SIMO/UCB1SDA
P5.0/UCB1STE/UCA1CLK
P4.7/TBCLK
P4.6/TB6
P4.5/TB5
P4.4/TB4
P4.3/TB3
P4.2/TB2
P1.5/TA0
P1.6/TA1
P1.7/TA2
P2.0/ACLK/CA2
P2.1/TAINCLK/CA3
P2.2/CAOUT/TA0/CA4
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.5/ROSC/CA5
P2.6/ADC12CLK/CA6
P2.7/TA0/CA7
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 7-2. 64-Pin PM Package, MSP430F241x (Top View)
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
P8.5
P8.4
P8.3
P8.2
P8.1
P8.0
P7.7
AV CC
DVSS1
AV SS
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
P8.7/XT2IN
P8.6/XT2OUT
Figure 7-3 shows the pinout of the 80-pin PN package for the MSP430F261x devices.
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
DVCC1
P6.3/A3
P6.4/A4
1
2
3
60
59
58
P7.6
P7.5
P7.4
P6.5/A5/DAC1
P6.6/A6/DAC0
P6.7/A7/DAC1/SVSIN
4
5
6
57
56
55
P7.3
P7.2
P7.1
VREF+
XIN
XOUT
7
8
9
54
53
52
P7.0
DVSS2
DVCC2
Ve REF+/DAC0
VREF-/VeREFP1.0/TACLK/CAOUT
10
11
12
51
50
49
P5.7/TBOUTH/SVSOUT
P5.6/ACLK
P5.5/SMCLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
13
14
15
48
47
46
P5.4/MCLK
P5.3/UCB1CLK/UCA1STE
P5.2/UCB1SOMI/UCB1SCL
P1.4/SMCLK
P1.5/TA0
P1.6/TA1
16
45
17
18
44
43
P5.1/UCB1SIMO/UCB1SDA
P5.0/UCB1STE/UCA1CLK
P4.7/TBCLK
P1.7/TA2
P2.0/ACLK/CA2
19
20
42
41
P4.6/TB6
P4.5/TB5
P2.1/TAINCLK/CA3
P2.2/CAOUT/TA0/CA4
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.5/ROSC/CA5
P2.6/ADC12CLK/DMAE0/CA6
P2.7/TA0/CA7
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
P3.6/UCA1TXD/UCA1SIMO
P3.7/UCA1RXD/UCA1SOMI
P4.0/TB0
P4.1/TB1
P4.2/TB2
P4.3/TB3
P4.4/TB4
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Figure 7-3. 80-Pin PN Package, MSP430F261x (Top View)
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
P5.5/SMCLK
P5.7/TBOUTH/SVSOUT
P5.6/ACLK
XT2IN
XT2OUT
TDI/TCLK
TDO/TDI
TCK
TMS
RST/NMI
P6.1/A1
P6.0/A0
AV SS
P6.2/A2
DVSS1
AV CC
Figure 7-4 shows the pinout of the 64-pin PM package for the MSP430F261x devices.
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DV CC1
1
48
P6.3/A3
2
47
P5.3/UCB1CLK/UCA1STE
P6.4/A4
3
46
P5.2/UCB1SOMI/UCB1SCL
P6.5/A5/DAC1
P6.6/A6/DAC0
4
5
45
44
P5.1/UCB1SIMO/UCB1SDA
P5.0/UCB1STE/UCA1CLK
P6.7/A7/DAC1/SVSIN
6
43
P4.7/TBCLK
VREF+
7
42
P4.6/TB6
XIN
8
41
P4.5/TB5
XOUT
Ve REF+/DAC0
9
10
40
39
P4.4/TB4
P4.3/TB3
P5.4/MCLK
VREF-/Ve REF-
11
38
P4.2/TB2
P1.0/TACLK/CAOUT
12
37
P4.1/TB1
P1.1/TA0
13
36
P4.0/TB0
P1.2/TA1
14
35
P3.7/UCA1RXD/UCA1SOMI
P1.3/TA2
P1.4/SMCLK
15
16
34
33
P3.6/UCA1TXD/UCA1SIMO
P3.5/UCA0RXD/UCA0SOMI
P3.4/UCA0TXD/UCA0SIMO
P3.3/UCB0CLK/UCA0STE
P3.2/UCB0SOMI/UCB0SCL
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P2.7/TA0/CA7
P2.6/ADC12CLK/DMAE0/CA6
P2.5/ROSC/CA5
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.1/TAINCLK/CA3
P2.2/CAOUT/TA0/CA4
P2.0/ACLK/CA2
P1.7/TA2
P1.5/TA0
P1.6/TA1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 7-4. 64-Pin PM Package, MSP430F261x (Top View)
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
Figure 7-5 shows the pinout of the 113-pin ZCA and ZQW packages. For the terminal assignments, see Section
7.2.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
C1
C2
C3
C11
C12
D1
D2
D4
D5
D6
D7
D8
D9
D11
D12
E1
E2
E4
E5
E6
E7
E8
E9
E11
E12
F1
F2
F4
F5
F8
F9
F11
F12
G1
G2
G4
G5
G8
G9
G11
G12
H1
H2
H4
H5
H6
H7
H8
H9
H11
H12
J1
J2
J4
J5
J6
J7
J8
J9
J11
J12
K1
K2
K11
K12
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
Figure 7-5. 113-Pin ZCA and ZQW Packages (Top View)
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
7.2 Signal Descriptions
Section 7.2 describes the signals for all device variants and package options.
Table 7-1. Signal Descriptions
TERMINAL
NO.
I/O
DESCRIPTION
PM
64‑PIN
PN
80‑PIN
ZCA or
ZQW
113‑PIN
AVCC
64
80
A2
Analog supply voltage, positive terminal. Supplies only the analog
portion of ADC12 and DAC12.
AVSS
62
78
B2, B3
Analog supply voltage, negative terminal. Supplies only the analog
portion of ADC12 and DAC12.
NAME
DVCC1
1
1
A1
Digital supply voltage, positive terminal. Supplies all digital parts.
DVSS1
63
79
A3
Digital supply voltage, negative terminal. Supplies all digital parts.
DVCC2
52
F12
Digital supply voltage, positive terminal. Supplies all digital parts.
DVSS2
53
E12
Digital supply voltage, negative terminal. Supplies all digital parts.
12
G2
General-purpose digital I/O pin
P1.0/TACLK/CAOUT
12
I/O
Timer_A, clock signal TACLK input
Comparator_A output
General-purpose digital I/O pin
P1.1/TA0
13
13
H1
I/O
Timer_A, capture: CCI0A input, compare: Out0 output
BSL transmit
P1.2/TA1
14
14
H2
I/O
P1.3/TA2
15
15
J1
I/O
P1.4/SMCLK
16
16
J2
I/O
P1.5/TA0
17
17
K1
I/O
P1.6/TA1
18
18
K2
I/O
P1.7/TA2
19
19
L1
I/O
P2.0/ACLK/CA2
20
20
M1
I/O
General-purpose digital I/O pin
Timer_A, capture: CCI1A input, compare: Out1 output
General-purpose digital I/O pin
Timer_A, capture: CCI2A input, compare: Out2 output
General-purpose digital I/O pin
SMCLK signal output
General-purpose digital I/O pin
Timer_A, compare: Out0 output
General-purpose digital I/O pin
Timer_A, compare: Out1 output
General-purpose digital I/O pin
Timer_A, compare: Out2 output
General-purpose digital I/O pin
ACLK output
Comparator_A input
P2.1/TAINCLK/CA3
21
21
M2
I/O
General-purpose digital I/O pin
Timer_A, clock signal at INCLK
General-purpose digital I/O pin
Timer_A, capture: CCI0B input
P2.2/CAOUT/TA0/CA4
22
22
M3
I/O
Comparator_A output
BSL receive
Comparator_A input
General-purpose digital I/O pin
P2.3/CA0/TA1
23
23
L3
I/O
Timer_A, compare: Out1 output
Comparator_A input
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
Table 7-1. Signal Descriptions (continued)
TERMINAL
NO.
NAME
PM
64‑PIN
PN
80‑PIN
ZCA or
ZQW
113‑PIN
I/O
DESCRIPTION
General-purpose digital I/O pin
P2.4/CA1/TA2
24
24
L4
I/O
Timer_A, compare: Out2 output
Comparator_A input
General-purpose digital I/O pin
P2.5/ROSC/CA5
25
25
M4
I/O
Input for external resistor defining the DCO nominal frequency
Comparator_A input
General-purpose digital I/O pin
P2.6/ADC12CLK/
DMAE0(1)/CA6
26
26
J4
I/O
Conversion clock for 12-bit ADC
DMA channel 0 external trigger
Comparator_A input
General-purpose digital I/O pin
P2.7/TA0/CA7
27
27
L5
I/O
Timer_A, compare: Out0 output
Comparator_A input
General-purpose digital I/O pin
P3.0/UCB0STE/
UCA0CLK
28
P3.1/UCB0SIMO/
UCB0SDA
29
M5
I/O
USCI_B0 slave transmit enable
USCI_A0 clock input/output
General-purpose digital I/O pin
29
L6
I/O
USCI_B0 slave in master out for SPI mode
USCI_B0 SDA I2C data in I2C mode
General-purpose digital I/O pin
P3.2/UCB0SOMI/
UCB0SCL
30
P3.3/UCB0CLK/
UCA0STE
31
P3.4/UCA0TXD/
UCA0SIMO
32
P3.5/UCA0RXD/
UCA0SOMI
28
30
M6
I/O
USCI_B0 slave out master in for SPI mode
USCI_B0 SCL I2C clock in I2C mode
General-purpose digital I/O
31
L7
I/O
USCI_B0 clock input/output
USCI_A0 slave transmit enable
General-purpose digital I/O pin
32
M7
I/O
USCI_A transmit data output in UART mode
USCI_A slave data in/master out for SPI mode
General-purpose digital I/O pin
33
33
L8
I/O
USCI_A0 receive data input in UART mode
USCI_A0 slave data out/master in for SPI mode
General-purpose digital I/O pin
P3.6/UCA1TXD/
UCA1SIMO
34
P3.7/UCA1RXD/
UCA1SOMI
35
P4.0/TB0
36
36
M9
I/O
P4.1/TB1
37
37
J9
I/O
P4.2/TB2
38
38
M10
I/O
34
M8
I/O
USCI_A1 transmit data output in UART mode
USCI_A1 slave data in/master out for SPI mode
General-purpose digital I/O pin
35
L9
I/O
USCI_A1 receive data input in UART mode
USCI_A1 slave data out/master in for SPI mode
Copyright © 2022 Texas Instruments Incorporated
General-purpose digital I/O pin
Timer_B, capture: CCI0A/B input, compare: Out0 output
General-purpose digital I/O pin
Timer_B, capture: CCI1A/B input, compare: Out1 output
General-purpose digital I/O pin
Timer_B, capture: CCI2A/B input, compare: Out2 output
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
Table 7-1. Signal Descriptions (continued)
TERMINAL
NO.
I/O
PM
64‑PIN
PN
80‑PIN
ZCA or
ZQW
113‑PIN
P4.3/TB3
39
39
L10
I/O
P4.4/TB4
40
40
M11
I/O
P4.5/TB5
41
41
M12
I/O
P4.6/TB6
42
42
L12
I/O
P4.7/TBCLK
43
43
K11
I/O
P5.0/UCB1STE/
UCA1CLK
44
44
K12
I/O
P5.1/UCB1SIMO/
UCB1SDA
45
NAME
DESCRIPTION
General-purpose digital I/O pin
Timer_B, capture: CCI3A/B input, compare: Out3 output
General-purpose digital I/O pin
Timer_B, capture: CCI4A/B input, compare: Out4 output
General-purpose digital I/O pin
Timer_B, capture: CCI5A/B input, compare: Out5 output
General-purpose digital I/O pin
Timer_B, capture: CCI6A input, compare: Out6 output
General-purpose digital I/O pin
Timer_B, clock signal TBCLK input
General-purpose digital I/O pin
USCI_B1 slave transmit enable
USCI_A1 clock input/output
General-purpose digital I/O pin
45
J11
I/O
USCI_B1 slave in master out for SPI mode
USCI_B1 SDA I2C data in I2C mode
General-purpose digital I/O pin
P5.2/UCB1SOMI/
UCB1SCL
46
46
J12
I/O
USCI_B1 slave out master in for SPI mode
USCI_B1 SCL I2C clock in I2C mode
General-purpose digital I/O
P5.3/UCB1CLK/
UCA1STE
47
P5.4/MCLK
48
48
H12
I/O
P5.5/SMCLK
49
49
G11
I/O
P5.6/ACLK
50
50
G12
I/O
47
H11
I/O
USCI_B1 clock input/output
USCI_A1 slave transmit enable
General-purpose digital I/O pin
Main system clock MCLK output
General-purpose digital I/O pin
Submain system clock SMCLK output
General-purpose digital I/O pin
Auxiliary clock ACLK output
General-purpose digital I/O pin
P5.7/TBOUTH/SVSOUT
51
51
F11
I/O
Switch all PWM digital output ports to high impedance – Timer_B TB0
to TB6
SVS comparator output
P6.0/A0
59
75
D4
I/O
P6.1/A1
60
76
A4
I/O
P6.2/A2
61
77
B4
I/O
P6.3/A3
2
2
B1
I/O
P6.4/A4
3
3
C1
I/O
16
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General-purpose digital I/O pin
Analog input A0 for 12-bit ADC
General-purpose digital I/O pin
Analog input A1 for 12-bit ADC
General-purpose digital I/O pin
Analog input A2 for 12-bit ADC
General-purpose digital I/O pin
Analog input A3 for 12-bit ADC
General-purpose digital I/O pin
Analog input A4 for 12-bit ADC
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
Table 7-1. Signal Descriptions (continued)
TERMINAL
NO.
NAME
PM
64‑PIN
P6.5/A5/DAC1(1)
4
PN
80‑PIN
ZCA or
ZQW
113‑PIN
4
C2,
C3
I/O
DESCRIPTION
General-purpose digital I/O pin
I/O
Analog input A5 for 12-bit ADC
DAC12.1 output
General-purpose digital I/O pin
P6.6/A6/DAC0(1)
5
5
D1
I/O
Analog input A6 for 12-bit ADC
DAC12.0 output
General-purpose digital I/O pin
P6.7/A7/DAC1(1)/SVSIN
6
Analog input A7 for 12-bit ADC
6
D2
I/O
P7.0
54
E11
I/O
General-purpose digital I/O pin
P7.1
55
D12
I/O
General-purpose digital I/O pin
P7.2
56
D11
I/O
General-purpose digital I/O pin
P7.3
57
C12
I/O
General-purpose digital I/O pin
P7.4
58
C11
I/O
General-purpose digital I/O pin
P7.5
59
B12
I/O
General-purpose digital I/O pin
P7.6
60
A12
I/O
General-purpose digital I/O pin
P7.7
61
A11
I/O
General-purpose digital I/O pin
P8.0
62
B10
I/O
General-purpose digital I/O pin
P8.1
63
A10
I/O
General-purpose digital I/O pin
P8.2
64
D9
I/O
General-purpose digital I/O pin
P8.3
65
A9
I/O
General-purpose digital I/O pin
P8.4
66
B9
I/O
General-purpose digital I/O pin
P8.5
67
B8
I/O
General-purpose digital I/O pin
P8.6/XT2OUT
68
A8
I/O
P8.7/XT2IN
69
A7
I/O
Input port for crystal oscillator XT2. Only standard crystals can be
connected.
DAC12.1 output
SVS input
General-purpose digital I/O pin
Output terminal of crystal oscillator XT2
General-purpose digital I/O pin
XT2OUT
52
O
Output terminal of crystal oscillator XT2
XT2IN
53
I
Input port for crystal oscillator XT2
RST/NMI
58
74
B5
I
Reset input, nonmaskable interrupt input port, or bootloader start (in
flash devices)
TCK
57
73
A5
I
Test clock (JTAG). TCK is the clock input port for device programming
test and bootloader start
TDI/TCLK
55
71
A6
I
Test data input or test clock input. The device protection fuse is
connected to TDI/TCLK.
TDO/TDI
54
70
B7
I/O
TMS
56
72
B6
I
VeREF+/DAC0(1)
10
10
F2
I
VREF+
7
7
E2
O
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Test data output port. TDO/TDI data output or programming data input
terminal.
Test mode select. TMS is used as an input port for device programming
and test.
Input for an external reference voltage
DAC12.0 output
Output of positive terminal of the reference voltage in the ADC12
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
Table 7-1. Signal Descriptions (continued)
TERMINAL
NO.
I/O
DESCRIPTION
PM
64‑PIN
PN
80‑PIN
ZCA or
ZQW
113‑PIN
VREF-/VeREF-
11
11
G1
I
Negative terminal for the reference voltage for both sources, the
internal reference voltage or an external applied reference voltage
XIN
8
8
E1
I
Input port for crystal oscillator XT1. Standard or watch crystals can be
connected.
XOUT
9
9
F1
O
Output port for crystal oscillator XT1. Standard or watch crystals can be
connected.
Reserved
–
–
(2)
NA
NAME
(1)
(2)
18
Reserved pins. TI recommends connecting to DVSS and AVSS.
MSP430F261x devices only
Reserved pins are L2, E4, F4, G4, H4, D5, E5, F5, G5, H5, J5, D6, E6, H6, J6, D7, E7, H7, J7, D8, E8, F8, G8, H8, J8, E9, F9, G9,
H9, B11, L11.
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
–0.3
4.1
–0.3
VCC + 0.3
–2
2
Unprogrammed device
–55
150
Programmed device
–55
150
Voltage applied at VCC to VSS
Voltage applied to any
pin(2)
Diode current at any device terminal
Storage temperature, Tstg (3)
(1)
(2)
(3)
UNIT
V
V
mA
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TEST pin when blowing the JTAG fuse.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
8.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as
±250 V may actually have higher performance.
8.3 Recommended Operating Conditions
Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
VCC
Supply voltage (AVCC = DVCC = VCC (1))
VSS
Supply voltage (AVSS = DVSS = VSS)
TA
Operating free-air temperature
fSYSTEM
(1)
(2)
(3)
Processor frequency (maximum MCLK frequency)(2) (3) (see
Figure 8-1)
MIN
MAX
UNIT
During program execution
1.8
3.6
During flash program or erase
2.2
3.6
0
0
V
T version
–40
105
°C
VCC = 1.8 V,
Duty cycle = 50% ±10%
DC
4.15
VCC = 2.7 V,
Duty cycle = 50% ±10%
DC
12
VCC ≥ 3.3 V,
Duty cycle = 50% ±10%
DC
16
V
MHz
TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up.
The MSP430 CPU is clocked directly with MCLK. Both the high and low phases of MCLK must not exceed the pulse duration of the
specified maximum frequency.
Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
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Legend :
System Frequency
16 MHz
Supply voltage range
during flash memory
programming
12 MHz
Supply voltage range
during program execution
7.5 MHz
4.15 MHz
1.8 V
2.2 V
2.7 V
3.3 V 3.6 V
Supply Voltage
A.
Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V.
Figure 8-1. Operating Area
20
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8.4 Active Mode Supply Current Into VCC Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2) (see Figure
8-2 and Figure 8-3)
PARAMETER
Active mode (AM)
current (1 MHz)
IAM,1MHz
Active mode (AM)
current (1 MHz)
IAM,1MHz
Active mode (AM)
current (4 kHz)
IAM,4kHz
Active mode (AM)
current (100 kHz)
IAM,100kHz
(1)
(2)
TEST CONDITIONS
TA
fDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 32768 Hz,
Program executes in flash,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0,
SCG1 = 0, OSCOFF = 0
–40°C to 85°C
fDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 32768 Hz,
Program executes in RAM,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0,
SCG1 = 0, OSCOFF = 0
–40°C to 85°C
fMCLK = fSMCLK = fACLK = 32768 Hz/8
= 4096 Hz,
fDCO = 0 Hz,
Program executes in flash,
SELMx = 11, SELS = 1,
DIVMx = DIVSx = DIVAx = 11,
CPUOFF = 0, SCG0 = 1,
SCG1 = 0, OSCOFF = 0
–40°C to 85°C
fMCLK = fSMCLK = fDCO(0, 0) ≈ 100 kHz,
fACLK = 0 Hz,
Program executes in flash,
RSELx = 0, DCOx = 0,
CPUOFF = 0, SCG0 = 0,
SCG1 = 0, OSCOFF = 1
105°C
VCC
MIN
MAX UNIT
365
395
375
420
515
560
525
595
330
370
340
390
460
495
470
520
2.2 V
2.1
9
2.2 V
–40°C to 85°C
3V
105°C
105°C
TYP
2.2 V
–40°C to 85°C
3V
105°C
105°C
2.2 V
15
31
–40°C to 85°C
3V
3
11
105°C
3V
19
32
–40°C to 85°C
2.2 V
67
86
105°C
2.2 V
80
99
–40°C to 85°C
3V
84
107
105°C
3V
99
128
µA
µA
µA
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
8.5 Typical Characteristics – Active Mode Supply Current (Into VCC)
7.0
10.0
9.0
6.0
TA = 25 °C
8.0
Active Mode Current − mA
Active Mode Current − mA
TA = 85 °C
f DCO = 16 MHz
f DCO = 12 MHz
7.0
6.0
5.0
f DCO = 8 MHz
4.0
3.0
4.0
TA = 85 °C
3.0
TA = 25 °C
2.0
2.0
f DCO = 1 MHz
1.0
1.0
0.0
1.5
2.0
2.5
3.0
3.5
4.0
VCC − Supply Voltage − V
Figure 8-2. Active Mode Current vs Supply Voltage (TA = 25°C)
Copyright © 2022 Texas Instruments Incorporated
VCC = 3 V
5.0
0.0
0.0
VCC = 2.2 V
4.0
8.0
12.0
16.0
f DCO − DCO Frequency − MHz
Figure 8-3. Active Mode Current vs DCO Frequency
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8.6 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
PARAMETER
ILPM0,1MHz
ILPM0,100kHz
Low-power mode 0
(LPM0) current(3)
Low-power mode 0
(LPM0) current(3)
Low-power mode 2
(LPM2) current(4)
ILPM2
ILPM3,LFXT1
Low-power mode 3
(LPM3) current(3)
TEST CONDITIONS
TA
TYP
MAX
68
63
83
98
87
105
100
125
37
49
50
62
40
55
57
73
23
33
35
46
25
36
40
55
–40°C
0.8
1.2
25°C
1
1.3
fMCLK = 0 MHz,
fSMCLK = fDCO = 1 MHz,
fACLK = 32,768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0,
SCG1 = 0, OSCOFF = 0
–40°C to 85°C
fMCLK = 0 MHz,
fSMCLK = fDCO(0, 0) ≈ 100 kHz,
fACLK = 0 Hz,
RSELx = 0, DCOx = 0,
CPUOFF = 1, SCG0 = 0,
SCG1 = 0, OSCOFF = 1
–40°C to 85°C
fMCLK = fSMCLK = 0 MHz, fDCO = 1
MHz,
fACLK = 32,768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0,
SCG1 = 1, OSCOFF = 0
–40°C to 85°C
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 32,768 Hz,
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 0
105°C
ILPM3,VLO
Low-power mode 3
(LPM3) current(4)
105°C
ILPM4
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 1
2.2 V
105°C
3V
2.2 V
–40°C to 85°C
105°C
105°C
3V
2.2 V
–40°C to 85°C
105°C
85°C
3V
2.2 V
4.6
7
105°C
14
24
–40°C
0.9
1.3
1.1
1.5
25°C
3V
5.5
8
105°C
17
30
–40°C
0.4
1
25°C
0.5
1
85°C
2.2 V
4.3
6.5
105°C
14
24
–40°C
0.6
1.2
0.6
1.2
25°C
85°C
Low-power mode
4 (LPM4) current(5)
(see Figure 8-4)
MIN
–40°C to 85°C
85°C
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK from internal LF oscillator
(VLO),
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 0
VCC
3V
5
7.5
105°C
16.5
29.5
–40°C
0.1
0.5
25°C
0.1
0.5
85°C
2.2 V
4
6
105°C
13
23
–40°C
0.2
0.5
0.2
0.5
25°C
85°C
3V
105°C
(1)
(2)
(3)
(4)
(5)
22
4.7
7
14
24
UNIT
µA
µA
µA
µA
µA
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF.
Current for brownout and WDT clocked by SMCLK included.
Current for brownout and WDT clocked by ACLK included.
Current for brownout included.
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ILPM4 − Low−power mode current − µA
8.7 Typical Characteristics – LPM4 Current
16.0
15.0
14.0
13.0
12.0
11.0
10.0
9.0
8.0
VCC = 3.6 V
7.0
VCC = 3.0 V
6.0
5.0
VCC = 2.2 V
4.0
3.0
2.0
1.0
VCC = 1.8 V
0.0
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0
TA − Temperature − °C
Figure 8-4. LPM4 Current vs Temperature
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8.8 Schmitt-Trigger Inputs (Ports P1 to P8, RST/NMI, JTAG, XIN, and XT2IN)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
VIT+
TEST CONDITIONS
Positive-going input threshold voltage
VCC
2.2 V
3V
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup/pulldown resistor
For pullup: VIN = VSS,
For pulldown: VIN = VCC
CI
Input capacitance
VIN = VSS or VCC
(1)
MIN
TYP
MAX
0.45 VCC
0.75 VCC
1.00
1.65
1.35
2.25
0.25 VCC
0.55 VCC
2.2 V
0.55
1.20
3V
0.75
1.65
2.2 V
0.2
1
3V
0.3
1
20
35
50
5
UNIT
V
V
V
kΩ
pF
XIN and XT2IN in bypass mode only
8.9 Inputs (Ports P1 and P2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
t(int)
(1)
TEST CONDITIONS
VCC
Port P1, P2: P1.x to P2.x, External trigger pulse duration to
set interrupt flag(1)
External interrupt timing
MIN
2.2 V, 3 V
MAX
20
UNIT
ns
An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set even with trigger
signals shorter than t(int).
8.10 Leakage Current (Ports P1 to P8)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Px.y)
(1)
(2)
High-impedance leakage
VCC
current(1) (2)
MIN
2.2 V, 3 V
MAX
UNIT
±50
nA
The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
8.11 Standard Inputs ( RST/NMI)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
VCC
MIN
MAX
VIL
Low-level input voltage
PARAMETER
2.2 V, 3 V
VSS
VSS + 0.6
V
VIH
High-level input voltage
2.2 V, 3 V
0.8 VCC
VCC
V
24
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8.12 Outputs (Ports P1 to P8)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(also see Figure 8-5, Figure 8-6, Figure 8-7, and Figure 8-8)
PARAMETER
VOH
VOL
(1)
(2)
TEST CONDITIONS
High-level output voltage
Low-level output voltage
VCC
MIN
I(OHmax) = –1.5 mA(1)
2.2 V
VCC – 0.25
TYP
MAX
VCC
I(OHmax) = –6 mA (2)
2.2 V
VCC – 0.6
VCC
I(OHmax) = –1.5 mA(1)
3V
VCC – 0.25
VCC
I(OHmax) = –6 mA(2)
3V
VCC – 0.6
VCC
I(OLmax) = 1.5 mA(1)
2.2 V
VSS
VSS + 0.25
I(OLmax) = 6 mA(2)
2.2 V
VSS
VSS + 0.6
I(OLmax) = 1.5 mA(1)
3V
VSS
VSS + 0.25
I(OLmax) = 6 mA(2)
3V
VSS
VSS + 0.6
UNIT
V
V
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±12 mA to hold the maximum voltage
drop specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage
drop specified.
8.13 Output Frequency (Ports P1 to P8)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fPx.y
Port output frequency
(with load)
P1.4/SMCLK, CL = 20 pF, RL = 1 kΩ(1) (2)
fPort°CLK
Clock output frequency
P2.0/ACLK/CA2, P1.4/SMCLK, CL = 20 pF(2)
t(Xdc)
MAX
2.2 V
DC
10
3V
DC
12
2.2 V
DC
12
3V
DC
16
30%
50%
70%
40%
50%
60%
P5.4/MCLK, CL = 20 pF, DCO
P1.4/SMCLK, CL = 20 pF, DCO
(2)
TYP
P5.6/ACLK, CL = 20 pF, XT1 mode
P1.4/SMCLK, CL = 20 pF, XT2 mode
(1)
MIN
P5.6/ACLK, CL = 20 pF, LF mode
P5.4/MCLK, CL = 20 pF, XT1 mode
Duty cycle of output
frequency
VCC
40%
60%
50% –
15 ns
50% +
15 ns
40%
60%
50% –
15 ns
50% +
15 ns
UNIT
MHz
MHz
A resistive divider with two 0.5-kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap of the
divider.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
8.14 Typical Characteristics – Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
50.0
VCC = 2.2 V
P4.5
TA = 25°C
20.0
I OL − Typical Low-Level Output Current − mA
I OL − Typical Low-Level Output Current − mA
25.0
TA = 85°C
15.0
10.0
5.0
0.0
0.0
0.5
1.0
1.5
2.0
VCC = 3 V
P4.5
TA = 85°C
30.0
20.0
10.0
0.0
0.0
2.5
VOL − Low-Level Output Voltage − V
I OH − Typical High-Level Output Current − mA
I OH − Typical High-Level Output Current − mA
1.5
2.0
2.5
3.0
3.5
0.0
VCC = 2.2 V
P4.5
−5.0
−10.0
−15.0
TA = 85°C
TA = 25°C
0.5
1.0
1.5
2.0
2.5
VOH − High-Level Output Voltage − V
Figure 8-7. High-Level Output Current vs High-Level Output
Voltage
26
1.0
Figure 8-6. Low-Level Output Current vs Low-Level Output
Voltage
0.0
−25.0
0.0
0.5
VOL − Low-Level Output Voltage − V
Figure 8-5. Low-Level Output Current vs Low-Level Output
Voltage
−20.0
TA = 25°C
40.0
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VCC = 3 V
P4.5
−10.0
−20.0
−30.0
TA = 85°C
−40.0
−50.0
0.0
TA = 25°C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOH − High-Level Output Voltage − V
Figure 8-8. High-Level Output Current vs High-Level Output
Voltage
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
8.15 POR and Brownout Reset (BOR)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC(start)
See Figure 8-9
dVCC/dt ≤ 3 V/s
V(B_IT–)
See Figure 8-9, Figure 8-10, and Figure 8-11
dVCC/dt ≤ 3 V/s
Vhys(B_IT–)
See Figure 8-9
dVCC/dt ≤ 3 V/s
td(BOR)
See Figure 8-9
t(reset)
Pulse duration needed at RST/NMI pin to accept
reset internally
(1)
VCC
MIN
TYP
MAX
0.7 ×
V(B_IT–)
70
2.2 V, 3 V
130
2
UNIT
V
1.71
V
210
mV
2000
µs
µs
The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT–) +
Vhys(B_IT–) is ≤ 1.8 V.
VCC
Vhys(B_IT−)
V(B_IT−)
VCC(start)
1
0
t d(BOR)
Figure 8-9. POR and BOR vs Supply Voltage
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
8.16 Typical Characteristics – POR and BOR
VCC
2
tpw
3V
VCC = 3 V
Typical Conditions
VCC(drop) − V
1.5
1
VCC(drop)
0.5
0
0.001
1
1000
1 ns
t pw − Pulse Width − µs
1 ns
t pw − Pulse Width − µs
Figure 8-10. VCC(drop) Level With a Rectangular Voltage Drop to Generate a POR or BOR Signal
VCC
2
tpw
3V
VCC(drop) − V
VCC = 3 V
1.5
Typical Conditions
1
VCC(drop)
0.5
t f = tr
0
0.001
1
t pw − Pulse Width − µs
1000
tf
tr
t pw − Pulse Width − µs
Figure 8-11. VCC(drop) Level With a Triangular Voltage Drop to Generate a POR or BOR Signal
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
8.17 Supply Voltage Supervisor (SVS), Supply Voltage Monitor (SVM)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
t(SVSR)
TEST CONDITIONS
MIN
dVCC/dt > 30 V/ms (see Figure 8-12)
5
SVSon, switch from VLD = 0 to VLD ≠ 0, VCC = 3 V
tsettle
VLD ≠ 0(2)
V(SVSstart)
VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 8-12)
2000
150
VLD = 1
VCC/dt ≤ 3 V/s (see Figure 8-12)
Vhys(SVS_IT–)
VCC/dt ≤ 3 V/s (see Figure 8-12), external voltage
applied on A7
VCC/dt ≤ 3 V/s (see Figure 8-12 and Figure 8-13)
V(SVS_IT–)
VCC/dt ≤ 3 V/s (see Figure 8-12 and Figure 8-13),
external voltage applied on A7
(1)
(2)
(3)
VLD ≠ 0, VCC = 2.2 V, 3 V
MAX
150
dVCC/dt ≤ 30 V/ms
td(SVSon)
ICC(SVS) (3)
TYP
70
µs
300
µs
12
µs
1.55
1.7
V
120
155
mV
0.004 ×
V(SVS_IT–)
0.016 ×
V(SVS_IT–)
VLD = 15
4.4
20
VLD = 1
1.8
1.9
2.05
VLD = 2
1.94
2.1
2.25
VLD = 3
2.05
2.2
2.37
VLD = 4
2.14
2.3
2.48
VLD = 5
2.24
2.4
2.60
VLD = 6
2.33
2.5
2.71
VLD = 7
2.46
2.65
2.86
VLD = 8
2.58
2.8
3
VLD = 9
2.69
2.9
3.13
VLD = 10
2.83
3.05
3.29
VLD = 11
2.94
3.2
3.42
VLD = 12
3.11
3.35
3.61(1)
VLD = 13
3.24
3.5
3.76(1)
VLD = 14
3.43
3.7(1)
3.99(1)
VLD = 15
1.1
1.2
1.3
10
15
VLD = 2 to 14
UNIT
V
mV
V
µA
The recommended operating voltage range is limited to 3.6 V.
tsettle is the settling time that the comparator output requires to have a stable level after VLD is switched from VLD ≠ 0 to a different
VLD value somewhere between 2 and 15. The overdrive is assumed to be >50 mV.
The current consumption of the SVS module is not included in the ICC current consumption data.
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Software sets VLD >0:
SVS is active
AVCC
V(SVS_IT−)
V(SVSstart)
Vhys(SVS_IT−)
Vhys(B_IT−)
V(B_IT−)
VCC(start)
Brownout
Region
Brownout
Region
Brownout
1
0
SVS out
t d(BOR)
t d(BOR)
SVS Circuit is Active From VLD > to V CC < V( B_IT−)
1
0
td(SVSon)
Set POR
1
td(SVSR)
undefined
0
Figure 8-12. SVS Reset (SVSR) vs Supply Voltage
VCC
3V
t pw
2
Rectangular Drop
VCC(min)
VCC(min) − V
1.5
Triangular Drop
1
1 ns
1 ns
VCC
0.5
t pw
3V
0
1
10
100
1000
t pw − Pulse Width − µs
VCC(min)
t f = tr
tf
tr
t − Pulse Width − µs
Figure 8-13. VCC(min): Rectangular Voltage Drop and Triangular Voltage Drop to Generate an SVS Signal
(VLD = 1)
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
8.18 Main DCO Characteristics
•
•
•
All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15.
DCO control bits DCOx have a step size as defined by parameter SDCO.
Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to:
32 × fDCO(RSEL,DCO) × fDCO(RSEL,DCO+1)
faverage =
MOD × fDCO(RSEL,DCO) + (32 – MOD) × fDCO(RSEL,DCO+1)
8.19 DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
RSELx < 14
1.8
3.6
RSELx = 14
2.2
3.6
UNIT
VCC
Supply voltage
3.0
3.6
fDCO(0,0)
DCO frequency (0, 0)
RSELx = 0, DCOx = 0, MODx = 0
2.2 V, 3 V
0.06
0.14
MHz
fDCO(0,3)
DCO frequency (0, 3)
RSELx = 0, DCOx = 3, MODx = 0
2.2 V, 3 V
0.07
0.17
MHz
fDCO(1,3)
DCO frequency (1, 3)
RSELx = 1, DCOx = 3, MODx = 0
2.2 V, 3 V
0.10
0.20
MHz
fDCO(2,3)
DCO frequency (2, 3)
RSELx = 2, DCOx = 3, MODx = 0
2.2 V, 3 V
0.14
0.28
MHz
fDCO(3,3)
DCO frequency (3, 3)
RSELx = 3, DCOx = 3, MODx = 0
2.2 V, 3 V
0.20
0.40
MHz
fDCO(4,3)
DCO frequency (4, 3)
RSELx = 4, DCOx = 3, MODx = 0
2.2 V, 3 V
0.28
0.54
MHz
fDCO(5,3)
DCO frequency (5, 3)
RSELx = 5, DCOx = 3, MODx = 0
2.2 V, 3 V
0.39
0.77
MHz
fDCO(6,3)
DCO frequency (6, 3)
RSELx = 6, DCOx = 3, MODx = 0
2.2 V, 3 V
0.54
1.06
MHz
fDCO(7,3)
DCO frequency (7, 3)
RSELx = 7, DCOx = 3, MODx = 0
2.2 V, 3 V
0.80
1.50
MHz
fDCO(8,3)
DCO frequency (8, 3)
RSELx = 8, DCOx = 3, MODx = 0
2.2 V, 3 V
1.10
2.10
MHz
fDCO(9,3)
DCO frequency (9, 3)
RSELx = 9, DCOx = 3, MODx = 0
2.2 V, 3 V
1.60
3.00
MHz
fDCO(10,3)
DCO frequency (10, 3)
RSELx = 10, DCOx = 3, MODx = 0
2.2 V, 3 V
2.50
4.30
MHz
fDCO(11,3)
DCO frequency (11, 3)
RSELx = 11, DCOx = 3, MODx = 0
2.2 V, 3 V
3.00
5.50
MHz
fDCO(12,3)
DCO frequency (12, 3)
RSELx = 12, DCOx = 3, MODx = 0
2.2 V, 3 V
4.30
7.30
MHz
fDCO(13,3)
DCO frequency (13, 3)
RSELx = 13, DCOx = 3, MODx = 0
2.2 V, 3 V
6.00
9.60
MHz
fDCO(14,3)
DCO frequency (14, 3)
RSELx = 14, DCOx = 3, MODx = 0
2.2 V, 3 V
8.60
13.9
MHz
fDCO(15,3)
DCO frequency (15, 3)
RSELx = 15, DCOx = 3, MODx = 0
3V
12.0
18.5
MHz
fDCO(15,7)
DCO frequency (15, 7)
RSELx = 15, DCOx = 7, MODx = 0
3V
16.0
26.0
MHz
SRSEL
Frequency step between
range RSEL and RSEL+1
SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO)
2.2 V, 3 V
1.55
ratio
SDCO
Frequency step between tap
DCO and DCO+1
SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)
2.2 V, 3 V
1.05
1.08
1.12
ratio
Duty cycle
Measured at P1.4/SMCLK
2.2 V, 3 V
40%
50%
60%
RSELx = 15
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8.20 Calibrated DCO Frequencies – Tolerance at Calibration
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Frequency tolerance at calibration
TA
VCC
MIN
TYP
MAX
UNIT
25°C
3V
–1%
±0.2%
+1%
25°C
3V
0.990
1
1.010
MHz
fCAL(1MHz)
1-MHz calibration value
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
fCAL(8MHz)
8-MHz calibration value
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
25°C
3V
7.920
8
8.080
MHz
fCAL(12MHz)
12-MHz calibration value
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
25°C
3V
11.88
12
12.12
MHz
fCAL(16MHz)
16-MHz calibration value
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms
25°C
3V
15.84
16
16.16
MHz
UNIT
8.21 Calibrated DCO Frequencies – Tolerance Over Temperature 0°C to 85°C
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fCAL(1MHz)
fCAL(8MHz)
TA
VCC
MIN
TYP
MAX
1-MHz tolerance over
temperature
0°C to 85°C
3V
–2.5%
±0.5%
+2.5%
8-MHz tolerance over
temperature
0°C to 85°C
3V
–2.5%
±1.0%
+2.5%
12-MHz tolerance over
temperature
0°C to 85°C
3V
–2.5%
±1.0%
+2.5%
16-MHz tolerance over
temperature
0°C to 85°C
3V
–3%
±2.0%
+3%
2.2 V
0.970
1
1.030
3V
0.975
1
1.025
3.6 V
0.970
1
1.030
2.2 V
7.760
8
8.40
1-MHz calibration value
8-MHz calibration value
TEST CONDITIONS
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
fCAL(12MHz)
BCSCTL1 = CALBC1_12MHZ,
12-MHz calibration value DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
fCAL(16MHz)
BCSCTL1 = CALBC1_16MHZ,
16-MHz calibration value DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms
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0°C to 85°C
0°C to 85°C
0°C to 85°C
0°C to 85°C
3V
7.800
8
8.20
3.6 V
7.600
8
8.24
2.2 V
11.64
12
12.36
3V
11.64
12
12.36
3.6 V
11.64
12
12.36
3V
15.52
16
16.48
3.6 V
15.00
16
16.48
MHz
MHz
MHz
MHz
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8.22 Calibrated DCO Frequencies – Tolerance Over Supply Voltage VCC
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX
1-MHz tolerance over VCC
25°C
1.8 V to 3.6 V
–3%
±2%
+3%
8-MHz tolerance over VCC
25°C
1.8 V to 3.6 V
–3%
±2%
+3%
12-MHz tolerance over VCC
25°C
2.2 V to 3.6 V
–3%
±2%
+3%
16-MHz tolerance over VCC
25°C
3 V to 3.6 V
–6%
±2%
+3%
UNIT
fCAL(1MHz)
1-MHz calibration value
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
25°C
1.8 V to 3.6 V
0.97
1
1.03
MHz
fCAL(8MHz)
8-MHz calibration value
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
25°C
1.8 V to 3.6 V
7.76
8
8.24
MHz
fCAL(12MHz)
12-MHz calibration value
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
25°C
2.2 V to 3.6 V
11.64
12
12.36
MHz
fCAL(16MHz)
16-MHz calibration value
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms
25°C
3 V to 3.6 V
15
16
16.48
MHz
8.23 Calibrated DCO Frequencies – Overall Tolerance
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TA
VCC
MIN
TYP
MAX UNIT
1-MHz tolerance
overall
–40°C to 105°C
1.8 V to 3.6 V
–5%
±2%
+5%
8-MHz tolerance
overall
–40°C to 105°C
1.8 V to 3.6 V
–5%
±2%
+5%
12-MHz tolerance
overall
–40°C to 105°C
2.2 V to 3.6 V
–5%
±2%
+5%
16-MHz tolerance
overall
–40°C to 105°C
3 V to 3.6 V
–6%
±3%
+6%
fCAL(1MHz)
BCSCTL1 = CALBC1_1MHZ,
1-MHz calibration value
DCOCTL = CALDCO_1MHZ,
(see Figure 8-14)
Gating time: 5 ms
–40°C to 105°C
1.8 V to 3.6 V
0.95
1
1.05
MHz
fCAL(8MHz)
BCSCTL1 = CALBC1_8MHZ,
8-MHz calibration value
DCOCTL = CALDCO_8MHZ,
(see Figure 8-15)
Gating time: 5 ms
–40°C to 105°C
1.8 V to 3.6 V
7.6
8
8.4
MHz
fCAL(12MHz)
BCSCTL1 = CALBC1_12MHZ,
12-MHz calibration
DCOCTL = CALDCO_12MHZ,
value (see Figure 8-16)
Gating time: 5 ms
–40°C to 105°C
2.2 V to 3.6 V
11.4
12
12.6
MHz
fCAL(16MHz)
BCSCTL1 = CALBC1_16MHZ,
16-MHz calibration
DCOCTL = CALDCO_16MHZ,
value (see Figure 8-17)
Gating time: 2 ms
–40°C to 105°C
3 V to 3.6 V
15
16
17
MHz
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TEST CONDITIONS
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8.24 Typical Characteristics – Calibrated DCO Frequency
1.02
8.20
TA = 105 °C
8.15
8.10
Frequency − MHz
Frequency − MHz
1.01
TA = 105 °C
1.00
TA = 85 °C
TA = 25 °C
0.99
8.00
TA = 85 °C
TA = 25 °C
7.95
TA = −40 °C
7.90
7.85
TA = −40 °C
0.98
1.5
8.05
2.0
2.5
3.0
3.5
7.80
1.5
4.0
2.0
VCC − Supply Voltage − V
2.5
Figure 8-14. Calibrated 1-MHz Frequency vs Supply Voltage
16.0
TA = −40 °C
TA = −40 °C
Frequency − MHz
Frequency − MHz
4.0
16.1
12.1
TA = 25 °C
12.0
TA = 85 °C
11.9
TA = 105 °C
11.8
2.0
2.5
3.0
3.5
4.0
Figure 8-16. Calibrated 12-MHz Frequency vs Supply Voltage
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15.9
TA = 25 °C
TA = 85 °C
15.8
TA = 105 °C
15.7
VCC − Supply Voltage − V
34
3.5
Figure 8-15. Calibrated 8-MHz Frequency vs Supply Voltage
12.2
11.7
1.5
3.0
VCC − Supply Voltage − V
15.6
1.5
2.0
2.5
3.0
3.5
4.0
VCC − Supply Voltage − V
Figure 8-17. Calibrated 16-MHz Frequency vs Supply Voltage
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
8.25 Wake-up Times From Lower-Power Modes (LPM3, LPM4)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ
tDCO,LPM3/4
DCO clock wake-up time from
LPM3 or LPM4(1) (see Figure
8-18)
(1)
(2)
UNIT
2
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ
2.2 V, 3 V
1.5
µs
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ
tCPU,LPM3/4
MAX
1
3V
CPU wake-up time from LPM3
or LPM4(2)
1
1 / fMCLK +
tClock,LPM3/4
The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt) to the first clock
edge observable externally on a clock pin (MCLK or SMCLK).
Parameter applicable only if DCOCLK is used for MCLK.
8.26 Typical Characteristics – DCO Clock Wake-up Time From LPM3 or LPM4
DCO Wake Time − µs
10.00
RSELx = 12 to 15
1.00
RSELx = 0 to 11
0.10
0.10
1.00
10.00
DCO Frequency − MHz
Figure 8-18. DCO Wake-up Time From LPM3 vs DCO Frequency
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8.27 DCO With External Resistor ROSC
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
(see Figure 8-19, Figure 8-20, Figure 8-21, and Figure 8-22)
PARAMETER
TEST CONDITIONS
VCC
TYP
2.2 V
1.8
3V
1.95
UNIT
fDCO,ROSC
DCO output frequency with ROSC
DCOR = 1,
RSELx = 4, DCOx = 3, MODx = 0,
TA = 25°C
DT
Temperature drift
DCOR = 1,
RSELx = 4, DCOx = 3, MODx = 0
2.2 V, 3 V
±0.1
%/°C
DV
Drift with VCC
DCOR = 1,
RSELx = 4, DCOx = 3, MODx = 0
2.2 V, 3 V
10
%/V
(1)
MHz
ROSC = 100 kΩ. Metal film resistor, type 0257, 0.6 W with 1% tolerance and TK = ±50 ppm/°C.
8.28 Typical Characteristics – DCO With External Resistor ROSC
10.00
DCO Frequency − MHz
DCO Frequency − MHz
10.00
RSELx = 4
1.00
0.10
0.01
10.00
100.00
1000.00
RSELx = 4
1.00
0.10
0.01
10.00
10000.00
ROSC − External Resistor − kW
Figure 8-19. DCO Frequency vs ROSC
(VCC = 2.2 V, TA = 25°C)
1.75
1.50
1.25
1.00
ROSC = 270k
0.75
0.50
DCO Frequency − MHz
2.25
ROSC = 100k
2.00
DCO Frequency − MHz
10000.00
2.50
2.25
ROSC = 100k
2.00
1.75
1.50
1.25
1.00
ROSC = 270k
0.75
0.50
ROSC = 1M
0.25
−25.0
0.0
25.0
50.0
75.0
100.0
Figure 8-21. DCO Frequency vs Temperature
(VCC = 3 V)
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ROSC = 1M
0.25
TA − Temperature − °C
36
1000.00
Figure 8-20. DCO Frequency vs ROSC
(VCC = 3 V, TA = 25°C)
2.50
0.00
−50.0
100.00
ROSC − External Resistor − kW
0.00
1.5
2.0
2.5
3.0
3.5
4.0
VCC − Supply Voltage − V
Figure 8-22. DCO Frequency vs Supply Voltage
(TA = 25°C)
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8.29 Crystal Oscillator LFXT1, Low-Frequency Mode
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
fLFXT1,LF
LFXT1 oscillator crystal
frequency, LF mode 0, 1
XTS = 0, LFXT1Sx = 0 or 1
1.8 V to 3.6 V
fLFXT1,LF,logic
LFXT1 oscillator logic level
square wave input frequency,
LF mode
XTS = 0, LFXT1Sx = 3, XCAPx = 0
1.8 V to 3.6 V
OALF
Oscillation allowance for
LF crystals
Integrated effective load
capacitance, LF mode(2)
CL,eff
fFault,LF
(1)
MIN
TYP
MAX
32768
10000
32768
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 6 pF
500
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 12 pF
200
UNIT
Hz
50000
Hz
kΩ
XTS = 0, XCAPx = 0
1
XTS = 0, XCAPx = 1
5.5
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
11
Duty cycle, LF mode
XTS = 0, Measured at P2.0/ACLK,
fLFXT1,LF = 32768 Hz
2.2 V, 3 V
30%
Oscillator fault frequency,
LF mode(3)
XTS = 0, LFXT1Sx = 3, XCAPx = 0(4)
2.2 V, 3 V
10
50%
pF
70%
10000
Hz
To improve EMI on the XT1 oscillator, the following guidelines should be observed.
•
•
•
•
•
•
•
(2)
(3)
(4)
Keep the trace between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, the
effective load capacitance should always match the specification of the crystal that is used.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
8.30 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TA
–40°C to 85°C
fVLO
VLO frequency
dfVLO/dT
VLO frequency temperature drift(1)
dfVLO/dVCC
(1)
(2)
VLO frequency supply voltage
105°C
drift(2)
VCC
2.2 V, 3 V
2.2 V, 3 V
25°C
MIN
TYP
MAX
4
12
20
22
UNIT
kHz
0.5
%/°C
4
%/V
1.8 V to 3.6 V
Calculated using the box method:
I: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (-40°C))
T: (MAX(–40°C to 105°C) – MIN(–40°C to 105°C)) / MIN(–40°C to 105°C) / (105°C – (-40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
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8.31 Crystal Oscillator LFXT1, High-Frequency Mode
PARAMETER(1)
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
fLFXT1,HF0
LFXT1 oscillator crystal
frequency, HF mode 0
XTS = 1, LFXT1Sx = 0, XCAPx = 0
1.8 V to 3.6 V
0.4
1
MHz
fLFXT1,HF1
LFXT1 oscillator crystal
frequency, HF mode 1
XTS = 1, LFXT1Sx = 1, XCAPx = 0
1.8 V to 3.6 V
1
4
MHz
1.8 V to 3.6 V
2
10
fLFXT1,HF2
LFXT1 oscillator crystal
frequency, HF mode 2
XTS = 1, LFXT1Sx = 2, XCAPx = 0
2.2 V to 3.6 V
2
12
3 V to 3.6 V
fLFXT1,HF,logic
LFXT1 oscillator logic-level
square-wave input frequency, XTS = 1, LFXT1Sx = 3, XCAPx = 0
HF mode
2
16
1.8 V to 3.6 V
0.4
10
2.2 V to 3.6 V
0.4
12
3 V to 3.6 V
0.4
16
XTS = 1, XCAPx = 0, LFXT1Sx = 0,
fLFXT1,HF = 1 MHz, CL,eff = 15 pF
Integrated effective load
capacitance, HF mode(2)
CL,eff
Duty cycle, HF mode
fFault,HF
(1)
Oscillator fault frequency(4)
800
XTS = 1, XCAPx = 0,
Measured at P2.0/ACLK,
fLFXT1,HF = 16 MHz
XTS = 1, LFXT1Sx = 3, XCAPx = 0(5)
Ω
300
XTS = 1, XCAPx = 0(3)
XTS = 1, XCAPx = 0,
Measured at P2.0/ACLK,
fLFXT1,HF = 10 MHz
MHz
2700
Oscillation allowance for HF
XTS = 1, XCAPx = 0, LFXT1Sx = 1,
crystals (see Figure 8-23 and
fLFXT1,HF = 4 MHz, CL,eff = 15 pF
Figure 8-24)
XTS = 1, XCAPx = 0, LFXT1Sx = 2,
fLFXT1,HF = 16 MHz, CL,eff = 15 pF
OAHF
MHz
1
pF
40%
50%
60%
40%
50%
60%
2.2 V, 3 V
2.2 V, 3 V
30
300
kHz
To improve EMI on the XT2 oscillator the following guidelines should be observed:
•
•
•
•
•
•
•
(2)
(3)
(4)
(5)
38
Keep the trace between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, verify
the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the
specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and
frequencies in between might set the flag.
Measured with logic-level input frequency, but also applies to operation with crystals.
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8.32 Typical Characteristics – LFXT1 Oscillator in HF Mode (XTS = 1)
1500
100000
1400
10000
1000
LFXT1Sx = 2
100
LFXT1Sx =0
LFXT1Sx = 1
XT Oscillator Supply Current − µA
Oscillation Allowance − W
1300
LFXT1Sx = 2
1200
1100
1000
900
800
700
600
500
400
300
LFXT1Sx = 1
200
100
10
0.10
1.00
10.00
100.00
Crystal Frequency − MHz
Figure 8-23. Oscillation Allowance vs Crystal Frequency
CL,eff = 15 pF, TA = 25°C
Copyright © 2022 Texas Instruments Incorporated
LFXT1Sx = 0
0
0
4
8
12
16
20
Crystal Frequency − MHz
Figure 8-24. Oscillator Supply Current vs Crystal Frequency
CL,eff = 15 pF, TA = 25°C
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8.33 Crystal Oscillator XT2
PARAMETER(1)
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
fXT2
XT2 oscillator crystal frequency, mode 0
XT2Sx = 0
1.8 V to 3.6 V
0.4
1
MHz
fXT2
XT2 oscillator crystal frequency, mode 1
XT2Sx = 1
1.8 V to 3.6 V
1
4
MHz
1.8 V to 2.2 V
2
10
fXT2
XT2 oscillator crystal frequency, mode 2
XT2Sx = 2
2.2 V to 3.6 V
2
12
3 V to 3.6 V
fXT2
OA
CL,eff
XT2 oscillator logic-level square-wave input
frequency
Oscillation allowance (see Figure 8-25 and
Figure 8-26)
Integrated effective load capacitance,
HF mode(2)
(1)
(2)
(3)
(4)
(5)
40
10
2.2 V to 3.6 V
0.4
12
3 V to 3.6 V
0.4
16
2700
XT2Sx = 1, fXT2 = 4 MHz,
CL,eff = 15 pF
800
XT2Sx = 2, fXT2 = 16 MHz,
CL,eff = 15 pF
300
See (3)
Measured at P1.4/SMCLK,
fXT2 = 16 MHz
Oscillator fault frequency, HF mode(4)
16
0.4
XT2Sx = 0, fXT2 = 1 MHz,
CL,eff = 15 pF
Measured at P1.4/SMCLK,
fXT2 = 10 MHz
Duty cycle
fFault
XT2Sx = 3
2
1.8 V to 2.2 V
XT2Sx = 3(5)
MHz
MHz
Ω
1
pF
40%
50%
60%
40%
50%
60%
2.2 V, 3 V
2.2 V, 3 V
30
300
kHz
To improve EMI on the XT2 oscillator the following guidelines should be observed:
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.
• Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, verify
the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the
specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and
frequencies in between might set the flag.
Measured with logic-level input frequency, but also applies to operation with crystals.
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8.34 Typical Characteristics – XT2 Oscillator
10000
1000
XT2Sx = 2
100
XT2Sx = 0
XT2Sx = 1
10
0.10
1.00
10.00
100.00
Crystal Frequency − MHz
Figure 8-25. Oscillation Allowance vs Crystal Frequency
CL,eff = 15 pF, TA = 25°C
Copyright © 2022 Texas Instruments Incorporated
XT Oscillator Supply Current − µA
Oscillation Allowance − W
100000
1600
1500
1400
1300
1200
1100
1000
900
XT2Sx = 2
800
700
600
500
400
300
200
100
0
XT2Sx = 1
XT2Sx = 0
0
4
8
12
16
20
Crystal Frequency − MHz
Figure 8-26. Oscillator Supply Current vs Crystal Frequency
CL,eff = 15 pF, TA = 25°C
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8.35 Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTA
Timer_A clock frequency
Internal: SMCLK or ACLK,
External: TACLK or INCLK,
Duty cycle = 50% ±10%
tTA,cap
Timer_A capture timing
TA0, TA1, TA2
VCC
MIN
TYP
MAX UNIT
2.2 V
10
3V
16
2.2 V, 3 V
20
MHz
ns
8.36 Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTB
Timer_B clock frequency
Internal: SMCLK or ACLK,
External: TBCLK or INCLK,
Duty cycle = 50% ±10%
tTB,cap
Timer_B capture timing
TB0, TB1, TB2
VCC
MIN
TYP
MAX UNIT
2.2 V
10
3V
16
2.2 V, 3 V
20
MHz
ns
8.37 USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fUSCI
USCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baud rate in MBaud)(1)
tτ
UART receive deglitch time(2)
(1)
(2)
TEST CONDITIONS
VCC
MIN
TYP
Internal: SMCLK or ACLK,
External: UCLK,
Duty cycle = 50% ±10%
MAX UNIT
fSYSTEM MHz
2.2 V, 3 V
1 MHz
2.2 V
50
150
600
3V
50
100
600
ns
The DCO wake-up time must be considered in LPM3 or LPM4 for baud rates above 1 MHz.
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed.
8.38 USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
(see Figure 8-27 and Figure 8-28)
PARAMETER
fUSCI
USCI input clock frequency
tSU,MI
SOMI input data setup time
tHD,MI
SOMI input data hold time
tVALID,MO
SIMO output data valid time
(1)
42
TEST CONDITIONS
VCC
MIN
SMCLK, ACLK
Duty cycle = 50% ±10%
UCLK edge to SIMO valid, CL = 20 pF
MAX UNIT
fSYSTEM MHz
2.2 V
110
3V
75
2.2 V
0
3V
0
ns
ns
2.2 V
30
3V
20
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave))
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
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8.39 USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Figure 8-29 and Figure 8-30)
PARAMETER(1)
TEST CONDITIONS
VCC
MIN
TYP
MAX
STE lead time, STE low to clock
2.2 V, 3 V
tSTE,LAG
STE lag time, last clock to STE high
2.2 V, 3 V
tSTE,ACC
STE access time, STE low to SOMI data out
2.2 V, 3 V
50
ns
tSTE,DIS
STE disable time, STE high to SOMI high
impedance
2.2 V, 3 V
50
ns
tSU,SI
SIMO input data setup time
tHD,SI
SIMO input data hold time
tVALID,SO
SOMI output data valid time
(1)
UCLK edge to SOMI valid,
CL = 20 pF
50
UNIT
tSTE,LEAD
ns
10
2.2 V
20
3V
15
2.2 V
10
3V
10
ns
ns
ns
2.2 V
75
110
3V
50
75
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI))
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tSU,MI
tLO/HI
tHD,MI
SOMI
tVALID,MO
SIMO
Figure 8-27. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tHD,MI
tSU,MI
SOMI
tVALID,MO
SIMO
Figure 8-28. SPI Master Mode, CKPH = 1
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tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tSU,SI
tHD,SI
SIMO
tVALID,SO
tSTE,ACC
tSTE,DIS
SOMI
Figure 8-29. SPI Slave Mode, CKPH = 0
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tHD,SI
tSU,SI
SIMO
tSTE,ACC
tVALID,SO
tSTE,DIS
SOMI
Figure 8-30. SPI Slave Mode, CKPH = 1
44
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8.40 USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 8-31)
PARAMETER
fUSCI
USCI input clock frequency
fSCL
SCL clock frequency
TEST CONDITIONS
VCC
MIN
TYP
Internal: SMCLK or ACLK,
External: UCLK,
Duty cycle = 50% ±10%
2.2 V, 3 V
fSCL ≤ 100 kHz
UNIT
fSYSTEM
MHz
400
kHz
4
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
2.2 V, 3 V
0
tSU,DAT
Data setup time
2.2 V, 3 V
250
ns
tSU,STO
Setup time for STOP
2.2 V, 3 V
4
µs
tSP
Pulse duration of spikes suppressed by
input filter
2.2 V
50
150
600
3V
50
100
600
fSCL > 100 kHz
fSCL ≤ 100 kHz
fSCL > 100 kHz
tHD,STA
2.2 V, 3 V
0
MAX
2.2 V, 3 V
µs
0.6
4.7
µs
0.6
ns
ns
tSU,STA tHD,STA
SDA
1/fSCL
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 8-31. I2C Mode Timing
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8.41 Comparator_A+
over recommended operating free-air temperature range (unless otherwise noted)(1) (2)
PARAMETER
TEST CONDITIONS
I(DD)
CAON = 1, CARSEL = 0, CAREF = 0
I(Refladder/RefDiode)
CAON = 1, CARSEL = 0, CAREF = 1/2/3,
No load at P2.3/CA0/TA1 and P2.4/CA1/TA2
VCC
MIN
TYP
MAX
2.2 V
25
40
3V
45
60
2.2 V
30
50
3V
45
71
UNIT
µA
µA
VIC
Common-mode input
voltage range
CAON = 1
2.2 V, 3 V
0
V(Ref025)
(Voltage at 0.25 VCC
node) ÷ VCC
PCA0 = 1, CARSEL = 1, CAREF = 1,
No load at P2.3/CA0/TA1 and P2.4/CA1/TA2
2.2 V, 3 V
0.23
0.24
0.25
V(Ref050)
(Voltage at 0.5 VCC
node) ÷ VCC
PCA0 = 1, CARSEL = 1, CAREF = 2,
No load at P2.3/CA0/TA1 and P2.4/CA1/TA2
2.2 V, 3 V
0.47
0.48
0.5
See Figure 8-35 and
Figure 8-36
PCA0 = 1, CARSEL = 1, CAREF = 3,
No load at P2.3/CA0/TA1 and P2.4/CA1/TA2,
TA = 85°C
2.2 V
390
480
540
V(RefVT)
3V
400
490
550
V(offset)
Offset voltage(3)
2.2 V, 3 V
–30
30
mV
Vhys
Input hysteresis
2.2 V, 3 V
0
0.7
1.4
mV
TA = 25°C, Overdrive 10 mV,
Without filter: CAF = 0
2.2 V
80
165
300
3V
70
120
240
TA = 25°C, Overdrive 10 mV,
With filter: CAF = 1
2.2 V
1.4
1.9
2.8
3V
0.9
1.5
2.2
t(response)
(1)
(2)
(3)
(4)
46
Response time, low to
high and high to low(4)
(see Figure 8-32 and
Figure 8-33)
CAON = 1
VCC – 1
V
mV
ns
µs
The leakage current for the Comparator_A+ terminals is identical to Ilkg(Px.y) specification.
Also see Figure 8-34 and Figure 8-37.
The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements.
The two successive measurements are then summed together.
The response time is measured at P2.2/CAOUT/TA0/CA4 with an input voltage step and with Comparator_A+ already enabled
(CAON = 1). If CAON is set at the same time, a settling time of up to 300 ns is added to the response time.
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0V
VCC
1
0
CAF
CAON
To Internal
Modules
Low-Pass Filter
V+
V−
+
_
0
0
1
1
CAOUT
Set CAIFG
Flag
τ ≈ 2.0 µs
Figure 8-32. Comparator_A+ Module Block Diagram
VCAOUT
Overdrive
V−
400 mV
t(response)
V+
Figure 8-33. Overdrive Definition
CASHORT
CA0
CA1
1
VIN
+
−
Comparator_A+
CASHORT = 1
IOU T = 10 µA
Figure 8-34. Comparator_A+ Short Resistance Test Condition
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8.42 Typical Characteristics – Comparator_A+
650
650
VCC = 2.2 V
600
V(REFVT) − Reference Volts −mV
V(REFVT) − Reference Volts −mV
VCC = 3 V
Typical
550
500
450
400
−45
−25
−5
15
35
55
75
600
Typical
550
500
450
400
−45
95
−25
TA − Free-Air Temperature − °C
−5
15
35
55
75
95
TA − Free-Air Temperature − °C
Figure 8-35. V(RefVT) vs Temperature
(VCC = 3 V)
Figure 8-36. V(RefVT) vs Temperature
(VCC = 2.2 V)
Short Resistance − kW
100.00
VCC = 1.8 V
VCC = 2.2 V
10.00
VCC = 3.0 V
VCC = 3.6 V
1.00
0.0
0.2
0.4
0.6
0.8
1.0
VIN/VCC − Normalized Input Voltage − V/V
Figure 8-37. Short Resistance vs VIN/VCC
48
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8.43 12-Bit ADC Power Supply and Input Range Conditions
over recommended operating free-air temperature range (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
VCC
AVCC
Analog supply voltage
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
V(P6.x/Ax)
Analog input voltage
range(2)
All P6.0/A0 to P6.7/A7 terminals, Analog inputs
selected in ADC12MCTLx register,
P6Sel.x = 1, 0 ≤ × ≤ 7,
V(AVSS) ≤ VP6.x/Ax ≤ V(AVCC)
IADC12
f
= 5 MHz,
Operating supply current ADC12CLK
ADC12ON = 1, REFON = 0,
into AVCC terminal(3)
SHT0 = 0, SHT1 = 0, ADC12DIV = 0
IREF+
fADC12CLK = 5 MHz,
ADC12ON = 0, REFON = 1, REF2_5V = 1
Operating supply current
(4)
into AVCC terminal
fADC12CLK = 5 MHz,
ADC12ON = 0, REFON = 1, REF2_5V = 0
CI
Input capacitance(5)
Only one terminal can be selected at one time,
P6.x/Ax
RI
Input MUX ON
resistance(5)
0 V ≤ VAx ≤ VAVCC
(1)
(2)
(3)
(4)
(5)
MIN
TYP
MAX
UNIT
2.2
3.6
V
0
VAVCC
V
2.2 V
0.65
0.8
3V
0.8
1
3V
0.5
0.7
2.2 V
0.5
0.7
3V
0.5
0.7
2.2 V
3V
mA
mA
40
pF
2000
Ω
The leakage current is defined in the leakage current table with P6.x/Ax parameter.
The analog input voltage range must be within the selected reference voltage range VR+ to VR- for valid conversion results.
The internal reference supply current is not included in current consumption parameter IADC12.
The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. The REFON bit enables settling of the built-in reference before starting an A/D conversion.
Not production tested, limits verified by design.
8.44 12-Bit ADC External Reference
over recommended operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VeREF+
Positive external reference voltage input
VeREF+ > VREF-/VeREF-
VREF-/VeREF-
Negative external reference voltage input
VeREF+ > VREF-/VeREF- (3)
(VeREF+ – VREF-/
VeREF-)
Differential external reference voltage input
VeREF+ > VREF-/VeREF- (4)
IVeREF+
Static leakage current
0 V ≤ VeREF+ ≤ VAVCC
IVREF-/VeREF-
Static leakage current
0 V ≤ VeREF- ≤ VAVCC
(1)
(2)
(3)
(4)
VCC
MIN
(2)
MAX UNIT
1.4 VAVCC
0
V
1.2
V
1.4 VAVCC
V
2.2 V, 3 V
±1
µA
2.2 V, 3 V
±1
µA
The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
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8.45 12-Bit ADC Built-In Reference
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 8-39 and Figure 8-40)
PARAMETER
TEST CONDITIONS
Positive built-in
reference voltage
output
VREF+
AVCC(min)
AVCC minimum
voltage, positive
built-in reference
active
TA
REF2_5V = 1 for 2.5 V,
IVREF+max ≤ IVREF+ ≤ IVREF+min
–40°C to 85°C
REF2_5V = 0 for 1.5 V,
IVREF+max ≤ IVREF+ ≤ IVREF+min
–40°C to 85°C
105°C
105°C
IL(VREF)+
2.4
2.5
2.6
2.5
2.64
1.44
1.5
1.56
1.42
1.5
1.57
2.8
REF2_5V = 1,
–1 mA ≤ IVREF+ ≤ IVREF+min
2.9
UNIT
V
V
2.2 V
0.01
–0.5
3V
0.01
–1
2.2 V
±2
3V
±2
mA
LSB
IVREF+ = 500 µA ±100 µA,
Analog input voltage ≈ 1.25 V,
REF2_5V = 1
3V
±2
3V
20
Load current
regulation, VREF+
terminal (2)
IVREF+ = 100 µA → 900 µA,
CVREF+ = 5 µF, Ax ≈ 0.5 × VREF+,
Error of conversion result ≤ 1 LSB
CVREF+
Capacitance at pin
VREF+ (3)
REFON = 1,
0 mA ≤ IVREF+ ≤ IVREF+max
TREF+
Temperature
I
is a constant in the range of
coefficient of built-in VREF+
0 mA ≤ IVREF+ ≤ 1 mA
(2)
reference
tREFON
Settling time of
internal reference
voltage (see Figure
8-38)(2) (4)
(4)
MAX
2.37
REF2_5V = 1,
–0.5 mA ≤ IVREF+ ≤ IVREF+min
IDL(VREF) +
(1)
(2)
(3)
2.2 V, 3 V
TYP
2.2
IVREF+ = 500 µA ±100 µA,
Analog input voltage ≈ 0.75 V,
REF2_5V = 0
Load-current
regulation, VREF+
terminal (1)
3V
MIN
REF2_5V = 0,
IVREF+max ≤ IVREF+ ≤ IVREF+min
Load current out of
VREF+terminal
IVREF+
VCC
2.2 V, 3 V
5
10
2.2 V, 3 V
IVREF+ = 0.5 mA, CVREF+ = 10 µF,
VREF+ = 1.5 V, VAVCC = 2.2 V
ns
µF
±100 ppm/°C
2.2 V
17
ms
Not production tested, limits characterized
Not production tested, limits verified by design
The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests use two
capacitors between pins VREF+ and AVSS and between VREF-/VeREF- and AVSS: 10-µF tantalum and 100-nF ceramic.
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load.
CVREF+
100 µF
t REFON ≈ .66 x CVREF+ [ms] with C VREF+ in µF
10 µF
1 µF
0
1 ms
10 ms
100 ms
t REFON
Figure 8-38. Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF+
50
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DVCC
From power supply
+
−
DVSS
10 µF
100 nF
AVCC
+
−
AVSS
10 µF
Apply external reference [VeREF+]
or use internal reference [VREF+]
100 nF
VREF+ or VeREF+
+
−
10 µF
100 nF
Apply external reference
VREF−/VeREF−
+
−
10 µ F
MSP430F261x
MSP430F241x
100 nF
Figure 8-39. Supply Voltage and Reference Voltage Design VREF-/VeREF- External Supply
DVCC
From power supply
+
−
DVSS
10 µF
100 nF
AVCC
+
−
AVSS
10 µF
Apply external reference [VeREF+]
or use internal reference [VREF+]
100 nF
VREF+ or VeREF+
+
−
10 µF
Reference is internally
switched to AVSS
MSP430F261x
MSP430F241x
100 nF
VREF−/VeREF−
Figure 8-40. Supply Voltage and Reference Voltage Design VREF-/VeREF- = AVSS, Internally Connected
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8.46 12-Bit ADC Timing Parameters
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
fADC12CLK
fADC12OSC
Internal ADC12 oscillator
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
For specified performance of ADC12
linearity parameters
2.2 V, 3 V
0.45
5
7 MHz
ADC12DIV = 0,
fADC12CLK = fADC12OSC
2.2 V, 3 V
3.7
5
7 MHz
CVREF+ ≥ 5 µF, Internal oscillator,
fADC12OSC = 3.7 MHz to 7 MHz
2.2 V, 3 V
1.86
tCONVERT
Conversion time
tADC12ON
Turn-on settling time of the
ADC (1)
See (2)
tSample
Sampling time (1)
RS = 400 Ω,RI = 1000 Ω, CI = 30 pF,
τ = [RS +RI] × CI (3)
(1)
(2)
(3)
External fADC12CLK from ACLK, MCLK,
or SMCLK, ADC12SSEL ≠ 0
3.51
µs
13 × 1/
fADC12CLK
100
3V
1220
2.2 V
1400
ns
ns
Limits verified by design
The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signal are already
settled.
Approximately 10 Tau (τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) × (RS + RI) × CI + 800 ns, where n = ADC resolution = 12, RS = external source resistance
8.47 12-Bit ADC Linearity Parameters
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
1.4 V ≤ (VeREF+ – VREF-/VeREF-) min ≤ 1.6 V
VCC
EI
Integral linearity
error
ED
Differential linearity (VeREF+ – VREF-/VeREF-) min ≤ (VeREF+ – VREF-/VeREF-),
error
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
2.2 V, 3 V
EO
Offset error
(VeREF+ – VREF-/VeREF-) min ≤ (VeREF+ – VREF-/VeREF-),
Internal impedance of source RS < 100 Ω,
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
2.2 V, 3 V
EG
Gain error
(VeREF+ – VREF-/VeREF-) min ≤ (VeREF+ – VREF-/VeREF-),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
ET
Total unadjusted
error
(VeREF+ – VREF-/VeREF- ) min ≤ (VeREF+ -VREF-/VeREF-),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
52
1.6 V < (VeREF+ – VREF-/VeREF-) min ≤ VAVCC
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MIN
TYP
MAX UNIT
±2
2.2 V, 3 V
±1.7
LSB
±1
LSB
±2
±4
LSB
2.2 V, 3 V
±1.1
±2
LSB
2.2 V, 3 V
±2
±5
LSB
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8.48 12-Bit ADC Temperature Sensor and Built-In VMID
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Operating supply current into
AVCC terminal (2)
ISENSOR
Temperature sensor voltage(3)
VSENSOR
REFON = 0, INCH = 0Ah,
ADC12ON = 1, TA = 25°C
VCC
MIN
TYP
MAX UNIT
2.2 V
40
120
3V
60
160
2.2 V
986
3V
986
2.2 V
3.55
3V
3.55
(1)
ADC12ON = 1, INCH = 0Ah, TA = 0°C
TCSENSOR
Temperature coefficient(1)
ADC12ON = 1, INCH = 0Ah
tSENSOR(sample)
Sample time required if
channel 10 is selected (4) (1)
ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
IVMID
Current into divider at channel
11(5)
ADC12ON = 1, INCH = 0Bh
VMID
AVCC divider at channel 11
ADC12ON = 1, INCH = 0Bh,
VMID ≈ 0.5 × VAVCC
2.2 V
1.1
1.1 ±0.04
3V
1.5
1.5 ±0.04
tVMID(sample)
Sample time required if
channel 11 is selected (6)
ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
2.2 V
1400
3V
1220
(1)
(2)
(3)
(4)
(5)
(6)
2.2 V
30
3V
30
µA
mV
mV/°C
µs
2.2 V
N/A(5)
3V
N/A(5)
µA
V
ns
Limits characterized
The sensor current ISENSOR is consumed if (ADC12ON = 1 and REFON = 1), or (ADC12ON = 1 AND INCH = 0Ah and sample signal is
high). Therefore it includes the constant current through the sensor and the reference.
The temperature sensor offset can be as much as ±20°C. TI recommends a single-point calibration to minimize the offset error of the
built-in temperature sensor.
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on)
No additional current is needed. The VMID is used during sampling.
The on-time tVMID(on) is included in the sampling time tVMID(sample), no additional on time is needed.
8.49 12-Bit DAC Supply Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
AVCC
Analog supply voltage
Supply current, single
DAC channel(1) (2)
IDD
PSRR
(1)
(2)
(3)
(4)
Power-supply rejection
ratio(3) (4)
TEST CONDITIONS
VCC
TA
AVCC = DVCC, AVSS = DVSS = 0 V
MIN
TYP
MAX
2.2
3.6
–40°C to 85°C
50
110
105°C
69
150
50
130
DAC12AMPx = 2, DAC12IR = 0,
DAC12_xDAT = 0x0800
2.2 V, 3 V
DAC12AMPx = 2, DAC12IR = 1,
DAC12_xDAT = 0x0800,
VeREF+ = VREF+ = AVCC
2.2 V, 3 V
DAC12AMPx = 5, DAC12IR = 1,
DAC12_xDAT = 0x0800,
VeREF+ = VREF+= AVCC
2.2 V, 3 V
200
440
DAC12AMPx = 7, DAC12IR = 1,
DAC12_xDAT = 0x0800,
VeREF+ = VREF+ = AVCC
2.2 V, 3 V
700
1500
2.2 V
70
3V
70
DAC12_xDAT = 800h, VREF = 1.5 V,
ΔAVCC = 100 mV
DAC12_xDAT = 800h,
VREF = 1.5 V or 2.5 V,
ΔAVCC = 100 mV
UNIT
V
µA
dB
No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly.
Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input
specifications.
PSRR = 20 × log(ΔAVCC/ΔVDAC12_xOUT)
VREF is applied externally. The internal reference is not used.
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8.50 12-Bit DAC Linearity Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 8-41)
PARAMETER
TEST CONDITIONS
Resolution
Offset voltage without
calibration(1) (2)
EO
Offset voltage with calibration(1) (2)
dE(O)/dT
Offset error temperature coefficient(1)
EG
Gain error(1)
dE(G)/dT
Gain temperature coefficient(1)
tOffset_Cal
Time for offset calibration(3)
TYP
12
2.2 V
±2.0
±8.0
VREF = 2.5 V,
DAC12AMPx = 7, DAC12IR = 1
3V
±2.0
±8.0
2.2 V
±0.4
±1.0
3V
±0.4
±1.0
LSB
LSB
VREF = 1.5 V,
DAC12AMPx = 7, DAC12IR = 1
2.2 V
±21
VREF = 2.5 V,
DAC12AMPx = 7, DAC12IR = 1
3V
±21
VREF = 1.5 V,
DAC12AMPx = 7, DAC12IR = 1
2.2 V
±2.5
VREF = 2.5 V,
DAC12AMPx = 7, DAC12IR = 1
3V
±2.5
mV
2.2 V, 3 V
30
µV/C
VREF = 1.5 V
2.2 V
±3.50
VREF = 2.5 V
3V
±3.50
2.2 V, 3 V
% FSR
ppm of
FSR/°C
10
100
DAC12AMPx = 3, 5
2.2 V, 3 V
32
DAC12AMPx = 4, 6, 7
(2)
(3)
UNIT
bits
DAC12AMPx = 2
(1)
MAX
VREF = 1.5 V,
DAC12AMPx = 7, DAC12IR = 1
VREF = 1.5 V,
Differential nonlinearity(1) (see Figure DAC12AMPx = 7, DAC12IR = 1
8-43)
VREF = 2.5 V,
DAC12AMPx = 7, DAC12IR = 1
DNL
MIN
12-bit monotonic
Integral nonlinearity(1) (see Figure
8-42)
INL
VCC
ms
6
Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients "a" and "b"
of the first-order equation: y = a + b × x. VDAC12_xOUT = EO + (1 + EG) × (VeREF+ / 4095) × DAC12_xDAT, DAC12IR = 1.
The offset calibration works on the output operational amplifier. Offset calibration is triggered setting bit DAC12CALON.
The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with
DAC12AMPx= {0, 1}. The DAC12 module should be configured before initiating calibration. Port activity during calibration may affect
accuracy and is not recommended.
DAC VOUT
DAC Output
VR+
RLoad = ¥
Ideal transfer
function
AVCC
2
CLoad = 100 pF
Offset Error
Positive
Negative
Gain Error
DAC Code
Figure 8-41. Linearity Test Load Conditions, Gain and Offset Definition
54
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
8.51 Typical Characteristics, 12-Bit DAC Linearity Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
4
2.0
INL − Integral Nonlinearity Error − LSB
DNL − Differential Nonlinearity Error − LSB
VCC = 2.2 V, VREF = 1.5V
DAC12AMPx = 7
DAC12IR = 1
3
2
1
0
−1
−2
−3
VCC = 2.2 V, VREF = 1.5V
DAC12AMPx = 7
DAC12IR = 1
1.5
1.0
0.5
0.0
−0.5
−1.0
−1.5
−2.0
−4
0
512
1024
1536
2048
2560
3072
3584
4095
0
512
1024
1536
2048
2560
3072
3584
4095
DAC12_xDAT − Digital Code
DAC12_xDAT − Digital Code
Figure 8-42. Typical INL Error vs Digital Input Data
Figure 8-43. Typical DNL Error vs Digital Input Data
8.52 12-Bit DAC Output Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
No Load, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
Output voltage
Figure 8-44)
VO
range(1)
(see
No Load, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
RLoad = 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
Maximum DAC12 load
capacitance
IL(DAC12)
Maximum DAC12 load current
0
0.005
AVCC –
0.05
AVCC
2.2 V
3V
Output resistance (see Figure
8-44)
RLoad = 3 kΩ, VO/P(DAC12) = AVCC,
DAC12AMPx = 7,
DAC12_xDAT = 0FFFh
2.2 V, 3 V
UNIT
V
0
0.1
AVCC –
0.13
AVCC
100
–0.5
0.5
–1
1
150
250
150
250
1
4
RLoad = 3 kΩ,
0.3 V < VO/P(DAC12) < AVCC – 0.3 V,
DAC12AMPx = 7
(1)
MAX
2.2 V, 3 V
RLoad = 3 kΩ, VO/P(DAC12) = 0 V,
DAC12AMPx = 7, DAC12_xDAT = 0h
RO/P(DAC12)
TYP
2.2 V, 3 V
RLoad = 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
CL(DAC12)
MIN
pF
mA
Ω
Data is valid after the offset calibration of the output amplifier.
RO/P(DAC12_x)
Max
RLoad
ILoad
AVCC
DAC12
2
CLoad = 100 pF
O/P(DAC12_x)
Min
0.3
AVCC − 0.3 V
VOUT
AVCC
Figure 8-44. DAC12_x Output Resistance Tests
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8.53 12-Bit DAC Reference Input Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DAC12IR =
Reference input
voltage range
VeREF+
0(1) (2)
VCC
2.2 V, 3 V
DAC12IR = 1(3) (4)
DAC12_0 IR = DAC12_1 IR = 0
Ri(VREF+),
Ri(VeREF+)
DAC12_0 IR = 0, DAC12_1 IR = 1
2.2 V, 3 V
DAC12_0 IR = DAC12_1 IR = 1,
DAC12_0 SREFx = DAC12_1 SREFx(5)
(1)
(2)
(3)
(4)
(5)
TYP
MAX
AVCC / 3
AVCC + 0.2
AVCC
AVCC + 0.2
20
DAC12_0 IR = 1, DAC12_1 IR = 0
Reference input
resistance
MIN
UNIT
V
MΩ
40
48
56
20
24
28
kΩ
For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / [3 × (1 + EG)].
For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / (1 + EG).
When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel
reducing the reference input resistance.
8.54 12-Bit DAC Dynamic Specifications
VREF = VCC, DAC12IR = 1, over recommended ranges of supply voltage and operating free-air temperature (unless otherwise
noted)
PARAMETER
tON
DAC12 on-time
TEST CONDITIONS
DAC12_xDAT = 800h,
ErrorV(O) < ±0.5 LSB(1) (see
Figure 8-45)
VCC
MIN
DAC12AMPx = 0 → {2, 3, 4}
DAC12AMPx = 0 → {5, 6}
2.2 V, 3 V
Settling time,
full scale
DAC12_xDAT =
80h → F7Fh → 80h
DAC12AMPx = 3, 5
2.2 V, 3 V
DAC12AMPx = 4, 6, 7
tS(C-C)
DAC12_xDAT =
Settling time, code
3F8h → 408h → 3F8h
to code
BF8h → C08h → BF8h
Slew rate(2) (see
Figure 8-46)
SR
DAC12AMPx = 3, 5
BW–3dB
Channel-tochannel
crosstalk(1) (see
Figure 8-48)
(1)
(2)
56
6
12
100
200
40
80
15
30
2
DAC12AMPx = 4, 6, 7
DAC12AMPx = 3, 5
DAC12AMPx = 3, 5
2.2 V, 3 V
0.12
0.35
0.7
1.5
2.7
DAC12_0DAT = 80h ↔ F7Fh, RLoad = 3 kΩ,
DAC12_1DAT = 800h, No load, fDAC12_0OUT = 10 kHz,
Duty cycle = 50%
µs
V/µs
150
nV-s
30
40
2.2 V, 3 V
DAC12AMPx = 7, DAC12SREFx = 2, DAC12IR = 1,
DAC12_xDAT = 800h
DAC12_0DAT = 800h, No load,
DAC12_1DAT = 80h ↔ F7Fh, RLoad = 3 kΩ,
fDAC12_1OUT = 10 kHz, Duty cycle = 50%
µs
600
2.2 V, 3 V
DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2, DAC12IR = 1,
DAC12_xDAT = 800h
DAC12AMPx = {5, 6}, DAC12SREFx = 2, DAC12IR = 1,
DAC12_xDAT = 800h
µs
1
0.05
DAC12AMPx = 4, 6, 7
3-dB bandwidth,
VDC = 1.5 V, VAC
= 0.1 VPP (see
Figure 8-47)
30
UNIT
5
DAC12AMPx = 2
DAC12_xDAT =
80h → F7Fh → 80h
120
15
2.2 V, 3 V
DAC12AMPx = 4, 6, 7
Glitch energy, full
scale
60
DAC12AMPx = 2
DAC12AMPx = 2
DAC12_xDAT =
80h → F7Fh → 80h
MAX
DAC12AMPx = 0 → 7
DAC12AMPx = 2
tS(FS)
TYP
180
kHz
550
–80
2.2 V, 3 V
dB
–80
RLoad and CLoad are connected to AVSS (not AVCC/2) in Figure 8-45.
Slew rate applies to output voltage steps ≥ 200 mV.
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Conversion 1
VOUT
DAC Output
ILoad
RLoad = 3 kΩ
Conversion 2
Conversion 3
±1/2 LSB
Glitch
Energy
AVCC
2
RO/P(DAC12.x)
±1/2 LSB
CLoad = 100 pF
tsettleLH
tsettleHL
Figure 8-45. Settling Time and Glitch Energy Testing
Conversion 1
Conversion 2
Conversion 3
VOUT
90%
90%
10%
10%
tSRHL
tSRLH
Figure 8-46. Slew Rate Testing
ILoad
VeREF+
RLoad = 3 kΩ
AVCC
DAC12_x
2
DACx
AC
CLoad = 100 pF
DC
Figure 8-47. Test Conditions for 3-dB Bandwidth Specification
RLoad
ILoad
AVCC
DAC12_0
2
DAC0
DAC12_xDAT 080h
7F7h
080h
7F7h
080h
V OUT
CLoad = 100 pF
VREF+
V DAC12_yOUT
RLoad
ILoad
AVCC
DAC12_1
V DAC12_xOUT
2
DAC1
fToggle
CLoad = 100 pF
Figure 8-48. Crosstalk Test Conditions
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8.55 Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VCC(PGM/ERASE)
Program and erase supply voltage
2.2
3.6
V
fFTG
Flash timing generator frequency
257
476
kHz
IPGM
Supply current from VCC during program
2.2 V/3.6 V
1
5
mA
IERASE
Supply current from VCC during erase
2.2 V/3.6 V
1
7
mA
10
ms
(1)
tCPT
Cumulative program time
tCMErase
Cumulative mass erase time
2.2 V/3.6 V
2.2 V/3.6 V
20
Program and erase endurance
tRetention
ms
104
105
cycles
Data retention duration
TJ = 25°C
tWord
Word or byte program time
(2)
30
tFTG
tBlock, 0
Block program time for first byte or word
(2)
25
tFTG
tBlock, 1-63
Block program time for each additional
byte or word
(2)
18
tFTG
tBlock, End
Block program end-sequence wait time
(2)
6
tFTG
tMass Erase
Mass erase time
(2)
10593
tFTG
tSeg Erase
Segment erase time
(2)
4819
tFTG
(1)
(2)
100
years
The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
These values are hardwired into the state machine of the flash controller (tFTG = 1/fFTG).
8.56 RAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
V(RAMh)
(1)
RAM retention supply voltage
(1)
TEST CONDITIONS
MIN
CPU halted
MAX
1.6
UNIT
V
This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
8.57 JTAG Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fTCK
TCK input frequency(1)
RInternal
Internal pullup resistance on TMS, TCK, and TDI/TCLK(2)
(1)
(2)
VCC
MIN
TYP
2.2 V
0
5
3V
0
10
2.2 V, 3 V
25
60
MAX
90
UNIT
MHz
kΩ
fTCK may be restricted to meet the timing requirements of the module selected.
TMS, TCK, and TDI/TCLK pullup resistors are implemented in all versions.
8.58 JTAG Fuse
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
VCC(FB)
Supply voltage during fuse-blow condition
VFB
Voltage level on TEST for fuse blow
IFB
Supply current into TEST during fuse blow
tFB
Time to blow fuse
(1)
58
TA
MIN
25°C
2.5
6
MAX
UNIT
V
7
V
100
mA
1
ms
When the fuse is blown, no further access to the JTAG/Test and emulation feature is possible, and JTAG is switched to bypass mode.
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9 Detailed Description
9.1 CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations,
other than program-flow instructions, are performed as register operations in conjunction with seven addressing
modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register
operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant
generator respectively. The remaining registers are general-purpose registers (see Figure 9-1).
Peripherals are connected to the CPU using data, address, and control buses. Peripherals can be manged with
all instructions.
Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
Constant Generator
SR/CG1/R2
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Figure 9-1. CPU Registers
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9.2 Instruction Set
The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can
operate on word and byte data. Table 9-1 lists examples of the three types of instruction formats; Table 9-2 lists
the address modes.
Table 9-1. Instruction Word Formats
INSTRUCTION FORMAT
Dual operands, source and destination
EXAMPLE
OPERATION
ADD R4,R5
R4 + R5 → R5
CALL R8
PC → (TOS), R8 → PC
JNE
Jump-on-equal bit = 0
Single operands, destination only
Relative jump, unconditional or conditional
Table 9-2. Address Mode Descriptions
S(1)
D(1)
Register
✓
✓
MOV Rs,Rd
MOV R10,R11
R10 → R11
Indexed
✓
✓
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
M(2+R5) → M(6+R6)
Symbolic (PC relative)
✓
✓
MOV EDE,TONI
M(EDE) → M(TONI)
Absolute
✓
✓
MOV &MEM,&TCDAT
M(MEM) → M(TCDAT)
Indirect
✓
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) → M(Tab+R6)
Indirect autoincrement
✓
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) → R11
R10 + 2 → R10
Immediate
✓
MOV #X,TONI
MOV #45,TONI
#45 → M(TONI)
ADDRESS MODE
(1)
60
SYNTAX
EXAMPLE
OPERATION
S = source, D = destination
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9.3 Operating Modes
The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt
event can wake the device from any of the five low-power modes, service the request, and restore back to the
low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
•
•
•
•
•
•
Active mode (AM)
– All clocks are active
Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active
– MCLK is disabled
Low-power mode 1 (LPM1)
– CPU is disabled
– ACLK and SMCLK remain active. MCLK is disabled
– DC generator of the DCO is disabled if DCO not used in active mode
Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK and SMCLK are disabled
– DC generator of the DCO remains enabled
– ACLK remains active
Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK and SMCLK are disabled
– DC generator of the DCO is disabled
– ACLK remains active
Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK and SMCLK are disabled
– DC generator of the DCO is disabled
– Crystal oscillator is stopped
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9.4 Interrupt Vector Addresses
The interrupt vectors and the power up starting address are in the address range of 0FFFFh to 0FFC0h. The
vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed) the CPU enters
LPM4 immediately after power up.
Table 9-3. Interrupt Sources
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power up
External reset
Watchdog Timer+
Flash key violation
PC out of range(1)
PORIFG
RSTIFG
WDTIFG
KEYV
See (2)
Reset
0FFFEh
31, highest
NMI
Oscillator fault
Flash memory access violation
NMIIFG
OFIFG
ACCVIFG(2) (6)
(Non)maskable,
(Non)maskable,
(Non)maskable
0FFFCh
30
Timer_B7
TBCCR0 CCIFG(3)
Maskable
0FFFAh
29
Timer_B7
TBCCR1 to TBCCR6 CCIFGs,
TBIFG(2) (3)
Maskable
0FFF8h
28
Comparator_A+
CAIFG
Maskable
0FFF6h
27
Watchdog Timer+
WDTIFG
Maskable
0FFF4h
26
Timer_A3
TACCR0 CCIFG(3)
Maskable
0FFF2h
25
Timer_A3
TACCR1 CCIFG
TACCR2 CCIFG(2) (3)
Maskable
0FFF0h
24
USCI_A0 or USCI_B0 receive
USCI_B0 I2C status
UCA0RXIFG, UCB0RXIFG(2) (4)
Maskable
0FFEEh
23
USCI_A0 or USCI_B0 transmit
USCI_B0 I2C receive or transmit
UCA0TXIFG, UCB0TXIFG(2) (5)
Maskable
0FFECh
22
ADC12
ADC12IFG(2) (3)
Maskable
0FFEAh
21
0FFE8h
20
I/O port P2 (eight flags)
P2IFG.0 to
P2IFG.7(2) (3)
Maskable
0FFE6h
19
I/O port P1 (eight flags)
P1IFG.0 to P1IFG.7(2) (3)
Maskable
0FFE4h
18
UCB1RXIFG(2) (4)
Maskable
0FFE2h
17
USCI_A1 or USCI_B1 transmit
USCI_B1 I2C receive or transmit
UCA1TXIFG, UCB1TXIFG(2) (5)
Maskable
0FFE0h
16
DMA
DMA0IFG, DMA1IFG, DMA2IFG(2) (3)
Maskable
0FFDEh
15
DAC12
DAC12_0IFG, DAC12_1IFG(2) (3)
Maskable
0FFDCh
14
0FFDAh to 0FFC0h
15 to 0, lowest
USCI_A1 or USCI_B1 receive
USCI_B1 I2C status
See (7) (8)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
62
UCA1RXIFG,
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address ranges.
Multiple source flags
Interrupt flags are in the module.
In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.
In UART or SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
The address 0FFBEh is used as bootloader security key (BSLSKEY).
A 0AA55h at this location disables the BSL completely.
A zero disables the erasure of the flash if an invalid password is supplied.
The interrupt vectors at addresses 0FFDAh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
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9.5 Special Function Registers (SFRs)
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
Legend
rw
Bit can be read and written.
rw-0, rw-1
Bit can be read and written. It is Reset or Set by PUC.
rw-(0), rw-(1)
Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device.
Figure 9-2. Interrupt Enable Register 1 (Address = 00h)
7
6
5
4
ACCVIE
rw-0
3
2
1
0
NMIIE
OFIE
WDTIE
rw-0
rw-0
rw-0
Table 9-4. Interrupt Enable Register 1 Description
BIT
FIELD
TYPE
RESET
DESCRIPTION
5
ACCVIE
RW
0h
Flash access violation interrupt enable
4
NMIIE
RW
0h
(Non)maskable interrupt enable
1
OFIE
RW
0h
Oscillator fault interrupt enable
0
WDTIE
RW
0h
Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if
the watchdog timer is configured in interval timer mode.
Figure 9-3. Interrupt Enable Register 2 (Address = 01h)
7
6
5
4
3
2
1
0
UCB0TXIE
UCB0RXIE
UCA0TXIE
UCA0RXIE
rw-0
rw-0
rw-0
rw-0
Table 9-5. Interrupt Enable Register 2 Description
BIT
FIELD
TYPE
RESET
DESCRIPTION
3
UCB0TXIE
RW
0h
USCI_B0 transmit interrupt enable
2
UCB0RXIE
RW
0h
USCI_B0 receive interrupt enable
1
UCA0TXIE
RW
0h
USCI_A0 transmit interrupt enable
0
UCA0RXIE
RW
0h
USCI_A0 receive interrupt enable
Figure 9-4. Interrupt Flag Register 1 (Address = 02h)
7
6
5
4
3
2
1
0
NMIIFG
RSTIFG
PORIFG
OFIFG
WDTIFG
rw-0
rw-(0)
rw-(1)
rw-1
rw-(0)
Table 9-6. Interrupt Flag Register 1 Description
BIT
FIELD
TYPE
RESET
DESCRIPTION
4
NMIIFG
RW
0h
Set by the RST/NMI pin
3
RSTIFG
RW
0h
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset
mode. Reset on VCC power up.
2
PORIFG
RW
1h
Power-on reset interrupt flag. Set on VCC power up.
1
OFIFG
RW
1h
Flag set on oscillator fault.
0
WDTIFG
RW
0h
Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power on or a reset condition at the RST/NMI pin in reset mode.
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Figure 9-5. Interrupt Flag Register 2 (Address = 03h)
7
6
5
4
3
2
1
0
UCB0TXIFG
UCB0RXIFG
UCA0TXIFG
UCA0RXIFG
rw-1
rw-0
rw-1
rw-0
Table 9-7. Interrupt Flag Register 2 Description
BIT
64
FIELD
TYPE
RESET
DESCRIPTION
3
UCB0TXIFG
RW
0h
USCI_B0 transmit interrupt flag
2
UCB0RXIFG
RW
1h
USCI_B0 receive interrupt flag
1
UCA0TXIFG
RW
1h
USCI_A0 transmit interrupt flag
0
UCA0RXIFG
RW
0h
USCI_A0 receive interrupt flag
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9.6 Memory Organization
Table 9-8 summarizes the memory map of each device variant.
Table 9-8. Memory Organization
MSP430F2416
MSP430F2616
Memory
MSP430F2417
MSP430F2617
MSP430F2418
MSP430F2618
MSP430F2419
MSP430F2619
Size
92KB
92KB
116KB
120KB
Main: interrupt vector
Flash
0x0FFFF to 0x0FFC0
0x0FFFF to 0x0FFC0
0x0FFFF to 0x0FFC0
0x0FFFF to 0x0FFC0
Main: code memory
Flash
0x18FFF to 0x02100
0x19FFF to 0x03100
0x1FFFF to 0x03100
0x1FFFF to 0x02100
RAM (total)
Size
4KB
0x020FF to 0x01100
8KB
0x030FF to 0x01100
8KB
0x030FF to 0x01100
4KB
0x020FF to 0x01100
Extended
Size
2KB
0x020FF to 0x01900
6KB
0x030FF to 0x01900
6KB
0x030FF to 0x01900
2KB
0x020FF to 0x01900
Mirrored
Size
2KB
0x018FF to 0x01100
2KB
0x018FF to 0x01100
2KB
0x018FF to 0x01100
2KB
0x018FF to 0x01100
Size
Information memory
256 bytes
256 bytes
256 bytes
256 bytes
Info A
0x010FF to 0x010C0
0x010FF to 0x010C0
0x010FF to 0x010C0
0x010FF to 0x010C0
Info B
0x010BF to 0x01080
0x010BF to 0x01080
0x010BF to 0x01080
0x010BF to 0x01080
Info C
0x0107F to 0x01040
0x0107F to 0x01040
0x0107F to 0x01040
0x0107F to 0x01040
Info D
0x0103F to 0x01000
0x0103F to 0x01000
0x0103F to 0x01000
0x0103F to 0x01000
Size
1KB
1KB
1KB
1KB
ROM
0x00FFF to 0x00C00
0x00FFF to 0x00C00
0x00FFF to 0x00C00
0x00FFF to 0x00C00
Size
2KB
0x009FF to 0x00200
2KB
0x009FF to 0x00200
2KB
0x009FF to 0x00200
2KB
0x009FF to 0x00200
16-bit
0x001FF to 0x00100
0x001FF to 0x00100
0x001FF to 0x00100
0x001FF to 0x00100
8-bit
0x000FF to 0x00010
0x000FF to 0x00010
0x000FF to 0x00010
0x000FF to 0x00010
8-bit SFR
0x0000F to 0x00000
0x0000F to 0x00000
0x0000F to 0x00000
0x0000F to 0x00000
Boot memory
RAM (mirrored at
0x18FF to 0x01100)
Peripherals
9.7 Bootloader (BSL)
The MSP430 BSL lets users program the flash memory or RAM using a UART serial interface. Table 9-9 lists
the BSL pin requirements. Access to memory through the BSL is protected by a user-defined password. For
complete description of the features of the BSL and its implementation, see the MSP430™ Flash Devices
Bootloader (BSL) User's Guide. For design resources to help use the BSL, visit Bootloader (BSL) for MSP
low-power microcontrollers.
Table 9-9. BSL Pin Functions
BSL FUNCTION
PM, PN PACKAGE
PINS
ZCA, ZQW
PACKAGE PINS
Data Transmit
13 - P1.1
H1 - P1.1
Data Receive
22 - P2.2
M3 - P2.2
9.8 Flash Memory
The flash memory can be programmed through the JTAG port, the bootloader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
•
•
•
Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also
called information memory.
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•
•
Segment A contains calibration data. After reset segment A is protected against programming and erasing. It
can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is
required.
Flash content integrity check with marginal read modes
9.9 Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430F2xx, MSP430G2xx Family User's Guide.
9.9.1 DMA Controller (MSP430F261x Only)
The DMA controller allows movement of data from one memory address to another without CPU intervention.
For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using
the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system
power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to or
from a peripheral.
9.9.2 Oscillator and System Clock
The clock system in the MSP430F241x and MSP430F261x family of devices is supported by the basic clock
module that includes support for a 32768-Hz watch crystal oscillator, an internal very low-power low-frequency
oscillator, an internal digitally controlled oscillator (DCO), and a high-frequency crystal oscillator. The basic clock
module is designed to meet the requirements of both low system cost and low power consumption. The internal
DCO provides a fast turnon clock source and stabilizes in less than 1 µs. The basic clock module provides the
following clock signals:
•
•
•
Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.
Main clock (MCLK), the system clock used by the CPU.
Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules.
The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A.
9.9.3 Calibration Data Stored in Information Memory Segment A
Calibration data is stored for the DCO and for the ADC12. It is organized in a tag-length-value (TLV) structure
(see Table 9-10 and Table 9-11).
Table 9-10. Tags Used by the TLV Structure
NAME
ADDRESS
VALUE
TAG_DCO_30
0x10F6
0x01
DCO frequency calibration at VCC = 3 V and TA = 25°C
TAG_ADC12_1
0x10DA
0x08
ADC12_1 calibration tag
–
0xFE
Identifier for empty memory areas
TAG_EMPTY
DESCRIPTION
Table 9-11. Labels Used by the ADC Calibration Structure
ADDRESS
OFFSET
SIZE
CAL_ADC_25T85
0x0010
Word
INCHx = 1010b, REF2_5 = 1, TA = 85°C
CAL_ADC_25T30
0x000E
Word
INCHx = 1010b, REF2_5 = 1, TA = 30°C
CAL_ADC_25VREF_FACTOR
0x000C
Word
REF2_5 = 1, TA = 30°C
CAL_ADC_15T85
0x000A
Word
INCHx = 1010b, REF2_5 = 0, TA = 85°C
CAL_ADC_15T30
0x0008
Word
INCHx = 1010b, REF2_5 = 0, TA = 30°C
CAL_ADC_15VREF_FACTOR
0x0006
Word
REF2_5 = 0, TA = 30°C
CAL_ADC_OFFSET
0x0004
Word
External VREF = 1.5 V, fADC12CLK = 5 MHz
CAL_ADC_GAIN_FACTOR
0x0002
Word
External VREF = 1.5 V, fADC12CLK = 5 MHz
CAL_BC1_1MHZ
0x0009
Byte
–
CAL_DCO_1MHZ
0x0008
Byte
–
CAL_BC1_8MHZ
0x0007
Byte
–
LABEL
66
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CONDITION AT CALIBRATION
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Table 9-11. Labels Used by the ADC Calibration Structure (continued)
ADDRESS
OFFSET
SIZE
CAL_DCO_8MHZ
0x0006
Byte
–
CAL_BC1_12MHZ
0x0005
Byte
–
CAL_DCO_12MHZ
0x0004
Byte
–
CAL_BC1_16MHZ
0x0003
Byte
–
CAL_DCO_16MHZ
0x0002
Byte
–
LABEL
CONDITION AT CALIBRATION
9.9.4 Brownout, Supply Voltage Supervisor (SVS)
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and
power off. The SVS circuitry detects if the supply voltage drops below a user selectable level and supports both
supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM) (the device is
not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not
have ramped to VCC(min) at that time. The user must ensure that the default DCO settings are not changed until
VCC reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).
9.9.5 Digital I/O
Up to eight 8-bit I/O ports are implemented—ports P1 to P8:
•
•
•
•
•
•
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt condition is possible.
Edge-selectable interrupt input capability for all 8 bits of both port P1 and port P2.
Read and write access to port-control registers is supported by all instructions.
Each I/O has an individually programmable pullup or pulldown resistor.
Ports P7 and P8 can be accessed word-wise.
9.9.6 Watchdog Timer (WDT+)
The primary function of the WDT+ module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be disabled or configured as an interval timer and can generate interrupts at
selected time intervals.
9.9.7 Hardware Multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs 16- × 16-bit,
16- × 8-bit, 8- × 16-bit, and 8- × 8-bit operations. The module supports signed and unsigned multiplication as
well as signed and unsigned multiply-and-accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.
9.9.8 Universal Serial Communication Interface (USCI)
The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3-pin or 4-pin) or I2C, and asynchronous combination protocols such
as UART, enhanced UART with automatic baudrate detection (LIN), and IrDA.
The USCI_A module provides support for SPI (3-pin or 4-pin), UART, enhanced UART, and IrDA.
The USCI_B module provides support for SPI (3-pin or 4-pin) and I2C
9.9.9 Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 supports multiple capture/
compares, PWM outputs, and interval timing (see Table 9-12). Timer_A3 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/
compare registers.
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Table 9-12. Timer_A3 Signal Connections
INPUT PIN NUMBER
ZCA, ZQW
PM, PN
DEVICE INPUT
SIGNAL
G2 - P1.0
12 - P1.0
TACLK
MODULE
INPUT NAME
TACLK
ACLK
ACLK
SMCLK
SMCLK
M2 - P2.1
21 - P2.1
TAINCLK
INCLK
H1 - P1.1
13 - P1.1
TA0
CCI0A
M3 - P2.2
22 - P2.2
TA0
CCI0B
DVSS
GND
H2 - P1.2
14 - P1.2
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
NA
CCR0
TA0
OUTPUT PIN NUMBER
PM, PN
ZCA, ZQW
13 - P1.1
H1 - P1.1
17 - P1.5
K1 - P1.5
27 - P2.7
L5 - P2.7
DVCC
VCC
TA1
CCI1A
14 - P1.2
H2 - P1.2
CAOUT
(internal)
CCI1B
18 - P1.6
K2 - P1.6
DVSS
GND
23 - P2.3
L3 - P2.3
DVCC
VCC
CCR1
TA1
ADC12 (internal)
DAC12_0 (internal)
DAC12_1 (internal)
J1 - P1.3
68
15 - P1.3
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TA2
CCI2A
ACLK (internal)
CCI2B
DVSS
GND
DVCC
VCC
CCR2
TA2
15 - P1.3
J1 - P1.3
19 - P1.7
L1 - P1.7
24 - P2.4
L4 - P2.4
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9.9.10 Timer_B7
Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 supports multiple capture/
compares, PWM outputs, and interval timing (see Table 9-13). Timer_B7 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/
compare registers.
Table 9-13. Timer_B3, Timer_B7 Signal Connections
INPUT PIN NUMBER
ZCA, ZQW
PM, PN
DEVICE INPUT
SIGNAL
MODULE
INPUT NAME
K11 - P4.7
43 - P4.7
TBCLK
TBCLK
ACLK
ACLK
SMCLK
SMCLK
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
NA
OUTPUT PIN NUMBER
PM, PN
ZCA, ZQW
M9 - P4.0
K11 - P4.7
43 - P4.7
TBCLK
INCLK
M9 - P4.0
36 - P4.0
TB0
CCI0A
36 - P4.0
TB0
CCI0B
ADC12
(internal)
DVSS
GND
M9- P4.0
36 - P4.0
DVCC
VCC
J9 - P4.1
37 - P4.1
TB1
CCI1A
J9 - P4.1
37 - P4.1
TB1
CCI1B
M10 - P4.2
M10 - P4.2
38 - P4.2
38 - P4.2
CCR0
37 - P4.1
CCR1
39 - P4.3
L10 - P4.3
39 - P4.3
M11 - P4.4
40 - P4.4
M11 - P4.4
40 - P4.4
M12 - P4.5
41 - P4.5
M12 - P4.5
41 - P4.5
L12 - P4.6
42 - P4.6
TB1
DVSS
GND
VCC
TB2
CCI2A
38 - P4.2
TB2
CCI2B
DAC_0
(internal)
DVSS
GND
DVCC
VCC
TB3
CCI3A
TB3
CCI3B
DVSS
GND
DVCC
VCC
TB4
CCI4A
TB4
CCI4B
DVSS
GND
DVCC
VCC
TB5
CCI5A
TB5
CCI5B
DVSS
GND
DVCC
VCC
TB6
CCI6A
ACLK (internal)
CCI6B
DVSS
GND
DVCC
VCC
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CCR3
CCR4
CCR5
CCR6
TB2
J9 - P4.1
ADC12
(internal)
DVCC
CCR2
L10 - P4.3
TB0
M10 - P4.2
DAC_1
(internal)
39 - P4.3
L10 - P4.3
40 - P4.4
M11 - P4.4
41 - P4.5
M12 - P4.5
42 - P4.6
L12 - P4.6
TB3
TB4
TB5
TB6
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
9.9.11 Comparator_A+
The primary function of the Comparator_A+ module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
9.9.12 ADC12
The ADC12 module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The conversionand-control buffer allows the conversion and storage of up to 16 independent ADC samples without any CPU
intervention.
9.9.13 DAC12 (MSP430F261x Only)
The DAC12 module is a 12-bit R-ladder voltage-output digital-to-analog converter (DAC). The DAC12 may be
used in 8-bit or 12-bit mode and may be used with the DMA controller. When multiple DAC12 modules are
present, they may be grouped together for synchronous operation.
9.9.14 Peripheral File Map
Table 9-14 lists the supported registers for each peripheral module.
Table 9-14. Peripherals File Map
MODULE
DMA(1)
ACRONYM
ADDRESS
DMA channel 2 transfer size
REGISTER
DMA2SZ
0x01F2
DMA channel 2 destination address
DMA2DA
0x01EE
DMA channel 2 source address
DMA2SA
0x01EA
DMA channel 2 control
DMA2CTL
0x01E8
DMA channel 1 transfer size
DMA1SZ
0x01E6
DMA channel 1 destination address
DMA1DA
0x01E2
DMA channel 1 source address
DMA1SA
0x01DE
DMA channel 1 control
DMA1CTL
0x01DC
DMA channel 0 transfer size
DMA0SZ
0x01DA
DMA channel 0 destination address
DMA0DA
0x01D6
DMA channel 0 source address
DMA0SA
0x01D2
DMA channel 0 control
DMA0CTL
0x01D0
DMAIV
0x0126
DMACTL1
0x0124
DMA module interrupt vector word
DMA module control 1
DMA module control 0
DMACTL0
0x0122
DAC12_1DAT
0x01CA
DAC12_1 control
DAC12_1CTL
0x01C2
DAC12_0 data
DAC12_0DAT
0x01C8
DAC12_0 control
DAC12_0CTL
0x01C0
DAC12_1 data
DAC12(1)
70
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
Table 9-14. Peripherals File Map (continued)
MODULE
REGISTER
Interrupt vector word
Interrupt enable
ADDRESS
ADC12IV
0x01A8
ADC12IE
0x01A6
ADC12IFG
0x01A4
Control 1
ADC12CTL1
0x01A2
Control 0
ADC12CTL0
0x01A0
Interrupt flag
ADC12
ACRONYM
Conversion memory 15
ADC12MEM15
0x015E
Conversion memory 14
ADC12MEM14
0x015C
Conversion memory 13
ADC12MEM13
0x015A
Conversion memory 12
ADC12MEM12
0x0158
Conversion memory 11
ADC12MEM11
0x0156
Conversion memory 10
ADC12MEM10
0x0154
Conversion memory 9
ADC12MEM9
0x0152
Conversion memory 8
ADC12MEM8
0x0150
Conversion memory 7
ADC12MEM7
0x014E
Conversion memory 6
ADC12MEM6
0x014C
Conversion memory 5
ADC12MEM5
0x014A
Conversion memory 4
ADC12MEM4
0x0148
Conversion memory 3
ADC12MEM3
0x0146
Conversion memory 2
ADC12MEM2
0x0144
Conversion memory 1
ADC12MEM1
0x0142
Conversion memory 0
ADC12MEM0
0x0140
ADC memory control 15
ADC12MCTL15
0x008F
ADC memory control 14
ADC12MCTL14
0x008E
ADC memory control 13
ADC12MCTL13
0x008D
ADC memory control 12
ADC12MCTL12
0x008C
ADC memory control 11
ADC12MCTL11
0x008B
ADC memory control 10
ADC12MCTL10
0x008A
ADC memory control 9
ADC12MCTL9
0x0089
ADC memory control 8
ADC12MCTL8
0x0088
ADC memory control 7
ADC12MCTL7
0x0087
ADC memory control 6
ADC12MCTL6
0x0086
ADC memory control 5
ADC12MCTL5
0x0085
ADC memory control 4
ADC12MCTL4
0x0084
ADC memory control 3
ADC12MCTL3
0x0083
ADC memory control 2
ADC12MCTL2
0x0082
ADC memory control 1
ADC12MCTL1
0x0081
ADC memory control 0
ADC12MCTL0
0x0080
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
Table 9-14. Peripherals File Map (continued)
MODULE
ACRONYM
ADDRESS
Capture/compare 6
REGISTER
TBCCR6
0x019E
Capture/compare 5
TBCCR5
0x019C
Capture/compare 4
TBCCR4
0x019A
Capture/compare 3
TBCCR3
0x0198
Capture/compare 2
TBCCR2
0x0196
Capture/compare 1
TBCCR1
0x0194
Capture/compare 0
TBCCR0
0x0192
Timer_B counter
Timer_B7
TBR
0x0190
Capture/compare control 6
TBCCTL6
0x018E
Capture/compare control 5
TBCCTL5
0x018C
Capture/compare control 4
TBCCTL4
0x018A
Capture/compare control 3
TBCCTL3
0x0188
Capture/compare control 2
TBCCTL2
0x0186
Capture/compare control 1
TBCCTL1
0x0184
Capture/compare control 0
TBCCTL0
0x0182
Timer_B control
TBCTL
0x0180
TBIV
0x011E
Capture/compare 2
TACCR2
0x0176
Capture/compare 1
TACCR1
0x0174
Capture/compare 0
TACCR0
0x0172
TAR
0x0170
Timer_B interrupt vector
Timer_A counter
Timer_A3
Reserved
0x016E
Reserved
0x016C
Reserved
0x016A
Reserved
0x0168
Capture/compare control 2
TACCTL2
0x0166
Capture/compare control 1
TACCTL1
0x0164
Capture/compare control 0
TACCTL0
0x0162
Timer_A control
Timer_A interrupt vector
Sum extend
Hardware
multiplier
0x013E
RESHI
0x013C
Result low word
RESLO
0x013A
Second operand
OP2
0x0138
MACS
0x0136
MAC
0x0134
MPYS
0x0132
MPY
0x0130
Flash control 4
FCTL4
0x01BE
Flash control 3
FCTL3
0x012C
Flash control 2
FCTL2
0x012A
Flash control 1
FCTL1
0x0128
WDTCTL
0x0120
Multiply signed +accumulate/operand 1
Multiply unsigned/operand 1
72
0x012E
SUMEXT
Multiply signed/operand 1
Watchdog
0x0160
TAIV
Result high word
Multiply+accumulate/operand 1
Flash
TACTL
Watchdog Timer control
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
Table 9-14. Peripherals File Map (continued)
MODULE
REGISTER
ACRONYM
ADDRESS
UCA0ABCTL
0x005D
USCI_A0 transmit buffer
UCA0TXBUF
0x0067
USCI_A0 receive buffer
UCA0RXBUF
0x0066
USCI_A0 status
UCA0STAT
0x0065
USCI_A0 modulation control
UCA0MCTL
0x0064
USCI_A0 baud rate control 1
UCA0BR1
0x0063
USCI_A0 baud rate control 0
UCA0BR0
0x0062
USCI_A0 control 1
UCA0CTL1
0x0061
USCI_A0 control 0
UCA0CTL0
0x0060
USCI_A0 auto baud rate control
USCI_A0,
USCI_B0
USCI_A0 IrDA receive control
UCA0IRRCTL
0x005F
USCI_A0 IrDA transmit control
UCA0IRTCLT
0x005E
USCI_B0 transmit buffer
UCB0TXBUF
0x006F
USCI_B0 receive buffer
UCB0RXBUF
0x006E
USCI_B0 status
USCI_A1,
USCI_B1
UCB0STAT
0x006D
USCI_B0 I2C Interrupt enable
UCB0CIE
0x006C
USCI_B0 baud rate control 1
UCB0BR1
0x006B
USCI_B0 baud rate control 0
UCB0BR0
0x006A
USCI_B0 control 1
UCB0CTL1
0x0069
USCI_B0 control 0
UCB0CTL0
0x0068
USCI_B0 I2C slave address
UCB0SA
0x011A
USCI_B0 I2C own address
UCB0OA
0x0118
USCI_A1 auto baud rate control
UCA1ABCTL
0x00CD
USCI_A1 transmit buffer
UCA1TXBUF
0x00D7
USCI_A1 receive buffer
UCA1RXBUF
0x00D6
USCI_A1 status
UCA1STAT
0x00D5
USCI_A1 modulation control
UCA1MCTL
0x00D4
USCI_A1 baud rate control 1
UCA1BR1
0x00D3
USCI_A1 baud rate control 0
UCA1BR0
0x00D2
USCI_A1 control 1
UCA1CTL1
0x00D1
USCI_A1 control 0
UCA1CTL0
0x00D0
USCI_A1 IrDA receive control
UCA1IRRCTL
0x00CF
USCI_A1 IrDA transmit control
UCA1IRTCLT
0x00CE
USCI_B1 transmit buffer
UCB1TXBUF
0x00DF
USCI_B1 receive buffer
UCB1RXBUF
0x00DE
USCI_B1 status
UCB1STAT
0x00DD
USCI_B1 I2C Interrupt enable
UCB1CIE
0x00DC
USCI_B1 baud rate control 1
UCB1BR1
0x00DB
USCI_B1 baud rate control 0
UCB1BR0
0x00DA
USCI_B1 control 1
UCB1CTL1
0x00D9
USCI_B1 control 0
UCB1CTL0
0x00D8
USCI_B1 I2C slave address
UCB1SA
0x017E
USCI_B1 I2C own address
UCB1OA
0x017C
UC1IE
0x0006
UC1IFG
0x0007
USCI_A1/B1 interrupt enable
USCI_A1/B1 interrupt flag
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
Table 9-14. Peripherals File Map (continued)
MODULE
REGISTER
ACRONYM
ADDRESS
CAPD
0x005B
Comparator_A control2
CACTL2
0x005A
Comparator_A control1
CACTL1
0x0059
Basic clock system control 3
BCSCTL3
0x0053
Basic clock system control 2
BCSCTL2
0x0058
Basic clock system control 1
BCSCTL1
0x0057
DCO clock frequency control
DCOCTL
0x0056
SVS control (reset by brownout signal)
SVSCTL
0x0055
Port PA resistor enable
PAREN
0x0014
Port PA selection
PASEL
0x003E
Port PA direction
PADIR
0x003C
Port PA output
PAOUT
0x003A
PAIN
0x0038
Comparator_A port disable
Comparator_A+
Basic clock
Brownout, SVS
Port PA(2)
Port PA input
Port P8(2)
Port P8 resistor enable
P8REN
0x0015
Port P8 selection
P8SEL
0x003F
Port P8 direction
P8DIR
0x003D
Port P8 output
P8OUT
0x003B
Port P8 input
Port P7(2)
P8IN
0x0039
Port P7 resistor enable
P7REN
0x0014
Port P7 selection
P7SEL
0x003E
Port P7 direction
P7DIR
0x003C
Port P7 output
P7OUT
0x003A
P7IN
0x0038
Port P6 resistor enable
P6REN
0x0013
Port P6 selection
P6SEL
0x0037
Port P6 direction
P6DIR
0x0036
Port P6 output
P6OUT
0x0035
Port P7 input
Port P6
Port P6 input
Port P5
P6IN
0x0034
Port P5 resistor enable
P5REN
0x0012
Port P5 selection
P5SEL
0x0033
Port P5 direction
P5DIR
0x0032
Port P5 output
P5OUT
0x0031
Port P5 input
Port P4
P5IN
0x0030
Port P4 selection
P4SEL
0x001F
Port P4 resistor enable
P4REN
0x0011
Port P4 direction
P4DIR
0x001E
Port P4 output
P4OUT
0x001D
P4IN
0x001C
Port P4 input
Port P3
Port P3 resistor enable
P3REN
0x0010
Port P3 selection
P3SEL
0x001B
Port P3 direction
P3DIR
0x001A
Port P3 output
P3OUT
0x0019
P3IN
0x0018
Port P3 input
74
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
Table 9-14. Peripherals File Map (continued)
MODULE
ACRONYM
ADDRESS
Port P2 resistor enable
REGISTER
P2REN
0x002F
Port P2 selection
P2SEL
0x002E
P2IE
0x002D
Port P2 interrupt-edge select
P2IES
0x002C
Port P2 interrupt flag
P2IFG
0x002B
Port P2 direction
P2DIR
0x002A
Port P2 output
P2OUT
0x0029
Port P2 interrupt enable
Port P2
Port P2 input
P2IN
0x0028
Port P1 resistor enable
P1REN
0x0027
Port P1 selection
P1SEL
0x0026
P1IE
0x0025
Port P1 interrupt-edge select
P1IES
0x0024
Port P1 interrupt flag
P1IFG
0x0023
Port P1 direction
P1DIR
0x0022
Port P1 output
P1OUT
0x0021
Port P1 input
P1IN
0x0020
SFR interrupt flag 2
IFG2
0x0003
SFR interrupt flag 1
Port P1 interrupt enable
Port P1
Special functions
(1)
(2)
IFG1
0x0002
SFR interrupt enable 2
IE2
0x0001
SFR interrupt enable 1
IE1
0x0000
MSP430F261x devices only
80-pin PN and 113-pin ZCA or ZQW devices only
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9.10 Port Diagrams
9.10.1 Port P1 (P1.0 to P1.7), Input/Output With Schmitt Trigger
Figure 9-6 shows the port diagram. Table 9-15 summarizes the selection of the pin function.
Pad Logic
P1REN.x
P1DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P1OUT.x
DVSS
P1.0/TACLK/CAOUT
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
P1.5/TA0
P1.6/TA1
P1.7/TA2
P1SEL.x
P1IN.x
EN
Module X IN
D
P1IE.x
EN
P1IRQ.x
Q
Set
P1IFG.x
P1SEL.x
Interrupt
Edge Select
P1IES.x
Figure 9-6. Port P1 (P1.0 to P1.7) Diagram
76
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
Table 9-15. Port P1 (P1.0 to P1.7) Pin Functions
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
0 = Input
1 = Output
0
Timer_A3.TACLK
0
1
CAOUT
1
1
0 = Input
1 = Output
0
Timer_A3.CCI0A
0
1
Timer_A3.TA0
1
1
0 = Input
1 = Output
0
0
1
P1.0 (I/O)
P1.0/TACLK/CAOUT
0
P1.1 (I/O)
P1.1/TA0
1
P1.2 (I/O)
P1.2/TA1
2
Timer_A3.CCI1A
Timer_A3.TA1
P1.3 (I/O)
P1.3/TA2
3
Timer_A3.CCI2A
Timer_A3.TA2
P1.4/SMCLK
4
P1.4 (I/O)
SMCLK
P1.5/TA0
5
P1.5 (I/O)
Timer_A3.TA0
P1.6/TA1
6
P1.6 (I/O)
Timer_A3.TA1
P1.7/TA2
7
CONTROL BITS OR SIGNALS
P1.7 (I/O)
Timer_A3.TA2
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1
1
0 = Input
1 = Output
0
0
1
1
1
0 = Input
1 = Output
0
1
1
0 = Input
1 = Output
0
1
1
0 = Input
1 = Output
0
1
1
0 = Input
1 = Output
0
1
1
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9.10.2 Port P2 (P2.0 to P2.4, P2.6, and P2.7), Input/Output With Schmitt Trigger
Figure 9-7 shows the port diagram. Table 9-16 summarizes the selection of the pin function.
Pad Logic
To
Comparator_A
From
Comparator_A
CAPD.x
P2REN.x
P2DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.x
DVSS
P2.0/ACLK/CA2
P2.1/TAINCLK/CA3
P2.2/CAOUT/TA0/CA4
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.6/ADC12CLK/DMAE0/CA6
P2.7/TA0/CA7
Bus
Keeper
EN
P2SEL.x
P2IN.x
EN
D
Module X IN
P2IE.x
P2IRQ.x
EN
Q
Set
P2IFG.x
P2SEL.x
P2IES.x
Interrupt
Edge
Select
Figure 9-7. Port P2 (P2.0 to P2.4, P2.6, and P2.7) Diagram
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
Table 9-16. Port P2 (P2.0 to P2.4, P2.6, and P2.7) Pin Functions
PIN NAME (P2.x)
P2.0/ACLK/CA2
x
0
FUNCTION
CAPD.x
P2DIR.x
P2SEL.x
P2.0 (I/O)
0
0 = Input
1 = Output
0
ACLK
0
1
1
CA2
1
X
X
P2.1 (I/O)
0
0 = Input
1 = Output
0
0
0
1
0
1
1
1
X
X
0
0 = Input
1 = Output
0
0
1
1
0
0
1
1
X
X
P2.3 (I/O)
0
0 = Input
1 = Output
0
Timer_A3.TA1
0
1
1
CA0
1
X
X
P2.4 (I/O)
0
0 = Input
1 = Output
0
Timer_A3.TA2
0
1
X
CA1
1
X
1
0
0 = Input
1 = Output
0
0
1
1
1 Timer_A3.INCLK
DVSS
P2.1/TAINCLK/CA3
CA3
P2.2 (I/O)
P2.2/CAOUT/TA0/CA4
2 CAOUT
Timer_A3.CCI0B
CA4
P2.3/CA0/TA1
P2.4/CA1/TA2
3
4
P2.6 (I/O)
P2.6/ADC12CLK/
DMAE0(2)/CA6
P2.7/TA0/CA7
(1)
6 ADC12CLK
DMAE0
7
CONTROL BITS OR SIGNALS(1)
0
0
1
CA6
1
X
X
P2.7 (I/O)
0
0 = Input
1 = Output
0
Timer_A3.TA0
0
1
1
CA7
1
X
X
X = Don't care
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
9.10.3 Port P2 (P2.5), Input/Output With Schmitt Trigger
Figure 9-8 shows the port diagram. Table 9-17 summarizes the selection of the pin function.
Pad Logic
To Comparator
From Comparator
CAPD.5
To DCO
in DCO
DCOR
P2REN.5
P2DIR.5
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.5
DVSS
P2.5/ROSC/CA5
Bus
Keeper
EN
P2SEL.x
P2IN.5
EN
Module X IN
D
P2IE.5
P2IRQ.5
EN
Q
Set
P2SEL.5
P2IES.5
Interrupt
Edge
Select
Figure 9-8. Port P2 (P2.5) Diagram
Table 9-17. Port P2 (P2.5) Pin Functions
PIN NAME (P2.x)
x
FUNCTION
DCOR
P2DIR.5
P2SEL.5
0
0
0 = Input
1 = Output
0
(1)
5 ROSC
DVSS
0
1
X
X
0
0
1
1
CA5
1 or selected
0
X
X
P2.5 (I/O)
P2.5/ROSC/CA5
(1)
80
CONTROL BITS OR SIGNALS(1)
CAPD
If ROSC is used, it is connected to an external resistor.
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
9.10.4 Port P3 (P3.0 to P3.7), Input/Output With Schmitt Trigger
Figure 9-9 shows the port diagram. Table 9-18 summarizes the selection of the pin function.
Pad Logic
P3REN.x
P3DIR.x
Module direction
P3OUT.x
Module X OUT
0
DVSS
0
DVCC
1
1
0
1
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
P3.6/UCA1TXD/UCA1SIMO
P3.7/UCA1RXD/UCA1SOMI
P3SEL.x
P3IN.x
EN
Module X IN
1
Direction
0: Input
1: Output
D
Figure 9-9. Port P3 (P3.0 to P3.7) Diagram
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
Table 9-18. Port P3 (P3.0 to P3.7) Pin Functions
PIN NAME (P3.x)
P3.0/UCB0STE/
UCA0CLK
x
0
1
P3.2/UCB0SOMI/
UCB0SCL
2
P3.3/UCB0CLK/
UCA0STE
3
5
82
P3.3 (I/O)
UCB0CLK/UCA0STE(1) (4)
P3.5/UCA0RXD/
UCA0SOMI
(4)
P3.2 (I/O)
UCB0SOMI/UCB0SCL(1) (2)
4
(1)
(2)
(3)
P3.1 (I/O)
UCB0SIMO/UCB0SDA(1) (2)
P3.4/UCA0TXD/
UCA0SIMO
P3.7/UCA1RXD/
UCA1SOMI
P3.0 (I/O)
UCB0STE/UCA0CLK(1) (3)
P3.1/UCB0SIMO/
UCB0SDA
P3.6/UCA1TXD/
UCA1SIMO
FUNCTION
P3.4 (I/O)
UCA0TXD/UCA0SIMO(1)
P3.5 (I/O)
UCA0RXD/UCA0SOMI(1)
6
P3.6 (I/O)
UCA1TXD/UCA1SIMO(1)
7
P3.7 (I/O)
UCA1RXD/UCA1SOMI(1)
CONTROL BITS OR SIGNALS(1)
P3DIR.x
P3SEL.x
0 = Input
1 = Output
0
X
1
0 = Input
1 = Output
0
X
1
0 = Input
1 = Output
0
X
1
0 = Input
1 = Output
0
X
1
0 = Input
1 = Output
0
X
1
0 = Input
1 = Output
0
X
1
0 = Input
1 = Output
0
X
1
0 = Input
1 = Output
0
X
1
The pin direction is controlled by the USCI module.
If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI_B0 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output, USCI_A0 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
9.10.5 Port P4 (P4.0 to P4.7), Input/Output With Schmitt Trigger
Figure 9-10 shows the port diagram. Table 9-19 summarizes the selection of the pin function.
Pad Logic
P4REN.x
P4DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P4OUT.x
DVSS
P4.0/TB0
P4.1/TB1
P4.2/TB2
P4.3/TB3
P4.4/TB4
P4.5/TB5
P4.6/TB6
P4.7/TBCLK
P4SEL.x
P4IN.x
EN
Module X IN
D
Figure 9-10. Port P4 (P4.0 to P4.7) Diagram
Table 9-19. Port P4 (P4.0 to P4.7) Pin Functions
PIN NAME (P4.x)
x
FUNCTION
P4.0 (I/O)
P4.0/TB0
0
Timer_B7.CCI0A and Timer_B7.CCI0B
Timer_B7.TB0
P4.1 (I/O)
P4.1/TB1
1
Timer_B7.CCI1A and Timer_B7.CCI1B
Timer_B7.TB1
2
3
4
5
0
1
1
1
0 = Input
1 = Output
0
0
1
0
Timer_B7.CCI2A and Timer_B7.CCI2B
0
1
Timer_B7.TB2
1
1
0 = Input
1 = Output
0
Timer_B7.CCI3A and Timer_B7.CCI3B
0
1
Timer_B7.TB3
1
1
0 = Input
1 = Output
0
Timer_B7.CCI4A and Timer_B7.CCI4B
0
1
Timer_B7.TB4
1
1
0 = Input
1 = Output
0
Timer_B7.CCI5A and Timer_B7.CCI5B
0
1
Timer_B7.TB5
1
1
P4.5 (I/O)
P4.5/TB5
0
1
P4.4 (I/O)
P4.4/TB4
P4SEL.x
1
P4.3 (I/O)
P4.3/TB3
P4DIR.x
0 = Input
1 = Output
0 = Input
1 = Output
P4.2 (I/O)
P4.2/TB2
CONTROL BITS OR SIGNALS(1)
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
Table 9-19. Port P4 (P4.0 to P4.7) Pin Functions (continued)
PIN NAME (P4.x)
x
FUNCTION
P4DIR.x
P4SEL.x
0 = Input
1 = Output
0
Timer_B7.CCI6A and Timer_B7.CCI6B
0
1
Timer_B7.TB6
1
1
0 = Input
1 = Output
0
0
1
P4.6 (I/O)
P4.6/TB6
P4.7/TBCLK
6
7
P4.7 (I/O)
Timer_B7.TBCLK
84
CONTROL BITS OR SIGNALS(1)
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
9.10.6 Port P5 (P5.0 to P5.7), Input/Output With Schmitt Trigger
Figure 9-11 shows the port diagram. Table 9-20 summarizes the selection of the pin function.
Pad Logic
P5REN.x
P5DIR.x
0
Module
Direction
1
P5OUT.x
0
Module X OUT
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
1
P5.0/UCB1STE/UCA1CLK
P5.1/UCB1SIMO/UCB1SDA
P5.2/UCB1SOMI/UCB1SCL
P5.3/UCB1CLK/UCA1STE
P5.4/MCLK
P5.5/SMCLK
P5.6/ACLK
P5.7/TBOUTH/SVSOUT
P5SEL.x
P5IN.x
EN
Module X IN
D
Figure 9-11. Port P5 (P5.0 to P5.7) Diagram
Table 9-20. Port P5 (P5.0 to P5.7) Pin Functions
PIN NAME (P5.x)
x
P5.0/UCB1STE/
UCA1CLK
0
P5.1/UCB1SIMO/
UCB1SDA
1
FUNCTION
P5.0 (I/O)
UCB1STE/UCA1CLK(1) (1)
P5.1 (I/O)
UCB1SIMO/UCB1SDA(1) (2)
P5.2/UCB1SOMI/
UCB1SCL
2
P5.2 (I/O)
UCB1SOMI/UCB1SCL(1) (2)
P5.3/UCB1CLK/
UCA1STE
3
P5.4/MCLK
4
P5.3 (I/O)
UCB1CLK/UCA1STE(1)
P5.0 (I/O)
MCLK
P5.5/SMCLK
5
6
(1)
7
P5SEL.x
0
X
1
0 = Input
1 = Output
0
X
1
0 = Input
1 = Output
0
X
1
0 = Input
1 = Output
0
X
1
0 = Input
1 = Output
0
1
1
0
1
1
0 = Input
1 = Output
0
1
1
P5.7 (I/O)
0 = Input
1 = Output
0
TBOUTH
0
1
SVSOUT
1
1
P5.1 (I/O)
P5.2 (I/O)
ACLK
P5.7/TBOUTH/SVSOUT
P5DIR.x
0 = Input
1 = Output
0 = Input
1 = Output
SMCLK
P5.6/ACLK
CONTROL BITS OR SIGNALS(1)
UCA1CLK function takes precedence over UCB1STE function. If the pin is required as UCA1CLK input or output, USCI_B1 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
9.10.7 Port P6 (P6.0 to P6.4), Input/Output With Schmitt Trigger
Figure 9-12 shows the port diagram. Table 9-21 summarizes the selection of the pin function.
Pad Logic
ADC12 Ax
P6REN.x
P6DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P6OUT.x
DVSS
P6.0/A0
P6.1/A1
P6.2/A2
P6.3/A3
P6.4/A4
Bus
Keeper
EN
P6SEL.x
P6IN.x
EN
Module X IN
D
Figure 9-12. Port P6 (P6.0 to P6.4) Diagram
Table 9-21. Port P6 (P6.0 to P6.4) Pin Functions
PIN NAME (P6.x)
P6.0/A0
x
0
FUNCTION
P6.0 (I/O)
A0(1)
P6.1/A1
1
P6.1 (I/O)
A1(1)
P6.2/A2
2
P6.2 (I/O)
A2(1)
P6.3/A3
3
P6.3 (I/O)
A3(1)
P6.4/A4
4
P6.4 (I/O)
A4(1)
(1)
86
CONTROL BITS OR SIGNALS(1)
P6DIR.x
P6SEL.x
INCH.x
0 = Input
1 = Output
0
0
X
1
1 (y = 0)
0 = Input
1 = Output
0
0
X
1
1 (y = 1)
0 = Input
1 = Output
0
0
X
1
1 (y = 2)
0 = Input
1 = Output
0
0
X
1
1 (y = 3)
0 = Input
1 = Output
0
0
X
1
1 (y = 4)
The ADC12 channel Ax is connected to AVSS internally if not selected.
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
9.10.8 Port P6 (P6.5 and P6.6), Input/Output With Schmitt Trigger
Figure 9-13 shows the port diagram. Table 9-22 summarizes the selection of the pin function.
Pad Logic
DAC12_0OUT
DAC12AMP > 0
ADC12 Ax
ADC12 Ax
P6REN.x
P6DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P6OUT.x
DVSS
P6.5/A5/DAC1
P6.6/A6/DAC0
Bus
Keeper
EN
P6SEL.x
P6IN.x
EN
Module X IN
D
Figure 9-13. Port P6 (P6.5 and P6.6) Diagram
Table 9-22. Port P6 (P6.5 and P6.6) Pin Functions
PIN NAME (P6.x)
x
FUNCTION
P6.5 (I/O)
P6.5/A5/DAC1(2)
5 DVSS
A5(1)
DAC1 (DAC12OPS = 1)(1)
P6.6 (I/O)
P6.6/A6/DAC0(2)
6 DVSS
A6(1)
DAC0 (DAC12OPS = 0)(1)
(1)
(2)
CONTROL BITS OR SIGNALS(1)
P6DIR.x
P6SEL.x
DAC12AMP > 0
INCH.y
0 = Input
1 = Output
0
0
0
1
1
0
0
X
X
0
1 (y = 5)
X
X
1
0
0 = Input
1 = Output
0
0
0
1
1
0
0
X
X
0
1 (y = 6)
X
X
1
0
The DAC outputs are floating if not selected.
MSP430F261x devices only
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
9.10.9 Port P6 (P6.7), Input/Output With Schmitt Trigger
Figure 9-14 shows the port diagram. Table 9-23 summarizes the selection of the pin function.
Pad Logic
to SVS Mux
VLD = 15
DAC12_0OUT
DAC12AMP > 0
ADC12 A7
from ADC12
P6REN.7
P6DIR.7
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P6OUT.7
DVSS
P6.7/A7/DAC1/SVSIN
Bus
Keeper
EN
P6SEL.7
P6IN.7
EN
Module X IN
D
Figure 9-14. Port P6 (P6.7) Diagram
Table 9-23. Port P6 (P6.7) Pin Functions
PIN NAME (P6.x)
x
FUNCTION
P6DIR.x
P6SEL.x
INCH.y
DAC12AMP>0
0 = Input
1 = Output
0
0
0
DVSS
1
1
0
0
A7(1)
X
1
1 (y = 7)
0
X
1
0
1
X
1
0
0
P6.7 (I/O)
P6.7/A7/DAC1(2)/
SVSIN(2)
7
DAC1 (DAC12OPS =
SVSIN (VLD = 15)
88
CONTROL BITS OR SIGNALS(1)
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
9.10.10 Port P7 (P7.0 to P7.7), Input/Output With Schmitt Trigger
Port P7 is available on 80-pin PN and 113-pin ZCA or ZQW devices only.
Figure 9-15 shows the port diagram. Table 9-24 summarizes the selection of the pin function.
Pad Logic
P7REN.x
P7DIR.x
0
0
1
P7OUT.x
0
VSS
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7
P7SEL.x
P7IN.x
EN
D
Module X IN
Figure 9-15. Port P7 (P7.0 to P7.7) Diagram
Table 9-24. Port P7 (P7.0 to P7.7) Pin Functions
PIN NAME (P7.x)
P7.0
x
0
FUNCTION
P7.0 (I/O)
Input
P7.1
1
P7.1 (I/O)
Input
P7.2
2
P7.2 (I/O)
Input
P7.3
3
P7.3 (I/O)
Input
P7.4
4
P7.4 (I/O)
Input
P7.5
5
P7.5 (I/O)
Input
P7.6
6
P7.6 (I/O)
Input
P7.7
7
P7.7 (I/O)
Input
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CONTROL BITS OR SIGNALS(1)
P7DIR.x
P7SEL.x
0 = Input
1 = Output
0
X
1
0 = Input
1 = Output
0
X
1
0 = Input
1 = Output
0
X
1
0 = Input
1 = Output
0
X
1
0 = Input
1 = Output
0
X
1
0 = Input
1 = Output
0
X
1
0 = Input
1 = Output
0
X
1
0 = Input
1 = Output
0
X
1
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SLAS541M – JUNE 2007 – REVISED MARCH 2022
9.10.11 Port P8 (P8.0 to P8.5), Input/Output With Schmitt Trigger
Port P8 is available on 80-pin PN and 113-pin ZCA or ZQW devices only.
Figure 9-16 shows the port diagram. Table 9-25 summarizes the selection of the pin function.
Pad Logic
P8REN.x
P8DIR.x
0
0
1
P8OUT.x
0
VSS
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P8.0
P8.1
P8.2
P8.3
P8.4
P8.5
P8SEL.x
P8IN.x
EN
Module X IN
D
Figure 9-16. Port P8 (P8.0 to P8.5) Diagram
Table 9-25. Port P8 (P8.0 to P8.5) Pin Functions
PIN NAME (P8.x)
P8.0
x
0
FUNCTION
P8.0 (I/O)
Input
P8.1
1
P8.1 (I/O)
Input
P8.2
2
P8.2 (I/O)
Input
P8.3
3
P8.3 (I/O)
Input
P8.4
4
P8.4 (I/O)
Input
P8.5
5
P8.5 (I/O)
Input
90
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CONTROL BITS OR SIGNALS(1)
P8DIR.x
P8SEL.x
0 = Input
1 = Output
0
X
1
0 = Input
1 = Output
0
X
1
0 = Input
1 = Output
0
X
1
0 = Input
1 = Output
0
X
1
0 = Input
1 = Output
0
X
1
0 = Input
1 = Output
0
X
1
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9.10.12 Port P8 (P8.6), Input/Output With Schmitt Trigger
Port P8 is available on 80-pin PN and 113-pin ZCA or ZQW devices only.
Figure 9-17 shows the port diagram. Table 9-26 summarizes the selection of the pin function.
BCSCTL3.XT2Sx = 11
0
XT2CLK
1
From
P8.7/XIN
P8.7/XT2IN
XT2 off
Pad Logic
P8SEL.7
P8REN.6
P8DIR.6
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P8OUT.6
DVSS
P8.6/XT2OUT
Bus
Keeper
EN
P8SEL.6
P8IN.6
EN
Module X IN
D
Figure 9-17. Port P8 (P8.6) Diagram
Table 9-26. Port P8 (P8.6) Pin Functions
PIN NAME (P8.x)
x
FUNCTION
P8DIR.x
P8SEL.x
0 = Input
1 = Output
0
XT2OUT (default)
0
1
DVSS
1
1
P8.6 (I/O)
P8.6/XT2OUT
6
CONTROL BITS OR SIGNALS
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9.10.13 Port P8 (P8.7), Input/Output With Schmitt Trigger
Port P8 is available on 80-pin PN and 113-pin ZCA or ZQW devices only.
Figure 9-18 shows the port diagram. Table 9-27 summarizes the selection of the pin function.
BCSCTL3.XT2Sx = 11
P8.6/XT2OUT
XT2 off
0
XT2CLK
1
Pad Logic
P8SEL.6
P8REN.7
0
P8DIR.7
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P8OUT.7
DVSS
P8.7/XT2IN
P8SEL.7
Bus
Keeper
EN
P8IN.7
EN
D
Module X IN
Figure 9-18. Port P8 (P8.7) Diagram
Table 9-27. Port P8 (P8.7) Pin Functions
PIN NAME (P8.x)
x
FUNCTION
P8DIR.x
P8SEL.x
0 = Input
1 = Output
0
XT2IN (default)
0
1
VSS
1
1
P8.7 (I/O)
P8.7/XT2IN
92
7
CONTROL BITS OR SIGNALS
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9.10.14 JTAG Pins (TMS, TCK, TDI/TCLK, TDO/TDI) Input/Output With Schmitt Trigger
Figure 9-19 shows the port diagram.
TDO
Controlled by JTAG
Controlled by JTAG
JTAG
TDO/TDI
Controlled
by JTAG
DVCC DVCC
TDI
Fuse
Burn and Test
Fuse
Test
and
Emulation
Module
TDI/TCLK
DVCC
TMS
TMS
DVCC
TCK
TCK
During programming activity and during blowing of the fuse, pin TDO/TDI is used to apply
the test input data for JTAG circuitry.
Figure 9-19. JTAG Pins (TMS, TCK, TDI/TCLK, TDO/TDI) Diagram
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9.10.15 JTAG Fuse Check Mode
MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the
fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current
(ITF) of 1 mA at 3 V or 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Take care to
avoid accidentally activating the fuse check mode and increasing overall system power consumption.
When the TEST pin is again taken low after a test or programming session, the fuse check mode and sense
currents are terminated.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS
is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode.
After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR, the fuse
check mode has the potential to be activated.
The fuse check current flows only when the fuse check mode is active and the TMS pin is in a low state
(see Figure 9-20). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
Time TMS Goes Low After POR
TMS
ITF
ITDI/TCLK
Figure 9-20. Fuse Check Mode Current
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10 Device and Documentation Support
10.1 Getting Started
For more information on the MSP430 family of devices and the tools and libraries that are available to help with
your development, visit the MSP430™ ultra-low-power sensing & measurement MCUs overview.
10.2 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP
MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS. These
prefixes represent evolutionary stages of product development from engineering prototypes (XMS) through fully
qualified production devices (MSP).
XMS – Experimental device that is not necessarily representative of the final device's electrical specifications
MSP – Fully qualified production device
XMS devices are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated
fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices.
TI recommends that these devices not be used in any production system because their expected end-use failure
rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature
range, package type, and distribution format. Figure 10-1 provides a legend for reading the complete device
name.
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MSP 430 F 5 438 A I PM T -EP
Processor Family
Optional: Additional Features
MCU Platform
Optional: Tape and Reel
Device Type
Packaging
Series
Feature Set
Processor Family
MCU Platform
Optional: Temperature Range
Optional: Revision
CC = Embedded RF Radio
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
430 = MSP430 low-power microcontroller platform
Device Type
Memory Type
C = ROM
F = Flash
FR = FRAM
G = Flash
L = No nonvolatile memory
Specialized Application
AFE = Analog front end
BQ = Contactless power
CG = ROM medical
FE = Flash energy meter
FG = Flash medical
FW = Flash electronic flow meter
Series
1 = Up to 8 MHz
2 = Up to 16 MHz
3 = Legacy
4 = Up to 16 MHz with LCD driver
5 = Up to 25 MHz
6 = Up to 25 MHz with LCD driver
0 = Low-voltage series
Feature Set
Various levels of integration within a series
Optional: Revision
Updated version of the base part number
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging
http://www.ti.com/packaging
Optional: Tape and Reel
T = Small reel
R = Large reel
No markings = Tube or tray
Optional: Additional Features -EP = Enhanced product (–40°C to 105°C)
-HT = Extreme temperature parts (–55°C to 150°C)
-Q1 = Automotive Q100 qualified
Figure 10-1. Device Nomenclature
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10.3 Tools and Software
Table 10-1 lists the debug features supported by the MSP430F261x and MSP430F241x microcontrollers. See
the Code Composer Studio IDE for MSP430 MCUs User's Guide for details on the available features.
Table 10-1. Hardware Features
MSP430
ARCHITECTURE
4-WIRE
JTAG
2-WIRE
JTAG
BREAKPOINTS
(N)
RANGE
BREAKPOINTS
CLOCK
CONTROL
STATE
SEQUENCER
TRACE
BUFFER
MSP430X
Yes
No
8
Yes
Yes
Yes
Yes
Design Kits and Evaluation Modules
64-pin Target Development Board and MSP-FET Programmer Bundle - MSP430F1x, MSP430F2x, MSP430F4x
MCUs
The MSP-FET430U64 is a powerful flash emulation tool that includes the hardware and software required
to quickly begin application development on the MSP430 MCU. It includes a ZIF socket target board (MSPTS430PM64) and a USB debugging interface (MSP-FET) used to program and debug the MSP430 in-system
through the JTAG interface or the pin-saving Spy-Bi-Wire (2-wire JTAG) protocol. The flash memory can be
erased and programmed in seconds with only a few keystrokes, and because the MSP430 flash is ultra-low
power, no external power supply is required.
80-pin Target Development Board and MSP-FET Programmer Bundle for MSP430F2x and MSP430F4x MCUs
The MSP-FET430U80 is a powerful flash emulation tool that includes the hardware and software required to
quickly begin application development on the MSP430 MCU. It includes a ZIF socket target board and a USB
debugging interface (MSP-FET) used to program and debug the MSP430 in-system through the JTAG interface
or the pin-saving Spy-Bi-Wire (2-wire JTAG) protocol. The flash memory can be erased and programmed in
seconds with only a few keystrokes, and because the MSP430 flash is ultra-low power, no external power supply
is required.
Software
MSP430F241x, MSP430F261x Code Examples
C code examples are available for every MSP device that configures each of the integrated peripherals for
various application needs.
MSPWare Software
MSPWare software is a collection of code examples, data sheets, and other design resources for all MSP
devices delivered in a convenient package. In addition to providing a complete collection of existing MSP design
resources, MSPWare software also includes a high-level API called MSP Driver Library. This library makes it
easy to program MSP hardware. MSPWare software is available as a component of CCS or as a stand-alone
package.
MSP Driver Library
The abstracted API of MSP Driver Library provides easy-to-use function calls that free you from directly
manipulating the bits and bytes of the MSP430 hardware. Thorough documentation is delivered through a helpful
API Guide, which includes details on each function call and the recognized parameters. Developers can use
Driver Library functions to write complete projects with minimal overhead.
MSP EnergyTrace Technology
EnergyTrace technology for MSP430 microcontrollers is an energy-based code analysis tool that measures and
displays the energy profile of the application and helps to optimize it for ultra-low power consumption.
ULP (Ultra-Low Power) Advisor
ULP Advisor™ software is a tool for guiding developers to write more efficient code to fully use the unique ultralow-power features of MSP and MSP432 microcontrollers. Aimed at both experienced and new microcontroller
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developers, ULP Advisor checks your code against a thorough ULP checklist to help minimize the energy
consumption of your application. At build time, ULP Advisor provides notifications and remarks to highlight areas
of your code that can be further optimized for lower power.
Fixed Point Math Library for MSP
The MSP IQmath and Qmath Libraries are a collection of highly optimized and high-precision mathematical
functions for C programmers to seamlessly port a floating-point algorithm into fixed-point code on MSP430 and
MSP432 devices. These routines are typically used in computationally intensive real-time applications where
optimal execution speed, high accuracy, and ultra-low energy are critical. By using the IQmath and Qmath
libraries, it is possible to achieve execution speeds considerably faster and energy consumption considerably
lower than equivalent code written using floating-point math.
Development Tools
Code Composer Studio™ Integrated Development Environment for MSP Microcontrollers
Code Composer Studio (CCS) integrated development environment (IDE) supports all MSP microcontroller
devices. CCS comprises a suite of embedded software utilities used to develop and debug embedded
applications. CCS includes an optimizing C/C++ compiler, source code editor, project build environment,
debugger, profiler, and many other features.
MSPWare Software
MSPWare software is a collection of code examples, data sheets, and other design resources for all MSP
devices delivered in a convenient package. In addition to providing a complete collection of existing MSP design
resources, MSPWare software also includes a high-level API called MSP Driver Library. This library makes it
easy to program MSP hardware. MSPWare software is available as a component of CCS or as a stand-alone
package.
Command-Line Programmer
MSP Flasher is an open-source shell-based interface for programming MSP microcontrollers through a FET
programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP Flasher can download binary
files (.txt or .hex) directly to the MSP microcontroller without an IDE.
MSP MCU Programmer and Debugger
The MSP-FET is a powerful emulation development tool – often called a debug probe – which lets users quickly
begin application development on MSP low-power MCUs. Creating MCU software usually requires downloading
the resulting binary program to the MSP device for validation and debugging.
MSP-GANG Production Programmer
The MSP Gang Programmer is an MSP430 or MSP432 device programmer that can program up to eight
identical MSP430 or MSP432 flash or FRAM devices at the same time. The MSP Gang Programmer connects
to a host PC using a standard RS-232 or USB connection and provides flexible programming options that let the
user fully customize the process.
10.4 Documentation Support
The following documents describe the MSP430F261x and MSP430F241x MCUs. Copies of these documents
are available on the Internet at www.ti.com.
Receiving Notification of Document Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for your
device on ti.com (for example, MSP430F2619). In the upper right corner, click the "Alert me" button. This
registers you to receive a weekly digest of product information that has changed (if any). For change details,
check the revision history of any revised document.
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Errata
MSP430F2619 Microcontroller Errata
Describes the known exceptions to the functional specifications.
MSP430F2618 Microcontroller Errata
Describes the known exceptions to the functional specifications.
MSP430F2617 Microcontroller Errata
Describes the known exceptions to the functional specifications.
MSP430F2616 Microcontroller Errata
Describes the known exceptions to the functional specifications.
MSP430F2419 Microcontroller Errata
Describes the known exceptions to the functional specifications.
MSP430F2418 Microcontroller Errata
Describes the known exceptions to the functional specifications.
MSP430F2417 Microcontroller Errata
Describes the known exceptions to the functional specifications.
MSP430F2416 Microcontroller Errata
Describes the known exceptions to the functional specifications.
User's Guides
MSP430F2xx, MSP430G2xx Family User's Guide
Detailed description of all modules and peripherals available in this device family.
MSP430 Programming With the JTAG Interface
This document describes the functions that are required to erase, program, and verify the memory module
of the MSP430 flash-based and FRAM-based microcontroller families using the JTAG communication port. In
addition, it describes how to program the JTAG access security fuse that is available on all MSP430 devices.
This document describes device access using both the standard 4-wire JTAG interface and the 2-wire JTAG
interface, which is also referred to as Spy-Bi-Wire (SBW).
MSP430 Flash Device Bootloader (BSL) User's Guide
The MSP430 BSL lets users communicate with embedded memory in the MSP430 MCU during the prototyping
phase, final production, and in service. Both the programmable memory (flash memory) and the data memory
(RAM) can be modified as required.
MSP430 Hardware Tools User's Guide
This manual describes the hardware of the TI MSP-FET430 Flash Emulation Tool (FET). The FET is the
program development tool for the MSP430 ultra-low-power microcontroller. Both available interface types, the
parallel port interface and the USB interface, are described.
Application Reports
MSP430 32-kHz Crystal Oscillators
Selection of the right crystal, correct load circuit, and proper board layout are important for a stable crystal
oscillator. This application report summarizes crystal oscillator function and explains the parameters to select the
correct crystal for MSP430 ultra-low-power operation. In addition, hints and examples for correct board layout
are given. The document also contains detailed information on the possible oscillator tests to ensure stable
oscillator operation in mass production.
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MSP430 System-Level ESD Considerations
System-level ESD has become increasingly demanding with silicon technology scaling towards lower voltages
and the need for designing cost-effective and ultra-low-power components. This application report addresses
three different ESD topics to help board designers and OEMs understand and design robust system-level
designs.
Understanding MSP430 Flash Data Retention
The MSP430 family of microcontrollers, as part of its broad portfolio, offers both read-only memory (ROM)-based
and flash-based devices. Understanding the MSP430 flash is extremely important for efficient, robust, and
reliable system design. Data retention is one of the key aspects to flash reliability. In this application report, data
retention for the MSP430 flash is discussed in detail and the effect of temperature is given primary importance.
Interfacing the 3-V MSP430 to 5-V Circuits
The interfacing of the 3-V MSP430x1xx and MSP430x4xx microcontroller families to circuits with a supply of 5 V
or higher is shown. Input, output and I/O interfaces are given and explained. Worse-case design equations are
provided, where necessary. Some simple power supplies generating both voltages are shown, too.
Efficient Multiplication and Division Using MSP430
Multiplication and division in the absence of a hardware multiplier require many instruction cycles, especially in
C. This report discusses a method that does not need a hardware multiplier and can perform multiplication and
division with only shift and add instructions. The method described in this application report is based on Horner's
method.
10.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
MSP Academy is a starting point for all developers to learn about the MSP430 MCU Platform, which provides
affordable solutions for many applications. MSP Academy delivers easy-to-use training modules that span a
wide range of topics and LaunchPad development kits in the MSP430 MCU portfolio.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.6 Trademarks
MSP430™, MicroStar Junior™, ULP Advisor™, Code Composer Studio™, and TI E2E™ are trademarks of Texas
Instruments.
All trademarks are the property of their respective owners.
10.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.8 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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13-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
MSP430F2416TPM
ACTIVE
LQFP
PM
64
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
M430F2416T
MSP430F2416TPMR
ACTIVE
LQFP
PM
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
M430F2416T
MSP430F2416TPN
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
M430F2416T
MSP430F2416TPNR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
M430F2416T
MSP430F2416TZCA
ACTIVE
NFBGA
ZCA
113
260
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 105
F2416T
MSP430F2416TZCAR
ACTIVE
NFBGA
ZCA
113
2500
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 105
F2416T
MSP430F2417TPM
ACTIVE
LQFP
PM
64
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
M430F2417T
MSP430F2417TPMR
ACTIVE
LQFP
PM
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
M430F2417T
MSP430F2417TPN
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
M430F2417T
MSP430F2417TPNR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
M430F2417T
MSP430F2417TZCAR
ACTIVE
NFBGA
ZCA
113
2500
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 105
F2417T
MSP430F2418TPM
ACTIVE
LQFP
PM
64
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
M430F2418T
MSP430F2418TPMR
ACTIVE
LQFP
PM
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
M430F2418T
MSP430F2418TPN
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
M430F2418T
MSP430F2418TPNR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
M430F2418T
MSP430F2418TZCA
ACTIVE
NFBGA
ZCA
113
260
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 105
F2418T
MSP430F2418TZCAR
ACTIVE
NFBGA
ZCA
113
2500
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 105
F2418T
MSP430F2419TPM
ACTIVE
LQFP
PM
64
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
M430F2419T
MSP430F2419TPMR
ACTIVE
LQFP
PM
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
M430F2419T
MSP430F2419TPN
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
M430F2419T
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
13-Apr-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
MSP430F2419TPNR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
M430F2419T
MSP430F2616TPM
ACTIVE
LQFP
PM
64
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
M430F2616T
MSP430F2616TPMR
ACTIVE
LQFP
PM
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
M430F2616T
MSP430F2616TPN
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
M430F2616T
MSP430F2616TPNR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
M430F2616T
MSP430F2616TZCA
ACTIVE
NFBGA
ZCA
113
260
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 105
F2616T
MSP430F2616TZCAR
ACTIVE
NFBGA
ZCA
113
2500
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 105
F2616T
MSP430F2617TPM
ACTIVE
LQFP
PM
64
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
M430F2617T
MSP430F2617TPMR
ACTIVE
LQFP
PM
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
M430F2617T
MSP430F2617TPN
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
M430F2617T
MSP430F2617TPNR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
M430F2617T
MSP430F2617TZCA
ACTIVE
NFBGA
ZCA
113
260
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 105
F2617T
MSP430F2617TZCAR
ACTIVE
NFBGA
ZCA
113
2500
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 105
F2617T
MSP430F2618TPM
ACTIVE
LQFP
PM
64
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
M430F2618T
MSP430F2618TPMR
ACTIVE
LQFP
PM
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
M430F2618T
MSP430F2618TPN
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
M430F2618T
MSP430F2618TPNR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
M430F2618T
MSP430F2618TZCA
ACTIVE
NFBGA
ZCA
113
260
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 105
F2618T
MSP430F2618TZCAR
ACTIVE
NFBGA
ZCA
113
2500
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 105
F2618T
MSP430F2619TPM
ACTIVE
LQFP
PM
64
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
M430F2619T
REV #
MSP430F2619TPMR
ACTIVE
LQFP
PM
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
M430F2619T
REV #
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
13-Apr-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
MSP430F2619TPN
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
M430F2619T
MSP430F2619TPNR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
M430F2619T
MSP430F2619TZCA
ACTIVE
NFBGA
ZCA
113
260
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 105
F2619T
MSP430F2619TZCAR
ACTIVE
NFBGA
ZCA
113
2500
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 105
F2619T
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of