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MSP430F479, MSP430F478, MSP430F477
SLAS629B – MARCH 2009 – REVISED MAY 2020
MSP430F47x Mixed-Signal Microcontrollers
1 Device Overview
1.1
Features
1
• Low supply-voltage range: 1.8 V to 3.6 V
• Ultra-low power consumption
– Active mode: 262 µA at 1 MHz, 2.2 V
– Standby mode: 1.1 µA
– Off mode (RAM retention): 0.1 µA
• Five power-saving modes
• Wakeup from standby mode in less than 6 µs
• 16-bit RISC architecture, extended memory,
125‑ns instruction cycle time
• 16-bit sigma-delta analog-to-digital converter
(ADC) with internal reference and five differential
analog inputs
• One 12-bit digital-to-analog converter (DAC)
• 16-bit Timer_A with three capture/compare
registers
• 16-bit Timer_B with seven capture/compare-withshadow registers
• Two universal serial communication interfaces
(USCIs)
– USCI_A0
– Enhanced UART supports automatic baudrate detection
– IrDA encoder and decoder
– Synchronous SPI
1.2
•
•
•
•
•
•
•
•
•
•
•
•
Applications
Analog and digital sensor systems
Digital motor control
Remote controls
1.3
•
– USCI_B0
– I2C
– Synchronous SPI
Integrated LCD driver up to 160 segments with
regulated charge pump
Brownout detector
Basic timer with real-time clock (RTC) feature
Supply voltage supervisor and monitor with
programmable level detection
On-Chip Comparator
Serial onboard programming, programmable code
protection by security fuse
Bootloader
On chip emulation module
Device Comparison summarizes the available
family members
– MSP430F477: 32KB + 256 bytes of flash,
2KB of RAM
– MSP430F478: 48KB + 256 bytes of flash,
2KB of RAM
– MSP430F479: 60KB + 256 bytes of flash,
2KB of RAM
Available in 113-ball MicroStar Junior™ BGA
(ZQW), 113-ball nFBGA (ZCA), and 80-pin QFP
(PN) packages (see Device Comparison)
•
•
•
Thermostats
Digital timers
Hand-held meters
Description
The Texas Instruments MSP430™ family of ultra-low-power microcontrollers consists of several devices
featuring different sets of peripherals targeted for various applications. The architecture, combined with
five low-power modes, is optimized to achieve extended battery life in portable measurement applications.
The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute
to maximum code efficiency.The digitally controlled oscillator (DCO) allows wake-up from low-power
modes to active mode in less than 6 µs.
The MSP430F47x is a microcontroller configuration with two 16-bit timers, a basic timer with a real-time
clock, a high-performance 16-bit sigma-delta A/D converter, single 12-bit D/A converter, two universal
serial communication interface, 48 I/O pins, and a liquid crystal display driver.
For complete module descriptions, see the MSP430x4xx Family User’s Guide.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430F479, MSP430F478, MSP430F477
SLAS629B – MARCH 2009 – REVISED MAY 2020
www.ti.com
Device Information (1)
PART NUMBER
MSP430F479IPN
MSP430F479IZCA
MSP430F479IZQW (3)
(1)
(2)
(3)
1.4
PACKAGE
BODY SIZE (2)
LQFP (80)
12 mm × 12 mm
nFBGA (113)
7 mm × 7 mm
MicroStar Junior™ BGA (113)
7 mm × 7 mm
For the most current part, package, and ordering information for all available devices, see the Package
Option Addendum in Section 8, or see the TI website at www.ti.com.
The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 8.
All orderable part numbers in the ZQW (MicroStar Junior BGA) package have been changed to a
status of Last Time Buy. Visit the Product life cycle page for details on this status.
Functional Block Diagram
Figure 1-1 shows the functional block diagram.
Figure 1-1. Functional Block Diagram
2
Device Overview
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SLAS629B – MARCH 2009 – REVISED MAY 2020
Table of Contents
1
2
3
Device Overview ......................................... 1
1.1
Features .............................................. 1
1.2
Applications ........................................... 1
1.3
Description ............................................ 1
1.4
Functional Block Diagram ............................ 2
Revision History ......................................... 4
Device Comparison ..................................... 5
3.1
4
5
5.28
Related Products ..................................... 5
Terminal Configuration and Functions .............. 6
4.1
Pin Diagrams ......................................... 6
4.2
Signal Descriptions ................................... 8
Specifications ........................................... 12
5.1
5.2
5.3
5.4
5.5
........................
ESD Ratings ........................................
Recommended Operating Conditions ...............
Absolute Maximum Ratings
12
12
13
Supply Current Into AVCC and DVCC Excluding
External Current .................................... 14
Schmitt-Trigger Inputs – Ports P1 to P6, RST/NMI,
JTAG (TCK, TMS, TDI/TCLK,TDO/TDI) ............ 15
5.6
Inputs Px.y, TAx ..................................... 15
5.7
.................
Outputs – Ports P1 to P6 ...........................
Output Frequency ...................................
Typical Characteristics – Outputs ...................
Wake-up Timing From LPM3 .......................
POR – Brownout Reset (BOR)......................
SVS (Supply Voltage Supervisor and Monitor) .....
DCO .................................................
Crystal Oscillator, LFXT1, Low-Frequency Mode ...
Crystal Oscillator, LFXT1, High-Frequency Mode ..
5.8
5.9
5.10
5.11
5.12
5.13
5.14
5.15
5.16
5.17
Leakage Current – Ports P1 to P6
15
16
16
17
18
18
20
22
24
25
Crystal Oscillator, XT2 Oscillator, High-Frequency
Mode ................................................ 25
5.18
RAM ................................................. 25
5.19
LCD_A ............................................... 26
5.20
Comparator_A
5.21
5.22
5.23
5.24
5.25
5.26
5.27
......................................
Typical Characteristics – Comparator_A ............
6
7
27
28
SD16_A, Power Supply and Recommended
Operating Conditions ................................ 29
..............................
SD16_A, Performance .............................
SD16_A, Performance .............................
SD16_A, Linearity ..................................
SD16_A, Input Range
29
30
30
31
Typical Characteristics, SD16_A SINAD
Performance Over OSR ............................. 31
8
SD16_A, Temperature Sensor and Built-in VCC
Sense................................................ 32
...............
.................
5.31 SD16_A, External Reference Input .................
5.32 12-Bit DAC, Supply Specifications ..................
5.33 12-Bit DAC, Linearity Specifications ................
5.34 12-Bit DAC, Output Specifications ..................
5.35 12-Bit DAC, Reference Input Specifications ........
5.36 12-Bit DAC, Dynamic Specifications ................
5.37 12-Bit DAC, Dynamic Specifications Continued ....
5.38 Timer_A .............................................
5.39 Timer_B .............................................
5.40 USCI (UART Mode) .................................
5.41 USCI (SPI Master Mode)............................
5.42 USCI (SPI Slave Mode) .............................
5.43 USCI (I2C Mode) ....................................
5.44 Flash Memory .......................................
5.45 JTAG Interface ......................................
5.46 JTAG Fuse .........................................
Detailed Description ...................................
6.1
CPU .................................................
6.2
Instruction Set .......................................
6.3
Operating Modes ....................................
6.4
Interrupt Vector Addresses..........................
6.5
Special Function Registers (SFRs) .................
6.6
Memory Organization ...............................
6.7
Bootloader (BSL) ....................................
6.8
Flash Memory .......................................
6.9
Peripherals ..........................................
6.10 Input/Output Schematics ............................
Device and Documentation Support ...............
7.1
Device Support ......................................
7.2
Documentation Support .............................
7.3
Related Links ........................................
7.4
Support Resources ..................................
7.5
Trademarks..........................................
7.6
Electrostatic Discharge Caution .....................
7.7
Export Control Notice ...............................
7.8
Glossary .............................................
5.29
SD16_A, Built-In Voltage Reference
32
5.30
SD16_A, Reference Output Buffer
32
32
33
34
36
36
37
38
38
38
39
39
39
42
43
43
43
44
44
45
46
47
48
50
50
50
51
57
81
81
84
84
84
84
84
84
84
Mechanical, Packaging, and Orderable
Information .............................................. 85
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Table of Contents
3
MSP430F479, MSP430F478, MSP430F477
SLAS629B – MARCH 2009 – REVISED MAY 2020
www.ti.com
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from April 25, 2009 to May 4, 2020
•
•
•
•
•
•
•
•
•
•
•
•
•
•
4
Page
Changes to document format including section numbering and organization ................................................ 1
Throughout the document, added the ZCA package ............................................................................ 1
Added Section 1.2, Applications ................................................................................................... 1
Added Device Information table .................................................................................................... 2
Changed the status of all orderable part numbers in the ZQW package ..................................................... 2
Removed former section Development Tool Support ........................................................................... 2
Moved functional block diagram to Section 1.4 ................................................................................... 2
Added Section 3, Device Comparison ............................................................................................. 5
Added Section 5 and moved all electrical specifications to it ................................................................. 12
Added Section 5.2, ESD Ratings.................................................................................................. 12
In Recommended Operating Conditions, added test conditions for TYP values ........................................... 13
Changed all instances of "bootstrap loader" to "bootloader" throughout document ........................................ 50
Added Section 7 and moved Trademarks and ESD Caution sections to it .................................................. 81
Added Section 8 ..................................................................................................................... 85
Revision History
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SLAS629B – MARCH 2009 – REVISED MAY 2020
3 Device Comparison
The following table summarizes the available family members.
Table 3-1. Device Comparison (1) (2)
FLASH
(KB)
RAM
(KB)
Timer_A
Timer_B
SD16_A
DAC12
USCI
I/Os
PACKAGE
MSP430F479
60
2
TA3
TB3
1
1
A0, B0
48
PN 80
ZCA 113
ZQW 113
MSP430F478
48
2
TA3
TB3
1
1
A0, B0
48
PN 80
ZCA 113
ZQW 113
MSP430F477
32
2
TA3
TB3
1
1
A0, B0
48
PN 80
ZCA 113
ZQW 113
DEVICE
(1)
(2)
3.1
For the most current device, package, and ordering information for all available devices, see the Package Option Addendum in
Section 8, or see the TI website at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Related Products
For information about other devices in this family of products or related products, see the following links.
Products for TI Microcontrollers TI's low-power and high-performance MCUs, with wired and wireless
connectivity options, are optimized for a broad range of applications.
Products for MSP430 Ultra-Low-Power Microcontrollers One platform. One ecosystem. Endless
possibilities. Enabling the connected world with innovations in ultra-low-power
microcontrollers with advanced peripherals for precise sensing and measurement.
Companion Products for MSP430F479 Review products that are frequently purchased or used in
conjunction with this product.
Reference Designs Find reference designs leveraging the best in TI technology to solve your systemlevel challenges
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Device Comparison
5
MSP430F479, MSP430F478, MSP430F477
SLAS629B – MARCH 2009 – REVISED MAY 2020
www.ti.com
4 Terminal Configuration and Functions
4.1
Pin Diagrams
Figure 4-1 shows the pinout for the 80-pin PN package.
Figure 4-1. 80-Pin PN Package (Top View)
6
Terminal Configuration and Functions
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SLAS629B – MARCH 2009 – REVISED MAY 2020
Figure 4-2 shows the pinout for the 113-pin ZCA and ZQW packages. For pin assignments, see Table 4-1.
NOTE: For the terminal assignments, see Section 4.2.
Figure 4-2. 113-Pin ZCA and ZQW Packages (Top View)
Terminal Configuration and Functions
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MSP430F479, MSP430F478, MSP430F477
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4.2
www.ti.com
Signal Descriptions
Table 4-1 describes the device signals.
Table 4-1. Signal Descriptions
PIN NO.
SIGNAL NAME
PN
ZCA,
ZQW
I/O
DESCRIPTION
AVCC
52
F12
Analog supply voltage, positive terminal.
AVSS
53
E12
Analog supply voltage, negative terminal.
DVCC1
1
A1
Digital supply voltage, positive terminal. Supplies all digital parts.
DVSS1
79
A3
Digital supply voltage, negative terminal. Supplies all digital parts.
DVCC2
80
A2
Digital supply voltage, positive terminal. Supplies all digital parts.
DVSS2
78
B2, B3
Digital supply voltage, negative terminal. Supplies all digital parts.
P1.0/TA0
58
C11
General-purpose digital I/O pin
I/O
Timer_A, capture: CCI0A input, compare: Out0 output
BSL transmit
General-purpose digital I/O pin
P1.1/TA0/MCLK
57
C12
I/O
Timer_A, capture: CCI0B input, compare: Out0 output
MCLK signal output
BSL receive
General-purpose digital I/O pin
P1.2/TA1/A4-
56
D11
I/O
Timer_A, capture: CCI1A input, compare: Out1 output
SD16 negative analog input A4
General-purpose digital I/O pin
Timer_A, capture: CCI2A input, compare: Out2 output
P1.3/TBOUTH/SVSOUT/A4
+
55
D12
I/O
Set all PWM digital output ports to high impedance - Timer_B TB0 to
TB2
SVS comparator output
SD16 positive analog input A4
General-purpose digital I/O pin
P1.4/TBCLK/SMCLK/A3-
54
E11
I/O
Timer_B, clock signal TBCLK input
SMCLK signal output
SD16 negative analog input A3
General-purpose digital I/O pin
P1.5/TACLK/ACLK/A3+
51
F11
I/O
Timer_A, clock signal TACLK input
ACLK signal output
SD16 positive analog input A3
General-purpose digital I/O pin
P1.6/CA0/A2-/DAC0
50
G12
I/O
Comparator_A input 0
SD16 negative analog input A2
DAC12.0 output
General-purpose digital I/O pin
P1.7/CA1/A2+
49
G11
I/O
Comparator_A input 1
SD16 positive analog input A2
General-purpose digital I/O pin
P2.0/TA2/S1
4
C2, C3
I/O
Timer_A, capture: CCI2A/B input, compare: Out2 output
LCD segment output 1
General-purpose digital I/O pin
P2.1/TB0/S0
3
C1
I/O
Timer_B, capture: CCI0A/B input, compare: Out0 output
LCD segment output 0
8
Terminal Configuration and Functions
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SLAS629B – MARCH 2009 – REVISED MAY 2020
Table 4-1. Signal Descriptions (continued)
PIN NO.
SIGNAL NAME
PN
ZCA,
ZQW
I/O
P2.2/TB1
2
B1
I/O
P2.3/TB2
77
B4
I/O
P2.4/UCA0TXD/
UCA0SIMO
76
A4
I/O
P2.5/UCA0RXD/
UCA0SOMI
75
D4
I/O
P2.6/CAOUT/S2
5
D1
I/O
DESCRIPTION
General-purpose digital I/O pin
Timer_B, capture: CCI1A/B input, compare: Out1 output
General-purpose digital I/O pin
Timer_B, capture: CCI2A/B input, compare: Out2 output
General-purpose digital I/O pin
USCIA transmit data output in UART mode, slave data in/master out in
SPI mode
General-purpose digital I/O pin
USCI A0 receive data input in UART mode, slave data out/master in in
SPI mode
General-purpose digital I/O pin
Comparator_A output
LCD segment output 2
P2.7/S3
6
D2
I/O
General-purpose digital I/O pin
LCD segment output 3
General-purpose digital I/O pin
P3.0/UCB0STE/UCA0CLK
41
M12
I/O
USCI B0 slave transmit enable
USCI A0 clock input/output
General-purpose digital I/O pin
P3.1/UCB0SIMO/
UCB0SDA/S26
42
L12
I/O
USCI B0 slave in/master out in SPI mode, SDA I2C data in I2C mode
LCD segment output 26
General-purpose digital I/O pin
P3.2/UCB0SOMI/
UCB0SCL/S27
43
K11
I/O
USCI B0 slave out/master in in SPI mode, SCL I2C clock in I2C mode
LCD segment output 27
P3.3/UCB0CLK/UCA0STE
44
K12
I/O
P3.4/S28
45
J11
I/O
P3.5/S29
46
J12
I/O
P3.6/S30
47
H11
I/O
P3.7/S31
48
H12
I/O
P4.0/S11
18
K2
I/O
P4.1/S10
17
K1
I/O
P4.2/S9
16
J2
I/O
P4.3/S8
15
J1
I/O
P4.4/S7
14
H2
I/O
P4.5/S6
13
H1
I/O
General-purpose digital I/O
USCI B0 clock input/output, USCI A0 slave transmit enable
General-purpose digital I/O pin
LCD segment output 28
General-purpose digital I/O pin
LCD segment output 29
General-purpose digital I/O pin
LCD segment output 30
General-purpose digital I/O pin
LCD segment output 31
General-purpose digital I/O pin
LCD segment output 11
General-purpose digital I/O pin
LCD segment output 10
General-purpose digital I/O pin
LCD segment output 9
General-purpose digital I/O pin
LCD segment output 8
General-purpose digital I/O pin
LCD segment output 7
General-purpose digital I/O pin
LCD segment output 6
Terminal Configuration and Functions
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Table 4-1. Signal Descriptions (continued)
PIN NO.
SIGNAL NAME
PN
ZCA,
ZQW
I/O
P4.6/S5
12
G2
I/O
P4.7/S4
11
G1
I/O
COM0
33
L8
O
P5.0/S20
27
L5
I/O
P5.1/S21
28
M5
I/O
P5.2/COM1
34
M8
I/O
P5.3/COM2
35
L9
I/O
P5.4/COM3
36
M9
I/O
LCDCAP/R33
37
J9
I/O
P5.5/R23
38
M10
I/O
P5.6/LCDREF/R13
39
L10
I/O
DESCRIPTION
General-purpose digital I/O pin
LCD segment output 5
General-purpose digital I/O pin
LCD segment output 4
Common output, COM0- 3 are used for LCD backplanes
General-purpose digital I/O pin
LCD segment output 20
General-purpose digital I/O pin
LCD segment output 21
General-purpose digital I/O pin
common output, COM0- 3 are used for LCD backplanes
General-purpose digital I/O pin
common output, COM0- 3 are used for LCD backplanes
General-purpose digital I/O pin
common output, COM0- 3 are used for LCD backplanes
Capacitor connection for LCD charge pump
input port of most positive analog LCD level (V4)
General-purpose digital I/O pin
input port of the second most positive analog LCD level (V3)
General-purpose digital I/O pin
External LCD reference voltage input
input port of the third most positive analog LCD level (V3 or V2)
General-purpose digital I/O pin
P5.7/R03
40
M11
I/O
P6.0/A0+
67
B8
I/O
P6.1/A0-
66
B9
I/O
P6.2
65
A9
I/O
P6.3/A1+
64
D9
I/O
P6.4/A1-
63
A10
I/O
P6.5
62
B10
I/O
General-purpose digital I/O pin
P6.6
61
A11
I/O
General-purpose digital I/O pin
P6.7/SVSIN
59
B12
I/O
S12
19
L1
O
LCD segment output 12
S13
20
M1
O
LCD segment output 13
S14
21
M2
O
LCD segment output 14
S15
22
M3
O
LCD segment output 15
S16
23
L3
O
LCD segment output 16
S17
24
L4
O
LCD segment output 17
S18
25
M4
O
LCD segment output 18
S19
26
J4
O
LCD segment output 19
S22
29
L6
O
LCD segment output 22
10
Terminal Configuration and Functions
input port of the fourth most positive analog LCD level (V1)
General-purpose digital I/O pin
SD16 positive analog input A0
General-purpose digital I/O pin
SD16 positive negative input A0
General-purpose digital I/O pin
General-purpose digital I/O pin
SD16 positive analog input A1
General-purpose digital I/O pin
SD16 positive negative input A1
General-purpose digital I/O pin
SVS input
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Table 4-1. Signal Descriptions (continued)
PIN NO.
SIGNAL NAME
PN
ZCA,
ZQW
I/O
S23
30
M6
O
LCD segment output 23
S24
31
L7
O
LCD segment output 24
S25
32
M7
O
LCD segment output 25
GND
7
E2
XIN
8
E1
I
Input port for crystal oscillator XT1. Standard or watch crystals can be
connected.
XOUT
9
F1
O
Output port for crystal oscillator XT1. Standard or watch crystals can be
connected.
GND
10
F2
VREF
60
A12
O
Input for an external reference voltage/internal reference voltage output
RST/NMI
74
B5
I
Reset input, nonmaskable interrupt input port, or bootloader start (in
flash devices).
TCK
73
A5
I
Test clock (JTAG). TCK is the clock input port for device programming
test and bootloader start.
TDI/TCLK
71
A6
I
Test data input or test clock input. The device protection fuse is
connected to TDI/TCLK.
TDO/TDI
70
B7
I/O
TMS
72
B6
I
Test mode select. TMS is used as an input port for device programming
and test.
XT2OUT
68
A8
O
Output terminal of crystal oscillator XT2
XT2IN
69
A7
I
Input port for crystal oscillator XT2
NA
B11, D6,
D7, D8,
E4, E5,
E6, E7,
E8, E9,
F4, F5,
F8, F9,
G4,
G5,G8,
G9, H4,
H5, H6,
H7, H8,
H9, J5, J6,
J7, J8, L2,
L11
Reserved
(1)
DESCRIPTION
Ground. It is used to shield the oscillator. See Note 1.
Ground. It is used to shield the oscillator. (1)
Test data output port. TDO/TDI data output or programming data input
terminal.
Unused BGA balls. Connection to DVSS/AVSS recommended.
It is recommended to connect GND externally to DVSS.
Terminal Configuration and Functions
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MSP430F479, MSP430F478, MSP430F477
SLAS629B – MARCH 2009 – REVISED MAY 2020
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5 Specifications
5.1
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Voltage applied at VCC to VSS
Voltage applied to any pin
(2)
MIN
MAX
–0.3
4.1
–0.3
VCC + 0.3
Diode current at any device terminal
Storage temperature, Tstg (3)
(1)
(2)
(3)
±2
Unprogrammed device
–55
150
Programmed device
–40
85
V(ESD)
12
V
mA
°C
ESD Ratings
VALUE
(2)
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are referenced to VSS.The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TDI/TCLK pin when blowing the JTAG fuse.
Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak
reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2
(1)
UNIT
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
Specifications
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5.3
SLAS629B – MARCH 2009 – REVISED MAY 2020
Recommended Operating Conditions
Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MIN
1.8
3.6
During flash memory programming (AVCC = DVCC1 = DVCC2 =
VCC)
2.7
3.6
0
0
Supply voltage
VSS
Supply ground (AVSS = DVSS1 = DVSS2 = VSS)
TA
Operating free-air temperature range
LFXT1 crystal
frequency (1)
–40
LF selected, XTS_FLL = 0
Watch crystal
XT1 selected, XTS_FLL = 1
Ceramic resonator
XT1 selected, XTS_FLL = 1
Crystal
XT2 crystal frequency
f(System)
Processor frequency (MCLK, SMCLK, ACLK)
85
32.768
6
1
6
0.45
8
1
8
VCC = 1.8 V
DC
4.15
VCC = 2.5 V
DC
8
Crystal
UNIT
V
V
°C
kHz
0.45
Ceramic resonator
f(XT2)
(1)
MAX
During program execution (AVCC = DVCC1 = DVCC2 = VCC)
VCC
f(LFXT1)
NOM
MHz
MHz
MHz
In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.
Supply voltage range
during program
execution
Supply voltage range
during flash memory programming
Figure 5-1. Frequency vs Supply Voltage
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13
MSP430F479, MSP430F478, MSP430F477
SLAS629B – MARCH 2009 – REVISED MAY 2020
5.4
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Supply Current Into AVCC and DVCC Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITION
TYP
MAX
VCC = 2.2 V
262
295
VCC = 3 V
420
460
VCC = 2.2 V
32
62
VCC = 3 V
51
77
VCC = 2.2 V
5
9
VCC = 3 V
7
13
TA = –40°C
1.0
1.8
TA = 25°C
1.0
1.8
(1)
I(AM)
Active mode
f(MCLK) = f(SMCLK) = 1 MHz,
f(ACLK) = 32768 Hz,
XTS = 0, SELM = 0 or 1
TA = –40°C to 85°C
I(LPM0)
Low power mode (LPM0) (1)
TA = –40°C to 85°C
I(LPM2)
Low-power mode (LPM2),
f(MCLK) = f(SMCLK) = 0 MHz,
f(ACLK) = 32768 Hz, SCG0 = 0 (2)
TA = –40°C to 85°C
I(LPM3)
Low-power mode (LPM3),
f(MCLK) = f(SMCLK) = 0 MHz,
f(ACLK) = 32768 Hz, SCG0 = 1,
Basic Timer1 enabled, ACLK selected,
LCD_A enabled, LCDCPEN = 0,
(static mode, fLCD = f(ACLK)/32) (2) (3)
TA = 60°C
1.1
2.0
TA = 85°C
2.3
4.0
TA = –40°C
1.2
2.0
1.2
2.0
TA = 25°C
TA = 60°C
I(LPM3)
Low-power mode (LPM3),
f(MCLK) = f(SMCLK) = 0 MHz,
f(ACLK) = 32768 Hz, SCG0 = 1,
Basic Timer1 enabled, ACLK selected,
LCD_A enabled, LCDCPEN = 0,
(4-mux mode; fLCD = f(ACLK)/32) (2) (3)
I(LPM4)
VCC = 3 V
1.4
2.2
TA = 85°C
2.7
4.5
TA = –40°C
1.0
3.0
TA = 25°C
1.1
3.2
TA = 85°C
3.5
6.0
TA = –40°C
1.8
3.3
TA = 25°C
VCC = 2.2 V
2.0
4.0
TA = 85°C
4.2
7.5
TA = –40°C
0.1
0.5
TA = 25°C
0.1
0.5
TA = 60°C
Low-power mode (LPM4),
f(MCLK) = 0 MHz, f(SMCLK) = 0 MHz,
f(ACLK) = 0 Hz, SCG0 = 1 (2)
VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V
0.7
1.1
TA = 85°C
1.7
3.0
TA = –40°C
0.1
0.8
0.1
0.8
0.8
1.2
1.5
3.5
TA = 25°C
TA = 60°C
VCC = 3 V
TA = 85°C
(1)
(2)
(3)
MIN
UNIT
µA
µA
µA
µA
µA
µA
Timer_A is clocked by f(DCOCLK)= 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The LPM3 currents are characterized with a Micro Crystal CC4V-T1A (9 pF) crystal and OSCCAPx = 1h.
Current consumption of active mode versus system frequency:
I(AM) = I(AM) [1 MHz] × f(System) [MHz]
Current consumption of active mode versus supply voltage:
I(AM) = I(AM) [3 V] + 200 µA/V × (VCC – 2.2 V)
14
Specifications
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SLAS629B – MARCH 2009 – REVISED MAY 2020
Figure 5-2. ILPM4 -- LPM4 Current vs Temperature
5.5
Schmitt-Trigger Inputs – Ports P1 to P6, RST/NMI, JTAG (TCK, TMS, TDI/TCLK,TDO/TDI)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT– )
5.6
MIN
MAX
VCC = 2.2 V
1.1
1.55
VCC = 3 V
1.5
1.98
VCC = 2.2 V
0.4
0.9
VCC = 3 V
0.9
1.3
VCC = 2.2 V
0.3
1.1
VCC = 3 V
0.5
1
UNIT
V
V
V
Inputs Px.y, TAx
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2.2 V
62
3V
50
2.2 V
62
3V
50
t(int)
External interrupt timing
Port P1, P2: P1.x to P2.x, external trigger signal
for the interrupt flag (1)
t(cap)
Timer_A capture timing
TA0, TA1, TA2
f(TAext)
Timer_A clock frequency externally
applied to pin
TACLK, INCLK t(H) = t(L)
Timer A clock frequency
SMCLK or ACLK signal selected
f(TBext)
f(TAint)
f(TBint)
(1)
MIN
MAX
UNIT
ns
ns
2.2 V
8
3V
10
2.2 V
8
3V
10
MHz
MHz
The external signal sets the interrupt flag every time the minimum t(int) parameters are met. It may be set even with trigger signals
shorter than t(int).
5.7
Leakage Current – Ports P1 to P6
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
Ilkg(Px.y)
(1)
(2)
TEST CONDITIONS
V(Px.y) (2)
Leakage current, Port Px
VCC = 2.2 V, 3 V
MIN
MAX
UNIT
±50
nA
The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The port pin must be selected as input.
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MSP430F479, MSP430F478, MSP430F477
SLAS629B – MARCH 2009 – REVISED MAY 2020
5.8
www.ti.com
Outputs – Ports P1 to P6
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH(max) = –1.5 mA, VCC = 2.2 V
VOH
High-level output voltage
(1)
VCC – 0.25
VCC
VCC – 0.6
VCC
IOH(max) = –1.5 mA, VCC = 3 V (1)
VCC – 0.25
VCC
VCC – 0.6
VCC
VSS
VSS + 0.25
IOL(max) = 1.5 mA, VCC = 2.2 V
(1)
(2)
Low-level output voltage
MAX
IOH(max) = –6 mA, VCC = 2.2 V (2)
IOH(max) = –6 mA, VCC = 3 V (2)
VOL
MIN
(1)
IOL(max) = 6 mA, VCC = 2.2 V (2)
VSS
VSS + 0.6
IOL(max) = 1.5 mA, VCC = 3 V (1)
VSS
VSS + 0.25
IOL(max) = 6 mA, VCC = 3 V (2)
VSS
VSS + 0.6
UNIT
V
V
The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to satisfy the maximum specified
voltage drop.
The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to satisfy the maximum specified
voltage drop.
5.9
Output Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
f(Px.y)
1 ≤ × ≤ 6, 0 ≤ y ≤ 7
CL = 20 F, IL = ±1.5 mA
f(MCLK)
P1.1/TA0/MCLK
CL = 20 pF
t(Xdc)
Duty cycle of output
frequency
P1.1/TA0/MCLK,
CL = 20 pF, VCC = 2.2 V, 3 V
16
Specifications
MIN
VCC = 2.2 V, 3 V
f(MCLK) = f(XT1)
f(MCLK) = f(DCOCLK)
TYP
DC
MAX
UNIT
fSystem
MHz
fSystem
MHz
40%
60%
50% –
15 ns
50%+
15 ns
50%
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5.10 Typical Characteristics – Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
Figure 5-3. Typical Low-Level Output Current vs Typical LowLevel Output Current
Figure 5-4. Typical Low-Level Output Current vs Typical LowLevel Output Current
Figure 5-5. Typical High-Level Output Current vs Typical HighLevel Output Current
Figure 5-6. Typical High-Level Output Current vs Typical HighLevel Output Current
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Specifications
17
MSP430F479, MSP430F478, MSP430F477
SLAS629B – MARCH 2009 – REVISED MAY 2020
5.11
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Wake-up Timing From LPM3
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
f = 1 MHz
td(LPM3)
Delay time
UNIT
6
f = 2 MHz
VCC = 2.2 V, 3 V
6
f = 3 MHz
µs
6
5.12 POR – Brownout Reset (BOR)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
td(BOR)
Brownout (2)
V(B_IT–)
V(B_IT–
dVCC/dt ≤ 3 V/s (see Figure 5-7 through Figure 5-9)
Vhys(B_IT–)
dVCC/dt ≤ 3 V/s (see Figure 5-7)
t(reset)
Pulse duration needed at RST/NMI pin to accepted
reset internally, VCC = 2.2 V, 3 V
(1)
(2)
UNIT
2000
µs
0.7 ×
dVCC/dt ≤ 3 V/s (see Figure 5-7)
VCC(start)
MAX
V
)
1.71
V
mV
2
µs
The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT–) +
Vhys(B_IT–) ≤ 1.89 V.
During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT–) + Vhys(B_IT–). The default FLL+ settings
must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency. See the
MSP430x4xx Family User’s Guide (SLAU056) for more information on the brownout and SVS circuit.
VCC
Vhys(B_IT-)
V(B_IT-)
VCC(start)
1
0
td(BOR)
Figure 5-7. POR, BOR vs Supply Voltage
18
Specifications
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V CC
3V
2
VCC = 3 V
Typical Conditions
tpw
VCC(drop) - V
1.5
1
V CC(drop)
0.5
0
0.001
1
1000
1 ns
tpw - Pulse Width - m s
1 ns
tpw - Pulse Width - ms
Figure 5-8. VCC(drop) Level with a Square Voltage Drop to Generate a POR or BOR Signal
V CC
2
tpw
3V
V C C (drop) - V
VCC = 3 V
1.5
Typical Conditions
1
V CC(drop)
0.5
tf = tr
0
0.001
1
tpw - Pulse Width - m s
1000
tf
tr
tpw - Pulse Width - ms
Figure 5-9. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR or BOR Signal
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Specifications
19
MSP430F479, MSP430F478, MSP430F477
SLAS629B – MARCH 2009 – REVISED MAY 2020
5.13
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SVS (Supply Voltage Supervisor and Monitor)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
dVCC/dt > 30 V/ms (see Figure 5-10)
t(SVSR)
5
2000
SVS on, switch from VLD = 0 to VLD ≠ 0, VCC = 3 V
tsettle
VLD ≠ 0 (1)
V(SVSstart)
VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 5-10)
20
VLD = 1
VCC/dt ≤ 3 V/s (see Figure 5-10)
Vhys(SVS_IT–)
VCC/dt ≤ 3 V/s (see Figure 5-10), external voltage
applied on A7
VCC/dt ≤ 3 V/s (see Figure 5-10)
V(SVS_IT–)
VCC/dt ≤ 3 V/s (see Figure 5-10), external voltage
applied on A7
(1)
(2)
(3)
20
(3)
MAX
150
dVCC/dt ≤ 30 V/ms
td(SVSon)
ICC(SVS)
TYP
70
µs
12
µs
1.55
1.7
V
120
210
mV
V(SVS_IT–)
× 0.016
VLD = 15
4.4
20
VLD = 1
1.8
1.9
2.05
VLD = 2
1.94
2.1
2.23
VLD = 3
2.05
2.2
2.37
VLD = 4
2.14
2.3
2.48
VLD = 5
2.24
2.4
2.6
VLD = 6
2.33
2.5
2.71
VLD = 7
2.46
2.65
2.86
VLD = 8
2.58
2.8
3
VLD = 9
2.69
2.9
3.13
VLD = 10
2.83
3.05
3.29
VLD = 11
2.94
3.2
3.42
VLD = 12
3.11
3.35
3.61 (2)
VLD = 13
3.24
3.5
3.76 (2)
VLD = 14
3.43
3.7 (2)
3.99 (2)
VLD = 15
1.1
1.2
1.3
10
15
VLD ≠ 0, VCC = 2.2 V, 3 V
µs
150
V(SVS_IT–)
× 0.001
VLD = 2 to 14
UNIT
mV
V
µA
tsettle is the settling time that the comparator output needs to have a stable level after VLD is switched from VLD ≠ 0 to a different VLD
value from 2 to 15. The overdrive is assumed to be > 50 mV.
The recommended operating voltage range is limited to 3.6 V.
The current consumption of the SVS module is not included in the ICC current consumption data.
Specifications
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VCC
V(SVS_IT-)
V(SVSstart)
Software Sets VLD>0:
SVS is Active
Vhys(SVS_IT-)
Vhys(B_IT-)
V(B_IT-)
VCC(start)
Brown
Out
Region
Brownout
Region
Brownout
1
0
SVSOut
t d(BOR)
t d(BOR)
SVS Circuit is Active From VLD > to VCC < V(B_IT-)
1
0
td(SVSon)
Set POR
1
td(SVSR)
undefined
0
Figure 5-10. SVS Reset (SVSR) vs Supply Voltage
V CC
tpw
3V
2
Rectangular Drop
V CC(drop)
V C C (drop) - V
1.5
Triangular Drop
1
1 ns
1 ns
0.5
V CC
t pw
3V
0
1
10
100
1000
tpw - Pulse Width - m s
V CC(drop)
tf = tr
tf
tr
t - Pulse Width - ms
Figure 5-11. VCC(drop) with a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal
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Specifications
21
MSP430F479, MSP430F478, MSP430F477
SLAS629B – MARCH 2009 – REVISED MAY 2020
5.14
www.ti.com
DCO
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
f(DCOCLK)
N(DCO) = 01Eh, FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2,
DCOPLUS = 0
f(DCO = 2)
FN_8 = FN_4 = FN_3 = FN_2 = 0, DCOPLUS = 1
f(DCO = 27)
FN_8 = FN_4 = FN_3 = FN_2 = 0, DCOPLUS = 1 (1)
f(DCO = 2)
FN_8 = FN_4 = FN_3 = FN_2 = 1, DCOPLUS = 1
f(DCO = 27)
FN_8 = FN_4 = FN_3 = FN_2 = 1, DCOPLUS = 1 (1)
f(DCO = 2)
FN_8 = FN_4 = 0, FN_3 = 1, FN_2 = x, DCOPLUS = 1
f(DCO = 27)
FN_8 = FN_4 = 0, FN_3 = 1, FN_2 = x, DCOPLUS = 1 (1)
f(DCO = 2)
FN_8 = 0, FN_4 = 1, FN_3 = FN_2 = x, DCOPLUS = 1
f(DCO = 27)
FN_8 = 0, FN_4 = 1, FN_3 = FN_2 = x, DCOPLUS = 1 (1)
f(DCO = 2)
FN_8 = 1, FN_4 = 1 = FN_3 = FN_2 = x, DCOPLUS = 1
f(DCO = 27)
FN_8 = 1, FN_4 = 1 = FN_3 = FN_2 = x, DCOPLUS = 1 (1)
Sn
Step size between adjacent DCO taps:
Sn = fDCO(Tap n+1) /fDCO(Tap n) (see Figure 5-13 for taps 21 to 27)
Dt
Temperature drift, N(DCO) = 01Eh,
FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2, DCOPLUS = 0 (2)
DV
Drift with VCC variation, N(DCO) = 01Eh,
FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2, DCOPLUS = 0 (2)
(1)
(2)
MIN
TYP
2.2 V, 3 V
MAX
UNIT
1
MHz
2.2 V
0.3
0.65
1.25
3V
0.3
0.7
1.3
2.2 V
2.5
5.6
10.5
3V
2.7
6.1
11.3
2.2 V
0.7
1.3
2.3
3V
0.8
1.5
2.5
2.2 V
5.7
10.8
18
3V
6.5
12.1
20
2.2 V
1.2
2
3
3V
1.3
2.2
3.5
2.2 V
9
15.5
25
3V
10.3
17.9
28.5
2.2 V
1.8
2.8
4.2
3V
2.1
3.4
5.2
2.2 V
13.5
21.5
33
3V
16
26.6
41
2.2 V
2.8
4.2
6.2
3V
4.2
6.3
9.2
2.2 V
21
32
46
3V
30
46
70
1 < TAP ≤ 20
1.06
1.11
TAP = 27
1.07
1.17
2.2 V
–0.2
–0.3
–0.4
3V
–0.2
–0.3
–0.4
0
5
15
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%/°C
%/V
Do not exceed the maximum system frequency.
This parameter is not production tested.
f(DCO)
f(DCO)
f(DCO3V)
f(DCO20°C)
1.0
1.0
0
1.8
2.4
3.0
3.6
-40
-20
0
20
40
60
85
TA - ° C
VCC - V
Figure 5-12. DCO Frequency vs Supply Voltage VCC and vs Ambient Temperature
22
Specifications
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1.17
Max
1.11
1.07
1.06
Min
1
20
27
DCO Tap
Figure 5-13. DCO Tap Step Size
Legend
f(DCO)
Tolerance at Tap 27
DCO Frequency
Adjusted by Bits
9
5
2 to 2 in SCFI1 {N{DCO}}
Tolerance at Tap 2
Overlapping DCO Ranges:
Uninterrupted Frequency Range
FN_2=0
FN_3=0
FN_4=0
FN_8=0
FN_2=x
FN_3=1
FN_4=0
FN_8=0
FN_2=1
FN_3=0
FN_4=0
FN_8=0
FN_2=x
FN_3=x
FN_4=1
FN_8=0
FN_2=x
FN_3=x
FN_4=x
FN_8=1
Figure 5-14. Five Overlapping DCO Ranges Controlled by FN_x Bits
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5.15 Crystal Oscillator, LFXT1, Low-Frequency Mode
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fLFXT1,LF
LFXT1 oscillator crystal
frequency, LF mode 0, 1
OALF
Oscillation allowance for LF
crystals
CL,eff
Integrated effective load
capacitance, LF mode (2)
Duty cycle, LF mode
fFault,LF
(1)
(2)
(3)
(4)
24
XTS = 0, LFXT1Sx = 0 or 1
VCC
MIN
1.8 V to
3.6 V
TYP
MAX
32768
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 kHz, CL,eff = 6 pF
500
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 kHz, CL,eff = 12 pF
200
UNIT
Hz
kΩ
XTS = 0, XCAPx = 0
1
XTS = 0, XCAPx = 1
5.5
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
11
XTS = 0, Measured at P1.5/ACLK,
fLFXT1,LF = 32768Hz
(1)
2.2 V, 3 V
30
2.2 V, 3 V
10
50
pF
70
%
10000
Hz
Oscillator fault frequency, LF XTS = 0, XCAPx = 0, LFXT1Sx =
mode (3)
3 (4)
To
•
•
•
•
•
•
•
improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines should be observed.
Keep the trace between the MCU and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance it is
recommended to verify the correct load by measuring the ACLK frequency. For a correct setup the effective load capacitance should
always match the specification of the used crystal.
Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and
frequencies in between might set the flag.
Measured with logic level input frequency but also applies to operation with crystals.
Specifications
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5.16 Crystal Oscillator, LFXT1, High-Frequency Mode
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fLFXT1
LFXT1 oscillator crystal frequency
CL,eff
Integrated effective load
capacitance, HF mode (1) (2)
(2)
MIN
TYP
MAX
Ceramic resonator
1.8 V to 3.6 V
0.45
8
Crystal resonator
1.8 V to 3.6 V
1
8
1
Duty cycle
(1)
VCC
Measured at P1.5/ACLK
2.2 V, 3 V
40
50
UNIT
MHz
pF
60
%
Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it is
recommended to verify the correct load by measuring the ACLK frequency. For a correct setup the effective load capacitance should
always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
5.17 Crystal Oscillator, XT2 Oscillator, High-Frequency Mode
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fXT2
XT2 oscillator crystal frequency
CL,eff
Integrated effective load
capacitance, HF mode (1) (2)
Duty cycle
(1)
(2)
VCC
MIN
Ceramic resonator
1.8 V to 3.6 V
0.45
TYP
MAX
8
Crystal resonator
1.8 V to 3.6 V
1
8
1
Measured at P1.4/SMCLK
2.2 V, 3 V
40
50
UNIT
MHz
pF
60
%
Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it is
recommended to verify the correct load by measuring the ACLK frequency. For a correct setup the effective load capacitance should
always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
5.18
RAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VRAMh
(1)
CPU halted
(1)
MIN
MAX
1.6
UNIT
V
This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution
should take place during this supply voltage condition.
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5.19
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LCD_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
VCC(LCD)
Supply voltage
Charge pump enabled
(LCDCPEN = 1, VLCDx > 0000)
2.2
CLCD
Capacitor on LCDCAP (1)
Charge pump enabled
(LCDCPEN = 1, VLCDx > 0000)
4.7
ICC(LCD)
Average supply current (2)
VLCD(typ) = 3 V, LCDCPEN = 1,
VLCDx= 1000, all segments on, fLCD = fACLK/32,
no LCD connected (3), TA = 25°C
fLCD
LCD frequency
VLCD
RLCD
(1)
(2)
(3)
26
2.2 V
TYP
MAX
3.6
LCD driver output impedance
3.8
VLCDx = 0000
VCC
VLCDx = 0001
2.60
VLCDx = 0010
2.66
VLCDx = 0011
2.72
VLCDx = 0100
2.78
VLCDx = 0101
2.84
VLCDx = 0110
2.90
VLCDx = 0111
2.96
VLCDx = 1000
3.02
VLCDx = 1001
3.08
VLCDx = 1010
3.14
VLCDx = 1011
3.20
VLCDx = 1100
3.26
VLCDx = 1101
3.32
VLCDx = 1110
3.38
VLCDx = 1111
3.44
VLCD= 3 V, CPEN = 1, VLCDx = 1000, ILOAD =
±10 µΑ
V
µF
µA
1.1
LCD voltage
UNIT
kHz
V
3.60
2.2 V
10
kΩ
Enabling the internal charge pump with an external capacitor smaller than the minimum specified might damage the device.
Refer to the supply current specifications I(LPM3) for additional current specifications with the LCD_A module active.
Connecting an actual display increases the current consumption depending on the size of the LCD.
Specifications
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5.20 Comparator_A (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(CC)
CAON = 1, CARSEL = 0, CAREF = 0
I(Refladder/RefDiode)
CAON = 1, CARSEL = 0, CAREF = (1, 2, 3),
No load at P1.6/CA0 and P1.7/CA1
VCC
MIN
TYP
MAX
2.2 V
25
40
3V
45
60
2.2 V
30
50
3V
45
80
V(Ref025)
Voltage @ 0.25 VCC node
VCC
PCA0 = 1, CARSEL = 1, CAREF = 1,
No load at P1.6/CA0 and P1.7/CA1
2.2 V, 3 V
0.23
0.24
0.25
V(Ref050)
Voltage @ 0.5 VCC node
VCC
PCA0 = 1, CARSEL = 1, CAREF = 2,
No load at P1.6/CA0 and P1.7/CA1
2.2 V, 3 V
0.47
0.48
0.5
2.2 V
390
480
540
3V
400
490
550
V(RefVT)
See Figure 5-15 and
Figure 5-16
PCA0 = 1, CARSEL = 1, CAREF = 3,
No load at P1.6/CA0 and P1.7/CA1,
TA = 85°C
VIC
Common-mode input
voltage range
CAON = 1
Vp – VS
Offset voltage
Vhys
Input hysteresis
t(response
t(response
(1)
(2)
LH)
HL)
See
(2)
2.2 V, 3 V
0
2.2 V, 3 V
–30
2.2 V, 3 V
0
0.7
TA = 25°C,
Overdrive 10 mV, without filter: CAF = 0
2.2 V
80
165
3..
3V
70
120
240
TA = 25°C,
Overdrive 10 mV, without filter: CAF = 1
2.2 V
1.4
1.9
2.8
3V
0.9
1.5
2.2
CAON = 1
VCC – 1
UNIT
µA
µA
mV
V
30
mV
1.4
mV
ns
µs
The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification.
The response time is measured at P1.6/CA0 with an input voltage step and the Comparator_A already enabled (CAON = 1). If CAON is
set at the same time, a settling time of up to 300 ns is added to the response time.
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5.21 Typical Characteristics – Comparator_A
650
650
VCC = 2.2 V
VREF - Reference Voltage - mV
VREF - Reference Voltage - mV
VCC = 3 V
600
Typical
550
500
450
400
-45
-25
15
-5
35
55
75
95
600
Typical
550
500
450
400
-45
TA - Free-Air Temperature - °C
15
35
55
75
95
TA - Free-Air Temperature - °C
Figure 5-15. Reference Voltage vs Free-Air
Temperature
0V
-5
-25
Figure 5-16. Reference Voltage vs Free-Air
Temperature
VCC
0
1
CAF
CAON
To Internal
Modules
Low-Pass Filter
V+
V-
+
_
0
0
1
1
CAOUT
Set CAIFG
Flag
t » 2 µs
Figure 5-17. Block Diagram of Comparator_A Module
VCAOUT
Overdrive
V-
400 mV
V+
t(response)
Figure 5-18. Overdrive Definition
28
Specifications
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5.22 SD16_A, Power Supply and Recommended Operating Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
AVCC
Analog supply
voltage range
TEST CONDITIONS
ISD16
MIN
AVCC = DVCC = VCC,
AVSS = DVSS = VSS = 0 V
SD16LP = 0,
fSD16 = 1 MHz,
SD16OSR = 256
Analog supply
current including
internal reference
VCC
SD16LP = 1,
fSD16 = 0.5 MHz,
SD16OSR = 256
SD16LP = 0,
SD16OSR = 256
2.5
MAX
3.6
SD16BUFx = 00, GAIN: 1, 2
750
1050
SD16BUFx = 00, GAIN: 4, 8,
16
830
1150
SD16BUFx = 00, GAIN: 32
1150
1700
SD16BUFx = 00, GAIN: 1
730
1030
830
1150
3V
SD16BUFx = 00, GAIN: 32
SD16BUFx = 01, GAIN: 1
850
SD16BUFx = 10, GAIN: 1
1000
SD16BUFx = 11, GAIN: 1
fSD16
TYP
SD16LP = 0 (Low power mode disabled)
Analog front-end
input clock frequency SD16LP = 1 (Low power mode enabled)
UNIT
V
µA
1130
3V
0.03
1
0.03
0.5
1.1
MHz
5.23 SD16_A, Input Range
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VI
Absolute input voltage range
VIC
Common-mode input voltage
range
VID,FSR
Differential full scale input voltage
range (1)
VID
ZI
ZID
(1)
Differential input voltage range for
specified performance (1)
TYP
MAX
AVCC
SD16BUFx > 00
AVSS + 0.2
AVCC –
1.2 V
SD16BUFx = 00
AVSS – 0.1
AVCC
AVSS + 0.2
AVCC –
1.2 V
–VREF/
2GAIN
+VREF/
2GAIN
0
+VREF/2GAI
N
SD16BUFx > 00
Bipolar mode, SD16UNI = 0
Unipolar mode, SD16UNI = 1
SD16REFON = 1
fSD16 = 1 MHz,
SD16BUFx = 01
Differential input impedance
(IN+ to IN-)
MIN
AVSS – 0.1
fSD16 = 1 MHz,
SD16BUFx = 00
Input impedance
(one input pin to AVSS)
VCC
SD16BUFx = 00
fSD16 = 1 MHz,
SD16BUFx = 00
fSD16 = 1 MHz,
SD16BUFx = 01
SD16GAINx = 1
±500
SD16GAINx = 2
±250
SD16GAINx = 4
±125
SD16GAINx = 8
±62
SD16GAINx = 16
±31
SD16GAINx = 32
±15
SD16GAINx = 1
200
SD16GAINx = 32
SD16GAINx = 1
V
V
mV
mV
75
3V
UNIT
kΩ
>10
SD16GAINx = 1
300
400
SD16GAINx = 32
100
150
3V
SD16GAINx = 1
kΩ
>10
The analog input range depends on the reference voltage applied to VREF. If VREF is sourced externally, the full-scale range is defined
by VFSR+ = +(VREF / 2) / GAIN and VFSR– = –(VREF / 2) / GAIN. The analog input range should not exceed 80% of VFSR+ or VFSR-.
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5.24 SD16_A, Performance
fSD16 = 30 kHz, SD16REFON = 1, SD16BUFx = 01
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP MAX
SD16GAINx = 1,Signal Amplitude = 500 mV,
SD16OSRx = 256
Signal-to-noise + distortion
ratio
SINAD
UNIT
84
SD16GAINx = 1,Signal Amplitude = 500 mV,
fIN = 2.8 Hz
SD16OSRx = 512
3V
84
SD16GAINx = 1,Signal Amplitude = 500 mV,
SD16OSRx = 1024
dB
84
G
Nominal gain
SD16GAINx = 1, SD16OSRx = 1024
dG/dT
Gain temperature drift
SD16GAINx = 1, SD16OSRx = 1024
0.97
dG/dVCC
Gain supply voltage drift
SD16GAINx = 1, SD16OSRx = 1024, VCC = 2.5 V to
3.6 V
1.00
1.02
15
ppm/°C
0.35
%/V
5.25 SD16_A, Performance
fSD16 = 1 MHz, SD16OSRx = 256, SD16REFON = 1, SD16BUFx = 00
VCC = 3 V, over recommended operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
G
Nominal gain
Offset error
dEOS/dT
Offset error temperature
coefficient
CMRR
Common-mode rejection
ratio
30
Power supply rejection
ratio
Specifications
83.5
85
SD16GAINx = 2, Signal Amplitude =
250 mV
81.5
84
76
79.5
73
76.5
SD16GAINx = 16, Signal Amplitude =
31 mV
69
73
SD16GAINx = 32, Signal Amplitude =
15 mV
62
69
SD16GAINx = 1
0.97
1.00
1.02
SD16GAINx = 2
1.90
1.96
2.02
SD16GAINx = 4
3.76
3.86
3.96
SD16GAINx = 8, Signal Amplitude =
62 mV
EOS
PSRR
TYP
SD16GAINx = 4, Signal Amplitude =
125 mV
Signal-to-noise +
distortion ratio
SINAD
MIN
SD16GAINx = 1, Signal Amplitude =
500 mV
fIN = 50 Hz or
100 Hz
MAX
UNIT
dB
SD16GAINx = 8
7.36
7.62
7.84
SD16GAINx = 16
14.56
15.04
15.52
SD16GAINx = 32
27.20
28.35
29.76
SD16GAINx = 1
±0.2
SD16GAINx = 32
±1.5
SD16GAINx = 1
±4
±20
SD16GAINx = 32
±20
±100
SD16GAINx = 1, Common-mode input signal:
VID = 500 mV, fIN = 50 Hz or 100 Hz
>90
SD16GAINx = 32, Common-mode input signal:
VID = 16 mV, fIN = 50 Hz or 100 Hz
>75
SD16GAINx = 1
>80
%FSR
ppm
FSR/°C
dB
dB
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5.26 SD16_A, Linearity
fSD16 = 1 MHz, SD16REFON = 1, SD16BUFx = 00
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
SD16OSR = 256, SD16GAINx = 000b, Signal Amplitude = 500 mV
INL
Integral nonlinearity
SD16OSR = 256, SD16GAINx = 101b, Signal Amplitude = 15 mV
SD16OSR = 1024, SD16GAINx = 000b, Signal Amplitude = 500 mV
SD16OSR = 1024, SD16GAINx = 101b, Signal Amplitude = 15 mV
TYP
UNIT
1.5
3V
6
0.8
LSB
3.5
5.27 Typical Characteristics, SD16_A SINAD Performance Over OSR
fSD16 = 1 MHz
SD16REFON = 1
SD16GAINx = 1
Figure 5-19. SINAD Performance vs OSR
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5.28 SD16_A, Temperature Sensor and Built-in VCC Sense
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
Sensor temperature
coefficient
TCSensor
VOffset,Sensor
Sensor offset voltage
VCC
Sensor output voltage (3)
VCC,Sense
(1)
(2)
(3)
VCC divider at input 5
TYP
MAX
UNIT
1.32
1.46
mV/K
100
mV
See
(2)
1.18
See
(2)
–100
Temperature sensor voltage at TA = 85°C
VSensor
MIN
Temperature sensor voltage at TA = 25°C
3V
435
475
515
355
395
435
Temperature sensor voltage at TA = 0°C (2)
320
360
400
fSD16 = 32 kHz, SD16OSRx = 256,
SD16REFON = 1
0.08
1/11
0.1
mV
V
Results based on characterization and/or production test, not TCSensor or VOffset,sensor.
Not production tested, limits characterized.
The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ = TCSensor ( 273 + T [°C] ) + VOffset,sensor [mV]
5.29 SD16_A, Built-In Voltage Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
VCC
MIN
TYP
MAX
VREF
Internal reference voltage
PARAMETER
SD16REFON = 1, SD16VMIDON = 0
3V
1.14
1.20
1.26
V
IREF
Reference supply current
SD16REFON = 1, SD16VMIDON = 0
3V
175
260
µA
TC
Temperature coefficient
SD16REFON = 1, SD16VMIDON = 0 (1)
3V
18
50
ppm/°C
CREF
VREF load capacitance
SD16REFON = 1, SD16VMIDON = 0 (2)
ILOAD
VREF(I) maximum load current
SD16REFON = 1, SD16VMIDON = 0
3V
tON
Turn-on time
SD16REFON = 0 → 1, SD16VMIDON =
0,
CREF = 100 nF
3V
5
PSRR
Line regulation
SD16REFON = 1, SD16VMIDON = 0
3V
100
(1)
(2)
TEST CONDITIONS
UNIT
100
nF
±200
nA
ms
µV/V
Calculated using the box method: (MAX(--40...85°C) -- MIN(--40...85°C))/MIN(--40...85°C)/(85C -- (--40°C))
There is no capacitance required on VREF. However, TI recommends a capacitance of at least 100 nF to reduce any reference voltage
noise.
5.30 SD16_A, Reference Output Buffer
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
3V
1.2
3V
385
VREF,BUF
Reference buffer output voltage
SD16REFON = 1, SD16VMIDON =
1
IREF,BUF
Reference supply + reference output
buffer quiescent current
SD16REFON = 1, SD16VMIDON =
1
CREF(O)
Required load capacitance on VREF
SD16REFON = 1, SD16VMIDON =
1
ILOAD,Max
Maximum load current on VREF
SD16REFON = 1, SD16VMIDON =
1
3V
Maximum voltage variation vs load
current
|ILOAD| = 0 to 1 mA
3V
Turn-on time
SD16REFON = 0 → 1,
SD16VMIDON = 1,
CREF = 470 nF
3V
tON
MIN
TYP
MAX
UNIT
V
600
470
µA
nF
–15
±1
mA
+15
mV
100
µs
5.31 SD16_A, External Reference Input
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
1.0
1.25
1.5
V
50
nA
VREF(I) Input voltage range
SD16REFON = 0
3V
IREF(I)
SD16REFON = 0
3V
32
Input current
Specifications
UNIT
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5.32 12-Bit DAC, Supply Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
AVCC
Analog supply voltage
TEST CONDITIONS
VCC
AVCC = DVCC, AVSS = DVSS = 0 V
IDD
DAC12AMPx = 2, DAC12IR = 1,
DAC12_xDAT = 0800h, VREF,DAC12 = AVCC
DAC12AMPx = 5, DAC12IR = 1,
DAC12_xDAT = 0800h, VREF,DAC12 = AVCC
(1)
(2)
(3)
(4)
Power-supply rejection
ratio (3) (4)
DAC12_xDAT = 800h, VREF,DAC12 = 1.2 V,
ΔAVCC = 100 mV
MAX
UNIT
3.60
V
50
110
50
110
200
440
700
1500
2.2 V, 3 V
DAC12AMPx = 7, DAC12IR = 1,
DAC12_xDAT = 0800h, VREF,DAC12 = AVCC
PSRR
TYP
2.20
DAC12AMPx = 2, DAC12IR = 0,
DAC12_xDAT = 0800h
Supply current, single DAC
channel (1) (2)
MIN
2.7 V
µA
70
dB
No load at the output pin, DAC12_0, assuming that the control bits for the shared pins are set properly.
Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input specifications.
PSRR = 20 × log{ΔAVCC/ΔVDAC12_xOUT}.
VREF is applied externally. The internal reference is not used.
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33
MSP430F479, MSP430F478, MSP430F477
SLAS629B – MARCH 2009 – REVISED MAY 2020
5.33
www.ti.com
12-Bit DAC, Linearity Specifications
over recommended operating free-air temperature (unless otherwise noted) (see Figure 5-20)
PARAMETER
Integral nonlinearity (1)
INL
TEST CONDITIONS
VCC
VREF,DAC12 = 1.2 V or VREF,ext = 2.5 V
DAC12AMPx = 7, DAC12IR = 1
2.7 V
MIN
VREF,ext = 1.2 V,
DAC12AMPx = 7, DAC12IR = 1
VREF,ext = 2.5 V,
DAC12AMPx = 7, DAC12IR = 1
Differential nonlinearity (1)
DNL
–1
2.7 V
VREF,DAC12 = 1.2 V,
DAC12AMPx = 7, DAC12IR = 1
Offset voltage without calibration (1)
(2)
EO
Offset voltage with calibration (1)
(2)
dE(O)/dT
Offset error temperature coefficient (1)
EG
Gain error (1)
dE(G)/dT
Gain temperature coefficient (1)
tOffset_Cal
Time for offset calibration (3)
VREF,DAC12 = 1.2 V,
DAC12AMPx = 7, DAC12IR = 1
VREF,DAC12 = 1.2 V,
DAC12AMPx = 7, DAC12IR = 1
MAX
UNIT
±2.0
±8.0
LSB
±0.4
±1.3
±0.4
±1.0
±0.4
±1.0
mV
±2.5
±30
2.7 V
2.7 V
%FSR
ppm of
FSR/°C
10
100
DAC12AMPx = 3, 5
2.7 V
32
DAC12AMPx = 4, 6, 7
(2)
(3)
µV/°C
±3.50
DAC12AMPx = 2
(1)
LSB
±20
2.7 V
2.7 V
VREF,DAC12 = 1.2 V
TYP
ms
6
Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients “a” and “b” of
the first order equation: y = a + b × x. VDAC12_xOUT = EO + (1 + EG) × (VeREF+/4095) × DAC12_xDAT, DAC12IR = 1.
The offset calibration works on the output operational amplifier. Offset calibration is triggered by setting bit DAC12CALON.
The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx =
{0, 1}. TI recommends that the DAC12 module be configured before initiating calibration. Port activity during calibration may effect
accuracy and is not recommended.
DAC VOUT
DAC Output
V R+
R Load =
Ideal transfer
function
AVCC
2
Offset Error
C Load = 100pF
Gain Error
Positive
Negative
DAC Code
Figure 5-20. Linearity Test Load Conditions and Gain and Offset Definition
34
Specifications
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INL – Integral Nonlinearity Error – LSB
4
VCC = 2.2 V, VREF = 1.5 V
DAC12AMPx = 7
DAC12IR = 1
3
2
1
0
-1
-2
-3
-4
0
512
1024
1536
2048
2560
3072
3584
4095
DAC12_xDAT – Digital Code
Figure 5-21. Typical INL Error vs Digital Input Data
DNL - Differential Nonlinearity Error - LSB
2.0
VCC = 2.2 V, VREF = 1/.5 V
DAC12AMPx = 7
DAC12IR = 1
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
0
512
1024
1536
2048
2560
3072
3584
4095
DAC12_xDAT - Digital Code
Figure 5-22. Typical DNL Error vs Digital Input Data
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5.34 12-Bit DAC, Output Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
No load, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
No load, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
Output voltage range (1) (see
Figure 5-23)
VO
RLoad = 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
Maximum DAC12 load
capacitance
IL(DAC12)
Maximum DAC12 load current
0
0.005
AVCC –
0.05
AVCC
0
0.1
AVCC –
0.13
AVCC
2.2 V, 3 V
12)
Output resistance (see Figure 523)
RLoad = 3 kΩ,
VO/P(DAC12) > AVCC – 0.3 V,
DAC12_xDAT = 0FFFh
100
2.2 V
–0.5
+0.5
3V
–1.0
+1.0
2.2 V, 3 V
150
250
150
250
1
4
RLoad = 3 kΩ,
0.3 V ≤ VO/P(DAC12) ≤ AVCC – 0.3 V
(1)
UNIT
V
RLoad = 3 kΩ, VO/P(DAC12) < 0.3 V,
DAC12AMPx = 2, DAC12_xDAT = 0h
RO/P(DAC
MAX
2.2 V, 3 V
RLoad = 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
CL(DAC12)
TYP
pF
mA
Ω
Data is valid after the offset calibration of the output amplifier.
R O/P(DAC12_x)
Max
R Load
I Load
AVCC
DAC12
2
C Load = 100pF
O/P(DAC12_x)
Min
0.3
AVCC -0.3V
V OUT
AVCC
Figure 5-23. DAC12_x Output Resistance Tests
5.35
12-Bit DAC, Reference Input Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VeREF+
Reference input voltage
range
Ri(VREF+)
Reference input resistance
(1)
(2)
(3)
(4)
(5)
36
DAC12IR = 0 (1)
(2)
DAC12IR = 1 (3)
(4)
DAC12IR = 0, SD16VMIDON = 1 (5)
DAC12IR = 1, SD16VMIDON = 1
VCC
MIN
2.2 V, 3 V
2.2 V, 3 V
TYP
MAX
AVCC/3
AVCC + 0.2
AVCC
AVCC + 0.2
48
56
20
40
UNIT
V
MΩ
kΩ
For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / [3 × (1 + EG)].
For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / (1 + EG).
Characterized, not production tested
Specifications
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5.36
SLAS629B – MARCH 2009 – REVISED MAY 2020
12-Bit DAC, Dynamic Specifications
Vref = VCC, DAC12IR = 1, over recommended ranges of supply voltage and operating free-air temperature (unless otherwise
noted) (see Figure 5-24 and Figure 5-25)
PARAMETER
tON
TEST CONDITIONS
DAC12_xDAT = 800h,
ErrorV(O) < ±0.5 LSB (1)
(see Figure 5-24)
DAC12 on time
VCC
MIN
TYP MAX
DAC12AMPx = 0 → {2, 3, 4}
DAC12AMPx = 0 → {5, 6}
2.2 V, 3 V
DAC12AMPx = 0 → 7
DAC12AMPx = 2
tS(FS)
DAC12_xDAT =
80h→F7Fh→80h
Settling time, full scale
DAC12AMPx = 3, 5
2.2 V, 3 V
DAC12AMPx = 4, 6, 7
tS(C–C)
DAC12_xDAT =
3F8h→408h→3F8h
BF8h→C08h→BF8h
Settling time, code to code
DAC12AMPx = 2
DAC12_xDAT =
80h→F7Fh→80h (2)
Slew rate
DAC12AMPx = 3, 5
2.2 V, 3 V
12
100
200
40
80
15
30
2.2 V, 3 V
0.05
0.12
0.35
0.7
1.5
µs
µs
µs
V/µs
2.7
DAC12AMPx = 2
600
DAC12AMPx = 3,5
2.2 V, 3 V
150
DAC12AMPx = 4, 6, 7
(1)
(2)
30
6
UNIT
1
DAC12AMPx = 3,5
DAC12_xDAT =
80h→F7Fh→80h
15
2
DAC12AMPx = 4, 6, 7
DAC12AMPx = 4, 6, 7
Glitch energy, full-scale
120
5
DAC12AMPx = 2
SR
60
nV-s
30
RLoad and CLoad connected to AVSS (not AVCC/2) in Figure 5-24.
Slew rate applies to output voltage steps ≥200 mV.
Conversion 1
V OUT
DAC Output
I Load
R Load = 3 k W
Conversion 2
Conversion 3
+/- 1/2 LSB
Glitch
Energy
AVCC
2
R O/P(DAC12.x)
+/- 1/2 LSB
C Load = 100pF
t settleLH
t settleHL
Figure 5-24. Settling Time and Glitch Energy Testing
Conversion 1
Conversion 2
Conversion 3
V OUT
90%
90%
10%
10%
t SRLH
t SRHL
Figure 5-25. Slew Rate Testing
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5.37
www.ti.com
12-Bit DAC, Dynamic Specifications Continued
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
BW–3dB
3-dB bandwidth,
VDC = 1.5 V, VAC = 0.1 VPP
(see Figure 5-26)
2.2 V, 3 V
DAC12AMPx = 7, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
I Load
UNIT
40
DAC12AMPx = {5, 6}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
VeREF+
MAX
180
kHz
550
R Load = 3 k W
AVCC
DAC12_x
2
DACx
AC
C Load = 100pF
DC
Figure 5-26. Test Conditions for 3-dB Bandwidth Specification
5.38 Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTA
Timer_A clock frequency
Internal: SMCLK, ACLK
External: TACLK, INCLK
Duty cycle = 50% ±10%
tTA,cap
Timer_A capture timing
TA0, TA1, TA2
VCC
MIN
MAX
2.2 V
8
3V
10
2.2 V, 3 V
20
UNIT
MHz
ns
5.39 Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTA
Timer_B clock frequency
Internal: SMCLK, ACLK
External: TACLK, INCLK
Duty cycle = 50% ±10%
tTA,cap
Timer_B capture timing
TB0, TB1, TB2
38
Specifications
VCC
MIN
MAX
2.2 V
8
3V
10
2.2 V, 3 V
20
UNIT
MHz
ns
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5.40
SLAS629B – MARCH 2009 – REVISED MAY 2020
USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fUSCI
USCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baud rate in MBaud) (1)
tτ
UART receive deglitch time UART (2)
(1)
(2)
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ±10%
MAX UNIT
fSYSTEM MHz
2.2 V, 3 V
2
MHz
2.2 V
50
150
600
3V
50
100
600
ns
The DCO wake-up time must be considered in LPM3 or LPM4 for baud rates above 1 MHz.
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed.
5.41
USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (see Figure 5-27
and Figure 5-28)
PARAMETER
TEST CONDITIONS
fUSCI
USCI input clock frequency
tSU,MI
SOMI input data setup time
tHD,MI
iSOMI input data hold time
tVALID,MO
SIMO output data valid time
(1)
VCC
MIN
SMCLK, ACLK
Duty cycle = 50% ±10%
UCLK edge to SIMO valid, CL = 20 pF
2.2 V
110
3V
75
2.2 V
0
3V
0
MAX
UNIT
fSYSTEM
MHz
ns
ns
2.2 V
30
3V
20
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave))
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
5.42
USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (see Figure 5-29
and Figure 5-30)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP MAX UNIT
tSTE,LEAD
STE lead time
STE low to clock
2.2 V, 3 V
tSTE,LAG
STE lag time
Last clock to STE high
2.2 V, 3 V
tSTE,ACC
STE access time
STE low to SOMI data out
2.2 V, 3 V
50
ns
tSTE,DIS
STE disable time
STE high to SOMI high impedance
2.2 V, 3 V
50
ns
tSU,SI
SIMO input data setup time
tHD,SI
SIMO input data hold time
tVALID,SO
SOMI output data valid time
(1)
UCLK edge to SOMI valid, CL = 20 pF
50
ns
10
2.2 V
20
3V
15
2.2 V
10
3V
10
ns
ns
ns
2.2 V
75
110
3V
50
75
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI))
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
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1/fUCx CLK
CKPL
=0
CKPL
=1
UCLK
tLOW /HIGH
tLOW /HIGH
tSU ,MI
tHD ,MI
SOMI
tVALID ,MO
SIMO
Figure 5-27. SPI Master Mode, CKPH = 0
1/fUC xC LK
CKPL
=0
CKPL
=1
UCLK
tLOW /HIGH
tLOW /HIGH
tHD ,MI
tSU ,MI
SO MI
tVALID
,MO
SIMO
Figure 5-28. SPI Master Mode, CKPH = 1
40
Specifications
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tSTE ,LEAD
tSTE ,LAG
STE
1/fUCx CLK
CKPL
=0
CKPL
=1
UCLK
tLOW /HIGH
tLOW /HIGH
tSU ,SIMO
tHD ,SIMO
SIMO
tACC
tVALID ,SOMI
tDIS
SO MI
Figure 5-29. SPI Slave Mode, CKPH = 0
tSTE ,LEAD
tSTE ,LAG
STE
1/fUCx CLK
CKPL =0
UCLK
CKPL =1
tLOW /HIGH
tLOW /HIGH
tHD ,SI
tSU ,SI
SI MO
tACC
tVALID ,SO
tDIS
SO MI
Figure 5-30. SPI Slave Mode, CKPH = 1
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5.43
www.ti.com
USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-31)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty Cycle = 50% ±10%
MAX UNIT
fUSCI
USCI input clock frequency
fSCL
SCL clock frequency
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
2.2 V, 3 V
0
tSU,DAT
Data setup time
2.2 V, 3 V
250
ns
tSU,STO
Setup time for STOP
2.2 V, 3 V
4
µs
tSP
Pulse duration of spikes suppressed by
input filter
2.2 V
50
150
600
3V
50
100
600
t HD
fSYSTEM MHz
2.2 V, 3 V
0
fSCL ≤ 100 kHz
2.2 V, 3 V
4.0
fSCL > 100 kHz
2.2 V, 3 V
0.6
fSCL ≤ 100 kHz
2.2 V, 3 V
4.7
fSCL > 100 kHz
2.2 V, 3 V
0.6
tSU
, STA
, STA
t HD
400
kHz
µs
µs
ns
ns
tBUF
, STA
SDA
t
LOW
t HIGH
t SP
SCL
t SU , DAT
tHD
t SU
, STO
, DAT
Figure 5-31. I2C Mode Timing
42
Specifications
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5.44
SLAS629B – MARCH 2009 – REVISED MAY 2020
Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
VCC
MIN
TYP
MAX
UNIT
VCC(PGM/ERASE)
Program and erase supply voltage
2.2
3.6
V
fFTG
Flash timing generator frequency
257
476
kHz
IPGM
Supply current from DVCC during program
5
mA
IERASE
Supply current from DVCC during erase
7
mA
tCPT
Cumulative program time
10
ms
tCMErase
Cumulative mass erase time
(1)
2.5 V, 3.6 V
3
2.5 V, 3.6 V
3
2.5 V, 3.6 V
2.5 V, 3.6 V
200
ms
4
Program and erase endurance
5
10
Data retention duration
tWord
Word or byte program time
35
Block program time for 1st byte or word
30
tBlock,
0
TJ = 25°C
10
tRetention
years
tBlock, 1-63
Block program time for each additional byte or word
tBlock, End
Block program end-sequence wait time
tMass Erase
Mass erase time
5297
tSeg Erase
Segment erase time
4819
(1)
(2)
cycles
100
21
(2)
tFTG
6
The cumulative program time must not be exceeded when writing to a 64--byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/fFTG,max = 5297x1/476kHz). To achieve
the required cumulative mass erase time the flash controller’ mass erase operation can be repeated until this time is met. (A worst case
minimum of 19 cycles are required).
5.45
JTAG Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTCK
TCK input frequency
(1)
RInternal
Internal pullup resistance on TMS, TCK, TDI/TCLK
(2)
(1)
(2)
VCC
MIN
TYP
MAX
2.2 V
0
5
3V
0
10
2.2 V, 3 V
25
60
90
UNIT
MHz
kΩ
fTCK may be restricted to meet the timing requirements of the module selected.
TMS, TDI/TCLK, and TCK pullup resistors are implemented in all versions.
5.46
JTAG Fuse (1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VCC(FB)
Supply voltage during fuse-blow condition
VFB
Voltage level on TDI/TCLK for fuse-blow
IFB
Supply current into TDI/TCLK during fuse blow
tFB
Time to blow fuse
(1)
TEST CONDITIONS
TA = 25°C
MIN
MAX
2.5
6
UNIT
V
7
V
100
mA
1
ms
After the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched to
bypass mode.
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6 Detailed Description
6.1
CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and
constant generator, respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
Constant Generator
44
Detailed Description
SR/CG1/R2
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
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6.2
SLAS629B – MARCH 2009 – REVISED MAY 2020
Instruction Set
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word and
byte data. Table 6-1 shows examples of the three types of instruction formats; the address modes are
listed in Table 6-2.
Table 6-1. Instruction Word Formats
EXAMPLE
OPERATION
Dual operands, source-destination
FORMAT
ADD R4,R5
R4 + R5 → R5
Single operands, destination only
CALL R8
PC→ (TOS), R8 → PC
JNE
Jump-on-equal bit = 0
Relative jump, un/conditional
Table 6-2. Address Mode Descriptions
(1)
ADDRESS MODE
S (1)
D (1)
SYNTAX
EXAMPLE
Register
•
•
MOV Rs,Rd
MOV R10,R11
R10 → R11
Indexed
•
•
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
M(2+R5)→ M(6+R6)
Symbolic (PC relative)
•
•
MOV EDE,TONI
Absolute
•
•
MOV & MEM, & TCDAT
Indirect
•
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) → M(Tab+R6)
Indirect autoincrement
•
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) → R11
R10 + 2→ R10
Immediate
•
MOV #X,TONI
MOV #45,TONI
#45 → M(TONI)
OPERATION
M(EDE) → M(TONI)
M(MEM) → M(TCDAT)
NOTE: S = source D = destination
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6.3
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Operating Modes
These devices have one active mode and five software-selectable low-power modes of operation. An
interrupt event can wake up the device from any of the five low-power modes, service the request, and
restore back to the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active. MCLK is disabled
– FLL+ loop control remains active
• Low-power mode 1 (LPM1)
– CPU is disabled
– FLL+ loop control is disabled
– ACLK and SMCLK remain active. MCLK is disabled
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK, FLL+ loop control and DCOCLK are disabled
– DCO DC generator remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK, FLL+ loop control, and DCOCLK are disabled
– DCO DC generator is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK, FLL+ loop control, and DCOCLK are disabled
– DCO DC generator is disabled
– Crystal oscillator is stopped
46
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6.4
SLAS629B – MARCH 2009 – REVISED MAY 2020
Interrupt Vector Addresses
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FFC0h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
If the reset vector (located at address 0xFFFE) contains 0xFFFF (for example, flash is not programmed)
the CPU goes into LPM4 immediately after power-up.
Table 6-3. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
Power-Up
External Reset
Watchdog
Flash Memory
PC Out-of-Range (1)
PORIFG
RSTIFG
WDTIFG
KEYV (2)
Reset
0FFFEh
15, highest
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG (2) (3)
OFIFG (2) (3)
ACCVIFG (2) (4)
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh
14
Timer_B3
TBCCR0 CCIFG0 (4)
Maskable
0FFFAh
13
Timer_B3
TBCCR1 CCIFG1 and TBCCR2 CCIFG2,
TBIFG (2) (4)
Maskable
0FFF8h
12
Comparator_A
CAIFG
Maskable
0FFF6h
11
Watchdog Timer+
WDTIFG
Maskable
0FFF4h
10
USCI_A0, USCI_B0 Receive,
USCI_B0 I2C status
UCA0RXIFG, UCB0RXIFG (2) (5)
Maskable
0FFF2h
9
USCI_A0, USCI_B0 Transmit,
USCI_B0 I2C receive/transmit
UCA0TXIFG, UCB0TXIFG
(2) (6)
Maskable
0FFF0h
8
Maskable
0FFEEh
7
Maskable
0FFECh
6
Maskable
0FFEAh
5
Maskable
0FFE8h
4
Maskable
0FFE6h
3
Maskable
0FFE4h
2
Maskable
0FFE2h
1
Maskable
0FFE0h
0, lowest
SD16_A
SD16CCTLx SD16OVIFG, SD16CCTLx SD16IFG
(2) (4)
Timer_A3
Timer_A3
I/O Port P1 (8 Flags)
TACCR0 CCIFG0
TACCR1 CCIFG1 and TACCR2 CCIFG2,
TAIFG (2) (4)
P1IFG.0 to P1IFG.7 (2)
DAC12
I/O Port P2 (8 Flags)
(4)
(5)
(6)
(4)
DAC12_0IFG
P2IFG.0 to P2IFG.7
Basic Timer 1, RTC
(1)
(2)
(3)
(4)
BTIFG
(2) (4)
Access and key violations, KEYV and ACCVIFG.
Multiple source flags
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh).
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
Interrupt flags are located in the module.
In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.
In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.
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6.5
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Special Function Registers (SFRs)
The SFRs are in the lowest address space and are organized as byte mode registers. SFRs should be
accessed with byte instructions.
Legend
rw
Bit can be read and written.
rw-0, rw-1
Bit can be read and written. It is Reset or Set by PUC.
rw-(0), rw-(1)
Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device
6.5.1
Interrupt Enable 1 and 2
WDTIE
Watchdog timer interrupt enable. Inactive if watchdog mode is selected.
Active if watchdog timer is configured as a general-purpose timer.
OFIE
Oscillator fault-interrupt enable
NMIIE
Nonmaskable interrupt enable
ACCVIE
Flash access violation interrupt enable
UCA0RXIE USCI_A0 receive-interrupt enable
UCA0TXIE USCI_A0 transmit-interrupt enable
UCB0RXIE USCI_B0 receive-interrupt enable
UCB0TXIE USCI_B0 transmit-interrupt enable
BTIE
48
Basic timer interrupt enable
Detailed Description
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6.5.2
SLAS629B – MARCH 2009 – REVISED MAY 2020
Interrupt Flag Register 1 and 2
WDTIFG
Set on watchdog timer overflow (in watchdog mode) or security key violation
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode
OFIFG
Flag set on oscillator fault
RSTIFG
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset
on VCC power-up.
PORIFG
Power-on interrupt flag. Set on Vcs power-up.
NMIIFG
Set by the RST/NMI pin
UCA0RXIFG USCI_A0 receive-interrupt flag
UCA0TXIFG
USCI_A0 transmit-interrupt flag
UCB0RXIFG USCI_B0 receive-interrupt flag
UCB0TXIFG
USCI_B0 transmit-interrupt flag
BTIFG
Basic timer flag
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6.6
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Memory Organization
Table 6-4 summarizes the memory organization for the MSP430F47x MCUs.
Table 6-4. Memory Organization
MSP430F477
MSP430F478
MSP430F479
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
32KB
0FFFFh to 0FFE0h
0FFFFh to 08000h
48KB
0FFFFh to 0FFE0h
0FFFFh to 04000h
60KB
0FFFFh to 0FFE0h
0FFFFh to 01100h
Information memory
Size
Flash
256 Byte
010FFh to 01000h
256 Byte
010FFh to 01000h
256 Byte
010FFh to 01000h
Boot memory
Size
ROM
1KB
0FFFh to 0C00h
1KB
0FFFh to 0C00h
1KB
0FFFh to 0C00h
RAM
Size
2KB
09FFh to 0200h
2KB
09FFh to 0200h
2KB
09FFh to 0200h
16 bit
8 bit
8-bit SFR
01FFh to 0100h
0FFh to 010h
0Fh to 00h
01FFh to 0100h
0FFh to 010h
0Fh to 00h
01FFh to 0100h
0FFh to 010h
0Fh to 00h
Peripherals
6.7
Bootloader (BSL)
The BSL lets users program the flash memory or RAM using a UART serial interface. Access to the MCU
memory through the BSL is protected by user-defined password. A bootloader security key is provided at
address 0FFBEh to disable the BSL completely or to disable the erasure of the flash if an invalid
password is supplied. The BSL is optional for ROM-based devices. For complete description of the
features of the BSL and its implementation, see the MSP430™ Flash Devices Bootloader (BSL) User's
Guide.
6.8
BSL FUNCTION
PN PACKAGE
ZCA OR ZQW PACKAGE
Data Transmit
58 - P1.0
C11 - P1.0
Data Receiver
57 - P1.1
C12 - P1.1
Flash Memory
The flash memory can be programmed by the JTAG port, the bootloader, or in system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory
include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are
also called information memory.
• Segment A might contain calibration data. After reset, segment A is protected against programming or
erasing. It can be unlocked, but care should be taken not to erase this segment if the calibration data is
required.
• Flash content integrity check with marginal read modes.
50
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6.9
SLAS629B – MARCH 2009 – REVISED MAY 2020
Peripherals
Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be
handled using all instructions. For complete module descriptions, refer to the MSP430x4xx Family User’s
Guide.
6.9.1
Oscillator and System Clock
The clock system is supported by the FLL+ module, which includes support for a 32768-Hz watch crystal
oscillator, an internal digitally-controlled oscillator (DCO), and a 8-MHz high-frequency crystal oscillator
(XT1), plus a 8-MHz high-frequency crystal oscillator (XT2). The FLL+ clock module is designed to meet
the requirements of both low system cost and low power consumption. The FLL+ features digital
frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO
frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast
turn-on clock source and stabilizes in less than 6 s. The FLL+ module provides the following clock signals:
• Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal
• Main clock (MCLK), the system clock used by the CPU
• Submain clock (SMCLK), the subsystem clock used by the peripheral modules
• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8
6.9.2
Brownout, Supply Voltage Supervisor (SVS)
The brownout circuit provides the proper internal reset signal to the device during power-on and power-off.
The SVS circuitry detects if the supply voltage drops below a user-selectable level and supports both
supply voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is
not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may
not have ramped to VCC(min) at that time. The user must make sure the default FLL+ settings are not
changed until VCC reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC
reaches VCC(min).
6.9.3
Digital I/O
There are six 8-bit I/O ports implemented—ports P1 through P6:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
• Read and write access to port-control registers is supported by all instructions
6.9.4
Watchdog Timer (WDT+)
The primary function of the WDT+ module is to perform a controlled system restart after a software
problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function
is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
6.9.5
Basic Timer1 and Real-Time Clock
The Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter.
Both timers can be read and written by software. Basic Timer1 is extended to provide an integrated realtime clock (RTC). An internal calendar compensates for months with less than 31 days and includes leapyear correction.
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6.9.6
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LCD_A Drive With Regulated Charge Pump
The LCD_A driver generates the segment and common signals required to drive an LCD display. The
LCD_A controller has dedicated data memory to hold segment drive information. Common and segment
signals are generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by
this peripheral. The module can provide a LCD voltage independent of the supply voltage via an
integrated charge pump. Furthermore, it is possible to control the level of the LCD voltage and, thus,
contrast in software.
6.9.7
Timer_A3
Timer_A3 is a 16-bit timer or counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 6-5. Timer_A3 Signal Connections
INPUT PIN NUMBER
PN
ZCA OR ZQW
DEVICE INPUT
SIGNAL
P1.5 - 51
F11
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
NA
OUTPUT PIN NUMBER
PN
ZCA OR ZQW
P1.5 - 51
F11
TAINCLK
INCLK
P1.0 - 58
C11
TA0
CCI0A
P1.0 - 58
C11
P1.1 - 57
C12
TA0
CCI0B
P1.1 - 57
C12
DVSS
GND
P1.2 - 56
D11
P2.0 - 4
C2
P1.2 - 56
P2.0 - 4
52
MODULE
INPUT NAME
D11
C2
Detailed Description
DVCC
VCC
TA1
CCI1A
CAOUT
(internal)
CCI1B
DVSS
GND
DVCC
VCC
TA2
CCI2A
ACLK (internal)
CCI2B
DVSS
GND
DVCC
VCC
CCR0
CCR1
CCR2
TA0
TA1
TA2
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6.9.8
SLAS629B – MARCH 2009 – REVISED MAY 2020
Timer_B3
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 6-6. Timer_B3 Signal Connections
INPUT PIN NUMBER
PN
ZCA OR ZQW
DEVICE INPUT
SIGNAL
P1.4 - 54
E11
TBCLK
TBCLK
ACLK
ACLK
SMCLK
SMCLK
P1.4 - 54
E11
TBCLK (1)
INCLK
P2.1 - 3
C1
TB0
CCI0A
P2.1 - 3
C1
TB0
CCI0B
VSS
GND
VCC
VCC
P2.2 - 2
B1
TB1
CCI1A
P2.2 - 2
B1
TB1
CCI1B
VSS
GND
P2.3 - 77
(1)
MODULE
INPUT NAME
B4
VCC
VCC
TB2
CCI2A
ACLK (internal)
CCI2B
VSS
GND
VCC
VCC
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
NA
CCR0
CCR1
CCR2
OUTPUT PIN NUMBER
PN
ZCA OR ZQW
P2.1 - 3
C1
P2.2 - 2
B1
P2.3 - 77
B4
TB0
TB1
TB2
The inversion of TBCLK is done inside the module.
6.9.9
Universal Serial Communication Interface (USCI)
The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols like SPI (3-pin or 4-pin), I2C, and asynchronous communication protocols like
UART, enhanced UART with automatic baudrate detection, and IrDA.
The USCI_A0 module provides support for SPI (3-pin or 4-pin), UART, enhanced UART and IrDA.
The USCI_B0 module provides support for SPI (3-pin or 4-pin) and I2C.
6.9.10 Comparator_A
The primary function of the comparator_A module is to support precision slope analog-to-digital
conversions, battery-voltage supervision, and monitoring of external analog signals.
6.9.11 SD16_A
The SD16_A module supports 16-bit analog-to-digital conversions. The module implements a 16-bit
sigma-delta core and a reference generator. In addition to external analog inputs, an internal VCC sense
and temperature sensor are also available.
6.9.12 DAC12
The DAC12 module is a 12-bit R-ladder voltage-output DAC. The DAC12 can be used in 8-bit or 12-bit
mode and can be used in conjunction with the DMA controller. When multiple DAC12 modules are
present, they may be grouped together for synchronous operation.
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6.9.13 Peripheral File Map
Table 6-7 lists the registers and addresses for peripherals with word access. Table 6-8 lists the registers
and addresses for peripherals with byte access.
Table 6-7. Peripherals With Word Access
MODULE
Watchdog
ACRONYM
ADDRESS
Watchdog timer control
REGISTER NAME
WDTCTL
0120h
Capture/compare register 2
TBCCR2
0 96h
Capture/compare register 1
TBCCR1
0 94h
Capture/compare register 0
TBCCR0
0192h
TBR
0190h
Capture/compare control 2
TBCCTL2
0186h
Capture/compare control 1
TBCCTL1
0184h
Capture/compare control 0
TBCCTL0
0182h
TBCTL
0180h
Timer_B register
Timer_B3
Timer_B control
Timer_B interrupt vector
TBIV
011Eh
Capture/compare register 2
TACCR1
0176h
Capture/compare register 1
TACCR1
0174h
Capture/compare register 0
TACCR0
0172h
TAR
0170h
Capture/compare control 2
TACCTL2
0166h
Capture/compare control 1
TACCTL1
0164h
Capture/compare control 0
TACCTL0
0162h
Timer_A register
Timer_A3
Timer_A control
TACTL
0160h
TAIV
012Eh
Flash control 4
FCTL4
01BEh
Flash control 3
FCTL3
012Ch
Flash control 2
FCTL2
012Ah
Timer_A interrupt vector
Flash
DAC12
Flash control 1
FCTL1
0128h
DAC12_0 data
DAC12_0DAT
01C8h
DAC12_0 control
DAC12_0CTL
01C0h
General control
SD16_A (also see
Table 6-8)
SD16CTL
0100h
Channel 0 control
SD16CCTL0
0102h
Channel 0 conversion memory
SD16MEM0
0112h
SD16IV
0110h
Interrupt vector word register
54
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Table 6-8. Peripherals With Byte Access
ACRONYM
ADDRESS
SD16_A (also see
Table 6-7)
MODULE
Channel 0 input control
Analog enable
SD16INCTL0
SD16AE
0B0h
0B7h
LCD_A
LCD Voltage Control 1
LCD Voltage Control 0
LCD Voltage Port Control 1
LCD Voltage Port Control 0
LCD memory 20
:
LCD memory 16
LCD memory 15
:
LCD memory 1
LCD control and mode
LCDAVCTL1
LCDAVCTL0
LCDAPCTL1
LCDAPCTL0
LCDM20
:
LCDM16
LCDM15
:
LCDM1
LCDCTL
0AFh
0AEh
0ADh
0ACh
0A4h
:
0A0h
09Fh
:
091h
090h
USCI
USCI
USCI
USCI
USCI
USCI
USCI
USCI
USCI
USCI
USCI
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
auto baud rate control
transmit buffer
receive buffer
status
modulation control
baud rate control 1
baud rate control 0
control 1
control 0
IrDA receive control
IrDA transmit control
UCA0ABCTL
UCA0TXBUF
UCA0RXBUF
UCA0STAT
UCA0MCTL
UCA0BR1
UCA0BR0
UCA0CTL1
UCA0CTL0
UCA0IRRCTL
UCA0IRTCTL
0x005D
0x0067
0x0066
0x0065
0x0064
0x0063
0x0062
0x0061
0x0060
0x005F
0x005E
USCI
USCI
USCI
USCI
USCI
USCI
USCI
USCI
USCI
USCI
B0
B0
B0
B0
B0
B0
B0
B0
B0
B0
transmit buffer
receive buffer
status
I2C Interrupt enable
baud rate control 1
baud rate control 0
control 1
control 0
I2C slave address
I2C own address
UCB0TXBUF
UCB0RXBUF
UCB0STAT
UCB0CIE
UCB0BR1
UCB0BR0
UCB0CTL1
UCB0CTL0
UCB0SA
UCB0OA
0x006F
0x006E
0x006D
0x006C
0x006B
0x006A
0x0069
0x0068
0x011A
0x0118
USCI_A0, USCI_B0
REGISTER NAME
Comparator_A
Comparator_A port disable
Comparator_A control 2
Comparator_A control 1
CAPD
CACTL2
CACTL1
05Bh
05Ah
059h
Brownout, SVS
SVS control register (reset by brownout signal)
SVSCTL
056h
FLL+ Clock
FLL+ Control 1
FLL+ Control 0
System clock frequency control
System clock frequency integrator
System clock frequency integrator
FLL_CTL1
FLL_CTL0
SCFQCTL
SCFI1
SCFI0
054h
053h
052h
051h
050h
RTC
(Basic Timer 1)
Real Time Clock Year High Byte
Real Time Clock Year Low Byte
Real Time Clock Month
Real Time Clock Day of Month
Basic Timer1 Counter 2
Basic Timer1 Counter 1
Real Time Counter 4 (Real Time
Real Time Counter 3 (Real Time
Real Time Counter 2 (Real Time
Real Time Counter 1 (Real Time
Real Time Clock Control
Basic Timer1 Control
RTCYEARH
RTCYEARL
RTCMON
RTCDAY
BTCNT2
BTCNT1
RTCNT4 (RTCDOW)
RTCNT3 (RTCHOUR)
RTCNT2 (RTCMIN)
RTCNT1 (RTCSEC)
RTCCTL
BTCTL
04Fh
04Eh
04Dh
04Ch
047h
046h
045h
044h
043h
042h
041h
040h
Port P6
Port
Port
Port
Port
P6
P6
P6
P6
selection
direction
output
input
P6SEL
P6DIR
P6OUT
P6IN
037h
036h
035h
034h
Port P5
Port
Port
Port
Port
P5
P5
P5
P5
selection
direction
output
input
P5SEL
P5DIR
P5OUT
P5IN
033h
032h
031h
030h
Clock
Clock
Clock
Clock
Day of Week)
Hour)
Minute)
Second)
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Table 6-8. Peripherals With Byte Access (continued)
MODULE
ACRONYM
ADDRESS
Port P4
Port
Port
Port
Port
P4
P4
P4
P4
selection
direction
output
input
P4SEL
P4DIR
P4OUT
P4IN
01Fh
01Eh
01Dh
01Ch
Port P3
Port
Port
Port
Port
P3
P3
P3
P3
selection
direction
output
input
P3SEL
P3DIR
P3OUT
P3IN
01Bh
01Ah
019h
018h
Port P2
Port
Port
Port
Port
Port
Port
Port
P2
P2
P2
P2
P2
P2
P2
selection
interrupt enable
interrupt-edge select
interrupt flag
direction
output
input
P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
Port P1
Port
Port
Port
Port
Port
Port
Port
P1
P1
P1
P1
P1
P1
P1
selection
interrupt enable
interrupt-edge select
interrupt flag
direction
output
input
P1SEL
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN
026h
025h
024h
023h
022h
021h
020h
Special functions
SFR module enable 2
SFR module enable 1
SFR interrupt flag 2
SFR interrupt flag 1
SFR interrupt enable 2
SFR interrupt enable 1
ME2
ME1
IFG2
IFG1
IE2
IE1
005h
004h
003h
002h
001h
000h
56
Detailed Description
REGISTER NAME
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6.10 Input/Output Schematics
6.10.1 Port P1, P1.0, Input/Output With Schmitt Trigger
Table 6-9. Port P1 (P1.0) Pin Functions
PIN NAME (P1.X)
P1.0/TA0
(1)
X
0
FUNCTION
CONTROL BITS / SIGNALS (1)
CAPD.x
P1DIR.x
P1SEL.x
P1SEL2.x
P1.x (I/O)
0
I: 0, O: 1
0
0
Timer_A3.CCI0A
0
0
1
0
Timer_A3.TA0
0
1
1
0
x = don't care
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6.10.2 Port P1, P1.1, Input/Output With Schmitt Trigger
Table 6-10. Port P1 (P1.1) Pin Functions
PIN NAME (P1.X)
P1.1/TA0/MCLK
(1)
58
X
1
FUNCTION
CONTROL BITS / SIGNALS (1)
CAPD.x
P1DIR.x
P1SEL.x
P1SEL2.x
P1.x (I/O)
0
I: 0, O: 1
0
0
Timer_A3.CCI0A
0
0
1
0
Timer_A3.TA0
0
1
1
0
MCLK
0
1
1
1
x = don't care
Detailed Description
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6.10.3 Port P1, P1.2, Input/Output With Schmitt Trigger
Table 6-11. Port P1 (P1.2) Pin Functions
CONTROL BITS / SIGNALS (1)
PIN NAME (P1.X)
P1.2/TA1/A4-
(1)
X
2
FUNCTION
CAPD.x
P1DIR.x
P1SEL.x
P1SEL2.x = 0
SD16AE.x
P1.x (I/O)
0
I: 0, O: 1
0
0
Timer_A3.CCI1A
0
0
1
0
Timer_A3.TA1
0
1
1
0
A4-
x
x
x
1
x = don't care
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6.10.4 Port P1, P1.3, Input/Output With Schmitt Trigger
Table 6-12. Port P1 (P1.3) Pin Functions
CONTROL BITS / SIGNALS (1)
PIN NAME (P1.X)
P1.3/TBOUTH/
SVSOUT/A4+
(1)
60
X
3
FUNCTION
CAPD.x
P1DIR.x
P1SEL.x
P1SEL2.x = 0
SD16AE.x
P1.x (I/O)
0
I: 0, O: 1
0
0
TBOUTH
0
0
1
0
SVSOUT
0
1
1
0
A4+
x
x
x
1
x = don't care
Detailed Description
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6.10.5 Port P1, P1.4, Input/Output With Schmitt Trigger
Table 6-13. Port P1 (P1.4) Pin Functions
CONTROL BITS / SIGNALS (1)
PIN NAME (P1.X)
P1.4/TBCLK/SMCLK/A3-
(1)
X
4
FUNCTION
P1DIR.x
P1SEL.x
P1SEL2.x = 0
SD16AE.x
P1.x (I/O)
I: 0, O: 1
0
0
TBCLK
0
1
0
SMCLK
1
1
0
A3-
x
x
1
CAPD.x
x = don't care
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6.10.6 Port P1, P1.5, Input/Output With Schmitt Trigger
Table 6-14. Port P1 (P1.5) Pin Functions
CONTROL BITS / SIGNALS (1)
PIN NAME (P1.X)
P1.5/ACLK/ACLK/A3+
(1)
62
X
5
FUNCTION
CAPD.x
P1DIR.x
P1SEL.x
P1SEL2.x = 0
SD16AE.x
P1.x (I/O)
0
I: 0, O: 1
0
0
TACLK
0
0
1
0
ACLK
0
1
1
0
A3+
x
x
x
1
x = don't care
Detailed Description
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6.10.7 Port P1, P1.6, Input/Output With Schmitt Trigger
Table 6-15. Port P1 (P1.6) Pin Functions
CONTROL BITS / SIGNALS (1)
PIN NAME (P1.X)
P1.6/CA0/A2-/DAC0
(1)
X
6
FUNCTION
P1SEL2.x = 0
CAPD.x
P1SEL2.x = 0
SD16AE.x
P1SEL2.x = 0
DAC12OPS
(DAC12_0)
0
0
0
0
x
1 or selected
x
x
x
x
x
1
x
x
x
x
x
1
P1DIR.x
P1SEL.x
P1.x (I/O)
I: 0, O: 1
CA0
x
A2DAC0
x = don't care
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6.10.8 Port P1, P1.7, Input/Output With Schmitt Trigger
Table 6-16. Port P1 (P1.7) Pin Functions
CONTROL BITS / SIGNALS (1)
(1)
64
PIN NAME (P1.X)
X
P1.7/CA1/A2+
7
FUNCTION
P1SEL2.x = 0
CAPD.x
P1SEL2.x = 0
SD16AE.x
0
0
0
x
1 or selected
x
x
x
1
P1DIR.x
P1SEL.x
P1.x (I/O)
I: 0, O: 1
CA1
x
A2+
x
x = don't care
Detailed Description
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6.10.9 Port P2, P2.0 and P2.1, Input/Output With Schmitt Trigger
Table 6-17. Port P2 (P2.0 and P2.1) Pin Functions
PIN NAME (P2.X)
P2.0/TA2/S1
P2.1/TB0/S0
(1)
X
0
1
FUNCTION
CONTROL BITS / SIGNALS (1)
P2DIR.x
P2SEL.x
LCDS0
P2.x (I/O)
I: 0, O: 1
0
0
Timer_A3.CCI2A
0
1
0
Timer_A3.TA2
1
1
0
S1
x
x
1
P2.x (I/O)
I: 0, O: 1
0
0
Timer_B3.CCI0A
0
1
0
Timer_B3.TB0
1
1
0
S0
x
x
1
x = don't care
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Port P2, P2.2 and P2.3, Input/Output With Schmitt Trigger
Table 6-18. Port P2 (P2.2 and P2.3) Pin Functions
PIN NAME (P2.X)
P2.2/TB1
P2.3/TB2
66
Detailed Description
X
2
3
FUNCTION
CONTROL BITS / SIGNALS
P2DIR.x
P2SEL.x
P2.x (I/O)
I: 0, O: 1
0
Timer_B3.CCI1A
0
1
Timer_B3.TB1
1
1
P2.x (I/O)
I: 0, O: 1
0
Timer_B3.CCI2A
0
1
TimerB3.TB2
1
1
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6.10.11 Port P2, P2.4 and P2.5, Input/Output With Schmitt Trigger
Table 6-19. Port P2 (P2.4 and P2.5) Pin Functions
PIN NAME (P2.X)
X
P2.4/UCA0TXD/UCA0SIMO
4
P2.5/UCA0RXD/UCA0SOMI
(1)
(2)
5
FUNCTION
CONTROL BITS / SIGNALS (1)
P2DIR.x
P2SEL.x
P2.x (I/O)
I: 0, O: 1
0
UCA0TXD/UCA0SIMO (2)
x
1
P2.x (I/O)
I: 0, O: 1
0
UCA0RXD/UCA0SOMI (2)
x
1
x = don't care
The pin direction is controlled by the USCI module.
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6.10.12 Port P2, P2.6 and P2.7, Input/Output With Schmitt Trigger
Table 6-20. Port P2 (P2.6 and P2.7) Pin Functions
PIN NAME (P2.X)
X
P2.6/CAOUT/S2
6
P2.7/S3
(1)
68
7
CONTROL BITS / SIGNALS (1)
FUNCTION
P2DIR.x
P2SEL.x
LCDS0
P2.x (I/O)
I: 0, O: 1
0
0
CAOUT
1
1
0
S2
x
x
1
P2.x (I/O)
I: 0, O: 1
0
0
Vss
1
1
0
S3
x
x
1
x = don't care
Detailed Description
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6.10.13 Port P3, P3.0 and P3.3, Input/Output With Schmitt Trigger
Table 6-21. Port P3 (P3.0 and P3.3) Pin Functions
PIN NAME (P3.X)
X
P3.0/UCB0STE/UCA0CLK
0
P3.3/UCB0CLK/UCA0STE
(1)
(2)
3
CONTROL BITS / SIGNALS (1)
FUNCTION
P3DIR.x
P3SEL.x
P3.x (I/O)
I: 0, O: 1
0
UCB0STE/UCA0CLK (2)
x
1
P3.x (I/O)
I: 0, O: 1
0
x
1
UCB0CLK/UCA0STE
(2)
x = don't care
The pin direction is controlled by the USCI module.
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6.10.14 Port P3, P3.1 and P3.2, Input/Output With Schmitt Trigger
Table 6-22. Port P3 (P3.1 and P3.2) Pin Functions
PIN NAME (P3.X)
P3.1/UCB0SIMO/UCB0SDA/S2
6
P3.2/UCB00SOMI/UCB0SCL/S
27
(1)
(2)
(3)
70
X
1
2
FUNCTION
CONTROL BITS / SIGNALS (1)
P3DIR.x
P3SEL.x
LCDS24
P3.x (I/O)
I: 0, O: 1
0
0
UCB0SIMO/UCB0SD
A (2) (3)
x
1
0
S26
x
x
1
P3.x (I/O)
I: 0, O: 1
0
0
UCB0SOMI/UCB0SC
L (2) (3)
x
1
0
S27
x
x
1
x = don't care
The pin direction is controlled by the USCI module.
In case the I2C functionality is selected the output drives only the logical 0 to VSSlevel.
Detailed Description
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6.10.15 Port P3, P3.4 to P3.7, Input/Output With Schmitt Trigger
Table 6-23. Port P3 (P3.4 to P3.7) Pin Functions
PIN NAME (P3.X)
P3.4/S28
4
P3.5/S29
5
P3.6/S30
P3.7/S31
(1)
X
6
7
FUNCTION
CONTROL BITS / SIGNALS (1)
P3DIR.x
P3SEL.x
LCDS28
P3.x (I/O)
I: 0, O: 1
0
0
S28
x
x
1
P3.x (I/O)
I: 0, O: 1
0
0
S29
x
x
1
P3.x (I/O)
I: 0, O: 1
0
0
S30
x
x
1
P3.x (I/O)
I: 0, O: 1
0
0
S31
x
x
1
x: Don't care
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6.10.16 Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
Table 6-24. Port P4 (P4.0 to P4.7) Pin Functions
PIN NAME (P4.X)
X
P4.0/S11
0
P4.1/S10
1
P4.2/S9
2
P4.3/S8
(1)
72
3
P4.4/S7
4
P4.5/S6
5
P4.6/S5
6
P4.7/S4
7
FUNCTION
CONTROL BITS / SIGNALS (1)
P4DIR.x
P4SEL.x
LCDS4/8
P4.x (I/O)
I: 0, O: 1
0
0 (LCDS8)
S11
x
x
1 (LCDS8)
P4.x (I/O)
I: 0, O: 1
0
0 (LCDS8)
S10
x
x
1 (LCDS8)
P4.x (I/O)
I: 0, O: 1
0
0 (LCDS8)
S9
x
x
1 (LCDS8)
P4.x (I/O)
I: 0, O: 1
0
0 (LCDS8)
S8
x
x
1 (LCDS8)
P4.x (I/O)
I: 0, O: 1
0
0 (LCDS4)
S7
x
x
1 (LCDS4)
P4.x (I/O)
I: 0, O: 1
0
0 (LCDS4)
S6
x
x
1 (LCDS4)
P4.x (I/O)
I: 0, O: 1
0
0 (LCDS4)
S5
x
x
1 (LCDS4)
P4.x (I/O)
I: 0, O: 1
0
0 (LCDS4)
S4
x
x
1 (LCDS4)
x = don't care
Detailed Description
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6.10.17 Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
Table 6-25. Port P5 (P5.0 and P5.1) Pin Functions
PIN NAME (P5.X)
X
P5.0/S20
0
P5.1/S21
(1)
FUNCTION
1
CONTROL BITS / SIGNALS
(1)
P5DIR.x
P5SEL.x
LCDS20
P5.x (I/O)
I: 0, O: 1
0
0
S20
x
x
1
P5.x (I/O)
I: 0, O: 1
0
0
S21
x
x
1
x = don't care
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6.10.18 Port P5, P5.2 to P5.7, Input/Output With Schmitt Trigger
Table 6-26. Port P5 (P5.2 to P5.7) Pin Functions
PIN NAME (P5.X)
X
P5.2/COM1
2
P5.3/COM2
3
P5.4/COM3
4
P5.5/R23
(1)
74
5
P5.6/LCDREF/R13
6
P5.7/R03
7
FUNCTION
CONTOL BITS / SIGNALS (1)
P5DIR.x
P5SEL.x
P5.x (I/O)
I: 0, O: 1
0
COM1
x
1
P5.x (I/O)
I: 0, O: 1
0
COM2
x
1
P5.x (I/O)
I: 0, O: 1
0
COM3
x
1
P5.x (I/O)
I: 0, O: 1
0
R23
x
1
P5.x (I/O)
I: 0, O: 1
0
R13 or LCDREF
x
1
P5.x (I/O)
I: 0, O: 1
0
R03
x
1
x = don't care
Detailed Description
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6.10.19 Port P6, P6.0 and P6.3, Input/Output With Schmitt Trigger
Table 6-27. Port P6 (P6.0 and P6.3) Pin Functions
PIN NAME (P6.X)
X
P6.0/A0+
0
P6.3/A1+
(1)
3
FUNCTION
CONTROL BITS / SIGNALS (1)
P6DIR.x
P6SEL.x
P6.x (I/O)
I: 0, O: 1
0
A0+
x
1
P6.x (I/O)
I: 0, O: 1
0
A1+
x
1
x = don't care
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6.10.20 Port P6, P6.1 and P6.4, Input/Output With Schmitt Trigger
Table 6-28. Port P6 (P6.1 and P6.4) Pin Functions
PIN NAME (P6.X)
X
P6.1/A0-
1
P6.4/A1(1)
76
4
FUNCTION
CONTROL BITS / SIGNALS (1)
P6DIR.x
P6SEL.x
P6.x (I/O)
I: 0, O: 1
0
A0-
x
1
P6.x (I/O)
I: 0, O: 1
0
A1-
x
1
x = don't care
Detailed Description
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6.10.21 Port P6, P6.2, P6.5, and P6.6, Input/Output With Schmitt Trigger
Table 6-29. Port P6 (P6.2, P6.5, and P6.6) Pin Functions
(1)
CONTROL BITS / SIGNALS (1)
PIN NAME (P6.X)
X
FUNCTION
P6DIR.x
P6SEL.x
P6.2
2
P6.x (I/O)
I: 0, O: 1
0
P6.5
5
P6.x (I/O)
I: 0, O: 1
0
P6.6
6
P6.x (I/O)
I: 0, O: 1
0
x = don't care
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6.10.22 Port P6, P6.7, Input/Output With Schmitt Trigger
Table 6-30. Port P6 (P6.7) Pin Functions
78
PIN NAME (P6.X)
X
P6.7/SVSIN
7
Detailed Description
FUNCTION
CONTROL BITS / SIGNALS
P6DIR.x
P6SEL.x
VLDx
P6.x (I/O)
I: 0, O: 1
0
x
SVSIN
x
1
1111
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6.10.23 Segment Pin Schematic: Sx, Dedicated Segment Pins
Table 6-31. Sx Pin Functions
PIN NAME (P6.X)
X
Sx
12
Sx
13
Sx
14
Sx
FUNCTION
15
Sx
16
Sx
17
Sx
18
Sx
19
Sx
22
Sx
23
Sx
24
Sx
25
CONTROL BITS / SIGNALS
LCDSy
Sx
1 (LCDS12)
3-state
0 (LCDS12)
Sx
1 (LCDS12)
3-state
0 (LCDS12)
Sx
1 (LCDS12)
3-state
0 (LCDS12)
Sx
1 (LCDS12)
3-state
0 (LCDS12)
Sx
1 (LCD16)
3-state
0 (LCD16)
Sx
1 (LCD16)
3-state
0 (LCD16)
Sx
1 (LCD16)
3-state
0 (LCD16)
Sx
1 (LCDS16)
3-state
0 (LCDS16)
Sx
1 (LCDS20)
3-state
0 (LCDS20)
Sx
1 (LCDS20)
3-state
0 (LCDS20)
Sx
1 (LCDS24)
3-state
0 (LCDS24)
Sx
1 (LCDS24)
3-state
0 (LCDS24)
6.10.24 Segment Pin Schematic: COM0, Dedicated COM0 Pin
Table 6-32. COM0 Pin Functions
PIN NAME
X
FUNCTION
COM0
--
COM0
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6.10.25 JTAG Pins TMS, TCK, TDI/TCLK, TDO/TDI, Input/Output With Schmitt Trigger or Output
6.10.26 JTAG Fuse Check Mode
For details on the JTAG fuse check mode, see the MSP430x4xx Family User's Guide.
80
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7 Device and Documentation Support
7.1
Device Support
7.1.1
Getting Started and Next Steps
For more information on the MSP430F4x family of devices and the tools and libraries that are available to
help with your development, visit the MSP430™ ultra-low-power sensing & measurement MCUs overview
page.
7.1.2
Development Tools Support
All MSP430™ microcontrollers are supported by a wide variety of software and hardware development
tools. Tools are available from TI and various third parties. See them all at www.ti.com/msp430tools.
7.1.2.1
Recommended Hardware Options
7.1.2.1.1 Target Socket Boards
The target socket boards allow easy programming and debugging of the device using JTAG. They also
feature header pin outs for prototyping. Target socket boards are orderable individually or as a kit with the
JTAG programmer and debugger included. The following table shows the compatible target boards and
the supported packages.
Package
Target Board and Programmer Bundle
Target Board Only
80-pin LQFP (PN)
MSP-FET430U80
MSP-TS430PN80
7.1.2.1.2 Experimenter Boards
Experimenter Boards and Evaluation kits are available for some MSP430 devices. These kits feature
additional hardware components and connectivity for full system evaluation and prototyping. See
www.ti.com/msp430tools for details.
7.1.2.1.3 Debugging and Programming Tools
Hardware programming and debugging tools are available from TI and from its third party suppliers. See
the full list of available tools at www.ti.com/msp430tools.
7.1.2.1.4 Production Programmers
The production programmers expedite loading firmware to devices by programming several devices
simultaneously.
Part Number
PC Port
MSP-GANG
Serial and USB
7.1.2.2
Features
Program up to eight devices at a time. Works with PC or standalone.
Provider
Texas Instruments
Recommended Software Options
7.1.2.2.1 Integrated Development Environments
Software development tools are available from TI or from third parties. Open source solutions are also
available.
This device is supported by Code Composer Studio™ IDE (CCS).
Device and Documentation Support
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7.1.2.2.2 MSP430Ware
MSP430Ware is a collection of code examples, data sheets, and other design resources for all MSP430
devices delivered in a convenient package. In addition to providing a complete collection of existing
MSP430 design resources, MSP430Ware also includes a high-level API called MSP430 Driver Library.
This library makes it easy to program MSP430 hardware. MSP430Ware is available as a component of
CCS or as a standalone package.
7.1.2.2.3 Command-Line Programmer
MSP430 Flasher is an open-source shell-based interface for programming MSP430 microcontrollers
through a FET programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP430 Flasher
can be used to download binary files (.txt or .hex) files directly to the MSP430 microcontroller without the
need for an IDE.
7.1.3
Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS.
These prefixes represent evolutionary stages of product development from engineering prototypes (XMS)
through fully qualified production devices (MSP).
XMS – Experimental device that is not necessarily representative of the final device's electrical
specifications
MSP – Fully qualified production device
XMS devices are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices have been characterized fully, and the quality and reliability of the device have been
demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production
devices. TI recommends that these devices not be used in any production system because their expected
end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
temperature range, package type, and distribution format. Figure 7-1 provides a legend for reading the
complete device name.
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MSP 430 F 5 438 A I PM T -EP
Processor Family
Optional: Additional Features
MCU Platform
Optional: Tape and Reel
Device Type
Packaging
Series
Feature Set
Processor Family
Optional: Temperature Range
Optional: Revision
CC = Embedded RF Radio
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
430 = MSP430 low-power microcontroller platform
MCU Platform
Device Type
Memory Type
C = ROM
F = Flash
FR = FRAM
G = Flash
L = No nonvolatile memory
Specialized Application
AFE = Analog front end
BQ = Contactless power
CG = ROM medical
FE = Flash energy meter
FG = Flash medical
FW = Flash electronic flow meter
Series
1 = Up to 8 MHz
2 = Up to 16 MHz
3 = Legacy
4 = Up to 16 MHz with LCD driver
5 = Up to 25 MHz
6 = Up to 25 MHz with LCD driver
0 = Low-voltage series
Feature Set
Various levels of integration within a series
Optional: Revision
Updated version of the base part number
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging
http://www.ti.com/packaging
Optional: Tape and Reel
T = Small reel
R = Large reel
No markings = Tube or tray
Optional: Additional Features -EP = Enhanced product (–40°C to 105°C)
-HT = Extreme temperature parts (–55°C to 150°C)
-Q1 = Automotive Q100 qualified
Figure 7-1. Device Nomenclature
Device and Documentation Support
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7.2
www.ti.com
Documentation Support
The following documents describe the MSP430F47x devices. Copies of these documents are available on
the Internet at www.ti.com.
7.3
SLAU056
MSP430F4xx Family User's Guide. Detailed information on the modules and peripherals
available in this device family.
SLAZ243
MSP430F479 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revisions of the device.
SLAZ240
MSP430F478 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revisions of the device.
SLAZ239
MSP430F477 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revisions of the device.
Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 7-1. Related Links
7.4
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
MSP430F479
Click here
Click here
Click here
Click here
Click here
MSP430F478
Click here
Click here
Click here
Click here
Click here
MSP430F477
Click here
Click here
Click here
Click here
Click here
Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help —
straight from the experts. Search existing answers or ask your own question to get the quick design help
you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications
and do not necessarily reflect TI's views; see TI's Terms of Use.
7.5
Trademarks
MicroStar Junior, MSP430, Code Composer Studio, TI E2E are trademarks of Texas Instruments.
7.6
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
7.7
Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
authorization from U.S. Department of Commerce and other competent Government authorities to the
extent required by those laws.
7.8
Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
84
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8 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Mechanical, Packaging, and Orderable Information
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Aug-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
MSP430F477IPN
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F477
Samples
MSP430F477IPNR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F477
Samples
MSP430F477IZCA
ACTIVE
NFBGA
ZCA
113
260
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
F477
Samples
MSP430F477IZCAR
ACTIVE
NFBGA
ZCA
113
2500
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
F477
Samples
MSP430F477IZQW
OBSOLETE
BGA
MICROSTAR
JUNIOR
ZQW
113
TBD
Call TI
Call TI
M430F477
MSP430F477IZQWR
OBSOLETE
BGA
MICROSTAR
JUNIOR
ZQW
113
TBD
Call TI
Call TI
M430F477
MSP430F478IPN
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F478
Samples
MSP430F478IPNR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F478
Samples
MSP430F478IZCA
ACTIVE
NFBGA
ZCA
113
2500
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
F478
Samples
MSP430F478IZCAR
ACTIVE
NFBGA
ZCA
113
2500
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
F478
Samples
MSP430F479IPN
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F479
Samples
MSP430F479IPNR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F479
Samples
MSP430F479IZCAR
ACTIVE
NFBGA
ZCA
113
2500
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
F479
Samples
MSP430F479IZQWR
OBSOLETE
BGA
MICROSTAR
JUNIOR
ZQW
113
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
M430F479
PACKAGE OPTION ADDENDUM
www.ti.com
16-Aug-2023
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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