MSP430F5224IRGZT

Product Folder Order Now Technical Documents Tools & Software Support & Community Reference Design MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 MSP430F522x, MSP430F521x Mixed-Signal Microcontrollers 1 Device Overview 1.1 Features 1 • Dual-Supply Voltage Device – Primary Supply (AVCC, DVCC): – Powered From External Supply: 3.6 V Down to 1.8 V – Up to 22 General-Purpose I/Os With up to Four External Interrupts – Low-Voltage Interface Supply (DVIO): – Powered From Separate External Supply: 1.62 V to 1.98 V – Up to 31 General-Purpose I/Os With up to 12 External Interrupts – Serial Communications • Ultra-Low Power Consumption – Active Mode (AM): All System Clocks Active 290 µA/MHz at 8 MHz, 3.0 V, Flash Program Execution (Typical) 150 µA/MHz at 8 MHz, 3.0 V, RAM Program Execution (Typical) – Standby Mode (LPM3): Real-Time Clock (RTC) With Crystal, Watchdog, and Supply Supervisor Operational, Full RAM Retention, Fast Wakeup: 1.9 µA at 2.2 V, 2.1 µA at 3.0 V (Typical) Low-Power Oscillator (VLO), General-Purpose Counter, Watchdog, and Supply Supervisor Operational, Full RAM Retention, Fast Wakeup: 1.4 µA at 3.0 V (Typical) – Off Mode (LPM4): Full RAM Retention, Supply Supervisor Operational, Fast Wakeup: 1.1 µA at 3.0 V (Typical) – Shutdown Mode (LPM4.5): 0.18 µA at 3.0 V (Typical) • Wake up From Standby Mode in 3.5 µs (Typical) • 16-Bit RISC Architecture, Extended Memory, up to 25-MHz System Clock • Flexible Power-Management System – Fully Integrated LDO With Programmable Regulated Core Supply Voltage – Supply Voltage Supervision, Monitoring, and Brownout • Unified Clock System – FLL Control Loop for Frequency Stabilization – Low-Power Low-Frequency Internal Clock Source (VLO) – Low-Frequency Trimmed Internal Reference Source (REFO) – 32-kHz Watch Crystals (XT1) – High-Frequency Crystals up to 32 MHz (XT2) • 16-Bit Timer TA0, Timer_A With Five Capture/Compare Registers • 16-Bit Timer TA1, Timer_A With Three Capture/Compare Registers • 16-Bit Timer TA2, Timer_A With Three Capture/Compare Registers • 16-Bit Timer TB0, Timer_B With Seven Capture/Compare Shadow Registers • Two Universal Serial Communication Interfaces – USCI_A0 and USCI_A1 Each Support: – Enhanced UART With Automatic Baud Rate Detection – IrDA Encoder and Decoder – Synchronous SPI – USCI_B0 and USCI_B1 Each Support: – I2C – Synchronous SPI • 10-Bit Analog-to-Digital Converter (ADC) With Internal Reference, Sample-and-Hold • Comparator • Hardware Multiplier Supports 32-Bit Operations • Serial Onboard Programming, No External Programming Voltage Needed • Three-Channel Internal DMA • Basic Timer With RTC Feature • Device Comparison Summarizes Available Family Members 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 1.2 • • Applications Analog and Digital Sensor Systems Data Loggers 1.3 www.ti.com • General-Purpose Applications Description The TI MSP430™ family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with extensive low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from lowpower modes to active mode in 3.5 µs (typical). The MSP430F522x series are microcontrollers with four 16-bit timers, a high-performance 10-bit ADC, two universal serial communication interfaces (USCIs), a hardware multiplier, DMA, a comparator, and an RTC module with alarm capabilities. The MSP430F521x series include all of the peripherals of the MSP430F522x series with the exception of the ADC. All devices have a split I/O supply system that allows for a seamless interface to other devices that have a nominal 1.8-V I/O interface without the need for external level translation. For complete module descriptions, see the MSP430F5xx and MSP430F6xx Family User's Guide. For design guidelines, see Designing With MSP430F522x and MSP430F521x Devices. Device Information (1) PACKAGE BODY SIZE (2) MSP430F5229IRGC VQFN (64) 9 mm × 9 mm MSP430F5229IZQE BGA (80) 5 mm × 5 mm PART NUMBER MSP430F5224IRGZ VQFN (48) 7 mm × 7 mm MSP430F5219IYFF DSBGA (64) See Section 8 (1) (2) 2 For the most current part, package, and ordering information, see the Package Option Addendum in Section 8, or see the TI website at www.ti.com. The dimensions shown here are approximations. For the package dimensions with tolerances, see the Mechanical Data in Section 8. Device Overview Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com 1.4 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 Functional Block Diagrams Figure 1-1 shows the functional block diagram for the MSP430F5229 and MSP430F5227 devices in the RGC, ZQE, YFF packages. XIN XOUT XT2IN XT2OUT Unified Clock System RSTDVCC RST/NMI BSLEN ACLK 8KB Power Management Flash RAM LDO SVM/SVS Brownout PA DVIO VCORE P1.x P2.x SYS P1 P1 P2 1×4 I/Os 1×4 I/Os 1×8 I/Os Watchdog PA 1×16 I/Os Port Map Control (P4) I/O Ports Interrupt and Wakeup SMCLK MCLK CPUXV2 and Working Registers 128KB 64KB DVCC AVCC DVSS AVSS P3.x PB P4.x P5.x PC P6.x PJ PD P7.x PJ.x P3 P4 P5 P6 P7 1×5 I/Os 1×8 I/Os 1×6 I/Os 1×8 I/Os 1×6 I/Os PB 1×13 I/Os PC 1×14 I/Os USCI0,1 PD PJ 1×6 I/Os 1×4 I/Os I/O Ports USCI_Ax: UART, IrDA, SPI USCI_Bx: SPI, I2C MAB DMA MDB 3 Channel EEM (S: 3+1) ADC10_A JTAG, SBW Interface MPY32 TA0 TA1 TA2 TB0 Timer_A 5 CC Registers Timer_A 3 CC Registers Timer_A 3 CC Registers Timer_B 7 CC Registers I/O are supplied by DVIO RTC_A CRC16 10 Bit 200 KSPS COMP_B REF 12 Channels (10 ext,2 int) 8 Channels Copyright © 2016, Texas Instruments Incorporated Figure 1-1. Functional Block Diagram – F5229, F5227 – RGC, ZQE, YFF Packages Device Overview Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 3 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com Figure 1-2 shows the functional block diagram for the MSP430F5224 and MSP430F5222 devices in the RGZ package. XIN XOUT RSTDVCC RST/NMI BSLEN DVCC AVCC DVSS AVSS PA DVIO VCORE P1.x XT2IN XT2OUT Unified Clock System ACLK 8KB Power Management SYS P1 P1 P2 1×4 I/Os 1×4 I/Os 1×1 I/Os Watchdog PA 1×9 I/Os Port Map Control (P4) I/O Ports Interrupt and Wakeup SMCLK MCLK CPUXV2 and Working Registers 128KB 64KB Flash RAM LDO SVM,SVS Brownout P2.x P3.x PB P4.x P5.x PC P6.x PJ PJ.x P3 P4 P5 P6 1×5 I/Os 1×7 I/Os 1×6 I/Os 1×6 I/Os PB 1×12 I/Os PC 1×12 I/Os USCI0,1 PJ 1×4 I/Os USCI_Ax: UART, IrDA, SPI I/O Ports USCI_Bx: SPI, I2C MAB DMA MDB 3 Channel EEM (S: 3+1) ADC10_A JTAG, SBW Interface MPY32 TA0 TA1 TA2 TB0 Timer_A 5 CC Registers Timer_A 3 CC Registers Timer_A 3 CC Registers Timer_B 7 CC Registers RTC_A CRC16 10 Bit 200 KSPS COMP_B REF 6 Channels 10 Channels (8 ext, 2 int) I/O are supplied by DVIO Copyright © 2016, Texas Instruments Incorporated Figure 1-2. Functional Block Diagram – F5224, F5222 – RGZ Package Figure 1-3 shows the functional block diagram for the MSP430F5219 and MSP430F5217 devices in the RGC, ZQE, and YFF packages. XIN XOUT XT2IN XT2OUT Unified Clock System RSTDVCC RST/NMI BSLEN ACLK 8KB Power Management Flash RAM LDO SVM/SVS Brownout PA DVIO VCORE P1.x P2.x SYS P1 P1 P2 1×4 I/Os 1×4 I/Os 1×8 I/Os Watchdog PA 1×16 I/Os Port Map Control (P4) I/O Ports Interrupt and Wakeup SMCLK MCLK CPUXV2 and Working Registers 128KB 64KB DVCC AVCC DVSS AVSS P3.x PB P4.x P5.x PC P6.x PJ PD P7.x PJ.x P3 P4 P5 P6 P7 1×5 I/Os 1×8 I/Os 1×6 I/Os 1×8 I/Os 1×6 I/Os PB 1×13 I/Os PC 1×14 I/Os USCI0,1 PD PJ 1×6 I/Os 1×4 I/Os I/O Ports USCI_Ax: UART, IrDA, SPI USCI_Bx: SPI, I2C MAB DMA MDB 3 Channel EEM (S: 3+1) JTAG, SBW Interface MPY32 I/O are supplied by DVIO TA0 TA1 TA2 TB0 Timer_A 5 CC Registers Timer_A 3 CC Registers Timer_A 3 CC Registers Timer_B 7 CC Registers COMP_B RTC_A CRC16 REF 8 Channels Copyright © 2016, Texas Instruments Incorporated Figure 1-3. Functional Block Diagram – F5219, F5217 – RGC, ZQE, YFF Packages 4 Device Overview Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 Figure 1-4 shows the functional block diagram for the MSP430F5214 and MSP430F5212 devices in the RGZ package. XIN XOUT XT2IN XT2OUT Unified Clock System RSTDVCC RST/NMI BSLEN ACLK 8KB Power Management Flash RAM LDO SVM, SVS Brownout PA DVIO VCORE P1.x P2.x SYS P1 P1 P2 1×4 I/Os 1×4 I/Os 1×1 I/Os Watchdog PA 1×9 I/Os Port Map Control (P4) I/O Ports Interrupt and Wakeup SMCLK MCLK CPUXV2 and Working Registers 128KB 64KB DVCC AVCC DVSS AVSS P3.x PB P4.x P5.x PC P6.x PJ PJ.x P3 P4 P5 P6 1×5 I/Os 1×7 I/Os 1×6 I/Os 1×6 I/Os PB 1×12 I/Os PC 1×12 I/Os USCI0,1 PJ 1×4 I/Os USCI_Ax: UART, IrDA, SPI I/O Ports USCI_Bx: SPI, I2C MAB DMA MDB 3 Channel EEM (S: 3+1) JTAG, SBW Interface TA1 TA2 TB0 Timer_A 3 CC Registers Timer_A 3 CC Registers Timer_B 7 CC Registers TA0 MPY32 Timer_A 5 CC Registers I/O are supplied by DVIO COMP_B RTC_A CRC16 REF 6 Channels Copyright © 2016, Texas Instruments Incorporated Figure 1-4. Functional Block Diagram – F5214, F5212 – RGZ Package Device Overview Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 5 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com Table of Contents 1 2 3 Device Overview ......................................... 1 1.1 Features .............................................. 1 1.2 Applications ........................................... 2 1.3 Description ............................................ 2 1.4 Functional Block Diagrams ........................... 3 5 5.20 Related Products ..................................... 9 Terminal Configuration and Functions ............ 10 4.1 Pin Diagrams ........................................ 10 4.2 Signal Descriptions .................................. 16 Output Frequency – General-Purpose I/O DVIO Domain (P1.4 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5) .................................. 30 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0) ............................... 31 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1) ............................... 32 5.21 Crystal Oscillator, XT1, Low-Frequency Mode ...... 33 5.22 5.23 Crystal Oscillator, XT2 .............................. 34 Internal Very-Low-Power Low-Frequency Oscillator (VLO) ................................................ 35 Internal Reference, Low-Frequency Oscillator (REFO) .............................................. 35 5.24 Specifications ........................................... 21 5.1 Absolute Maximum Ratings ......................... 21 5.25 DCO Frequency ..................................... 36 5.2 ESD Ratings ........................................ Recommended Operating Conditions ............... 21 5.26 PMM, Brownout Reset (BOR)....................... 37 21 5.27 PMM, Core Voltage ................................. 37 Active Mode Supply Current Into VCC Excluding External Current ..................................... 24 Low-Power Mode Supply Currents (Into VCC) Excluding External Current.......................... 25 5.28 PMM, SVS High Side 5.29 PMM, SVM High Side ............................... 39 5.30 PMM, SVS Low Side ................................ 39 5.31 5.32 PMM, SVM Low Side ............................... 40 Wake-up Times From Low-Power Modes and Reset ................................................ 40 5.33 Timer_A 5.34 5.35 Timer_B ............................................. 41 USCI (UART Mode), Recommended Operating Conditions ........................................... 42 5.36 5.37 USCI (UART Mode) ................................. 42 USCI (SPI Master Mode), Recommended Operating Conditions ........................................... 42 5.38 USCI (SPI Master Mode)............................ 42 5.39 USCI (SPI Slave Mode) ............................. 44 5.40 5.41 USCI (I2C Mode) .................................... 46 10-Bit ADC, Power Supply and Input Range Conditions ........................................... 47 5.42 10-Bit ADC, Timing Parameters 5.43 10-Bit ADC, Linearity Parameters................... 48 5.44 REF, External Reference 5.45 REF, Built-In Reference ............................. 49 5.46 Comparator_B ....................................... 50 5.47 Flash Memory ....................................... 51 5.48 JTAG and Spy-Bi-Wire Interface .................... 51 5.49 DVIO BSL Entry ..................................... 52 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 6 5.19 Revision History ......................................... 8 Device Comparison ..................................... 9 3.1 4 5.18 Thermal Resistance Characteristics ................ 26 Schmitt-Trigger Inputs – General-Purpose I/O DVCC Domain (P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RSTDVCC) ................................... 27 Schmitt-Trigger Inputs – General-Purpose I/O DVIO Domain (P1.4 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5, RST/NMI, BSLEN) ............. 27 Inputs – Interrupts DVCC Domain Port P1 (P1.0 to P1.3) ....................................... 27 Inputs – Interrupts DVIO Domain Ports P1 and P2 (P1.4 to P1.7, P2.0 to P2.7)......................... 27 Leakage Current – General-Purpose I/O DVCC Domain (P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3) ................................................. 28 Leakage Current – General-Purpose I/O DVIO Domain (P1.4 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5) .................................. 28 Outputs – General-Purpose I/O DVCC Domain (Full Drive Strength) (P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3) ................................................. 28 Outputs – General-Purpose I/O DVCC Domain (Reduced Drive Strength) (P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3) ................................................. 28 Outputs – General-Purpose I/O DVIO Domain (Full Drive Strength) (P1.4 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5) .................................. 29 Outputs – General-Purpose I/O DVIO Domain (Reduced Drive Strength) (P1.4 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5) .................................. 29 Output Frequency – General-Purpose I/O DVCC Domain (P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3) ................................................. 30 Table of Contents 6 ............................... ............................................. .................... ........................... 38 41 47 48 Detailed Description ................................... 53 6.1 CPU (Link to user's guide) .......................... 53 6.2 Operating Modes .................................... 54 6.3 Interrupt Vector Addresses.......................... 55 6.4 Memory Organization ............................... 56 6.5 Bootloader (BSL) .................................... 58 6.6 JTAG Operation ..................................... 59 6.7 Flash Memory (Link to user's guide) ................ 60 6.8 RAM (Link to user's guide) .......................... 60 .......................................... 6.9 Peripherals 6.10 Input/Output Diagrams .............................. 82 61 Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com Device Descriptors .................................. 99 7.5 Related Links Device and Documentation Support .............. 105 7.6 Community Resources............................. 110 7.1 Getting Started ..................................... 105 7.7 Trademarks ........................................ 110 7.2 Device Nomenclature .............................. 105 7.8 Electrostatic Discharge Caution 7.3 Tools and Software ................................ 107 7.9 Glossary............................................ 110 7.4 Documentation Support ............................ 108 6.11 7 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 8 ...................................... ................... 110 Mechanical, Packaging, and Orderable Information ............................................. 110 Table of Contents Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 110 7 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 2 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from June 29, 2016 to September 26, 2018 • • • • • • • • • • • 8 Page Added Section 3.1, Related Products ............................................................................................. 9 Removed D and E dimension lines on the YFF pinout (for the package dimesions with tolerances, see the Mechanical Data in Section 8) ..................................................................................................... 15 Added typical conditions statements at the beginning of Section 5, Specifications ........................................ 21 Changed the MIN value of the V(DVCC_BOR_hys) parameter from 60 mV to 50 mV in Section 5.26, PMM, Brownout Reset (BOR) ............................................................................................................. 37 Updated notes (1) and (2) and added note (3) in Section 5.32, Wake-up Times From Low-Power Modes and Reset .................................................................................................................................. 40 Removed ADC10DIV from the formula for the TYP value in the second row of the tCONVERT parameter in Section 5.42, 10-Bit ADC, Timing Parameters (removed because ADC10CLK is after division)......................... 47 Added second row for tEN_CMP with Test Conditions of "CBPWRMD = 10" and MAX value of 100 μs in Section 5.46, Comparator_B ....................................................................................................... 50 Renamed FCTL4.MGR0 and MGR1 in Section 5.47, Flash Memory, to be consistent with header files ............... 51 Throughout document, changed all instances of "bootstrap loader" to "bootloader" ....................................... 58 Replaced former section Development Tools Support with Section 7.3, Tools and Software ........................... 107 Added content to Section 7.4, Documentation Support ...................................................................... 108 Revision History Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 3 Device Comparison Table 3-1 summarizes the available family members. Table 3-1. Family Members (1) (2) USCI DEVICE FLASH (KB) SRAM (KB) Timer_A (3) Timer_B (4) ADC10_A (Ch) Comp_B (Ch) I/O DVCC (5) I/O DVIO (6) PACKAGE MSP430F5229 128 8 5, 3, 3 7 2 2 10 ext, 2 int 8 22 31 64 RGC 64 YFF 80 ZQE MSP430F5227 64 8 5, 3, 3 7 2 2 10 ext, 2 int 8 22 31 64 RGC 64 YFF 80 ZQE MSP430F5224 128 8 5, 3, 3 MSP430F5222 64 8 5, 3, 3 7 2 2 8 ext, 2 int 6 20 17 48 RGZ 7 2 2 8 ext, 2 int 6 20 17 48 RGZ CHANNEL A: CHANNEL B: UART, IrDA, SPI, I2C SPI MSP430F5219 128 8 5, 3, 3 7 2 2 - 8 22 31 64 RGC 64 YFF 80 ZQE MSP430F5217 64 8 5, 3, 3 7 2 2 - 8 22 31 64 RGC 64 YFF 80 ZQE MSP430F5214 128 8 5, 3, 3 7 2 2 - 6 20 17 48 RGZ MSP430F5212 64 8 5, 3, 3 7 2 2 - 6 20 17 48 RGZ (1) (2) (3) (4) (5) (6) 3.1 For the most current device, package, and ordering information, see the Package Option Addendum in Section 8, or see the TI website at www.ti.com. Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging. Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively. Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively. All of these I/Os reside on a single voltage rail supplied by DVCC. All of these I/Os reside on a single voltage rail supplied by DVIO. Related Products For information about other devices in this family of products or related products, see the following links. Products for TI Microcontrollers TI's low-power and high-performance MCUs, with wired and wireless connectivity options, are optimized for a broad range of applications. Products for MSP430 Ultra-Low-Power Microcontrollers One platform. One ecosystem. Endless possibilities. Enabling the connected world with innovations in ultra-low-power microcontrollers with advanced peripherals for precise sensing and measurement. Companion Products for MSP430F5229 Review products that are frequently purchased or used with this product. Reference Designs for MSP430F5229 Find reference designs that leverage the best in TI technology to solve your system-level challenges. Device Comparison Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 9 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 4 Terminal Configuration and Functions 4.1 Pin Diagrams P7.0/TB0.0 P7.1/TB0.1 P7.2/TB0.2 P7.3/TB0.3 P7.4/TB0.4 P7.5/TB0.5 BSLEN RST/NMI P5.2/XT2IN P5.3/XT2OUT TEST/SBWTCK PJ.0/TDO PJ.1/TDI/TCLK PJ.2/TMS RSTDVCC/SBWTDIO PJ.3/TCK Figure 4-1 shows the pinout for the MSP430F5229 and MSP430F5227 devices in the 64-pin RGC package. 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P6.0/A0/CB0 1 48 P4.7/PM_NONE P6.1/A1/CB1 2 47 P4.6/PM_NONE P6.2/A2/CB2 3 46 P4.5/PM_UCA1RXD/PM_UCA1SOMI P6.3/A3/CB3 4 45 P4.4/PM_UCA1TXD/PM_UCA1SIMO P6.4/A4/CB4 5 44 P4.3/PM_UCB1CLK/PM_UCA1STE P6.5/A5/CB5 6 43 P4.2/PM_UCB1SOMI/PM_UCB1SCL P6.6/A6/CB6 7 42 P4.1/PM_UCB1SIMO/PM_UCB1SDA P6.7/A7/CB7 8 41 P4.0/PM_UCB1STE/PM_UCA1CLK MSP430F5229IRGC MSP430F5227IRGC P5.0/A8/VeREF+ 9 40 DVIO P5.1/A9/VeREF- 10 39 DVSS AVCC 11 38 P3.4/UCA0RXD/UCA0SOMI P5.4/XIN 12 37 P3.3/UCA0TXD/UCA0SIMO P5.5/XOUT 13 36 P3.2/UCB0CLK/UCA0STE P2.7/UCB0STE/UCA0CLK P2.6/RTCCLK/DMAE0 P2.5/TA2.2 P2.4/TA2.1 P2.3/TA2.0 P2.1/TA1.2 P2.2/TA2CLK/SMCLK P2.0/TA1.1 P1.7/TA1.0 P1.6/TA1CLK/CBOUT P1.5/TA0.4 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P1.4/TA0.3 DVSS P1.3/TA0.2 P3.0/UCB0SIMO/UCB0SDA P1.2/TA0.1 P3.1/UCB0SOMI/UCB0SCL 34 P1.1/TA0.0 35 15 VCORE 14 P1.0/TA0CLK/ACLK AVSS DVCC Supplied by DVIO NOTE: TI recommends connection of exposed thermal pad to VSS. Figure 4-1. 64-Pin RGC Package – F5229, F5227 10 Terminal Configuration and Functions Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 RST/NMI P5.2/XT2IN P5.3/XT2OUT TEST/SBWTCK PJ.0/TDO PJ.1/TDI/TCLK PJ.2/TMS PJ.3/TCK RSTDVCC/SBWTDIO P6.0/A0/CB0 P6.1/A1/CB1 P6.2/A2/CB2 Figure 4-2 shows the pinout for the MSP430F5224 and MSP430F5222 devices in the 48-pin RGZ package. 48 47 46 45 44 43 42 41 40 39 38 37 P6.3/A3/CB3 1 36 BSLEN P6.4/A4/CB4 2 35 P4.6/PM_NONE P6.5/A5/CB5 3 34 P4.5/PM_UCA1RXD/PM_UCA1SOMI P5.0/A8/VeREF+ 4 33 P4.4/PM_UCA1TXD/PM_UCA1SIMO P5.1/A9/VeREF- 5 32 P4.3/PM_UCB1CLK/PM_UCA1STE AVCC 6 31 P4.2/PM_UCB1SOMI/PM_UCB1SCL P5.4/XIN 7 30 P4.1/PM_UCB1SIMO/PM_UCB1SDA P5.5/XOUT 8 29 P4.0/PM_UCB1STE/PM_UCA1CLK MSP430F5224IRGZ MSP430F5222IRGZ P1.0/TA0CLK/ACLK P3.2/UCB0CLK/UCA0STE P3.3/UCA0TXD/UCA0SIMO P3.1/UCB0SOMI/UCB0SCL 25 12 13 14 15 16 17 18 19 20 21 22 23 24 VCORE P2.7/UCB0STE/UCA0CLK P3.4/UCA0RXD/UCA0SOMI P3.0/UCB0SIMO/UCB0SDA 26 P1.7/TA1.0 11 P1.6/TA1CLK/CBOUT DVSS P1.5/TA0.4 DVSS P1.4/TA0.3 DVIO 27 P1.3/TA0.2 28 P1.2/TA0.1 9 10 P1.1/TA0.0 AVSS DVCC Supplied by DVIO NOTE: TI recommends connection of exposed thermal pad to VSS. Figure 4-2. 48-Pin RGZ Package – F5224, F5222 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 11 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com P7.0/TB0.0 P7.1/TB0.1 P7.2/TB0.2 P7.3/TB0.3 P7.4/TB0.4 P7.5/TB0.5 RST/NMI BSLEN P5.2/XT2IN P5.3/XT2OUT TEST/SBWTCK PJ.0/TDO PJ.1/TDI/TCLK PJ.2/TMS PJ.3/TCK RSTDVCC/SBWTDIO Figure 4-3 shows the pinout for the MSP430F5219 and MSP430F5217 devices in the 64-pin RGC package. 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P6.0/CB0 1 48 P4.7/PM_NONE P6.1/CB1 2 47 P4.6/PM_NONE P6.2/CB2 3 46 P4.5/PM_UCA1RXD/PM_UCA1SOMI P6.3/CB3 4 45 P4.4/PM_UCA1TXD/PM_UCA1SIMO P6.4/CB4 5 44 P4.3/PM_UCB1CLK/PM_UCA1STE P6.5/CB5 6 43 P4.2/PM_UCB1SOMI/PM_UCB1SCL P6.6/CB6 7 42 P4.1/PM_UCB1SIMO/PM_UCB1SDA P6.7/CB7 8 41 P4.0/PM_UCB1STE/PM_UCA1CLK MSP430F5219IRGC MSP430F5217IRGC P5.0 9 40 DVIO P5.1 10 39 DVSS AVCC 11 38 P3.4/UCA0RXD/UCA0SOMI P5.4/XIN 12 37 P3.3/UCA0TXD/UCA0SIMO P5.5/XOUT 13 36 P3.2/UCB0CLK/UCA0STE P2.7/UCB0STE/UCA0CLK P2.6/RTCCLK/DMAE0 P2.5/TA2.2 P2.4/TA2.1 P2.3/TA2.0 P2.1/TA1.2 P2.2/TA2CLK/SMCLK P2.0/TA1.1 P1.7/TA1.0 P1.6/TA1CLK/CBOUT P1.5/TA0.4 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P1.4/TA0.3 DVSS P1.3/TA0.2 P3.0/UCB0SIMO/UCB0SDA P1.2/TA0.1 P3.1/UCB0SOMI/UCB0SCL 34 P1.1/TA0.0 35 15 VCORE 14 P1.0/TA0CLK/ACLK AVSS DVCC Supplied by DVIO NOTE: TI recommends connection of exposed thermal pad to VSS. Figure 4-3. 64-Pin RGC Package – F5219, F5217 12 Terminal Configuration and Functions Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 RST/NMI P5.2/XT2IN P5.3/XT2OUT TEST/SBWTCK PJ.0/TDO PJ.1/TDI/TCLK PJ.2/TMS PJ.3/TCK RSTDVCC/SBWTDIO P6.0/CB0 P6.1/CB1 P6.2/CB2 Figure 4-4 shows the pinout for the MSP430F5214 and MSP430F5212 devices in the 48-pin RGZ package. 48 47 46 45 44 43 42 41 40 39 38 37 P6.3/CB3 1 36 BSLEN P6.4/CB4 2 35 P4.6/PM_NONE P6.5/CB5 3 34 P4.5/PM_UCA1RXD/PM_UCA1SOMI P5.0 4 33 P4.4/PM_UCA1TXD/PM_UCA1SIMO P5.1 5 32 P4.3/PM_UCB1CLK/PM_UCA1STE 31 P4.2/PM_UCB1SOMI/PM_UCB1SCL 30 P4.1/PM_UCB1SIMO/PM_UCB1SDA AVCC 6 P5.4/XIN 7 P5.5/XOUT 8 29 P4.0/PM_UCB1STE/PM_UCA1CLK AVSS 9 28 DVIO DVCC 10 27 DVSS 11 26 P3.4/UCA0RXD/UCA0SOMI 12 25 13 14 15 16 17 18 19 20 21 22 23 24 P3.3/UCA0TXD/UCA0SIMO P3.2/UCB0CLK/UCA0STE P3.1/UCB0SOMI/UCB0SCL P2.7/UCB0STE/UCA0CLK P3.0/UCB0SIMO/UCB0SDA P1.7/TA1.0 P1.6/TA1CLK/CBOUT P1.5/TA0.4 P1.4/TA0.3 P1.3/TA0.2 P1.2/TA0.1 P1.0/TA0CLK/ACLK P1.1/TA0.0 DVSS VCORE MSP430F5214IRGZ MSP430F5212IRGZ Supplied by DVIO NOTE: TI recommends connection of exposed thermal pad to VSS. Figure 4-4. 48-Pin RGZ Package – F5214, F5212 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 13 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com Figure 4-5 shows the pinout for the MSP430F5229, MSP430F5227, MSP430F5219, and MSP430F5217 devices in the 80-pin ZQE package. TEST RST/NMI P7.5 P7.4 P7.3 P7.1 A4 A5 A7 A8 A9 PJ.3 P5.3 P5.2 B3 B4 B5 P6.3 PJ.1 PJ.0 C2 C4 C5 C6 D4 D5 D6 P6.0 RSTDVCC PJ.2 A1 A2 A3 P6.2 P6.1 B1 B2 P6.4 C1 P6.6 P6.5 P6.7 D1 D2 D3 P5.0 P5.1 E1 E2 P5.4 AVCC F1 F2 P5.5 AVSS G1 G2 G3 DVCC P1.0 H1 H2 J2 BSLEN P7.2 B6 P7.0 B7 B8 B9 P4.7 P4.6 P4.5 C7 C8 C9 P4.4 P4.3 P4.2 D7 D8 D9 P4.1 P4.0 DVIO E3 E4 E5 E6 E7 E8 F3 F4 F5 F6 F7 F8 E9 F9 P1.3 P1.6 P2.1 P3.4 P3.2 P3.3 G4 G5 G6 G7 G8 G9 P1.1 P1.4 P1.7 P2.3 P2.7 P3.0 P3.1 H3 H4 H5 H6 H7 H8 H9 P1.5 P2.0 P2.2 P2.4 P2.5 P2.6 J4 J5 J6 J7 J8 J9 DVSS DVSS VCORE P1.2 J1 A6 J3 Supplied by DVIO Figure 4-5. 80-Pin ZQE Package – F5229, F5227, F5219, F5217 14 Terminal Configuration and Functions Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 Figure 4-6 shows the pinout for the MSP430F5229, MSP430F5227, MSP430F5219, and MSP430F5217 devices in the 64-pin YFF package. Top View Ball-Side View H8 P3.0 H7 P3.3 H6 DVSS H5 DVIO H4 P4.1 H3 P4.4 H2 P4.6 H1 P7.0 H1 P7.0 H2 P4.6 H3 P4.4 H4 P4.1 H5 DVIO H6 DVSS H7 P3.3 H8 P3.0 G8 P2.6 G7 P3.1 G6 P3.2 G5 P3.4 G4 P4.3 G3 P4.7 G2 P7.1 G1 P7.3 G1 P7.3 G2 P7.1 G3 P4.7 G4 P4.3 G5 P3.4 G6 P3.2 G7 P3.1 G8 P2.6 F8 P2.3 F7 P2.5 F6 P2.7 F5 P4.0 F4 P4.5 F3 P7.2 F2 P7.4 F1 P7.5 F1 P7.5 F2 P7.4 F3 P7.2 F4 P4.5 F5 P4.0 F6 P2.7 F7 P2.5 F8 P2.3 E4 E3 E2 E1 E1 E2 E3 E4 E8 E7 E6 E5 P2.0 P2.2 P2.4 P4.2 D8 P1.5 D7 P1.6 P1.7 D5 D3 D4 P2.1 RSTDVCC PJ.2 D2 PJ.0 D1 P5.3 D1 P5.3 D2 PJ.0 D5 D3 D4 PJ.2 RSTDVCC P2.1 C8 P1.2 C7 P1.1 C6 P1.3 C5 P1.4 C4 P6.6 C3 P6.3 C2 P6.0 C1 PJ.1 C1 PJ.1 C2 P6.0 C3 P6.3 C4 P6.6 B8 B7 VCORE P1.0 B6 AVSS B5 AVCC B4 P5.0 B3 P6.5 B2 P6.2 B1 PJ.3 B1 PJ.3 B2 P6.2 B3 P6.5 A6 P5.5 A5 P5.4 A4 P5.1 A3 P6.7 A2 P6.4 A1 P6.1 A1 P6.1 A2 P6.4 A3 P6.7 A8 A7 DVSS DVCC D6 TEST RST/NMI BSLEN P5.2 E5 E6 E7 E8 P4.2 P2.4 P2.2 P2.0 D6 P1.7 D7 P1.6 D8 P1.5 C5 P1.4 C6 P1.3 C7 P1.1 C8 P1.2 B4 P5.0 B5 AVCC B6 AVSS B8 B7 P1.0 VCORE A4 P5.1 A5 P5.4 A6 P5.5 P5.2 BSLEN RST/NMI TEST A8 A7 DVCC DVSS Supplied by DVIO Figure 4-6. 64-Pin YFF Package – F5229, F5227, F5219, F5217 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 15 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 4.2 www.ti.com Signal Descriptions Table 4-1 describes the signals for all device variants and package options. Table 4-1. Terminal Functions TERMINAL NAME I/O (1) NO. RGC ZQE YFF SUPPLY DESCRIPTION RGZ General-purpose digital I/O P6.0/CB0/A0 1 A1 C2 46 I/O DVCC Comparator_B input CB0 Analog input A0 for ADC (not available on all device types) General-purpose digital I/O P6.1/CB1/A1 2 B2 A1 47 I/O DVCC Comparator_B input CB1 Analog input A1 for ADC (not available on all device types) General-purpose digital I/O P6.2/CB2/A2 3 B1 B2 48 I/O DVCC Comparator_B input CB2 Analog input A2 for ADC (not available on all device types) General-purpose digital I/O P6.3/CB3/A3 4 C2 C3 1 I/O DVCC Comparator_B input CB3 Analog input A3 for ADC (not available on all device types) General-purpose digital I/O P6.4/CB4/A4 5 C1 A2 2 I/O DVCC Comparator_B input CB4 Analog input A4 for ADC (not available on all device types) General-purpose digital I/O P6.5/CB5/A5 6 D2 B3 3 I/O DVCC Comparator_B input CB5 Analog input A5 for ADC (not available on all device types) General-purpose digital I/O (not available on all device types) P6.6/CB6/A6 7 D1 C4 N/A I/O DVCC Comparator_B input CB6 (not available on all device types) Analog input A6 for ADC (not available on all device types) General-purpose digital I/O (not available on all device types) P6.7/CB7/A7 8 D3 A3 N/A I/O DVCC Comparator_B input CB7 (not available on all device types) Analog input A7 for ADC (not available on all device types) General-purpose digital I/O P5.0/A8/VeREF+ 9 E1 B4 4 I/O DVCC Analog input A8 for ADC (not available on all device types) Input for an external reference voltage to the ADC (not available on all device types) General-purpose digital I/O P5.1/A9/VeREF- 10 E2 A4 5 I/O DVCC Analog input A9 for ADC (not available on all device types) Negative terminal for the ADC reference voltage for an external applied reference voltage (not available on all device types) AVCC 11 F2 B5 6 Analog power supply P5.4/XIN 12 F1 A5 7 I/O DVCC P5.5/XOUT 13 G1 A6 8 I/O DVCC AVSS 14 G2 B6 9 General-purpose digital I/O Input terminal for crystal oscillator XT1 (2) General-purpose digital I/O Output terminal of crystal oscillator XT1 (1) (2) 16 Analog ground supply I = input, O = output, N/A = not available When in crystal bypass mode, XIN can be configured so that it can support an input digital waveform with swing levels from DVSS to DVCC or DVSS to DVIO. In this case, it is required that the pin be configured properly for the intended input swing. Terminal Configuration and Functions Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 Table 4-1. Terminal Functions (continued) TERMINAL NAME I/O (1) NO. SUPPLY DESCRIPTION RGC ZQE YFF RGZ DVCC 15 H1 A7 10 Digital power supply DVSS 16 J1 A8 11 Digital ground supply VCORE (3) 17 J2 B8 12 DVCC Regulated core power supply output (internal use only, no external current loading) General-purpose digital I/O with port interrupt P1.0/TA0CLK/ACLK 18 H2 B7 13 I/O DVCC TA0 clock signal TA0CLK input ACLK output (divided by 1, 2, 4, 8, 16, or 32) General-purpose digital I/O with port interrupt P1.1/TA0.0 19 H3 C7 14 I/O DVCC TA0 CCR0 capture: CCI0A input, compare: Out0 output BSL transmit output General-purpose digital I/O with port interrupt P1.2/TA0.1 20 J3 C8 15 I/O DVCC TA0 CCR1 capture: CCI1A input, compare: Out1 output BSL receive input General-purpose digital I/O with port interrupt P1.3/TA0.2 21 G4 C6 16 I/O DVCC TA0 CCR2 capture: CCI2A input, compare: Out2 output P1.4/TA0.3 22 H4 C5 17 I/O DVIO (4) General-purpose digital I/O with port interrupt TA0 CCR3 capture: CCI3A input compare: Out3 output P1.5/TA0.4 23 J4 D8 18 I/O DVIO (4) General-purpose digital I/O with port interrupt TA0 CCR4 capture: CCI4A input, compare: Out4 output General-purpose digital I/O with port interrupt P1.6/TA1CLK/CBOUT 24 G5 D7 19 I/O DVIO (4) TA1 clock signal TA1CLK input Comparator_B output P1.7/TA1.0 25 H5 D6 20 I/O DVIO (4) General-purpose digital I/O with port interrupt TA1 CCR0 capture: CCI0A input, compare: Out0 output P2.0/TA1.1 26 J5 E8 N/A I/O DVIO (4) General-purpose digital I/O with port interrupt (not available on all device types) TA1 CCR1 capture: CCI1A input, compare: Out1 output (not available on all device types) P2.1/TA1.2 27 G6 D5 N/A I/O DVIO (4) General-purpose digital I/O with port interrupt (not available on all device types) TA1 CCR2 capture: CCI2A input, compare: Out2 output (not available on all device types) General-purpose digital I/O with port interrupt (not available on all device types) P2.2/TA2CLK/SMCLK 28 J6 E7 N/A I/O DVIO (4) TA2 clock signal TA2CLK input SMCLK output (not available on all device types) P2.3/TA2.0 29 H6 F8 N/A I/O DVIO (4) General-purpose digital I/O with port interrupt (not available on all device types) TA2 CCR0 capture: CCI0A input, compare: Out0 output (not available on all device types) P2.4/TA2.1 30 J7 E6 N/A I/O DVIO (4) General-purpose digital I/O with port interrupt (not available on all device types) TA2 CCR1 capture: CCI1A input, compare: Out1 output (not available on all device types) (3) (4) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended capacitor value, CVCORE. This pin function is supplied by DVIO. See Section 5.8 for input and output requirements. Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 17 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com Table 4-1. Terminal Functions (continued) TERMINAL NAME P2.5/TA2.2 I/O (1) NO. RGC 31 ZQE J8 YFF F7 SUPPLY DESCRIPTION RGZ N/A I/O DVIO (4) General-purpose digital I/O with port interrupt (not available on all device types) TA2 CCR2 capture: CCI2A input, compare: Out2 output (not available on all device types) General-purpose digital I/O with port interrupt (not available on all device types) P2.6/RTCCLK/DMAE0 32 J9 G8 N/A I/O DVIO (4) RTC clock output for calibration (not available on all device types) DMA external trigger input (not available on all device types) General-purpose digital I/O P2.7/UCB0STE/ UCA0CLK 33 H7 F6 21 I/O DVIO (4) Slave transmit enable – USCI_B0 SPI mode Clock signal input – USCI_A0 SPI slave Clock signal output – USCI_A0 SPI master mode mode General-purpose digital I/O P3.0/UCB0SIMO/ UCB0SDA 34 H8 H8 22 I/O DVIO (4) Slave in, master out – USCI_B0 SPI mode I2C data – USCI_B0 I2C mode General-purpose digital I/O P3.1/UCB0SOMI/ UCB0SCL 35 H9 G7 23 I/O DVIO (4) Slave out, master in – USCI_B0 SPI mode I2C clock – USCI_B0 I2C mode General-purpose digital I/O P3.2/UCB0CLK/ UCA0STE 36 G8 G6 24 I/O DVIO (4) Clock signal input – USCI_B0 SPI slave Clock signal output – USCI_B0 SPI master mode mode Slave transmit enable – USCI_A0 SPI mode General-purpose digital I/O P3.3/UCA0TXD/ UCA0SIMO 37 G9 H7 25 I/O DVIO (4) Transmit data – USCI_A0 UART mode Slave in, master out – USCI_A0 SPI mode General-purpose digital I/O P3.4/UCA0RXD/ UCA0SOMI 38 G7 G5 26 DVSS 39 F9 H6 27 Digital ground supply DVIO (5) 40 E9 H5 28 Digital I/O power supply I/O DVIO (4) Receive data – USCI_A0 UART mode Slave out, master in – USCI_A0 SPI mode P4.0/PM_UCB1STE/ PM_UCA1CLK P4.1/PM_UCB1SIMO/ PM_UCB1SDA 41 E8 F5 29 I/O DVIO (4) General-purpose digital I/O with reconfigurable port mapping secondary function Default mapping: Slave transmit enable – USCI_B1 SPI mode Default mapping: Clock signal input – USCI_A1 SPI slave mode Default mapping: Clock signal output – USCI_A1 SPI master mode General-purpose digital I/O with reconfigurable port mapping secondary function 42 E7 H4 30 I/O DVIO (4) Default mapping: Slave in, master out – USCI_B1 SPI mode Default mapping: I2C data – USCI_B1 I2C mode P4.2/PM_UCB1SOMI/ PM_UCB1SCL General-purpose digital I/O with reconfigurable port mapping secondary function 43 D9 E5 31 I/O DVIO (4) Default mapping: Slave out, master in – USCI_B1 SPI mode Default mapping: I2C clock – USCI_B1 I2C mode (5) 18 The voltage on DVIO is not supervised or monitored. Terminal Configuration and Functions Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 Table 4-1. Terminal Functions (continued) TERMINAL NAME I/O (1) NO. RGC ZQE YFF SUPPLY DESCRIPTION RGZ General-purpose digital I/O with reconfigurable port mapping secondary function P4.3/PM_UCB1CLK/ PM_UCA1STE 44 D8 G4 32 I/O DVIO (4) Default mapping: Clock signal input – USCI_B1 SPI slave mode Default mapping: Clock signal output – USCI_B1 SPI master mode Default mapping: Slave transmit enable – USCI_A1 SPI mode P4.4/PM_UCA1TXD/ PM_UCA1SIMO General-purpose digital I/O with reconfigurable port mapping secondary function 45 D7 H3 33 I/O DVIO (4) Default mapping: Transmit data – USCI_A1 UART mode Default mapping: Slave in, master out – USCI_A1 SPI mode P4.5/PM_UCA1RXD/ PM_UCA1SOMI General-purpose digital I/O with reconfigurable port mapping secondary function 46 C9 F4 34 I/O DVIO (4) Default mapping: Receive data – USCI_A1 UART mode Default mapping: Slave out, master in – USCI_A1 SPI mode P4.6/PM_NONE 47 C8 H2 35 I/O DVIO (4) General-purpose digital I/O with reconfigurable port mapping secondary function Default mapping: no secondary function P4.7/PM_NONE 48 C7 G3 N/A I/O DVIO (4) General-purpose digital I/O with reconfigurable port mapping secondary function (not available on all device types) Default mapping: no secondary function (not available on all device types) General-purpose digital I/O (not available on all device types) P7.0/TB0.0 49 B8, B9 H1 N/A I/O DVIO (4) P7.1/TB0.1 50 A9 G2 N/A I/O DVIO (4) P7.2/TB0.2 51 B7 F3 N/A I/O DVIO (4) P7.3/TB0.3 52 A8 G1 N/A I/O DVIO (4) P7.4/TB0.4 53 A7 F2 N/A I/O DVIO (4) P7.5/TB0.5 54 A6 F1 N/A I/O DVIO (4) BSLEN 55 B6 E2 36 I DVIO (4) RST/NMI 56 A5 E3 37 I DVIO (4) P5.2/XT2IN 57 B5 E1 38 I/O DVCC TB0 CCR0 capture: CCI0A input, compare: Out0 output (not available on all device types) General-purpose digital I/O (not available on all device types) TB0 CCR1 capture: CCI1A input, compare: Out1 output (not available on all device types) General-purpose digital I/O (not available on all device types) TB0 CCR2 capture: CCI2A input, compare: Out2 output (not available on all device types) General-purpose digital I/O (not available on all device types) TB0 CCR3 capture: CCI3A input, compare: Out3 output (not available on all device types) General-purpose digital I/O (not available on all device types) TB0 CCR4 capture: CCI4A input, compare: Out4 output (not available on all device types) General-purpose digital I/O (not available on all device types) TB0 CCR5 capture: CCI5A input, compare: Out5 output (not available on all device types) BSL enable with internal pulldown Reset input active low (6) (7) Nonmaskable interrupt input (6) General-purpose digital I/O (6) (7) (8) Input terminal for crystal oscillator XT2 (8) This pin is configurable as reset or NMI and resides on the DVIO supply domain. When driven from external, input swing levels from DVSS to DVIO are required. When this pin is configured as reset, the internal pullup resistor is enabled by default. When in crystal bypass mode, XT2IN can be configured so that it can support an input digital waveform with swing levels from DVSS to DVCC or DVSS to DVIO. In this case, it is required that the pin be configured properly for the intended input swing. Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 19 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com Table 4-1. Terminal Functions (continued) TERMINAL NAME NO. RGC ZQE YFF RGZ 58 B4 D1 39 I/O (1) SUPPLY I/O DVCC DESCRIPTION General-purpose digital I/O P5.3/XT2OUT Output terminal of crystal oscillator XT2 TEST/SBWTCK (9) Test mode pin – Selects four wire JTAG operation 59 A4 E4 40 I DVCC Spy-Bi-Wire input clock when Spy-Bi-Wire operation activated PJ.0/TDO (10) General-purpose digital I/O 60 C5 D2 41 I/O DVCC JTAG test data output port PJ.1/TDI/TCLK (10) General-purpose digital I/O 61 C4 C1 42 I/O DVCC JTAG test data input or test clock input PJ.2/TMS (10) General-purpose digital I/O 62 A3 D3 43 I/O DVCC JTAG test mode select PJ.3/TCK (10) General-purpose digital I/O 63 B3 B1 44 I/O DVCC JTAG test clock Reset input, active-low (11) RSTDVCC/ SBWTDIO (10) 64 Reserved N/A (12) N/A N/A Reserved QFN Pad Pad N/A N/A Pad QFN thermal pad. TI recommends connecting to VSS. A2 D4 45 I/O DVCC Spy-Bi-Wire data input/output when Spy-Bi-Wire operation activated (9) See Section 6.5 and Section 6.6 for use with BSL and JTAG functions. (10) See Section 6.6 for use with JTAG function. (11) This nonconfigurable reset resides on the DVCC supply domain and has an internal pullup to DVCC. When driven from external, input swing levels from DVSS to DVCC are required. This reset must be used for Spy-Bi-Wire communication and is not the same RST/NMI reset as found on other devices in the MSP430 family. See Section 6.5 and Section 6.6 for details regarding the use of this pin. (12) C6, D4, D5, D6, E3, E4, E5, E6, F3, F4, F5, F6, F7, F8, G3 are reserved and should be connected to ground. 20 Terminal Configuration and Functions Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 5 Specifications All graphs in this section are for typical conditions, unless otherwise noted. Typical (TYP) values are specified at VCC = 3.3 V and TA = 25°C, unless otherwise noted. 5.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX Voltage applied at VCC to VSS –0.3 4.1 V Voltage applied at VIO to VSS –0.3 2.2 V Voltage applied to any pin (excluding VCORE and VIO pins) (2) –0.3 VCC + 0.3 V Voltage applied to VIO pins –0.3 VIO + 0.2 Diode current at any device pin Storage temperature, Tstg (3) (1) (2) (3) –55 UNIT V ±2 mA 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied. Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. 5.2 ESD Ratings VALUE V(ESD) (1) (2) 5.3 Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±1000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) Recommended Operating Conditions VCC Supply voltage during program execution and flash programming (AVCC = DVCC) (1) (2) (3) VIO Supply voltage applied to DVIO referenced to VSS (2) VSS Supply voltage (AVSS = DVSS) TA Operating free-air temperature TJ Operating junction temperature CVCORE Recommended capacitor at VCORE CDVCC/ CVCORE Capacitor ratio of DVCC to VCORE (3) (4) NOM MAX PMMCOREVx = 0 1.8 3.6 PMMCOREVx = 0, 1 2.0 3.6 PMMCOREVx = 0, 1, 2 2.2 3.6 PMMCOREVx = 0, 1, 2, 3 (2) V ±250 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±1000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V may actually have higher performance. MIN (1) UNIT UNIT V 2.4 3.6 1.62 1.98 V –40 85 °C –40 85 °C 0 (4) V 470 nF 10 TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be tolerated during power up and operation. During VCC and VIO power up, it is required that VIO ≥ VCC during the ramp up phase of VIO. During VCC and VIO power down, it is required that VIO ≥ VCC during the ramp down phase of VIO (see Figure 5-1). The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the Section 5.28 threshold parameters for the exact values and further details. A capacitor tolerance of ±20% or better is required. Specifications Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 21 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com Recommended Operating Conditions (continued) MIN fSYSTEM (5) Processor frequency (maximum MCLK frequency) (5) (see Figure 5-3) NOM MAX PMMCOREVx = 0 (default condition), 1.8 V ≤ VCC ≤ 3.6 V 0 8 PMMCOREVx = 1, 2.0 V ≤ VCC ≤ 3.6 V 0 12 PMMCOREVx = 2, 2.2 V ≤ VCC ≤ 3.6 V 0 20 PMMCOREVx = 3, 2.4 V ≤ VCC ≤ 3.6 V 0 25 UNIT MHz Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet. VCC VIO VIO,min VSS t VCC ≤ VIO while VIO < VIO,min VIO ≤ VCC VCC ≤ VIO while VIO < VIO,min NOTE: The device supports continuous operation with VCC = VSS while VIO is fully within its specification. During this time, the general-purpose I/Os that reside on the VIO supply domain are configured as inputs and pulled down to VSS through their internal pulldown resistors. RST/NMI is high impedance. BSLEN is configured as an input and is pulled down to VSS through its internal pulldown resistor. When VCC reaches above the BOR threshold, the general-purpose I/Os become high-impedance inputs (no resistor enabled), RST/NMI becomes an input pulled up to VIO through its internal pullup resistor, and BSLEN remains pulled down to VSS through its internal pulldown resistor. NOTE: Under certain condtions during the rising transition of VCC, the general-purpose I/Os residing on the VIO supply domain may actively transition high momentarily before settling to high-impedance inputs. These voltage transitions are temporary (typically resolving to high-impedance inputs when VCC exceeds approximately 0.9 V) and are bounded by the VIO supply. Figure 5-1. VCC and VIO Power Sequencing 22 Specifications Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 VCC V(SVSH_+), min tWAKE_UP_RESET tWAKE_UP_RESET tWAKE_UP_RESET DVCC VCC VIT+ RSTDVCC VCC ≥ VRSTDVCC VRSTDVCC = VCC VIO tWAKE_UP_RESET tWAKE_UP_RESET DVIO VIO VIT+ RST VIO ≥ VRST VRST = VIO t NOTE: The device remains in reset based on the conditions of the RSTDVCC and RST pins and the voltage present on DVCC voltage supply. If RSTDVCC or RST is held at a logic low or if DVCC is below the SVSH_+ minimum threshold, the device remains in its reset condition; that is, these conditions form a logical OR with respect to device reset. Figure 5-2. Reset Timing Specifications Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 23 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 25 System Frequency - MHz 3 20 2 2, 3 1 1, 2 1, 2, 3 0, 1 0, 1, 2 0, 1, 2, 3 12 8 0 0 1.8 2.0 2.2 2.4 3.6 Supply Voltage - V NOTE: The numbers within the fields denote the supported PMMCOREVx settings. Figure 5-3. Maximum System Frequency 5.4 Active Mode Supply Current Into VCC Excluding External Current over recommended operating free-air temperature (unless otherwise noted) (1) (2) (3) FREQUENCY (fDCO = fMCLK = fSMCLK) PARAMETER IAM, IAM, (1) (2) (3) 24 Flash RAM EXECUTION MEMORY Flash RAM VCC 3.0 V 3.0 V PMMCOREVx 1 MHz 8 MHz 12 MHz 20 MHz TYP MAX TYP MAX TYP MAX 0 0.36 0.47 2.32 2.60 1 0.40 2.65 2 0.44 4.0 4.4 2.90 3 0.46 0 0.20 1 0.22 1.35 2.0 2 0.24 1.50 2.2 3.7 3 0.26 1.60 2.4 3.9 3.10 0.29 1.20 25 MHz TYP MAX 4.3 7.1 7.7 4.6 7.6 TYP UNIT MAX mA 10.1 11.0 1.30 2.2 mA 4.2 5.3 6.2 All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are chosen to closely match the required 12.5 pF. Characterized with program executing typical data processing. fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency. XTS = CPUOFF = SCG0 = SCG1 = OSCOFF= SMCLKOFF = 0. Specifications Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com 5.5 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 Low-Power Mode Supply Currents (Into VCC) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) PARAMETER ILPM0,1MHz Low-power mode 0 (3) (4) ILPM2 Low-power mode 2 (5) (4) VCC PMMCOREVx 2.2 V 0 3.0 V 3 2.2 V 3.0 V 2.2 V ILPM3,XT1LF Low-power mode 3, crystal mode (6) (4) 3.0 V ILPM3,VLO Low-power mode 3, VLO mode (7) (4) 3.0 V –40°C TYP 25°C MAX 60°C 85°C TYP MAX TYP 73 77 91 80 85 97 79 83 99 88 95 107 0 6.5 6.5 12 10 11 17 3 7.0 7.0 13 11 12 18 0 1.60 1.90 2,8 6.0 1 1.65 2.00 3.0 6.3 2 1.75 2.15 3.2 6.6 0 1.8 2.1 3.0 6.2 1 1.9 2.3 3.2 6.5 2 2.0 2.4 3.3 6.8 3 2.0 2.5 3.9 3.4 6.8 10.9 0 1.1 1.4 2.7 2.0 6.1 9.7 1 1.1 1.4 2.2 6.4 2 1.2 1.5 2.3 6.8 3 1.3 1.6 3.0 2.3 6.8 10.9 0 0.9 1.1 1.5 2.0 5.1 8.8 1 1.1 1.2 2.1 5.3 2 1.2 1.2 2.2 5.5 2.9 MAX TYP MAX 9.4 Low-power mode 4 (8) (4) 3.0 V 1.3 1.3 1.6 2.2 5.5 9.8 ILPM4.5 Low-power mode 4.5 (9) 3.0 V 0.15 0.18 0.35 0.26 0.5 1.0 IDVIO_START Current supplied from DVIO while DVCC = AVCC = 0 V, DVIO = 1.62 V to 1.98 V, All DVIO I/O floating including BSLEN and RST/NMI 0V 1.8 1.8 1.8 1.8 (1) (2) (3) (4) (5) (6) (7) (8) (9) µA µA µA µA ILPM4 3 UNIT µA µA µA All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are chosen to closely match the required 12.5 pF. Current for the watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz Current for brownout and high-side supervisor (SVSH) normal mode included. Low-side supervisor (SVSL) and low-side monitor (SVML) disabled. High-side monitor (SVMH) disabled. RAM retention enabled. Current for watchdog timer and RTC clocked by ACLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz; DCO setting = 1 MHz operation, DCO bias generator enabled.) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz Current for watchdog timer and RTC clocked by ACLK included. ACLK = VLO. CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz Internal regulator disabled. No data retention. CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz Specifications Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 25 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 5.6 www.ti.com Thermal Resistance Characteristics THERMAL METRIC (1) RθJA Junction-to-ambient thermal resistance, still air RθJC(TOP) Junction-to-case (top) thermal resistance RθJC(BOTTOM) RθJB ΨJT ΨJB (1) (2) (3) 26 Junction-to-case (bottom) thermal resistance Junction-to-board thermal resistance Junction-to-package-top thermal characterization parameter Junction-to-board thermal characterization parameter VALUE (2) VQFN 48 (RGZ) 27.8 VQFN 64 (RGC) 29.6 DSBGA 64 (YFF) 44.3 BGA 80 (ZQE) 35.2 VQFN 48 (RGZ) 13.6 VQFN 64 (RGC) 14.8 DSBGA 64 (YFF) 0.2 BGA 80 (ZQE) 17.6 VQFN 48 (RGZ) 0.9 VQFN 64 (RGC) 1.4 DSBGA 64 (YFF) N/A (3) BGA 80 (ZQE) N/A VQFN 48 (RGZ) 4.7 VQFN 64 (RGC) 8.5 DSBGA 64 (YFF) 6.0 BGA 80 (ZQE) 16.7 VQFN 48 (RGZ) 0.2 VQFN 64 (RGC) 0.2 DSBGA 64 (YFF) 0.6 BGA 80 (ZQE) 0.3 VQFN 48 (RGZ) 4.7 VQFN 64 (RGC) 8.4 DSBGA 64 (YFF) 6.0 BGA 80 (ZQE) 9.6 UNIT °C/W °C/W °C/W °C/W °C/W °C/W For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics. These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RθJC] value, which is based on a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards: • JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air) • JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages • JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages • JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements N/A = not applicable Specifications Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 Schmitt-Trigger Inputs – General-Purpose I/O DVCC Domain (1) (P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RSTDVCC) 5.7 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VIT+ Positive-going input threshold voltage VIT– Negative-going input threshold voltage Vhys Input voltage hysteresis (VIT+ – VIT–) RPull Pullup or pulldown resistor (2) For pullup: VIN = VSS, For pulldown: VIN = VCC CI Input capacitance VIN = VSS or VCC (1) (2) VCC MIN 1.8 V 0.80 TYP 1.40 3V 1.50 2.10 1.8 V 0.45 1.00 3V 0.75 1.65 1.8 V 0.3 0.8 3V 0.4 1.0 20 35 MAX 50 5 UNIT V V V kΩ pF Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN). RSTDVCC has a fixed pullup resistor that cannot be disabled. 5.8 Schmitt-Trigger Inputs – General-Purpose I/O DVIO Domain (P1.4 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5, RST/NMI, BSLEN) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VIT+ Positive-going input threshold voltage VCC = 3.0 V VIT– Negative-going input threshold voltage VCC = 3.0 V Vhys Input voltage hysteresis (VIT+ – VIT–) VCC = 3.0 V RPull Pullup or pulldown resistor (1) For pullup: VIN = VSS, For pulldown: VIN = VIO CI Input capacitance VIN = VSS or VIO (1) 5.9 VIO MIN 1.62 V 0.8 TYP 1.25 1.98 V 1.1 1.40 1.62 V 0.3 0.7 1.98 V 0.5 1.0 1.62 V to 1.98 V 0.3 0.8 V 50 kΩ 20 MAX 35 5 UNIT V V pF Also applies to RST pin when pullup or pulldown resistor is enabled. Inputs – Interrupts DVCC Domain Port P1 (P1.0 to P1.3) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER t(int) (1) External interrupt timing TEST CONDITIONS (1) External trigger pulse duration to set interrupt flag VCC 1.8 V, 3 V MIN MAX 20 UNIT ns An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals shorter than t(int). 5.10 Inputs – Interrupts DVIO Domain Ports P1 and P2 (P1.4 to P1.7, P2.0 to P2.7) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER t(int) (1) (2) External interrupt timing (2) TEST CONDITIONS External trigger pulse duration to set interrupt flag, VCC = 1.8 V or 3.0 V VIO (1) 1.62 V to 1.98 V MIN MAX 20 UNIT ns In all test conditions, VIO ≤ VCC. An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals shorter than t(int). Specifications Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 27 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 5.11 Leakage Current – General-Purpose I/O DVCC Domain (P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER Ilkg(Px.y) (1) (2) High-impedance leakage current TEST CONDITIONS (1) (2) VCC MIN MAX 1.8 V, 3 V –50 50 UNIT nA The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is disabled. 5.12 Leakage Current – General-Purpose I/O DVIO Domain (P1.4 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER Ilkg(Px.y) (1) (2) (3) High-impedance leakage current TEST CONDITIONS (2) (3) VIO (1) 1.62 V to 1.98 V MIN MAX –50 50 UNIT nA In all test conditions, VIO ≤ VCC. The leakage current is measured with VSS or VIO applied to the corresponding pins, unless otherwise noted. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is disabled. 5.13 Outputs – General-Purpose I/O DVCC Domain (Full Drive Strength) (P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS I(OHmax) = –3 mA (1) VOH High-level output voltage I(OHmax) = –10 mA (2) VCC 1.8 V I(OHmax) = –5 mA (1) 3V I(OHmax) = –15 mA (2) I(OLmax) = 3 mA VOL Low-level output voltage (2) MAX VCC VCC – 0.60 VCC VCC – 0.25 VCC VCC – 0.60 VCC VSS VSS + 0.25 VSS VSS + 0.60 VSS VSS + 0.25 VSS VSS + 0.60 (1) 1.8 V I(OLmax) = 10 mA (2) I(OLmax) = 5 mA (1) 3V I(OLmax) = 15 mA (2) (1) MIN VCC – 0.25 UNIT V V The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop specified. The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage drop specified. 5.14 Outputs – General-Purpose I/O DVCC Domain (Reduced Drive Strength) (P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TEST CONDITIONS I(OHmax) = –1 mA VOH High-level output voltage I(OHmax) = –3 mA (3) I(OHmax) = –2 mA (2) I(OHmax) = –6 mA (3) I(OLmax) = 1 mA VOL Low-level output voltage (3) 28 1.8 V 3.0 V (2) I(OLmax) = 3 mA (3) I(OLmax) = 2 mA (2) I(OLmax) = 6 mA (3) (1) (2) VCC (2) 1.8 V 3.0 V MIN MAX VCC – 0.25 VCC VCC – 0.60 VCC VCC – 0.25 VCC VCC – 0.60 VCC VSS VSS + 0.25 VSS VSS + 0.60 VSS VSS + 0.25 VSS VSS + 0.60 UNIT V V Selecting reduced drive strength may reduce EMI. The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop specified. The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage drop specified. Specifications Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 5.15 Outputs – General-Purpose I/O DVIO Domain (Full Drive Strength) (P1.4 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VOH High-level output voltage VOL Low-level output voltage (1) (2) TEST CONDITIONS I(OHmax) = –3 mA VIO (1) (2) I(OHmax) = –6 mA (2) I(OLmax) = 3 mA (2) I(OLmax) = 6 mA (2) 1.62 V to 1.98 V MIN MAX VIO – 0.25 VIO VIO – 0.50 VIO VSS VSS + 0.25 1.62 V to 1.98 V VSS VSS + 0.50 UNIT V V In all test conditions, VIO ≤ VCC. The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop specified. 5.16 Outputs – General-Purpose I/O DVIO Domain (Reduced Drive Strength) (P1.4 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER VOH High-level output voltage VOL Low-level output voltage (1) (2) (3) TEST CONDITIONS I(OHmax) = –1 mA VIO (2) (3) I(OHmax) = –2 mA (3) I(OLmax) = 1 mA (3) I(OLmax) = 2 mA (3) 1.62 V to 1.98 V 1.62 V to 1.98 V MIN MAX VIO – 0.25 VIO VIO – 0.50 VIO VSS VSS + 0.25 VSS VSS + 0.50 UNIT V V Selecting reduced drive strength may reduce EMI. In all test conditions, VIO ≤ VCC. The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop specified. Specifications Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 29 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 5.17 Output Frequency – General-Purpose I/O DVCC Domain (P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER Port output frequency (with load) fPx.y fPort_CLK (1) (2) Clock output frequency TEST CONDITIONS (1) (2) ACLK, SMCLK, or MCLK, CL = 20 pF (2) MIN MAX VCC = 1.8 V, PMMCOREVx = 0 16 VCC = 3 V, PMMCOREVx = 3 25 VCC = 1.8 V, PMMCOREVx = 0 16 VCC = 3 V, PMMCOREVx = 3 25 UNIT MHz MHz A resistive divider with 2 × R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For full drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency. 5.18 Output Frequency – General-Purpose I/O DVIO Domain (P1.4 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER Port output frequency (with load) fPx.y fPort_CLK (1) (2) (3) 30 Clock output frequency TEST CONDITIONS (1) (2) ACLK, SMCLK, or MCLK, CL = 20 pF (2) MIN MAX VIO = 1.62 V to 1.98 V (3), PMMCOREVx = 0 16 VIO = 1.62 V to 1.98 V (3), PMMCOREVx = 3 25 VIO = 1.62 V to 1.98 V (3), PMMCOREVx = 0 16 VIO = 1.62 V to 1.98 V (3), PMMCOREVx = 3 25 UNIT MHz MHz A resistive divider with 2 × R1 between VIO and VSS is used as load. The output is connected to the center tap of the divider. For full drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS. The output voltage reaches at least 10% and 90% VIO at the specified toggle frequency. In all test conditions, VIO ≤ VCC. Specifications Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 5.19 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) 8.0 VCC = 3.0 V Px.y IOL – Typical Low-Level Output Current – mA IOL – Typical Low-Level Output Current – mA 25.0 TA = 25°C 20.0 TA = 85°C 15.0 10.0 5.0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 IOH – Typical High-Level Output Current – mA IOH – Typical High-Level Output Current – mA −10.0 −20.0 −25.0 0.0 4.0 3.0 2.0 1.0 0.0 −5.0 −15.0 5.0 TA = 85°C TA = 25°C 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOH – High-Level Output Voltage – V Figure 5-6. Typical High-Level Output Current vs High-Level Output Voltage 0.5 1.0 1.5 −1.0 VCC = 1.8 V Px.y −2.0 −3.0 −4.0 −5.0 −6.0 TA = 85°C TA = 25°C −7.0 −8.0 0.0 0.5 1.0 1.5 2.0 VOH – High-Level Output Voltage – V Figure 5-7. Typical High-Level Output Current vs High-Level Output Voltage Specifications Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 2.0 VOL – Low-Level Output Voltage – V Figure 5-5. Typical Low-Level Output Current vs Low-Level Output Voltage 0.0 VCC = 3.0 V Px.y TA = 85°C 6.0 0.0 0.0 3.5 VOL – Low-Level Output Voltage – V Figure 5-4. Typical Low-Level Output Current vs Low-Level Output Voltage 7.0 TA = 25°C VCC = 1.8 V Px.y 31 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 5.20 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) 55.0 24 TA = 25°C VCC = 3.0 V Px.y 50.0 IOL – Typical Low-Level Output Current – mA IOL – Typical Low-Level Output Current – mA 60.0 TA = 85°C 45.0 40.0 35.0 30.0 25.0 20.0 15.0 10.0 0.5 1.0 1.5 2.0 2.5 3.0 TA = 85°C 16 12 8 4 0 0.0 3.5 VOL – Low-Level Output Voltage – V Figure 5-8. Typical Low-Level Output Current vs Low-Level Output Voltage −10.0 −15.0 −20.0 −25.0 −30.0 −35.0 −40.0 −45.0 −50.0 TA = 85°C −55.0 −60.0 0.0 1.0 1.5 2.0 0 VCC = 3.0 V Px.y IOH – Typical High-Level Output Current – mA −5.0 0.5 VOL – Low-Level Output Voltage – V Figure 5-9. Typical Low-Level Output Current vs Low-Level Output Voltage 0.0 IOH – Typical High-Level Output Current – mA TA = 25°C 20 5.0 0.0 0.0 TA = 25°C 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOH – High-Level Output Voltage – V Figure 5-10. Typical High-Level Output Current vs High-Level Output Voltage 32 VCC = 1.8 V Px.y Specifications VCC = 1.8 V Px.y −4 −8 −12 TA = 85°C −16 TA = 25°C −20 0.0 0.5 1.0 1.5 2.0 VOH – High-Level Output Voltage – V Figure 5-11. Typical High-Level Output Current vs High-Level Output Voltage Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 5.21 Crystal Oscillator, XT1, Low-Frequency Mode over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TEST CONDITIONS VCC MIN fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1, TA = 25°C ΔIDVCC.LF Differential XT1 oscillator crystal current consumption from lowest drive setting, LF mode fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 2, TA = 25°C 0.170 32768 XTS = 0, XT1BYPASS = 0 fXT1,LF,SW XT1 oscillator logic-level squarewave input frequency, LF mode XTS = 0, XT1BYPASS = 1 (2) (3) XT1BYPASSLV = 0 or 1 OALF 3.0 V 0.290 XT1 oscillator crystal frequency, LF mode 10 CL,eff fFault,LF tSTART,LF (1) (2) (3) (4) (5) (6) (7) (8) 32.768 XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0, fXT1,LF = 32768 Hz, CL,eff = 6 pF 210 XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1, fXT1,LF = 32768 Hz, CL,eff = 12 pF 300 µA Hz 50 5.5 XTS = 0, XCAPx = 2 8.5 XTS = 0, XCAPx = 3 12.0 pF Duty cycle, LF mode XTS = 0, Measured at ACLK, fXT1,LF = 32768 Hz 30% 70% Oscillator fault frequency, LF mode (7) XTS = 0, XT1BYPASS = 1 (8), XT1BYPASSLV = 0 or 1 10 10000 Start-up time, LF mode fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 3, TA = 25°C, CL,eff = 12 pF kHz 1 XTS = 0, XCAPx = 1 fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0, TA = 25°C, CL,eff = 6 pF UNIT kΩ XTS = 0, XCAPx = 0 (6) Integrated effective load capacitance, LF mode (5) MAX 0.075 fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 3, TA = 25°C fXT1,LF0 Oscillation allowance for LF crystals (4) TYP Hz 1000 3.0 V ms 500 To improve EMI on the XT1 oscillator, the following guidelines should be observed. • Keep the trace between the device and the crystal as short as possible. • Design a good ground plane around the oscillator pins. • Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. • Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. • Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins. • If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins. When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in the Schmitt-Trigger Inputs section of this data sheet. When in crystal bypass mode, XIN can be configured so that it can support an input digital waveform with swing levels from DVSS to DVCC (XT1BYPASSLV = 0) or DVSS to DVIO (XT1BYPASSLV = 1). In this case, the pin must be configured properly for the intended input swing. Maximum frequency of operation of the entire device cannot be exceeded. Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following guidelines, but each application should be evaluated based on the actual crystal selected: • For XT1DRIVEx = 0, CL,eff ≤ 6 pF • For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF • For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF • For XT1DRIVEx = 3, CL,eff ≥ 6 pF Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal. Requires external capacitors at both terminals. Values are specified by crystal manufacturers. Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specifications might set the flag. Measured with logic-level input frequency but also applies to operation with crystals. Specifications Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 33 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 5.22 Crystal Oscillator, XT2 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) PARAMETER TEST CONDITIONS VCC MIN fOSC = 4 MHz, XT2OFF = 0, XT2BYPASS = 0, XT2DRIVEx = 0, TA = 25°C IDVCC.XT2 XT2 oscillator crystal current consumption fOSC = 12 MHz, XT2OFF = 0, XT2BYPASS = 0, XT2DRIVEx = 1, TA = 25°C fOSC = 20 MHz, XT2OFF = 0, XT2BYPASS = 0, XT2DRIVEx = 2, TA = 25°C TYP MAX UNIT 200 260 3.0 V µA 325 fOSC = 32 MHz, XT2OFF = 0, XT2BYPASS = 0, XT2DRIVEx = 3, TA = 25°C 450 fXT2,HF0 XT2 oscillator crystal frequency, mode 0 XT2DRIVEx = 0, XT2BYPASS = 0 (3) 4 8 MHz fXT2,HF1 XT2 oscillator crystal frequency, mode 1 XT2DRIVEx = 1, XT2BYPASS = 0 (3) 8 16 MHz fXT2,HF2 XT2 oscillator crystal frequency, mode 2 XT2DRIVEx = 2, XT2BYPASS = 0 (3) 16 24 MHz fXT2,HF3 XT2 oscillator crystal frequency, mode 3 XT2DRIVEx = 3, XT2BYPASS = 0 (3) 24 32 MHz fXT2,HF,SW XT2 oscillator logic-level squarewave input frequency, bypass mode XT2BYPASS = 1 (4) (3) XT2BYPASSLV = 0 or 1 0.7 32 MHz Oscillation allowance for HF crystals (5) OAHF tSTART,HF CL,eff Start-up time Integrated effective load capacitance, HF mode (6) Duty cycle (1) (2) (3) (4) (5) (6) 34 XT2DRIVEx = 0, XT2BYPASS = 0, fXT2,HF0 = 6 MHz, CL,eff = 15 pF 450 XT2DRIVEx = 1, XT2BYPASS = 0, fXT2,HF1 = 12 MHz, CL,eff = 15 pF 320 XT2DRIVEx = 2, XT2BYPASS = 0, fXT2,HF2 = 20 MHz, CL,eff = 15 pF 200 XT2DRIVEx = 3, XT2BYPASS = 0, fXT2,HF3 = 32 MHz, CL,eff = 15 pF 200 fOSC = 6 MHz, XT2BYPASS = 0, XT2DRIVEx = 0, TA = 25°C, CL,eff = 15 pF 0.5 fOSC = 20 MHz, XT2BYPASS = 0, XT2DRIVEx = 2, TA = 25°C, CL,eff = 15 pF Ω 3.0 V ms 0.3 1 (1) Measured at ACLK, fXT2,HF2 = 20 MHz 40% 50% pF 60% Requires external capacitors at both terminals. Values are specified by crystal manufacturers. To improve EMI on the XT2 oscillator the following guidelines should be observed. • Keep the traces between the device and the crystal as short as possible. • Design a good ground plane around the oscillator pins. • Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT. • Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins. • Use assembly materials and processes that avoid any parasitic load on the oscillator XT2IN and XT2OUT pins. • If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins. This represents the maximum frequency that can be input to the device externally. Maximum frequency achievable on the device operation is based on the frequencies present on ACLK, MCLK, and SMCLK cannot be exceed for a given range of operation. When XT2BYPASS is set, the XT2 circuit is automatically powered down. Input signal is a digital square wave with parametrics defined in the Schmitt-trigger Inputs section of this data sheet. When in crystal bypass mode, XT2IN can be configured so that it can support an input digital waveform with swing levels from DVSS to DVCC (XT2BYPASSLV = 0) or DVSS to DVIO (XT2BYPASSLV = 1). In this case, it is required that the pin be configured properly for the intended input swing. Oscillation allowance is based on a safety factor of 5 for recommended crystals. Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal. Specifications Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 Crystal Oscillator, XT2 (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2) PARAMETER fFault,HF (7) (8) Oscillator fault frequency TEST CONDITIONS (7) VCC XT2BYPASS = 1 (8), XT2BYPASSLV = 0 or 1 MIN TYP 30 MAX UNIT 300 kHz Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specifications might set the flag. Measured with logic-level input frequency but also applies to operation with crystals. In general, an effective load capacitance of up to 18 pF can be supported. 5.23 Internal Very-Low-Power Low-Frequency Oscillator (VLO) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX 6 9.4 14 UNIT fVLO VLO frequency Measured at ACLK 1.8 V to 3.6 V dfVLO/dT VLO frequency temperature drift Measured at ACLK (1) 1.8 V to 3.6 V 0.5 %/°C Measured at ACLK (2) 1.8 V to 3.6 V 4 %/V Measured at ACLK 1.8 V to 3.6 V dfVLO/dVCC VLO frequency supply voltage drift Duty cycle (1) (2) 40% 50% kHz 60% Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C)) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V) 5.24 Internal Reference, Low-Frequency Oscillator (REFO) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER IREFO fREFO TEST CONDITIONS VCC MIN TYP REFO oscillator current consumption TA = 25°C 1.8 V to 3.6 V 3 REFO frequency Measured at ACLK 1.8 V to 3.6 V 32768 Full temperature range 1.8 V to 3.6 V –3.5% 3.5% 3V –1.5% 1.5% REFO absolute tolerance TA = 25°C (1) dfREFO/dT REFO frequency temperature drift Measured at ACLK 1.8 V to 3.6 V 0.01 dfREFO/dVCC REFO frequency supply voltage drift Measured at ACLK (2) 1.8 V to 3.6 V 1.0 Duty cycle Measured at ACLK 1.8 V to 3.6 V REFO start-up time 40%/60% duty cycle 1.8 V to 3.6 V tSTART (1) (2) MAX 40% 50% UNIT µA Hz %/°C %/V 60% 25 µs Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C)) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V) Specifications Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 35 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 5.25 DCO Frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT fDCO(0,0) DCO frequency (0, 0) DCORSELx = 0, DCOx = 0, MODx = 0 0.07 0.20 MHz fDCO(0,31) DCO frequency (0, 31) (1) DCORSELx = 0, DCOx = 31, MODx = 0 0.70 1.70 MHz fDCO(1,0) DCO frequency (1, 0) (1) DCORSELx = 1, DCOx = 0, MODx = 0 0.15 0.36 MHz fDCO(1,31) DCO frequency (1, 31) (1) DCORSELx = 1, DCOx = 31, MODx = 0 1.47 3.45 MHz (1) fDCO(2,0) DCO frequency (2, 0) DCORSELx = 2, DCOx = 0, MODx = 0 0.32 0.75 MHz fDCO(2,31) DCO frequency (2, 31) (1) DCORSELx = 2, DCOx = 31, MODx = 0 3.17 7.38 MHz fDCO(3,0) DCO frequency (3, 0) (1) DCORSELx = 3, DCOx = 0, MODx = 0 0.64 1.51 MHz (1) fDCO(3,31) DCO frequency (3, 31) DCORSELx = 3, DCOx = 31, MODx = 0 6.07 14.0 MHz fDCO(4,0) DCO frequency (4, 0) (1) DCORSELx = 4, DCOx = 0, MODx = 0 1.3 3.2 MHz fDCO(4,31) DCO frequency (4, 31) (1) DCORSELx = 4, DCOx = 31, MODx = 0 12.3 28.2 MHz (1) fDCO(5,0) DCO frequency (5, 0) DCORSELx = 5, DCOx = 0, MODx = 0 2.5 6.0 MHz fDCO(5,31) DCO frequency (5, 31) (1) DCORSELx = 5, DCOx = 31, MODx = 0 23.7 54.1 MHz fDCO(6,0) DCO frequency (6, 0) (1) DCORSELx = 6, DCOx = 0, MODx = 0 4.6 10.7 MHz fDCO(6,31) DCO frequency (6, 31) (1) DCORSELx = 6, DCOx = 31, MODx = 0 39.0 88.0 MHz (1) fDCO(7,0) DCO frequency (7, 0) DCORSELx = 7, DCOx = 0, MODx = 0 8.5 19.6 MHz fDCO(7,31) DCO frequency (7, 31) (1) DCORSELx = 7, DCOx = 31, MODx = 0 60 135 MHz SDCORSEL Frequency step between range DCORSEL and DCORSEL + 1 SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO) 1.2 2.3 ratio SDCO Frequency step between tap DCO and DCO + 1 SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO) 1.02 1.12 ratio Duty cycle Measured at SMCLK 40% DCO frequency temperature drift (2) dfDCO/dT dfDCO/dVCC (1) (2) (3) DCO frequency voltage drift (3) 50% 60% fDCO = 1 MHz 0.1 %/°C fDCO = 1 MHz 1.9 %/V When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within the range of fDCO(n, 0),MAX ≤ fDCO ≤ fDCO(n, 31),MIN, where fDCO(n, 0),MAX represents the maximum frequency specified for the DCO frequency, range n, tap 0 (DCOx = 0) and fDCO(n,31),MIN represents the minimum frequency specified for the DCO frequency, range n, tap 31 (DCOx = 31). This ensures that the target DCO frequency resides within the range selected. It should also be noted that if the actual fDCO frequency for the selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the selected range is at its minimum or maximum tap setting. Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C)) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V) 100 VCC = 3.0 V TA = 25°C fDCO – MHz 10 DCOx = 31 1 0.1 DCOx = 0 0 1 2 3 4 5 6 7 DCORSEL Figure 5-12. Typical DCO Frequency 36 Specifications Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 5.26 PMM, Brownout Reset (BOR) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VDVCC_BOR_IT– BORH on voltage, DVCC falling level | dDVCC/dt | < 3 V/s VDVCC_BOR_IT+ BORH off voltage, DVCC rising level | dDVCC/dt | < 3 V/s VDVCC_BOR_hys BORH hysteresis tRESET Pulse duration required at RST/NMI pin to accept a reset MIN TYP 0.80 1.30 50 MAX UNIT 1.45 V 1.50 V 250 mV 2 µs 5.27 PMM, Core Voltage over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCORE3(AM) Core voltage, active mode, PMMCOREV = 3 2.4 V ≤ DVCC ≤ 3.6 V 1.90 V VCORE2(AM) Core voltage, active mode, PMMCOREV = 2 2.2 V ≤ DVCC ≤ 3.6 V 1.80 V VCORE1(AM) Core voltage, active mode, PMMCOREV = 1 2.0 V ≤ DVCC ≤ 3.6 V 1.60 V VCORE0(AM) Core voltage, active mode, PMMCOREV = 0 1.8 V ≤ DVCC ≤ 3.6 V 1.40 V VCORE3(LPM) Core voltage, low-current mode, PMMCOREV = 3 2.4 V ≤ DVCC ≤ 3.6 V 1.94 V VCORE2(LPM) Core voltage, low-current mode, PMMCOREV = 2 2.2 V ≤ DVCC ≤ 3.6 V 1.84 V VCORE1(LPM) Core voltage, low-current mode, PMMCOREV = 1 2.0 V ≤ DVCC ≤ 3.6 V 1.64 V VCORE0(LPM) Core voltage, low-current mode, PMMCOREV = 0 1.8 V ≤ DVCC ≤ 3.6 V 1.44 V Specifications Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 37 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 5.28 PMM, SVS High Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN SVSHE = 0, DVCC = 3.6 V I(SVSH) SVS current consumption V(SVSH_IT+) tpd(SVSH) t(SVSH) 38 SVSH off voltage level (1) SVSH propagation delay SVSH on or off delay time dVDVCC/dt (1) SVSH on voltage level (1) DVCC rise time MAX 0 SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0 1.5 µA SVSHE = 1, SVSHRVL = 0 1.57 1.68 1.78 SVSHE = 1, SVSHRVL = 1 1.79 1.88 1.98 SVSHE = 1, SVSHRVL = 2 1.98 2.08 2.21 SVSHE = 1, SVSHRVL = 3 2.10 2.18 2.31 SVSHE = 1, SVSMHRRL = 0 1.62 1.74 1.85 SVSHE = 1, SVSMHRRL = 1 1.88 1.94 2.07 SVSHE = 1, SVSMHRRL = 2 2.07 2.14 2.28 SVSHE = 1, SVSMHRRL = 3 2.20 2.30 2.42 SVSHE = 1, SVSMHRRL = 4 2.32 2.40 2.55 SVSHE = 1, SVSMHRRL = 5 2.52 2.70 2.88 SVSHE = 1, SVSMHRRL = 6 2.90 3.10 3.23 SVSHE = 1, SVSMHRRL = 7 2.90 3.10 3.23 SVSHE = 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1 2.5 SVSHE = 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0 20 UNIT nA 200 SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1 V(SVSH_IT–) TYP V V µs SVSHE = 0 → 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1 12.5 SVSHE = 0 → 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0 100 µs 0 1000 V/s The SVSH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430F5xx and MSP430F6xx Family User's Guide on recommended settings and use. Specifications Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 5.29 PMM, SVM High Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP SVMHE = 0, DVCC = 3.6 V I(SVMH) SVMH current consumption 0 SVMHE= 1, DVCC = 3.6 V, SVMHFP = 0 V(SVMH) SVMH on or off voltage level 1.5 tpd(SVMH) t(SVMH) (1) SVMH propagation delay SVMH on or off delay time µA SVMHE = 1, SVSMHRRL = 0 1.62 1.74 1.85 SVMHE = 1, SVSMHRRL = 1 1.88 1.94 2.07 SVMHE = 1, SVSMHRRL = 2 2.07 2.14 2.28 SVMHE = 1, SVSMHRRL = 3 2.20 2.30 2.42 SVMHE = 1, SVSMHRRL = 4 2.32 2.40 2.55 SVMHE = 1, SVSMHRRL = 5 2.52 2.70 2.88 SVMHE = 1, SVSMHRRL = 6 2.90 3.10 3.23 SVMHE = 1, SVSMHRRL = 7 2.90 3.10 3.23 SVMHE = 1, SVMHOVPE = 1 UNIT nA 200 SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1 (1) MAX V 3.75 SVMHE = 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1 2.5 SVMHE = 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0 20 µs SVMHE = 0 → 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1 12.5 SVMHE = 0 → 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0 100 µs The SVMH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430F5xx and MSP430F6xx Family User's Guide on recommended settings and use. 5.30 PMM, SVS Low Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS SVSLE = 0, PMMCOREV = 2 I(SVSL) SVSL current consumption tpd(SVSL) SVSL propagation delay t(SVSL) SVSL on or off delay time MIN TYP MAX 0 SVSLE = 1, PMMCOREV = 2, SVSLFP = 0 200 SVSLE = 1, PMMCOREV = 2, SVSLFP = 1 1.5 SVSLE = 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1 2.5 SVSLE = 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0 20 SVSLE = 0 → 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1 12.5 SVSLE = 0 → 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0 100 Specifications Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated UNIT nA µA µs µs 39 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 5.31 PMM, SVM Low Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN SVMLE = 0, PMMCOREV = 2 I(SVML) SVML current consumption tpd(SVML) SVML propagation delay t(SVML) SVML on or off delay time TYP MAX 0 SVMLE= 1, PMMCOREV = 2, SVMLFP = 0 200 SVMLE= 1, PMMCOREV = 2, SVMLFP = 1 1.5 SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1 2.5 SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0 20 SVMLE = 0 → 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1 12.5 SVMLE = 0 → 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0 100 UNIT nA µA µs µs 5.32 Wake-up Times From Low-Power Modes and Reset over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS TYP MAX fMCLK ≥ 4.0 MHz MIN 3.5 7.5 UNIT 1.0 MHz < fMCLK < 4.0 MHz 4.5 9 150 175 µs tWAKE-UP-FAST Wake-up time from LPM2, LPM3, or LPM4 to active mode (1) PMMCOREV = SVSMLRRL = n (where n = 0, 1, 2, or 3), SVSLFP = 1 tWAKE-UP-SLOW Wake-up time from LPM2, LPM3, or LPM4 to active mode (2) (3) PMMCOREV = SVSMLRRL = n (where n = 0, 1, 2, or 3), SVSLFP = 0 tWAKE-UP-LPM5 Wake-up time from LPM4.5 to active mode (4) 2 3 ms tWAKE-UP-RESET Wake-up time from RST or BOR event to active mode (4) 2 3 ms (1) (2) (3) (4) 40 µs This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-FAST is possible with SVSL and SVML in full performance mode or disabled. For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode Selection section in the Power Management Module and Supply Voltage Supervisor chapter of the MSP430F5xx and MSP430F6xx Family User's Guide. This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-SLOW is set with SVSL and SVML in normal mode (low current mode). For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode Selection section in the Power Management Module and Supply Voltage Supervisor chapter of the MSP430F5xx and MSP430F6xx Family User's Guide. The wake-up times from LPM0 and LPM1 to AM are not specified. They are proportional to MCLK cycle time but are not affected by the performance mode settings as for LPM2, LPM3, and LPM4. This value represents the time from the wake-up event to the reset vector execution. Specifications Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 5.33 Timer_A over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VIO MIN TYP MAX UNIT 1.62 V to 1.8 V 25 Timer_A input clock frequency Internal: SMCLK or ACLK, External: TACLK, Duty cycle = 50% ±10% 1.8 V fTA 3.0 V 1.62 V to 1.98 V 25 Timer_A capture timing (1) All capture inputs, Minimum pulse duration required for capture 1.8 V 1.62 V to 1.8 V 20 tTA,cap 3.0 V 1.62 V to 1.98 V 20 (1) MHz ns The external signal sets the interrupt flag every time the minimum parameters are met. It may be set even with trigger signals shorter than tTA,cap. 5.34 Timer_B over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VIO MIN TYP MAX UNIT 1.62 V to 1.8 V 25 Timer_B input clock frequency Internal: SMCLK or ACLK, External: TBCLK, Duty cycle = 50% ±10% 1.8 V fTB 3.0 V 1.62 V to 1.98 V 25 Timer_B capture timing (1) All capture inputs, Minimum pulse duration required for capture 1.8 V 1.62 V to 1.8 V 20 tTB,cap 3.0 V 1.62 V to 1.98 V 20 (1) MHz ns The external signal sets the interrupt flag every time the minimum parameters are met. It may be set even with trigger signals shorter than tTB,cap. Specifications Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 41 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 5.35 USCI (UART Mode), Recommended Operating Conditions PARAMETER fUSCI USCI input clock frequency fBITCLK BITCLK clock frequency (equals baud rate in MBaud) TEST CONDITIONS MIN Internal: SMCLK or ACLK, External: UCLK, Duty cycle = 50% ±10% MAX UNIT fSYSTEM MHz 1 MHz UNIT 5.36 USCI (UART Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VIO MIN MAX 1.8 V 1.62 V to 1.80 V 50 600 3.0 V 1.62 V to 1.98 V 50 600 UART receive deglitch time (1) tτ (1) VCC ns Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are correctly recognized, their duration should exceed the maximum specification of the deglitch time. 5.37 USCI (SPI Master Mode), Recommended Operating Conditions PARAMETER fUSCI USCI input clock frequency TEST CONDITIONS MIN Internal: SMCLK or ACLK, Duty cycle = 50% ±10% MAX UNIT fSYSTEM MHz 5.38 USCI (SPI Master Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (see Figure 5-13 and Figure 5-14) PARAMETER fUSCI USCI input clock frequency TEST CONDITIONS PMMCOREV = 0 tSU,MI SOMI input data setup time PMMCOREV = 3 PMMCOREV = 0 tHD,MI SOMI input data hold time PMMCOREV = 3 tVALID,MO tHD,MO (1) (2) (3) 42 SIMO output data valid time (2) SIMO output data hold time (3) VCC VIO MIN SMCLK or ACLK, Duty cycle = 50% ±10% 1.8 V 1.62 V to 1.80 V 55 3.0 V 1.62 V to 1.98 V 55 2.4 V 1.62 V to 1.98 V 35 3.0 V 1.62 V to 1.98 V 35 1.8 V 1.62 V to 1.80 V 0 3.0 V 1.62 V to 1.98 V 0 2.4 V 1.62 V to 1.98 V 0 0 MAX UNIT fSYSTEM MHz ns ns 3.0 V 1.62 V to 1.98 V UCLK edge to SIMO valid, CL = 20 pF, PMMCOREV = 0 1.8 V 1.62 V to 1.80 V 20 3.0 V 1.62 V to 1.98 V 20 UCLK edge to SIMO valid, CL = 20 pF, PMMCOREV = 3 2.4 V 1.62 V to 1.98 V 16 3.0 V 1.62 V to 1.98 V 16 CL = 20 pF, PMMCOREV = 0 1.8 V 1.62 V to 1.80 V –10 3.0 V 1.62 V to 1.98 V –10 CL = 20 pF, PMMCOREV = 3 2.4 V 1.62 V to 1.98 V –10 3.0 V 1.62 V to 1.98 V –10 ns ns fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)) For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave. Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams in Figure 5-13 and Figure 5-14. Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 513 and Figure 5-14. Specifications Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tHD,MO tVALID,MO SIMO Figure 5-13. SPI Master Mode, CKPH = 0 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tHD,MO tVALID,MO SIMO Figure 5-14. SPI Master Mode, CKPH = 1 Specifications Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 43 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 5.39 USCI (SPI Slave Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (see Figure 5-15 and Figure 5-16) PARAMETER TEST CONDITIONS PMMCOREV = 0 tSTE,LEAD STE lead time, STE low to clock PMMCOREV = 3 PMMCOREV = 0 tSTE,LAG STE lag time, Last clock to STE high PMMCOREV = 3 PMMCOREV = 0 tSTE,ACC STE access time, STE low to SOMI data out PMMCOREV = 3 PMMCOREV = 0 STE disable time, STE high to SOMI high impedance tSTE,DIS PMMCOREV = 3 PMMCOREV = 0 tSU,SI SIMO input data setup time PMMCOREV = 3 PMMCOREV = 0 tHD,SI SIMO input data hold time PMMCOREV = 3 tVALID,SO tHD,SO (1) (2) (3) 44 SOMI output data valid time (2) SOMI output data hold time (3) VCC VIO 1.8 V 1.62 V to 1.80 V MIN 12 MAX 3.0 V 1.62 V to 1.98 V 12 2.4 V 1.62 V to 1.98 V 10 3.0 V 1.62 V to 1.98 V 10 1.8 V 1.62 V to 1.80 V 6 3.0 V 1.62 V to 1.98 V 6 2.4 V 1.62 V to 1.98 V 6 3.0 V 1.62 V to 1.98 V 6 1.8 V 1.62 V to 1.80 V 65 3.0 V 1.62 V to 1.98 V 65 2.4 V 1.62 V to 1.98 V 45 3.0 V 1.62 V to 1.98 V 45 1.8 V 1.62 V to 1.80 V 35 3.0 V 1.62 V to 1.98 V 35 2.4 V 1.62 V to 1.98 V 25 3.0 V 1.62 V to 1.98 V 1.8 V 1.62 V to 1.80 V 5 3.0 V 1.62 V to 1.98 V 5 2.4 V 1.62 V to 1.98 V 5 3.0 V 1.62 V to 1.98 V 5 1.8 V 1.62 V to 1.80 V 5 3.0 V 1.62 V to 1.98 V 5 2.4 V 1.62 V to 1.98 V 5 5 UNIT ns ns ns ns 25 ns ns 3.0 V 1.62 V to 1.98 V UCLK edge to SOMI valid, CL = 20 pF, PMMCOREV = 0 1.8 V 1.62 V to 1.80 V 75 3.0 V 1.62 V to 1.98 V 75 UCLK edge to SOMI valid, CL = 20 pF, PMMCOREV = 3 2.4 V 1.62 V to 1.98 V 50 3.0 V 1.62 V to 1.98 V 50 CL = 20 pF, PMMCOREV = 0 1.8 V 1.62 V to 1.80 V 18 3.0 V 1.62 V to 1.98 V 18 CL = 20 pF, PMMCOREV = 3 2.4 V 1.62 V to 1.98 V 10 3.0 V 1.62 V to 1.98 V 10 ns ns fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)) For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master. Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams in Figure 5-15 and Figure 5-16. Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-15 and Figure 5-16. Specifications Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tSU,SI tLO/HI tHD,SI SIMO tHD,SO tVALID,SO tSTE,ACC tSTE,DIS SOMI Figure 5-15. SPI Slave Mode, CKPH = 0 tSTE,LAG tSTE,LEAD STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tHD,SI tSU,SI SIMO tSTE,ACC tHD,MO tVALID,SO tSTE,DIS SOMI Figure 5-16. SPI Slave Mode, CKPH = 1 Specifications Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 45 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 5.40 USCI (I2C Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-17) PARAMETER TEST CONDITIONS fUSCI USCI input clock frequency fSCL SCL clock frequency tHD,STA Hold time (repeated) START tSU,STA Setup time for a repeated START tHD,DAT tSU,DAT MIN Internal: SMCLK or ACLK, External: UCLK, Duty cycle = 50% ±10% UNIT fSYSTEM MHz 400 kHz 1.62 V to 1.98 V 2.2 V, 3 V 1.62 V to 1.98 V 2.2 V, 3 V 1.62 V to 1.98 V Data hold time 2.2 V, 3 V 1.62 V to 1.98 V 0 ns Data setup time 2.2 V, 3 V 1.62 V to 1.98 V 250 ns Setup time for STOP tSP Pulse duration of spikes suppressed by input filter fSCL ≤ 100 kHz fSCL > 100 kHz fSCL ≤ 100 kHz fSCL > 100 kHz fSCL ≤ 100 kHz fSCL > 100 kHz 2.2 V, 3 V 1.62 V to 1.98 V 2.2 V, 3 V 1.62 V to 1.98 V 0 MAX 2.2 V, 3 V tSU,STO (1) VIO (1) VCC 4.0 µs 0.6 4.7 µs 0.6 4.0 µs 0.6 50 600 ns In all test conditions, VIO ≤ VCC tSU,STA tHD,STA tHD,STA tBUF SDA tLOW tHIGH tSP SCL tSU,DAT tSU,STO tHD,DAT Figure 5-17. I2C Mode Timing 46 Specifications Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 5.41 10-Bit ADC, Power Supply and Input Range Conditions over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TEST CONDITIONS VCC AVCC Analog supply voltage AVCC and DVCC are connected together, AVSS and DVSS are connected together, V(AVSS) = V(DVSS) = 0 V V(Ax) Analog input voltage range (2) All ADC10_A pins: P1.0 to P1.5 and P3.6 and P3.7 terminals Operating supply current into AVCC terminal, REF module and reference buffer off fADC10CLK = 5.0 MHz, ADC10ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF = 00 Operating supply current into AVCC terminal, REF module on, reference buffer on MIN TYP MAX 1.8 3.6 V 0 AVCC V 2.2 V 60 100 3V 75 110 fADC10CLK = 5.0 MHz, ADC10ON = 1, REFON = 1, SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF = 01 3V 113 150 Operating supply current into AVCC terminal, REF module off, reference buffer on fADC10CLK = 5.0 MHz, ADC10ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF = 10, VEREF = 2.5 V 3V 105 140 Operating supply current into AVCC terminal, REF module off, reference buffer off fADC10CLK = 5.0 MHz, ADC10ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF = 11, VEREF = 2.5 V 3V 70 110 CI Input capacitance Only one terminal Ax can be selected at one time from the pad to the ADC10_A capacitor array including wiring and pad. 2.2 V 3.5 RI Input MUX ON resistance IADC10_A (1) (2) UNIT µA pF AVCC > 2 V, 0 V ≤ VAx ≤ AVCC 36 1.8 V < AVCC < 2 V, 0 V ≤ VAx ≤ AVCC 96 kΩ The leakage current is defined in the leakage current table with P6.x/Ax parameter. The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. The external reference voltage requires decoupling capacitors. See (). 5.42 10-Bit ADC, Timing Parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT 2.2 V, 3 V 0.45 5 5.5 MHz 4.8 5.4 MHz fADC10CLK Input clock frequency For specified performance of ADC10_A linearity parameters fADC10OSC Internal ADC10_A oscillator (1) ADC10DIV = 0, fADC10CLK = fADC10OSC 2.2 V, 3 V 4.2 2.2 V, 3 V 2.4 Conversion time REFON = 0, Internal oscillator, 12 ADC10CLK cycles, 10-bit mode, fADC10OSC = 4 MHz to 5 MHz tCONVERT µs External fADC10CLK from ACLK, MCLK or SMCLK, ADC10SSEL ≠ 0 tADC10ON Turn on settling time of the ADC See tSample Sampling time RS = 1000 Ω, RI = 96 k Ω, CI = 3.5 pF (3) (1) (2) (3) 3.0 12 × 1 / fADC10CLK (2) 100 ns 1.8 V 3 µs 3.0 V 1 µs The ADC10OSC is sourced directly from MODOSC inside the UCS. The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already settled. Approximately 8 Tau (τ) are needed to get an error of less than ±0.5 LSB Specifications Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 47 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 5.43 10-Bit ADC, Linearity Parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS 1.4 V ≤ (VeREF+ – VeREF–) ≤ 1.6 V, CVeREF+ = 20 pF VCC MIN TYP MAX ±1.0 UNIT EI Integral linearity error ED Differential linearity error 1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF 2.2 V, 3 V ±1.0 LSB EO Offset error 1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF Internal impedance of source RS < 100 Ω 2.2 V, 3 V ±1.0 LSB EG Gain error 1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF, ADC10SREFx = 11b 2.2 V, 3 V ±1.0 LSB ET Total unadjusted error 1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF, ADC10SREFx = 11b 2.2 V, 3 V ±2.0 LSB 1.6 V < (VeREF+ – VeREF–) ≤ VAVCC, CVeREF+ = 20 pF 2.2 V, 3 V ±1.0 ±1.0 LSB 5.44 REF, External Reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER MIN MAX UNIT VeREF+ > VeREF– (2) 1.4 AVCC V Negative external reference voltage input VeREF+ > VeREF– (3) 0 1.2 V Differential external reference voltage input VeREF+ > VeREF– (4) 1.4 AVCC V –26 26 VeREF+ Positive external reference voltage input VeREF– (VeREF+ – VeREF–) IVeREF+, IVeREF– CVREF+, CVREF(1) (2) (3) (4) (5) 48 Static input current Capacitance at VeREF+ or VeREF- terminal TEST CONDITIONS VCC 1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V, fADC10CLK = 5 MHz, ADC10SHTx = 0x0001, Conversion rate = 200 ksps 2.2 V, 3 V 1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V, fADC10CLK = 5 MHZ, ADC10SHTX = 0x1000, Conversion rate = 20 ksps 2.2 V, 3 V (5) µA –1 1 10 µF The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance (CI) is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements. Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external reference source if it is used for the ADC10_A. See also the MSP430F5xx and MSP430F6xx Family User's Guide. Specifications Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 5.45 REF, Built-In Reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER Positive built-in reference voltage VREF+ AVCC minimum voltage, Positive built-in reference active AVCC(min) Operating supply current into AVCC terminal (2) IREF+ TEST CONDITIONS VCC MIN TYP MAX REFVSEL = {2} for 2.5 V, REFON = 1 3V 2.472 2.51 2.548 REFVSEL = {1} for 2.0 V, REFON = 1 3V 1.96 1.99 2.02 REFVSEL = {0} for 1.5 V, REFON = 1 2.2 V, 3 V 1.472 1.495 1.518 REFVSEL = {0} for 1.5 V 1.8 REFVSEL = {1} for 2.0 V 2.2 REFVSEL = {2} for 2.5 V 2.7 UNIT V V fADC10CLK = 5.0 MHz, REFON = 1, REFBURST = 0, REFVSEL = {2} for 2.5 V 3V 18 24 fADC10CLK = 5.0 MHz, REFON = 1, REFBURST = 0, REFVSEL = {1} for 2.0 V 3V 15.5 21 fADC10CLK = 5.0 MHz, REFON = 1, REFBURST = 0, REFVSEL = {0} for 1.5 V 3V 13.5 21 30 50 µA TCREF+ Temperature coefficient of built-in reference (3) IVREF+ = 0 A, REFVSEL = (0, 1, 2}, REFON = 1 ISENSOR Operating supply current into AVCC terminal (4) REFON = 0, INCH = 0Ah, ADC10ON = N A, TA = 30°C 2.2 V 20 22 3V 20 22 VSENSOR See ADC10ON = 1, INCH = 0Ah, TA = 30°C 2.2 V 770 3V 770 VMID AVCC divider at channel 11 ADC10ON = 1, INCH = 0Bh, VMID ≈ 0.5 × VAVCC 2.2 V 1.06 1.1 1.14 3V 1.46 1.5 1.54 tSENSOR(sample) Sample time required if channel 10 is selected (6) ADC10ON = 1, INCH = 0Ah, Error of conversion result ≤ 1 LSB 30 µs tVMID(sample) Sample time required if channel 11 is selected (7) ADC10ON = 1, INCH = 0Bh, Error of conversion result ≤ 1 LSB 1 µs PSRR_DC Power supply rejection ratio (DC) AVCC = AVCC (min) to AVCC(max), TA = 25°C, REFVSEL = {0, 1, 2}, REFON = 1 120 µV/V PSRR_AC Power supply rejection ratio (AC) AVCC = AVCC (min) to AVCC(max), TA = 25°C, f = 1 kHz, ΔVpp = 100 mV REFVSEL = {0, 1, 2}, REFON = 1 6.4 mV/V tSETTLE Settling time of reference voltage (8) AVCC = AVCC (min) to AVCC(max) REFVSEL = {0, 1, 2}, REFON = 0 → 1 75 µs (1) (2) (3) (4) (5) (6) (7) (8) (5) ppm/ °C µA mV V The leakage current is defined in the leakage current table with P6.x/Ax parameter. The internal reference current is supplied from terminal AVCC. Consumption is independent of the ADC10ON control bit, unless a conversion is active. The REFON bit enables to settle the built-in reference before starting an analog-to-digital conversion. Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C – (–40°C)). The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is high). When REFON = 1, ISENSOR is already included in IREF+. The temperature sensor offset can be significant. TI recommends a single-point calibration to minimize the offset error of the built-in temperature sensor. The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on). The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed. The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. Specifications Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 49 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 5.46 Comparator_B over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC TEST CONDITIONS VCC Supply voltage MIN TYP 1.8 MAX 3.6 1.8 V CBPWRMD = 00, CBON = 1, CBRSx = 00 IAVCC_COMP VREF Comparator operating supply current into AVCC, excludes reference resistor ladder Reference voltage level IAVCC_REF VIC Quiescent current of resistor ladder into AVCC, including REF module current VOFFSET Input offset voltage CIN Input capacitance RSIN Series input resistance 31 38 3V 32 39 CBPWRMD = 01, CBON = 1, CBRSx = 00 2.2 V, 3V 10 17 CBPWRMD = 10, CBON = 1, CBRSx = 00 2.2 V, 3V 0.2 0.85 CBREFLx = 01, CBREFACC = 0 ≥ 1.8 V 1.44 ±2.5% CBREFLx = 10, CBREFACC = 0 ≥ 2.2 V 1.92 ±2.5% CBREFLx = 11, CBREFACC = 0 ≥ 3.0 V 2.39 ±2.5% CBREFACC = 1, CBREFLx = 01, CBRSx = 10, REFON = 0, CBON = 0 2.2 V, 3V 17 22 CBREFACC = 0, CBREFLx = 01, CBRSx = 10, REFON = 0, CBON = 0 2.2 V, 3V 33 40 tPD Propagation delay, response time Propagation delay with filter active tPD,filter tEN_CMP Comparator enable time µA 0 VCC – 1 –20 20 CBPWRMD = 01 or 10 –10 10 5 On (switch closed) Resistor reference enable time TCCB_REF Temperature coefficient reference of VCB_REF VCB_REF Reference voltage for a given tap 50 Specifications 4 50 mV kΩ MΩ CBPWRMD = 00, CBF = 0 450 CBPWRMD = 01, CBF = 0 600 CBPWRMD = 10, CBF = 0 50 CBPWRMD = 00, CBON = 1, CBF = 1, CBFDLY = 00 0.35 0.6 1.5 CBPWRMD = 00, CBON = 1, CBF = 1, CBFDLY = 01 0.6 1.0 1.8 CBPWRMD = 00, CBON = 1, CBF = 1, CBFDLY = 10 1.0 1.8 3.4 CBPWRMD = 00, CBON = 1, CBF = 1, CBFDLY = 11 1.8 3.4 6.5 1 2 ns µs µs CBON = 0 → 1, CBPWRMD = 00 or 01 µs 100 CBON = 0 → 1 VIN = reference into resistor ladder, n = 0 to 31 V pF 3 CBON = 0 → 1, CBPWRMD = 10 tEN_REF V µA CBPWRMD = 00 Off (switch open) V 38 2.2 V Common mode input range UNIT 1.0 VIN × (n + 0.5) / 32 VIN × (n + 1) / 32 1.5 µs 50 ppm/ °C VIN × (n + 1.5) / 32 V Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 5.47 Flash Memory over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TJ DVCC(PGM/ERASE) Program and erase supply voltage MIN TYP 1.8 MAX 3.6 UNIT V IPGM Average supply current from DVCC during program 3 5 mA IERASE Average supply current from DVCC during erase 6 11 mA IMERASE, IBANK Average supply current from DVCC during mass erase or bank erase 6 11 mA tCPT Cumulative program time (1) 16 104 Program and erase endurance tRetention Data retention duration tWord ms cycles 100 years 64 85 µs 0 Block program time for first byte or word (2) 49 65 µs tBlock, 1–(N–1) Block program time for each additional byte or word, except for last byte or word (2) 37 49 µs tBlock, N Block program time for last byte or word (2) 55 73 µs tErase Erase time for segment, mass erase, and bank erase when available (2) 23 32 ms fMCLK,MGR MCLK frequency in marginal read mode (FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1) 0 1 MHz tBlock, (1) (2) Word or byte program time 25°C (2) 105 The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming methods: individual word or byte write mode and block write mode. These values are hardwired into the state machine of the flash controller. 5.48 JTAG and Spy-Bi-Wire Interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC VIO MIN TYP MAX UNIT fSBW Spy-Bi-Wire input frequency 2.2 V, 3 V 1.62 V to 1.98 V 0 20 MHz tSBW,Low Spy-Bi-Wire low clock pulse duration 2.2 V, 3 V 1.62 V to 1.98 V 0.025 15 µs tSBW, En Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge) (1) 2.2 V, 3 V 1.62 V to 1.98 V 1 µs tSBW,Rst Spy-Bi-Wire return to normal operation time 2.2 V, 3 V 1.62 V to 1.98 V 15 100 µs 2.2 V 1.62 V to 1.98 V 0 5 3V 1.62 V to 1.98 V 0 10 2.2 V, 3 V 1.62 V to 1.98 V 45 fTCK TCK input frequency for 4-wire JTAG Rinternal (1) (2) (2) Internal pulldown resistance on TEST MHz 60 80 kΩ Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the first SBWTCK clock edge. fTCK may be restricted to meet the timing requirements of the module selected. Specifications Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 51 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 5.49 DVIO BSL Entry over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER (1) tSU, BSLEN Setup time BSLEN to RST/NMI tHO, Hold time BSLEN to RST/NMI (2) (1) (2) BSLEN VCC VIO MIN MAX UNIT 2.2 V, 3 V 1.62 V to 1.98 V 100 ns 2.2 V, 3 V 1.62 V to 1.98 V 350 µs AVCC, DVCC, and DVIO stable and within specification. BSLEN must remain logic high long enough for the boot code to detect its level and enter the BSL sequence. After the minimum hold time is achieved, BSLEN is a don't care. BSLEN VIT+ VITtHO,BSLEN VIT+ VITRST/NMI (DVIO domain) t tSU,BSLEN Figure 5-18. DVIO BSL Entry Timing 52 Specifications Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 6 Detailed Description 6.1 CPU (Link to user's guide) The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers (see Figure 6-1). Peripherals are connected to the CPU using data, address, and control buses. Peripherals can be handled with all instructions. The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data. Program Counter PC/R0 Stack Pointer SP/R1 Status Register Constant Generator SR/CG1/R2 CG2/R3 General-Purpose Register R4 General-Purpose Register R5 General-Purpose Register R6 General-Purpose Register R7 General-Purpose Register R8 General-Purpose Register R9 General-Purpose Register R10 General-Purpose Register R11 General-Purpose Register R12 General-Purpose Register R13 General-Purpose Register R14 General-Purpose Register R15 Figure 6-1. CPU Registers Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 53 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 6.2 www.ti.com Operating Modes These MCUs have one active mode and six software selectable low-power modes of operation. An interrupt event can wake up the device from any of the low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. Software can configure the following operating modes: • Active mode (AM) – All clocks are active • Low-power mode 0 (LPM0) – CPU is disabled – ACLK and SMCLK remain active, MCLK is disabled – FLL loop control remains active • Low-power mode 1 (LPM1) – CPU is disabled – FLL loop control is disabled – ACLK and SMCLK remain active, MCLK is disabled • Low-power mode 2 (LPM2) – CPU is disabled – MCLK, FLL loop control, and DCOCLK are disabled – DCO dc-generator remains enabled – ACLK remains active • Low-power mode 3 (LPM3) – CPU is disabled – MCLK, FLL loop control, and DCOCLK are disabled – DCO dc generator is disabled – ACLK remains active • Low-power mode 4 (LPM4) – CPU is disabled – ACLK is disabled – MCLK, FLL loop control, and DCOCLK are disabled – DCO dc generator is disabled – Crystal oscillator is stopped – Complete data retention • Low-power mode 4.5 (LPM4.5) – Internal regulator disabled – No data retention – Wake-up signal from RST/NMI, P1, and P2 54 Detailed Description Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com 6.3 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 Interrupt Vector Addresses The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see Table 6-1). The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 6-1. Interrupt Sources, Flags, and Vectors INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY System Reset Power up External reset Watchdog time-out, password violation Flash memory password violation PMM password violation WDTIFG, KEYV (SYSRSTIV) (1) (2) Reset 0FFFEh 63, highest System NMI PMM Vacant memory access JTAG mailbox SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG, VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, JMBOUTIFG (SYSSNIV) (1) (Non)maskable 0FFFCh 62 User NMI NMI Oscillator fault Flash memory access violation NMIIFG, OFIFG, ACCVIFG, BUSIFG (SYSUNIV) (1) (2) (Non)maskable 0FFFAh 61 COMP_B Comparator B interrupt flags (CBIV) (1) (3) Maskable 0FFF8h 60 TB0 TB0CCR0 CCIFG0 Maskable 0FFF6h 59 TB0 TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6, TB0IFG (TB0IV) (1) (3) Maskable 0FFF4h 58 Watchdog timer interval timer mode WDTIFG Maskable 0FFF2h 57 USCI_A0 receive or transmit UCA0RXIFG, UCA0TXIFG (UCA0IV) (1) (3) Maskable 0FFF0h 56 USCI_B0 receive or transmit UCB0RXIFG, UCB0TXIFG (UCB0IV) (1) (3) Maskable 0FFEEh 55 ADC10_A (3) (4) ADC10IFG0 (1) (3) (4) Maskable 0FFECh 54 TA0 TA0CCR0 CCIFG0 (3) Maskable 0FFEAh 53 TA0 TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4, TA0IFG (TA0IV) (1) (3) Maskable 0FFE8h 52 Reserved Reserved Maskable 0FFE6h 51 DMA DMA0IFG, DMA1IFG, DMA2IFG (DMAIV) (1) (3) Maskable 0FFE4h 50 TA1 TA1CCR0 CCIFG0 (3) Maskable 0FFE2h 49 TA1 TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2, TA1IFG (TA1IV) (1) (3) Maskable 0FFE0h 48 I/O Port P1 (1) (2) (3) P1IFG.0 to P1IFG.7 (P1IV) (1) (3) Maskable 0FFDEh 47 USCI_A1 receive or transmit UCA1RXIFG, UCA1TXIFG (UCA1IV) (1) (3) Maskable 0FFDCh 46 USCI_B1 receive or transmit (1) (3) Maskable 0FFDAh 45 TA2 UCB1RXIFG, UCB1TXIFG (UCB1IV) TA2CCR0 CCIFG0 (3) Maskable 0FFD8h 44 TA2 TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2, TA2IFG (TA2IV) (1) (3) Maskable 0FFD6h 43 I/O port P2 P2IFG.0 to P2IFG.7 (P2IV) (1) (3) Maskable 0FFD4h 42 RTC_A RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG, RT1PSIFG (RTCIV) (1) (3) Maskable 0FFD2h 41 Multiple source flags A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it. Interrupt flags are located in the module. Only on devices with ADC, otherwise reserved Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 55 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com Table 6-1. Interrupt Sources, Flags, and Vectors (continued) (5) INTERRUPT SOURCE INTERRUPT FLAG Reserved Reserved (5) SYSTEM INTERRUPT WORD ADDRESS PRIORITY 0FFD0h 40 ⋮ ⋮ 0FF80h 0, lowest Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain compatibility with other devices, TI recommends reserving these locations. 6.4 Memory Organization Table 6-2 summarizes the memory map. Table 6-2. Memory Organization (1) Memory (flash) Main: interrupt vector MSP430F5227 MSP430F5222 MSP430F5217 MSP430F5212 MSP430F5229 MSP430F5224 MSP430F5219 MSP430F5214 64KB 00FFFFh to 00FF80h 128KB 00FFFFh to 00FF80h Bank D N/A 32KB 0243FFh to 01C400h Bank C N/A 32KB 01C3FFh to 014400h Bank B 32KB 0143FFh to 00C400h 32KB 0143FFh to 00C400h Bank A 32KB 00C3FFh to 004400h 32KB 00C3FFh to 004400h Sector 3 2KB 0043FFh to 003C00h 2KB 0043FFh to 003C00h Sector 2 2KB 003BFFh to 003400h 2KB 003BFFh to 003400h Sector 1 2KB 0033FFh to 002C00h 2KB 0033FFh to 002C00h Sector 0 2KB 002BFFh to 002400h 2KB 002BFFh to 002400h A 128 B 001BFFh to 001B80h 128 B 001BFFh to 001B80h B 128 B 001B7Fh to 001B00h 128 B 001B7Fh to 001B00h C 128 B 001AFFh to 001A80h 128 B 001AFFh to 001A80h D 128 B 001A7Fh to 001A00h 128 B 001A7Fh to 001A00h Info A 128 B 0019FFh to 001980h 128 B 0019FFh to 001980h Info B 128 B 00197Fh to 001900h 128 B 00197Fh to 001900h Info C 128 B 0018FFh to 001880h 128 B 0018FFh to 001880h Info D 128 B 00187Fh to 001800h 128 B 00187Fh to 001800h Total Size Main: code memory RAM TI factory memory (ROM) Information memory (flash) (1) 56 N/A = Not available Detailed Description Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 Table 6-2. Memory Organization(1) (continued) MSP430F5227 MSP430F5222 MSP430F5217 MSP430F5212 MSP430F5229 MSP430F5224 MSP430F5219 MSP430F5214 BSL 3 512 B 0017FFh to 001600h 512 B 0017FFh to 001600h BSL 2 512 B 0015FFh to 001400h 512 B 0015FFh to 001400h BSL 1 512 B 0013FFh to 001200h 512 B 0013FFh to 001200h BSL 0 512 B 0011FFh to 001000h 512 B 0011FFh to 001000h 4KB 000FFFh to 0h 4KB 000FFFh to 0h Bootloader (BSL) memory (flash) Peripherals Size Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 57 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 6.5 www.ti.com Bootloader (BSL) The BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the device memory by the BSL is protected by an user-defined password. Because the F522x and F521x have split I/O power domains, it is possible to interface with the BSL from either the DVCC or DVIO supply domains. This is useful when the MSP430 is interfacing to a host on the DVIO supply domain. The BSL interface on the DVIO supply domain (see Table 6-3) uses the USCI_A0 module configured as a UART. The BSL interface on the DVCC supply domain (see Table 6-4) uses a timer-based UART. NOTE Devices from TI come factory programmed with the timer-based UART BSL only. If the USCI-based BSL is preferred, it is also available, but it must be programmed by the user. When using the DVIO supply domain for the BSL, entry to the BSL requires a specific sequence on the RST/NMI and BSLEN pins. Table 6-3 shows the required pins and their functions. For further details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide. For a complete description of the features of the BSL and its implementation, see the MSP430 Flash Device Bootloader (BSL) User's Guide. The BSL on the DVIO supply domain uses the USCI_A0 module configured as a UART. NOTE To invoke the BSL from the DVIO domain, the RST/NMI and BSLEN pins must be used for the entry sequence (see Section 5.49). It is critical not to confuse the RST/NMI pin with the RSTDVCC/SBWTDIO pin. In other MSP430 devices, SBWTDIO is shared with the RST/NMI pin and RSTDVCC does not exist. Additional information can be found in Designing With MSP430F522x and MSP430F521x Devices. Table 6-3. DVIO BSL Pin Requirements and Functions DEVICE SIGNAL BSL FUNCTION RST/NMI External reset BSLEN Enable BSL P3.3 Data transmit P3.4 Data receive DVCC, AVCC Device power supply DVIO I/O power supply DVSS Ground supply For applications in which it is desirable to have BSL communication based on the DVCC supply domain, entry to the BSL requires a specific sequence on the RSTDVCC/SBWTDIO and TEST/SBWTCK pins. Table 6-4 shows the required pins and their function. NOTE To invoke the BSL from the DVCC domain, the RSTDVCC/SBWTDIO and TEST/SBWTCK pins must be used for the entry sequence. It is critical not to confuse the RST/NMI pin with the RSTDVCC/SBWTDIO pin. In other MSP430 devices, SBWTDIO is shared with the RST/NMI pin and RSTDVCC does not exist. Additional information can be found in Designing With MSP430F522x and MSP430F521x Devices. 58 Detailed Description Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 Table 6-4. DVCC BSL Pin Requirements and Functions 6.6 6.6.1 DEVICE SIGNAL BSL FUNCTION RSTDVCC/SBWTDIO External reset TEST/SBWTCK Enable BSL P1.1 Data transmit P1.2 Data receive DVCC, AVCC Device power supply DVIO I/O power supply DVSS Ground supply JTAG Operation JTAG Standard Interface The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the JTAG signals. In addition to these signals, the RSTDVCC/SBWTDIO is required to interface with MSP430 development tools and device programmers. The JTAG pin requirements are shown in Table 6-5. For further details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide. For a complete description of the features of the JTAG interface and its implementation, see MSP430 Programming With the JTAG Interface. Additional information can be found in Designing With MSP430F522x and MSP430F521x Devices. NOTE All JTAG I/O pins are supplied by DVCC. NOTE On other MSP430 devices, the RST/NMI pin has been used for SBWTDIO, so care must be taken not to mistakenly use the incorrect pin. On the F522x and F521x series of devices, RSTDVCC is used for SBWTDIO as shown in Table 6-5. Additional information can be found in Designing With MSP430F522x and MSP430F521x Devices. Table 6-5. JTAG Pin Requirements and Functions DEVICE SIGNAL DIRECTION FUNCTION PJ.3/TCK IN JTAG clock input PJ.2/TMS IN JTAG state control PJ.1/TDI/TCLK IN JTAG data input, TCLK input PJ.0/TDO OUT JTAG data output TEST/SBWTCK IN Enable JTAG pins RSTDVCC/SBWTDIO IN External reset DVCC, AVCC Device power supply DVIO I/O power supply DVSS Ground supply Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 59 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 6.6.2 www.ti.com Spy-Bi-Wire Interface In addition to the standard JTAG interface, the MSP430 family supports the 2-wire Spy-Bi-Wire interface. Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. The SpyBi-Wire interface pin requirements are shown in Table 6-6. For further details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide. For a complete description of the features of the JTAG interface and its implementation, see MSP430 Programming With the JTAG Interface.Additional information can be found in Designing With MSP430F522x and MSP430F521x Devices. NOTE All SBW I/O pins are supplied by DVCC. NOTE On other MSP430 devices, the RST/NMI pin has been used for SBWTDIO, so care must be taken not to mistakenly use the incorrect pin. On the F522x and F521x series of devices, RSTDVCC is used for SBWTDIO as shown in Table 6-6. Additional information can be found in Designing With MSP430F522x and MSP430F521x Devices. Table 6-6. Spy-Bi-Wire Pin Requirements and Functions DEVICE SIGNAL 6.7 DIRECTION FUNCTION TEST/SBWTCK IN Spy-Bi-Wire clock input RSTDVCC/SBWTDIO IN, OUT Spy-Bi-Wire data input/output DVCC, AVCC Device power supply DVIO I/O power supply DVSS Ground supply Flash Memory (Link to user's guide) The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the flash memory include: • Flash memory has n segments of main memory and four segments of information memory (A to D) of 128 bytes each. Each segment in main memory is 512 bytes in size. • Segments 0 to n may be erased in one step, or each segment may be individually erased. • Segments A to D can be erased individually. Segments A to D are also called information memory. • Segment A can be locked separately. 6.8 RAM (Link to user's guide) The RAM is made up of n sectors. Each sector can be completely powered down to reduce leakage; however, all data is lost during power down. Features of the RAM include: • RAM has n sectors. The sizes of the sectors can be found in Section 6.4. • Each sector 0 to n can be complete disabled; however, all data in a sector is lost when it is disabled. • Each sector 0 to n automatically enters low-power retention mode when possible. 60 Detailed Description Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com 6.9 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 Peripherals Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be managed using all instructions. For complete module descriptions, see the MSP430F5xx and MSP430F6xx Family User's Guide. 6.9.1 Digital I/O (Link to user's guide) • • • • • All individual I/O bits are independently programmable. Any combination of input, output, and interrupt conditions is possible. Pullup or pulldown on all ports is programmable. Drive strength on all ports is programmable. Edge-selectable interrupt and LPM4.5 wakeup input capability is available for all bits of ports P1 and P2. Read and write access to port-control registers is supported by all instructions. Ports can be accessed byte-wise or word-wise in pairs. • • 6.9.2 Port Mapping Controller (Link to user's guide) The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P4. Table 6-7 lists the valid settings. Table 6-7. Port Mapping Mnemonics and Functions VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION 0 PM_NONE None DVSS PM_CBOUT0 – COMP_B output PM_TB0CLK TB0 clock input – PM_ADC10CLK – ADC10CLK 1 2 PM_DMAE0 DMAE0 input – PM_SVMOUT – SVM output PM_TB0OUTH TB0 high-impedance input TB0OUTH – 4 PM_TB0CCR0A TB0 CCR0 capture input CCI0A TB0 CCR0 compare output Out0 5 PM_TB0CCR1A TB0 CCR1 capture input CCI1A TB0 CCR1 compare output Out1 6 PM_TB0CCR2A TB0 CCR2 capture input CCI2A TB0 CCR2 compare output Out2 7 PM_TB0CCR3A TB0 CCR3 capture input CCI3A TB0 CCR3 compare output Out3 8 PM_TB0CCR4A TB0 CCR4 capture input CCI4A TB0 CCR4 compare output Out4 9 PM_TB0CCR5A TB0 CCR5 capture input CCI5A TB0 CCR5 compare output Out5 10 PM_TB0CCR6A TB0 CCR6 capture input CCI6A TB0 CCR6 compare output Out6 3 11 12 13 14 15 16 PM_UCA1RXD USCI_A1 UART RXD (direction controlled by USCI – input) PM_UCA1SOMI USCI_A1 SPI slave out master in (direction controlled by USCI) PM_UCA1TXD USCI_A1 UART TXD (direction controlled by USCI – output) PM_UCA1SIMO USCI_A1 SPI slave in master out (direction controlled by USCI) PM_UCA1CLK USCI_A1 clock input/output (direction controlled by USCI) PM_UCB1STE USCI_B1 SPI slave transmit enable (direction controlled by USCI) PM_UCB1SOMI USCI_B1 SPI slave out master in (direction controlled by USCI) PM_UCB1SCL USCI_B1 I2C clock (open drain and direction controlled by USCI) PM_UCB1SIMO USCI_B1 SPI slave in master out (direction controlled by USCI) PM_UCB1SDA USCI_B1 I2C data (open drain and direction controlled by USCI) PM_UCB1CLK USCI_B1 clock input/output (direction controlled by USCI) PM_UCA1STE USCI_A1 SPI slave transmit enable (direction controlled by USCI) 17 PM_CBOUT1 None COMP_B output 18 PM_MCLK None MCLK Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 61 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com Table 6-7. Port Mapping Mnemonics and Functions (continued) VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION 19 PM_RTCCLK None RTCCLK output 20 21 22 23 24 25 (1) PM_UCA0RXD USCI_A0 UART RXD (direction controlled by USCI - input) PM_UCA0SOMI USCI_A0 SPI slave out master in (direction controlled by USCI) PM_UCA0TXD USCI_A0 UART TXD (direction controlled by USCI - output) PM_UCA0SIMO USCI_A0 SPI slave in master out (direction controlled by USCI) PM_UCA0CLK USCI_A0 clock input/output (direction controlled by USCI) PM_UCB0STE USCI_B0 SPI slave transmit enable (direction controlled by USCI) PM_UCB0SOMI USCI_B0 SPI slave out master in (direction controlled by USCI) PM_UCB0SCL USCI_B0 I2C clock (open drain and direction controlled by USCI) PM_UCB0SIMO USCI_B0 SPI slave in master out (direction controlled by USCI) PM_UCB0SDA USCI_B0 I2C data (open drain and direction controlled by USCI) PM_UCB0CLK USCI_B0 clock input/output (direction controlled by USCI) PM_UCA0STE USCI_A0 SPI slave transmit enable (direction controlled by USCI) 26 - 30 Reserved 31 (0FFh) (1) PM_ANALOG None DVSS Disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are ignored, resulting in a read out value of 31. Table 6-8. Default Mapping PIN PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION P4.0/P4MAP0 PM_UCB1STE/PM_UCA1CLK USCI_B1 SPI slave transmit enable (direction controlled by USCI) USCI_A1 clock input/output (direction controlled by USCI) P4.1/P4MAP1 PM_UCB1SIMO/PM_UCB1SDA USCI_B1 SPI slave in master out (direction controlled by USCI) USCI_B1 I2C data (open drain and direction controlled by USCI) P4.2/P4MAP2 PM_UCB1SOMI/PM_UCB1SCL USCI_B1 SPI slave out master in (direction controlled by USCI) USCI_B1 I2C clock (open drain and direction controlled by USCI) P4.3/P4MAP3 PM_UCB1CLK/PM_UCA1STE USCI_A1 SPI slave transmit enable (direction controlled by USCI) USCI_B1 clock input/output (direction controlled by USCI) P4.4/P4MAP4 PM_UCA1TXD/PM_UCA1SIMO USCI_A1 UART TXD (Direction controlled by USCI - output) USCI_A1 SPI slave in master out (direction controlled by USCI) P4.5/P4MAP5 PM_UCA1RXD/PM_UCA1SOMI USCI_A1 UART RXD (Direction controlled by USCI - input) USCI_A1 SPI slave out master in (direction controlled by USCI) P4.6/P4MAP6 PM_NONE None DVSS PM_NONE None DVSS P4.7/P4MAP7 (1) (1) Not available on all devices 62 Detailed Description Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com 6.9.3 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 Oscillator and System Clock (Link to user's guide) The clock system in the MSP430F522x and MSP430F521x family of devices is supported by the Unified Clock System (UCS) module, which includes support for a 32-kHz watch crystal oscillator (XT1 LF mode) (XT1 HF mode is not supported), an internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), an integrated internal digitally controlled oscillator (DCO), and a high-frequency crystal oscillator (XT2). The UCS module is designed to meet the requirements of both low system cost and low power consumption. The UCS module features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the selected FLL reference frequency. The internal DCO provides a fast turnon clock source and stabilizes in 3.5 µs (typical). The UCS module provides the following clock signals: • Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (XT1), a high-frequency crystal (XT2), the internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal digitally controlled oscillator DCO. • Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made available to ACLK. • Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by same sources made available to ACLK. • ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32. 6.9.4 Power-Management Module (PMM) (Link to user's guide) The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor (SVS) and supply voltage monitoring (SVM) circuitry, and brownout protection. The brownout circuit is implemented to provide the proper internal reset signal to the device during power-on and power-off. The SVS and SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not automatically reset). SVS and SVM circuitry is available on the primary supply and core supply. 6.9.5 Hardware Multiplier (Link to user's guide) The multiplication operation is supported by a dedicated peripheral module. The module performs operations with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication as well as signed and unsigned multiply-and-accumulate operations. 6.9.6 Real-Time Clock (RTC_A) (Link to user's guide) The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated real-time clock (RTC) (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit timers that can be cascaded to form a 16-bit timer or counter. Both timers can be read and written by software. Calendar mode integrates an internal calendar that compensates for months with less than 31 days and includes leap year correction. The RTC_A also supports flexible alarm functions and offsetcalibration hardware. 6.9.7 Watchdog Timer (WDT_A) (Link to user's guide) The primary function of the WDT_A module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 63 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 6.9.8 www.ti.com System Module (SYS) (Link to user's guide) The SYS module handles many of the system functions within the device. These include power-on reset (POR) and power-up clear (PUC) handling, NMI source selection and management, reset interrupt vector generators, bootloader (BSL) entry mechanisms, and configuration management (device descriptors). It also includes a data exchange mechanism when using JTAG that is called a JTAG mailbox and that can be used in the application. Table 6-9 lists the SYS module interrupt vector registers. Table 6-9. System Module Interrupt Vector Registers INTERRUPT VECTOR REGISTER SYSRSTIV, System Reset SYSSNIV, System NMI SYSUNIV, User NMI 64 Detailed Description ADDRESS 019Eh 019Ch 019Ah INTERRUPT EVENT VALUE No interrupt pending 00h Brownout (BOR) 02h RST/NMI (BOR) 04h PMMSWBOR (BOR) 06h Wakeup from LPMx.5 08h Security violation (BOR) 0Ah SVSL (POR) 0Ch SVSH (POR) 0Eh SVML_OVP (POR) 10h SVMH_OVP (POR) 12h PMMSWPOR (POR) 14h WDT time-out (PUC) 16h WDT password violation (PUC) 18h KEYV flash password violation (PUC) 1Ah Reserved 1Ch Peripheral area fetch (PUC) 1Eh PMM password violation (PUC) 20h Reserved 22h to 3Eh No interrupt pending 00h SVMLIFG 02h SVMHIFG 04h SVSMLDLYIFG 06h SVSMHDLYIFG 08h VMAIFG 0Ah JMBINIFG 0Ch JMBOUTIFG 0Eh SVMLVLRIFG 10h SVMHVLRIFG 12h Reserved 14h to 1Eh No interrupt pending 00h NMIIFG 02h OFIFG 04h ACCVIFG 06h Reserved 08h Reserved 0Ah to 1Eh PRIORITY Highest Lowest Highest Lowest Highest Lowest Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com 6.9.9 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 DMA Controller (Link to user's guide) The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC10_A conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or from a peripheral. Table 6-10 lists the trigger assignments. Table 6-10. DMA Trigger Assignments (1) TRIGGER (1) (2) CHANNEL 0 1 2 0 DMAREQ DMAREQ DMAREQ 1 TA0CCR0 CCIFG TA0CCR0 CCIFG TA0CCR0 CCIFG 2 TA0CCR2 CCIFG TA0CCR2 CCIFG TA0CCR2 CCIFG 3 TA1CCR0 CCIFG TA1CCR0 CCIFG TA1CCR0 CCIFG 4 TA1CCR2 CCIFG TA1CCR2 CCIFG TA1CCR2 CCIFG 5 TA2CCR0 CCIFG TA2CCR0 CCIFG TA2CCR0 CCIFG 6 TA2CCR2 CCIFG TA2CCR2 CCIFG TA2CCR2 CCIFG 7 TB0CCR0 CCIFG TB0CCR0 CCIFG TB0CCR0 CCIFG 8 TB0CCR2 CCIFG TB0CCR2 CCIFG TB0CCR2 CCIFG 9 Reserved Reserved Reserved 10 Reserved Reserved Reserved 11 Reserved Reserved Reserved 12 Reserved Reserved Reserved 13 Reserved Reserved Reserved 14 Reserved Reserved Reserved 15 Reserved Reserved Reserved 16 UCA0RXIFG UCA0RXIFG UCA0RXIFG 17 UCA0TXIFG UCA0TXIFG UCA0TXIFG 18 UCB0RXIFG UCB0RXIFG UCB0RXIFG 19 UCB0TXIFG UCB0TXIFG UCB0TXIFG 20 UCA1RXIFG UCA1RXIFG UCA1RXIFG 21 UCA1TXIFG UCA1TXIFG UCA1TXIFG 22 UCB1RXIFG UCB1RXIFG UCB1RXIFG 23 UCB1TXIFG UCB1TXIFG UCB1TXIFG (2) ADC10IFG0 (2) ADC10IFG0 (2) 24 ADC10IFG0 25 Reserved Reserved Reserved 26 Reserved Reserved Reserved 27 Reserved Reserved Reserved 28 Reserved Reserved Reserved 29 MPY ready MPY ready MPY ready 30 DMA2IFG DMA0IFG DMA1IFG 31 DMAE0 DMAE0 DMAE0 If a reserved trigger source is selected, no trigger is generated. Only on devices with ADC; reserved on devices without ADC Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 65 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 6.9.10 Universal Serial Communication Interface (USCI) (Links to user's guide: UART Mode, SPI Mode, I2C Mode) The USCI modules are used for serial data communication. The USCI module supports synchronous communication protocols such as SPI (3- or 4-pin) and I2C, and asynchronous communication protocols such as UART, enhanced UART with automatic baudrate detection, and IrDA. Each USCI module contains two portions, A and B. The USCI_An module provides support for SPI (3- or 4-pin), UART, enhanced UART, or IrDA. The USCI_Bn module provides support for SPI (3- or 4-pin) or I2C. The MSP430F522x and MSP430F521x series include two complete USCI modules (n = 0, 1). 66 Detailed Description Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 6.9.11 TA0 (Link to user's guide) TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. TA0 can support multiple captures or compares, PWM outputs, and interval timing (see Table 6-11). TA0 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 6-11. TA0 Signal Connections INPUT PIN NUMBER RGC, ZQE, YFF 18, H2, B7P1.0 RGZ DEVICE INPUT SIGNAL MODULE INPUT SIGNAL 13-P1.0 TA0CLK TACLK ACLK (internal) ACLK SMCLK (internal) SMCLK 18, H2, B7P1.0 13-P1.0 TA0CLK TACLK 19, H3, C7P1.1 14-P1.1 TA0.0 CCI0A DVSS CCI0B DVSS GND DVCC VCC TA0.1 CCI1A CBOUT (internal) CCI1B 20, J3, C8P1.2 21, G4, C6P1.3 22, H4, C5P1.4 23, J4, D8P1.5 15-P1.2 16-P1.3 17-P1.4 18-P1.5 DVSS GND DVCC VCC TA0.2 CCI2A ACLK (internal) CCI2B DVSS GND DVCC VCC TA0.3 CCI3A DVSS CCI3B DVSS GND DVCC VCC TA0.4 CCI4A DVSS CCI4B DVSS GND DVCC VCC MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL Timer NA NA CCR0 CCR1 CCR2 CCR3 CCR4 TA0 TA1 TA2 TA3 TA4 OUTPUT PIN NUMBER RGC, ZQE, YFF RGZ 19, H3, C7-P1.1 14-P1.1 20, J3, C8-P1.2 15-P1.2 ADC10 (internal) ADC10SHSx = {1} ADC10 (internal) ADC10SHSx = {1} 21, G4, C6-P1.3 16-P1.3 22, H4, C5-P1.4 17-P1.4 23, J4, D8-P1.5 18-P1.5 TA0.0 TA0.1 TA0.2 TA0.3 TA0.4 Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 67 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 6.9.12 TA1 (Link to user's guide) TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA1 can support multiple captures or compares, PWM outputs, and interval timing (see Table 6-12). TA1 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 6-12. TA1 Signal Connections INPUT PIN NUMBER RGC, ZQE, YFF 24, G5, D7P1.6 RGZ DEVICE INPUT SIGNAL MODULE INPUT SIGNAL 19-P1.6 TA1CLK TACLK ACLK (internal) ACLK SMCLK (internal) SMCLK 24, G5, D7P1.6 19-P1.6 TA1CLK TACLK 25, H5, D6P1.7 20-P1.7 TA1.0 CCI0A DVSS CCI0B DVSS GND DVCC VCC TA1.1 CCI1A CBOUT (internal) CCI1B DVSS GND DVCC VCC TA1.2 CCI2A ACLK (internal) CCI2B DVSS GND DVCC VCC 26, J5, E8P2.0 27, G6, D5P2.1 68 Detailed Description MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL Timer NA NA CCR0 TA0 OUTPUT PIN NUMBER RGC, ZQE, YFF RGZ 25, H5, D6P1.7 20-P1.7 TA1.0 26, J5, E8P2.0 CCR1 TA1 TA1.1 27, G6, D5P2.1 CCR2 TA2 TA1.2 Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 6.9.13 TA2 (Link to user's guide) TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA2 can support multiple captures or compares, PWM outputs, and interval timing (see Table 6-13). TA2 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 6-13. TA2 Signal Connections INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT SIGNAL TA2CLK TACLK ACLK (internal) ACLK SMCLK (internal) SMCLK 28, J6, E7P2.2 TA2CLK TACLK 29, H6, F8P2.3 TA2.0 CCI0A DVSS CCI0B DVSS GND DVCC VCC TA2.1 CCI1A CBOUT (internal) CCI1B DVSS GND DVCC VCC TA2.2 CCI2A ACLK (internal) CCI2B DVSS GND DVCC VCC RGC, ZQE, YFF 28, J6, E7P2.2 30, J7, E6P2.4 31, J8, F7P2.5 RGZ MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL Timer NA NA OUTPUT PIN NUMBER RGC, ZQE, YFF RGZ 29, H6, F8P2.3 CCR0 TA0 TA2.0 30, J7, E6P2.4 CCR1 TA1 TA2.1 31, J8, F7P2.5 CCR2 TA2 TA2.2 Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 69 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 6.9.14 TB0 (Link to user's guide) TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. TB0 can support multiple captures or compares, PWM outputs, and interval timing (see Table 6-14). TB0 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 6-14. TB0 Signal Connections INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT SIGNAL TB0CLK TBCLK ACLK (internal) ACLK SMCLK (internal) SMCLK (1) TB0CLK TBCLK 49, B8(9), H1P7.0 (1) (1) TB0.0 CCI0A 49, B8(9), H1P7.0 (1) (1) TB0.0 CCI0B RGC, ZQE, YFF (1) (1) (1) 50, A9, G2P7.1 (1) (1) DVSS GND DVCC VCC TB0.1 CCI1A CBOUT (internal) CCI1B DVSS GND DVCC VCC 51, B7, F3P7.2 (1) (1) TB0.2 CCI2A 51, B7, F3P7.2 (1) (1) TB0.2 CCI2B DVSS GND DVCC VCC 52, A8, G1P7.3 (1) (1) TB0.3 CCI3A 52, A8, G1P7.3 (1) (1) TB0.3 CCI3B (1) DVSS GND DVCC VCC 53, A7, F2P7.4 (1) (1) TB0.4 CCI4A 53, A7, F2P7.4 (1) (1) TB0.4 CCI4B DVSS GND DVCC VCC 54, A6, F1P7.5 (1) (1) TB0.5 CCI5A 54, A6, F1P7.5 (1) (1) TB0.5 CCI5B DVSS GND (1) 70 RGZ (1) DVCC VCC TB0.6 CCI6A ACLK (internal) CCI6B DVSS GND DVCC VCC MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL Timer NA NA CCR0 CCR1 CCR2 CCR3 CCR4 CCR5 CCR6 TB0 TB1 TB2 TB3 TB4 TB5 TB6 TB0.0 TB0.1 OUTPUT PIN NUMBER RGC, ZQE, YFF RGZ 49, B8(9), H1P7.0 (1) (1) ADC10 (internal) ADC10SHSx = {2} ADC10 (internal) ADC10SHSx = {2} 50, A9, G2-P7.1 (1) (1) ADC10 (internal) ADC10SHSx = {3} ADC10 (internal) ADC10SHSx = {3} 51, B7, F3-P7.2 (1) (1) 52, A8, G1-P7.3 (1) (1) 53, A7, F2-P7.4 (1) (1) 54, A6, F1-P7.5 (1) (1) (1) (1) TB0.2 TB0.3 TB0.4 TB0.5 TB0.6 Timer functions can be assigned by the port mapping controller. Detailed Description Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 6.9.15 Comparator_B (Link to user's guide) The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions, battery voltage supervision, and monitoring of external analog signals. 6.9.16 ADC10_A (Link to user's guide) The ADC10_A module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core, sample select control, reference generator, and a conversion result buffer. A window comparator with lower and upper limits allows CPU-independent result monitoring with three window comparator interrupt flags. 6.9.17 CRC16 (Link to user's guide) The CRC16 module produces a signature based on a sequence of entered data values and can be used for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard. 6.9.18 REF Voltage Reference (Link to user's guide) The REF is responsible for generation of all critical reference voltages that can be used by the various analog peripherals in the device. 6.9.19 Embedded Emulation Module (EEM) (S Version) (Link to user's guide) The EEM supports real-time in-system debugging. The S version of the EEM has the following features: • Three hardware triggers or breakpoints on memory access • One hardware trigger or breakpoint on CPU register write access • Up to four hardware triggers can be combined to form complex triggers or breakpoints • One cycle counter • Clock control on module level Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 71 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 6.9.20 Peripheral File Map Table 6-15 lists the base address for the registers of each peripheral. Table 6-15. Peripherals 72 MODULE NAME BASE ADDRESS OFFSET ADDRESS RANGE Special Functions (see Table 6-16) 0100h 000h-01Fh PMM (see Table 6-17) 0120h 000h-010h Flash Control (see Table 6-18) 0140h 000h-00Fh CRC16 (see Table 6-19) 0150h 000h-007h RAM Control (see Table 6-20) 0158h 000h-001h Watchdog (see Table 6-21) 015Ch 000h-001h UCS (see Table 6-22) 0160h 000h-01Fh SYS (see Table 6-23) 0180h 000h-01Fh Shared Reference (see Table 6-24) 01B0h 000h-001h Port Mapping Control (see Table 6-25) 01C0h 000h-002h Port Mapping Port P4 (see Table 6-25) 01E0h 000h-007h Port P1, P2 (see Table 6-26) 0200h 000h-01Fh Port P3, P4 (see Table 6-27) 0220h 000h-00Bh Port P5, P6 (see Table 6-28) 0240h 000h-00Bh Port P7 (see Table 6-29) 0260h 000h-00Bh Port PJ (see Table 6-30) 0320h 000h-01Fh TA0 (see Table 6-31) 0340h 000h-02Eh TA1 (see Table 6-32) 0380h 000h-02Eh TB0 (see Table 6-33) 03C0h 000h-02Eh TA2 (see Table 6-34) 0400h 000h-02Eh Real-Time Clock (RTC_A) (see Table 6-35) 04A0h 000h-01Bh 32-Bit Hardware Multiplier (see Table 6-36) 04C0h 000h-02Fh DMA General Control (see Table 6-37) 0500h 000h-00Fh DMA Channel 0 (see Table 6-37) 0510h 000h-00Ah DMA Channel 1 (see Table 6-37) 0520h 000h-00Ah DMA Channel 2 (see Table 6-37) 0530h 000h-00Ah USCI_A0 (see Table 6-38) 05C0h 000h-01Fh USCI_B0 (see Table 6-39) 05E0h 000h-01Fh USCI_A1 (see Table 6-40) 0600h 000h-01Fh USCI_B1 (see Table 6-41) 0620h 000h-01Fh ADC10_A (see Table 6-42) 0740h 000h-01Fh Comparator_B (see Table 6-43) 08C0h 000h-00Fh Detailed Description Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 Table 6-16. Special Function Registers (Base Address: 0100h) REGISTER DESCRIPTION REGISTER OFFSET SFR interrupt enable SFRIE1 00h SFR interrupt flag SFRIFG1 02h SFR reset pin control SFRRPCR 04h Table 6-17. PMM Registers (Base Address: 0120h) REGISTER DESCRIPTION REGISTER OFFSET PMM control 0 PMMCTL0 00h PMM control 1 PMMCTL1 02h SVS high-side control SVSMHCTL 04h SVS low-side control SVSMLCTL 06h PMM interrupt flags PMMIFG 0Ch PMM interrupt enable PMMIE 0Eh PMM power mode 5 control PM5CTL0 10h Table 6-18. Flash Control Registers (Base Address: 0140h) REGISTER DESCRIPTION REGISTER OFFSET Flash control 1 FCTL1 00h Flash control 3 FCTL3 04h Flash control 4 FCTL4 06h Table 6-19. CRC16 Registers (Base Address: 0150h) REGISTER DESCRIPTION REGISTER OFFSET CRC data input CRC16DI 00h CRC data input reverse byte CRCDIRB 02h CRC initialization and result CRCINIRES 04h CRC result reverse byte CRCRESR 06h Table 6-20. RAM Control Registers (Base Address: 0158h) REGISTER DESCRIPTION RAM control 0 REGISTER RCCTL0 OFFSET 00h Table 6-21. Watchdog Registers (Base Address: 015Ch) REGISTER DESCRIPTION Watchdog timer control REGISTER WDTCTL OFFSET 00h Table 6-22. UCS Registers (Base Address: 0160h) REGISTER DESCRIPTION REGISTER OFFSET UCS control 0 UCSCTL0 00h UCS control 1 UCSCTL1 02h UCS control 2 UCSCTL2 04h UCS control 3 UCSCTL3 06h UCS control 4 UCSCTL4 08h UCS control 5 UCSCTL5 0Ah UCS control 6 UCSCTL6 0Ch UCS control 7 UCSCTL7 0Eh Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 73 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com Table 6-22. UCS Registers (Base Address: 0160h) (continued) REGISTER DESCRIPTION REGISTER OFFSET UCS control 8 UCSCTL8 10h UCS control 9 UCSCTL9 12h Table 6-23. SYS Registers (Base Address: 0180h) REGISTER DESCRIPTION REGISTER OFFSET System control SYSCTL 00h Bootloader configuration area SYSBSLC 02h JTAG mailbox control SYSJMBC 06h JTAG mailbox input 0 SYSJMBI0 08h JTAG mailbox input 1 SYSJMBI1 0Ah JTAG mailbox output 0 SYSJMBO0 0Ch JTAG mailbox output 1 SYSJMBO1 0Eh User NMI vector generator SYSUNIV 1Ah System NMI vector generator SYSSNIV 1Ch Reset vector generator SYSRSTIV 1Eh Table 6-24. Shared Reference Registers (Base Address: 01B0h) REGISTER DESCRIPTION Shared reference control REGISTER REFCTL OFFSET 00h Table 6-25. Port Mapping Registers (Base Address of Port Mapping Control: 01C0h, Port P4: 01E0h) REGISTER DESCRIPTION REGISTER OFFSET Port mapping key/ID PMAPKEYID 00h Port mapping control PMAPCTL 02h Port P4.0 mapping P4MAP0 00h Port P4.1 mapping P4MAP1 01h Port P4.2 mapping P4MAP2 02h Port P4.3 mapping P4MAP3 03h Port P4.4 mapping P4MAP4 04h Port P4.5 mapping P4MAP5 05h Port P4.6 mapping P4MAP6 06h Port P4.7 mapping P4MAP7 07h Table 6-26. Port P1, P2 Registers (Base Address: 0200h) REGISTER DESCRIPTION REGISTER OFFSET Port P1 input P1IN 00h Port P1 output P1OUT 02h Port P1 direction P1DIR 04h Port P1 resistor enable P1REN 06h Port P1 drive strength P1DS 08h Port P1 selection P1SEL 0Ah Port P1 interrupt vector word P1IV 0Eh Port P1 interrupt edge select P1IES 18h Port P1 interrupt enable P1IE 1Ah Port P1 interrupt flag P1IFG 1Ch 74 Detailed Description Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 Table 6-26. Port P1, P2 Registers (Base Address: 0200h) (continued) REGISTER DESCRIPTION REGISTER OFFSET Port P2 input P2IN 01h Port P2 output P2OUT 03h Port P2 direction P2DIR 05h Port P2 resistor enable P2REN 07h Port P2 drive strength P2DS 09h Port P2 selection P2SEL 0Bh Port P2 interrupt vector word P2IV 1Eh Port P2 interrupt edge select P2IES 19h Port P2 interrupt enable P2IE 1Bh Port P2 interrupt flag P2IFG 1Dh Table 6-27. Port P3, P4 Registers (Base Address: 0220h) REGISTER DESCRIPTION REGISTER OFFSET Port P3 input P3IN 00h Port P3 output P3OUT 02h Port P3 direction P3DIR 04h Port P3 resistor enable P3REN 06h Port P3 drive strength P3DS 08h Port P3 selection P3SEL 0Ah Port P4 input P4IN 01h Port P4 output P4OUT 03h Port P4 direction P4DIR 05h Port P4 resistor enable P4REN 07h Port P4 drive strength P4DS 09h Port P4 selection P4SEL 0Bh Table 6-28. Port P5, P6 Registers (Base Address: 0240h) REGISTER DESCRIPTION REGISTER OFFSET Port P5 input P5IN 00h Port P5 output P5OUT 02h Port P5 direction P5DIR 04h Port P5 resistor enable P5REN 06h Port P5 drive strength P5DS 08h Port P5 selection P5SEL 0Ah Port P6 input P6IN 01h Port P6 output P6OUT 03h Port P6 direction P6DIR 05h Port P6 resistor enable P6REN 07h Port P6 drive strength P6DS 09h Port P6 selection P6SEL 0Bh Table 6-29. Port P7 Registers (Base Address: 0260h) REGISTER DESCRIPTION REGISTER OFFSET Port P7 input P7IN 00h Port P7 output P7OUT 02h Port P7 direction P7DIR 04h Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 75 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com Table 6-29. Port P7 Registers (Base Address: 0260h) (continued) REGISTER DESCRIPTION REGISTER OFFSET Port P7 resistor enable P7REN 06h Port P7 drive strength P7DS 08h Port P7 selection P7SEL 0Ah Table 6-30. Port J Registers (Base Address: 0320h) REGISTER DESCRIPTION REGISTER OFFSET Port PJ input PJIN 00h Port PJ output PJOUT 02h Port PJ direction PJDIR 04h Port PJ resistor enable PJREN 06h Port PJ drive strength PJDS 08h Table 6-31. TA0 Registers (Base Address: 0340h) REGISTER DESCRIPTION REGISTER OFFSET TA0 control TA0CTL 00h Capture/compare control 0 TA0CCTL0 02h Capture/compare control 1 TA0CCTL1 04h Capture/compare control 2 TA0CCTL2 06h Capture/compare control 3 TA0CCTL3 08h Capture/compare control 4 TA0CCTL4 0Ah TA0 counter TA0R 10h Capture/compare 0 TA0CCR0 12h Capture/compare 1 TA0CCR1 14h Capture/compare 2 TA0CCR2 16h Capture/compare 3 TA0CCR3 18h Capture/compare 4 TA0CCR4 1Ah TA0 expansion 0 TA0EX0 20h TA0 interrupt vector TA0IV 2Eh Table 6-32. TA1 Registers (Base Address: 0380h) REGISTER DESCRIPTION REGISTER OFFSET TA1 control TA1CTL 00h Capture/compare control 0 TA1CCTL0 02h Capture/compare control 1 TA1CCTL1 04h Capture/compare control 2 TA1CCTL2 06h TA1 counter TA1R 10h Capture/compare 0 TA1CCR0 12h Capture/compare 1 TA1CCR1 14h Capture/compare 2 TA1CCR2 16h TA1 expansion 0 TA1EX0 20h TA1 interrupt vector TA1IV 2Eh Table 6-33. TB0 Registers (Base Address: 03C0h) REGISTER DESCRIPTION REGISTER OFFSET TB0 control TB0CTL 00h Capture/compare control 0 TB0CCTL0 02h 76 Detailed Description Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 Table 6-33. TB0 Registers (Base Address: 03C0h) (continued) REGISTER DESCRIPTION REGISTER OFFSET Capture/compare control 1 TB0CCTL1 04h Capture/compare control 2 TB0CCTL2 06h Capture/compare control 3 TB0CCTL3 08h Capture/compare control 4 TB0CCTL4 0Ah Capture/compare control 5 TB0CCTL5 0Ch Capture/compare control 6 TB0CCTL6 0Eh TB0 counter TB0R 10h Capture/compare 0 TB0CCR0 12h Capture/compare 1 TB0CCR1 14h Capture/compare 2 TB0CCR2 16h Capture/compare 3 TB0CCR3 18h Capture/compare 4 TB0CCR4 1Ah Capture/compare 5 TB0CCR5 1Ch Capture/compare 6 TB0CCR6 1Eh TB0 expansion 0 TB0EX0 20h TB0 interrupt vector TB0IV 2Eh Table 6-34. TA2 Registers (Base Address: 0400h) REGISTER DESCRIPTION REGISTER OFFSET TA2 control TA2CTL 00h Capture/compare control 0 TA2CCTL0 02h Capture/compare control 1 TA2CCTL1 04h Capture/compare control 2 TA2CCTL2 06h TA2 counter TA2R 10h Capture/compare 0 TA2CCR0 12h Capture/compare 1 TA2CCR1 14h Capture/compare 2 TA2CCR2 16h TA2 expansion 0 TA2EX0 20h TA2 interrupt vector TA2IV 2Eh Table 6-35. Real-Time Clock Registers (Base Address: 04A0h) REGISTER DESCRIPTION REGISTER OFFSET RTC control 0 RTCCTL0 00h RTC control 1 RTCCTL1 01h RTC control 2 RTCCTL2 02h RTC control 3 RTCCTL3 03h RTC prescaler 0 control RTCPS0CTL 08h RTC prescaler 1 control RTCPS1CTL 0Ah RTC prescaler 0 RTCPS0 0Ch RTC prescaler 1 RTCPS1 0Dh RTC interrupt vector word RTCIV 0Eh RTC seconds/counter 1 RTCSEC/RTCNT1 10h RTC minutes/counter 2 RTCMIN/RTCNT2 11h RTC hours/counter 3 RTCHOUR/RTCNT3 12h RTC day of week/counter 4 RTCDOW/RTCNT4 13h RTC days RTCDAY 14h RTC month RTCMON 15h Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 77 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com Table 6-35. Real-Time Clock Registers (Base Address: 04A0h) (continued) REGISTER DESCRIPTION REGISTER OFFSET RTC year low RTCYEARL 16h RTC year high RTCYEARH 17h RTC alarm minutes RTCAMIN 18h RTC alarm hours RTCAHOUR 19h RTC alarm day of week RTCADOW 1Ah RTC alarm days RTCADAY 1Bh Table 6-36. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h) REGISTER DESCRIPTION REGISTER OFFSET 16-bit operand 1 – multiply MPY 00h 16-bit operand 1 – signed multiply MPYS 02h 16-bit operand 1 – multiply accumulate MAC 04h 16-bit operand 1 – signed multiply accumulate MACS 06h 16-bit operand 2 OP2 08h 16 × 16 result low word RESLO 0Ah 16 × 16 result high word RESHI 0Ch 16 × 16 sum extension SUMEXT 0Eh 32-bit operand 1 – multiply low word MPY32L 10h 32-bit operand 1 – multiply high word MPY32H 12h 32-bit operand 1 – signed multiply low word MPYS32L 14h 32-bit operand 1 – signed multiply high word MPYS32H 16h 32-bit operand 1 – multiply accumulate low word MAC32L 18h 32-bit operand 1 – multiply accumulate high word MAC32H 1Ah 32-bit operand 1 – signed multiply accumulate low word MACS32L 1Ch 32-bit operand 1 – signed multiply accumulate high word MACS32H 1Eh 32-bit operand 2 – low word OP2L 20h 32-bit operand 2 – high word OP2H 22h 32 × 32 result 0 – least significant word RES0 24h 32 × 32 result 1 RES1 26h 32 × 32 result 2 RES2 28h 32 × 32 result 3 – most significant word RES3 2Ah MPY32 control 0 MPY32CTL0 2Ch Table 6-37. DMA Registers (Base Address DMA General Control: 0500h, DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h) REGISTER DESCRIPTION REGISTER OFFSET DMA channel 0 control DMA0CTL 00h DMA channel 0 source address low DMA0SAL 02h DMA channel 0 source address high DMA0SAH 04h DMA channel 0 destination address low DMA0DAL 06h DMA channel 0 destination address high DMA0DAH 08h DMA channel 0 transfer size DMA0SZ 0Ah DMA channel 1 control DMA1CTL 00h DMA channel 1 source address low DMA1SAL 02h DMA channel 1 source address high DMA1SAH 04h DMA channel 1 destination address low DMA1DAL 06h DMA channel 1 destination address high DMA1DAH 08h 78 Detailed Description Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 Table 6-37. DMA Registers (Base Address DMA General Control: 0500h, DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h) (continued) REGISTER DESCRIPTION REGISTER OFFSET DMA channel 1 transfer size DMA1SZ 0Ah DMA channel 2 control DMA2CTL 00h DMA channel 2 source address low DMA2SAL 02h DMA channel 2 source address high DMA2SAH 04h DMA channel 2 destination address low DMA2DAL 06h DMA channel 2 destination address high DMA2DAH 08h DMA channel 2 transfer size DMA2SZ 0Ah DMA module control 0 DMACTL0 00h DMA module control 1 DMACTL1 02h DMA module control 2 DMACTL2 04h DMA module control 3 DMACTL3 06h DMA module control 4 DMACTL4 08h DMA interrupt vector DMAIV 0Eh Table 6-38. USCI_A0 Registers (Base Address: 05C0h) REGISTER DESCRIPTION REGISTER OFFSET USCI control 1 UCA0CTL1 00h USCI control 0 UCA0CTL0 01h USCI baud rate 0 UCA0BR0 06h USCI baud rate 1 UCA0BR1 07h USCI modulation control UCA0MCTL 08h USCI status UCA0STAT 0Ah USCI receive buffer UCA0RXBUF 0Ch USCI transmit buffer UCA0TXBUF 0Eh USCI LIN control UCA0ABCTL 10h USCI IrDA transmit control UCA0IRTCTL 12h USCI IrDA receive control UCA0IRRCTL 13h USCI interrupt enable UCA0IE 1Ch USCI interrupt flags UCA0IFG 1Dh USCI interrupt vector word UCA0IV 1Eh Table 6-39. USCI_B0 Registers (Base Address: 05E0h) REGISTER DESCRIPTION REGISTER OFFSET USCI synchronous control 1 UCB0CTL1 00h USCI synchronous control 0 UCB0CTL0 01h USCI synchronous bit rate 0 UCB0BR0 06h USCI synchronous bit rate 1 UCB0BR1 07h USCI synchronous status UCB0STAT 0Ah USCI synchronous receive buffer UCB0RXBUF 0Ch USCI synchronous transmit buffer UCB0TXBUF 0Eh USCI I2C own address UCB0I2COA 10h USCI I2C slave address UCB0I2CSA 12h USCI interrupt enable UCB0IE 1Ch USCI interrupt flags UCB0IFG 1Dh USCI interrupt vector word UCB0IV 1Eh Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 79 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com Table 6-40. USCI_A1 Registers (Base Address: 0600h) REGISTER DESCRIPTION REGISTER OFFSET USCI control 1 UCA1CTL1 00h USCI control 0 UCA1CTL0 01h USCI baud rate 0 UCA1BR0 06h USCI baud rate 1 UCA1BR1 07h USCI modulation control UCA1MCTL 08h USCI status UCA1STAT 0Ah USCI receive buffer UCA1RXBUF 0Ch USCI transmit buffer UCA1TXBUF 0Eh USCI LIN control UCA1ABCTL 10h USCI IrDA transmit control UCA1IRTCTL 12h USCI IrDA receive control UCA1IRRCTL 13h USCI interrupt enable UCA1IE 1Ch USCI interrupt flags UCA1IFG 1Dh USCI interrupt vector word UCA1IV 1Eh Table 6-41. USCI_B1 Registers (Base Address: 0620h) REGISTER DESCRIPTION REGISTER OFFSET USCI synchronous control 1 UCB1CTL1 00h USCI synchronous control 0 UCB1CTL0 01h USCI synchronous bit rate 0 UCB1BR0 06h USCI synchronous bit rate 1 UCB1BR1 07h USCI synchronous status UCB1STAT 0Ah USCI synchronous receive buffer UCB1RXBUF 0Ch USCI synchronous transmit buffer UCB1TXBUF 0Eh USCI I2C own address UCB1I2COA 10h USCI I2C slave address UCB1I2CSA 12h USCI interrupt enable UCB1IE 1Ch USCI interrupt flags UCB1IFG 1Dh USCI interrupt vector word UCB1IV 1Eh Table 6-42. ADC10_A Registers (Base Address: 0740h) REGISTER DESCRIPTION REGISTER OFFSET ADC10_A control 0 ADC10CTL0 00h ADC10_A control 1 ADC10CTL1 02h ADC10_A control 2 ADC10CTL2 04h ADC10_A window comparator low threshold ADC10LO 06h ADC10_A window comparator high threshold ADC10HI 08h ADC10_A memory control 0 ADC10MCTL0 0Ah ADC10_A conversion memory ADC10MEM0 12h ADC10_A interrupt enable ADC10IE 1Ah ADC10_A interrupt flags ADC10IGH 1Ch ADC10_A interrupt vector word ADC10IV 1Eh 80 Detailed Description Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 Table 6-43. Comparator_B Registers (Base Address: 08C0h) REGISTER DESCRIPTION REGISTER OFFSET Comp_B control 0 CBCTL0 00h Comp_B control 1 CBCTL1 02h Comp_B control 2 CBCTL2 04h Comp_B control 3 CBCTL3 06h Comp_B interrupt CBINT 0Ch Comp_B interrupt vector word CBIV 0Eh Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 81 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 6.10 Input/Output Diagrams 6.10.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger Figure 6-2 shows the port diagram. Table 6-44 summarizes the selection of the port function. Pad Logic P1REN.x P1DIR.x 0 From module 1 P1OUT.x 0 From module 1 DVSS 0 (P1.0 to P1.3) DVCC (P1.4 to P1.7) DVIO 1 1 Direction 0: Input 1: Output P1DS.x 0: Low drive 1: High drive P1SEL.x P1IN.x EN To module P1.0/TA0CLK/ACLK P1.1/TA0.0 P1.2/TA0.1 P1.3/TA0.2 P1.4/TA0.3 P1.5/TA0.4 P1.6/TA1CLK/CBOUT P1.7/TA1.0 D P1IE.x EN P1IRQ.x Q P1IFG.x P1SEL.x P1IES.x Set Interrupt Edge Select Figure 6-2. Port P1 (P1.0 to P1.7) Diagram 82 Detailed Description Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 Table 6-44. Port P1 (P1.0 to P1.7) Pin Functions PIN NAME (P1.x) P1.0/TA0CLK/ACLK x 0 FUNCTION P1DIR.x P1SEL.x P1.0 (I/O) I: 0; O: 1 0 TA0CLK 0 1 ACLK P1.1 (I/O) P1.1/TA0.0 1 TA0.CCI0A TA0.0 P1.2 (I/O) P1.2/TA0.1 2 TA0.CCI1A TA0.1 3 4 P1.6/TA1CLK/CBOUT 5 6 7 1 1 1 I: 0; O: 1 0 0 1 0 TA0.CCI2A 0 1 TA0.2 1 1 I: 0; O: 1 0 TA0.CCI3A 0 1 TA0.3 1 1 I: 0; O: 1 0 TA0.CCI4A 0 1 TA0.4 1 1 P1.6 (I/O) I: 0; O: 1 0 TA1CLK 0 1 CBOUT comparator B 1 1 I: 0; O: 1 0 TA1.CCI0A 0 1 TA1.0 1 1 P1.7 (I/O) P1.7/TA1.0 0 0 1 P1.5 (I/O) P1.5/TA0.4 1 1 P1.4 (I/O) P1.4/TA0.3 1 I: 0; O: 1 I: 0; O: 1 P1.3 (I/O) P1.3/TA0.2 CONTROL BITS OR SIGNALS Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 83 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 6.10.2 Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger Figure 6-3 shows the port diagram. Table 6-45 summarizes the selection of the port function. Pad Logic P2REN.x P2DIR.x 0 From module 1 P2OUT.x 0 From module 1 DVSS 0 DVIO 1 1 Direction 0: Input 1: Output P2DS.x 0: Low drive 1: High drive P2SEL.x P2IN.x EN To module P2.0/TA1.1 P2.1/TA1.2 P2.2/TA2CLK/SMCLK P2.3/TA2.0 P2.4/TA2.1 P2.5/TA2.2 P2.6/RTCCLK/DMAE0 P2.7/UB0STE/UCA0CLK D P2IE.x EN To module Q P2IFG.x P2SEL.x P2IES.x Set Interrupt Edge Select Figure 6-3. Port P2 (P2.0 to P2.7) Diagram 84 Detailed Description Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 Table 6-45. Port P2 (P2.0 to P2.7) Pin Functions PIN NAME (P2.x) x FUNCTION P2.0 (I/O) P2.0/TA1.1 (2) 0 TA1.CCI1A TA1.1 P2.1 (I/O) P2.1/TA1.2 (2) 1 TA1.CCI2A TA1.2 P2.2/TA2CLK/SMCLK (2) 2 4 5 P2.7/UCB0STE/UCA0CLK (1) (2) (3) (4) 6 7 1 1 I: 0; O: 1 0 0 1 0 TA2CLK 0 1 1 1 I: 0; O: 1 0 TA2.CCI0A 0 1 TA2.0 1 1 I: 0; O: 1 0 TA2.CCI1A 0 1 TA2.1 1 1 I: 0; O: 1 0 TA2.CCI2A 0 1 TA2.2 1 1 P2.6 (I/O) P2.6/RTCCLK/DMAE0 (2) 1 1 P2.5 (I/O) P2.5/TA2.2 (2) 0 0 1 P2.4 (I/O) P2.4/TA2.1 (2) P2SEL.x I: 0; O: 1 P2.3 (I/O) 3 P2DIR.x I: 0; O: 1 P2.2 (I/O) SMCLK P2.3/TA2.0 (2) CONTROL BITS OR SIGNALS (1) I: 0; O: 1 0 DMAE0 0 1 RTCCLK 1 1 P2.7 (I/O) I: 0; O: 1 0 X 1 UCB0STE/UCA0CLK (3) (4) X = Don't care Not available on RGZ package types. The pin direction is controlled by the USCI module. UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI_B0 is forced to 3-wire SPI mode if 4-wire SPI mode is selected. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 85 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 6.10.3 Port P3 (P3.0 to P3.4) Input/Output With Schmitt Trigger Figure 6-4 shows the port diagram. Table 6-46 summarizes the selection of the port function. Pad Logic P3REN.x P3DIR.x 0 From module 1 P3OUT.x 0 From module 1 DVSS 0 DVIO 1 1 Direction 0: Input 1: Output P3DS.x 0: Low drive 1: High drive P3SEL.x P3IN.x P3.0/UCB0SIMO/UCB0SDA P3.1/UCB0SOMI/UCB0SCL P3.2/UCB0CLK/UCA0STE P3.3/UCA0TXD/UCA0SIMO P3.4/UCA0RXD/UCA0SOMI EN To module D Figure 6-4. Port P3 (P3.0 to P3.4) Diagram Table 6-46. Port P3 (P3.0 to P3.4) Pin Functions PIN NAME (P3.x) P3.0/UCB0SIMO/UCB0SDA P3.1/UCB0SOMI/UCB0SCL P3.2/UCB0CLK/UCA0STE x 0 1 2 P3.3/UCA0TXD/UCA0SIMO 3 P3.4/UCA0RXD/UCA0SOMI 4 (1) (2) (3) (4) 86 FUNCTION P3.0 (I/O) UCB0SIMO/UCB0SDA (2) (3) P3.1 (I/O) UCB0SOMI/UCB0SCL (2) (3) P3.2 (I/O) UCB0CLK/UCA0STE (2) (4) P3.3 (I/O) UCA0TXD/UCA0SIMO (2) P3.4 (I/O) UCA0RXD/UCA0SOMI (2) CONTROL BITS OR SIGNALS (1) P3DIR.x P3SEL.x I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 X = Don't care The pin direction is controlled by the USCI module. If the I2C functionality is selected, the output drives only the logical 0 to VSS level. UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output, USCI_A0 is forced to 3-wire SPI mode if 4-wire SPI mode is selected. Detailed Description Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 6.10.4 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger Figure 6-5 shows the port diagram. Table 6-47 summarizes the selection of the port function. Pad Logic P4REN.x P4DIR.x 0 From Port Mapping Control 1 P4OUT.x 0 From Port Mapping Control 1 DVSS 0 DVIO 1 1 Direction 0: Input 1: Output P4.0/P4MAP0 P4.1/P4MAP1 P4.2/P4MAP2 P4.3/P4MAP3 P4.4/P4MAP4 P4.5/P4MAP5 P4.6/P4MAP6 P4.7/P4MAP7 P4DS.x 0: Low drive 1: High drive P4SEL.x P4IN.x EN D To Port Mapping Control Figure 6-5. Port P4 (P4.0 to P4.7) Diagram Table 6-47. Port P4 (P4.0 to P4.7) Pin Functions PIN NAME (P4.x) x P4.0/P4MAP0 0 P4.1/P4MAP1 1 P4.2/P4MAP2 2 P4.3/P4MAP3 3 P4.4/P4MAP4 4 P4.5/P4MAP5 5 P4.6/P4MAP6 6 P4.7/P4MAP7 (3) (1) (2) (3) 7 FUNCTION P4.0 (I/O) Mapped secondary digital function P4.1 (I/O) Mapped secondary digital function P4.2 (I/O) Mapped secondary digital function P4.3 (I/O) Mapped secondary digital function P4.4 (I/O) Mapped secondary digital function P4.5 (I/O) Mapped secondary digital function P4.6 (I/O) Mapped secondary digital function P4.7 (I/O) Mapped secondary digital function CONTROL BITS OR SIGNALS (1) P4DIR.x (2) P4SEL.x I: 0; O: 1 0 X X 1 ≤ 30 I: 0; O: 1 0 X ≤ 30 P4MAPx X 1 I: 0; O: 1 0 X X 1 ≤ 30 I: 0; O: 1 0 X X 1 ≤ 30 I: 0; O: 1 0 X X 1 ≤ 30 I: 0; O: 1 0 X X 1 ≤ 30 I: 0; O: 1 0 X ≤ 30 X 1 I: 0; O: 1 0 X X 1 ≤ 30 X = Don't care The direction of some mapped secondary functions are controlled directly by the module. See Table 6-7 for specific direction control information of mapped secondary functions. Not available on RGZ package types. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 87 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 6.10.5 Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger Figure 6-6 shows the port diagram. Table 6-48 summarizes the selection of the port function. Pad Logic To or from Reference (not available on F521x) (not available on F521x) to ADC10 (not available on F521x) INCHx = x P5REN.x P5DIR.x DVSS 0 DVCC 1 1 0 1 P5OUT.x 0 From module 1 P5.0/(A8/VeREF+) P5.1/(A9/VeREF–) P5DS.x 0: Low drive 1: High drive P5SEL.x P5IN.x Bus Keeper EN To module D Figure 6-6. Port P5 (P5.0 and P5.1) Diagram Table 6-48. Port P5 (P5.0 and P5.1) Pin Functions PIN NAME (P5.x) P5.0/A8/VeREF+ P5.1/A9/VeREF– (1) (2) (3) (4) (5) 88 x 0 1 FUNCTION P5.0 (I/O) (3) A8/VeREF+ (4) P5.1 (I/O) (3) A9/VeREF– (5) CONTROL BITS OR SIGNALS (1) P5DIR.x P5SEL.x REFOUT (2) I: 0; O: 1 0 X X 1 0 I: 0; O: 1 0 X X 1 0 X = Don't care REFOUT resides in the REF module. Default condition Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. An external voltage can be applied to VeREF+ and used as the reference for the ADC10_A. Channel A8, when selected with the INCHx bits, is connected to the VeREF+ pin. Setting the P5SEL.1 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. An external voltage can be applied to VeREF- and used as the reference for the ADC10_A. Channel A9, when selected with the INCHx bits, is connected to the VeREF- pin. Detailed Description Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 6.10.6 Port P5 (P5.2) Input/Output With Schmitt Trigger Figure 6-7 shows the port diagram. Table 6-49 summarizes the selection of the port function. Pad Logic To XT2 P5REN.2 P5DIR.2 DVSS 0 DVCC 1 1 0 1 P5OUT.2 0 Module X OUT 1 P5DS.2 0: Low drive 1: High drive P5SEL.2 P5.2/XT2IN P5IN.2 Bus Keeper EN Module X IN D Figure 6-7. Port P5 (P5.2) Diagram 6.10.7 Port P5 (P5.3) Input/Output With Schmitt Trigger Figure 6-8 shows the port diagram. Table 6-49 summarizes the selection of the port function. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 89 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com Pad Logic To XT2 P5REN.3 P5DIR.3 DVSS 0 DVCC 1 1 0 1 P5OUT.3 0 Module X OUT 1 P5SEL.2 P5.3/XT2OUT P5DS.3 0: Low drive 1: High drive XT2BYPASS P5SEL.3 P5IN.3 Bus Keeper EN Module X IN D Figure 6-8. Port P5 (P5.3) Diagram Table 6-49. Port P5 (P5.2 and P5.3) Pin Functions PIN NAME (P5.x) x FUNCTION P5.2 (I/O) P5.2/XT2IN 2 XT2IN crystal mode (2) XT2IN bypass mode (2) P5.3 (I/O) P5.3/XT2OUT 3 XT2OUT crystal mode (3) P5.3 (I/O) (1) (2) (3) 90 (3) CONTROL BITS OR SIGNALS (1) P5DIR.x P5SEL.2 P5SEL.3 XT2BYPASS I: 0; O: 1 0 X X X 1 X 0 X 1 X 1 I: 0; O: 1 0 0 X X 1 X 0 X 1 0 1 X = Don't care Setting P5SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P5.2 is configured for crystal mode or bypass mode. Setting P5SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.3 can be used as general-purpose I/O. Detailed Description Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 6.10.8 Port P5 (P5.4 and P5.5) Input/Output With Schmitt Trigger Figure 6-9 and Figure 6-10 show the port diagrams. Table 6-50 summarizes the selection of the port function. Pad Logic to XT1 P5REN.4 P5DIR.4 DVSS 0 DVCC 1 1 0 1 P5OUT.4 0 Module X OUT 1 P5DS.4 0: Low drive 1: High drive P5SEL.4 P5.4/XIN P5IN.4 Bus Keeper EN Module X IN D Figure 6-9. Port P5 (P5.4) Diagram Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 91 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com Pad Logic to XT1 P5REN.5 P5DIR.5 DVSS 0 DVCC 1 1 0 1 P5OUT.5 0 Module X OUT 1 P5.5/XOUT P5SEL.4 P5DS.5 0: Low drive 1: High drive XT1BYPASS P5SEL.5 P5IN.5 Bus Keeper EN Module X IN D Figure 6-10. Port P5 (P5.5) Diagram Table 6-50. Port P5 (P5.4 and P5.5) Pin Functions PIN NAME (P5.x) x FUNCTION P5.4 (I/O) P5.4/XIN 4 XIN crystal mode (2) XIN bypass mode (2) 5 (3) 92 P5SEL.4 P5SEL.5 XT1BYPASS 0 X X X 1 X 0 X 1 X 1 0 0 X XOUT crystal mode (3) X 1 X 0 (3) X 1 0 1 P5.5 (I/O) (1) (2) P5DIR.x I: 0; O: 1 I: 0; O: 1 P5.5 (I/O) P5.5/XOUT CONTROL BITS OR SIGNALS (1) X = Don't care Setting P5SEL.4 causes the general-purpose I/O to be disabled. Pending the setting of XT1BYPASS, P5.4 is configured for crystal mode or bypass mode. Setting P5SEL.4 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.5 can be used as general-purpose I/O. Detailed Description Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 6.10.9 Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger Figure 6-11 shows the port diagram. Table 6-51 summarizes the selection of the port function. Pad Logic to ADC10 (n/a MSPF430F521x) INCHx = x (n/a MSPF430F521x) to Comparator_B from Comparator_B CBPD.x P6REN.x P6DIR.x 0 0 From module 1 0 DVCC 1 P6DS.x 0: Low drive 1: High drive P6SEL.x P6IN.x Bus Keeper EN To module 1 Direction 0: Input 1: Output 1 P6OUT.x DVSS P6.0/CB0/(A0) P6.1/CB1/(A1) P6.2/CB2/(A2) P6.3/CB3/(A3) P6.4/CB4/(A4) P6.5/CB5/(A5) P6.6/CB6/(A6) P6.7/CB7/(A7) D Figure 6-11. Port P6 (P6.0 to P6.7) Diagram Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 93 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com Table 6-51. Port P6 (P6.0 to P6.7) Pin Functions PIN NAME (P6.x) x FUNCTION P6.0 (I/O) P6.0/CB0/(A0) 0 A0 CB0 (1) P6.1 (I/O) P6.1/CB1/(A1) 1 A1 CB1 (1) P6.2 (I/O) P6.2/CB2/(A2) 2 A2 CB2 (1) 3 4 5 6 (1) (2) 94 7 X 1 X X I: 0; O: 1 0 0 X 1 X 1 X X I: 0; O: 1 0 0 X 1 X 1 0 X 1 X CB3 (1) X X 1 I: 0; O: 1 0 0 A4 X 1 X CB4 (1) X X 1 I: 0; O: 1 0 0 A5 X 1 X CB5 (1) X X 1 I: 0; O: 1 0 0 X 1 X X X 1 I: 0; O: 1 0 0 A6 P6.7 (I/O) P6.7/CB7/(A7) 1 A3 CB6 (1) (2) 0 X 0 P6.6 (I/O) P6.6/CB6/(A6) (2) CBPD X P6.5 (I/O) P6.5/CB5/(A5) 0 X P6.4 (I/O) P6.4/CB4/(A4) P6SEL.x I: 0; O: 1 I: 0; O: 1 P6.3 (I/O) P6.3/CB3/(A3) CONTROL BITS OR SIGNALS P6DIR.x A7 X 1 X CB7 (1) X X 1 Setting the CBPD.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Selecting the CBx input pin to the comparator multiplexer with the CBx bits automatically disables output driver and input buffer for that pin, regardless of the state of the associated CBPD.x bit. Not available on RGZ package types. Detailed Description Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 6.10.10 Port P7 (P7.0 to P7.5) Input/Output With Schmitt Trigger Figure 6-12 shows the port diagram. Table 6-52 summarizes the selection of the port function. Pad Logic P7REN.x P7DIR.x 0 From module 1 P7OUT.x 0 DVSS 0 DVIO 1 1 Direction 0: Input 1: Output 1 P7.0/TB0.0 P7.1/TB0.1 P7.2/TB0.2 P7.3/TB0.3 P7.4/TB0.4 P7.5/TB0.5 P7DS.x 0: Low drive 1: High drive P7SEL.x P7IN.x EN D To module Figure 6-12. Port P7 (P7.0 to P7.5) Diagram Table 6-52. Port P7 (P7.0 to P7.5) Pin Functions PIN NAME (P7.x) x FUNCTION P7DIR.x P7SEL.x I: 0; O: 1 0 TB0.CCI0A 0 1 TB0.0 1 1 P7.0 (I/O) P7.0/TB0.0 (1) 0 P7.1 (I/O) P7.1/TB0.1 (1) 1 I: 0; O: 1 0 TB0.CCI1A 0 1 TB0.1 1 1 P7.2 (I/O) P7.2/TB0.2 (1) 2 I: 0; O: 1 0 TB0.CCI2A 0 1 TB0.2 1 1 P7.3 (I/O) P7.3/TB0.3 (1) 3 I: 0; O: 1 0 TB0.CCI3A 0 1 TB0.3 1 1 I: 0; O: 1 0 TB0.CCI4A 0 1 TB0.4 1 1 I: 0; O: 1 0 TB0.CCI5A 0 1 TB0.5 1 1 P7.4 (I/O) P7.4/TB0.4 (1) 4 P7.5 (I/O) P7.5/TB0.5 (1) (1) 5 CONTROL BITS OR SIGNALS Not available on RGZ package types. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 95 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com 6.10.11 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output Figure 6-13 shows the port diagram. Table 6-53 summarizes the selection of the port function. Pad Logic PJREN.0 PJDIR.0 0 DVCC 1 PJOUT.0 0 From JTAG 1 DVSS 0 DVCC 1 PJDS.0 0: Low drive 1: High drive From JTAG 1 PJ.0/TDO PJIN.0 EN D Figure 6-13. Port PJ (PJ.0) Diagram 6.10.12 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output Figure 6-14 shows the port diagram. Table 6-53 summarizes the selection of the port function. 96 Detailed Description Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 Pad Logic PJREN.x PJDIR.x 0 DVSS 1 PJOUT.x 0 From JTAG 1 DVSS 0 DVCC 1 PJDS.x 0: Low drive 1: High drive From JTAG 1 PJ.1/TDI/TCLK PJ.2/TMS PJ.3/TCK PJIN.x EN To JTAG D Figure 6-14. Port PJ (PJ.1 to PJ.3) Diagram Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 97 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com Table 6-53. Port PJ (PJ.0 to PJ.3) Pin Functions PIN NAME (PJ.x) x CONTROL BITS OR SIGNALS (1) FUNCTION PJDIR.x PJ.0/TDO 0 PJ.1/TDI/TCLK PJ.2/TMS 2 PJ.3/TCK (1) (2) (3) (4) 98 1 3 PJ.0 (I/O) (2) I: 0; O: 1 TDO (3) X PJ.1 (I/O) (2) TDI/TCLK (3) PJ.2 (I/O) TMS (3) I: 0; O: 1 (4) X (2) I: 0; O: 1 (4) X PJ.3 (I/O) (2) TCK (3) I: 0; O: 1 (4) X X = Don't care Default condition The pin direction is controlled by the JTAG module. In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care. Detailed Description Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 6.11 Device Descriptors Table 6-54 and Table 6-55 list the contents of the device descriptor tag-length-value (TLV) structure for each device type. Table 6-54. MSP430F522x Device Descriptor Table (1) Info Block Die Record ADC10 Calibration REF Calibration (1) VALUE ADDRESS SIZE (BYTES) F5229 F5227 F5224 F5222 Info length 01A00h 1 06h 06h 06h 06h CRC length 01A01h 1 06h 06h 06h 06h CRC value 01A02h 2 Per unit Per unit Per unit Per unit Device ID 01A04h 1 51h 4Fh 4Ch 4Ah DESCRIPTION Device ID 01A05h 1 81h 81h 81h 81h Hardware revision 01A06h 1 Per unit Per unit Per unit Per unit Firmware revision 01A07h 1 Per unit Per unit Per unit Per unit Die record tag 01A08h 1 08h 08h 08h 08h Die record length 01A09h 1 0Ah 0Ah 0Ah 0Ah Lot/wafer ID 01A0Ah 4 Per unit Per unit Per unit Per unit Die X position 01A0Eh 2 Per unit Per unit Per unit Per unit Die Y position 01A10h 2 Per unit Per unit Per unit Per unit Test results 01A12h 2 Per unit Per unit Per unit Per unit ADC10 calibration tag 01A14h 1 13h 13h 13h 13h ADC10 calibration length 01A15h 1 10h 10h 10h 10h ADC gain factor 01A16h 2 Per unit Per unit Per unit Per unit ADC offset 01A18h 2 Per unit Per unit Per unit Per unit ADC 1.5-V reference Temperature sensor 30°C 01A1Ah 2 Per unit Per unit Per unit Per unit ADC 1.5-V reference Temperature sensor 85°C 01A1Ch 2 Per unit Per unit Per unit Per unit ADC 2.0-V reference Temperature sensor 30°C 01A1Eh 2 Per unit Per unit Per unit Per unit ADC 2.0-V reference Temperature sensor 85°C 01A20h 2 Per unit Per unit Per unit Per unit ADC 2.5-V reference Temperature sensor 30°C 01A22h 2 Per unit Per unit Per unit Per unit ADC 2.5-V reference Temperature sensor 85°C 01A24h 2 Per unit Per unit Per unit Per unit 12h REF calibration tag 01A26h 1 12h 12h 12h REF calibration length 01A27h 1 06h 06h 06h 06h REF 1.5-V reference factor 01A28h 2 Per unit Per unit Per unit Per unit REF 2.0-V reference factor 01A2Ah 2 Per unit Per unit Per unit Per unit REF 2.5-V reference factor 01A2Ch 2 Per unit Per unit Per unit Per unit NA = Not applicable Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 99 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com Table 6-54. MSP430F522x Device Descriptor Table(1) (continued) SIZE (BYTES) Peripheral descriptor tag 01A2Eh 1 02h 02h 02h 02h Peripheral descriptor length 01A2Fh 1 5Fh 5Fh 5Dh 5Dh Memory 1 2 08h 8Ah 08h 8Ah 08h 8Ah 08h 8Ah Memory 2 2 0Ch 86h 0Ch 86h 0Ch 86h 0Ch 86h Memory 3 2 12h 2Eh 12h 2Eh 12h 2Eh 12h 2Eh Memory 4 2 22h 96h 22h 94h 22h 96h 22h 94h Memory 5 2 N/A N/A N/A N/A Memory 6 1/2 N/A N/A N/A N/A Delimiter 1 00h 00h 00h 00h Peripheral count 1 20h 20h 1Fh 1Fh MSP430CPUXV2 2 00h 23h 00h 23h 00h 23h 00h 23h JTAG 2 00h 09h 00h 09h 00h 09h 00h 09h SBW 2 00h 0Fh 00h 0Fh 00h 0Fh 00h 0Fh EEM-S 2 00h 03h 00h 03h 00h 03h 00h 05h TI BSL 2 00h FCh 00h FCh 00h FCh 00h FCh SFR 2 10h 41h 10h 41h 10h 41h 10h 41h PMM 2 02h 30h 02h 30h 02h 30h 02h 30h FCTL 2 02h 38h 02h 38h 02h 38h 02h 38h CRC16 2 01h 3Ch 01h 3Ch 01h 3Ch 01h 3Ch CRC16_RB 2 00h 3Dh 00h 3Dh 00h 3Dh 00h 3Dh RAMCTL 2 00h 44h 00h 44h 00h 44h 00h 44h WDT_A 2 00h 40h 00h 40h 00h 40h 00h 40h UCS 2 01h 48h 01h 48h 01h 48h 01h 48h SYS 2 02h 42h 02h 42h 02h 42h 02h 42h REF 2 03h A0h 03h A0h 03h A0h 03h A0h Port mapping 2 01h 10h 01h 10h 01h 10h 01h 10h Port 1/2 2 04h 51h 04h 51h 04h 51h 04h 51h Port 3/4 2 02h 52h 02h 52h 02h 52h 02h 52h Port 5/6 2 02h 53h 02h 53h 02h 53h 02h 53h Peripheral Descriptor 100 VALUE ADDRESS DESCRIPTION Detailed Description F5229 F5227 F5224 F5222 Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 Table 6-54. MSP430F522x Device Descriptor Table(1) (continued) DESCRIPTION Peripheral Descriptor (continued) Interrupts ADDRESS SIZE (BYTES) VALUE F5229 F5227 F5224 F5222 Port 7/8 2 02h 54h 02h 54h N/A N/A JTAG 2 0Ch 5Fh 0Ch 5Fh 0Eh 5Fh 0Eh 5Fh TA0 2 02h 62h 02h 62h 02h 62h 02h 62h TA1 2 04h 61h 04h 61h 04h 61h 04h 61h TB0 2 04h 67h 04h 67h 04h 67h 04h 67h TA2 2 04h 61h 04h 61h 04h 61h 04h 61h RTC 2 0Ah 68h 0Ah 68h 0Ah 68h 0Ah 68h MPY32 2 02h 85h 02h 85h 02h 85h 02h 85h DMA-3 2 04h 47h 04h 47h 04h 47h 04h 47h USCI_A/B 2 0Ch 90h 0Ch 90h 0Ch 90h 0Ch 90h USCI_A/B 2 04h 90h 04h 90h 04h 90h 04h 90h ADC10_A 2 14h D3h 14h D3h 14h D3h 14h D3h COMP_B 2 18h A8h 18h A8h 18h A8h 18h A8h COMP_B 1 A8h A8h A8h A8h TB0.CCIFG0 1 64h 64h 64h 64h TB0.CCIFG1..6 1 65h 65h 65h 65h WDTIFG 1 40h 40h 40h 40h USCI_A0 1 90h 90h 90h 90h USCI_B0 1 91h 91h 91h 91h ADC10_A 1 D0h D0h D0h D0h TA0.CCIFG0 1 60h 60h 60h 60h TA0.CCIFG1..4 1 61h 61h 61h 61h Reserved 1 01h 01h 01h 01h DMA 1 46h 46h 46h 46h TA1.CCIFG0 1 62h 62h 62h 62h TA1.CCIFG1..2 1 63h 63h 63h 63h P1 1 50h 50h 50h 50h USCI_A1 1 92h 92h 92h 92h USCI_B1 1 93h 93h 93h 93h TA1.CCIFG0 1 66h 66h 66h 66h TA1.CCIFG1..2 1 67h 67h 67h 67h P2 1 51h 51h 51h 51h RTC_A 1 68h 68h 68h 68h Delimiter 1 00h 00h 00h 00h Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 101 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com Table 6-55. MSP430F521x Device Descriptor Table (1) Info Block Die Record ADC10 Calibration REF Calibration (1) 102 VALUE ADDRESS SIZE (BYTES) F5219 F5217 F5214 F5212 Info length 01A00h 1 06h 06h 06h 06h CRC length 01A01h 1 06h 06h 06h 06h CRC value 01A02h 2 Per unit Per unit Per unit Per unit Device ID 01A04h 1 47h 45h 42h 40h Device ID 01A05h 1 81h 81h 81h 81h Hardware revision 01A06h 1 Per unit Per unit Per unit Per unit Firmware revision 01A07h 1 Per unit Per unit Per unit Per unit Die record tag 01A08h 1 08h 08h 08h 08h Die record length 01A09h 1 0Ah 0Ah 0Ah 0Ah Lot/wafer ID 01A0Ah 4 Per unit Per unit Per unit Per unit Die X position 01A0Eh 2 Per unit Per unit Per unit Per unit Die Y position 01A10h 2 Per unit Per unit Per unit Per unit DESCRIPTION Test results 01A12h 2 Per unit Per unit Per unit Per unit ADC10 calibration tag 01A14h 1 13h 13h 13h 13h ADC10 calibration length 01A15h 1 10h 10h 10h 10h ADC gain factor 01A16h 2 Blank Blank Blank Blank ADC offset 01A18h 2 Blank Blank Blank Blank ADC 1.5-V reference Temperature sensor 30°C 01A1Ah 2 Blank Blank Blank Blank ADC 1.5-V Reference Temperature sensor 85°C 01A1Ch 2 Blank Blank Blank Blank ADC 2.0-V reference Temperature sensor 30°C 01A1Eh 2 Blank Blank Blank Blank ADC 2.0-V reference Temperature sensor 85°C 01A20h 2 Blank Blank Blank Blank ADC 2.5-V reference Temperature sensor 30°C 01A22h 2 Blank Blank Blank Blank ADC 2.5-V reference Temperature sensor 85°C 01A24h 2 Blank Blank Blank Blank 12h REF calibration tag 01A26h 1 12h 12h 12h REF calibration length 01A27h 1 06h 06h 06h 06h REF 1.5-V reference factor 01A28h 2 Per unit Per unit Per unit Per unit REF 2.0-V reference factor 01A2Ah 2 Per unit Per unit Per unit Per unit REF 2.5-V reference factor 01A2Ch 2 Per unit Per unit Per unit Per unit NA = Not applicable, Blank = unused and reads FFh Detailed Description Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 Table 6-55. MSP430F521x Device Descriptor Table(1) (continued) Peripheral Descriptor VALUE ADDRESS SIZE (BYTES) Peripheral descriptor tag 01A2Eh 1 02h 02h 02h 02h Peripheral descriptor length 01A2Fh 1 5Dh 5Dh 5Bh 5Bh Memory 1 2 08h 8Ah 08h 8Ah 08h 8Ah 08h 8Ah Memory 2 2 0Ch 86h 0Ch 86h 0Ch 86h 0Ch 86h Memory 3 2 12h 2Eh 12h 2Eh 12h 2Eh 12h 2Eh Memory 4 2 22h 96h 22h 94h 22h 96h 22h 94h Memory 5 2 N/A N/A N/A N/A Memory 6 1/2 N/A N/A N/A N/A Delimiter 1 00h 00h 00h 00h Peripheral count 1 1Fh 1Fh 1Eh 1Eh MSP430CPUXV2 2 00h 23h 00h 23h 00h 23h 00h 23h JTAG 2 00h 09h 00h 09h 00h 09h 00h 09h SBW 2 00h 0Fh 00h 0Fh 00h 0Fh 00h 0Fh EEM-S 2 00h 03h 00h 03h 00h 03h 00h 05h TI BSL 2 00h FCh 00h FCh 00h FCh 00h FCh SFR 2 10h 41h 10h 41h 10h 41h 10h 41h PMM 2 02h 30h 02h 30h 02h 30h 02h 30h FCTL 2 02h 38h 02h 38h 02h 38h 02h 38h CRC16 2 01h 3Ch 01h 3Ch 01h 3Ch 01h 3Ch CRC16_RB 2 00h 3Dh 00h 3Dh 00h 3Dh 00h 3Dh RAMCTL 2 00h 44h 00h 44h 00h 44h 00h 44h WDT_A 2 00h 40h 00h 40h 00h 40h 00h 40h UCS 2 01h 48h 01h 48h 01h 48h 01h 48h SYS 2 02h 42h 02h 42h 02h 42h 02h 42h REF 2 03h A0h 03h A0h 03h A0h 03h A0h Port mapping 2 01h 10h 01h 10h 01h 10h 01h 10h Port 1/2 2 04h 51h 04h 51h 04h 51h 04h 51h Port 3/4 2 02h 52h 02h 52h 02h 52h 02h 52h Port 5/6 2 02h 53h 02h 53h 02h 53h 02h 53h DESCRIPTION F5219 F5217 F5214 F5212 Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 103 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com Table 6-55. MSP430F521x Device Descriptor Table(1) (continued) DESCRIPTION Peripheral Descriptor (continued) Interrupts 104 Detailed Description ADDRESS SIZE (BYTES) VALUE F5219 F5217 F5214 F5212 Port 7/8 2 02h 54h 02h 54h N/A N/A JTAG 2 0Ch 5Fh 0Ch 5Fh 0Eh 5Fh 0Eh 5Fh TA0 2 02h 62h 02h 62h 02h 62h 02h 62h TA1 2 04h 61h 04h 61h 04h 61h 04h 61h TB0 2 04h 67h 04h 67h 04h 67h 04h 67h TA2 2 04h 61h 04h 61h 04h 61h 04h 61h RTC 2 0Ah 68h 0Ah 68h 0Ah 68h 0Ah 68h MPY32 2 02h 85h 02h 85h 02h 85h 02h 85h DMA-3 2 04h 47h 04h 47h 04h 47h 04h 47h USCI_A/B 2 0Ch 90h 0Ch 90h 0Ch 90h 0Ch 90h USCI_A/B 2 04h 90h 04h 90h 04h 90h 04h 90h ADC10_A 2 N/A N/A N/A N/A COMP_B 2 2Ch A8h 2Ch A8h 2Ch A8h 2Ch A8h COMP_B 1 A8h A8h A8h A8h TB0.CCIFG0 1 64h 64h 64h 64h TB0.CCIFG1..6 1 65h 65h 65h 65h WDTIFG 1 40h 40h 40h 40h USCI_A0 1 90h 90h 90h 90h USCI_B0 1 91h 91h 91h 91h Reserved 1 01h 01h 01h 01h TA0.CCIFG0 1 60h 60h 60h 60h TA0.CCIFG1..4 1 61h 61h 61h 61h Reserved 1 01h 01h 01h 01h DMA 1 46h 46h 46h 46h TA1.CCIFG0 1 62h 62h 62h 62h TA1.CCIFG1..2 1 63h 63h 63h 63h P1 1 50h 50h 50h 50h USCI_A1 1 92h 92h 92h 92h USCI_B1 1 93h 93h 93h 93h TA2.CCIFG0 1 66h 66h 66h 66h TA2.CCIFG1..2 1 67h 67h 67h 67h P2 1 51h 51h 51h 51h RTC_A 1 68h 68h 68h 68h Delimiter 1 00h 00h 00h 00h Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 7 Device and Documentation Support 7.1 Getting Started For more information on the MSP430 family of devices and the tools and libraries that are available to help with your development, visit the MSP430 ultra-low-power sensing and measurement MCUs overview. 7.2 Device Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS. These prefixes represent evolutionary stages of product development from engineering prototypes (XMS) through fully qualified production devices (MSP). XMS – Experimental device that is not necessarily representative of the final device's electrical specifications MSP – Fully qualified production device XMS devices are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices. TI recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature range, package type, and distribution format. Figure 7-1 provides a legend for reading the complete device name. Device and Documentation Support Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 105 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com MSP 430 F 5 438 A I ZQW T -EP Processor Family Optional: Additional Features MCU Platform Optional: Tape and Reel Device Type Packaging Series Feature Set Processor Family MCU Platform Optional: Temperature Range Optional: A = Revision CC = Embedded RF Radio MSP = Mixed-Signal Processor XMS = Experimental Silicon PMS = Prototype Device 430 = MSP430 low-power microcontroller platform Device Type Memory Type C = ROM F = Flash FR = FRAM G = Flash or FRAM (Value Line) L = No Nonvolatile Memory Specialized Application AFE = Analog Front End BQ = Contactless Power CG = ROM Medical FE = Flash Energy Meter FG = Flash Medical FW = Flash Electronic Flow Meter Series 1 = Up to 8 MHz 2 = Up to 16 MHz 3 = Legacy 4 = Up to 16 MHz with LCD 5 = Up to 25 MHz 6 = Up to 25 MHz with LCD 0 = Low-Voltage Series Feature Set Various levels of integration within a series Optional: A = Revision N/A Optional: Temperature Range S = 0°C to 50°C C = 0°C to 70°C I = –40°C to 85°C T = –40°C to 105°C Packaging http://www.ti.com/packaging Optional: Tape and Reel T = Small reel R = Large reel No markings = Tube or tray Optional: Additional Features -EP = Enhanced Product (–40°C to 105°C) -HT = Extreme Temperature Parts (–55°C to 150°C) -Q1 = Automotive Q100 Qualified Figure 7-1. Device Nomenclature 106 Device and Documentation Support Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com 7.3 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 Tools and Software All MSP microcontrollers are supported by a wide variety of software and hardware development tools. Tools are available from TI and various third parties. See them all at MSP430 Ultra-Low-Power MCUs – Tools & software. Table 7-1 lists the debug features of the MSP430F522x and MSP430F521x MCUs. See the Code Composer Studio for MSP430 User's Guide for details on the available features. Table 7-1. Hardware Debug Features MSP430 ARCHITECTURE 4-WIRE JTAG 2-WIRE JTAG BREAKPOINTS (N) RANGE BREAKPOINTS CLOCK CONTROL STATE SEQUENCER TRACE BUFFER LPMx.5 DEBUGGING SUPPORT EnergyTrace++ Technology MSP430Xv2 Yes Yes 3 Yes Yes No No Yes Yes Design Kits and Evaluation Modules MSP-TS430RGC64C - 64-pin Target Development Board for MSP430F5x MCUs The MSPTS430RGC64C is a stand-alone 64-pin ZIF socket target board used to program and debug the MSP430 MCU in system through the JTAG interface or the Spy-Bi-Wire (2-wire JTAG) protocol. Bluetooth® and MSP430 Audio Source Reference Design Board The Bluetooth and MSP430 Audio Source reference design can be used by customers to create a variety of applications for low-end, low-power audio source solutions for applications including toys, projectors, smart remotes and any audio streaming accessories. Dual-Mode Bluetooth CC2564 Module With Integrated Antenna Evaluation Board The CC2564MODAEM evaluation board contains the Bluetooth BR/EDR/LE HCI solution. Based on TI's CC2564B dual-mode Bluetooth single-chip device, the bCC2564MODA is intended for evaluation and design purposes, reducing design effort and enabling fast time to market. Software MSP430Ware™ Software MSP430Ware software is a collection of code examples, data sheets, and other design resources for all MSP430 devices delivered in a convenient package. In addition to providing a complete collection of existing MSP430 MCU design resources, MSP430Ware software also includes a high-level API called MSP Driver Library. This library makes it easy to program MSP430 hardware. MSP430Ware software is available as a component of CCS or as a stand-alone package. MSP430F522x, MSP430F521x Code Examples C code examples that configure each of the integrated peripherals for various application needs. MSP Driver Library The abstracted API of MSP Driver Library provides easy-to-use function calls that free you from directly manipulating the bits and bytes of the MSP430 hardware. Thorough documentation is delivered through a helpful API Guide, which includes details on each function call and the recognized parameters. Developers can use Driver Library functions to write complete projects with minimal overhead. MSP EnergyTrace™ Technology EnergyTrace technology for MSP430 microcontrollers is an energybased code analysis tool that measures and displays the energy profile of the application and helps to optimize it for ultra-low-power consumption. ULP (Ultra-Low Power) Advisor ULP Advisor™ software is a tool for guiding developers to write more efficient code to fully use the unique ultra-low-power features of MSP and MSP432 microcontrollers. Aimed at both experienced and new microcontroller developers, ULP Advisor checks your code against a thorough ULP checklist to help minimize the energy consumption of your application. At build time, ULP Advisor provides notifications and remarks to highlight areas of your code that can be further optimized for lower power. IEC60730 Software Package The IEC60730 MSP430 software package was developed to help customers comply with IEC 60730-1:2010 (Automatic Electrical Controls for Household and Similar Use – Part 1: General Requirements) for up to Class B products, which includes home appliances, arc detectors, power converters, power tools, e-bikes, and many others. The IEC60730 MSP430 software package can be embedded in customer applications running on MSP430s to help simplify the customer’s certification efforts of functional safetycompliant consumer devices to IEC 60730-1:2010 Class B. Device and Documentation Support Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 107 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 www.ti.com Fixed Point Math Library for MSP The MSP IQmath and Qmath Libraries are a collection of highly optimized and high-precision mathematical functions for C programmers to seamlessly port a floating-point algorithm into fixed-point code on MSP430 and MSP432 devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed, high accuracy, and ultra-low energy are critical. By using the IQmath and Qmath libraries, it is possible to achieve execution speeds considerably faster and energy consumption considerably lower than equivalent code written using floating-point math. Floating Point Math Library for MSP430 Continuing to innovate in the low-power and low-cost microcontroller space, TI provides MSPMATHLIB. Leveraging the intelligent peripherals of our devices, this floating-point math library of scalar functions that are up to 26 times faster than the standard MSP430 math functions. Mathlib is easy to integrate into your designs. This library is free and is integrated in both Code Composer Studio IDE and IAR Embedded Workbench IDE. Development Tools Code Composer Studio™ Integrated Development Environment for MSP Microcontrollers Code Composer Studio (CCS) integrated development environment (IDE) supports all MSP microcontroller devices. CCS comprises a suite of embedded software utilities used to develop and debug embedded applications. CCS includes an optimizing C/C++ compiler, source code editor, project build environment, debugger, profiler, and many other features. Command-Line Programmer MSP Flasher is an open-source shell-based interface for programming MSP microcontrollers through a FET programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP Flasher can download binary files (.txt or .hex) directly to the MSP microcontroller without an IDE. MSP MCU Programmer and Debugger The MSP-FET is a powerful emulation development tool – often called a debug probe – which lets users quickly begin application development on MSP lowpower MCUs. Creating MCU software usually requires downloading the resulting binary program to the MSP device for validation and debugging. MSP-GANG Production Programmer The MSP Gang Programmer is an MSP430 or MSP432 device programmer that can program up to eight identical MSP430 or MSP432 flash or FRAM devices at the same time. The MSP Gang Programmer connects to a host PC using a standard RS-232 or USB connection and provides flexible programming options that let the user fully customize the process. 7.4 Documentation Support The following documents describe the MSP430F522x and MSP430F521x MCUs. Copies of these documents are available on the Internet at www.ti.com. Receiving Notification of Document Updates To receive notification of documentation updates—including silicon errata—go to the product folder for your device on ti.com (see Section 7.5 for links to product folders). In the upper right corner, click the "Alert me" button. This registers you to receive a weekly digest of product information that has changed (if any). For change details, check the revision history of any revised document. Errata MSP430F5229 Device Erratasheet Describes the known exceptions to the functional specifications for the MSP430F5229 device. MSP430F5227 Device Erratasheet Describes the known exceptions to the functional specifications for the MSP430F5227 device. MSP430F5224 Device Erratasheet Describes the known exceptions to the functional specifications for the MSP430F5224 device. MSP430F5222 Device Erratasheet Describes the known exceptions to the functional specifications for the MSP430F5222 device. MSP430F5219 Device Erratasheet Describes the known exceptions to the functional specifications for the MSP430F5219 device. MSP430F5217 Device Erratasheet Describes the known exceptions to the functional specifications for the MSP430F5217 device. 108 Device and Documentation Support Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 MSP430F5214 Device Erratasheet Describes the known exceptions to the functional specifications for the MSP430F5214 device. MSP430F5212 Device Erratasheet Describes the known exceptions to the functional specifications for the MSP430F5212 device. User's Guides MSP430F5xx and MSP430F6xx Family User's Guide peripherals available in this device family. Detailed information on the modules and MSP430 Flash Device Bootloader (BSL) User's Guide The MSP430 bootloader (BSL) (formerly known as the bootstrap loader) lets users communicate with embedded memory in the MSP430 microcontroller during the prototyping phase, final production, and in service. Both the programmable memory (flash memory) and the data memory (RAM) can be modified as required. Do not confuse the bootloader with the bootstrap loader programs found in some digital signal processors (DSPs) that automatically load program code (and data) from external memory to the internal memory of the DSP. MSP430 Programming With the JTAG Interface This document describes the functions that are required to erase, program, and verify the memory module of the MSP430 flash-based and FRAM-based microcontroller families using the JTAG communication port. In addition, it describes how to program the JTAG access security fuse that is available on all MSP430 devices. This document describes device access using both the standard 4-wire JTAG interface and the 2-wire JTAG interface, which is also referred to as Spy-Bi-Wire (SBW). MSP430 Hardware Tools User's Guide This manual describes the hardware of the TI MSP-FET430 Flash Emulation Tool (FET). The FET is the program development tool for the MSP430 ultralow-power microcontroller. Application Reports Designing with MSP430F522x and MSP430F521x Devices The MSP430F522x and MSP430F521x devices support a split supply I/O system that is essential in systems in which the MCU is required to interface with external devices (such as sensors or other processors) that operate at different voltage level compared to the MCU device supply. Additionally, the split supply input voltage range of the F522x and F521x devices starts as low as 1.62 V (see the device data sheet specifications), and this allows for nominal 1.8-V I/O interface without the need for external level translation. This application report describes the various design considerations to keep in mind while designing the F522x and F521x devices in an application. General Oversampling of MSP ADCs for Higher Resolution Multiple MSP ultra-low-power microcontrollers offer analog-to-digital converters (ADCs) to convert physical quantities into digital numbers, a function that is widely used across numerous applications. There are times, however, when a customer design demands a higher resolution than the ADC of the selected MSP can offer. This application report, which is based on the previously-published Oversampling the ADC12 for Higher Resolution (SLAA323), therefore describes how an oversampling method can be incorporated to increase ADC resolution past the currently available number of bits. MSP430 32-kHz Crystal Oscillators Selection of the correct crystal, correct load circuit, and proper board layout are important for a stable crystal oscillator. This application report summarizes crystal oscillator function and explains the parameters to select the correct crystal for MSP430 ultra-low-power operation. In addition, hints and examples for correct board layout are given. The document also contains detailed information on the possible oscillator tests to ensure stable oscillator operation in mass production. MSP430 System-Level ESD Considerations System-Level ESD has become increasingly demanding as silicon technology scales to lower voltages and the need for designing cost-effective and ultra-low-power components. This application report addresses three ESD topics to help board designers and OEMs understand and design robust system-level designs: (1) Component-level ESD testing and system-level ESD testing; (2) General design guidelines for system-level ESD protection; (3) Introduction to System Efficient ESD Design (SEED), a co-design methodology of on-board and on-chip ESD protection. A few real-world systemlevel ESD protection design examples and their results are discussed. Device and Documentation Support Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 Copyright © 2012–2018, Texas Instruments Incorporated 109 MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718H – NOVEMBER 2012 – REVISED SEPTEMBER 2018 7.5 www.ti.com Related Links Table 7-2 lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 7-2. Related Links 7.6 PARTS PRODUCT FOLDER ORDER NOW TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY MSP430F5229 Click here Click here Click here Click here Click here MSP430F5227 Click here Click here Click here Click here Click here MSP430F5224 Click here Click here Click here Click here Click here MSP430F5222 Click here Click here Click here Click here Click here MSP430F5219 Click here Click here Click here Click here Click here MSP430F5217 Click here Click here Click here Click here Click here MSP430F5214 Click here Click here Click here Click here Click here MSP430F5212 Click here Click here Click here Click here Click here Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers. TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices. 7.7 Trademarks MSP430, MSP430Ware, EnergyTrace, ULP Advisor, Code Composer Studio, E2E are trademarks of Texas Instruments. Bluetooth is a registered trademark of Bluetooth SIG. All other trademarks are the property of their respective owners. 7.8 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 7.9 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 8 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 110 Mechanical, Packaging, and Orderable Information Copyright © 2012–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 PACKAGE OPTION ADDENDUM www.ti.com 28-Jan-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) MSP430F5212IRGZT ACTIVE VQFN RGZ 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F5212 MSP430F5214IRGZR ACTIVE VQFN RGZ 48 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F5214 MSP430F5217IRGCT ACTIVE VQFN RGC 64 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F5217 MSP430F5217IYFFR ACTIVE DSBGA YFF 64 2500 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 M430F5217 MSP430F5219IYFFT ACTIVE DSBGA YFF 64 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 M430F5219 MSP430F5222IRGZR ACTIVE VQFN RGZ 48 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F5222 MSP430F5222IRGZT ACTIVE VQFN RGZ 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F5222 MSP430F5224IRGZR ACTIVE VQFN RGZ 48 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F5224 MSP430F5229IRGCR ACTIVE VQFN RGC 64 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F5229 MSP430F5229IRGCT ACTIVE VQFN RGC 64 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F5229 MSP430F5229IYFFR ACTIVE DSBGA YFF 64 2500 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 M430F5229 MSP430F5229IYFFT ACTIVE DSBGA YFF 64 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 M430F5229 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of