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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435
MSP430F5419, MSP430F5418
SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
MSP430F543x, MSP430F541x Mixed-Signal Microcontrollers
1 Device Overview
1.1
Features
1
• Low Supply Voltage Range: 2.2 V to 3.6 V
• Ultra-Low Power Consumption
– Active Mode (AM): All System Clocks Active
– 312 µA/MHz at 8 MHz, 3.0 V, Flash Program
Execution (Typical)
– 140 µA/MHz at 8 MHz, 3.0 V, RAM Program
Execution (Typical)
– Standby Mode (LPM3):
– Real-Time Clock (RTC) With Crystal,
Watchdog, and Supply Supervisor
Operational, Full RAM Retention, Fast Wake
up: 2.6 µA at 3.0 V (Typical)
– Low-Power Oscillator (VLO), GeneralPurpose Counter, Watchdog, and Supply
Supervisor Operational, Full RAM Retention,
Fast Wakeup: 1.8 µA at 3.0 V (Typical)
– Off Mode (LPM4):
Full RAM Retention, Supply Supervisor
Operational, Fast Wakeup:
1.69 µA at 3.0 V (Typical)
• Wake up From Standby Mode in Less Than 5 µs
• 16-Bit RISC Architecture
– Extended Memory
– Up to 18-MHz System Clock
• Flexible Power-Management System
– Fully Integrated LDO With Programmable
Regulated Core Supply Voltage
– Supply Voltage Supervision, Monitoring, and
Brownout
• Unified Clock System (UCS)
– FLL Control Loop for Frequency Stabilization
– Low-Power Low-Frequency Internal Clock
Source (VLO)
1.2
•
•
•
•
•
•
•
•
•
•
•
•
•
– Low-Frequency Trimmed Internal Reference
Source (REFO)
– 32-kHz Crystals
– High-Frequency Crystals up to 32 MHz
16-Bit Timer TA0, Timer_A With Five
Capture/Compare Registers
16-Bit Timer TA1, Timer_A With Three
Capture/Compare Registers
16-Bit Timer TB0, Timer_B With Seven
Capture/Compare Shadow Registers
Up to Four Universal Serial Communication
Interfaces
– USCI_A0, USCI_A1, USCI_A2, and USCI_A3
Each Support:
– Enhanced UART Supports Automatic BaudRate Detection
– IrDA Encoder and Decoder
– Synchronous SPI
– USCI_B0, USCI_B1, USCI_B2, and USCI_B3
Each Support:
– I2C
– Synchronous SPI
12-Bit Analog-to-Digital Converter (ADC)
– Internal Reference
– Sample-and-Hold
– Autoscan Feature
– 14 External Channels, 2 Internal Channels
Hardware Multiplier Supporting 32-Bit Operations
Serial Onboard Programming, No External
Programming Voltage Needed
3-Channel Internal DMA
Basic Timer With RTC Feature
Device Comparison Summarizes the Available
Family Members
Applications
Analog and Digital Sensor Systems
Digital Motor Control
Remote Controls
•
•
•
Thermostats
Digital Timers
Hand-Held Meters
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435
MSP430F5419, MSP430F5418
SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
1.3
www.ti.com
Description
The TI MSP family of ultra-low-power microcontrollers consists of several devices featuring different sets
of peripherals targeted for various applications. The architecture, combined with five low-power modes, is
optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from low-power modes to
active mode in less than 5 µs.
The MSP430F543x and MSP430F541x microcontrollers have three 16-bit timers, a high-performance 12bit analog-to-digital converter (ADC), up to four universal serial communication interfaces (USCIs), a
hardware multiplier, DMA, a real-time clock (RTC) module with alarm capabilities, and up to 87 I/O pins.
For complete module descriptions, see the MSP430F5xx and MSP430F6xx Family User's Guide.
Device Information (1)
PACKAGE
BODY SIZE (2)
MSP430F5438IPZ
LQFP (100)
14 mm × 14 mm
MSP430F5437IPN
LQFP (80)
12 mm × 12 mm
MSP430F5436IPZ
LQFP (100)
14 mm × 14 mm
MSP430F5435IPN
LQFP (80)
12 mm × 12 mm
MSP430F5419IPZ
LQFP (100)
14 mm × 14 mm
MSP430F5418IPN
LQFP (80)
12 mm × 12 mm
PART NUMBER
(1)
(2)
2
For the most current device, package, and ordering information, see the Package Option Addendum in
Section 8, or see the TI website at www.ti.com.
The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 8.
Device Overview
Copyright © 2009–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5438 MSP430F5437 MSP430F5436 MSP430F5435 MSP430F5419 MSP430F5418
MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435
MSP430F5419, MSP430F5418
www.ti.com
1.4
SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
Functional Block Diagrams
Figure 1-1 shows the functional block diagram for the devices in the PZ package.
DVCC DVSS
XIN XOUT
AVCC AVSS
PA
P2.x
RST/NMI
P1.x
XT2IN
XT2OUT
Unified
Clock
System
ACLK
256KB
192KB
128KB
SMCLK
Flash
MCLK
CPUXV2
and
Working
Registers
16KB
Power
Management
SYS
LDO,
SVM, SVS,
Brownout
RAM
Watchdog
PB
P4.x
P3.x
I/O Ports
P1, P2
2×8 I/Os
Interrupt
Capability
PA
1×16 I/Os
P5.x
PC
P6.x
P7.x
PD
P8.x
PE
P9.x P10.x
PF
P11.x
I/O Ports
P3, P4
2×8 I/Os
I/O Ports
P5, P6
2×8 I/Os
I/O Ports
P7, P8
2×8 I/Os
I/O Ports
P9, P10
2×8 I/Os
I/O Ports
P11
1×3 I/Os
PB
1×16 I/Os
PC
1×16 I/Os
PD
1×16 I/Os
PE
1×16 I/Os
PF
1×3 I/Os
MAB
DMA
MDB
3 Channel
EEM
(L: 8+2)
TA0
JTAG,
SBW
Interface
MPY32
TA1
Timer_A
5 CC
Registers
TB0
Timer_A
3 CC
Registers
Timer_B
7 CC
Registers
RTC_A
CRC16
USCI0,1,2,3
ADC12_A
UCSI_Ax:
UART,
IrDA, SPI
12 bit
200 ksps
16 channels
(14 ext, 2 int)
Autoscan
UCSI_Bx:
SPI, I2C
Copyright © 2016, Texas Instruments Incorporated
Figure 1-1. Functional Block Diagram, MSP430F5438IPZ, MSP430F5436IPZ, MSP430F5419IPZ
Figure 1-2 shows the functional block diagram of the devices in the PN package.
XIN XOUT
DVCC DVSS
AVCC AVSS
RST/NMI
P1.x
XT2IN
XT2OUT
Unified
Clock
System
Power
Management
ACLK
SMCLK
256KB
192KB
128KB
16KB
RAM
MCLK
CPUXV2
and
Working
Registers
SYS
Flash
LDO,
SVM, SVS,
Brownout
Watchdog
PA
P2.x
I/O Ports
P1, P2
2×8 I/Os
Interrupt
Capability
PA
1×16 I/Os
P3.x
PB
P4.x
P5.x
PC
P6.x
P7.x
PD
P8.x
I/O Ports
P3, P4
2×8 I/Os
I/O Ports
P5, P6
2×8 I/Os
I/O Ports
P7, P8
2×8 I/Os
PB
1×16 I/Os
PC
1×16 I/Os
PD
1×16 I/Os
MAB
DMA
MDB
3 Channel
EEM
(L: 8+2)
JTAG,
SBW
Interface
MPY32
TA0
TA1
TB0
Timer_A
5 CC
Registers
Timer_A
3 CC
Registers
Timer_B
7 CC
Registers
RTC_A
CRC16
USCI0,
USCI1
ADC12_A
USCI_Ax:
UART,
IrDA, SPI
12 bit
200 ksps
16 channels
(14 ext, 2 int)
Autoscan
USCI_Bx:
SPI, I2C
Copyright © 2016, Texas Instruments Incorporated
Figure 1-2. Functional Block Diagram, MSP430F5437IPN, MSP430F5435IPN, MSP430F5418IPN
Device Overview
Submit Documentation Feedback
Product Folder Links: MSP430F5438 MSP430F5437 MSP430F5436 MSP430F5435 MSP430F5419 MSP430F5418
Copyright © 2009–2018, Texas Instruments Incorporated
3
MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435
MSP430F5419, MSP430F5418
SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
www.ti.com
Table of Contents
Device Overview ......................................... 1
5.26
PMM, SVM Low Side
29
1.1
Features .............................................. 1
5.27
Wake-up Times From Low-Power Modes
30
1.2
Applications ........................................... 1
5.28
1.3
Description ............................................ 2
5.29
1.4
Functional Block Diagrams ........................... 3
5.30
2
3
Revision History ......................................... 5
Device Comparison ..................................... 6
5.31
Related Products ..................................... 6
5.33
4
Terminal Configuration and Functions .............. 7
5.34
4.1
Pin Diagrams ......................................... 7
4.2
Signal Descriptions ................................... 9
5.35
5.36
1
3.1
5
Specifications ........................................... 15
5.1
5.2
5.5
30
30
31
31
31
31
33
34
12-Bit ADC, Power Supply and Input Range
Conditions ........................................... 35
Absolute Maximum Ratings ......................... 15
5.37
12-Bit ADC, External Reference .................... 35
........................................
Recommended Operating Conditions ...............
15
5.38
12-Bit ADC, Built-In Reference...................... 36
15
5.39
12-Bit ADC, Timing Parameters
Active Mode Supply Current Into VCC Excluding
External Current ..................................... 17
Low-Power Mode Supply Currents (Into VCC)
Excluding External Current.......................... 17
5.40
12-Bit ADC, Linearity Parameters................... 37
5.41
12-Bit ADC, Temperature Sensor and Built-In VMID
5.42
Flash Memory ....................................... 39
5.43
JTAG and Spy-Bi-Wire Interface .................... 39
ESD Ratings
5.3
5.4
....................
37
38
5.6
Thermal Resistance Characteristics ................ 17
5.7
Schmitt-Trigger Inputs – General-Purpose I/O...... 18
6.1
CPU
5.8
Inputs – Ports P1 and P2
18
6.2
Operating Modes .................................... 41
5.9
5.10
18
Outputs – General-Purpose I/O (Full Drive
Strength) ............................................ 19
Outputs – General-Purpose I/O (Reduced Drive
Strength) ............................................ 19
6.3
Interrupt Vector Addresses.......................... 42
6.4
Memory Organization ............................... 43
6.5
Bootloader (BSL) .................................... 44
6.6
JTAG Operation ..................................... 44
Output Frequency – General-Purpose I/O .......... 19
Typical Characteristics – Outputs, Reduced Drive
Strength (PxDS.y = 0) ............................... 20
Typical Characteristics – Outputs, Full Drive
Strength (PxDS.y = 1) ............................... 21
6.7
Flash Memory (Link to User's Guide) ............... 45
6.8
RAM (Link to User's Guide) ......................... 45
5.11
5.12
5.13
5.14
...........................
Leakage Current – General-Purpose I/O ...........
.....
....
Crystal Oscillator, XT2 ..............................
5.15
Crystal Oscillator, XT1, Low-Frequency Mode
22
5.16
Crystal Oscillator, XT1, High-Frequency Mode
23
5.17
5.18
24
Internal Very-Low-Power Low-Frequency Oscillator
(VLO) ................................................ 25
Internal Reference, Low-Frequency Oscillator
(REFO) .............................................. 25
5.19
4
5.32
...............................
..........
Timer_A .............................................
Timer_B .............................................
USCI (UART Mode) Clock Frequency ..............
USCI (UART Mode) .................................
USCI (SPI Master Mode) Clock Frequency .........
USCI (SPI Master Mode)............................
USCI (SPI Slave Mode) .............................
USCI (I2C Mode) ....................................
5.20
DCO Frequency ..................................... 26
5.21
PMM, Brownout Reset (BOR)....................... 27
5.22
PMM, Core Voltage ................................. 27
5.23
PMM, SVS High Side ............................... 28
5.24
PMM, SVM High Side ............................... 28
5.25
PMM, SVS Low Side ................................ 29
Table of Contents
6
Detailed Description ................................... 40
8
40
.......................................... 46
6.10 Input/Output Diagrams .............................. 67
6.11 TLV (Device Descriptor) Structures ................. 93
Device and Documentation Support ............... 96
7.1
Getting Started and Next Steps ..................... 96
7.2
Device Nomenclature ............................... 96
7.3
Tools and Software ................................. 98
7.4
Documentation Support ............................ 100
7.5
Related Links ...................................... 101
7.6
Community Resources............................. 101
7.7
Trademarks ........................................ 102
7.8
Electrostatic Discharge Caution ................... 102
7.9
Export Control Notice .............................. 102
7.10 Glossary............................................ 102
6.9
7
.................................................
Peripherals
Mechanical, Packaging, and Orderable
Information ............................................. 102
Copyright © 2009–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5438 MSP430F5437 MSP430F5436 MSP430F5435 MSP430F5419 MSP430F5418
MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435
MSP430F5419, MSP430F5418
www.ti.com
SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from August 26, 2014 to September 20, 2018
•
•
•
•
•
•
•
•
•
•
Page
Added Section 3.1, Related Products ............................................................................................. 6
Added typical conditions statements at the beginning of Section 5, Specifications ........................................ 15
Moved Tstg to Section 5.1, Absolute Maximum Ratings ........................................................................ 15
Added Section 5.2, ESD Ratings.................................................................................................. 15
Updated notes (1) and (2) and added note (3) in Section 5.27,Wake-up Times From Low-Power Modes and
Reset ................................................................................................................................. 30
Removed ADC12DIV from the formula for the TYP value in the second row of the tCONVERT parameter in
Section 5.39, 12-Bit ADC, Timing Parameters, because ADC12CLK is after division ..................................... 37
Throughout document, changed all instances of "bootstrap loader" to "bootloader" ....................................... 44
Corrected spelling of NMIIFG in Table 6-6, System Module Interrupt Vector Registers ................................... 48
Replaced former Tools Support section with Section 7.3, Tools and Software ............................................ 98
Added content to Section 7.4, Documentation Support ...................................................................... 100
Revision History
Submit Documentation Feedback
Product Folder Links: MSP430F5438 MSP430F5437 MSP430F5436 MSP430F5435 MSP430F5419 MSP430F5418
Copyright © 2009–2018, Texas Instruments Incorporated
5
MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435
MSP430F5419, MSP430F5418
SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
www.ti.com
3 Device Comparison
Table 3-1 summarizes the available family members.
Table 3-1. Device Comparison (1) (2)
USCI
(1)
(2)
(3)
(4)
3.1
DEVICE
FLASH
(KB)
SRAM
(KB)
Timer_A (3)
Timer_B (4)
CHANNEL A:
UART, IrDA,
SPI
CHANNEL B:
SPI, I2C
ADC12_A
(Ch)
I/Os
PACKAGE
MSP430F5438
256
16
5, 3
7
4
MSP430F5437
256
16
5, 3
7
2
4
14 ext, 2 int
87
100 PZ
2
14 ext, 2 int
67
MSP430F5436
192
16
5, 3
7
80 PN
4
4
14 ext, 2 int
87
100 PZ
MSP430F5435
192
16
5, 3
MSP430F5419
128
16
5, 3
7
2
2
14 ext, 2 int
67
80 PN
7
4
4
14 ext, 2 int
87
100 PZ
MSP430F5418
128
16
5, 3
7
2
2
14 ext, 2 int
67
80 PN
For the most current package and ordering information, see the Package Option Addendum in Section 8, or see the TI website at
www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
Related Products
For information about other devices in this family of products or related products, see the following links.
Products for TI Microcontrollers TI's low-power and high-performance MCUs, with wired and wireless
connectivity options, are optimized for a broad range of applications.
Products for MSP430 Ultra-Low-Power Microcontrollers One platform. One ecosystem. Endless
possibilities. Enabling the connected world with innovations in ultra-low-power
microcontrollers with advanced peripherals for precise sensing and measurement.
Companion Products for MSP430F5438 Review products that are frequently purchased or used in
conjunction with this product.
TI Reference Designs Find reference designs that leverage the best in TI technology to solve your
system-level challenges
6
Device Comparison
Copyright © 2009–2018, Texas Instruments Incorporated
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435
MSP430F5419, MSP430F5418
www.ti.com
SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
4 Terminal Configuration and Functions
4.1
Pin Diagrams
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
MSP430F5438IPZ
MSP430F5436IPZ
MSP430F5419IPZ
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P9.7
P9.6
P9.5/UCA2RXDUCA2SOMI
P9.4/UCA2TXD/UCA2SIMO
P9.3/UCB2CLK/UCA2STE
P9.2/UCB2SOMI/UCB2SCL
P9.1/UCB2SIMO/UCB2SDA
P9.0/UCB2STE/UCA2CLK
P8.7
P8.6/TA1.1
P8.5/TA1.0
DVCC2
DVSS2
VCORE
P8.4/TA0.4
P8.3/TA0.3
P8.2/TA0.2
P8.1/TA0.1
P8.0/TA0.0
P7.3/TA1.2
P7.2/TB0OUTH/SVMOUT
P5.7/UCA1RXD/UCA1SOMI
P5.6/UCA1TXD/UCA1SIMO
P5.5/UCB1CLK/UCA1STE
P5.4/UCB1SOMI/UCB1SCL
P2.1/TA1.0
P2.2/TA1.1
P2.3/TA1.2
P2.4/RTCCLK
P2.5
P2.6/ACLK
P2.7/ADC12CLK/DMAE0
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
DVSS3
DVCC3
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
P3.6/UCB1STE/UCA1CLK
P3.7/UCB1SIMO/UCB1SDA
P4.0/TB0.0
P4.1/TB0.1
P4.2/TB0.2
P4.3/TB0.3
P4.4/TB0.4
P4.5/TB0.5
P4.6/TB0.6
P4.7/TB0CLK/SMCLK
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7
P7.4/A12
P7.5/A13
P7.6/A14
P7.7/A15
P5.0/A8/VREF+/VeREF+
P5.1/A9/VREF−/VeREF−
AVCC
AVSS
P7.0/XIN
P7.1/XOUT
DVSS1
DVCC1
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
P1.6/SMCLK
P1.7
P2.0/TA1CLK/MCLK
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
P6.3/A3
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK
P5.3/XT2OUT
P5.2/XT2IN
DVSS4
DVCC4
P11.2/SMCLK
P11.1/MCLK
P11.0/ACLK
P10.7
P10.6
P10.5/UCA3RXDUCA3SOMI
P10.4/UCA3TXD/UCA3SIMO
P10.3/UCB3CLK/UCA3STE
P10.2/UCB3SOMI/UCB3SCL
P10.1/UCB3SIMO/UCB3SDA
P10.0/UCB3STE/UCA3CLK
Figure 4-1 shows the pinout for the MSP430F5438, MSP430F5436, and MSP430F5419 devices in the
100-pin PZ package.
Figure 4-1. 100-Pin PZ Package (Top View) – MSP430F5438IPZ, MSP430F5436IPZ, MSP430F5419IPZ
Terminal Configuration and Functions
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Copyright © 2009–2018, Texas Instruments Incorporated
7
MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435
MSP430F5419, MSP430F5418
SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
www.ti.com
P6.3/A3
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCLK
P5.3/XT2OUT
P5.2/XT2IN
DVSS4
DVCC4
P8.6/TA1.1
P8.5/TA1.0
P8.4/TA0.4
P8.3/TA0.3
P8.2/TA0.2
P8.1/TA0.1
Figure 4-2 shows the pinout for the MSP430F5437, MSP430F5435, and MSP430F5418 devices in the 80pin PN package.
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7
P7.4/A12
P7.5/A13
P7.6/A14
P7.7/A15
P5.0/A8/VREF+/VeREF+
P5.1/A9/VREF−/VeREF−
AVCC
AVSS
P7.0/XIN
P7.1/XOUT
DVSS1
DVCC1
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
MSP430F5437IPN
MSP430F5435IPN
MSP430F5418IPN
P8.0/TA0.0
P7.3/TA1.2
P7.2/TB0OUTH/SVMOUT
P5.7/UCA1RXD/UCA1SOMI
P5.6/UCA1TXD/UCA1SIMO
P5.5/UCB1CLK/UCA1STE
P5.4/UCB1SOMI/UCB1SCL
P4.7/TB0CLK/SMCLK
P4.6/TB0.6
DVCC2
DVSS2
VCORE
P4.5/TB0.5
P4.4/TB0.4
P4.3/TB0.3
P4.2/TB0.2
P4.1/TB0.1
P4.0/TB0.0
P3.7/UCB1SIMO/UCB1SDA
P3.6/UCB1STE/UCA1CLK
P1.4/TA0.3
P1.5/TA0.4
P1.6/SMCLK
P1.7
P2.0/TA1CLK/MCLK
P2.1/TA1.0
P2.2/TA1.1
P2.3/TA1.2
P2.4/RTCCLK
DVSS3
DVCC3
P2.5
P2.6/ACLK
P2.7/ADC12CLK/DMAE0
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Figure 4-2. 80-Pin PN Package (Top View) – MSP430F5437IPN, MSP430F5435IPN, MSP430F5418IPN
8
Terminal Configuration and Functions
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4.2
SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
Signal Descriptions
Table 4-1 describes the signals for all device variants and package options.
Table 4-1. Signal Descriptions
TERMINAL
NAME
I/O (1)
NO.
PZ
PN
P6.4/A4
1
1
I/O
P6.5/A5
2
2
I/O
P6.6/A6
3
3
I/O
P6.7/A7
4
4
I/O
P7.4/A12
5
5
I/O
P7.5/A13
6
6
I/O
P7.6/A14
7
7
I/O
P7.7/A15
8
8
I/O
DESCRIPTION
General-purpose digital I/O
Analog input A4 for ADC
General-purpose digital I/O
Analog input A5 for ADC
General-purpose digital I/O
Analog input A6 for ADC
General-purpose digital I/O
Analog input A7 for ADC
General-purpose digital I/O
Analog input A12 for ADC
General-purpose digital I/O
Analog input A13 for ADC
General-purpose digital I/O
Analog input A14 for ADC
General-purpose digital I/O
Analog input A15 for ADC
General-purpose digital I/O
P5.0/A8/VREF+/VeREF+
9
9
I/O
Analog input A8 for ADC
Output of reference voltage to the ADC
Input for an external reference voltage to the ADC
General-purpose digital I/O
Analog input A9 for ADC
P5.1/A9/VREF-/VeREF-
10
10
I/O
Negative terminal for the ADC reference voltage for the internal reference voltage
Negative terminal for the ADC reference voltage for an external applied reference
voltage
AVCC
11
11
Analog power supply
AVSS
12
12
Analog ground supply
P7.0/XIN
13
13
I/O
P7.1/XOUT
14
14
I/O
DVSS1
15
15
Digital ground supply
DVCC1
16
16
Digital power supply
P1.0/TA0CLK/ACLK
17
17
General-purpose digital I/O
Input terminal for crystal oscillator XT1
General-purpose digital I/O
Output terminal of crystal oscillator XT1
General-purpose digital I/O with port interrupt
I/O
TA0 clock signal TACLK input
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
General-purpose digital I/O with port interrupt
P1.1/TA0.0
18
18
I/O
TA0 CCR0 capture: CCI0A input, compare: Out0 output
BSL transmit output
General-purpose digital I/O with port interrupt
P1.2/TA0.1
19
19
I/O
TA0 CCR1 capture: CCI1A input, compare: Out1 output
BSL receive input
(1)
I = input, O = output, N/A = not available on this package offering
Terminal Configuration and Functions
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Table 4-1. Signal Descriptions (continued)
TERMINAL
NAME
I/O (1)
NO.
PZ
PN
P1.3/TA0.2
20
20
I/O
P1.4/TA0.3
21
21
I/O
P1.5/TA0.4
22
22
I/O
P1.6/SMCLK
23
23
I/O
P1.7
24
24
I/O
P2.0/TA1CLK/MCLK
25
25
I/O
DESCRIPTION
General-purpose digital I/O with port interrupt
TA0 CCR2 capture: CCI2A input, compare: Out2 output
General-purpose digital I/O with port interrupt
TA0 CCR3 capture: CCI3A input compare: Out3 output
General-purpose digital I/O with port interrupt
TA0 CCR4 capture: CCI4A input, compare: Out4 output
General-purpose digital I/O with port interrupt
SMCLK output
General-purpose digital I/O with port interrupt
General-purpose digital I/O with port interrupt
TA1 clock signal TA1CLK input
MCLK output
P2.1/TA1.0
26
26
I/O
P2.2/TA1.1
27
27
I/O
P2.3/TA1.2
28
28
I/O
P2.4/RTCCLK
29
29
I/O
P2.5
30
32
I/O
P2.6/ACLK
31
33
I/O
P2.7/ADC12CLK/DMAE0
32
34
I/O
General-purpose digital I/O with port interrupt
TA1 CCR0 capture: CCI0A input, compare: Out0 output
General-purpose digital I/O with port interrupt
TA1 CCR1 capture: CCI1A input, compare: Out1 output
General-purpose digital I/O with port interrupt
TA1 CCR2 capture: CCI2A input, compare: Out2 output
General-purpose digital I/O with port interrupt
RTCCLK output
General-purpose digital I/O with port interrupt
General-purpose digital I/O with port interrupt
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
General-purpose digital I/O with port interrupt
Conversion clock output for ADC
DMA external trigger input
General-purpose digital I/O
P3.0/UCB0STE/UCA0CLK
33
35
I/O
Slave transmit enable – USCI_B0 SPI mode
Clock signal input – USCI_A0 SPI slave mode
Clock signal output – USCI_A0 SPI master mode
General-purpose digital I/O
P3.1/UCB0SIMO/UCB0SDA
34
36
I/O
Slave in, master out – USCI_B0 SPI mode
I2C data – USCI_B0 I2C mode
General-purpose digital I/O
P3.2/UCB0SOMI/UCB0SCL
35
37
I/O
Slave out, master in – USCI_B0 SPI mode
I2C clock – USCI_B0 I2C mode
General-purpose digital I/O
I/O
Clock signal input – USCI_B0 SPI slave mode
P3.3/UCB0CLK/UCA0STE
36
38
DVSS3
37
30
Digital ground supply
DVCC3
38
31
Digital power supply
P3.4/UCA0TXD/UCA0SIMO
39
39
Clock signal output – USCI_B0 SPI master mode
Slave transmit enable – USCI_A0 SPI mode
General-purpose digital I/O
I/O
Transmit data – USCI_A0 UART mode
Slave in, master out – USCI_A0 SPI mode
10
Terminal Configuration and Functions
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SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
Table 4-1. Signal Descriptions (continued)
TERMINAL
NAME
I/O (1)
NO.
PZ
PN
40
40
DESCRIPTION
General-purpose digital I/O
P3.5/UCA0RXD/UCA0SOMI
I/O
Receive data – USCI_A0 UART mode
Slave out, master in – USCI_A0 SPI mode
General-purpose digital I/O
P3.6/UCB1STE/UCA1CLK
41
41
I/O
Slave transmit enable – USCI_B1 SPI mode
Clock signal input – USCI_A1 SPI slave mode
Clock signal output – USCI_A1 SPI master mode
General-purpose digital I/O
P3.7/UCB1SIMO/UCB1SDA
42
42
I/O
Slave in, master out – USCI_B1 SPI mode
I2C data – USCI_B1 I2C mode
P4.0/TB0.0
43
43
I/O
P4.1/TB0.1
44
44
I/O
P4.2/TB0.2
45
45
I/O
P4.3/TB0.3
46
46
I/O
P4.4/TB0.4
47
47
I/O
P4.5/TB0.5
48
48
I/O
P4.6/TB0.6
49
52
I/O
General-purpose digital I/O
TB0 capture CCR0: CCI0A/CCI0B input, compare: Out0 output
General-purpose digital I/O
TB0 capture CCR1: CCI1A/CCI1B input, compare: Out1 output
General-purpose digital I/O
TB0 capture CCR2: CCI2A/CCI2B input, compare: Out2 output
General-purpose digital I/O
TB0 capture CCR3: CCI3A/CCI3B input, compare: Out3 output
General-purpose digital I/O
TB0 capture CCR4: CCI4A/CCI4B input, compare: Out4 output
General-purpose digital I/O
TB0 capture CCR5: CCI5A/CCI5B input, compare: Out5 output
General-purpose digital I/O
TB0 capture CCR6: CCI6A/CCI6B input, compare: Out6 output
General-purpose digital I/O
P4.7/TB0CLK/SMCLK
50
53
I/O
TB0 clock input
SMCLK output
General-purpose digital I/O
P5.4/UCB1SOMI/UCB1SCL
51
54
I/O
Slave out, master in – USCI_B1 SPI mode
I2C clock – USCI_B1 I2C mode
General-purpose digital I/O
P5.5/UCB1CLK/UCA1STE
52
55
I/O
Clock signal input – USCI_B1 SPI slave mode
Clock signal output – USCI_B1 SPI master mode
Slave transmit enable – USCI_A1 SPI mode
General-purpose digital I/O
P5.6/UCA1TXD/UCA1SIMO
53
56
I/O
Transmit data – USCI_A1 UART mode
Slave in, master out – USCI_A1 SPI mode
General-purpose digital I/O
P5.7/UCA1RXD/UCA1SOMI
54
57
I/O
Receive data – USCI_A1 UART mode
Slave out, master in – USCI_A1 SPI mode
General-purpose digital I/O
P7.2/TB0OUTH/SVMOUT
55
58
I/O
Switch all PWM outputs high impedance – Timer TB0
SVM output
P7.3/TA1.2
56
59
I/O
General-purpose digital I/O
TA1 CCR2 capture: CCI2B input, compare: Out2 output
Terminal Configuration and Functions
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Table 4-1. Signal Descriptions (continued)
TERMINAL
NAME
I/O (1)
NO.
DESCRIPTION
PZ
PN
P8.0/TA0.0
57
60
I/O
P8.1/TA0.1
58
61
I/O
P8.2/TA0.2
59
62
I/O
P8.3/TA0.3
60
63
I/O
P8.4/TA0.4
61
64
I/O
VCORE (2)
62
49
Regulated core power supply output (internal use only, no external current loading)
DVSS2
63
50
Digital ground supply
DVCC2
64
51
Digital power supply
P8.5/TA1.0
65
65
I/O
P8.6/TA1.1
66
66
I/O
P8.7
67
N/A
I/O
General-purpose digital I/O
TA0 CCR0 capture: CCI0B input, compare: Out0 output
General-purpose digital I/O
TA0 CCR1 capture: CCI1B input, compare: Out1 output
General-purpose digital I/O
TA0 CCR2 capture: CCI2B input, compare: Out2 output
General-purpose digital I/O
TA0 CCR3 capture: CCI3B input, compare: Out3 output
General-purpose digital I/O
TA0 CCR4 capture: CCI4B input, compare: Out4 output
General-purpose digital I/O
TA1 CCR0 capture: CCI0B input, compare: Out0 output
General-purpose digital I/O
TA1 CCR1 capture: CCI1B input, compare: Out1 output
General-purpose digital I/O
General-purpose digital I/O
P9.0/UCB2STE/UCA2CLK
68
N/A
I/O
Slave transmit enable – USCI_B2 SPI mode
Clock signal input – USCI_A2 SPI slave mode
Clock signal output – USCI_A2 SPI master mode
General-purpose digital I/O
P9.1/UCB2SIMO/UCB2SDA
69
N/A
I/O
Slave in, master out – USCI_B2 SPI mode
I2C data – USCI_B2 I2C mode
General-purpose digital I/O
P9.2/UCB2SOMI/UCB2SCL
70
N/A
I/O
Slave out, master in – USCI_B2 SPI mode
I2C clock – USCI_B2 I2C mode
General-purpose digital I/O
P9.3/UCB2CLK/UCA2STE
71
N/A
I/O
Clock signal input – USCI_B2 SPI slave mode
Clock signal output – USCI_B2 SPI master mode
Slave transmit enable – USCI_A2 SPI mode
General-purpose digital I/O
P9.4/UCA2TXD/UCA2SIMO
72
N/A
I/O
Transmit data – USCI_A2 UART mode
Slave in, master out – USCI_A2 SPI mode
General-purpose digital I/O
P9.5/UCA2RXD/UCA2SOMI
73
N/A
I/O
Receive data – USCI_A2 UART mode
P9.6
74
N/A
I/O
General-purpose digital I/O
P9.7
75
N/A
I/O
General-purpose digital I/O
Slave out, master in – USCI_A2 SPI mode
General-purpose digital I/O
P10.0/UCB3STE/UCA3CLK
76
N/A
I/O
Slave transmit enable – USCI_B3 SPI mode
Clock signal input – USCI_A3 SPI slave mode
Clock signal output – USCI_A3 SPI master mode
(2)
12
VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE.
Terminal Configuration and Functions
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SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
Table 4-1. Signal Descriptions (continued)
TERMINAL
NAME
I/O (1)
NO.
PZ
PN
77
N/A
DESCRIPTION
General-purpose digital I/O
P10.1/UCB3SIMO/UCB3SDA
I/O
Slave in, master out – USCI_B3 SPI mode
I2C data – USCI_B3 I2C mode
General-purpose digital I/O
P10.2/UCB3SOMI/UCB3SCL
78
N/A
I/O
Slave out, master in – USCI_B3 SPI mode
I2C clock – USCI_B3 I2C mode
General-purpose digital I/O
P10.3/UCB3CLK/UCA3STE
79
N/A
I/O
Clock signal input – USCI_B3 SPI slave mode
Clock signal output – USCI_B3 SPI master mode
Slave transmit enable – USCI_A3 SPI mode
General-purpose digital I/O
P10.4/UCA3TXD/UCA3SIMO
80
N/A
I/O
Transmit data – USCI_A3 UART mode
Slave in, master out – USCI_A3 SPI mode
General-purpose digital I/O
P10.5/UCA3RXD/UCA3SOMI
81
N/A
I/O
Receive data – USCI_A3 UART mode
P10.6
82
N/A
I/O
General-purpose digital I/O
P10.7
83
N/A
I/O
General-purpose digital I/O
P11.0/ACLK
84
N/A
I/O
P11.1/MCLK
85
N/A
I/O
P11.2/SMCLK
86
N/A
I/O
DVCC4
87
67
Digital power supply
DVSS4
88
68
Digital ground supply
P5.2/XT2IN
89
69
I/O
P5.3/XT2OUT
90
70
I/O
TEST/SBWTCK (3)
91
71
I
PJ.0/TDO (4)
92
72
I/O
PJ.1/TDI/TCLK (4)
93
73
I/O
PJ.2/TMS (4)
94
74
I/O
PJ.3/TCK (4)
95
75
I/O
RST/NMI/SBWTDIO (3)
96
76
I/O
Slave out, master in – USCI_A3 SPI mode
General-purpose digital I/O
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
General-purpose digital I/O
MCLK output
General-purpose digital I/O
SMCLK output
General-purpose digital I/O
Input terminal for crystal oscillator XT2
General-purpose digital I/O
Output terminal of crystal oscillator XT2
Test mode pin – select digital I/O on JTAG pins
Spy-Bi-Wire input clock
General-purpose digital I/O
Test data output port
General-purpose digital I/O
Test data input or test clock input
General-purpose digital I/O
Test mode select
General-purpose digital I/O
Test clock
Reset input active low
Nonmaskable interrupt input
Spy-Bi-Wire data input/output
(3)
(4)
See Section 6.5 and Section 6.6 for use with BSL and JTAG functions
See Section 6.6 for use with JTAG function.
Terminal Configuration and Functions
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Table 4-1. Signal Descriptions (continued)
TERMINAL
NAME
I/O (1)
NO.
PZ
PN
P6.0/A0
97
77
I/O
P6.1/A1
98
78
I/O
P6.2/A2
99
79
I/O
P6.3/A3
100
80
I/O
Reserved
N/A
N/A
14
Terminal Configuration and Functions
DESCRIPTION
General-purpose digital I/O
Analog input A0 for ADC
General-purpose digital I/O
Analog input A1 for ADC
General-purpose digital I/O
Analog input A2 for ADC
General-purpose digital I/O
Analog input A3 for ADC
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5 Specifications
All graphs in this section are for typical conditions, unless otherwise noted.
Typical (TYP) values are specified at VCC = 3.3 V and TA = 25°C, unless otherwise noted.
5.1
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Voltage VCC applied at supply pins DVCC or AVCC to supply pins DVSS or AVSS
Voltage applied to any pin (excluding VCORE)
(2)
MIN
MAX
–0.3
4.1
–0.3
VCC + 0.3
Diode current at any device pin
(1)
(2)
(3)
(3)
–55
V
V
±2
mA
95
°C
150
°C
Maximum operating junction temperature, TJ
Storage temperature, Tstg
UNIT
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS. VCORE is for internal device use only. No external dc loading or voltage should be applied.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2
ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
5.3
Recommended Operating Conditions
MIN
NOM
MAX
VCC
Supply voltage during program execution and flash programming
(VCC = DVCC1 = DVCC2 = DVCC3 = DVCC4 = AVCC) (1) (2)
VSS
Supply voltage (VSS = DVSS1 = DVSS2 = DVSS3 = DVSS4 = DVSS= AVSS)
TA
Operating free-air temperature
I version
–40
85
TJ
Operating junction temperature
I version
–40
85
CVCORE
Recommended capacitor at VCORE (3)
CDVCC/
CVCORE
Capacitor ratio of DVCC to VCORE
fSYSTEM
(1)
(2)
(3)
(4)
(5)
Processor frequency (maximum MCLK frequency)
(see Figure 5-1)
2.2
3.6
0
UNIT
V
V
470
°C
°C
nF
10
(4) (5)
PMMCOREVx = 2,
2.2 V ≤ VCC ≤ 3.6 V
0
18
MHz
TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the Section 5.23 threshold parameters for
the exact values and further details.
A capacitor tolerance of ±20% or better is required.
The MSP430 CPU is clocked directly with MCLK. Both the high and low phases of MCLK must not exceed the pulse duration of the
specified maximum frequency.
Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Specifications
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System Frequency - MHz
3
18
2
0
2.2
3.6
Supply Voltage - V
The numbers within the fields denote the supported PMMCOREVx settings.
Figure 5-1. Frequency vs Supply Voltage
16
Specifications
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5.4
SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted) (1)
(2) (3)
FREQUENCY (fDCO = fMCLK = fSMCLK)
PARAMETER
IAM,
IAM,
(1)
(2)
(3)
EXECUTION
MEMORY
VCC
PMMCOREVx
1 MHz
4 MHz
8 MHz
16 MHz
MAX
TYP
MAX
TYP
MAX
TYP
MAX
Flash
Flash
3.0 V
2
0.37
0.45
1.27
1.47
2.50
2.84
5.00
5.56
mA
RAM
RAM
3.0 V
2
0.20
0.29
0.60
0.72
1.12
1.27
2.20
2.60
mA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
Characterized with program executing worst case JMP $.
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0.
5.5
Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
VCC
PMMCOREVx
3.0 V
(4)
ILPM3,XT1LF
ILPM3,VLO
ILPM0,1MHz
ILPM4
(3)
(4)
(5)
(6)
(7)
(8)
5.6
–40°C
25°C
55°C
(2)
85°C
MAX
TYP
MAX
TYP
MAX
TYP
MAX
2
86
98
86
98
86
98
86
98
µA
3.0 V
2
8.0
15.6
8.0
15.6
8.0
15.6
8.0
15.6
µA
Low-power mode 3,
crystal mode (6) (4)
3.0 V
2
2.3
2.6
3.37
4.5
7.9
15.6
µA
Low-power mode 3,
VLO mode (7) (4)
3.0 V
2
1.39
1.80
2.30
2.95
6.9
14.6
µA
3.0 V
2
1.26
1.69
2.2
3.6
6.8
14.5
µA
Low-power mode 0 (3)
(4)
(5)
Low-power mode 4 (8)
(4)
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz
Current for brownout included. High and low-side supervisor and monitors disabled (SVSH, SVMH, SVSL, SVML). RAM retention
enabled.
Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz, DCO setting = 1
MHz operation, DCO bias generator enabled.
Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
Current for watchdog timer and RTC clocked by ACLK included. For this condition, the VLO must be selected as the source for ACLK,
MCLK, and SMCLK otherwise additional current will be drawn due to the REFO oscillator. ACLK = MCLK = SMCLK = VLO.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = fVLO, fMCLK = fSMCLK = fVLO = 0 MHz
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
Thermal Resistance Characteristics
VALUE
Low-K board (JESD51-3)
θJA
Junction-to-ambient thermal resistance, still air
High-K board (JESD51-7)
θJC
UNIT
TYP
Low-power mode 2
ILPM2
(1)
(2)
UNIT
TYP
Junction-to-case thermal resistance
LQFP (PZ)
50.1
LQFP (PN)
57.9
LQFP (PZ)
40.8
LQFP (PN)
37.9
LQFP (PZ)
8.9
LQFP (PN)
10.3
Specifications
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UNIT
°C/W
°C/W
17
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Schmitt-Trigger Inputs – General-Purpose I/O (1)
5.7
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup or pulldown resistor (2)
For pullup: VIN = VSS
For pulldown: VIN = VCC
CI
Input capacitance
VIN = VSS or VCC
(1)
(2)
VCC
MIN
1.8 V
0.80
1.40
3V
1.50
2.10
1.8 V
0.45
1.00
3V
0.75
1.65
1.8 V
0.3
0.8
3V
0.4
1.0
20
TYP
35
MAX
UNIT
V
V
V
50
kΩ
5
pF
Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).
Also applies to RST pin when pullup or pulldown resistor is enabled.
Inputs – Ports P1 and P2 (1)
5.8
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
t(int)
(1)
(2)
PARAMETER
TEST CONDITIONS
VCC
External interrupt timing (2)
Port P1, P2: P1.x to P2.x, External trigger pulse duration
to set interrupt flag
2.2 V, 3 V
MIN
MAX
UNIT
20
ns
Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int).
5.9
Leakage Current – General-Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Px.x)
(1)
(2)
18
High-impedance leakage current
TEST CONDITIONS
See
(1) (2)
VCC
1.8 V, 3 V
MIN
MAX
UNIT
±50
nA
The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
Specifications
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SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
5.10 Outputs – General-Purpose I/O (Full Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-6,
Figure 5-7, Figure 5-8, and Figure 5-9)
PARAMETER
TEST CONDITIONS
I(OHmax) = –3 mA (1)
VOH
I(OHmax) = –10 mA (2)
High-level output voltage
I(OHmax) = –5 mA (1)
I(OHmax) = –15 mA (2)
I(OLmax) = 3 mA (1)
VOL
I(OLmax) = 5 mA (1)
(2)
3V
MAX
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.60
VCC
VSS
VSS + 0.25
VSS
VSS + 0.60
VSS
VSS + 0.25
VSS
VSS + 0.60
3V
I(OLmax) = 15 mA (2)
(1)
1.8 V
MIN
VCC – 0.25
1.8 V
I(OLmax) = 10 mA (2)
Low-level output voltage
VCC
UNIT
V
V
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
5.11 Outputs – General-Purpose I/O (Reduced Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (see Figure 5-2,
Figure 5-3, Figure 5-4, and Figure 5-5)
PARAMETER
TEST CONDITIONS
I(OHmax) = –1 mA
VOH
1.8 V
I(OHmax) = –3 mA (3)
High-level output voltage
I(OHmax) = –2 mA (2)
3.0 V
I(OHmax) = –6 mA (3)
I(OLmax) = 1 mA
VOL
(3)
MAX
VCC – 0.25
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.60
VCC
VSS
VSS + 0.25
VSS
VSS + 0.60
VSS
VSS + 0.25
VSS
VSS + 0.60
1.8 V
I(OLmax) = 2 mA (2)
3.0 V
I(OLmax) = 6 mA (3)
(1)
(2)
MIN
(2)
I(OLmax) = 3 mA (3)
Low-level output voltage
VCC
(2)
UNIT
V
V
Selecting reduced drive strength may reduce EMI.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage
drop specified.
5.12 Output Frequency – General-Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fPx.y
Port output frequency
(with load)
fPort_CLK
Clock output frequency
(1)
(2)
TEST CONDITIONS
MAX
UNIT
(1) (2)
VCC = 3 V
PMMCOREVx = 2
25
MHz
P1.0/TA0CLK/ACLK,
P1.6/SMCLK,
P2.0/TA1CLK/MCLK,
CL = 20 pF (2)
VCC = 3 V
PMMCOREVx = 2
25
MHz
P1.6/SMCLK
MIN
A resistive divider with 2 × R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For full
drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
Specifications
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5.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
8.0
VCC = 3.0 V
Px.y
IOL – Typical Low-Level Output Current – mA
IOL – Typical Low-Level Output Current – mA
25.0
TA = 25°C
20.0
TA = 85°C
15.0
10.0
5.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
IOH – Typical High-Level Output Current – mA
IOH – Typical High-Level Output Current – mA
−5.0
−10.0
TA = 85°C
TA = 25°C
0.5
1.0
1.5
2.0
2.5
3.0
VOH – High-Level Output Voltage – V
Figure 5-4. Typical High-Level Output Current vs
High-Level Output Voltage
20
4.0
3.0
2.0
1.0
0.5
1.0
1.5
2.0
0.0
VCC = 3.0 V
Px.y
−25.0
0.0
5.0
VOL – Low-Level Output Voltage – V
Figure 5-3. Typical Low-Level Output Current vs
Low-Level Output Voltage
0.0
−20.0
TA = 85°C
6.0
0.0
0.0
3.5
VOL – Low-Level Output Voltage – V
Figure 5-2. Typical Low-Level Output Current vs
Low-Level Output Voltage
−15.0
7.0
TA = 25°C
VCC = 1.8 V
Px.y
Specifications
3.5
−1.0
VCC = 1.8 V
Px.y
−2.0
−3.0
−4.0
−5.0
−6.0
TA = 85°C
TA = 25°C
−7.0
−8.0
0.0
0.5
1.0
1.5
VOH – High-Level Output Voltage – V
Figure 5-5. Typical High-Level Output Current vs
High-Level Output Voltage
2.0
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5.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
55.0
24
TA = 25°C
VCC = 3.0 V
Px.y
50.0
IOL – Typical Low-Level Output Current – mA
IOL – Typical Low-Level Output Current – mA
60.0
TA = 85°C
45.0
40.0
35.0
30.0
25.0
20.0
15.0
10.0
TA = 25°C
20
TA = 85°C
16
12
8
4
5.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.0
3.5
IOH – Typical High-Level Output Current – mA
VCC = 3.0 V
Px.y
−10.0
−15.0
−20.0
−25.0
−30.0
−35.0
−40.0
−45.0
−50.0
TA = 85°C
−55.0
−60.0
0.0
1.0
1.5
2.0
0
0.0
−5.0
0.5
VOL – Low-Level Output Voltage – V
Figure 5-7. Typical Low-Level Output Current vs
Low-Level Output Voltage
VOL – Low-Level Output Voltage – V
Figure 5-6. Typical Low-Level Output Current vs
Low-Level Output Voltage
IOH – Typical High-Level Output Current – mA
VCC = 1.8 V
Px.y
TA = 25°C
0.5
1.0
1.5
2.0
2.5
3.0
VOH – High-Level Output Voltage – V
Figure 5-8. Typical High-Level Output Current vs
High-Level Output Voltage
3.5
VCC = 1.8 V
Px.y
−4
−8
−12
TA = 85°C
−16
TA = 25°C
−20
0.0
0.5
1.0
1.5
VOH – High-Level Output Voltage – V
Figure 5-9. Typical High-Level Output Current vs
High-Level Output Voltage
Specifications
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2.0
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5.15 Crystal Oscillator, XT1, Low-Frequency Mode (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
TA = 25°C
ΔIDVCC.LF
Differential XT1 oscillator crystal
current consumption from lowest
drive setting, LF mode
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 2,
TA = 25°C
0.170
32768
XTS = 0, XT1BYPASS = 0
fXT1,LF,SW
XT1 oscillator logic-level squarewave input frequency, LF mode
XTS = 0, XT1BYPASS = 1 (2)
OALF
3.0 V
0.290
XT1 oscillator crystal frequency,
LF mode
(3)
10
CL,eff
fFault,LF
tSTART,LF
210
XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,LF = 32768 Hz, CL,eff = 12 pF
300
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
22
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
12.0
Oscillator fault frequency,
LF mode (7)
XTS = 0 (8)
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
TA = 25°C, CL,eff = 6 pF
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C, CL,eff = 12 pF
µA
Hz
50
kHz
1
5.5
Duty cycle, LF mode
UNIT
kΩ
XTS = 0, XCAPx = 1
XTS = 0, Measured at ACLK,
fXT1,LF = 32768 Hz
Start-up time, LF mode
32.768
XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,LF = 32768 Hz, CL,eff = 6 pF
XTS = 0, XCAPx = 0 (6)
Integrated effective load
capacitance, LF mode (5)
MAX
0.075
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C
fXT1,LF0
Oscillation allowance for
LF crystals (4)
TYP
pF
30%
70%
10
10000
Hz
1000
3.0 V
ms
500
To improve EMI on the XT1 oscillator, the following guidelines should be observed.
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-Trigger Inputs section of this data sheet.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
• For XT1DRIVEx = 0, CL,eff ≤ 6 pF.
• For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF.
• For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF.
• For XT1DRIVEx = 3, CL,eff ≥ 6 pF.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, the
effective load capacitance should always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies that are between MIN and MAX might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Specifications
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5.16 Crystal Oscillator, XT1, High-Frequency Mode (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IDVCC.HF
XT1 oscillator crystal current HF
mode
TEST CONDITIONS
VCC
MIN
TYP
fOSC = 4 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
TA = 25°C
200
fOSC = 12 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
TA = 25°C
260
fOSC = 20 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVEx = 2,
TA = 25°C
MAX
3.0 V
UNIT
µA
325
fOSC = 32 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C
450
fXT1,HF0
XT1 oscillator crystal frequency,
HF mode 0
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 0 (2)
4
8
MHz
fXT1,HF1
XT1 oscillator crystal frequency,
HF mode 1
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 1 (2)
8
16
MHz
fXT1,HF2
XT1 oscillator crystal frequency,
HF mode 2
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 2 (2)
16
24
MHz
fXT1,HF3
XT1 oscillator crystal frequency,
HF mode 3
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 3 (2)
24
32
MHz
fXT1,HF,SW
XT1 oscillator logic-level squarewave input frequency, HF mode,
bypass mode
XTS = 1,
XT1BYPASS = 1 (3)
1.5
32
MHz
OAHF
tSTART,HF
(1)
(2)
(3)
(4)
Oscillation allowance for
HF crystals (4)
Start-up time, HF mode
(2)
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,HF = 6 MHz, CL,eff = 15 pF
450
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,HF = 12 MHz, CL,eff = 15 pF
320
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 2,
fXT1,HF = 20 MHz, CL,eff = 15 pF
200
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 3,
fXT1,HF = 32 MHz, CL,eff = 15 pF
200
fOSC = 6 MHz, XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 0,
TA = 25°C, CL,eff = 15 pF
0.5
fOSC = 20 MHz, XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 2,
TA = 25°C, CL,eff = 15 pF
Ω
3.0 V
ms
0.3
To improve EMI on the XT1 oscillator the following guidelines should be observed.
• Keep the traces between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
This represents the maximum frequency that can be input to the device externally. Maximum frequency achievable on the device
operation is based on the frequencies present on ACLK, MCLK, and SMCLK cannot be exceed for a given range of operation.
When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-Trigger Inputs section of this data sheet.
Oscillation allowance is based on a safety factor of 5 for recommended crystals.
Specifications
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Crystal Oscillator, XT1, High-Frequency Mode(1) (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Integrated effective load
capacitance, HF mode (5)
CL,eff
fFault,HF
(5)
(6)
(7)
(8)
TEST CONDITIONS
(6)
VCC
MIN
XTS = 1
TYP
MAX
UNIT
1
Duty cycle, HF mode
XTS = 1, Measured at ACLK,
fXT1,HF2 = 20 MHz
Oscillator fault frequency,
HF mode (7)
XTS = 1 (8)
40%
50%
30
pF
60%
300
kHz
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, the
effective load capacitance should always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies that are between MIN and MAX might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
5.17 Crystal Oscillator, XT2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
IDVCC.XT2
XT2 oscillator crystal current
consumption
TEST CONDITIONS
VCC
MIN
(2)
TYP
fOSC = 4 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 0,
TA = 25°C
200
fOSC = 12 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 1,
TA = 25°C
260
fOSC = 20 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 2,
TA = 25°C
MAX
3.0 V
UNIT
µA
325
fOSC = 32 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 3,
TA = 25°C
450
fXT2,HF0
XT2 oscillator crystal frequency,
mode 0
XT2DRIVEx = 0, XT2BYPASS = 0 (3)
4
8
MHz
fXT2,HF1
XT2 oscillator crystal frequency,
mode 1
XT2DRIVEx = 1, XT2BYPASS = 0 (3)
8
16
MHz
fXT2,HF2
XT2 oscillator crystal frequency,
mode 2
XT2DRIVEx = 2, XT2BYPASS = 0 (3)
16
24
MHz
fXT2,HF3
XT2 oscillator crystal frequency,
mode 3
XT2DRIVEx = 3, XT2BYPASS = 0 (3)
24
32
MHz
fXT2,HF,SW
XT2 oscillator logic-level squarewave input frequency, bypass
mode
XT2BYPASS = 1 (4)
1.5
32
MHz
(1)
(2)
(3)
(4)
24
(3)
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
To improve EMI on the XT2 oscillator the following guidelines should be observed.
• Keep the traces between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.
• Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
This represents the maximum frequency that can be input to the device externally. Maximum frequency achievable on the device
operation is based on the frequencies present on ACLK, MCLK, and SMCLK cannot be exceed for a given range of operation.
When XT2BYPASS is set, the XT2 circuit is automatically powered down. Input signal is a digital square wave with parametrics defined
in the Schmitt-Trigger Inputs section of this datasheet.
Specifications
Copyright © 2009–2018, Texas Instruments Incorporated
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SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
Crystal Oscillator, XT2 (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
PARAMETER
TEST CONDITIONS
Oscillation allowance for
HF crystals (5)
OAHF
tSTART,HF
Integrated effective load
capacitance, HF mode (6)
fFault,HF
(7)
(8)
Oscillator fault frequency
TYP
XT2DRIVEx = 1, XT2BYPASS = 0,
fXT2,HF1 = 12 MHz, CL,eff = 15 pF
320
XT2DRIVEx = 2, XT2BYPASS = 0,
fXT2,HF2 = 20 MHz, CL,eff = 15 pF
200
XT2DRIVEx = 3, XT2BYPASS = 0,
fXT2,HF3 = 32 MHz, CL,eff = 15 pF
200
UNIT
0.5
3.0 V
ms
0.3
1
(1)
Measured at ACLK, fXT2,HF2 = 20 MHz
(7)
MAX
Ω
fOSC = 20 MHz,
XT2BYPASS = 0, XT2DRIVEx = 2,
TA = 25°C, CL,eff = 15 pF
Duty cycle
(5)
(6)
MIN
450
fOSC = 6 MHz,
XT2BYPASS = 0, XT2DRIVEx = 0,
TA = 25°C, CL,eff = 15 pF
Start-up time
CL,eff
VCC
XT2DRIVEx = 0, XT2BYPASS = 0,
fXT2,HF0 = 6 MHz, CL,eff = 15 pF
XT2BYPASS = 1
40%
(8)
pF
50%
60%
30
300
kHz
Oscillation allowance is based on a safety factor of 5 for recommended crystals.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, the
effective load capacitance should always match the specification of the used crystal.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies that are between MIN and MAX might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
5.18 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
6
9.4
14
UNIT
fVLO
VLO frequency
Measured at ACLK
1.8 V to 3.6 V
dfVLO/dT
VLO frequency temperature drift
Measured at ACLK (1)
1.8 V to 3.6 V
0.5
%/°C
Measured at ACLK (2)
1.8 V to 3.6 V
4
%/V
Measured at ACLK
1.8 V to 3.6 V
dfVLO/dVCC VLO frequency supply voltage drift
Duty cycle
(1)
(2)
40%
50%
kHz
60%
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
5.19 Internal Reference, Low-Frequency Oscillator (REFO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
IREFO
REFO oscillator current
consumption
TA = 25°C
1.8 V to 3.6 V
3
µA
fREFO
REFO frequency calibrated
Measured at ACLK
1.8 V to 3.6 V
32768
Hz
Full temperature range
1.8 V to 3.6 V
REFO absolute tolerance calibrated
TA = 25°C
±3.5%
3V
±1.5%
dfREFO/dT
REFO frequency temperature drift
Measured at ACLK (1)
1.8 V to 3.6 V
0.01
%/°C
dfREFO/dVCC
REFO frequency supply voltage
drift
Measured at ACLK (2)
1.8 V to 3.6 V
1.0
%/V
Duty cycle
Measured at ACLK
1.8 V to 3.6 V
REFO startup time
40%/60% duty cycle
1.8 V to 3.6 V
tSTART
(1)
(2)
40%
50%
60%
25
µs
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
Specifications
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435
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5.20 DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(1)
MIN
TYP
MAX
UNIT
fDCO(0,0)
DCO frequency (0, 0)
DCORSELx = 0, DCOx = 0, MODx = 0
0.07
0.20
MHz
fDCO(0,31)
DCO frequency (0, 31) (1)
DCORSELx = 0, DCOx = 31, MODx = 0
0.70
1.70
MHz
fDCO(1,0)
DCO frequency (1, 0) (1)
DCORSELx = 1, DCOx = 0, MODx = 0
0.15
0.36
MHz
fDCO(1,31)
DCO frequency (1, 31) (1)
DCORSELx = 1, DCOx = 31, MODx = 0
1.47
3.45
MHz
(1)
fDCO(2,0)
DCO frequency (2, 0)
DCORSELx = 2, DCOx = 0, MODx = 0
0.32
0.75
MHz
fDCO(2,31)
DCO frequency (2, 31) (1)
DCORSELx = 2, DCOx = 31, MODx = 0
3.17
7.38
MHz
fDCO(3,0)
DCO frequency (3, 0) (1)
DCORSELx = 3, DCOx = 0, MODx = 0
0.64
1.51
MHz
(1)
fDCO(3,31)
DCO frequency (3, 31)
DCORSELx = 3, DCOx = 31, MODx = 0
6.07
14.0
MHz
fDCO(4,0)
DCO frequency (4, 0) (1)
DCORSELx = 4, DCOx = 0, MODx = 0
1.3
3.2
MHz
fDCO(4,31)
DCO frequency (4, 31) (1)
DCORSELx = 4, DCOx = 31, MODx = 0
12.3
28.2
MHz
(1)
fDCO(5,0)
DCO frequency (5, 0)
DCORSELx = 5, DCOx = 0, MODx = 0
2.5
6.0
MHz
fDCO(5,31)
DCO frequency (5, 31) (1)
DCORSELx = 5, DCOx = 31, MODx = 0
23.7
54.1
MHz
fDCO(6,0)
DCO frequency (6, 0) (1)
DCORSELx = 6, DCOx = 0, MODx = 0
4.6
10.7
MHz
fDCO(6,31)
DCO frequency (6, 31) (1)
DCORSELx = 6, DCOx = 31, MODx = 0
39.0
88.0
MHz
(1)
fDCO(7,0)
DCO frequency (7, 0)
DCORSELx = 7, DCOx = 0, MODx = 0
8.5
19.6
MHz
fDCO(7,31)
DCO frequency (7, 31) (1)
DCORSELx = 7, DCOx = 31, MODx = 0
60
135
MHz
SDCORSEL
Frequency step between range
DCORSEL and DCORSEL + 1
SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO)
1.2
2.3
ratio
SDCO
Frequency step between tap DCO
and DCO + 1
SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO)
1.02
1.12
ratio
Duty cycle
Measured at SMCLK
40%
dfDCO/dT
DCO frequency temperature drift
dfDCO/dVCC
DCO frequency voltage drift (3)
(1)
(2)
(3)
(2)
50%
60%
fDCO = 1 MHz
0.1
%/°C
fDCO = 1 MHz
1.9
%/V
When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within the
range of fDCO(n, 0),MAX ≤ fDCO ≤ fDCO(n, 31),MIN, where fDCO(n, 0),MAX represents the maximum frequency specified for the DCO frequency,
range n, tap 0 (DCOx = 0) and fDCO(n,31),MIN represents the minimum frequency specified for the DCO frequency, range n, tap 31
(DCOx = 31). This makes sure that the target DCO frequency resides within the range selected. It should also be noted that if the actual
fDCO frequency for the selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the
selected range is at its minimum or maximum tap setting.
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(2.2 V to 3.6 V) – MIN(2.2 V to 3.6 V)) / MIN(2.2 V to 3.6 V) / (3.6 V – 2.2 V)
100
VCC = 3.0 V
TA = 25°C
fDCO – MHz
10
DCOx = 31
1
0.1
DCOx = 0
0
1
2
3
4
5
6
7
DCORSEL
Figure 5-10. Typical DCO Frequency
26
Specifications
Copyright © 2009–2018, Texas Instruments Incorporated
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SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
5.21 PMM, Brownout Reset (BOR)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V(DVCC_BOR_IT–)
BORH on voltage, DVCC falling level
| dDVCC/dt | < 3 V/s
V(DVCC_BOR_IT+)
BORH off voltage, DVCC rising level
| dDVCC/dt | < 3 V/s
V(DVCC_BOR_hys)
BORH hysteresis
V(VCORE_BOR_IT–)
BORL on voltage, VCORE falling level
V(VCORE_BOR_IT+)
BORL off voltage, VCORE rising level
V(VCORE_BOR_hys)
BORL hysteresis
tRESET
Pulse duration required at RST/NMI pin to
accept a reset
MIN
TYP
0.80
1.30
MAX
UNIT
1.55
V
1.65
V
100
250
mV
DVCC = 1.8 V to 3.6 V
0.69
0.83
V
DVCC = 1.8 V to 3.6 V
0.83
1.05
V
70
200
mV
2
µs
5.22 PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCORE2(AM)
Core voltage, active mode,
PMMCOREV = 2
VCORE2(LPM)
Core voltage, low-current
mode, PMMCOREV = 2
PSRR(DC,AM)
Power-supply rejection
ratio, active mode
PSRR(DC,LPM)
Power-supply rejection
ratio, low-current mode
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.2 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 21 mA
1.60
1.81
1.89
V
2.2 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA
1.68
1.89
1.98
V
DVCC = 2.2 V or 3.6 V, I(VCORE) = 0 mA,
PMMCOREV = 2
60
DVCC = 2.2 V or 3.6 V, I(VCORE) = 21 mA,
PMMCOREV = 2
60
DVCC = 2.2 V or 3.6 V, I(VCORE) = 0 mA,
PMMCOREV = 2
50
DVCC = 2.4 V or 3.6 V, I(VCORE) = 30 µA,
PMMCOREV = 2
50
dB
dB
Specifications
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5.23 PMM, SVS High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVSHE = 0, DVCC = 3.6 V
I(SVSH)
SVS current consumption
V(SVSH_IT+)
tpd(SVSH)
t(SVSH)
SVSH on voltage level
SVSH off voltage level
SVSH propagation delay
SVSH on or off delay time
dVDVCC/dt
MAX
0
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0
2.0
µA
SVSHE = 1, SVSHRVL = 0
1.59
1.64
1.69
SVSHE = 1, SVSHRVL = 1
1.79
1.84
1.91
SVSHE = 1, SVSHRVL = 2
1.98
2.04
2.11
SVSHE = 1, SVSHRVL = 3
2.10
2.16
2.23
SVSHE = 1, SVSMHRRL = 0
1.62
1.74
1.81
SVSHE = 1, SVSMHRRL = 1
1.88
1.94
2.01
SVSHE = 1, SVSMHRRL = 2
2.07
2.14
2.21
SVSHE = 1, SVSMHRRL = 3
2.20
2.26
2.33
SVSHE = 1, SVSMHRRL = 4
2.40
SVSHE = 1, SVSMHRRL = 5
2.70
SVSHE = 1, SVSMHRRL = 6
3.00
SVSHE = 1, SVSMHRRL = 7
3.00
SVSHE = 1, dVDVCC/dt = 10 mV/µs,
SVSHFP = 1
2.5
SVSHE = 1, dVDVCC/dt = 1 mV/µs,
SVSHFP = 0
20
UNIT
nA
200
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1
V(SVSH_IT–)
TYP
V
V
µs
SVSHE = 0 → 1, dVDVCC/dt = 10 mV/µs,
SVSHFP = 1
12.5
SVSHE = 0 → 1, dVDVCC/dt = 1 mV/µs,
SVSHFP = 0
100
DVCC rise time
µs
0
1000
V/s
MAX
UNIT
5.24 PMM, SVM High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVMHE = 0, DVCC = 3.6 V
I(SVMH)
SVMH current consumption
0
SVMHE= 1, DVCC = 3.6 V, SVMHFP = 0
SVMH on or off voltage level
tpd(SVMH)
SVMH propagation delay
t(SVMH)
SVMH on or off delay time
28
Specifications
nA
200
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1
V(SVMH)
TYP
2.0
µA
SVMHE = 1, SVSMHRRL = 0
1.65
1.74
1.86
SVMHE = 1, SVSMHRRL = 1
1.85
1.94
2.02
SVMHE = 1, SVSMHRRL = 2
2.02
2.14
2.22
SVMHE = 1, SVSMHRRL = 3
2.18
2.26
2.35
SVMHE = 1, SVSMHRRL = 4
2.40
SVMHE = 1, SVSMHRRL = 5
2.70
SVMHE = 1, SVSMHRRL = 6
3.00
SVMHE = 1, SVSMHRRL = 7
3.00
SVMHE = 1, SVMHOVPE = 1
3.75
SVMHE = 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1
2.5
SVMHE = 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0
20
SVMHE = 0 → 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1
12.5
SVMHE = 0 → 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0
100
V
µs
µs
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SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
5.25 PMM, SVS Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVSLE = 0, PMMCOREV = 2
I(SVSL)
SVSL current consumption
SVSL on voltage level
V(SVSL_IT+)
SVSL off voltage level
V(SVSL_HYS)
SVSL hysteresis
tpd(SVSL)
SVSL propagation delay
t(SVSL)
SVSL on or off delay time
MAX
0
SVSLE = 1, PMMCOREV = 2, SVSLFP = 0
2.0
µA
SVSLE = 1, SVSLRVL = 0
1.20
1.27
1.32
SVSLE = 1, SVSLRVL = 1
1.39
1.47
1.52
SVSLE = 1, SVSLRVL = 2
1.60
1.67
1.72
SVSLE = 1, SVSLRVL = 3
1.70
1.77
1.82
SVSLE = 1, SVSMLRRL = 0
1.29
1.34
1.39
SVSLE = 1, SVSMLRRL = 1
1.49
1.54
1.59
SVSLE = 1, SVSMLRRL = 2
1.69
1.74
1.79
SVSLE = 1, SVSMLRRL = 3, 4, 5, 6, 7
1.79
1.84
1.89
SVSLE = 1, SVSMLRRL = 0
70
SVSLE = 1, SVSMLRRL = 1
70
SVSLE = 1, SVSMLRRL = 2
70
SVSLE = 1, SVSMLRRL = 3
70
SVSLE = 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1
2.5
SVSLE = 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0
20
SVSLE = 0 → 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1
12.5
SVSLE = 0 → 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0
100
UNIT
nA
200
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1
V(SVSL_IT–)
TYP
V
V
mV
µs
µs
5.26 PMM, SVM Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVMLE = 0, PMMCOREV = 2
I(SVML)
V(SVML)
SVML current consumption
SVML on or off voltage level
SVML propagation delay
t(SVML)
SVML on or off delay time
MAX
0
SVMLE= 1, PMMCOREV = 2, SVMLFP = 0
200
SVMLE= 1, PMMCOREV = 2, SVMLFP = 1
2.0
µA
1.28
1.34
1.40
SVMLE = 1, SVSMLRRL = 1
1.49
1.54
1.60
SVMLE = 1, SVSMLRRL = 2
1.68
1.74
1.79
SVMLE = 1, SVSMLRRL = 3, 4, 5, 6, 7
1.76
1.84
1.90
V
2.02
SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1
2.5
SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0
20
SVMLE = 0 → 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1
12.5
SVMLE = 0 → 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0
100
Specifications
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UNIT
nA
SVMLE = 1, SVSMLRRL = 0
SVMLE = 1, SVSMLOVPE = 1
tpd(SVML)
TYP
µs
µs
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5.27 Wake-up Times From Low-Power Modes
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
tWAKE-UP-FAST
Wake-up time from LPM2, LPM3, or
LPM4 to active mode (1)
PMMCOREV = SVSMLRRL = 2,
SVSLFP = 1
2.2 V, 3 V
tWAKE-UP-SLOW
Wake-up time from LPM2, LPM3, or
LPM4 to active mode (2) (3)
PMMCOREV = SVSMLRRL = 2,
SVSLFP = 0
2.2 V, 3 V
(1)
(2)
(3)
MIN
TYP MAX
5
150
UNIT
µs
µs
This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance
mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-FAST is possible with SVSL and SVML in full performance
mode or disabled. For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode Selection section in
the Power Management Module and Supply Voltage Supervisor chapter of the MSP430F5xx and MSP430F6xx Family User's Guide.
This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance
mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-SLOW is set with SVSL and SVML in normal mode (low
current mode). For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode Selection section in the
Power Management Module and Supply Voltage Supervisor chapter of the MSP430F5xx and MSP430F6xx Family User's Guide.
The wake-up times from LPM0 and LPM1 to AM are not specified. They are proportional to MCLK cycle time but are not affected by the
performance mode settings as for LPM2, LPM3, and LPM4.
5.28 Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTA
Timer_A input clock frequency
Internal: SMCLK or ACLK,
External: TACLK,
Duty cycle = 50% ±10%
tTA,cap
Timer_A capture timing
All capture inputs, minimum pulse duration
required for capture
VCC
1.8 V, 3 V
1.8 V, 3 V
MIN
MAX
UNIT
25
MHz
20
ns
5.29 Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
fTB
Timer_B input clock frequency
Internal: SMCLK or ACLK,
External: TBCLK,
Duty cycle = 50% ±10%
tTB,cap
Timer_B capture timing
All capture inputs, minimum pulse duration
required for capture
30
Specifications
1.8 V, 3 V
1.8 V, 3 V
MIN
MAX
UNIT
25
MHz
20
ns
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5.30 USCI (UART Mode) Clock Frequency
PARAMETER
fUSCI
USCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
TEST CONDITIONS
MIN
Internal: SMCLK or ACLK,
External: UCLK,
Duty cycle = 50% ±10%
MAX
UNIT
fSYSTEM
MHz
1
MHz
5.31 USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
UART receive deglitch time (1)
tτ
(1)
VCC
MIN
MAX
2.2 V
50
600
3V
50
600
UNIT
ns
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To make sure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
5.32 USCI (SPI Master Mode) Clock Frequency
PARAMETER
fUSCI
USCI input clock frequency
TEST CONDITIONS
MIN
Internal: SMCLK or ACLK,
Duty cycle = 50% ±10%
MAX
UNIT
fSYSTEM
MHz
MAX
UNIT
fSYSTEM
MHz
5.33 USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
(see Figure 5-11 and Figure 5-12)
PARAMETER
TEST CONDITIONS
fUSCI
USCI input clock frequency
tSU,MI
SOMI input data setup time
tHD,MI
SOMI input data hold time
tVALID,MO
SIMO output data valid time (2)
UCLK edge to SIMO valid,
CL = 20 pF
tHD,MO
SIMO output data hold time (3)
CL = 20 pF
(1)
(2)
(3)
VCC
MIN
SMCLK, ACLK
Duty cycle = 50% ±10%
2.2 V
65
3V
50
2.2 V
0
3V
0
ns
ns
2.2 V
25
3V
20
2.2 V
3V
ns
ns
fUCxCLK = 1/2 × tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave))
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-11 and Figure 5-12.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 511 and Figure 5-12.
Specifications
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1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tHD,MO
tVALID,MO
SIMO
Figure 5-11. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tHD,MI
tSU,MI
SOMI
tHD,MO
tVALID,MO
SIMO
Figure 5-12. SPI Master Mode, CKPH = 1
32
Specifications
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5.34 USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
(see Figure 5-13 and Figure 5-14)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
STE lead time, STE low to clock
2.2 V, 3 V
tSTE,LAG
STE lag time, Last clock to STE high
2.2 V, 3 V
tSTE,ACC
STE access time, STE low to SOMI data out
2.2 V, 3 V
40
ns
tSTE,DIS
STE disable time, STE high to SOMI high
impedance
2.2 V, 3 V
40
ns
tSU,SI
SIMO input data setup time
tHD,SI
SIMO input data hold time
tVALID,SO
SOMI output data valid time (2)
UCLK edge to SOMI valid,
CL = 20 pF
tHD,SO
SOMI output data hold time (3)
CL = 20 pF
(1)
(2)
(3)
40
UNIT
tSTE,LEAD
ns
10
2.2 V
20
3V
15
2.2 V
10
3V
10
ns
ns
ns
2.2 V
62
3V
50
2.2 V
0
3V
0
ns
ns
fUCxCLK = 1/2 × tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI))
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-11 and Figure 5-12.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-11
and Figure 5-12.
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tSU,SI
tLO/HI
tHD,SI
SIMO
tSTE,ACC
tHD,SO
tVALID,SO
tSTE,DIS
SOMI
Figure 5-13. SPI Slave Mode, CKPH = 0
Specifications
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tSTE,LAG
tSTE,LEAD
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tHD,SI
tSU,SI
SIMO
tHD,MO
tVALID,SO
tSTE,ACC
tSTE,DIS
SOMI
Figure 5-14. SPI Slave Mode, CKPH = 1
5.35 USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-15)
PARAMETER
fUSCI
USCI input clock frequency
fSCL
SCL clock frequency
TEST CONDITIONS
VCC
MIN
Internal: SMCLK or ACLK,
External: UCLK,
Duty cycle = 50% ±10%
2.2 V, 3 V
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
tSU,DAT
Data setup time
fSCL ≤ 100 kHz
fSCL ≤ 100 kHz
fSCL ≤ 100 kHz
Setup time for STOP
tSP
Pulse duration of spikes suppressed by input filter
tSU,STA
tHD,STA
MHz
400
kHz
µs
4.7
µs
0.6
2.2 V, 3 V
0
ns
2.2 V, 3 V
250
ns
4.0
2.2 V, 3 V
fSCL > 100 kHz
fSYSTEM
0.6
2.2 V, 3 V
fSCL > 100 kHz
UNIT
4.0
2.2 V, 3 V
fSCL > 100 kHz
tSU,STO
0
MAX
µs
0.6
2.2 V
50
600
3V
50
600
tHD,STA
ns
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 5-15. I2C Mode Timing
34
Specifications
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5.36 12-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
AVCC
Analog supply voltage
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
V(Ax)
Analog input voltage range (2)
All ADC12 pins: P6.0 to P6.7, P7.4 to P7.7,
P5.0, and P5.1 terminals
IADC12_A
Operating supply current into
AVCC terminal (3)
fADC12CLK = 5.0 MHz, ADC12ON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0,
ADC12DIV = 0
IREF+
Operating supply current into
AVCC terminal (4)
VCC
MAX
UNIT
2.2
3.6
V
0
AVCC
V
125
155
3V
150
220
ADC12ON = 0,
REFON = 1, REF2_5V = 1
3V
150
190
ADC12ON = 0,
REFON = 1, REF2_5V = 0
2.2 V, 3 V
150
180
2.2 V
20
25
pF
200
1900
Ω
µA
µA
Input capacitance
Only one terminal Ax can be selected at one
time
RI
Input MUX ON resistance
0 V ≤ VAx ≤ AVCC
(3)
(4)
TYP
2.2 V
CI
(1)
(2)
MIN
10
The leakage current is specified by the digital I/O input leakage.
The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. If the
reference voltage is supplied by an external source or if the internal reference voltage is used and REFOUT = 1, then decoupling
capacitors are required. See Section 5.37 and Section 5.38.
The internal reference supply current is not included in current consumption parameter IADC12.
The internal reference current is supplied through the AVCC terminal. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an analog-to-digital conversion. No external
load.
5.37 12-Bit ADC, External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX
UNIT
VeREF+
Positive external reference voltage input
VeREF+ > VREF–/VeREF–
(2)
1.4
AVCC
V
VREF–/VeREF–
Negative external reference voltage input
VeREF+ > VREF–/VeREF–
(3)
0
1.2
V
(VeREF+ –
VREF–/VeREF–)
Differential external reference voltage input
VeREF+ > VREF–/VeREF–
(4)
1.4
AVCC
V
IVeREF+
Static input current
0 V ≤ VeREF+ ≤ VAVCC
2.2 V, 3 V
±1
µA
IVREF–/VeREF–
Static input current
0 V ≤ VeREF– ≤ VAVCC
2.2 V, 3 V
±1
µA
CVREF+/-
Capacitance at VREF+ or VREF- terminal
(1)
(2)
(3)
(4)
(5)
(5)
10
µF
The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also the
dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external
reference source if it is used for the ADC12_A. Also see the MSP430F5xx and MSP430F6xx Family User's Guide.
Specifications
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5.38 12-Bit ADC, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Positive built-in reference
voltage output
VREF+
AVCC(min)
AVCC minimum voltage,
Positive built-in reference
active
IVREF+
Load current out of VREF+
terminal
IL(VREF)+
Load-current regulation,
VREF+ terminal
CVREF+
TREF+
tSETTLE
(1)
(2)
(3)
36
Capacitance at VREF+
terminal
Temperature coefficient of
built-in reference (2)
Settling time of reference
voltage (3)
TEST CONDITIONS
VCC
MIN
TYP
MAX
REF2_5V = 1 for 2.5 V,
IVREF+(max) ≤ IVREF+ ≤ IVREF+(min)
3V
2.35
2.45
2.53
REF2_5V = 0 for 1.5 V,
IVREF+(max) ≤ IVREF+ ≤ IVREF+(min)
2.2 V, 3 V
1.41
1.47
1.53
V
REF2_5V = 0
2.2
REF2_5V = 1
2.8
IVREF+ = +10 µA or –1000 µA,
Analog input voltage ≈ 0.75 V, REF2_5V = 0
IVREF+ = +10 µA or –1000 µA,
Analog input voltage ≈ 1.25 V, REF2_5V = 1
UNIT
V
2.2 V
–1
3V
–1
2.2 V
±2
3V
±2
3V
±2
REFON = REFOUT = 1 (1)
2.2 V, 3 V
REF2_5V = 0,
IVREF+ is a constant in the range of
0 mA ≤ IVREF+ ≤ –1 mA
2.2 V, 3 V
REF2_5V = 1,
IVREF+ is a constant in the range of
0 mA ≤ IVREF+ ≤ –1 mA
3V
20
100
mA
LSB
pF
30
ppm/
°C
30
VREF+ = 1.5 V, VAVCC = 2.2 V,
REFOUT = 0, REFON = 0 → 1
20
VREF+ = 2.5 V, VAVCC = 2.8 V,
REFOUT = 0, REFON = 0 → 1
20
VREF+ = 1.5 V, VAVCC = 2.2 V,
CVREF = CVREF(max),
REFOUT = 1, REFON = 0 → 1
35
VREF+ = 2.5 V, VAVCC = 2.8 V,
CVREF = CVREF(max),
REFOUT = 1, REFON = 0 → 1
35
µs
Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external
reference source if it is used for the ADC12_A. Also see the MSP430F5xx and MSP430F6xx Family User's Guide.
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C – (–40°C))
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load.
Specifications
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5.39 12-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fADC12CLK
fADC12OSC
Internal ADC12
oscillator (1)
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
For specified performance of ADC12 linearity
parameters
2.2 V, 3 V
0.45
4.8
5.4
MHz
ADC12DIV = 0, fADC12CLK = fADC12OSC
2.2 V, 3 V
4.2
4.65
5.0
MHz
REFON = 0, Internal oscillator,
fADC12OSC = 4.2 MHz to 5.4 MHz
2.2 V, 3 V
2.4
tCONVERT
Conversion time
tADC12ON
Turnon settling time of
the ADC
See
tSample
Sampling time
RS = 400 Ω, RI = 1000 Ω, CI = 30 pF,
τ = (RS + RI) × CI (3)
(1)
(2)
(3)
External fADC12CLK from ACLK, MCLK or
SMCLK, ADC12SSEL ≠ 0
3.1
µs
13 ×
1 / fADC12CLK
(2)
100
2.2 V, 3 V
1000
ns
ns
The ADC12OSC is sourced directly from MODOSC inside the UCS.
The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signal are already
settled.
Approximately 10 Tau (τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) x (RS + RI) × CI + 800 ns, where n = ADC resolution = 12, RS = external source resistance
5.40 12-Bit ADC, Linearity Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
EI
Integral
linearity error
1.4 V ≤ (VeREF+ – VREF–/VeREF–)min ≤ 1.6 V
ED
Differential
linearity error
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
CVREF+ = 20 pF
2.2 V, 3 V
EO
Offset error
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
Internal impedance of source RS < 100 Ω, CVREF+ = 20 pF
2.2 V, 3 V
EG
Gain error
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
CVREF+ = 20 pF
ET
Total unadjusted
error
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
CVREF+ = 20 pF
1.6 V < (VeREF+ – VREF–/VeREF–)min ≤ VAVCC
MIN
TYP
MAX
±2
2.2 V, 3 V
±1.7
LSB
±1
LSB
±1
±3.5
LSB
2.2 V, 3 V
±1.1
±2
LSB
2.2 V, 3 V
±2
±5
LSB
Specifications
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5.41 12-Bit ADC, Temperature Sensor and Built-In VMID
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ISENSOR
Operating supply current into
AVCC terminal (1)
VSENSOR
See
(2)
TCSENSOR
VCC
MIN
TYP
REFON = 0, INCH = 0Ah,
ADC12ON = N/A, TA = 25°C
2.2 V
150
3V
150
ADC12ON = 1, INCH = 0Ah,
TA = 0°C
2.2 V
894
3V
894
2.2 V
3.66
3V
3.66
ADC12ON = 1, INCH = 0Ah
tSENSOR(sample)
Sample time required if
channel 10 is selected (3)
ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
2.2 V
30
3V
30
VMID
AVCC divider at channel 11
ADC12ON = 1, INCH = 0Bh,
VMID ≈ 0.5 × VAVCC
2.2 V
1.1
3V
1.5
tVMID(sample)
Sample time required if
channel 11 is selected (4)
ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
(1)
(2)
(3)
(4)
2.2 V, 3 V
MAX
UNIT
µA
mV
mV/°C
µs
1000
V
ns
The sensor current ISENSOR is consumed if (ADC12ON = 1 and REFON = 1) or (ADC12ON = 1 and INCH = 0Ah and sample signal is
high). When REFON = 1, ISENSOR is already included in IREF+.
The temperature sensor offset can be significant. TI recommends a single-point calibration to minimize the offset error of the built-in
temperature sensor.
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
The on-time tVMID(on) is included in the sampling time tVMID(sample). No additional on time is needed.
Typical Temperature Sensor Voltage - mV
1250
1200
1150
1100
1050
1000
950
900
850
800
750
700
-40
-25
-10
5
20
35
50
65
80
TA - Ambient Temperature - °C
Figure 5-16. Typical Temperature Sensor Voltage
38
Specifications
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SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
5.42 Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
DVCC(PGM/ERASE) Program and erase supply voltage
MIN
TYP
1.8
MAX
3.6
UNIT
V
IPGM
Average supply current from DVCC during program
3
5
mA
IERASE
Average supply current from DVCC during erase
6
11
mA
IMERASE, IBANK
Average supply current from DVCC during mass erase or bank
erase
6
11
mA
16
ms
tCPT
Cumulative program time
See
(1)
4
Program and erase endurance
10
5
10
cycles
tRetention
Data retention duration
TJ = 25°C
tWord
Word or byte program time
See
(2)
64
85
µs
tBlock,
0
Block program time for first byte or word
See
(2)
49
65
µs
tBlock,
1–(N–1)
Block program time for each additional byte or word, except for last
byte or word
See
(2)
37
49
µs
Block program time for last byte or word
See
(2)
55
73
µs
tErase
Erase time for segment, mass erase, and bank erase when
available.
See
(2)
23
32
ms
fMCLK,MGR
MCLK frequency in marginal read mode
(FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1)
0
1
MHz
tBlock,
(1)
(2)
N
100
years
The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word or byte write and block write modes.
These values are hardwired into the state machine of the flash controller.
5.43 JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
2.2 V, 3 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse duration
2.2 V, 3 V
0.025
15
µs
tSBW, En
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
edge) (1)
2.2 V, 3 V
1
µs
tSBW,Rst
Spy-Bi-Wire return to normal operation time
fTCK
TCK input frequency for 4-wire JTAG (2)
Rinternal
Internal pulldown resistance on TEST
(1)
(2)
2.2 V
15
100
0
5
MHz
10
MHz
80
kΩ
3V
0
2.2 V, 3 V
45
60
µs
Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
Specifications
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6 Detailed Description
6.1
CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time (see Figure 6-1).
The register-to-register operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and
constant generator, respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word and
byte data.
Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
Constant Generator
SR/CG1/R2
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Figure 6-1. Integrated CPU Registers
40
Detailed Description
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6.2
SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
Operating Modes
These MCUs have one active mode and five software-selectable low-power modes of operation. An
interrupt event can wake up the device from any of the low-power modes, service the request, and restore
back to the low-power mode on return from the interrupt program.
Software can configure the following operating modes:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– FLL loop control remains active
• Low-power mode 1 (LPM1)
– CPU is disabled
– FLL loop control is disabled
– ACLK and SMCLK remain active, MCLK is disabled
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK and FLL loop control and DCOCLK are disabled
– DC generator of the DCO remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO is disabled
– Crystal oscillator is stopped
– Complete data retention
Detailed Description
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6.3
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Interrupt Vector Addresses
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see
Table 6-1). The vector contains the 16-bit address of the appropriate interrupt-handler instruction
sequence.
Table 6-1. Interrupt Sources, Flags, and Vectors
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
Reset
0FFFEh
63, highest
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,
JMBOUTIFG (SYSSNIV) (1)
(Non)maskable
0FFFCh
62
User NMI
NMI
Oscillator fault
Flash memory access violation
NMIIFG, OFIFG, ACCVIFG (SYSUNIV) (1)
(Non)maskable
0FFFAh
61
TB0
TBCCR0 CCIFG0
Maskable
0FFF8h
60
INTERRUPT SOURCE
System Reset
Power up
External reset
Watchdog time-out, password
violation
Flash memory password violation
PMM password violation
System NMI
PMM
Vacant memory access
JTAG mailbox
INTERRUPT FLAG
WDTIFG, KEYV (SYSRSTIV) (1)
(2)
(2)
(3)
TB0
TBCCR1 CCIFG1 ... TBCCR6 CCIFG6,
TBIFG (TBIV) (1) (3)
Maskable
0FFF6h
59
Watchdog Timer_A interval timer
mode
WDTIFG
Maskable
0FFF4h
58
(3)
Maskable
0FFF2h
57
(1) (3)
Maskable
0FFF0h
56
Maskable
0FFEEh
55
USCI_A0 receive or transmit
USCI_B0 receive or transmit
ADC12_A
TA0
TA0
USCI_A2 receive or transmit
USCI_B2 receive or transmit
DMA
TA0CCR0 CCIFG0
(3)
(3)
Maskable
0FFECh
54
TA0CCR1 CCIFG1 ... TA0CCR4 CCIFG4,
TA0IFG (TA0IV) (1) (3)
Maskable
0FFEAh
53
UCA2RXIFG, UCA2TXIFG (UCA2IV) (1)
Maskable
0FFE8h
52
Maskable
0FFE6h
51
Maskable
0FFE4h
50
Maskable
0FFE2h
49
Maskable
0FFE0h
48
UCB2RXIFG, UCB2TXIFG (UCB2IV)
(3)
(1) (3)
DMA0IFG, DMA1IFG, DMA2IFG (DMAIV) (1)
TA1
TA1CCR1 CCIFG1 ... TA1CCR2 CCIFG2,
TA1IFG (TA1IV) (1) (3)
P1IFG.0 to P1IFG.7 (P1IV)
(1) (3)
(3)
Maskable
0FFDEh
47
(3)
Maskable
0FFDCh
46
(1) (3)
UCA1RXIFG, UCA1TXIFG (UCA1IV) (1)
USCI_B1 receive or transmit
UCB1RXIFG, UCB1TXIFG (UCB1IV)
Maskable
0FFDAh
45
USCI_A3 receive or transmit
UCA3RXIFG, UCA3TXIFG (UCA3IV) (1)
(3)
Maskable
0FFD8h
44
USCI_B3 receive or transmit
UCB3RXIFG, UCB3TXIFG (UCB3IV) (1)
(3)
Maskable
0FFD6h
43
Maskable
0FFD4h
42
Maskable
0FFD2h
41
0FFD0h
40
I/O port P2
RTC_A
Reserved
42
ADC12IFG0 ... ADC12IFG15 (ADC12IV) (1)
TA1CCR0 CCIFG0 (3)
I/O port P1
(3)
(4)
UCB0RXIFG, UCB0TXIFG (UCB0IV)
TA1
USCI_A1 receive or transmit
(1)
(2)
UCA0RXIFG, UCA0TXIFG (UCA0IV) (1)
P2IFG.0 to P2IFG.7 (P2IV)
(1) (3)
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RT0PSIFG, RT1PSIFG (RTCIV) (1) (3)
Reserved
(4)
⋮
⋮
0FF80h
0, lowest
Multiple source flags
A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable bit cannot disable it.
Interrupt flags are in the module.
Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, TI recommends reserving these locations.
Detailed Description
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6.4
SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
Memory Organization
Table 6-2 summarizes the memory maps of all device variants.
Table 6-2. Memory Organization
MSP430F5419
MSP430F5418
MSP430F5436
MSP430F5435
MSP430F5438
MSP430F5437
128KB
00FFFFh to 00FF80h
025BFFh to 005C00h
192KB
00FFFFh to 00FF80h
035BFFh to 005C00h
256KB
00FFFFh to 00FF80h
045BFFh to 005C00h
Bank D
N/A
23KB
035BFFh to 030000h
64KB
03FFFFh to 030000h
Bank C
23KB
025BFFh to 020000h
64KB
02FFFFh to 020000h
64KB
02FFFFh to 020000h
Bank B
64KB
01FFFFh to 010000h
64KB
01FFFFh to 010000h
64KB
01FFFFh to 010000h
Bank A
41KB
00FFFFh to 005C00h
41KB
00FFFFh to 005C00h
64KB
045BFFh to 040000h
00FFFFh to 005C00h
16 KB
16KB
16KB
Sector 3
4KB
005BFFh to 004C00h
4KB
005BFFh to 004C00h
4KB
005BFFh to 004C00h
Sector 2
4KB
004BFFh to 003C00h
4KB
004BFFh to 003C00h
4KB
004BFFh to 003C00h
Sector 1
4KB
003BFFh to 002C00h
4KB
003BFFh to 002C00h
4KB
003BFFh to 002C00h
Sector 0
4KB
002BFFh to 001C00h
4KB
002BFFh to 001C00h
4KB
002BFFh to 001C00h
Factory memory
(Boot code)
Size
256 B
001BFFh to 001B00h
256 B
001BFFh to 001B00h
256 B
001BFFh to 001B00h
Factory memory
(TLV)
Size
256 B
001AFFh to 001A00h
256 B
001AFFh to 001A00h
256 B
001AFFh to 001A00h
Info A
128 B
0019FFh to 001980h
128 B
0019FFh to 001980h
128 B
0019FFh to 001980h
Info B
128 B
00197Fh to 001900h
128 B
00197Fh to 001900h
128 B
00197Fh to 001900h
Info C
128 B
0018FFh to 001880h
128 B
0018FFh to 001880h
128 B
0018FFh to 001880h
Info D
128 B
00187Fh to 001800h
128 B
00187Fh to 001800h
128 B
00187Fh to 001800h
BSL 3
512 B
0017FFh to 001600h
512 B
0017FFh to 001600h
512 B
0017FFh to 001600h
BSL 2
512 B
0015FFh to 001400h
512 B
0015FFh to 001400h
512 B
0015FFh to 001400h
BSL 1
512 B
0013FFh to 001200h
512 B
0013FFh to 001200h
512 B
0013FFh to 001200h
BSL 0
512 B
0011FFh to 001000h
512 B
0011FFh to 001000h
512 B
0011FFh to 001000h
Size
4KB
000FFFh to 000000h
4KB
000FFFh to 000000h
4KB
000FFFh to 000000h
Memory (flash)
Main: interrupt vector
Main: code memory
Main: code memory
Total Size
Flash
Flash
Size
RAM
Information memory
(flash)
Bootloader (BSL) (1)
memory (flash)
Peripherals
(1)
The BSL area contains a Texas Instruments provided BSL and cannot be modified.
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Bootloader (BSL)
The BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the
device memory through the BSL is protected by an user-defined password. Use of the BSL requires four
pins (see Table 6-3). BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and
TEST/SBWTCK pins. For a complete description of the features of the BSL and its implementation, see
MSP430 Programming With the Bootloader (BSL). For further details on interfacing to development tools
and device programmers, see the MSP430 Hardware Tools User's Guide.
Table 6-3. BSL Pin Requirements and Functions
6.6
6.6.1
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
TEST/SBWTCK
Entry sequence signal
P1.1
Data transmit
P1.2
Data receive
VCC
Power supply
VSS
Ground supply
JTAG Operation
JTAG Standard Interface
The MSP430 family supports the standard JTAG interface which requires four signals for sending and
receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to
enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with
MSP430 development tools and device programmers. Table 6-4 lists the JTAG pin requirements. For a
complete description of the features of the JTAG interface and its implementation, see MSP430
Programming With the JTAG Interface. For further details on interfacing to development tools and device
programmers, see the MSP430 Hardware Tools User's Guide.
Table 6-4. JTAG Pin Requirements and Functions
44
DEVICE SIGNAL
DIRECTION
FUNCTION
PJ.3/TCK
IN
JTAG clock input
PJ.2/TMS
IN
JTAG state control
PJ.1/TDI/TCLK
IN
JTAG data input, TCLK input
PJ.0/TDO
OUT
JTAG data output
TEST/SBWTCK
IN
Enable JTAG pins
RST/NMI/SBWTDIO
IN
External reset
Detailed Description
VCC
Power supply
VSS
Ground supply
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6.6.2
SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire
interface. Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers.
Table 6-5 lists the Spy-Bi-Wire interface pin requirements. For a complete description of the features of
the JTAG interface and its implementation, see MSP430 Programming With the JTAG Interface. For
further details on interfacing to development tools and device programmers, see the MSP430 Hardware
Tools User's Guide.
Table 6-5. Spy-Bi-Wire Pin Requirements and Functions
6.7
DEVICE SIGNAL
DIRECTION
FUNCTION
TEST/SBWTCK
IN
Spy-Bi-Wire clock input
RST/NMI/SBWTDIO
IN, OUT
Spy-Bi-Wire data input and output
VCC
Power supply
VSS
Ground supply
Flash Memory (Link to User's Guide)
The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system
by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory.
Features of the flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually. Segments A to D are also called information memory.
• Segment A can be locked separately.
6.8
RAM (Link to User's Guide)
The RAM is made up of n sectors. Each sector can be completely powered down to save leakage;
however, all data are lost. Features of the RAM include:
• RAM has n sectors. The size of a sector can be found in Memory Organization.
• Each sector 0 to n can be complete disabled; however, data retention is lost.
• Each sector 0 to n automatically enters low power retention mode when possible.
• For Devices that contain USB memory, the USB memory can be used as normal RAM if USB is not
required.
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6.9
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Peripherals
Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be
handled using all instructions. For complete module descriptions, see the MSP430F5xx and MSP430F6xx
Family User's Guide.
6.9.1
Digital I/O (Link to User's Guide)
Up to ten 8-bit I/O ports are implemented: for 100-pin options, P1 through P10 are complete, and P11
contains three individual I/O ports. For 80-pin options, P1 through P7 are complete, P8 contains seven
individual I/O ports, and P9 through P11 do not exist. Port PJ contains four individual I/O ports, common
to all devices.
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Pullup or pulldown on all ports is programmable.
• Drive strength on all ports is programmable.
• Edge-selectable interrupt and LPM5 wake-up input capability is available for all bits of ports P1 and P2.
• Read and write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise (P1 through P11) or word-wise in pairs (PA through PF).
6.9.2
Oscillator and System Clock (Link to User's Guide)
The clock system is supported by the Unified Clock System (UCS) module that includes support for a 32kHz watch crystal oscillator (XT1 LF mode), an internal very-low-power low-frequency oscillator (VLO), an
internal trimmed low-frequency oscillator (REFO), an integrated internal digitally controlled oscillator
(DCO), and a high-frequency crystal oscillator (XT1 HF mode or XT2). The UCS module is designed to
meet the requirements of both low system cost and low power consumption. The UCS module features
digital frequency-locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the
DCO frequency to a programmable multiple of the selected FLL reference frequency. The internal DCO
provides a fast turnon clock source and stabilizes in less than 5 µs. The UCS module provides the
following clock signals:
• Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal, a high-frequency crystal, the internal lowfrequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal digitally
controlled oscillator DCO.
• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made
available to ACLK.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be
sourced by same sources made available to ACLK.
• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
6.9.3
Power-Management Module (PMM) (Link to User's Guide)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device and
contains programmable output levels to provide for power optimization. The PMM also includes supply
voltage supervisor (SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection.
The brownout circuit is implemented to provide the proper internal reset signal to the device during poweron and power-off. The SVS/SVM circuitry detects if the supply voltage drops below a user-selectable level
and supports both supply voltage supervision (the device is automatically reset) and supply voltage
monitoring (SVM, the device is not automatically reset). SVS and SVM circuitry is available on the primary
supply and core supply.
46
Detailed Description
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6.9.4
SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
Hardware Multiplier (Link to User's Guide)
The multiplication operation is supported by a dedicated peripheral module. The module performs
operations with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication
as well as signed and unsigned multiply-and-accumulate operations.
6.9.5
Real-Time Clock (RTC_A) (Link to User's Guide)
The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated
real-time clock (RTC) (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit
timers that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by
software. Calendar mode integrates an internal calendar which compensates for months with less than
31 days and includes leap year correction. The RTC_A also supports flexible alarm functions and offsetcalibration hardware.
6.9.6
Watchdog Timer (WDT_A) (Link to User's Guide)
The primary function of the WDT_A module is to perform a controlled system restart after a software
problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function
is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
Detailed Description
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6.9.7
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System Module (SYS) (Link to User's Guide)
The SYS module handles many of the system functions within the device. These include power-on reset
and power-up clear handling, NMI source selection and management, reset interrupt vector generators,
bootloader entry mechanisms, and configuration management (device descriptors) (see Table 6-6). The
SYS module also includes a data exchange mechanism through JTAG called a JTAG mailbox that can be
used in the application.
Table 6-6. System Module Interrupt Vector Registers
INTERRUPT VECTOR REGISTER
SYSRSTIV, System Reset
SYSSNIV, System NMI
SYSUNIV, User NMI
48
Detailed Description
ADDRESS
019Eh
019Ch
019Ah
INTERRUPT EVENT
VALUE
No interrupt pending
00h
Brownout (BOR)
02h
RST/NMI (POR)
04h
PMMSWBOR (BOR)
06h
Reserved
08h
Security violation (BOR)
0Ah
SVSL (POR)
0Ch
SVSH (POR)
0Eh
SVML_OVP (POR)
10h
SVMH_OVP (POR)
12h
PMMSWPOR (POR)
14h
WDT time-out (PUC)
16h
WDT password violation (PUC)
18h
KEYV flash password violation (PUC)
1Ah
Reserved
1Ch
Peripheral area fetch (PUC)
1Eh
PMM password violation (PUC)
20h
Reserved
22h to 3Eh
No interrupt pending
00h
SVMLIFG
02h
SVMHIFG
04h
SVSMLDLYIFG
06h
SVSMHDLYIFG
08h
VMAIFG
0Ah
JMBINIFG
0Ch
JMBOUTIFG
0Eh
SVMLVLRIFG
10h
SVMHVLRIFG
12h
Reserved
14h to 1Eh
No interrupt pending
00h
NMIIFG
02h
OFIFG
04h
ACCVIFG
06h
Reserved
08h
Reserved
0Ah to 1Eh
PRIORITY
Highest
Lowest
Highest
Lowest
Highest
Lowest
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6.9.8
SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
DMA Controller (Link to User's Guide)
The DMA controller allows movement of data from one memory address to another without CPU
intervention. For example, the DMA controller can be used to move data from the ADC12_A conversion
memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA
controller reduces system power consumption by allowing the CPU to remain in sleep mode, without
having to awaken to move data to or from a peripheral. Table 6-7 lists the available triggers for DMA
operation.
Table 6-7. DMA Trigger Assignments
CHANNEL
TRIGGER
(1)
(1)
0
1
2
0
DMAREQ
DMAREQ
DMAREQ
1
TA0CCR0 CCIFG
TA0CCR0 CCIFG
TA0CCR0 CCIFG
2
TA0CCR2 CCIFG
TA0CCR2 CCIFG
TA0CCR2 CCIFG
3
TA1CCR0 CCIFG
TA1CCR0 CCIFG
TA1CCR0 CCIFG
4
TA1CCR2 CCIFG
TA1CCR2 CCIFG
TA1CCR2 CCIFG
5
TB0CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR0 CCIFG
6
TB0CCR2 CCIFG
TB0CCR2 CCIFG
TB0CCR2 CCIFG
7
Reserved
Reserved
Reserved
8
Reserved
Reserved
Reserved
9
Reserved
Reserved
Reserved
10
Reserved
Reserved
Reserved
11
Reserved
Reserved
Reserved
12
Reserved
Reserved
Reserved
13
Reserved
Reserved
Reserved
14
Reserved
Reserved
Reserved
15
Reserved
Reserved
Reserved
16
UCA0RXIFG
UCA0RXIFG
UCA0RXIFG
17
UCA0TXIFG
UCA0TXIFG
UCA0TXIFG
18
UCB0RXIFG
UCB0RXIFG
UCB0RXIFG
19
UCB0TXIFG
UCB0TXIFG
UCB0TXIFG
20
UCA1RXIFG
UCA1RXIFG
UCA1RXIFG
21
UCA1TXIFG
UCA1TXIFG
UCA1TXIFG
22
UCB1RXIFG
UCB1RXIFG
UCB1RXIFG
23
UCB1TXIFG
UCB1TXIFG
UCB1TXIFG
24
ADC12IFGx
ADC12IFGx
ADC12IFGx
25
Reserved
Reserved
Reserved
26
Reserved
Reserved
Reserved
27
Reserved
Reserved
Reserved
28
Reserved
Reserved
Reserved
29
MPY ready
MPY ready
MPY ready
30
DMA2IFG
DMA0IFG
DMA1IFG
31
DMAE0
DMAE0
DMAE0
Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers do not
cause any DMA trigger event when selected.
Detailed Description
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6.9.9
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Universal Serial Communication Interface (USCI) (Links to User's Guide: UART
Mode, SPI Mode, I2C Mode)
The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3- or 4-pin) and I2C, and asynchronous communication protocols
such as UART, enhanced UART with automatic baud-rate detection, and IrDA. Each USCI module
contains two portions, A and B.
The USCI_An module provides support for SPI (3- or 4-pin), UART, enhanced UART, or IrDA.
The USCI_Bn module provides support for SPI (3- or 4-pin) or I2C.
The MSP430F5438, MSP430F5436, and MSP430F5419 include four complete USCI modules (n = 0 to 3).
The MSP430F5437, MSP430F5435, and MSP430F5418 include two complete USCI modules (n = 0 to 1).
6.9.10 TA0 (Link to User's Guide)
TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. TA0 can support multiple
capture/compares, PWM outputs, and interval timing (see Table 6-8). TA0 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 6-8. TA0 Signal Connections
INPUT PIN NUMBER
50
PZ
PN
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
17-P1.0
17-P1.0
TA0CLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
17-P1.0
17-P1.0
TA0CLK
TACLK
18-P1.1
18-P1.1
TA0.0
CCI0A
57-P8.0
60-P8.0
TA0.0
CCI0B
DVSS
GND
DVCC
VCC
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
N/A
N/A
CCR0
TA0
TA0.0
OUTPUT PIN NUMBER
PZ
PN
18-P1.1
18-P1.1
57-P8.0
60-P8.0
ADC12 (internal)
ADC12SHSx = {1}
ADC12 (internal)
ADC12SHSx = {1}
19-P1.2
19-P1.2
TA0.1
CCI1A
19-P1.2
19-P1.2
58-P8.1
61-P8.1
TA0.1
CCI1B
58-P8.1
61-P8.1
DVSS
GND
CCR1
TA1
TA0.1
DVCC
VCC
20-P1.3
20-P1.3
TA0.2
CCI2A
20-P1.3
20-P1.3
59-P8.2
62-P8.2
TA0.2
CCI2B
59-P8.2
62-P8.2
DVSS
GND
CCR2
TA2
TA0.2
DVCC
VCC
21-P1.4
21-P1.4
TA0.3
CCI3A
21-P1.4
21-P1.4
60-P8.3
63-P8.3
TA0.3
CCI3B
60-P8.3
63-P8.3
DVSS
GND
22-P1.5
22-P1.5
61-P8.4
64-P8.4
DVCC
VCC
22-P1.5
22-P1.5
TA0.4
CCI4A
61-P8.4
64-P8.4
TA0.4
CCI4B
DVSS
GND
DVCC
VCC
Detailed Description
CCR3
CCR4
TA3
TA4
TA0.3
TA0.4
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6.9.11 TA1 (Link to User's Guide)
TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA1 can support
multiple capture/compares, PWM outputs, and interval timing (see Table 6-9). TA1 also has extensive
interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each
of the capture/compare registers.
Table 6-9. TA1 Signal Connections
INPUT PIN NUMBER
PZ
PN
DEVICE
INPUT
SIGNAL
25-P2.0
25-P2.0
TA1CLK
MODULE
INPUT
SIGNAL
TACLK
ACLK
ACLK
SMCLK
SMCLK
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
N/A
N/A
OUTPUT PIN NUMBER
PZ
PN
25-P2.0
25-P2.0
TA1CLK
TACLK
26-P2.1
26-P2.1
TA1.0
CCI0A
26-P2.1
26-P2.1
65-P8.5
65-P8.5
TA1.0
CCI0B
65-P8.5
65-P8.5
DVSS
GND
CCR0
TA0
TA1.0
DVCC
VCC
27-P2.2
27-P2.2
TA1.1
CCI1A
27-P2.2
27-P2.2
66-P8.6
66-P8.6
TA1.1
CCI1B
66-P8.6
66-P8.6
DVSS
GND
DVCC
VCC
CCR1
TA1
TA1.1
28-P2.3
28-P2.3
TA1.2
CCI2A
28-P2.3
28-P2.3
56-P7.3
59-P7.3
TA1.2
CCI2B
56-P7.3
59-P7.3
DVSS
GND
DVCC
VCC
CCR2
TA2
TA1.2
Detailed Description
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6.9.12 TB0 (Link to User's Guide)
TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. TB0 can support
multiple capture/compares, PWM outputs, and interval timing (see Table 6-10). TB0 also has extensive
interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each
of the capture/compare registers.
Table 6-10. TB0 Signal Connections
INPUT PIN NUMBER
PZ
PN
DEVICE
INPUT
SIGNAL
50-P4.7
53-P4.7
TB0CLK
TBCLK
ACLK
ACLK
SMCLK
SMCLK
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
N/A
N/A
OUTPUT PIN NUMBER
PZ
PN
50-P4.7
53-P4.7
TB0CLK
TBCLK
43-P4.0
43-P4.0
TB0.0
CCI0A
43-P4.0
43-P4.0
TB0.0
CCI0B
ADC12 (internal)
ADC12SHSx = {2}
ADC12 (internal)
ADC12SHSx = {2}
DVSS
GND
44-P4.1
44-P4.1
ADC12 (internal)
ADC12SHSx = {3}
ADC12 (internal)
ADC12SHSx = {3}
45-P4.2
45-P4.2
46-P4.3
46-P4.3
47-P4.4
47-P4.4
48-P4.5
48-P4.5
49-P4.6
52-P4.6
43-P4.0
43-P4.0
DVCC
VCC
44-P4.1
44-P4.1
TB0.1
CCI1A
44-P4.1
44-P4.1
TB0.1
CCI1B
DVSS
GND
DVCC
VCC
45-P4.2
45-P4.2
TB0.2
CCI2A
45-P4.2
45-P4.2
TB0.2
CCI2B
DVSS
GND
DVCC
VCC
46-P4.3
46-P4.3
TB0.3
CCI3A
46-P4.3
46-P4.3
TB0.3
CCI3B
DVSS
GND
DVCC
VCC
47-P4.4
47-P4.4
TB0.4
CCI4A
47-P4.4
47-P4.4
TB0.4
CCI4B
DVSS
GND
DVCC
VCC
48-P4.5
48-P4.5
TB0.5
CCI5A
48-P4.5
48-P4.5
TB0.5
CCI5B
DVSS
GND
49-P4.6
52
MODULE
INPUT
SIGNAL
52-P4.6
Detailed Description
DVCC
VCC
TB0.6
CCI6A
ACLK
(internal)
CCI6B
DVSS
GND
DVCC
VCC
CCR0
CCR1
CCR2
CCR3
CCR4
CCR5
CCR6
TB0
TB1
TB2
TB3
TB4
TB5
TB6
TB0.0
TB0.1
TB0.2
TB0.3
TB0.4
TB0.5
TB0.6
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6.9.13 ADC12_A (Link to User's Guide)
The ADC12_A module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit
SAR core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored
without any CPU intervention.
6.9.14 CRC16 (Link to User's Guide)
The CRC16 module produces a signature based on a sequence of entered data values and can be used
for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
6.9.15 Embedded Emulation Module (EEM) (L Version) (Link to User's Guide)
The EEM supports real-time in-system debugging. The L version of the EEM has the following features:
• Eight hardware triggers or breakpoints on memory access
• Two hardware trigger or breakpoint on CPU register write access
• Up to ten hardware triggers can be combined to form complex triggers or breakpoints
• Two cycle counters
• Sequencer
• State storage
• Clock control on module level
Detailed Description
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6.9.16 Peripheral File Map
Table 6-11 lists the base register address for each supported peripheral.
Table 6-11. Peripherals
MODULE NAME
BASE ADDRESS
OFFSET ADDRESS
RANGE
Special Functions (see Table 6-12)
0100h
000h to 01Fh
PMM (see Table 6-13)
0120h
000h to 00Fh
Flash Control (see Table 6-14)
0140h
000h to 00Fh
CRC16 (see Table 6-15)
0150h
000h to 007h
RAM Control (see Table 6-16)
0158h
000h to 001h
Watchdog (see Table 6-17)
015Ch
000h to 001h
UCS (see Table 6-18)
0160h
000h to 01Fh
SYS (see Table 6-19)
0180h
000h to 01Fh
Port P1, P2 (see Table 6-20)
0200h
000h to 01Fh
Port P3, P4 (see Table 6-21)
0220h
000h to 00Bh
Port P5, P6 (see Table 6-22)
0240h
000h to 00Bh
Port P7, P8 (see Table 6-23)
0260h
000h to 00Bh
Port P9, P10 (see Table 6-24) (1)
0280h
000h to 00Bh
Port P11 (see Table 6-25) (1)
02A0h
000h to 00Ah
Port PJ (see Table 6-26)
0320h
000h to 01Fh
TA0 (see Table 6-27)
0340h
000h to 02Eh
TA1 (see Table 6-28)
0380h
000h to 02Eh
TB0 (see Table 6-29)
03C0h
000h to 02Eh
Real-Time Clock (RTC_A) (see Table 6-30)
04A0h
000h to 01Bh
32-Bit Hardware Multiplier (see Table 6-31)
04C0h
000h to 02Fh
DMA General Control (see Table 6-32)
0500h
000h to 00Fh
DMA Channel 0 (see Table 6-32)
0510h
000h to 00Ah
DMA Channel 1 (see Table 6-32)
0520h
000h to 00Ah
DMA Channel 2 (see Table 6-32)
0530h
000h to 00Ah
USCI_A0 (see Table 6-33)
05C0h
000h to 01Fh
USCI_B0 (see Table 6-34)
05E0h
000h to 01Fh
USCI_A1 (see Table 6-35)
0600h
000h to 01Fh
USCI_B1 (see Table 6-36)
0620h
000h to 01Fh
(1)
0640h
000h to 01Fh
USCI_B2 (see Table 6-38) (1)
0660h
000h to 01Fh
USCI_A3 (see Table 6-39) (1)
0680h
000h to 01Fh
(1)
06A0h
000h to 01Fh
0700h
000h to 03Eh
USCI_A2 (see Table 6-37)
USCI_B3 (see Table 6-40)
ADC12_A (see Table 6-41)
(1)
54
Not available on F5437, F5435, F5418 devices
Detailed Description
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Table 6-12. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
REGISTER
OFFSET
SFR interrupt enable
SFRIE1
00h
SFR interrupt flag
SFRIFG1
02h
SFR reset pin control
SFRRPCR
04h
Table 6-13. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
REGISTER
OFFSET
PMM control 0
PMMCTL0
00h
PMM control 1
PMMCTL1
02h
SVS high-side control
SVSMHCTL
04h
SVS low-side control
SVSMLCTL
06h
PMM interrupt flags
PMMIFG
0Ch
PMM interrupt enable
PMMIE
0Eh
Table 6-14. Flash Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Flash control 1
FCTL1
00h
Flash control 3
FCTL3
04h
Flash control 4
FCTL4
06h
Table 6-15. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
REGISTER
OFFSET
CRC data input
CRC16DI
00h
CRC result
CRC16INIRES
04h
Table 6-16. RAM Control Registers (Base Address: 0158h)
REGISTER DESCRIPTION
RAM control 0
REGISTER
RCCTL0
OFFSET
00h
Table 6-17. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
Watchdog timer control
REGISTER
WDTCTL
OFFSET
00h
Table 6-18. UCS Registers (Base Address: 0160h)
REGISTER DESCRIPTION
REGISTER
OFFSET
UCS control 0
UCSCTL0
00h
UCS control 1
UCSCTL1
02h
UCS control 2
UCSCTL2
04h
UCS control 3
UCSCTL3
06h
UCS control 4
UCSCTL4
08h
UCS control 5
UCSCTL5
0Ah
UCS control 6
UCSCTL6
0Ch
UCS control 7
UCSCTL7
0Eh
UCS control 8
UCSCTL8
10h
Detailed Description
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Table 6-19. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
OFFSET
System control
SYSCTL
00h
Bootloader configuration area
SYSBSLC
02h
JTAG mailbox control
SYSJMBC
06h
JTAG mailbox input 0
SYSJMBI0
08h
JTAG mailbox input 1
SYSJMBI1
0Ah
JTAG mailbox output 0
SYSJMBO0
0Ch
JTAG mailbox output 1
SYSJMBO1
0Eh
Bus Error vector generator
SYSBERRIV
18h
User NMI vector generator
SYSUNIV
1Ah
System NMI vector generator
SYSSNIV
1Ch
Reset vector generator
SYSRSTIV
1Eh
Table 6-20. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P1 input
P1IN
00h
Port P1 output
P1OUT
02h
Port P1 direction
P1DIR
04h
Port P1 resistor enable
P1REN
06h
Port P1 drive strength
P1DS
08h
Port P1 selection
P1SEL
0Ah
Port P1 interrupt vector word
P1IV
0Eh
Port P1 interrupt edge select
P1IES
18h
Port P1 interrupt enable
P1IE
1Ah
Port P1 interrupt flag
P1IFG
1Ch
Port P2 input
P2IN
01h
Port P2 output
P2OUT
03h
Port P2 direction
P2DIR
05h
Port P2 resistor enable
P2REN
07h
Port P2 drive strength
P2DS
09h
Port P2 selection
P2SEL
0Bh
Port P2 interrupt vector word
P2IV
1Eh
Port P2 interrupt edge select
P2IES
19h
Port P2 interrupt enable
P2IE
1Bh
Port P2 interrupt flag
P2IFG
1Dh
56
Detailed Description
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Table 6-21. Port P3, P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3 input
P3IN
00h
Port P3 output
P3OUT
02h
Port P3 direction
P3DIR
04h
Port P3 resistor enable
P3REN
06h
Port P3 drive strength
P3DS
08h
Port P3 selection
P3SEL
0Ah
Port P4 input
P4IN
01h
Port P4 output
P4OUT
03h
Port P4 direction
P4DIR
05h
Port P4 resistor enable
P4REN
07h
Port P4 drive strength
P4DS
09h
Port P4 selection
P4SEL
0Bh
Table 6-22. Port P5, P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P5 input
P5IN
00h
Port P5 output
P5OUT
02h
Port P5 direction
P5DIR
04h
Port P5 resistor enable
P5REN
06h
Port P5 drive strength
P5DS
08h
Port P5 selection
P5SEL
0Ah
Port P6 input
P6IN
01h
Port P6 output
P6OUT
03h
Port P6 direction
P6DIR
05h
Port P6 resistor enable
P6REN
07h
Port P6 drive strength
P6DS
09h
Port P6 selection
P6SEL
0Bh
Table 6-23. Port P7, P8 Registers (Base Address: 0260h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P7 input
P7IN
00h
Port P7 output
P7OUT
02h
Port P7 direction
P7DIR
04h
Port P7 resistor enable
P7REN
06h
Port P7 drive strength
P7DS
08h
Port P7 selection
P7SEL
0Ah
Port P8 input
P8IN
01h
Port P8 output
P8OUT
03h
Port P8 direction
P8DIR
05h
Port P8 resistor enable
P8REN
07h
Port P8 drive strength
P8DS
09h
Port P8 selection
P8SEL
0Bh
Detailed Description
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Table 6-24. Port P9, P10 Registers (Base Address: 0280h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P9 input
P9IN
00h
Port P9 output
P9OUT
02h
Port P9 direction
P9DIR
04h
Port P9 resistor enable
P9REN
06h
Port P9 drive strength
P9DS
08h
Port P9 selection
P9SEL
0Ah
Port P10 input
P10IN
01h
Port P10 output
P10OUT
03h
Port P10 direction
P10DIR
05h
Port P10 resistor enable
P10REN
07h
Port P10 drive strength
P10DS
09h
Port P10 selection
P10SEL
0Bh
Table 6-25. Port P11 Registers (Base Address: 02A0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P11 input
P11IN
00h
Port P11 output
P11OUT
02h
Port P11 direction
P11DIR
04h
Port P11 resistor enable
P11REN
06h
Port P11 drive strength
P11DS
08h
Port P11 selection
P11SEL
0Ah
Table 6-26. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port PJ input
PJIN
00h
Port PJ output
PJOUT
02h
Port PJ direction
PJDIR
04h
Port PJ resistor enable
PJREN
06h
Port PJ drive strength
PJDS
08h
Table 6-27. TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA0 control
TA0CTL
00h
Capture/compare control 0
TA0CCTL0
02h
Capture/compare control 1
TA0CCTL1
04h
Capture/compare control 2
TA0CCTL2
06h
Capture/compare control 3
TA0CCTL3
08h
Capture/compare control 4
TA0CCTL4
0Ah
TA0 counter
TA0R
10h
Capture/compare 0
TA0CCR0
12h
Capture/compare 1
TA0CCR1
14h
Capture/compare 2
TA0CCR2
16h
Capture/compare 3
TA0CCR3
18h
Capture/compare 4
TA0CCR4
1Ah
TA0 expansion 0
TA0EX0
20h
TA0 interrupt vector
TA0IV
2Eh
58
Detailed Description
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SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
Table 6-28. TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA1 control
TA1CTL
00h
Capture/compare control 0
TA1CCTL0
02h
Capture/compare control 1
TA1CCTL1
04h
Capture/compare control 2
TA1CCTL2
06h
TA1 counter
TA1R
10h
Capture/compare 0
TA1CCR0
12h
Capture/compare 1
TA1CCR1
14h
Capture/compare 2
TA1CCR2
16h
TA1 expansion 0
TA1EX0
20h
TA1 interrupt vector
TA1IV
2Eh
Table 6-29. TB0 Registers (Base Address: 03C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TB0 control
TB0CTL
00h
Capture/compare control 0
TB0CCTL0
02h
Capture/compare control 1
TB0CCTL1
04h
Capture/compare control 2
TB0CCTL2
06h
Capture/compare control 3
TB0CCTL3
08h
Capture/compare control 4
TB0CCTL4
0Ah
Capture/compare control 5
TB0CCTL5
0Ch
Capture/compare control 6
TB0CCTL6
0Eh
TB0 counter
TB0R
10h
Capture/compare 0
TB0CCR0
12h
Capture/compare 1
TB0CCR1
14h
Capture/compare 2
TB0CCR2
16h
Capture/compare 3
TB0CCR3
18h
Capture/compare 4
TB0CCR4
1Ah
Capture/compare 5
TB0CCR5
1Ch
Capture/compare 6
TB0CCR6
1Eh
TB0 expansion 0
TB0EX0
20h
TB0 interrupt vector
TB0IV
2Eh
Detailed Description
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Table 6-30. Real-Time Clock Registers (Base Address: 04A0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
RTC control 0
RTCCTL0
00h
RTC control 1
RTCCTL1
01h
RTC control 2
RTCCTL2
02h
RTC control 3
RTCCTL3
03h
RTC prescaler 0 control
RTCPS0CTL
08h
RTC prescaler 1 control
RTCPS1CTL
0Ah
RTC prescaler 0
RTCPS0
0Ch
RTC prescaler 1
RTCPS1
0Dh
RTC interrupt vector word
RTCIV
0Eh
RTC seconds/counter 1
RTCSEC/RTCNT1
10h
RTC minutes/counter 2
RTCMIN/RTCNT2
11h
RTC hours/counter 3
RTCHOUR/RTCNT3
12h
RTC day of week/counter 4
RTCDOW/RTCNT4
13h
RTC days
RTCDAY
14h
RTC month
RTCMON
15h
RTC year low
RTCYEARL
16h
RTC year high
RTCYEARH
17h
RTC alarm minutes
RTCAMIN
18h
RTC alarm hours
RTCAHOUR
19h
RTC alarm day of week
RTCADOW
1Ah
RTC alarm days
RTCADAY
1Bh
60
Detailed Description
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Table 6-31. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
16-bit operand 1 – multiply
MPY
00h
16-bit operand 1 – signed multiply
MPYS
02h
16-bit operand 1 – multiply accumulate
MAC
04h
16-bit operand 1 – signed multiply accumulate
MACS
06h
16-bit operand 2
OP2
08h
16 × 16 result low word
RESLO
0Ah
16 × 16 result high word
RESHI
0Ch
16 × 16 sum extension
SUMEXT
0Eh
32-bit operand 1 – multiply low word
MPY32L
10h
32-bit operand 1 – multiply high word
MPY32H
12h
32-bit operand 1 – signed multiply low word
MPYS32L
14h
32-bit operand 1 – signed multiply high word
MPYS32H
16h
32-bit operand 1 – multiply accumulate low word
MAC32L
18h
32-bit operand 1 – multiply accumulate high word
MAC32H
1Ah
32-bit operand 1 – signed multiply accumulate low word
MACS32L
1Ch
32-bit operand 1 – signed multiply accumulate high word
MACS32H
1Eh
32-bit operand 2 – low word
OP2L
20h
32-bit operand 2 – high word
OP2H
22h
32 × 32 result 0 – least significant word
RES0
24h
32 × 32 result 1
RES1
26h
32 × 32 result 2
RES2
28h
32 × 32 result 3 – most significant word
RES3
2Ah
MPY32 control 0
MPY32CTL0
2Ch
Detailed Description
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Table 6-32. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA channel 0 control
DMA0CTL
00h
DMA channel 0 source address low
DMA0SAL
02h
DMA channel 0 source address high
DMA0SAH
04h
DMA channel 0 destination address low
DMA0DAL
06h
DMA channel 0 destination address high
DMA0DAH
08h
DMA channel 0 transfer size
DMA0SZ
0Ah
DMA channel 1 control
DMA1CTL
00h
DMA channel 1 source address low
DMA1SAL
02h
DMA channel 1 source address high
DMA1SAH
04h
DMA channel 1 destination address low
DMA1DAL
06h
DMA channel 1 destination address high
DMA1DAH
08h
DMA channel 1 transfer size
DMA1SZ
0Ah
DMA channel 2 control
DMA2CTL
00h
DMA channel 2 source address low
DMA2SAL
02h
DMA channel 2 source address high
DMA2SAH
04h
DMA channel 2 destination address low
DMA2DAL
06h
DMA channel 2 destination address high
DMA2DAH
08h
DMA channel 2 transfer size
DMA2SZ
0Ah
DMA module control 0
DMACTL0
00h
DMA module control 1
DMACTL1
02h
DMA module control 2
DMACTL2
04h
DMA module control 3
DMACTL3
06h
DMA module control 4
DMACTL4
08h
DMA interrupt vector
DMAIV
0Eh
Table 6-33. USCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI control 1
UCA0CTL1
00h
USCI control 0
UCA0CTL0
01h
USCI baud rate 0
UCA0BR0
06h
USCI baud rate 1
UCA0BR1
07h
USCI modulation control
UCA0MCTL
08h
USCI status
UCA0STAT
0Ah
USCI receive buffer
UCA0RXBUF
0Ch
USCI transmit buffer
UCA0TXBUF
0Eh
USCI LIN control
UCA0ABCTL
10h
USCI IrDA transmit control
UCA0IRTCTL
12h
USCI IrDA receive control
UCA0IRRCTL
13h
USCI interrupt enable
UCA0IE
1Ch
USCI interrupt flags
UCA0IFG
1Dh
USCI interrupt vector word
UCA0IV
1Eh
62
Detailed Description
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SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
Table 6-34. USCI_B0 Registers (Base Address: 05E0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI synchronous control 1
UCB0CTL1
00h
USCI synchronous control 0
UCB0CTL0
01h
USCI synchronous bit rate 0
UCB0BR0
06h
USCI synchronous bit rate 1
UCB0BR1
07h
USCI synchronous status
UCB0STAT
0Ah
USCI synchronous receive buffer
UCB0RXBUF
0Ch
USCI synchronous transmit buffer
UCB0TXBUF
0Eh
USCI I2C own address
UCB0I2COA
10h
USCI I2C slave address
UCB0I2CSA
12h
USCI interrupt enable
UCB0IE
1Ch
USCI interrupt flags
UCB0IFG
1Dh
USCI interrupt vector word
UCB0IV
1Eh
Table 6-35. USCI_A1 Registers (Base Address: 0600h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI control 1
UCA1CTL1
00h
USCI control 0
UCA1CTL0
01h
USCI baud rate 0
UCA1BR0
06h
USCI baud rate 1
UCA1BR1
07h
USCI modulation control
UCA1MCTL
08h
USCI status
UCA1STAT
0Ah
USCI receive buffer
UCA1RXBUF
0Ch
USCI transmit buffer
UCA1TXBUF
0Eh
USCI LIN control
UCA1ABCTL
10h
USCI IrDA transmit control
UCA1IRTCTL
12h
USCI IrDA receive control
UCA1IRRCTL
13h
USCI interrupt enable
UCA1IE
1Ch
USCI interrupt flags
UCA1IFG
1Dh
USCI interrupt vector word
UCA1IV
1Eh
Detailed Description
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Table 6-36. USCI_B1 Registers (Base Address: 0620h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI synchronous control 1
UCB1CTL1
00h
USCI synchronous control 0
UCB1CTL0
01h
USCI synchronous bit rate 0
UCB1BR0
06h
USCI synchronous bit rate 1
UCB1BR1
07h
USCI synchronous status
UCB1STAT
0Ah
USCI synchronous receive buffer
UCB1RXBUF
0Ch
USCI synchronous transmit buffer
UCB1TXBUF
0Eh
USCI I2C own address
UCB1I2COA
10h
USCI I2C slave address
UCB1I2CSA
12h
USCI interrupt enable
UCB1IE
1Ch
USCI interrupt flags
UCB1IFG
1Dh
USCI interrupt vector word
UCB1IV
1Eh
Table 6-37. USCI_A2 Registers (Base Address: 0640h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI control 1
UCA2CTL1
00h
USCI control 0
UCA2CTL0
01h
USCI baud rate 0
UCA2BR0
06h
USCI baud rate 1
UCA2BR1
07h
USCI modulation control
UCA2MCTL
08h
USCI status
UCA2STAT
0Ah
USCI receive buffer
UCA2RXBUF
0Ch
USCI transmit buffer
UCA2TXBUF
0Eh
USCI LIN control
UCA2ABCTL
10h
USCI IrDA transmit control
UCA2IRTCTL
12h
USCI IrDA receive control
UCA2IRRCTL
13h
USCI interrupt enable
UCA2IE
1Ch
USCI interrupt flags
UCA2IFG
1Dh
USCI interrupt vector word
UCA2IV
1Eh
64
Detailed Description
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Table 6-38. USCI_B2 Registers (Base Address: 0660h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI synchronous control 1
UCB2CTL1
00h
USCI synchronous control 0
UCB2CTL0
01h
USCI synchronous bit rate 0
UCB2BR0
06h
USCI synchronous bit rate 1
UCB2BR1
07h
USCI synchronous status
UCB2STAT
0Ah
USCI synchronous receive buffer
UCB2RXBUF
0Ch
USCI synchronous transmit buffer
UCB2TXBUF
0Eh
USCI I2C own address
UCB2I2COA
10h
USCI I2C slave address
UCB2I2CSA
12h
USCI interrupt enable
UCB2IE
1Ch
USCI interrupt flags
UCB2IFG
1Dh
USCI interrupt vector word
UCB2IV
1Eh
Table 6-39. USCI_A3 Registers (Base Address: 0680h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI control 1
UCA3CTL1
00h
USCI control 0
UCA3CTL0
01h
USCI baud rate 0
UCA3BR0
06h
USCI baud rate 1
UCA3BR1
07h
USCI modulation control
UCA3MCTL
08h
USCI status
UCA3STAT
0Ah
USCI receive buffer
UCA3RXBUF
0Ch
USCI transmit buffer
UCA3TXBUF
0Eh
USCI LIN control
UCA3ABCTL
10h
USCI IrDA transmit control
UCA3IRTCTL
12h
USCI IrDA receive control
UCA3IRRCTL
13h
USCI interrupt enable
UCA3IE
1Ch
USCI interrupt flags
UCA3IFG
1Dh
USCI interrupt vector word
UCA3IV
1Eh
Table 6-40. USCI_B3 Registers (Base Address: 06A0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI synchronous control 1
UCB3CTL1
00h
USCI synchronous control 0
UCB3CTL0
01h
USCI synchronous bit rate 0
UCB3BR0
06h
USCI synchronous bit rate 1
UCB3BR1
07h
USCI synchronous status
UCB3STAT
0Ah
USCI synchronous receive buffer
UCB3RXBUF
0Ch
USCI synchronous transmit buffer
UCB3TXBUF
0Eh
USCI I2C own address
UCB3I2COA
10h
USCI I2C slave address
UCB3I2CSA
12h
USCI interrupt enable
UCB3IE
1Ch
USCI interrupt flags
UCB3IFG
1Dh
USCI interrupt vector word
UCB3IV
1Eh
Detailed Description
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Table 6-41. ADC12_A Registers (Base Address: 0700h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Control 0
ADC12CTL0
00h
Control 1
ADC12CTL1
02h
Control 2
ADC12CTL2
04h
Interrupt flag
ADC12IFG
0Ah
Interrupt enable
ADC12IE
0Ch
Interrupt vector word
ADC12IV
0Eh
ADC memory control 0
ADC12MCTL0
10h
ADC memory control 1
ADC12MCTL1
11h
ADC memory control 2
ADC12MCTL2
12h
ADC memory control 3
ADC12MCTL3
13h
ADC memory control 4
ADC12MCTL4
14h
ADC memory control 5
ADC12MCTL5
15h
ADC memory control 6
ADC12MCTL6
16h
ADC memory control 7
ADC12MCTL7
17h
ADC memory control 8
ADC12MCTL8
18h
ADC memory control 9
ADC12MCTL9
19h
ADC memory control 10
ADC12MCTL10
1Ah
ADC memory control 11
ADC12MCTL11
1Bh
ADC memory control 12
ADC12MCTL12
1Ch
ADC memory control 13
ADC12MCTL13
1Dh
ADC memory control 14
ADC12MCTL14
1Eh
ADC memory control 15
ADC12MCTL15
1Fh
Conversion memory 0
ADC12MEM0
20h
Conversion memory 1
ADC12MEM1
22h
Conversion memory 2
ADC12MEM2
24h
Conversion memory 3
ADC12MEM3
26h
Conversion memory 4
ADC12MEM4
28h
Conversion memory 5
ADC12MEM5
2Ah
Conversion memory 6
ADC12MEM6
2Ch
Conversion memory 7
ADC12MEM7
2Eh
Conversion memory 8
ADC12MEM8
30h
Conversion memory 9
ADC12MEM9
32h
Conversion memory 10
ADC12MEM10
34h
Conversion memory 11
ADC12MEM11
36h
Conversion memory 12
ADC12MEM12
38h
Conversion memory 13
ADC12MEM13
3Ah
Conversion memory 14
ADC12MEM14
3Ch
Conversion memory 15
ADC12MEM15
3Eh
66
Detailed Description
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6.10 Input/Output Diagrams
6.10.1 Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
Figure 6-2 shows the port diagram. Table 6-42 summarizes the selection of the pin function.
Pad Logic
P1REN.x
P1DIR.x
0
0
Module X OUT
1
0
DVCC
1
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1IN.x
EN
Module X IN
1
Direction
0: Input
1: Output
1
P1OUT.x
DVSS
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
P1.6/SMCLK
P1.7
D
P1IE.x
EN
P1IRQ.x
Q
P1IFG.x
P1SEL.x
P1IES.x
Set
Interrupt
Edge
Select
Figure 6-2. Port P1 (P1.0 to P1.7) Diagram
Detailed Description
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Table 6-42. Port P1 (P1.0 to P1.7) Pin Functions
PIN NAME (P1.x)
x
FUNCTION
P1.0 (I/O)
P1.0/TA0CLK/ACLK
0
TA0.TA0CLK
ACLK
P1.1 (I/O)
P1.1/TA0.0
1
TA0.CCI0A
TA0.0
P1.2 (I/O)
P1.2/TA0.1
2
TA0.CCI1A
TA0.1
3
4
5
P1.6/SMCLK
6
P1.7
7
68
Detailed Description
0
0
1
1
1
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
0
1
1
0
TA0.CCI2A
0
1
TA0.2
1
1
I: 0; O: 1
0
TA0.CCI3A
0
1
TA0.3
1
1
P1.5 (I/O)
P1.5/TA0.4
P1SEL.x
1
P1.4 (I/O)
P1.4/TA0.3
P1DIR.x
I: 0; O: 1
I: 0; O: 1
P1.3 (I/O)
P1.3/TA0.2
CONTROL BITS OR SIGNALS
I: 0; O: 1
0
TA0.CCI4A
0
1
TA0.4
1
1
I: 0; O: 1
0
1
1
I: 0; O: 1
0
P1.6 (I/O)
SMCLK
P1.7 (I/O)
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6.10.2 Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger
Figure 6-3 shows the port diagram. Table 6-43 summarizes the selection of the pin function.
Pad Logic
P2REN.x
P2DIR.x
0
0
Module X OUT
1
0
DVCC
1
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2IN.x
EN
Module X IN
1
Direction
0: Input
1: Output
1
P2OUT.x
DVSS
P2.0/TA1CLK/MCLK
P2.1/TA1.0
P2.2/TA1.1
P2.3/TA1.2
P2.4/RTCCLK
P2.5
P2.6/ACLK
P2.7/ADC12CLK/DMAE0
D
P2IE.x
EN
P2IRQ.x
Q
P2IFG.x
P2SEL.x
P2IES.x
Set
Interrupt
Edge
Select
Figure 6-3. Port P2 (P2.0 to P2.7) Diagram
Detailed Description
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Table 6-43. Port P2 (P2.0 to P2.7) Pin Functions
PIN NAME (P2.x)
P2.0/TA1CLK/MCLK
x
0
FUNCTION
P2DIR.x
P2SEL.x
P2.0 (I/O)
I: 0; O: 1
0
TA1CLK
0
1
MCLK
P2.1 (I/O)
P2.1/TA1.0
1
TA1.CCI0A
TA1.0
P2.2 (I/O)
P2.2/TA1.1
2
TA1.CCI1A
TA1.1
3
P2.4/RTCCLK
4
P2.5
5
P2.6/ACLK
6
70
Detailed Description
7
1
0
0
1
1
1
I: 0; O: 1
0
0
1
1
1
0
TA1.CCI2A
0
1
TA1.2
1
1
P2.4 (I/O)
I: 0; O: 1
0
RTCCLK
1
1
P2.5 (I/O
I: 0; O: 1
0
P2.6 (I/O)
I: 0; O: 1
0
1
1
I: 0; O: 1
0
DMAE0
0
1
ADC12CLK
1
1
ACLK
P2.7 (I/O)
P2.7/ADC12CLK/DMAE0
1
I: 0; O: 1
I: 0; O: 1
P2.3 (I/O)
P2.3/TA1.2
CONTROL BITS OR SIGNALS
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SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
6.10.3 Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger
Figure 6-4 shows the port diagram. Table 6-44 summarizes the selection of the pin function.
Pad Logic
P3REN.x
P3DIR.x
0
0
Module X OUT
1
0
DVCC
1
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3IN.x
EN
Module X IN
1
Direction
0: Input
1: Output
1
P3OUT.x
DVSS
P3.0/UB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/USC0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
P3.6/UCB1STE/UCA1CLK
P3.7/UCB1SIMO/UCB1SDA
D
Figure 6-4. Port P3 (P3.0 to P3.7) Diagram
Table 6-44. Port P3 (P3.0 to P3.7) Pin Functions
PIN NAME (P3.x)
P3.0/UCB0STE/UCA0CLK
x
0
P3.1/UCB0SIMO/UCB0SDA
1
P3.2/UCB0SOMI/UCB0SCL
2
P3.3/UCB0CLK/UCA0STE
3
P3.4/UCA0TXD/UCA0SIMO
4
P3.5/UCA0RXD/UCA0SOMI
5
P3.6/UCB1STE/UCA1CLK
6
P3.7/UCB1SIMO/UCB1SDA
7
(1)
(2)
(3)
(4)
(5)
FUNCTION
P3.0 (I/O)
UCB0STE/UCA0CLK (2)
(3)
P3.1 (I/O)
UCB0SIMO/UCB0SDA (2)
(4)
P3.2 (I/O)
UCB0SOMI/UCB0SCL (2)
(4)
P3.3 (I/O)
UCB0CLK/UCA0STE
(2)
P3.4 (I/O)
UCA0TXD/UCA0SIMO (2)
P3.5 (I/O)
UCA0RXD/UCA0SOMI (2)
P3.6 (I/O)
UCB1STE/UCA1CLK (2)
(5)
P3.7 (I/O)
UCB1SIMO/UCB1SDA (2)
(4)
CONTROL BITS OR SIGNALS (1)
P3DIR.x
P3SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
X = Don't care
The pin direction is controlled by the USCI module.
UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI B0 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
UCA1CLK function takes precedence over UCB1STE function. If the pin is required as UCA1CLK input or output, USCI B1 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
Detailed Description
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6.10.4 Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
Figure 6-5 shows the port diagram. Table 6-45 summarizes the selection of the pin function.
Pad Logic
P4REN.x
P4DIR.x
0
0
Module X OUT
1
0
DVCC
1
P4DS.x
0: Low drive
1: High drive
P4SEL.x
P4IN.x
EN
Module X IN
1
Direction
0: Input
1: Output
1
P4OUT.x
DVSS
P4.0/TB0.0
P4.1/TB0.1
P4.2/TB0.2
P4.3/TB0.3
P4.4/TB0.4
P4.5/TB0.5
P4.6/TB0.6
P4.7/TB0CLK/SMCLK
D
Figure 6-5. Port P4 (P4.0 to P4.7) Diagram
72
Detailed Description
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SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
Table 6-45. Port P4 (P4.0 to P4.7) Pin Functions
PIN NAME (P4.x)
x
FUNCTION
4.0 (I/O)
P4.0/TB0.0
0
TB0.CCI0A and TB0.CCI0B
TB0.0
(1)
4.1 (I/O)
P4.1/TB0.1
1
TB0.CCI1A and TB0.CCI1B
TB0.1
(1)
4.2 (I/O)
P4.2/TB0.2
2
TB0.CCI2A and TB0.CCI2B
TB0.2
(1)
P4.4/TB0.5
P4.5/TB0.5
P4.6/TB0.6
P4.7/TB0CLK/SMCLK
(1)
3
4
5
6
7
P4DIR.x
P4SEL.x
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
TB0.CCI3A and TB0.CCI3B
0
1
TB0.3 (1)
1
1
4.4 (I/O)
4.3 (I/O)
P4.3/TB0.3
CONTROL BITS OR SIGNALS
I: 0; O: 1
0
TB0.CCI4A and TB0.CCI4B
0
1
TB0.4 (1)
1
1
4.5 (I/O)
I: 0; O: 1
0
TB0.CCI5A and TB0.CCI5B
0
1
TB0.5 (1)
1
1
4.6 (I/O)
I: 0; O: 1
0
TB0.CCI6A and TB0.CCI6B
0
1
TB0.6 (1)
1
1
4.7 (I/O)
I: 0; O: 1
0
TB0CLK
0
1
SMCLK
1
1
Setting TBOUTH causes all Timer_B configured outputs to be set to high impedance.
Detailed Description
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6.10.5 Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
Figure 6-6 shows the port diagram. Table 6-46 summarizes the selection of the pin function.
Pad Logic
To ADC12
INCHx = y
To/From
ADC12 Reference
P5REN.x
P5DIR.x
DVSS
0
DVCC
1
1
0
1
P5OUT.x
0
Module X OUT
1
P5DS.x
0: Low drive
1: High drive
P5SEL.x
P5.0/A8/VREF+/VeREF+
P5.1/A9/VREF–/VeREF–
P5IN.x
EN
Module X IN
Bus
Keeper
D
Figure 6-6. Port P5 (P5.0 and P5.1) Diagram
74
Detailed Description
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SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
Table 6-46. Port P5 (P5.0 and P5.1) Pin Functions
PIN NAME (P5.x)
P5.0/A8/VREF+/VeREF+
x
0
FUNCTION
P5DIR.x
P5SEL.x
REFOUT
P5.0 (I/O) (2)
I: 0; O: 1
0
X
VeREF+ (3)
X
1
0
X
1
1
X
1
0
P5.1 (I/O) (2)
I: 0; O: 1
0
X
VeREF– (6)
X
1
0
VREF– (7)
X
1
1
A9 (8)
X
1
0
VREF+
(4)
A8 (5)
P5.1/A9/VREF–/VeREF–
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
1
CONTROL BITS OR SIGNALS (1)
X = Don't care
Default condition
Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals. An external voltage can be applied to VeREF+ and used as the reference for the ADC12_A.
Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals. The ADC12_A, VREF+ reference is available at the pin.
When not using an external reference applied to VeREF+ or not outputting the internal reference to VREF+, A8 may be used as an
external ADC channel. Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents
when applying analog signals.
Setting the P5SEL.1 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals. An external voltage can be applied to VeREF- and used as the reference for the ADC12_A.
Setting the P5SEL.1 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals. The ADC12_A, VREF– reference is available at the pin.
When not using an external reference applied to VeREF+ or not outputting the internal reference to VREF+, A8 may be used as an
external ADC channel. Setting the P5SEL.1 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents
when applying analog signals.
Detailed Description
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6.10.6 Port P5, P5.2, Input/Output With Schmitt Trigger
Figure 6-7 shows the port diagram. Table 6-47 summarizes the selection of the pin function.
Pad Logic
To XT2
P5REN.2
P5DIR.2
DVSS
0
DVCC
1
1
0
1
P5OUT.2
0
Module X OUT
1
P5DS.2
0: Low drive
1: High drive
P5SEL.2
P5.2/XT2IN
P5IN.2
EN
Module X IN
Bus
Keeper
D
Figure 6-7. Port P5 (P5.2) Diagram
76
Detailed Description
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6.10.7 Port P5, P5.3, Input/Output With Schmitt Trigger
Figure 6-8 shows the port diagram. Table 6-47 summarizes the selection of the pin function.
Pad Logic
To XT2
P5REN.3
P5DIR.3
DVSS
0
DVCC
1
1
0
1
P5OUT.3
0
Module X OUT
1
P5.3/XT2OUT
P5DS.3
0: Low drive
1: High drive
P5SEL.3
P5IN.3
Bus
Keeper
EN
Module X IN
D
Figure 6-8. Port P5 (P5.3) Diagram
Table 6-47. Port P5 (P5.2 and P5.3) Pin Functions
PIN NAME (P5.x)
x
FUNCTION
P5.2 (I/O)
P5.2/XT2IN
2
(1)
(2)
(3)
3
P5DIR.x
P5SEL.2
P5SEL.3
XT2BYPASS
I: 0; O: 1
0
X
X
XT2IN crystal mode (2)
X
1
X
0
XT2IN bypass mode (2)
X
1
X
1
I: 0; O: 1
0
X
X
XT2OUT crystal mode (3)
X
1
X
0
P5.3 (I/O) (3)
X
1
X
1
P5.3 (I/O)
P5.3/XT2OUT
CONTROL BITS OR SIGNALS (1)
X = Don't care
Setting P5SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P5.2 is configured for crystal
mode or bypass mode.
Setting P5SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.3 can be used as
general-purpose I/O.
Detailed Description
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6.10.8 Port P5, P5.4 to P5.7, Input/Output With Schmitt Trigger
Figure 6-9 shows the port diagram. Table 6-48 summarizes the selection of the pin function.
Pad Logic
P5REN.x
P5DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P5OUT.x
DVSS
P5DS.x
0: Low drive
1: High drive
P5SEL.x
P5.4/UCB1SOMI/UCB1SCL
P5.5/UCB1CLK/UCA1STE
P5.6/UCA1TXD/UCA1SIMO
P5.7/UCA1RXD/UCA1SOMI
P5IN.x
EN
Module X IN
D
Figure 6-9. Port P5 (P5.4 to P5.7) Diagram
Table 6-48. Port P5 (P5.4 to P5.7) Pin Functions
PIN NAME (P5.x)
x
P5.4/UCB1SOMI/UCB1SCL
4
P5.5/UCB1CLK/UCA1STE
P5.6/UCA1TXD/UCA1SIMO
P5.7/UCA1RXD/UCA1SOMI
(1)
(2)
(3)
78
5
6
7
FUNCTION
P5.4 (I/O)
UCB1SOMI/UCB1SCL (2)
(3)
P5.5 (I/O)
UCB1CLK/UCA1STE
(2)
P5.6 (I/O)
UCA1TXD/UCA1SIMO (2)
P5.7 (I/O)
UCA1RXD/UCA1SOMI
(2)
CONTROL BITS OR SIGNALS (1)
P5DIR.x
P5SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
X = Don't care
The pin direction is controlled by the USCI module.
If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
Detailed Description
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SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
6.10.9 Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger
Figure 6-10 shows the port diagram. Table 6-49 summarizes the selection of the pin function.
Pad Logic
To ADC12
INCHx = y
P6REN.x
P6DIR.x
DVSS
0
DVCC
1
1
0
1
P6OUT.x
0
Module X OUT
1
P6DS.x
0: Low drive
1: High drive
P6SEL.x
P6IN.x
Bus
Keeper
EN
Module X IN
P6.0/A0
P6.1/A1
P6.2/A2
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7
D
Figure 6-10. Port P6 (P6.0 to P6.7) Diagram
Detailed Description
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Table 6-49. Port P6 (P6.0 to P6.7) Pin Functions
PIN NAME (P6.x)
x
P6.0/A0
0
P6.1/A1
1
P6.2/A2
2
P6.3/A3
3
P6.4/A4
4
P6.5/A5
5
P6.6/A6
6
P6.7/A7
(1)
(2)
(3)
80
7
FUNCTION
P6.0 (I/O)
A0 (2)
(3)
P6.1 (I/O)
A1 (2)
(3)
P6.2 (I/O)
A2 (2)
(3)
P6.3 (I/O)
A3 (2)
(3)
P6.4 (I/O)
A4 (2)
(3)
P6.5 (I/O)
A5 (1)
(2) (3)
P6.6 (I/O)
A6 (2)
(3)
P6.7 (I/O)
A7 (2)
(3)
CONTROL BITS OR SIGNALS (1)
P6DIR.x
P6SEL.x
INCHx
I: 0; O: 1
0
X
X
X
0
I: 0; O: 1
0
X
X
X
1
I: 0; O: 1
0
X
X
X
2
I: 0; O: 1
0
X
X
X
3
I: 0; O: 1
0
X
X
X
4
I: 0; O: 1
0
X
X
X
5
I: 0; O: 1
0
X
X
X
6
I: 0; O: 1
0
X
X
X
7
X = Don't care
Setting the P6SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals.
The ADC12_A channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
Detailed Description
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6.10.10 Port P7, P7.0, Input/Output With Schmitt Trigger
Figure 6-11 shows the port diagram. Table 6-50 summarizes the selection of the pin function.
Pad Logic
To XT1
P7REN.0
P7DIR.0
DVSS
0
DVCC
1
1
0
1
P7OUT.0
0
Module X OUT
1
P7DS.0
0: Low drive
1: High drive
P7SEL.0
P7.0/XIN
P7IN.0
Bus
Keeper
EN
Module X IN
D
Figure 6-11. Port P7 (P7.0) Diagram
Detailed Description
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6.10.11 Port P7, P7.1, Input/Output With Schmitt Trigger
Figure 6-12 shows the port diagram. Table 6-50 summarizes the selection of the pin function.
Pad Logic
To XT1
P7REN.1
P7DIR.1
DVSS
0
DVCC
1
1
0
1
P7OUT.1
0
Module X OUT
1
P7.1/XOUT
P7DS.1
0: Low drive
1: High drive
P7SEL.0
XT1BYPASS
P7IN.1
Bus
Keeper
EN
Module X IN
D
Figure 6-12. Port P7 (P7.1) Diagram
Table 6-50. Port P7 (P7.0 and P7.1) Pin Functions
PIN NAME (P7.x)
x
FUNCTION
P7DIR.x
P7SEL.0
P7SEL.1
XT1BYPASS
I: 0; O: 1
0
X
X
X
1
X
0
X
1
X
1
I: 0; O: 1
0
X
X
XOUT crystal mode (3)
X
1
X
0
P7.1 (I/O) (3)
X
1
X
1
P7.0 (I/O)
P7.0/XIN
0
XIN crystal mode
(2)
XIN bypass mode (2)
P7.1 (I/O)
P7.1/XOUT
(1)
(2)
(3)
82
1
CONTROL BITS OR SIGNALS (1)
X = Don't care
Setting P7SEL.0 causes the general-purpose I/O to be disabled. Pending the setting of XT1BYPASS, P7.0 is configured for crystal
mode or bypass mode.
Setting P7SEL.0 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P7.1 can be used as
general-purpose I/O.
Detailed Description
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MSP430F5419, MSP430F5418
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SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
6.10.12 Port P7, P7.2 and P7.3, Input/Output With Schmitt Trigger
Figure 6-13 shows the port diagram. Table 6-51 summarizes the selection of the pin function.
Pad Logic
P7REN.x
P7DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P7OUT.x
DVSS
P7.2/TB0OUTH/SVMOUT
P7.3/TA1.2
P7DS.x
0: Low drive
1: High drive
P7SEL.x
P7IN.x
EN
Module X IN
D
Figure 6-13. Port P7 (P7.2 and P7.3) Diagram
Table 6-51. Port P7 (P7.2 and P7.3) Pin Functions
PIN NAME (P7.x)
P7.2/TB0OUTH/SVMOUT
P7.3/TA1.2
x
2
3
FUNCTION
CONTROL BITS OR SIGNALS
P7DIR.x
P7SEL.x
P7.2 (I/O)
I: 0; O: 1
0
TB0OUTH
0
1
SVMOUT
1
1
P7.3 (I/O)
I: 0; O: 1
0
TA1.CCI2B
0
1
TA1.2
1
1
Detailed Description
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6.10.13 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger
Figure 6-14 shows the port diagram. Table 6-52 summarizes the selection of the pin function.
Pad Logic
To ADC12
INCHx = y
P7REN.x
P7DIR.x
DVSS
0
DVCC
1
1
0
1
P7OUT.x
0
Module X OUT
1
P7.4/A12
P7.5/A13
P7.6/A14
P7.7/A15
P7DS.x
0: Low drive
1: High drive
P7SEL.x
P7IN.x
Bus
Keeper
EN
Module X IN
D
Figure 6-14. Port P7 (P7.4 to P7.7) Diagram
Table 6-52. Port P7 (P7.4 to P7.7) Pin Functions
PIN NAME (P7.x)
x
P7.4/A12
4
P7.5/A13
5
P7.6/A14
6
P7.7/A15
7
(1)
(2)
(3)
84
FUNCTION
P7.4 (I/O)
A12 (2)
(3)
P7.5 (I/O)
A13 (2)
(3)
P7.6 (I/O)
A14 (2)
(3)
P7.7 (I/O)
A15
(2) (3)
CONTROL BITS OR SIGNALS (1)
P7DIR.x
P7SEL.x
INCHx
I: 0; O: 1
0
X
X
X
12
I: 0; O: 1
0
X
X
X
13
I: 0; O: 1
0
X
X
X
14
I: 0; O: 1
0
X
X
X
15
X = Don't care
Setting the P7SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals.
The ADC12_A channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
Detailed Description
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SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
6.10.14 Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger
Figure 6-15 shows the port diagram. Table 6-53 summarizes the selection of the pin function.
Pad Logic
P8REN.x
P8DIR.x
0
0
Module X OUT
1
0
DVCC
1
P8DS.x
0: Low drive
1: High drive
P8SEL.x
P8IN.x
EN
Module X IN
1
Direction
0: Input
1: Output
1
P8OUT.x
DVSS
P8.0/TA0.0
P8.1/TA0.1
P8.2/TA0.2
P8.3/TA0.3
P8.4/TA0.4
P8.5/TA1.0
P8.6/TA1.1
P8.7
D
Figure 6-15. Port P8 (P8.0 to P8.7) Diagram
Detailed Description
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Table 6-53. Port P8 (P8.0 to P8.7) Pin Functions
PIN NAME (P8.x)
x
FUNCTION
P8.0 (I/O)
P8.0/TA0.0
0
TA0.CCI0B
TA0.0
P8.1 (I/O)
P8.1/TA0.1
1
TA0.CCI1B
TA0.1
P8.2 (I/O)
P8.2/TA0.2
2
TA0.CCI2B
TA0.2
3
4
5
P8.7
86
6
7
Detailed Description
1
1
1
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
0
1
0
TA0.CCI3B
0
1
TA0.3
1
1
I: 0; O: 1
0
TA0.CCI4B
0
1
TA0.4
1
1
I: 0; O: 1
0
TA1.CCI0B
0
1
TA1.0
1
1
P8.6 (I/O)
P8.6/TA1.1
0
0
1
P8.5 (I/O)
P8.5/TA1.0
P8SEL.x
1
P8.4 (I/O)
P8.4/TA0.4
P8DIR.x
I: 0; O: 1
I: 0; O: 1
P8.3 (I/O)
P8.3/TA0.3
CONTROL BITS OR SIGNALS
I: 0; O: 1
0
TA1.CCI1B
0
1
TA1.1
1
1
I: 0; O: 1
0
P8.7 (I/O)
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SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
6.10.15 Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger
Figure 6-16 shows the port diagram. Table 6-54 summarizes the selection of the pin function.
Pad Logic
P9REN.x
P9DIR.x
0
0
Module X OUT
1
0
DVCC
1
P9DS.x
0: Low drive
1: High drive
P9SEL.x
P9IN.x
EN
Module X IN
1
Direction
0: Input
1: Output
1
P9OUT.x
DVSS
P9.0/UCB2STE/UCA2CLK
P9.1/UCB2SIMO/UCB2SDA
P9.2/UCB2SOMI/UCB2SCL
P9.3/UCB2CLK/UCA2STE
P9.4/UCA2TXD/UCA2SIMO
P9.5/UCA2RXD/UCA2SOMI
P9.6
P9.7
D
Figure 6-16. Port P9 (P9.0 to P9.7) Diagram
Table 6-54. Port P9 (P9.0 to P9.7) Pin Functions
PIN NAME (P9.x)
P9.0/UCB2STE/UCA2CLK
x
0
P9.1/UCB2SIMO/UCB2SDA
1
P9.2/UCB2SOMI/UCB2SCL
2
P9.3/UCB2CLK/UCA2STE
3
FUNCTION
P9.0 (I/O)
UCB2STE/UCA2CLK (2)
(3)
P9.1 (I/O)
UCB2SIMO/UCB2SDA (2)
(4)
P9.2 (I/O)
UCB2SOMI/UCB2SCL (2)
P9.3 (I/O)
UCB2CLK/UCA2STE
(2)
P9.4 (I/O)
(4)
CONTROL BITS OR SIGNALS (1)
P9DIR.x
P9SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
P9.4/UCA2TXD/UCA2SIMO
4
P9.5/UCA2RXD/UCA2SOMI
5
P9.6
6
P9.6 (I/O)
I: 0; O: 1
0
P9.7
7
P9.7 (I/O)
I: 0; O: 1
0
(1)
(2)
(3)
(4)
UCA2TXD/UCA2SIMO (2)
P9.5 (I/O)
UCA2RXD/UCA2SOMI (2)
X = Don't care
The pin direction is controlled by the USCI module.
UCB2CLK function takes precedence over UCA2STE function. If the pin is required as UCB2CLK input or output, USCI_A2 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
Detailed Description
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6.10.16 Port P10, P10.0 to P10.7, Input/Output With Schmitt Trigger
Figure 6-17 shows the port diagram. Table 6-55 summarizes the selection of the pin function.
Pad Logic
P10REN.x
P10DIR.x
0
0
Module X OUT
1
0
DVCC
1
P10DS.x
0: Low drive
1: High drive
P10SEL.x
P10IN.x
EN
Module X IN
1
Direction
0: Input
1: Output
1
P10OUT.x
DVSS
P10.0/UCB3STE/UCA3CLK
P10.1/UCB3SIMO/UCB3SDA
P10.2/UCB3SOMI/UCB3SCL
P10.3/UCB3CLK/UCA3STE
P10.4/UCA3TXD/UCA3SIMO
P10.5/UCA3RXD/UCA3SOMI
P10.6
P10.7
D
Figure 6-17. Port P10 (P10.0 to P10.7) Diagram
88
Detailed Description
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SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
Table 6-55. Port P10 (P10.0 to P10.7) Pin Functions
PIN NAME (P10.x)
x
P10.0/UCB3STE/UCA3CLK
0
P10.1/UCB3SIMO/UCB3SDA
1
P10.2/UCB3SOMI/UCB3SCL
2
P10.3/UCB3CLK/UCA3STE
3
P10.4/UCA3TXD/UCA3SIMO
4
P10.5/UCA3RXD/UCA3SOMI
5
P10.6
6
P10.7
7
FUNCTION
P10.0 (I/O)
UCB3STE/UCA3CLK (2)
P10.1 (I/O)
UCB3SIMO/UCB3SDA (2)
(4)
(5)
(4)
P10.2 (I/O)
UCB3SOMI/UCB3SCL
(2) (4)
P10DIR.x
P10SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
P10.6 (I/O)
I: 0; O: 1
0
Reserved (5)
X
1
P10.7 (I/O)
I: 0; O: 1
0
x
1
P10.3 (I/O)
UCB3CLK/UCA3STE (2)
P10.4 (I/O)
UCA3TXD/UCA3SIMO (2)
P10.5 (I/O)
UCA3RXD/UCA3SOMI (2)
Reserved
(1)
(2)
(3)
(3)
CONTROL BITS OR SIGNALS (1)
(5)
X = Don't care
The pin direction is controlled by the USCI module.
UCA3CLK function takes precedence over UCB3STE function. If the pin is required as UCA3CLK input or output, USCI_B3 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
The secondary functions on these pins are reserved for factory test purposes. Application should keep the P10SEL.x of these ports
cleared to prevent potential conflicts with the application.
Detailed Description
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6.10.17 Port P11, P11.0 to P11.2, Input/Output With Schmitt Trigger
Figure 6-18 shows the port diagram. Table 6-56 summarizes the selection of the pin function.
Pad Logic
P11REN.x
P11DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P11OUT.x
DVSS
P11.0/ACLK
P11.1/MCLK
P11.2/SMCLK
P11DS.x
0: Low drive
1: High drive
P11SEL.x
P11IN.x
EN
D
Module X IN
Figure 6-18. Port P11 (P11.0 to P11.2) Diagram
Table 6-56. Port P11 (P11.0 to P11.2) Pin Functions
PIN NAME (P11.x)
P11.0/ACLK
P11.1/MCLK
P11.2/SMCLK
90
Detailed Description
x
0
1
2
FUNCTION
P11.0 (I/O)
ACLK
P11.1 (I/O)
MCLK
P11.2 (I/O)
SMCLK
CONTROL BITS OR SIGNALS
P11DIR.x
P11SEL.x
I: 0; O: 1
0
1
1
I: 0; O: 1
0
1
1
I: 0; O: 1
0
1
1
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SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
6.10.18 Port J, J.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
Figure 6-19 shows the port diagram. Table 6-57 summarizes the selection of the pin function.
Pad Logic
PJREN.0
PJDIR.0
0
DVCC
1
PJOUT.0
0
From JTAG
1
DVSS
0
DVCC
1
PJDS.0
0: Low drive
1: High drive
From JTAG
1
PJ.0/TDO
PJIN.0
EN
D
Figure 6-19. Port PJ (PJ.0) Diagram
Detailed Description
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6.10.19 Port J, J.1 to J.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt
Trigger or Output
Figure 6-20 shows the port diagram. Table 6-57 summarizes the selection of the pin function.
Pad Logic
PJREN.x
PJDIR.x
0
DVSS
1
PJOUT.x
0
From JTAG
1
DVSS
0
DVCC
1
PJDS.x
0: Low drive
1: High drive
From JTAG
1
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
PJIN.x
EN
D
To JTAG
Figure 6-20. Port PJ (PJ.1 to PJ.3) Diagram
Table 6-57. Port PJ (PJ.0 to PJ.3) Pin Functions
PIN NAME (PJ.x)
x
CONTROL BITS OR
SIGNALS (1)
FUNCTION
PJDIR.x
PJ.0/TDO
0
PJ.1/TDI/TCLK
PJ.2/TMS
2
PJ.3/TCK
(1)
(2)
(3)
(4)
92
1
3
PJ.0 (I/O) (2)
I: 0; O: 1
TDO (3)
X
PJ.1 (I/O)
(2)
TDI/TCLK (3)
I: 0; O: 1
(4)
X
PJ.2 (I/O) (2)
TMS (3)
I: 0; O: 1
(4)
X
PJ.3 (I/O) (2)
TCK (3)
I: 0; O: 1
(4)
X
X = Don't care
Default condition
The pin direction is controlled by the JTAG module.
In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.
Detailed Description
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SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
6.11 TLV (Device Descriptor) Structures
Table 6-58 lists the complete contents of the device descriptor tag-length-value (TLV) structure.
Table 6-58. Device Descriptor Table (1)
SIZE
(bytes)
F5438
F5437
F5436
F5435
F5419
F5418
Info length
01A00h
1
06h
06h
06h
06h
06h
06h
CRC length
01A01h
1
06h
06h
06h
06h
06h
06h
CRC value
01A02h
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Device ID
01A04h
1
54h
54h
54h
54h
54h
54h
Info Block
Die Record
ADC12
Calibration
Device ID
01A05h
1
38h
37h
36h
35h
19h
18h
Hardware revision
01A06h
1
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Firmware revision
01A07h
1
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Die record tag
01A08h
1
08h
08h
08h
08h
08h
08h
Die record length
01A09h
1
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
Lot/wafer ID
01A0Ah
4
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Die X position
01A0Eh
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Die Y position
01A10h
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Test results
01A12h
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC12 calibration tag
01A14h
1
10h
10h
10h
10h
10h
10h
ADC12 calibration length
01A15h
1
10h
10h
10h
10h
10h
10h
ADC gain factor
01A16h
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC offset
01A18h
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 1.5-V reference factor
01A1Ah
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 1.5-V reference
Temperature sensor 30°C
01A1Ch
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 1.5-V reference
Temperature sensor 85°C
01A1Eh
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 2.5-V reference factor
01A20h
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 2.5-V reference
Temperature sensor 30°C
01A22h
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 2.5-V reference
Temperature sensor 85°C
01A24h
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Peripheral descriptor tag
01A26h
1
02h
02h
02h
02h
02h
02h
Peripheral descriptor length
01A27h
1
5Dh
55h
5Eh
56h
5Dh
55h
Memory 1
2
08h
8Ah
08h
8Ah
08h
8Ah
08h
8Ah
08h
8Ah
08h
8Ah
Memory 2
2
0Ch
86h
0Ch
86h
0Ch
86h
0Ch
86h
0Ch
86h
0Ch
86h
Memory 3
2
0Eh
30h
0Eh
30h
0Eh
30h
0Eh
30h
0Eh
30h
0Eh
30h
Memory 4
2
2Eh
98h
2Eh
98h
2Eh
97h
2Eh
97h
2Eh
96h
2Eh
96h
Memory 5
0/1
N/A
N/A
94h
94h
N/A
N/A
Delimiter
1
00h
00h
00h
00h
00h
00h
Peripheral count
1
1Fh
1Bh
1Fh
1Fh
1Fh
1Bh
2
00h
23h
00h
23h
00h
23h
00h
23h
00h
23h
00h
23h
Peripheral
Descriptor
MSP430CPUXV2
(1)
VALUE
ADDRESS
DESCRIPTION
N/A = Not applicable
Detailed Description
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Table 6-58. Device Descriptor Table(1) (continued)
DESCRIPTION
Peripheral
Descriptor
(continued)
94
ADDRESS
SIZE
(bytes)
VALUE
F5438
F5437
F5436
F5435
F5419
F5418
SBW
2
00h
0Fh
00h
0Fh
00h
0Fh
00h
0Fh
00h
0Fh
00h
0Fh
EEM-8
2
00h
05h
00h
05h
00h
05h
00h
05h
00h
05h
00h
05h
TI BSL
2
00h
FCh
00h
FCh
00h
FCh
00h
FCh
00h
FCh
00h
FCh
Package
2
00h
1Fh
00h
1Fh
00h
1Fh
00h
1Fh
00h
1Fh
00h
1Fh
SFR
2
10h
41h
10h
41h
10h
41h
10h
41h
10h
41h
10h
41h
PMM
2
02h
30h
02h
30h
02h
30h
02h
30h
02h
30h
02h
30h
FCTL
2
02h
38h
02h
38h
02h
38h
02h
38h
02h
38h
02h
38h
CRC16
2
01h
3Dh
01h
3Dh
01h
3Dh
01h
3Dh
01h
3Dh
01h
3Dh
RAMCTL
2
00h
44h
00h
44h
00h
44h
00h
44h
00h
44h
00h
44h
WDT_A
2
00h
40h
00h
40h
00h
40h
00h
40h
00h
40h
00h
40h
UCS
2
01h
48h
01h
48h
01h
48h
01h
48h
01h
48h
01h
48h
SYS
2
02h
42h
02h
42h
02h
42h
02h
42h
02h
42h
02h
42h
Port 1 and 2
2
08h
51h
08h
51h
08h
51h
08h
51h
08h
51h
08h
51h
Port 3 and 4
2
02h
52h
02h
52h
02h
52h
02h
52h
02h
52h
02h
52h
Port 5 and 6
2
02h
53h
02h
53h
02h
53h
02h
53h
02h
53h
02h
53h
Port 7 and 8
2
02h
54h
02h
54h
02h
54h
02h
54h
02h
54h
02h
54h
Port 9 and 10
2
02h
55h
N/A
02h
55h
N/A
02h
55h
N/A
Port 11 and 12
2
02h
56h
N/A
02h
56h
N/A
02h
56h
N/A
JTAG
2
08h
5Fh
0Ch
5F
08h
5Fh
0Ch
5F
08h
5Fh
0Ch
5F
TA0
2
02h
62h
02h
62h
02h
62h
02h
62h
02h
62h
02h
62h
TA1
2
04h
61h
04h
61h
04h
61h
04h
61h
04h
61h
04h
61h
TB0
2
04h
67h
04h
67h
04h
67h
04h
67h
04h
67h
04h
67h
RTC
2
0Eh
68h
0Eh
68h
0Eh
68h
0Eh
68h
0Eh
68h
0Eh
68h
MPY32
2
02h
85h
02h
85h
02h
85h
02h
85h
02h
85h
02h
85h
DMA-3
2
04h
47h
04h
47h
04h
47h
04h
47h
04h
47h
04h
47h
USCI_A and USCI_B
2
0Ch
90h
0Ch
90h
0Ch
90h
0Ch
90h
0Ch
90h
0Ch
90h
Detailed Description
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MSP430F5419, MSP430F5418
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SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
Table 6-58. Device Descriptor Table(1) (continued)
DESCRIPTION
Peripheral
Descriptor
(continued)
Interrupts
ADDRESS
SIZE
(bytes)
VALUE
F5438
F5437
F5436
F5435
F5419
F5418
USCI_A and USCI_B
2
04h
90h
04h
90h
04h
90h
04h
90h
04h
90h
04h
90h
USCI_A and USCI_B
2
04h
90h
N/A
04h
90h
N/A
04h
90h
N/A
USCI_A and USCI_B
2
04h
90h
N/A
04h
90h
N/A
04h
90h
N/A
ADC12_A
2
08h
D0h
10h
D0h
08h
D0h
10h
D0h
08h
D0h
10h
D0h
TB0.CCIFG0
1
64h
64h
64h
64h
64h
64h
TB0.CCIFG1..6
1
65h
65h
65h
65h
65h
65h
WDTIFG
1
40h
40h
40h
40h
40h
40h
USCI_A0
1
90h
90h
90h
90h
90h
90h
USCI_B0
1
91h
91h
91h
91h
91h
91h
ADC12_A
1
D0h
D0h
D0h
D0h
D0h
D0h
TA0.CCIFG0
1
60h
60h
60h
60h
60h
60h
TA0.CCIFG1..4
1
61h
61h
61h
61h
61h
61h
USCI_A2
1
94h
01h
94h
01h
94h
01h
USCI_B2
1
95h
01h
95h
01h
95h
01h
DMA
1
46h
46h
46h
46h
46h
46h
TA1.CCIFG0
1
62h
62h
62h
62h
62h
62h
TA1.CCIFG1..2
1
63h
63h
63h
63h
63h
63h
P1
1
50h
50h
50h
50h
50h
50h
USCI_A1
1
92h
92h
92h
92h
92h
92h
USCI_B1
1
93h
93h
93h
93h
93h
93h
USCI_A3
1
96h
01h
96h
01h
96h
01h
USCI_B3
1
97h
01h
97h
01h
97h
01h
P2
1
51h
51h
51h
51h
51h
51h
RTC_A
1
68h
68h
68h
68h
68h
68h
Delimiter
1
00h
00h
00h
00h
00h
00h
Detailed Description
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7 Device and Documentation Support
7.1
Getting Started and Next Steps
For more information on the MSP430™ family of devices and the tools and libraries that are available to
help with your development, visit the Getting Started page.
7.2
Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS.
These prefixes represent evolutionary stages of product development from engineering prototypes (XMS)
through fully qualified production devices (MSP).
XMS – Experimental device that is not necessarily representative of the final device's electrical
specifications
MSP – Fully qualified production device
XMS devices are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices have been characterized fully, and the quality and reliability of the device have been
demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production
devices. TI recommends that these devices not be used in any production system because their expected
end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
temperature range, package type, and distribution format. Figure 7-1 provides a legend for reading the
complete device name.
96
Device and Documentation Support
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MSP430F5419, MSP430F5418
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SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
MSP 430 F 5 438 A I ZQW T -EP
Processor Family
Optional: Additional Features
MCU Platform
Optional: Tape and Reel
Device Type
Packaging
Series
Feature Set
Processor Family
Optional: Temperature Range
Optional: A = Revision
CC = Embedded RF Radio
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
430 = MSP430 low-power microcontroller platform
MCU Platform
Device Type
Memory Type
C = ROM
F = Flash
FR = FRAM
G = Flash or FRAM (Value Line)
L = No Nonvolatile Memory
Specialized Application
AFE = Analog Front End
BQ = Contactless Power
CG = ROM Medical
FE = Flash Energy Meter
FG = Flash Medical
FW = Flash Electronic Flow Meter
Series
1 = Up to 8 MHz
2 = Up to 16 MHz
3 = Legacy
4 = Up to 16 MHz with LCD
5 = Up to 25 MHz
6 = Up to 25 MHz with LCD
0 = Low-Voltage Series
Feature Set
Various levels of integration within a series
Optional: A = Revision
N/A
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging
http://www.ti.com/packaging
Optional: Tape and Reel
T = Small reel
R = Large reel
No markings = Tube or tray
Optional: Additional Features -EP = Enhanced Product (–40°C to 105°C)
-HT = Extreme Temperature Parts (–55°C to 150°C)
-Q1 = Automotive Q100 Qualified
Figure 7-1. Device Nomenclature
Device and Documentation Support
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7.3
www.ti.com
Tools and Software
All MSP microcontrollers are supported by a wide variety of software and hardware development tools.
Tools are available from TI and various third parties. See them all at MSP430 Ultra-Low-Power MCUs –
Tools & software.
Table 7-1 lists the debug features of the MSP430F543x MCUs. See the Code Composer Studio for
MSP430 User's Guide for details on the available features.
Table 7-1. Hardware Debug Features
MSP430
ARCHITECTURE
4-WIRE
JTAG
2-WIRE
JTAG
BREAKPOINTS
(N)
RANGE
BREAKPOINTS
CLOCK
CONTROL
STATE
SEQUENCER
TRACE
BUFFER
LPMx.5
DEBUGGING
SUPPORT
MSP430Xv2
Yes
Yes
8
Yes
Yes
Yes
Yes
No
Design Kits and Evaluation Modules
MSP-TS430PZ5x100 - 100-pin Target Development Board for MSP430F5x MCUs
The
MSPTS430PZ5X100 is a stand-alone ZIF socket target board used to program and debug the
MSP430 MCU in-system through the JTAG interface or the Spy Bi-Wire (2-wire JTAG)
protocol.
100-pin Target Development Board and MSP-FET Programmer Bundle for MSP430F5x MCUs
The
MSP-FET430U5x100 is a powerful flash emulation tool (FET) that includes the hardware and
software required to quickly begin application development on the MSP430 MCU. It includes
a ZIF socket target board (MSP-TS430PZ5x100) and a USB debugging interface (MSP-FET)
used to program and debug the MSP430 in-system through the JTAG interface or the Spy
Bi-Wire (2-wire JTAG) protocol. The flash memory can be erased and programmed in
seconds with only a few keystrokes, and since the MSP430 flash is ultra-low power, no
external power supply is required.
Software
MSP430Ware™ Software MSP430Ware software is a collection of code examples, data sheets, and
other design resources for all MSP430 devices delivered in a convenient package. In
addition to providing a complete collection of existing MSP430 design resources,
MSP430Ware software also includes a high-level API called MSP Driver Library. This library
makes it easy to program MSP430 hardware. MSP430Ware software is available as a
component of Code Composer Studio IDE or as a stand-alone package.
MSP430F534x Code Examples C code examples are available for every MSP device that configures
each of the integrated peripherals for various application needs.
MSP Driver Library Driver Library's abstracted API keeps you above the bits and bytes of the MSP430
hardware by providing easy-to-use function calls. Thorough documentation is delivered
through a helpful API Guide, which includes details on each function call and the recognized
parameters. Developers can use Driver Library functions to write complete projects with
minimal overhead.
MSP EnergyTrace™ Technology EnergyTrace technology for MSP430 microcontrollers is an energybased code analysis tool that measures and displays the application's energy profile and
helps to optimize it for ultra-low-power consumption.
ULP (Ultra-Low Power) Advisor ULP Advisor™ software is a tool for guiding developers to write more
efficient code to fully utilize the unique ultra-low power features of MSP and MSP432
microcontrollers. Aimed at both experienced and new microcontroller developers, ULP
Advisor checks your code against a thorough ULP checklist to squeeze every last nano amp
out of your application. At build time, ULP Advisor will provide notifications and remarks to
highlight areas of your code that can be further optimized for lower power.
IEC60730 Software Package The IEC60730 MSP430 software package was developed to be useful in
assisting customers in complying with IEC 60730-1:2010 (Automatic Electrical Controls for
Household and Similar Use – Part 1: General Requirements) for up to Class B products,
which includes home appliances, arc detectors, power converters, power tools, e-bikes, and
many others. The IEC60730 MSP430 software package can be embedded in customer
applications running on MSP430s to help simplify the customer’s certification efforts of
functional safety-compliant consumer devices to IEC 60730-1:2010 Class B.
98
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MSP430F5419, MSP430F5418
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Fixed Point Math Library for MSP The MSP IQmath and Qmath Libraries are a collection of highly
optimized and high-precision mathematical functions for C programmers to seamlessly port a
floating-point algorithm into fixed-point code on MSP430 and MSP432 devices. These
routines are typically used in computationally intensive real-time applications where optimal
execution speed, high accuracy, and ultra-low energy are critical. By using the IQmath and
Qmath libraries, it is possible to achieve execution speeds considerably faster and energy
consumption considerably lower than equivalent code written using floating-point math.
Floating Point Math Library for MSP430 Continuing to innovate in the low power and low cost
microcontroller space, TI brings you MSPMATHLIB. Leveraging the intelligent peripherals of
our devices, this floating point math library of scalar functions brings you up to 26x better
performance. Mathlib is easy to integrate into your designs. This library is free and is
integrated in both Code Composer Studio and IAR IDEs. Read the user’s guide for an in
depth look at the math library and relevant benchmarks.
Development Tools
Code Composer Studio™ Integrated Development Environment for MSP Microcontrollers
Code
Composer Studio is an integrated development environment (IDE) that supports all MSP
microcontroller devices. Code Composer Studio comprises a suite of embedded software
utilities used to develop and debug embedded applications. It includes an optimizing C/C++
compiler, source code editor, project build environment, debugger, profiler, and many other
features. The intuitive IDE provides a single user interface taking you through each step of
the application development flow. Familiar utilities and interfaces allow users to get started
faster than ever before. Code Composer Studio combines the advantages of the Eclipse
software framework with advanced embedded debug capabilities from TI resulting in a
compelling feature-rich development environment for embedded developers. When using
CCS with an MSP MCU, a unique and powerful set of plugins and embedded software
utilities are made available to fully leverage the MSP microcontroller.
Command-Line Programmer MSP Flasher is an open-source shell-based interface for programming
MSP microcontrollers through a FET programmer or eZ430 using JTAG or Spy-Bi-Wire
(SBW) communication. MSP Flasher can download binary files (.txt or .hex) files directly to
the MSP microcontroller without an IDE.
MSP MCU Programmer and Debugger The MSP-FET is a powerful emulation development tool – often
called a debug probe – which allows users to quickly begin application development on MSP
low-power microcontrollers (MCU). Creating MCU software usually requires downloading the
resulting binary program to the MSP device for validation and debugging. The MSP-FET
provides a debug communication pathway between a host computer and the target MSP.
Furthermore, the MSP-FET also provides a Backchannel UART connection between the
computer's USB interface and the MSP UART. This affords the MSP programmer a
convenient method for communicating serially between the MSP and a terminal running on
the computer. It also supports loading programs (often called firmware) to the MSP target
using the BSL (bootloader) through the UART and I2C communication protocols.
MSP-GANG Production Programmer The MSP Gang Programmer is an MSP430 or MSP432 device
programmer that can program up to eight identical MSP430 or MSP432 Flash or FRAM
devices at the same time. The MSP Gang Programmer connects to a host PC using a
standard RS-232 or USB connection and provides flexible programming options that allow
the user to fully customize the process. The MSP Gang Programmer is provided with an
expansion board, called the Gang Splitter, that implements the interconnections between the
MSP Gang Programmer and multiple target devices. Eight cables are provided that connect
the expansion board to eight target devices (through JTAG or Spy-Bi-Wire connectors). The
programming can be done with a PC or as a stand-alone device. A PC-side graphical user
interface is also available and is DLL-based.
Device and Documentation Support
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7.4
www.ti.com
Documentation Support
The following documents describe the MSP430F543x MCUs. Copies of these documents are available on
the Internet at www.ti.com.
Receiving Notification of Document Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for
your device on ti.com (for links to the product folders, see Section 7.5). In the upper right corner, click the
"Alert me" button. This registers you to receive a weekly digest of product information that has changed (if
any). For change details, check the revision history of any revised document.
Errata
MSP430F5438 Device Erratasheet Describes the known exceptions to the functional specifications for
this device.
MSP430F5437 Device Erratasheet Describes the known exceptions to the functional specifications for
this device.
MSP430F5436 Device Erratasheet Describes the known exceptions to the functional specifications for
this device.
MSP430F5435 Device Erratasheet Describes the known exceptions to the functional specifications for
this device.
MSP430F5419 Device Erratasheet Describes the known exceptions to the functional specifications for
this device.
MSP430F5418 Device Erratasheet Describes the known exceptions to the functional specifications for
this device.
User's Guides
MSP430F5xx and MSP430F6xx Family User's Guide
peripherals available in this device family.
Detailed information on the modules and
Code Composer Studio IDE for MSP430 User's Guide This user's guide describes how to use the TI
Code Composer Studio IDE with the MSP430 ultra-low-power microcontrollers.
MSP430 Flash Device Bootloader (BSL) User's Guide The MSP430 bootloader (BSL) lets users
communicate with embedded memory in the MSP430 microcontroller during the prototyping
phase, final production, and in service. Both the programmable memory (flash memory) and
the data memory (RAM) can be modified as required. Do not confuse the bootloader with the
bootstrap loader programs found in some digital signal processors (DSPs) that automatically
load program code (and data) from external memory to the internal memory of the DSP.
MSP430 Programming With the JTAG Interface This document describes the functions that are
required to erase, program, and verify the memory module of the MSP430 flash-based and
FRAM-based microcontroller families using the JTAG communication port. In addition, it
describes how to program the JTAG access security fuse that is available on all MSP430
devices. This document describes device access using both the standard 4-wire JTAG
interface and the 2-wire JTAG interface, which is also referred to as Spy-Bi-Wire (SBW).
MSP430 Hardware Tools User's Guide This manual describes the hardware of the TI MSP-FET430
Flash Emulation Tool (FET). The FET is the program development tool for the MSP430 ultralow-power microcontroller. Both available interface types, the parallel port interface and the
USB interface, are described.
100
Device and Documentation Support
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MSP430F5419, MSP430F5418
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SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
Application Reports
MSP430 32-kHz Crystal Oscillators Selection of the right crystal, correct load circuit, and proper board
layout are important for a stable crystal oscillator. This application report summarizes crystal
oscillator function and explains the parameters to select the correct crystal for MSP430 ultralow-power operation. In addition, hints and examples for correct board layout are given. The
document also contains detailed information on the possible oscillator tests to ensure stable
oscillator operation in mass production.
MSP430 System-Level ESD Considerations System-Level ESD has become increasingly demanding
with silicon technology scaling towards lower voltages and the need for designing costeffective and ultra-low-power components. This application report addresses three different
ESD topics to help board designers and OEMs understand and design robust system-level
designs: (1) Component-level ESD testing and system-level ESD testing, their differences
and why component-level ESD rating does not ensure system-level robustness. (2) General
design guidelines for system-level ESD protection at different levels including enclosures,
cables, PCB layout, and on-board ESD protection devices. (3) Introduction to System
Efficient ESD Design (SEED), a co-design methodology of on-board and on-chip ESD
protection to achieve system-level ESD robustness, with example simulations and test
results. A few real-world system-level ESD protection design examples and their results are
also discussed.
Advanced Debugging Using the Enhanced Emulation Module (EEM) With CCS v6 This document
describes the benefits of the Enhanced Emulation Module (EEM) advanced debugging
features that are available in the MSP430 devices and how they can be used with Code
Composer Studio (CCS) version 6 software development tool. The EEM advanced
debugging features support both precision analog and full-speed digital debugging. The
configuration of the debug environment for maximum control and the use of the embedded
trace capability are described. Some techniques that allow rapid development and designfor-testability are demonstrated.
7.5
Related Links
Table 7-2 lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 7-2. Related Links
7.6
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
MSP430F5438
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MSP430F5437
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MSP430F5436
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MSP430F5435
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MSP430F5419
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MSP430F5418
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Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At
e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow
engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
Device and Documentation Support
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Copyright © 2009–2018, Texas Instruments Incorporated
101
MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435
MSP430F5419, MSP430F5418
SLAS612F – AUGUST 2009 – REVISED SEPTEMBER 2018
7.7
www.ti.com
Trademarks
MSP430, MSP430Ware, EnergyTrace, ULP Advisor, Code Composer Studio, E2E are trademarks of
Texas Instruments.
All other trademarks are the property of their respective owners.
7.8
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
7.9
Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
authorization from U.S. Department of Commerce and other competent Government authorities to the
extent required by those laws.
7.10 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
8 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
102
Mechanical, Packaging, and Orderable Information
Copyright © 2009–2018, Texas Instruments Incorporated
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Product Folder Links: MSP430F5438 MSP430F5437 MSP430F5436 MSP430F5435 MSP430F5419 MSP430F5418
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
MSP430F5418IPN
NRND
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F5418
MSP430F5418IPNR
NRND
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F5418
MSP430F5419IPZ
NRND
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F5419
MSP430F5419IPZR
NRND
LQFP
PZ
100
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F5419
MSP430F5435IPN
NRND
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F5435
MSP430F5435IPNR
NRND
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F5435
MSP430F5436IPZ
NRND
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F5436
REV #
MSP430F5436IPZR
NRND
LQFP
PZ
100
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F5436
REV #
MSP430F5437IPN
NRND
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F5437
MSP430F5437IPNR
NRND
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F5437
MSP430F5438IPZ
NRND
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F5438
REV #
MSP430F5438IPZR
NRND
LQFP
PZ
100
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F5438
REV #
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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