MSP430F5508IRGCT

Product Folder Order Now Technical Documents Tools & Software Support & Community MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 MSP430F5510, MSP430F550x Mixed-Signal Microcontrollers 1 Device Overview 1.1 Features 1 • Low supply-voltage range: 3.6 V down to 1.8 V • Ultra-low power consumption – Active mode (AM) All system clocks active – 195 µA/MHz at 8 MHz, 3 V, flash program execution (typical) – 115 µA/MHz at 8 MHz, 3 V, RAM program execution (typical) – Standby mode (LPM3) – Real-time clock (RTC) with crystal, watchdog, and supply supervisor operational, full RAM retention, fast wakeup: 1.9 µA at 2.2 V, 2.1 µA at 3 V (typical) – Low-power oscillator (VLO), general-purpose counter, watchdog, and supply supervisor operational, full RAM retention, fast wakeup: 1.4 µA at 3 V (typical) – Off mode (LPM4) Full RAM retention, supply supervisor operational, fast wakeup: 1.1 µA at 3 V (typical) – Shutdown mode (LPM4.5) 0.18 µA at 3 V (typical) • Wake up from standby in less than 5 µs • 16-bit RISC architecture, extended memory, up to 25-MHz system clock • Flexible power-management system – Fully integrated LDO with programmable regulated core supply voltage – Supply voltage supervision, monitoring, and brownout • Unified clock system – FLL control loop for frequency stabilization – Low-power low-frequency internal clock source (VLO) – Low-frequency trimmed internal reference source (REFO) 1.2 • • • • • • • • • • • • • • • – 32-kHz watch crystals (XT1) – High-frequency crystals up to 32 MHz (XT2) 16-bit Timer TA0, Timer_A with five capture/compare registers 16-bit Timer TA1, Timer_A with three capture/compare registers 16-bit Timer TA2, Timer_A with three capture/compare registers 16-bit Timer TB0, Timer_B with seven capture/compare shadow registers Two universal serial communication interfaces (USCIs) – USCI_A0 and USCI_A1 each support: – Enhanced UART with automatic baud-rate detection – IrDA encoder and decoder – Synchronous SPI – USCI_B0 and USCI_B1 each support: – I2C – Synchronous SPI Full-speed universal serial bus (USB) – Integrated USB-PHY – Integrated 3.3-V and 1.8-V USB power system – Integrated USB-PLL – Eight input and eight output endpoints 10-bit analog-to-digital converter (ADC) with window comparator Comparator Hardware multiplier supports 32-bit operations Serial onboard programming, no external programming voltage needed Three-channel internal DMA Basic timer with RTC feature Device Comparison summarizes the available family members Applications Analog and digital sensor systems Data loggers • • Connectivity to USB hosts Wireless headsets 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 1.3 www.ti.com Description The TI MSP family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with extensive low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from lowpower modes to active mode in less than 5 µs. The MSP430F5510, MSP430F5509, and MSP430F5508 devices are microcontroller configurations with integrated USB and PHY supporting USB 2.0, four 16-bit timers, a high-performance 10-bit ADC, two USCIs (1), a hardware multiplier, DMA, an RTC module with alarm capabilities, and 31 or 47 I/O pins. The MSP430F5507, MSP430F5506, MSP430F5505, and MSP430F5504 devices are microcontroller configurations with integrated USB and PHY supporting USB 2.0, four 16-bit timers, a high-performance 10-bit ADC, one USCI, a hardware multiplier, DMA, an RTC module with alarm capabilities, and 31 I/O pins. The MSP430F5503, MSP430F5502, MSP430F5501, and MSP430F5500 devices include all of the MSP430F5507, MSP430F5506, MSP430F5505, and MSP430F5504 peripherals, except that they have a comparator instead of the 10-bit ADC. Typical applications include analog and digital sensor systems and data loggers that require connectivity to various USB hosts. For complete module descriptions, see the MSP430F5xx and MSP430F6xx Family User's Guide. (1) In the 48-pin packages, the USCI functions that are pinned out are limited to what the user configures on port 4 with the port mapping controller. It may not be possible to bring out all functions simultaneously. Device Information (1) PACKAGE BODY SIZE (2) VQFN (64) 9 mm × 9 mm MSP430F5510IPT LQFP (48) 7 mm × 7 mm MSP430F5510IRGZ VQFN (48) 7 mm × 7 mm MSP430F5510IZXH nFBGA (80) 5 mm × 5 mm MicroStar Junior™ BGA (80) 5 mm × 5 mm PART NUMBER MSP430F5510IRGC MSP430F5510IZQE (3) (1) (2) (3) 2 For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section 8, or see the TI website at www.ti.com. The sizes shown here are approximations. For the package dimensions with tolerances, see the Mechanical Data in Section 8. All orderable part numbers in the ZQE package have been changed to a status of Last Time Buy. Visit the Product life cycle page for details on this status. Device Overview Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com 1.4 SLAS645L – JULY 2009 – REVISED MAY 2020 Functional Block Diagrams Figure 1-1 shows the functional block diagram for the MSP430F5510, MSP430F5509, and MSP430F5508 devices in the RGC, ZQE, and ZXH packages. XIN XOUT RST/NMI DVCC DVSS VCORE AVCC AVSS P1.x XT2IN XT2OUT Unified Clock System ACLK SMCLK Flash MCLK CPUXV2 and Working Registers 32KB 24KB 16KB 4KB+2KB Power Management LDO SVM/SVS Brownout RAM SYS Watchdog Port Map Control (P4) PA P2.x P3.x PB P4.x P5.x PC P6.x I/O Ports P1/P2 2×8 I/Os Interrupt & Wakeup I/O Ports P3/P4 1×5 I/Os 1×8 I/Os I/O Ports P5/P6 1×6 I/Os 1×8 I/Os PA 1×16 I/Os PB 1×13 I/Os PC 1×14 I/Os REF COMP_B ADC10_A 10 Bit 200 KSPS 12 Channels (10 ext/ 2 int) Window Comparator MAB DMA MDB 3 Channel EEM (S:3+1) USCI0,1 TA0 JTAG/ SBW Interface MPY32 TA1 Timer_A 5 CC Registers Timer_A 3 CC Registers TA2 Timer_A 3 CC Registers TB0 Timer_B 7 CC Registers RTC_A CRC16 Ax: UART, IrDA, SPI Bx: SPI, I2C Full-speed USB USB-PHY USB-LDO USB-PLL DP,DM,PUR Copyright © 2016, Texas Instruments Incorporated Figure 1-1. Functional Block Diagram – RGC, ZXH, or ZQE Package – MSP430F5510, MSP430F5509, MSP430F5508 Figure 1-2 shows the functional block diagram for the MSP430F5510, MSP430F5509, and MSP430F5508 devices in the RGZ and PT packages. XIN XOUT RST/NMI DVCC DVSS VCORE AVCC AVSS P1.x XT2IN XT2OUT Unified Clock System ACLK SMCLK Flash MCLK CPUXV2 and Working Registers 32KB 24KB 16KB 4KB+2KB RAM Power Management LDO SVM, SVS, Brownout SYS Watchdog Port Map Control (P4) PA P2.x I/O Ports P1, P2 1×8 I/Os 1×1 I/Os Interrupt, Wakeup PA 1×9 I/Os PB P4.x P5.x PC P6.x I/O Ports P4 1×8 I/Os I/O Ports P5, P6 1×6 I/Os 1×4 I/Os PB 1×8 I/Os PC 1×10 I/Os REF COMP_B ADC10_A 10 Bit 200 ksps 8 Channels (6 ext, 2 int) Window Comparator MAB DMA MDB 3 Channel EEM (S:3+1) USCI0,1 JTAG, SBW Interface TA0 MPY32 Timer_A 5 CC Registers TA1 Timer_A 3 CC Registers TA2 Timer_A 3 CC Registers TB0 Timer_B 7 CC Registers RTC_A CRC16 Ax: UART, IrDA, SPI Bx: SPI, I2C Full-Speed USB USB-PHY USB-LDO USB-PLL DP,DM,PUR Copyright © 2016, Texas Instruments Incorporated NOTE: See Table 3-1 for limitations on the simultaneous availability of USCI module signals. Figure 1-2. Functional Block Diagram – RGZ or PT Package – MSP430F5510, MSP430F5509, MSP430F5508 Device Overview Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 3 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com Figure 1-3 shows the functional block diagram for the MSP430F5507, MSP430F5506, and MSP430F5505 devices in the RGZ package and the MSP430F5504 device in the RGZ and PT packages. XIN XOUT RST/NMI DVCC DVSS VCORE AVCC AVSS P1.x XT2IN XT2OUT Unified Clock System ACLK SMCLK MCLK CPUXV2 and Working Registers 32KB 24KB 16KB 8KB 4KB+2KB Power Management LDO SVM, SVS, Brownout RAM Flash SYS Watchdog Port Map Control (P4) PA P2.x I/O Ports P1, P2 1×8 I/Os 1×1 I/Os Interrupt, Wakeup PA 1×9 I/Os PB P4.x P5.x PC P6.x I/O Ports P4 1×8 I/Os I/O Ports P5, P6 1×6 I/Os 1×4 I/Os PB 1×8 I/Os PC 1×10 I/Os REF ADC10_A 10 Bit 200 ksps 8 Channels (6 int, 2 ext) Window Comparator MAB DMA MDB 3 Channel EEM (S:3+1) USCI1 TA0 JTAG, SBW Interface MPY32 TA1 Timer_A 5 CC Registers Timer_A 3 CC Registers TA2 Timer_A 3 CC Registers TB0 Timer_B 7 CC Registers RTC_A CRC16 A1: UART, IrDA, SPI B1: SPI, I2C Full-Speed USB USB-PHY USB-LDO USB-PLL DP,DM,PUR Copyright © 2016, Texas Instruments Incorporated Figure 1-3. Functional Block Diagram – RGZ or PT Package – MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 Figure 1-4 shows the functional block diagram for the MSP430F5503, MSP430F5502, MSP430F5501, and MSP430F5500 devices in the RGZ package. XIN XOUT RST/NMI DVCC DVSS VCORE AVCC AVSS P1.x XT2IN XT2OUT Unified Clock System ACLK SMCLK MCLK CPUXV2 and Working Registers 32KB 24KB 16KB 8KB 4KB+2KB RAM Flash Power Management LDO SVM, SVS, Brownout SYS Watchdog Port Map Control (P4) PA P2.x I/O Ports P1, P2 1×8 I/Os 1×1 I/Os Interrupt, Wakeup PA 1×9 I/Os PB P4.x P5.x PC P6.x I/O Ports P4 1×8 I/Os I/O Ports P5, P6 1×6 I/Os 1×4 I/Os PB 1×8 I/Os PC 1×10 I/Os REF COMP_B MAB DMA MDB 3 Channel EEM (S:3+1) JTAG, SBW Interface TA0 MPY32 Timer_A 5 CC Registers TA1 Timer_A 3 CC Registers TA2 Timer_A 3 CC Registers USCI1 TB0 Timer_B 7 CC Registers RTC_A CRC16 A1: UART, IrDA, SPI B1: SPI, I2C Full-Speed USB USB-PHY USB-LDO USB-PLL DP,DM,PUR Copyright © 2016, Texas Instruments Incorporated Figure 1-4. Functional Block Diagram – RGZ Package – MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 4 Device Overview Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 Table of Contents 1 Device Overview ......................................... 1 Features .............................................. 1 1.2 Applications ........................................... 1 5.27 Timer_A Description ............................................ 2 5.28 Timer_B Functional Block Diagrams ........................... 3 5.29 Revision History ......................................... 6 Device Comparison ..................................... 7 5.30 Related Products ..................................... 8 5.32 Terminal Configuration and Functions .............. 9 5.33 4.1 Pin Diagrams ......................................... 9 4.2 Signal Descriptions .................................. 14 5.34 5.35 1.4 3.1 4 5 Wake-up Times From Low-Power Modes and Reset ................................................ 35 1.1 1.3 2 3 5.26 5.31 Specifications ........................................... 19 5.11 5.12 5.13 5.14 40 10-Bit ADC, Power Supply and Input Range Conditions ........................................... 41 .................... 5.38 REF, External Reference 5.39 REF, Built-In Reference ............................. 43 5.40 Comparator B ....................................... 44 5.41 Ports PU.0 and PU.1 ................................ 45 5.42 USB Output Ports (DP and DM) .................... 47 Thermal Resistance Characteristics ................ 23 Schmitt-Trigger Inputs – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RST/NMI) ............................................ 24 Inputs – Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)......................... 24 Leakage Current – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RST/NMI) ............................................ 24 Outputs – General-Purpose I/O (Full Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3) ..... 24 Outputs – General-Purpose I/O (Reduced Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3) ..... 25 Output Frequency – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3) ..... 25 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0) ............................... 26 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1) ............................... 27 5.43 USB Input Ports (DP and DM) ...................... 47 5.44 USB-PWR (USB Power System) 5.45 USB-PLL (USB Phase-Locked Loop) ............... 48 5.46 Flash Memory ....................................... 48 5.47 JTAG and Spy-Bi-Wire Interface .................... 48 ........................................ 19 5.15 Crystal Oscillator, XT1, Low-Frequency Mode ...... 28 5.16 5.17 Crystal Oscillator, XT2 .............................. 29 Internal Very-Low-Power Low-Frequency Oscillator (VLO) ................................................ 30 Internal Reference, Low-Frequency Oscillator (REFO) .............................................. 30 5.18 36 38 Recommended Operating Conditions ............... 19 Active Mode Supply Current Into VCC Excluding External Current ..................................... 21 Low-Power Mode Supply Currents (Into VCC) Excluding External Current.......................... 22 ESD Ratings 5.10 36 10-Bit ADC, Linearity Parameters................... 42 5.3 5.4 5.9 36 10-Bit ADC, Timing Parameters 5.2 5.8 35 36 5.37 Absolute Maximum Ratings ......................... 19 5.6 5.7 35 5.36 5.1 5.5 ............................................. ............................................. USCI (UART Mode) Clock Frequency .............. USCI (UART Mode) ................................. USCI (SPI Master Mode) Clock Frequency ......... USCI (SPI Master Mode)............................ USCI (SPI Slave Mode) ............................. USCI (I2C Mode) .................................... 5.19 DCO Frequency ..................................... 31 5.20 PMM, Brownout Reset (BOR)....................... 32 5.21 PMM, Core Voltage ................................. 32 5.22 PMM, SVS High Side ............................... 33 5.23 PMM, SVM High Side ............................... 34 5.24 PMM, SVS Low Side ................................ 34 5.25 PMM, SVM Low Side ............................... 6 7 8 ........................... ................... 42 47 Detailed Description ................................... 49 6.1 CPU (Link to User's Guide) ......................... 49 6.2 Operating Modes .................................... 50 6.3 Interrupt Vector Addresses.......................... 51 6.4 Memory Organization ............................... 52 6.5 Bootloader (BSL) .................................... 53 6.6 JTAG Operation ..................................... 54 6.7 Flash Memory (Link to User's Guide) ............... 54 6.8 RAM (Link to User's Guide) ......................... 55 .......................................... 55 ................................. 65 6.11 Input/Output Diagrams .............................. 77 6.12 Device Descriptors .................................. 94 Device and Documentation Support .............. 100 7.1 Getting Started and Next Steps ................... 100 7.2 Device Nomenclature .............................. 100 7.3 Tools and Software ................................ 102 7.4 Documentation Support ............................ 104 7.5 Related Links ...................................... 105 7.6 Community Resources............................. 105 7.7 Trademarks ........................................ 106 7.8 Electrostatic Discharge Caution ................... 106 7.9 Export Control Notice .............................. 106 7.10 Glossary............................................ 106 6.9 Peripherals 6.10 Peripheral File Map Mechanical, Packaging, and Orderable Information ............................................. 107 35 Table of Contents Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 41 5 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com 2 Revision History Changes from September 21, 2018 to May 1, 2020 • • 6 Page Throughout the document, added the ZXH package ............................................................................ 1 Changed the status of all orderable part numbers in the ZQE package ...................................................... 2 Revision History Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 3 Device Comparison Table 3-1 summarizes the available family members. Table 3-1. Device Comparison (1) (2) DEVICE MSP430F5510 MSP430F5509 MSP430F5508 PROGRAM MEMORY (KB) 32 24 16 USCI SRAM (KB) (3) 4+2 4+2 4+2 Timer_A (4) 5, 3, 3 5, 3, 3 5, 3, 3 Timer_B (5) CHANNEL A: CHANNEL B: UART, LIN, SPI, I2C IrDA, SPI ADC10_A (CH) Comp_B (CH) I/Os PACKAGE 2 2 10 ext, 2 int 8 47 64 RGC, 80 ZXH, 80 ZQE 2 (6) 2 (6) 6 ext, 2 int 4 31 48 PT, 48 RGZ 2 2 10 ext, 2 int 8 47 64 RGC, 80 ZXH, 80 ZQE 2 (6) 2 (6) 6 ext, 2 int 4 31 48 PT, 48 RGZ, 2 2 10 ext, 2 int 8 47 64 RGC, 80 ZXH, 80 ZQE 2 (6) 2 (6) 6 ext, 2 int 4 31 48 PT, 48 RGZ, 7 7 7 MSP430F5507 32 4+2 5, 3, 3 7 1 1 6 ext, 2 int – 31 48 RGZ MSP430F5506 24 4+2 5, 3, 3 7 1 1 6 ext, 2 int – 31 48 RGZ MSP430F5505 16 4+2 5, 3, 3 7 1 1 6 ext, 2 int – 31 48 RGZ MSP430F5504 8 4+2 5, 3, 3 7 1 1 6 ext, 2 int – 31 48 PT, 48 RGZ MSP430F5503 32 4+2 5, 3, 3 7 1 1 – 4 31 48 RGZ MSP430F5502 24 4+2 5, 3, 3 7 1 1 – 4 31 48 RGZ MSP430F5501 16 4+2 5, 3, 3 7 1 1 – 4 31 48 RGZ MSP430F5500 8 4+2 5, 3, 3 7 1 1 – 4 31 48 RGZ (1) (2) (3) (4) (5) (6) For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section 8, or see the TI website at www.ti.com. Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging. The additional 2KB USB SRAM that is listed can be used as general-purpose SRAM when USB is not in use. Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively. Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively. Two USCIs are available; however, pinned out functions are limited to what the user configures on port 4 with the port mapping controller (see Section 6.9.2). It may not be possible to bring out all functions simultaneously. Device Comparison Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 7 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 3.1 www.ti.com Related Products For information about other devices in this family of products or related products, see the following links. Products for TI Microcontrollers TI's low-power and high-performance MCUs, with wired and wireless connectivity options, are optimized for a broad range of applications. Products for MSP430 Ultra-Low-Power Microcontrollers One platform. One ecosystem. Endless possibilities. Enabling the connected world with innovations in ultra-low-power microcontrollers with advanced peripherals for precise sensing and measurement. Companion Products for MSP430F5510 Review products that are frequently purchased or used in conjunction with this product. Reference Designs Find reference designs leveraging the best in TI technology to solve your systemlevel challenges 8 Device Comparison Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 4 Terminal Configuration and Functions 4.1 Pin Diagrams VSSU PU.0/DP PUR PU.1/DM VBUS VUSB V18 AVSS2 P5.2/XT2IN P5.3/XT2OUT TEST/SBWTCK PJ.0/TDO PJ.1/TDI/TCLK PJ.2/TMS PJ.3/TCK RST/NMI/SBWTDIO Figure 4-1 shows the pinout for the 64-pin RGC package of the MSP430F5510, MSP430F5509, and MSP430F5508 MCUs. 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P6.0/CB0/A0 1 48 P4.7/PM_NONE P6.1/CB1/A1 2 47 P4.6/PM_NONE P6.2/CB2/A2 3 46 P4.5/PM_UCA1RXD/PM_UCA1SOMI P6.3/CB3/A3 4 45 P4.4/PM_UCA1TXD/PM_UCA1SIMO P6.4/CB4/A4 5 44 P4.3/PM_UCB1CLK/PM_UCA1STE P6.5/CB5/A5 6 43 P4.2/PM_UCB1SOMI/PM_UCB1SCL P6.6/CB6/A6 7 42 P4.1/PM_UCB1SIMO/PM_UCB1SDA P6.7/CB7/A7 8 41 P4.0/PM_UCB1STE/PM_UCA1CLK P5.0/A8/VeREF+ 9 40 DVCC2 P5.1/A9/VeREF- 10 39 DVSS2 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P2.7/UCB0STE/UCA0CLK P2.6/RTCCLK/DMAE0 P2.5/TA2.2 DVSS1 P2.4/TA2.1 P3.0/UCB0SIMO/UCB0SDA P2.3/TA2.0 34 P2.1/TA1.2 15 P2.2/TA2CLK/SMCLK DVCC1 P2.0/TA1.1 P3.1/UCB0SOMI/UCB0SCL P1.7/TA1.0 P3.2/UCB0CLK/UCA0STE 35 P1.6/TA1CLK/CBOUT 36 14 P1.5/TA0.4 13 AVSS1 P1.4/TA0.3 P5.5/XOUT P1.3/TA0.2 P3.3/UCA0TXD/UCA0SIMO P1.2/TA0.1 P3.4/UCA0RXD/UCA0SOMI 37 P1.1/TA0.0 38 VCORE 11 12 P1.0/TA0CLK/ACLK AVCC1 P5.4/XIN NOTE: TI recommends connection of the exposed thermal pad to VSS. Figure 4-1. 64-Pin RGC Package (Top View) – F5510, F5509, F5508 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 9 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com Figure 4-2 shows the pinout for the 80-pin ZXH or ZQE package of the MSP430F5510, MSP430F5509, and MSP430F5508 MCUs. See Section 4.2 for the pin assignments. A1 A2 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B8 B9 C1 C2 C4 C5 C6 C7 C8 C9 D1 D2 D3 D4 D5 D6 D7 D8 D9 E1 E2 E3 E4 E5 E6 E7 E8 E9 F1 F2 F3 F4 F5 F6 F7 F8 F9 G1 G2 G3 G4 G5 G6 G7 G8 G9 H1 H2 H3 H4 H5 H6 H7 H8 H9 J1 J2 J3 J4 J5 J6 J7 J8 J9 Figure 4-2. 80-Pin ZXH or ZQE Package (Top View) – F5510, F5509, F5508 10 Terminal Configuration and Functions Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 VSSU PU.0/DP PUR PU.1/DM VBUS VUSB V18 AVSS2 P5.2/XT2IN P5.3/XT2OUT TEST/SBWTCK RST/NMI/SBWTDIO Figure 4-3 shows the pinout for 48-pin RGZ and PT packages of the MSP430F5510, MSP430F5509, and MSP430F5508 MCUs. 48 47 46 45 44 43 42 41 40 39 38 37 P6.0/CB0/A0 1 36 P4.7/PM_NONE P6.1/CB1/A1 2 35 P4.6/PM_NONE P6.2/CB2/A2 3 34 P4.5/PM_UCA1RXD/PM_UCA1SOMI P6.3/CB3/A3 4 33 P4.4/PM_UCA1TXD/PM_UCA1SIMO P5.0/A8/VeREF+ 5 32 P4.3/PM_UCB1CLK/PM_UCA1STE P5.1/A9/VeREF- 6 31 P4.2/PM_UCB1SOMI/PM_UCB1SCL AVCC1 7 30 P4.1/PM_UCB1SIMO/PM_UCB1SDA P5.4/XIN 8 29 P4.0/PM_UCB1STE/PM_UCA1CLK P5.5/XOUT 9 28 DVCC2 PJ.0/TDO PJ.1/TDI/TCLK P2.0/TA1.1 P1.7/TA1.0 P1.6/TA1CLK/CBOUT PJ.2/TMS P1.5/TA0.4 12 25 13 14 15 16 17 18 19 20 21 22 23 24 P1.4/TA0.3 DVSS1 P1.3/TA0.2 PJ.3/TCK P1.2/TA0.1 DVSS2 26 P1.1/TA0.0 27 11 VCORE 10 P1.0/TA0CLK/ACLK AVSS1 DVCC1 NOTE: TI recommends connection of the exposed thermal pad to VSS. Figure 4-3. 48-Pin RGZ or PT Package (Top View) – F5510, F5509, F5508 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 11 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com VSSU PU.0/DP PUR PU.1/DM VBUS VUSB V18 AVSS2 P5.2/XT2IN P5.3/XT2OUT TEST/SBWTCK RST/NMI/SBWTDIO Figure 4-4 shows the pinout for the 48-pin RGZ and PT packages of the MSP430F5507, MSP430F5506, MSP430F5505, and MSP430F5504 MCUs. 48 47 46 45 44 43 42 41 40 39 38 37 P6.0/A0 1 36 P4.7/PM_NONE P6.1/A1 2 35 P4.6/PM_NONE P6.2/A2 3 34 P4.5/PM_UCA1RXD/PM_UCA1SOMI P6.3/A3 4 33 P4.4/PM_UCA1TXD/PM_UCA1SIMO P5.0/A8/VeREF+ 5 32 P4.3/PM_UCB1CLK/PM_UCA1STE P5.1/A9/VeREF- 6 31 P4.2/PM_UCB1SOMI/PM_UCB1SCL AVCC1 7 30 P4.1/PM_UCB1SIMO/PM_UCB1SDA P5.4/XIN 8 29 P4.0/PM_UCB1STE/PM_UCA1CLK P5.5/XOUT 9 28 DVCC2 PJ.0/TDO PJ.1/TDI/TCLK P2.0/TA1.1 P1.7/TA1.0 P1.6/TA1CLK PJ.2/TMS P1.5/TA0.4 12 25 13 14 15 16 17 18 19 20 21 22 23 24 P1.4/TA0.3 DVSS1 P1.3/TA0.2 PJ.3/TCK P1.2/TA0.1 DVSS2 26 P1.1/TA0.0 27 11 VCORE 10 P1.0/TA0CLK/ACLK AVSS1 DVCC1 NOTE: TI recommends connection of the exposed thermal pad to VSS. Figure 4-4. 48-Pin RGZ or PT Package (Top View) – F5507, F5506, F5505, F5504 12 Terminal Configuration and Functions Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 VSSU PU.0/DP PUR PU.1/DM VBUS VUSB V18 AVSS2 P5.2/XT2IN P5.3/XT2OUT TEST/SBWTCK RST/NMI/SBWTDIO Figure 4-5 shows the pinout for the 48-pin RGZ package of the MSP430F5503, MSP430F5502, MSP430F5501, and MSP430F5500 MCUs. 48 47 46 45 44 43 42 41 40 39 38 37 P6.0/CB0 1 36 P4.7/PM_NONE P6.1/CB1 2 35 P4.6/PM_NONE P6.2/CB2 3 34 P4.5/PM_UCA1RXD/PM_UCA1SOMI P6.3/CB3 4 33 P4.4/PM_UCA1TXD/PM_UCA1SIMO P5.0 5 32 P4.3/PM_UCB1CLK/PM_UCA1STE P5.1 6 31 P4.2/PM_UCB1SOMI/PM_UCB1SCL AVCC1 7 30 P4.1/PM_UCB1SIMO/PM_UCB1SDA P5.4/XIN 8 29 P4.0/PM_UCB1STE/PM_UCA1CLK P5.5/XOUT 9 28 DVCC2 PJ.1/TDI/TCLK PJ.0/TDO P2.0/TA1.1 P1.7/TA1.0 P1.6/TA1CLK/CBOUT PJ.2/TMS P1.5/TA0.4 12 25 13 14 15 16 17 18 19 20 21 22 23 24 P1.4/TA0.3 DVSS1 P1.3/TA0.2 PJ.3/TCK P1.2/TA0.1 DVSS2 26 P1.1/TA0.0 27 11 P1.0/TA0CLK/ACLK 10 VCORE AVSS1 DVCC1 NOTE: TI recommends connection of the exposed thermal pad to VSS. Figure 4-5. 48-Pin RGZ Package (Top View) – F5503, F5502, F5501, F5500 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 13 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 4.2 www.ti.com Signal Descriptions Table 4-1 describes the signals for all device variants and package options. Table 4-1. Terminal Functions TERMINAL NO. NAME RGC RGZ, PT I/O (1) DESCRIPTION ZXH, ZQE General-purpose digital I/O P6.4/CB4/A4 5 N/A C1 I/O Comparator_B input CB4 (not available on PT and RGZ package devices) Analog input A4 – ADC (not available on PT and RGZ package devices) General-purpose digital I/O P6.5/CB5/A5 6 N/A D2 I/O Comparator_B input CB5 (not available on PT and RGZ package devices) Analog input A5 – ADC (not available on PT and RGZ package devices) General-purpose digital I/O P6.6/CB6/A6 7 N/A D1 I/O Comparator_B input CB6 (not available on PT and RGZ package devices) Analog input A6 – ADC (not available on PT and RGZ package devices) General-purpose digital I/O P6.7/CB7/A7 8 N/A D3 I/O Comparator_B input CB7 (not available on PT and RGZ package devices) Analog input A7 – ADC (not available on PT and RGZ package devices) General-purpose digital I/O P5.0/A8/VeREF+ 9 5 E1 I/O Analog input A8 – ADC (not available on F5503, F5502, F5501, F5500 devices) Input for an external reference voltage to the ADC (not available on F5503, F5502, F5501, F5500 devices) General-purpose digital I/O P5.1/A9/VeREF- 10 6 E2 I/O Analog input A9 – ADC (not available on F5503, F5502, F5501, F5500 devices) Negative terminal for an externally provided ADC reference (not available on F5503, F5502, F5501, F5500 devices) AVCC1 11 7 F2 P5.4/XIN 12 8 F1 I/O P5.5/XOUT 13 9 G1 I/O AVSS1 14 10 G2 Analog ground supply DVCC1 15 11 H1 Digital power supply 16 12 J1 Digital ground supply 17 13 J2 Regulated core power supply output (internal use only, no external current loading) 18 14 H2 DVSS1 VCORE (2) Analog power supply General-purpose digital I/O Input terminal for crystal oscillator XT1 General-purpose digital I/O Output terminal of crystal oscillator XT1 General-purpose digital I/O with port interrupt P1.0/TA0CLK/ACLK I/O TA0 clock signal TA0CLK input ACLK output (divided by 1, 2, 4, 8, 16, or 32) General-purpose digital I/O with port interrupt P1.1/TA0.0 19 15 H3 I/O TA0 CCR0 capture: CCI0A input, compare: Out0 output BSL transmit output General-purpose digital I/O with port interrupt P1.2/TA0.1 20 16 J3 I/O TA0 CCR1 capture: CCI1A input, compare: Out1 output BSL receive input (1) (2) 14 I = input, O = output, N/A = not available VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended capacitor value, CVCORE (see Section 5.3). Terminal Configuration and Functions Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 Table 4-1. Terminal Functions (continued) TERMINAL NO. NAME I/O (1) RGC RGZ, PT ZXH, ZQE P1.3/TA0.2 21 17 G4 I/O P1.4/TA0.3 22 18 H4 I/O P1.5/TA0.4 23 19 J4 I/O P1.6/TA1CLK/CBOUT 24 20 G5 I/O DESCRIPTION General-purpose digital I/O with port interrupt TA0 CCR2 capture: CCI2A input, compare: Out2 output General-purpose digital I/O with port interrupt TA0 CCR3 capture: CCI3A input compare: Out3 output General-purpose digital I/O with port interrupt TA0 CCR4 capture: CCI4A input, compare: Out4 output General-purpose digital I/O with port interrupt TA1 clock signal TA1CLK input Comparator_B output P1.7/TA1.0 25 21 H5 I/O P2.0/TA1.1 26 22 J5 I/O P2.1/TA1.2 27 N/A G6 I/O P2.2/TA2CLK/SMCLK 28 N/A J6 I/O General-purpose digital I/O with port interrupt TA1 CCR0 capture: CCI0A input, compare: Out0 output General-purpose digital I/O with port interrupt TA1 CCR1 capture: CCI1A input, compare: Out1 output General-purpose digital I/O with port interrupt TA1 CCR2 capture: CCI2A input, compare: Out2 output General-purpose digital I/O with port interrupt TA2 clock signal TA2CLK input SMCLK output P2.3/TA2.0 29 N/A H6 I/O P2.4/TA2.1 30 N/A J7 I/O P2.5/TA2.2 31 N/A J8 I/O General-purpose digital I/O with port interrupt TA2 CCR0 capture: CCI0A input, compare: Out0 output General-purpose digital I/O with port interrupt TA2 CCR1 capture: CCI1A input, compare: Out1 output General-purpose digital I/O with port interrupt TA2 CCR2 capture: CCI2A input, compare: Out2 output General-purpose digital I/O with port interrupt P2.6/RTCCLK/DMAE0 32 N/A J9 I/O RTC clock output for calibration DMA external trigger input General-purpose digital I/O with port interrupt P2.7/UCB0STE/UCA0CLK 33 N/A H7 I/O Slave transmit enable – USCI_B0 SPI mode Clock signal input – USCI_A0 SPI slave mode Clock signal output – USCI_A0 SPI master mode General-purpose digital I/O P3.0/UCB0SIMO/UCB0SDA 34 N/A H8 I/O Slave in, master out – USCI_B0 SPI mode I2C data – USCI_B0 I2C mode General-purpose digital I/O P3.1/UCB0SOMI/UCB0SCL 35 N/A H9 I/O Slave out, master in – USCI_B0 SPI mode I2C clock – USCI_B0 I2C mode General-purpose digital I/O P3.2/UCB0CLK/UCA0STE 36 N/A G8 I/O Clock signal input – USCI_B0 SPI slave mode Clock signal output – USCI_B0 SPI master mode Slave transmit enable – USCI_A0 SPI mode General-purpose digital I/O P3.3/UCA0TXD/UCA0SIMO 37 N/A G9 I/O Transmit data – USCI_A0 UART mode Slave in, master out – USCI_A0 SPI mode Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 15 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com Table 4-1. Terminal Functions (continued) TERMINAL NO. NAME RGC RGZ, PT I/O (1) DESCRIPTION ZXH, ZQE General-purpose digital I/O P3.4/UCA0RXD/UCA0SOMI 38 N/A G7 I/O Receive data – USCI_A0 UART mode Slave out, master in – USCI_A0 SPI mode General-purpose digital I/O with reconfigurable port mapping secondary function P4.0/PM_UCB1STE/ PM_UCA1CLK 41 29 E8 I/O Default mapping: Slave transmit enable – USCI_B1 SPI mode Default mapping: Clock signal input – USCI_A1 SPI slave mode Default mapping: Clock signal output – USCI_A1 SPI master mode P4.1/PM_UCB1SIMO/ PM_UCB1SDA General-purpose digital I/O with reconfigurable port mapping secondary function 42 30 E7 I/O Default mapping: Slave in, master out – USCI_B1 SPI mode Default mapping: I2C data – USCI_B1 I2C mode P4.2/PM_UCB1SOMI/ PM_UCB1SCL General-purpose digital I/O with reconfigurable port mapping secondary function 43 31 D9 I/O Default mapping: Slave out, master in – USCI_B1 SPI mode Default mapping: I2C clock – USCI_B1 I2C mode General-purpose digital I/O with reconfigurable port mapping secondary function P4.3/PM_UCB1CLK/ PM_UCA1STE 44 DVSS2 39 27 F9 Digital ground supply DVCC2 40 28 E9 Digital power supply 32 D8 I/O Default mapping: Clock signal input – USCI_B1 SPI slave mode Default mapping: Clock signal output – USCI_B1 SPI master mode Default mapping: Slave transmit enable – USCI_A1 SPI mode P4.4/PM_UCA1TXD/ PM_UCA1SIMO General-purpose digital I/O with reconfigurable port mapping secondary function 45 33 D7 I/O Default mapping: Transmit data – USCI_A1 UART mode Default mapping: Slave in, master out – USCI_A1 SPI mode P4.5/PM_UCA1RXD/ PM_UCA1SOMI General-purpose digital I/O with reconfigurable port mapping secondary function 46 34 C9 I/O Default mapping: Receive data – USCI_A1 UART mode Default mapping: Slave out, master in – USCI_A1 SPI mode P4.6/PM_NONE 47 35 C8 I/O General-purpose digital I/O with reconfigurable port mapping secondary function Default mapping: no secondary function P4.7/PM_NONE 48 36 C7 I/O General-purpose digital I/O with reconfigurable port mapping secondary function Default mapping: no secondary function VSSU 49 37 B8, B9 PU.0/DP 50 38 A9 I/O PUR 51 39 B7 I/O PU.1/DM 52 40 A8 I/O VBUS 53 41 A7 USB LDO input (connect to USB power source) VUSB 54 42 A6 USB LDO output 16 Terminal Configuration and Functions USB PHY ground supply General-purpose digital I/O - controlled by USB control register USB data terminal DP USB pullup resistor pin (open drain). The voltage level at the PUR pin is used to invoke the default USB BSL. Recommended 1-MΩ resistor to ground. See Section 6.5.1 for more information. General-purpose digital I/O - controlled by USB control register USB data terminal DM Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 Table 4-1. Terminal Functions (continued) TERMINAL NO. NAME I/O (1) DESCRIPTION RGC RGZ, PT ZXH, ZQE V18 55 43 B6 USB regulated power (internal use only, no external current loading) AVSS2 56 44 A5 Analog ground supply P5.2/XT2IN 57 45 B5 I/O P5.3/XT2OUT 58 46 B4 I/O TEST/SBWTCK 59 47 A4 I PJ.0/TDO 60 23 C5 I/O General-purpose digital I/O Input terminal for crystal oscillator XT2 General-purpose digital I/O Output terminal of crystal oscillator XT2 Test mode pin – select digital I/O on JTAG pins Spy-By-Wire input clock General-purpose digital I/O Test data output port General-purpose digital I/O PJ.1/TDI/TCLK 61 24 C4 I/O Test data input Test clock input PJ.2/TMS 62 25 A3 I/O PJ.3/TCK 63 26 B3 I/O General-purpose digital I/O Test mode select General-purpose digital I/O Test clock Reset input, active low (3) RST/NMI/SBWTDIO 64 48 A2 I/O Nonmaskable interrupt input Spy-By-Wire data input/output General-purpose digital I/O P6.0/CB0/A0 1 1 A1 I/O Comparator_B input CB0 (not available on F5507, F5506, F5505, F5504 devices) Analog input A0 – ADC (not available on F5503, F5502, F5501, F5500 devices) General-purpose digital I/O P6.1/CB1/A1 2 2 B2 I/O Comparator_B input CB1 (not available on F5507, F5506, F5505, F5504 devices) Analog input A1 – ADC (not available on F5503, F5502, F5501, F5500 devices) General-purpose digital I/O P6.2/CB2/A2 3 3 B1 I/O Comparator_B input CB2 (not available on F5507, F5506, F5505, F5504 devices) Analog input A2 – ADC (not available on F5503, F5502, F5501, F5500 devices) General-purpose digital I/O P6.3/CB3/A3 4 4 C2 I/O Comparator_B input CB3 (not available on F5507, F5506, F5505, F5504 devices) Analog input A3 – ADC (not available on F5503, F5502, F5501, F5500 devices) Reserved N/A N/A (4) QFN Pad Pad Pad N/A (3) (4) Reserved. Connect to ground. Exposed QFN package pad (not available on PT package devices). TI recommends connecting to VSS. When this pin is configured as reset, the internal pullup resistor is enabled by default. C6, D4, D5, D6, E3, E4, E5, E6, F3, F4, F5, F6, F7, F8, G3 are reserved and should be connected to ground. Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 17 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 18 Terminal Configuration and Functions www.ti.com Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 5 Specifications All graphs in this section are for typical conditions, unless otherwise noted. Typical (TYP) values are specified at VCC = 3.3 V and TA = 25°C, unless otherwise noted. Absolute Maximum Ratings (1) 5.1 over operating free-air temperature range (unless otherwise noted) Voltage applied at VCC to VSS Voltage applied to any pin (excluding VCORE, VBUS, V18) (2) MIN MAX –0.3 4.1 –0.3 VCC + 0.3 Diode current at any device pin Maximum junction temperature, TJ Storage temperature, Tstg (3) (1) (2) (3) –55 mA 95 °C 150 °C ESD Ratings V(ESD) 5.3 Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±1000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±250 Supply voltage during program execution and flash programming(AVCC = DVCC) (1) (2) Supply voltage during USB operation, USB PLL disabled, USB_EN = 1, UPLLEN = 0 VCC,USB Supply voltage during USB operation, USB PLL enabled (3), USB_EN = 1, UPLLEN = 1 NOM MAX PMMCOREVx = 0 1.8 3.6 PMMCOREVx = 0, 1 2.0 3.6 PMMCOREVx = 0, 1, 2 2.2 3.6 PMMCOREVx = 0, 1, 2, 3 2.4 3.6 PMMCOREVx = 0 1.8 3.6 PMMCOREVx = 0, 1 2.0 3.6 PMMCOREVx = 0, 1, 2 2.2 3.6 PMMCOREVx = 0, 1, 2, 3 2.4 3.6 PMMCOREVx = 2 2.2 3.6 PMMCOREVx = 2, 3 2.4 VSS Supply voltage (AVSS = DVSS1 = DVSS2 = DVSS) TA Operating free-air temperature I version –40 TJ Operating junction temperature I version –40 CVCORE Capacitor at VCORE (4) CDVCC/ CVCORE Capacitor ratio of DVCC to VCORE (3) (4) V Recommended Operating Conditions VCC (2) UNIT JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±1000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V may actually have higher performance. MIN (1) V ±2 VALUE (2) V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied. Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. 5.2 (1) UNIT UNIT V V 3.6 0 V 85 85 470 °C °C nF 10 TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be tolerated during power up and operation. The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the Section 5.22 threshold parameters for the exact values and further details. USB operation with USB PLL enabled requires PMMCOREVx ≥ 2 for proper operation. A capacitor tolerance of ±20% or better is required. Specifications Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 19 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com Recommended Operating Conditions (continued) MIN Processor frequency (maximum MCLK frequency) (5) (see Figure 5-1) fSYSTEM fSYSTEM_USB Minimum processor frequency for USB operation USB_wait Wait state cycles during USB operation (5) NOM MAX PMMCOREVx = 0, 1.8 V ≤ VCC ≤ 3.6 V (default condition) 0 8.0 PMMCOREVx = 1, 2.0 V ≤ VCC ≤ 3.6 V 0 12.0 PMMCOREVx = 2, 2.2 V ≤ VCC ≤ 3.6 V 0 20.0 PMMCOREVx = 3, 2.4 V ≤ VCC ≤ 3.6 V 0 25.0 1.5 UNIT MHz MHz 16 cycles Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet. 25 System Frequency - MHz 3 20 2 2, 3 1 1, 2 1, 2, 3 0, 1 0, 1, 2 0, 1, 2, 3 12 8 0 0 1.8 2.0 2.2 2.4 3.6 Supply Voltage - V NOTE: The numbers within the fields denote the supported PMMCOREVx settings. Figure 5-1. Maximum System Frequency 20 Specifications Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com 5.4 SLAS645L – JULY 2009 – REVISED MAY 2020 Active Mode Supply Current Into VCC Excluding External Current over recommended operating free-air temperature (unless otherwise noted) (1) (2) (3) FREQUENCY (fDCO = fMCLK = fSMCLK) PARAMETER IAM, IAM, (1) (2) (3) Flash RAM EXECUTION MEMORY Flash RAM VCC PMMCOREVx 3V 3V 1 MHz 8 MHz 12 MHz TYP MAX 1.74 2.58 2.78 1.91 20 MHz TYP MAX TYP MAX 0 0.25 0.27 1.55 1.68 1 0.28 2 0.30 3 0.32 0 0.17 1 0.19 1.03 1.54 2 0.20 1.16 1.73 2.84 3 0.21 1.24 1.87 3.1 2.09 0.19 0.91 TYP MAX 2.84 4.68 5.06 3.10 5.13 25 MHz TYP UNIT MAX mA 6.0 6.5 1.00 1.67 mA 3.11 3.9 4.3 All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are chosen to closely match the required 12.5 pF. Characterized with program executing typical data processing. USB disabled (VUSBEN = 0, SLDOEN = 0). fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency. XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0. Specifications Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 21 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 5.5 www.ti.com Low-Power Mode Supply Currents (Into VCC) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) TEMPERATURE (TA) PARAMETER VCC PMMCOREVx –40°C TYP ILPM0,1MHz Low-power mode 0 (3) (4) ILPM2 Low-power mode 2 (5) (4) 77 85 80 85 97 83 92 88 95 105 2.2 V 0 6.5 6.5 8 7.5 8 11 3V 3 7.0 7.0 9 7.9 8.9 13 0 1.60 1.90 2.6 3.4 1 1.65 2.00 2.7 3.6 2 1.75 2.15 2.9 3.8 0 1.8 2.1 2.8 3.6 1 1.9 2.3 2.9 3.8 2 2.0 2.4 3.0 4.0 3 2.0 2.5 3.0 3.1 4.0 6.5 0 1.1 1.3 1.8 1.9 2.7 5.0 1 1.1 1.4 2.0 2.8 2 1.2 1.5 2.1 2.9 3 1.3 1.5 2.0 2.2 3.0 5.5 0 0.9 1.1 1.5 1.8 2.5 4.8 1 1.1 1.2 2.0 2.6 2 1.2 1.2 2.1 2.7 3V ILPM4.5 Low-power mode 4.5 (9) 3V 3 (5) (6) (7) (8) (9) 22 UNIT MAX 79 3V (4) 85°C TYP 73 Low-power mode 4 (8) (4) (3) MAX 3 ILPM4 (1) (2) TYP 0 Low-power mode 3, crystal mode (6) (4) Low-power mode 3, VLO mode (7) (4) 60°C MAX 3V 3V ILPM3,VLO 25°C TYP 2.2 V 2.2 V ILPM3,XT1LF MAX 2.6 6.0 µA µA µA µA µA 1.3 1.3 1.6 2.2 2.8 5.0 0.15 0.18 0.35 0.26 0.45 0.80 µA All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are chosen to closely match the required 12.5 pF. Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz USB disabled (VUSBEN = 0, SLDOEN = 0). Current for brownout, high-side supervisor (SVSH) normal mode included. Low-side supervisor (SVSL) and low-side monitor (SVML) disabled. High-side monitor (SVMH) disabled. RAM retention enabled. Current for watchdog timer and RTC clocked by ACLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz, DCO setting = 1 MHz operation, DCO bias generator enabled. USB disabled (VUSBEN = 0, SLDOEN = 0) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz USB disabled (VUSBEN = 0, SLDOEN = 0) Current for watchdog timer and RTC clocked by ACLK included. ACLK = VLO. CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz USB disabled (VUSBEN = 0, SLDOEN = 0) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz USB disabled (VUSBEN = 0, SLDOEN = 0) Internal regulator disabled. No data retention. CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz Specifications Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com 5.6 SLAS645L – JULY 2009 – REVISED MAY 2020 Thermal Resistance Characteristics VALUE (1) Junction-to-ambient thermal resistance, still air (2) θJA Junction-to-case (top) thermal resistance (3) θJC(TOP) θJC(BOTTOM) θJB (1) (2) (3) (4) (5) Junction-to-case (bottom) thermal resistance (4) Junction-to-board thermal resistance (5) VQFN (RGC) 30 VQFN (RGZ) 28.6 LQFP (PT) 62.8 BGA (ZQE) 55.5 VQFN (RGC) 15.6 VQFN (RGZ) 14.4 LQFP (PT) 18.2 BGA (ZQE) 21.2 VQFN(RGC) 1.6 VQFN (RGZ) 1.6 LQFP (PT) N/A BGA (ZQE) N/A VQFN (RGC) 8.9 VQFN (RGZ) 5.5 LQFP (PT) 28.3 BGA (ZQE) 19.3 UNIT °C/W °C/W °C/W °C/W N/A = not applicable The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-case(bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. Specifications Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 23 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com Schmitt-Trigger Inputs – General-Purpose I/O (1) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RST/NMI) 5.7 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VIT+ Positive-going input threshold voltage VIT– Negative-going input threshold voltage Vhys Input voltage hysteresis (VIT+ – VIT–) RPull Pullup or pulldown resistor (2) For pullup: VIN = VSS For pulldown: VIN = VCC CI Input capacitance VIN = VSS or VCC (1) (2) VCC MIN 1.8 V 0.80 TYP 1.40 3V 1.50 2.10 1.8 V 0.45 1.00 3V 0.75 1.65 1.8 V 0.3 0.85 3V 0.4 1.0 20 35 MAX UNIT V V V 50 kΩ 5 pF Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN). Also applies to the RST pin when its pullup or pullup resistor is enabled. Inputs – Ports P1 and P2 (1) (P1.0 to P1.7, P2.0 to P2.7) 5.8 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER t(int) (1) (2) External interrupt timing (2) TEST CONDITIONS VCC Port P1, P2: P1.x to P2.x, External trigger pulse duration to set interrupt flag 2.2 V, 3 V MIN MAX UNIT 20 ns Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions. An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals shorter than t(int). 5.9 Leakage Current – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RST/NMI) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER Ilkg(Px.y) (1) (2) TEST CONDITIONS VCC (1) (2) High-impedance leakage current MIN 1.8 V, 3 V MAX UNIT ±50 nA The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is disabled. 5.10 Outputs – General-Purpose I/O (Full Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS I(OHmax) = –3 mA VOH High-level output voltage I(OHmax) = –10 mA (2) I(OHmax) = –5 mA (1) I(OHmax) = –15 mA (2) I(OLmax) = 3 mA VOL Low-level output voltage (2) 24 1.8 V 3V (1) I(OLmax) = 10 mA (2) I(OLmax) = 5 mA (1) I(OLmax) = 15 mA (2) (1) VCC (1) 1.8 V 3V MIN MAX VCC – 0.25 VCC VCC – 0.60 VCC VCC – 0.25 VCC VCC – 0.60 VCC VSS VSS + 0.25 VSS VSS + 0.60 VSS VSS + 0.25 VSS VSS + 0.60 UNIT V V The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop specified. The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage drop specified. Specifications Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 5.11 Outputs – General-Purpose I/O (Reduced Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TEST CONDITIONS I(OHmax) = –1 mA (2) VOH 1.8 V I(OHmax) = –3 mA (3) High-level output voltage I(OHmax) = –2 mA VCC (2) 3V I(OHmax) = –6 mA (3) I(OLmax) = 1 mA (2) VOL I(OLmax) = 2 mA (2) (3) VCC VCC – 0.60 VCC VCC – 0.25 VCC VCC – 0.60 VCC VSS VSS + 0.25 VSS VSS + 0.60 VSS VSS + 0.25 VSS VSS + 0.60 3V I(OLmax) = 6 mA (3) (1) (2) MAX 1.8 V I(OLmax) = 3 mA (3) Low-level output voltage MIN VCC – 0.25 UNIT V V Selecting reduced drive strength may reduce EMI. The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop specified. The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage drop specified. 5.12 Output Frequency – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT (1) (2) Port output frequency (with load) fPx.y fPort_CLK (1) (2) Clock output frequency ACLK SMCLK MCLK CL = 20 pF (2) VCC = 1.8 V PMMCOREVx = 0 16 VCC = 3 V PMMCOREVx = 3 25 VCC = 1.8 V PMMCOREVx = 0 16 VCC = 3 V PMMCOREVx = 3 25 MHz MHz A resistive divider with 2 × R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For full drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency. Specifications Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 25 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com 5.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) 8.0 VCC = 3.0 V Px.y IOL – Typical Low-Level Output Current – mA IOL – Typical Low-Level Output Current – mA 25.0 TA = 25°C 20.0 TA = 85°C 15.0 10.0 5.0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 IOH – Typical High-Level Output Current – mA IOH – Typical High-Level Output Current – mA −5.0 −10.0 −25.0 0.0 TA = 85°C TA = 25°C 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOH – High-Level Output Voltage – V Figure 5-4. Typical High-Level Output Current vs High-Level Output Voltage 26 4.0 3.0 2.0 1.0 0.5 1.0 1.5 2.0 0.0 VCC = 3.0 V Px.y −20.0 5.0 VOL – Low-Level Output Voltage – V Figure 5-3. Typical Low-Level Output Current vs Low-Level Output Voltage 0.0 −15.0 TA = 85°C 6.0 0.0 0.0 3.5 VOL – Low-Level Output Voltage – V Figure 5-2. Typical Low-Level Output Current vs Low-Level Output Voltage 7.0 TA = 25°C VCC = 1.8 V Px.y Specifications −1.0 VCC = 1.8 V Px.y −2.0 −3.0 −4.0 −5.0 −6.0 TA = 85°C TA = 25°C −7.0 −8.0 0.0 0.5 1.0 1.5 2.0 VOH – High-Level Output Voltage – V Figure 5-5. Typical High-Level Output Current vs High-Level Output Voltage Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 5.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) 55.0 24 TA = 25°C VCC = 3.0 V Px.y 50.0 IOL – Typical Low-Level Output Current – mA IOL – Typical Low-Level Output Current – mA 60.0 TA = 85°C 45.0 40.0 35.0 30.0 25.0 20.0 15.0 10.0 TA = 25°C 20 TA = 85°C 16 12 8 4 5.0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.0 3.5 VOL – Low-Level Output Voltage – V Figure 5-6. Typical Low-Level Output Current vs Low-Level Output Voltage −10.0 −15.0 −20.0 −25.0 −30.0 −35.0 −40.0 −45.0 −50.0 TA = 85°C −55.0 −60.0 0.0 1.0 1.5 2.0 0 VCC = 3.0 V Px.y IOH – Typical High-Level Output Current – mA −5.0 0.5 VOL – Low-Level Output Voltage – V Figure 5-7. Typical Low-Level Output Current vs Low-Level Output Voltage 0.0 IOH – Typical High-Level Output Current – mA VCC = 1.8 V Px.y TA = 25°C 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOH – High-Level Output Voltage – V Figure 5-8. Typical High-Level Output Current vs High-Level Output Voltage VCC = 1.8 V Px.y −4 −8 −12 TA = 85°C −16 TA = 25°C −20 0.0 0.5 1.0 1.5 VOH – High-Level Output Voltage – V Figure 5-9. Typical High-Level Output Current vs High-Level Output Voltage Specifications Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 2.0 27 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com 5.15 Crystal Oscillator, XT1, Low-Frequency Mode (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1, TA = 25°C ΔIDVCC.LF Differential XT1 oscillator crystal current consumption from lowest drive setting, LF mode fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 2, TA = 25°C 0.170 32768 XTS = 0, XT1BYPASS = 0 fXT1,LF,SW XT1 oscillator logic-level squarewave input frequency, LF mode XTS = 0, XT1BYPASS = 1 (2) OALF 3V 0.290 XT1 oscillator crystal frequency, LF mode (3) 10 CL,eff fFault,LF tSTART,LF 210 XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1, fXT1,LF = 32768 Hz, CL,eff = 12 pF 300 (1) (2) (3) (4) (5) (6) (7) (8) 28 XTS = 0, XCAPx = 2 8.5 XTS = 0, XCAPx = 3 12.0 Oscillator fault frequency, LF mode (7) XTS = 0 (8) fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0, TA = 25°C, CL,eff = 6 pF fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 3, TA = 25°C, CL,eff = 12 pF µA Hz 50 kHz 1 5.5 Duty cycle, LF mode UNIT kΩ XTS = 0, XCAPx = 1 XTS = 0, Measured at ACLK, fXT1,LF = 32768 Hz Start-up time, LF mode 32.768 XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0, fXT1,LF = 32768 Hz, CL,eff = 6 pF XTS = 0, XCAPx = 0 (6) Integrated effective load capacitance, LF mode (5) MAX 0.075 fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 3, TA = 25°C fXT1,LF0 Oscillation allowance for LF crystals (4) TYP pF 30% 70% 10 10000 Hz 1000 3V ms 500 To improve EMI on the XT1 oscillator, the following guidelines should be observed. • Keep the trace between the device and the crystal as short as possible. • Design a good ground plane around the oscillator pins. • Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. • Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. • Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins. • If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins. When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in the Schmitt-trigger Inputs section of this datasheet. Maximum frequency of operation of the entire device cannot be exceeded. Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following guidelines, but should be evaluated based on the actual crystal selected for the application: • For XT1DRIVEx = 0, CL,eff ≤ 6 pF • For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF • For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF • For XT1DRIVEx = 3, CL,eff ≥ 6 pF Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal. Requires external capacitors at both terminals. Values are specified by crystal manufacturers. Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specifications might set the flag. Measured with logic-level input frequency but also applies to operation with crystals. Specifications Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 5.16 Crystal Oscillator, XT2 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TEST CONDITIONS VCC MIN fOSC = 4 MHz, XT2OFF = 0, XT2BYPASS = 0, XT2DRIVEx = 0, TA = 25°C IDVCC.XT2 XT2 oscillator crystal current consumption fOSC = 12 MHz, XT2OFF = 0, XT2BYPASS = 0, XT2DRIVEx = 1, TA = 25°C fOSC = 20 MHz, XT2OFF = 0, XT2BYPASS = 0, XT2DRIVEx = 2, TA = 25°C (2) TYP MAX UNIT 200 260 3V µA 325 fOSC = 32 MHz, XT2OFF = 0, XT2BYPASS = 0, XT2DRIVEx = 3, TA = 25°C 450 fXT2,HF0 XT2 oscillator crystal frequency, mode 0 XT2DRIVEx = 0, XT2BYPASS = 0 (3) 4 8 MHz fXT2,HF1 XT2 oscillator crystal frequency, mode 1 XT2DRIVEx = 1, XT2BYPASS = 0 (3) 8 16 MHz fXT2,HF2 XT2 oscillator crystal frequency, mode 2 XT2DRIVEx = 2, XT2BYPASS = 0 (3) 16 24 MHz fXT2,HF3 XT2 oscillator crystal frequency, mode 3 XT2DRIVEx = 3, XT2BYPASS = 0 (3) 24 32 MHz fXT2,HF,SW XT2 oscillator logic-level square-wave input frequency, bypass mode XT2BYPASS = 1 (4) 0.7 32 MHz OAHF tSTART,HF CL,eff fFault,HF (1) (2) (3) (4) (5) (6) (7) (8) Oscillation allowance for HF crystals (5) Start-up time Integrated effective load capacitance, HF mode (6) (3) XT2DRIVEx = 0, XT2BYPASS = 0, fXT2,HF0 = 6 MHz, CL,eff = 15 pF 450 XT2DRIVEx = 1, XT2BYPASS = 0, fXT2,HF1 = 12 MHz, CL,eff = 15 pF 320 XT2DRIVEx = 2, XT2BYPASS = 0, fXT2,HF2 = 20 MHz, CL,eff = 15 pF 200 XT2DRIVEx = 3, XT2BYPASS = 0, fXT2,HF3 = 32 MHz, CL,eff = 15 pF 200 fOSC = 6 MHz, XT2BYPASS = 0, XT2DRIVEx = 0, TA = 25°C, CL,eff = 15 pF 0.5 fOSC = 20 MHz XT2BYPASS = 0, XT2DRIVEx = 2, TA = 25°C, CL,eff = 15 pF Ω 3V ms 0.3 1 (1) Duty cycle Measured at ACLK, fXT2,HF2 = 20 MHz Oscillator fault frequency (7) XT2BYPASS = 1 (8) 40% 30 50% pF 60% 300 kHz Requires external capacitors at both terminals. Values are specified by crystal manufacturers. To improve EMI on the XT2 oscillator the following guidelines should be observed. • Keep the traces between the device and the crystal as short as possible. • Design a good ground plane around the oscillator pins. • Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT. • Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins. • Use assembly materials and processes that avoid any parasitic load on the oscillator XT2IN and XT2OUT pins. • If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins. This represents the maximum frequency that can be input to the device externally. Maximum frequency achievable on the device operation is based on the frequencies present on ACLK, MCLK, and SMCLK cannot be exceed for a given range of operation. When XT2BYPASS is set, the XT2 circuit is automatically powered down. Input signal is a digital square wave with parametrics defined in the Schmitt-trigger Inputs section of this datasheet. Oscillation allowance is based on a safety factor of 5 for recommended crystals. Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal. Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specifications might set the flag. Measured with logic-level input frequency but also applies to operation with crystals. Specifications Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 29 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com 5.17 Internal Very-Low-Power Low-Frequency Oscillator (VLO) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC fVLO VLO frequency Measured at ACLK 1.8 V to 3.6 V dfVLO/dT VLO frequency temperature drift Measured at ACLK (1) 1.8 V to 3.6 V Measured at ACLK (2) 1.8 V to 3.6 V Measured at ACLK 1.8 V to 3.6 V dfVLO/dVCC VLO frequency supply voltage drift Duty cycle (1) (2) MIN TYP MAX 6 9.4 14 0.5 50% kHz %/°C 4 40% UNIT %/V 60% Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C)) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V) 5.18 Internal Reference, Low-Frequency Oscillator (REFO) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER IREFO fREFO TEST CONDITIONS VCC MIN TYP 1.8 V to 3.6 V 3 REFO frequency calibrated Measured at ACLK 1.8 V to 3.6 V 32768 Full temperature range 1.8 V to 3.6 V ±3.5% 3V ±1.5% REFO absolute tolerance calibrated TA = 25°C (1) dfREFO/dT REFO frequency temperature drift Measured at ACLK 1.8 V to 3.6 V 0.01 dfREFO/dVCC REFO frequency supply voltage drift Measured at ACLK (2) 1.8 V to 3.6 V 1.0 Duty cycle Measured at ACLK 1.8 V to 3.6 V REFO start-up time 40%/60% duty cycle 1.8 V to 3.6 V tSTART (1) (2) 30 MAX REFO oscillator current consumption TA = 25°C 40% 50% UNIT µA Hz %/°C %/V 60% 25 µs Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C)) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V) Specifications Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 5.19 DCO Frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT fDCO(0,0) DCO frequency (0, 0) DCORSELx = 0, DCOx = 0, MODx = 0 0.07 0.20 MHz fDCO(0,31) DCO frequency (0, 31) (1) DCORSELx = 0, DCOx = 31, MODx = 0 0.70 1.70 MHz fDCO(1,0) DCO frequency (1, 0) (1) DCORSELx = 1, DCOx = 0, MODx = 0 0.15 0.36 MHz fDCO(1,31) DCO frequency (1, 31) (1) DCORSELx = 1, DCOx = 31, MODx = 0 1.47 3.45 MHz (1) fDCO(2,0) DCO frequency (2, 0) DCORSELx = 2, DCOx = 0, MODx = 0 0.32 0.75 MHz fDCO(2,31) DCO frequency (2, 31) (1) DCORSELx = 2, DCOx = 31, MODx = 0 3.17 7.38 MHz fDCO(3,0) DCO frequency (3, 0) (1) DCORSELx = 3, DCOx = 0, MODx = 0 0.64 1.51 MHz (1) fDCO(3,31) DCO frequency (3, 31) DCORSELx = 3, DCOx = 31, MODx = 0 6.07 14.0 MHz fDCO(4,0) DCO frequency (4, 0) (1) DCORSELx = 4, DCOx = 0, MODx = 0 1.3 3.2 MHz fDCO(4,31) DCO frequency (4, 31) (1) DCORSELx = 4, DCOx = 31, MODx = 0 12.3 28.2 MHz (1) fDCO(5,0) DCO frequency (5, 0) DCORSELx = 5, DCOx = 0, MODx = 0 2.5 6.0 MHz fDCO(5,31) DCO frequency (5, 31) (1) DCORSELx = 5, DCOx = 31, MODx = 0 23.7 54.1 MHz fDCO(6,0) DCO frequency (6, 0) (1) DCORSELx = 6, DCOx = 0, MODx = 0 4.6 10.7 MHz fDCO(6,31) DCO frequency (6, 31) (1) DCORSELx = 6, DCOx = 31, MODx = 0 39.0 88.0 MHz (1) fDCO(7,0) DCO frequency (7, 0) DCORSELx = 7, DCOx = 0, MODx = 0 8.5 19.6 MHz fDCO(7,31) DCO frequency (7, 31) (1) DCORSELx = 7, DCOx = 31, MODx = 0 60 135 MHz SDCORSEL Frequency step between range DCORSEL and DCORSEL + 1 SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO) 1.2 2.3 ratio SDCO Frequency step between tap DCO and DCO + 1 SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO) 1.02 1.12 ratio Duty cycle Measured at SMCLK 40% dfDCO/dT DCO frequency temperature drift dfDCO/dVCC DCO frequency voltage drift (3) (1) (2) (3) (2) 50% 60% fDCO = 1 MHz, 0.1 %/°C fDCO = 1 MHz 1.9 %/V When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within the range of fDCO(n, 0),MAX ≤ fDCO ≤ fDCO(n, 31),MIN, where fDCO(n, 0),MAX represents the maximum frequency specified for the DCO frequency, range n, tap 0 (DCOx = 0) and fDCO(n,31),MIN represents the minimum frequency specified for the DCO frequency, range n, tap 31 (DCOx = 31). This ensures that the target DCO frequency resides within the range selected. It should also be noted that if the actual fDCO frequency for the selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the selected range is at its minimum or maximum tap setting. Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C)) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V) 100 VCC = 3.0 V TA = 25°C fDCO – MHz 10 DCOx = 31 1 0.1 DCOx = 0 0 1 2 3 4 5 6 7 DCORSEL Figure 5-10. Typical DCO Frequency Specifications Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 31 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com 5.20 PMM, Brownout Reset (BOR) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS V(DVCC_BOR_IT–) BORH on voltage, DVCC falling level | dDVCC/dt | < 3 V/s V(DVCC_BOR_IT+) BORH off voltage, DVCC rising level | dDVCC/dt | < 3 V/s V(DVCC_BOR_hys) BORH hysteresis tRESET Pulse duration required at RST/NMI pin to accept a reset MIN TYP 0.80 1.30 50 MAX UNIT 1.45 V 1.50 V 250 mV 2 µs 5.21 PMM, Core Voltage over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCORE3(AM) Core voltage, active mode, PMMCOREV = 3 2.4 V ≤ DVCC ≤ 3.6 V 1.90 V VCORE2(AM) Core voltage, active mode, PMMCOREV = 2 2.2 V ≤ DVCC ≤ 3.6 V 1.80 V VCORE1(AM) Core voltage, active mode, PMMCOREV = 1 2.0 V ≤ DVCC ≤ 3.6 V 1.60 V VCORE0(AM) Core voltage, active mode, PMMCOREV = 0 1.8 V ≤ DVCC ≤ 3.6 V 1.40 V VCORE3(LPM) Core voltage, low-current mode, PMMCOREV = 3 2.4 V ≤ DVCC ≤ 3.6 V 1.94 V VCORE2(LPM) Core voltage, low-current mode, PMMCOREV = 2 2.2 V ≤ DVCC ≤ 3.6 V 1.84 V VCORE1(LPM) Core voltage, low-current mode, PMMCOREV = 1 2.0 V ≤ DVCC ≤ 3.6 V 1.64 V VCORE0(LPM) Core voltage, low-current mode, PMMCOREV = 0 1.8 V ≤ DVCC ≤ 3.6 V 1.44 V 32 Specifications Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 5.22 PMM, SVS High Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN SVSHE = 0, DVCC = 3.6 V I(SVSH) SVS current consumption V(SVSH_IT+) tpd(SVSH) SVSH on voltage level (1) SVSH off voltage level (1) SVSH propagation delay t(SVSH) SVSH on or off delay time dVDVCC/dt DVCC rise time (1) MAX 0 SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0 1.5 µA SVSHE = 1, SVSHRVL = 0 1.57 1.68 1.78 SVSHE = 1, SVSHRVL = 1 1.79 1.88 1.98 SVSHE = 1, SVSHRVL = 2 1.98 2.08 2.21 SVSHE = 1, SVSHRVL = 3 2.10 2.18 2.31 SVSHE = 1, SVSMHRRL = 0 1.62 1.74 1.85 SVSHE = 1, SVSMHRRL = 1 1.88 1.94 2.07 SVSHE = 1, SVSMHRRL = 2 2.07 2.14 2.28 SVSHE = 1, SVSMHRRL = 3 2.20 2.30 2.42 SVSHE = 1, SVSMHRRL = 4 2.32 2.40 2.55 SVSHE = 1, SVSMHRRL = 5 2.52 2.70 2.88 SVSHE = 1, SVSMHRRL = 6 2.90 3.10 3.23 SVSHE = 1, SVSMHRRL = 7 2.90 3.10 3.23 SVSHE = 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1 2.5 SVSHE = 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0 20 UNIT nA 200 SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1 V(SVSH_IT–) TYP V V µs SVSHE = 0 → 1, SVSHFP = 1 12.5 SVSHE = 0 → 1, SVSHFP = 0 100 0 µs 1000 V/s The SVSH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430F5xx and MSP430F6xx Family User's Guide on recommended settings and use. Specifications Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 33 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com 5.23 PMM, SVM High Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN SVMHE = 0, DVCC = 3.6 V I(SVMH) SVMH current consumption SVMH on or off voltage level 1.5 tpd(SVMH) t(SVMH) (1) SVMH propagation delay SVMH on or off delay time µA SVMHE = 1, SVSMHRRL = 0 1.62 1.74 1.85 SVMHE = 1, SVSMHRRL = 1 1.88 1.94 2.07 SVMHE = 1, SVSMHRRL = 2 2.07 2.14 2.28 SVMHE = 1, SVSMHRRL = 3 2.20 2.30 2.42 SVMHE = 1, SVSMHRRL = 4 2.32 2.40 2.55 SVMHE = 1, SVSMHRRL = 5 2.52 2.70 2.88 SVMHE = 1, SVSMHRRL = 6 2.90 3.10 3.23 SVMHE = 1, SVSMHRRL = 7 2.90 3.10 3.23 SVMHE = 1, SVMHOVPE = 1 UNIT nA 200 SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1 V(SVMH) MAX 0 SVMHE = 1, DVCC = 3.6 V, SVMHFP = 0 (1) TYP V 3.75 SVMHE = 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1 2.5 SVMHE = 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0 20 µs SVMHE = 0 → 1, SVMHFP = 1 12.5 SVMHE = 0 → 1, SVMHFP = 0 100 µs The SVMH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430F5xx and MSP430F6xx Family User's Guide on recommended settings and use. 5.24 PMM, SVS Low Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN SVSLE = 0, PMMCOREV = 2 I(SVSL) SVSL current consumption tpd(SVSL) t(SVSL) 34 SVSL propagation delay SVSL on or off delay time Specifications TYP MAX 0 SVSLE = 1, PMMCOREV = 2, SVSLFP = 0 200 SVSLE = 1, PMMCOREV = 2, SVSLFP = 1 2.0 SVSLE = 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1 2.5 SVSLE = 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0 20 UNIT nA µA µs SVSLE = 0 → 1, SVSLFP = 1 12.5 SVSLE = 0 → 1, SVSLFP = 0 100 µs Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 5.25 PMM, SVM Low Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP SVMLE = 0, PMMCOREV = 2 I(SVML) SVML current consumption tpd(SVML) SVML propagation delay t(SVML) SVML on or off delay time MAX UNIT 0 SVMLE = 1, PMMCOREV = 2, SVMLFP = 0 200 SVMLE = 1, PMMCOREV = 2, SVMLFP = 1 1.5 SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1 2.5 SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0 20 SVMLE = 0 → 1, SVMLFP = 1 12.5 SVMLE = 0 → 1, SVMLFP = 0 100 nA µA µs µs 5.26 Wake-up Times From Low-Power Modes and Reset over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fMCLK < 4.0 MHz 6 tWAKE-UP-SLOW Wake-up time from LPM2, LPM3, or PMMCOREV = SVSMLRRL = n LPM4 to active mode (2) (3) (where n = 0, 1, 2, or 3), SVSLFP = 0 tWAKE-UP-LPM5 tWAKE-UP-RESET (2) (3) (4) TYP MAX UNIT 5 tWAKE-UP-FAST (1) MIN fMCLK ≥ 4.0 MHz PMMCOREV = SVSMLRRL = n Wake-up time from LPM2, LPM3, or (where n = 0, 1, 2, or 3), (1) LPM4 to active mode SVSLFP = 1 µs 150 165 µs Wake-up time from LPM4.5 to active mode (4) 2 3 ms Wake-up time from RST or BOR event to active mode (4) 2 3 ms This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-FAST is possible with SVSL and SVML in full performance mode or disabled. For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode Selection section in the Power Management Module and Supply Voltage Supervisor chapter of the MSP430F5xx and MSP430F6xx Family User's Guide. This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-SLOW is set with SVSL and SVML in normal mode (low current mode). For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode Selection section in the Power Management Module and Supply Voltage Supervisor chapter of the MSP430F5xx and MSP430F6xx Family User's Guide. The wake-up times from LPM0 and LPM1 to AM are not specified. They are proportional to MCLK cycle time but are not affected by the performance mode settings as for LPM2, LPM3, and LPM4. This value represents the time from the wake-up event to the reset vector execution. 5.27 Timer_A over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC fTA Timer_A input clock frequency Internal: SMCLK or ACLK, External: TACLK, Duty cycle = 50% ±10% 1.8 V, 3 V tTA,cap Timer_A capture timing All capture inputs, Minimum pulse duration required for capture. 1.8 V, 3 V MIN MAX UNIT 25 MHz 20 ns 5.28 Timer_B over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC fTB Timer_B input clock frequency Internal: SMCLK or ACLK, External: TBCLK, Duty cycle = 50% ±10% 1.8 V, 3 V tTB,cap Timer_B capture timing All capture inputs, Minimum pulse duration required for capture 1.8 V, 3 V MIN MAX UNIT 25 MHz 20 Specifications Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated ns 35 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com 5.29 USCI (UART Mode) Clock Frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN Internal: SMCLK or ACLK, External: UCLK, Duty cycle = 50% ±10% fUSCI USCI input clock frequency fBITCLK BITCLK clock frequency (equals baud rate in MBaud) MAX UNIT fSYSTEM MHz 1 MHz UNIT 5.30 USCI (UART Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER (1) VCC UART receive deglitch time (1) tτ MIN MAX 2.2 V 50 600 3V 50 600 ns Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are correctly recognized, their duration should exceed the maximum specification of the deglitch time. 5.31 USCI (SPI Master Mode) Clock Frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fUSCI USCI input clock frequency CONDITIONS MIN Internal: SMCLK or ACLK, Duty cycle = 50% ±10% MAX UNIT fSYSTEM MHz MAX UNIT fSYSTE MHz 5.32 USCI (SPI Master Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (see Figure 5-11 and Figure 5-12) PARAMETER fUSCI USCI input clock frequency TEST CONDITIONS SOMI input data setup time PMMCOREV = 3 PMMCOREV = 0 tHD,MI SOMI input data hold time PMMCOREV = 3 tVALID,MO SIMO output data valid time (2) (2) (3) 36 55 3V 38 2.4 V 30 3V 25 1.8 V 0 3V 0 2.4 V 0 3V 0 ns ns UCLK edge to SIMO valid, CL = 20 pF, PMMCOREV = 0 20 3V 18 UCLK edge to SIMO valid, CL = 20 pF, PMMCOREV = 3 2.4 V 16 SIMO output data hold time (3) CL = 20 pF, PMMCOREV = 3 (1) 1.8 V 1.8 V CL = 20 pF, PMMCOREV = 0 tHD,MO MIN M PMMCOREV = 0 tSU,MI VCC SMCLK, ACLK Duty cycle = 50% ±10% 3V 1.8 V ns 15 –10 3V –8 2.4 V –10 3V –8 ns fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)) For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave. Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams in Figure 5-11 and Figure 5-12. Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 511 and Figure 5-12. Specifications Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tHD,MO tVALID,MO SIMO Figure 5-11. SPI Master Mode, CKPH = 0 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tHD,MO tVALID,MO SIMO Figure 5-12. SPI Master Mode, CKPH = 1 Specifications Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 37 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com 5.33 USCI (SPI Slave Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (see Figure 5-13 and Figure 5-14) PARAMETER TEST CONDITIONS PMMCOREV = 0 tSTE,LEAD STE lead time, STE low to clock PMMCOREV = 3 PMMCOREV = 0 tSTE,LAG STE lag time, Last clock to STE high PMMCOREV = 3 PMMCOREV = 0 tSTE,ACC STE access time, STE low to SOMI data out PMMCOREV = 3 PMMCOREV = 0 STE disable time, STE high to SOMI high impedance tSTE,DIS PMMCOREV = 3 SIMO input data setup time PMMCOREV = 3 PMMCOREV = 0 tHD,SI SIMO input data hold time PMMCOREV = 3 tVALID,SO tHD,SO (1) (2) (3) 38 SOMI output data valid time (2) SOMI output data hold time (3) MIN 11 3V 8 2.4 V 7 3V 6 1.8 V 3 3V 3 2.4 V 3 3V 3 MAX UNIT ns ns 1.8 V 66 3V 50 2.4 V 36 3V 30 1.8 V 30 3V 23 2.4 V 16 3V PMMCOREV = 0 tSU,SI VCC 1.8 V ns ns 13 1.8 V 5 3V 5 2.4 V 2 3V 2 1.8 V 5 3V 5 2.4 V 5 3V 5 ns ns UCLK edge to SOMI valid, CL = 20 pF, PMMCOREV = 0 1.8 V 76 3V 60 UCLK edge to SOMI valid, CL = 20 pF, PMMCOREV = 3 2.4 V 44 3V 40 CL = 20 pF, PMMCOREV = 0 1.8 V 18 3V 12 CL = 20 pF, PMMCOREV = 3 2.4 V 10 3V 8 ns ns fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)) For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master. Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams in Figure 5-13 and Figure 5-14. Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-13 and Figure 5-14. Specifications Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tSU,SI tLO/HI tHD,SI SIMO tHD,SO tVALID,SO tSTE,ACC tSTE,DIS SOMI Figure 5-13. SPI Slave Mode, CKPH = 0 tSTE,LAG tSTE,LEAD STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tHD,SI tSU,SI SIMO tSTE,ACC tHD,MO tVALID,SO tSTE,DIS SOMI Figure 5-14. SPI Slave Mode, CKPH = 1 Specifications Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 39 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com 5.34 USCI (I2C Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-15) PARAMETER TEST CONDITIONS VCC MIN Internal: SMCLK or ACLK, External: UCLK Duty cycle = 50% ±10% MAX UNIT fSYSTEM MHz 400 kHz fUSCI USCI input clock frequency fSCL SCL clock frequency tHD,STA Hold time (repeated) START tSU,STA Setup time for a repeated START tHD,DAT Data hold time 2.2 V, 3 V 0 ns tSU,DAT Data setup time 2.2 V, 3 V 250 ns 2.2 V, 3 V fSCL ≤ 100 kHz fSCL ≤ 100 kHz fSCL ≤ 100 kHz tSP Pulse duration of spikes suppressed by input filter tSU,STA tHD,STA 4.7 µs 0.6 4.0 2.2 V, 3 V fSCL > 100 kHz µs 0.6 2.2 V, 3 V fSCL > 100 kHz Setup time for STOP 4.0 2.2 V, 3 V fSCL > 100 kHz tSU,STO 0 µs 0.6 2.2 V 50 600 3V 50 600 tHD,STA ns tBUF SDA tLOW tHIGH tSP SCL tSU,DAT tSU,STO tHD,DAT Figure 5-15. I2C Mode Timing 40 Specifications Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 5.35 10-Bit ADC, Power Supply and Input Range Conditions over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TEST CONDITIONS VCC AVCC Analog supply voltage AVCC and DVCC are connected together, AVSS and DVSS are connected together, V(AVSS) = V(DVSS) = 0 V V(Ax) Analog input voltage range (2) All ADC10_A pins: P1.0 to P1.5 and P3.6 and P3.7 terminals Operating supply current into AVCC terminal, REF module and reference buffer off fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF = 00 Operating supply current into AVCC terminal, REF module on, reference buffer on MIN TYP MAX 1.8 3.6 V 0 AVCC V 2.2 V 60 100 3V 75 110 fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 1, SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF = 01 3V 113 150 Operating supply current into AVCC terminal, REF module off, reference buffer on fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF = 10, VEREF = 2.5 V 3V 105 140 Operating supply current into AVCC terminal, REF module off, reference buffer off fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF = 11, VEREF = 2.5 V 3V 70 110 CI Input capacitance Only one terminal Ax can be selected at one time from the pad to the ADC10_A capacitor array including wiring and pad. 2.2 V 3.5 RI Input MUX ON resistance IADC10_A (1) (2) UNIT µA pF AVCC > 2.0 V, 0 V ≤ VAx ≤ AVCC 36 1.8V < AVCC < 2.0 V, 0 V ≤ VAx ≤ AVCC 96 kΩ The leakage current is defined in the leakage current table with P6.x/Ax parameter. The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. The external reference voltage requires decoupling capacitors. Two decoupling capacitors, 10 µF and 100 nF, should be connected to VeREF to decouple the dynamic current required for an external reference source if it is used for the ADC10_A. Also see the MSP430F5xx and MSP430F6xx Family User's Guide. 5.36 10-Bit ADC, Timing Parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC MIN TYP MAX UNIT For specified performance of ADC10_A linearity parameters 2.2 V, 3 V 0.45 5 5.5 MHz Internal ADC10_A oscillator (1) ADC10DIV = 0, fADC10CLK = fADC10OSC 2.2 V, 3 V 4.2 4.8 5.4 MHz 2.2 V, 3 V 2.4 Conversion time REFON = 0, Internal oscillator, 12 ADC10CLK cycles, 10-bit mode, fADC10OSC = 4 MHz to 5 MHz fADC10CLK fADC10OSC tCONVERT TEST CONDITIONS µs External fADC10CLK from ACLK, MCLK, or SMCLK, ADC10SSEL ≠ 0 tADC10ON Turn-on settling time of the ADC tSample Sampling time (1) (2) (3) See 3.0 12 × 1 / fADC10CLK (2) 100 RS = 1000 Ω, RI = 96 kΩ, CI = 3.5 pF (3) 1.8 V 3 RS = 1000 Ω, RI = 36 kΩ, CI = 3.5 pF (3) 3V 1 ns µs The ADC10OSC is sourced directly from MODOSC in the UCS. The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already settled. Approximately 8 Tau (τ) are required for an error of less than ±0.5 LSB Specifications Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 41 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com 5.37 10-Bit ADC, Linearity Parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS 1.4 V ≤ (VeREF+ – VeREF–) ≤ 1.6 V, CVeREF+ = 20 pF VCC MIN TYP MAX ±1.0 UNIT EI Integral linearity error ED Differential linearity error 1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF 2.2 V, 3 V ±1.0 LSB EO Offset error 1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF, Internal impedance of source RS < 100 Ω 2.2 V, 3 V ±1.0 LSB EG Gain error 1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF, ADC10SREFx = 11b 2.2 V, 3 V ±1.0 LSB ET Total unadjusted error 1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF, ADC10SREFx = 11b 2.2 V, 3 V ±2.0 LSB MAX UNIT 1.6 V < (VeREF+ – VeREF–) ≤ VAVCC, CVeREF+ = 20 pF 2.2 V, 3 V ±1.0 ±1.0 LSB 5.38 REF, External Reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TEST CONDITIONS VCC MIN TYP VeREF+ Positive external reference VeREF+ > VeREF– voltage input (2) 1.4 AVCC V VeREF– Negative external reference voltage input VeREF+ > VeREF– (3) 0 1.2 V (VeREF+ – VeREF–) Differential external reference voltage input VeREF+ > VeREF– (4) 1.4 AVCC V IVeREF+ IVeREF– Static input current CVeREF+/(1) (2) (3) (4) (5) 42 Capacitance at VeREF+ or VeREF- terminal 1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V, fADC10CLK = 5 MHz, ADC10SHTx = 0x0001, Conversion rate 200 ksps 2.2 V, 3 V 1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V, fADC10CLK = 5 MHZ, ADC10SHTX = 0x1000, Conversion rate 20 ksps 2.2 V, 3 V (5) ±8.5 ±26 µA ±1 10 µF The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements. Two decoupling capacitors, 10 µF and 100 nF, should be connected to VeREF to decouple the dynamic current required for an external reference source if it is used for the ADC10_A. Also see the MSP430F5xx and MSP430F6xx Family User's Guide. Specifications Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 5.39 REF, Built-In Reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER Positive built-in reference voltage VREF+ AVCC minimum voltage, Positive built-in reference active AVCC(min) Operating supply current into AVCC terminal (2) IREF+ TEST CONDITIONS VCC MIN TYP MAX REFVSEL = {2} for 2.5 V, REFON = 1 3V 2.51 ±1.5% REFVSEL = {1} for 2.0 V, REFON = 1 3V 1.99 ±1.5% REFVSEL = {0} for 1.5 V, REFON = 1 2.2 V, 3 V UNIT V 1.5 ±1.5% REFVSEL = {0} for 1.5 V 1.8 REFVSEL = {1} for 2.0 V 2.2 REFVSEL = {2} for 2.5 V 2.7 V fADC10CLK = 5.0 MHz, REFON = 1, REFBURST = 0, REFVSEL = {2} for 2.5 V 3V 18 24 fADC10CLK = 5.0 MHz, REFON = 1, REFBURST = 0, REFVSEL = {1} for 2.0 V 3V 15.5 21 fADC10CLK = 5.0 MHz, REFON = 1, REFBURST = 0, REFVSEL = {0} for 1.5 V 3V 13.5 21 30 50 2.2 V 20 22 3V 20 22 2.2 V 770 3V 770 µA TCREF+ Temperature coefficient of built-in reference (3) IVREF+ = 0 A, REFVSEL = {0, 1, 2}, REFON = 1 ISENSOR Operating supply current into AVCC terminal (4) REFON = 0, INCH = 0Ah, ADC10ON = N/A, TA = 30°C VSENSOR See VMID AVCC divider at channel 11 ADC10ON = 1, INCH = 0Bh, VMID ≈ 0.5 × VAVCC tSENSOR(sample) Sample time required if channel 10 is selected (6) ADC10ON = 1, INCH = 0Ah, Error of conversion result ≤ 1 LSB 30 µs tVMID(sample) Sample time required if channel 11 is selected (7) ADC10ON = 1, INCH = 0Bh, Error of conversion result ≤ 1 LSB 1 µs PSRR_DC Power supply rejection ratio (DC) AVCC = AVCC(min) to AVCC(max), TA = 25°C, REFVSEL = {0, 1, 2}, REFON = 1 120 µV/V PSRR_AC Power supply rejection ratio (AC) AVCC = AVCC(min) to AVCC(max), TA = 25°C, f = 1 kHz, ΔVpp = 100 mV, REFVSEL = {0, 1, 2}, REFON = 1 6.4 mV/V tSETTLE Settling time of reference voltage (8) AVCC = AVCC(min) to AVCC(max), REFVSEL = {0, 1, 2}, REFON = 0 → 1 75 µs (1) (2) (3) (4) (5) (6) (7) (8) (5) ADC10ON = 1, INCH = 0Ah, TA = 30°C ppm/ °C µA mV 2.2 V 1.06 1.1 1.14 3V 1.46 1.5 1.54 V The leakage current is defined in the leakage current table with P6.x/Ax parameter. The internal reference current is supplied from terminal AVCC. Consumption is independent of the ADC10ON control bit, unless a conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion. Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C – (–40°C)). The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is high). When REFON = 1, ISENSOR is already included in IREF+. The temperature sensor offset can be significant. TI recommends a single-point calibration to minimize the offset error of the built-in temperature sensor. The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor on-time tSENSOR(on). The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed. The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. Specifications Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 43 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com 5.40 Comparator B over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC TEST CONDITIONS VCC Supply voltage MIN TYP 1.8 MAX 3.6 1.8 V CBPWRMD = 00, CBON = 1, CBRS = 00 IAVCC_COMP IAVCC_REF VIC Comparator operating supply current into AVCC, Excludes reference resistor ladder Quiescent current of resistor ladder into AVCC, Includes REF module current VOFFSET Input offset voltage CIN Input capacitance RSIN Series input resistance 30 50 3V 40 65 CBPWRMD = 01, CBON = 1, CBRS = 00 2.2 V, 3 V 10 17 CBPWRMD = 10, CBON = 1, CBRS = 00 2.2 V, 3 V 0.1 0.5 CBREFACC = 1, CBREFLx = 01, CBRS = 10, REFON = 0, CBON = 0 2.2 V, 3 V 10 17 CBREFACC = 0, CBREFLx = 01, CBRS = 10, REFON = 0, CBON = 0 2.2 V, 3 V tPD Propagation delay, response time Propagation delay with filter active tPD,filter tEN_CMP Comparator enable time VCC – 1 ±20 CBPWRMD = 01 or 10 ±10 5 On (switch closed) 4 50 450 600 CBPWRMD = 10, CBF = 0 50 CBPWRMD = 00, CBON = 1, CBF = 1, CBFDLY = 00 0.35 0.6 1.0 CBPWRMD = 00, CBON = 1, CBF = 1, CBFDLY = 01 0.6 1.0 1.8 CBPWRMD = 00, CBON = 1, CBF = 1, CBFDLY = 10 1.0 1.8 3.4 CBPWRMD = 00, CBON = 1, CBF = 1, CBFDLY = 11 1.8 3.4 6.5 1 2 VIN = reference into resistor ladder, n = 0 to 31 ns µs µs CBON = 0 to CBON = 1 CBPWRMD = 10 Reference voltage for a given tap kΩ µs CBON = 0 to CBON = 1 CBPWRMD = 00 or 01 VCB_REF mV MΩ CBPWRMD = 01, CBF = 0 CBON = 0 to CBON = 1 V pF 3 CBPWRMD = 00, CBF = 0 Resistor reference enable time Specifications µA 22 0 tEN_REF 44 µA CBPWRMD = 00 Off (switch open) V 40 2.2 V Common mode input range UNIT 100 VIN × (n + 0.5) / 32 1 1.5 µs VIN × (n + 1) / 32 VIN × (n + 1.5) / 32 V Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 5.41 Ports PU.0 and PU.1 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VOH High-level output voltage VUSB = 3.3 V ±10%, IOH = –25 mA. See Figure 5-17 for typical characteristics VOL Low-level output voltage VUSB = 3.3 V ±10%, IOL = 25 mA. See Figure 5-16 for typical characteristics VIH High-level input voltage VUSB = 3.3 V ±10% See Figure 5-18 for typical characteristics VIL Low-level input voltage VUSB = 3.3 V ±10% See Figure 5-18 for typical characteristics MIN MAX 2.4 V 0.4 2.0 V V 0.8 Specifications Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated UNIT V 45 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com IOL - Typical Low-Level Output Current - mA 90 VCC = 3.0 V TA = 25ºC 80 VCC = 3.0 V TA = 85ºC VCC = 1.8 V TA = 25ºC 70 60 50 VCC = 1.8 V TA = 85ºC 40 30 20 10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 VOL - Low-Level Output Voltage - V Figure 5-16. Ports PU.0, PU.1 Typical Low-Level Output Characteristics IOH - Typical High-Level Output Current - mA 0 -10 -20 -30 VCC = 1.8 V TA = 85ºC -40 -50 VCC = 3.0 V TA = 85ºC -60 VCC = 1.8 V TA = 25ºC -70 VCC = 3.0 V TA = 25ºC -80 -90 0.5 1 1.5 2 VOH - High-Level Output Voltage - V 2.5 3 Figure 5-17. Ports PU.0, PU.1 Typical High-Level Output Characteristics 2.0 TA = 25°C, 85°C 1.8 VIT+, postive-going input threshold 1.6 Input Threshold - V 1.4 1.2 VIT–, negative-going input threshold 1.0 0.8 0.6 0.4 0.2 0.0 1.8 2.2 2.6 VUSB Supply Voltage, VUSB - V 3 3.4 Figure 5-18. Ports PU.0, PU.1 Typical Input Threshold Characteristics 46 Specifications Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 5.42 USB Output Ports (DP and DM) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT VOH D+, D- single ended USB 2.0 load conditions 2.8 3.6 VOL D+, D- single ended USB 2.0 load conditions 0 0.3 V V Z(DRV) D+, D- impedance Including external series resistor of 27 Ω 28 44 Ω tRISE Rise time Full speed, differential, CL = 50 pF, 10%/90%, Rpu on D+ 4 20 ns tFALL Fall time Full speed, differential, CL = 50 pF, 10%/90%, Rpu on D+ 4 20 ns UNIT 5.43 USB Input Ports (DP and DM) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) MIN MAX VCM Differential input common mode range PARAMETER 0.8 2.5 ZIN Input impedance 300 VCRS Crossover voltage 1.3 VIL Static SE input logic low level VIH Static SE input logic high level VDI Differential input voltage V kΩ 2.0 V 0.8 V 2.0 V 0.2 V MAX UNIT 3.75 V 5.5 V ±9% V 5.44 USB-PWR (USB Power System) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP VLAUNCH VBUS detection threshold VBUS USB bus voltage VUSB USB LDO output voltage 3.3 V18 Internal USB voltage (1) 1.8 IUSB_EXT Maximum external current from VUSB terminal (2) Normal operation 3.76 USB LDO is on (3) 12 mA 100 mA 250 µA IDET USB LDO current overload detection ISUSPEND Operating supply current into VBUS terminal (4) IUSB_LDO USB LDO on, Operating supply current into VBUS terminal, USB 1.8-V LDO disabled, Represents the current of the 3.3-V LDO only VBUS = 5 V, USBDETEN = 0 or 1 1.8 V, 3 V 60 µA IVBUS_DETECT USB LDO disabled, Operating supply current into VBUS terminal, USB 1.8-V LDO disabled, Represents the current of the VBUS VBUS > VLAUNCH, detection logic USBDETEN = 1 1.8 V, 3 V 30 µA CBUS VBUS terminal recommended capacitance 4.7 µF CUSB VUSB terminal recommended capacitance 220 nF C18 V18 terminal recommended capacitance 220 nF tENABLE Settling time VUSB and V18 RPUR Pullup resistance of PUR terminal (5) (1) (2) (3) (4) (5) 60 V USB LDO on, USB PLL disabled Within 2%, recommended capacitances 70 110 2 ms 150 Ω This voltage is for internal use only. No external DC loading should be applied. This represents additional current that can be supplied to the application from the VUSB terminal beyond the needs of the USB operation. A current overload is detected when the total current supplied from the USB LDO, including IUSB_EXT, exceeds this value. Does not include current contribution of Rpu and Rpd as outlined in the USB specification. This value, in series with an external resistor between PUR and D+, produces the Rpu as outlined in the USB specification. Specifications Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 47 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com 5.45 USB-PLL (USB Phase-Locked Loop) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER IPLL Operating supply current fPLL PLL frequency fUPD PLL reference frequency tLOCK PLL lock time tJitter PLL jitter MIN TYP MAX 7 48 UNIT mA MHz 1.5 3 MHz 2 ms 1000 ps 5.46 Flash Memory over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TJ DVCC(PGM/ERASE) Program and erase supply voltage MIN TYP 1.8 MAX UNIT 3.6 V 200 ns 3 5 mA Supply current from DVCC during erase 2 6.5 mA Supply current from DVCC during mass erase or bank erase 2 6.5 mA tREADMARGIN Read access time during marginal mode IPGM Supply current from DVCC during program IERASE IMERASE, IBANK tCPT Cumulative program time (1) 16 104 Program and erase endurance ms cycles tRetention Data retention duration tWord Word or byte program time (2) 64 85 µs tBlock, 0 Block program time for first byte or word (2) 49 65 µs tBlock, 1–(N–1) Block program time for each additional byte or word, except for last byte or word (2) 37 49 µs 55 73 µs 23 32 ms tBlock, Block program time for last byte or word N (2) (2) Erase time for segment, mass erase, and bank erase when available (2) tErase (1) 25°C 105 100 years The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming methods: individual word write, individual byte write, and block write modes. These values are hardwired into the state machine of the flash controller. 5.47 JTAG and Spy-Bi-Wire Interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC MIN TYP MAX UNIT fSBW Spy-Bi-Wire input frequency 2.2 V, 3 V 0 20 MHz tSBW,Low Spy-Bi-Wire low clock pulse duration 2.2 V, 3 V 0.025 15 µs tSBW, En Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge) (1) 2.2 V, 3 V 1 µs tSBW,Rst Spy-Bi-Wire return to normal operation time fTCK TCK input frequency for 4-wire JTAG (2) Rinternal Internal pulldown resistance on TEST (1) (2) 48 2.2 V 15 100 0 5 MHz 10 MHz 80 kΩ 3V 0 2.2 V, 3 V 45 60 µs Tools that access the Spy-Bi-Wire and BSL interfaces must wait for the tSBW,En time after the first transition of the TEST/SBWTCK pin (low to high), before the second transition of the pin (high to low) during the entry sequence. fTCK may be restricted to meet the timing requirements of the module selected. Specifications Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 6 Detailed Description 6.1 CPU (Link to User's Guide) The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers (see Figure 6-1). Peripherals are connected to the CPU using data, address, and control buses. Peripherals can be managed with all instructions. The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data. Program Counter PC/R0 Stack Pointer SP/R1 Status Register Constant Generator SR/CG1/R2 CG2/R3 General-Purpose Register R4 General-Purpose Register R5 General-Purpose Register R6 General-Purpose Register R7 General-Purpose Register R8 General-Purpose Register R9 General-Purpose Register R10 General-Purpose Register R11 General-Purpose Register R12 General-Purpose Register R13 General-Purpose Register R14 General-Purpose Register R15 Figure 6-1. Integrated CPU Registers Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 49 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 6.2 www.ti.com Operating Modes These microcontrollers have one active mode and six software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. Software can configure the following seven operating modes: • Active mode (AM) – All clocks are active • Low-power mode 0 (LPM0) – CPU is disabled – ACLK and SMCLK remain active – MCLK is disabled – FLL loop control remains active • Low-power mode 1 (LPM1) – CPU is disabled – FLL loop control is disabled – ACLK and SMCLK remain active – MCLK is disabled • Low-power mode 2 (LPM2) – CPU is disabled – MCLK, FLL loop control, and DCOCLK are disabled – DC generator of the DCO remains enabled – ACLK remains active • Low-power mode 3 (LPM3) – CPU is disabled – MCLK, FLL loop control, and DCOCLK are disabled – DC generator of the DCO is disabled – ACLK remains active • Low-power mode 4 (LPM4) – CPU is disabled – ACLK is disabled – MCLK, FLL loop control, and DCOCLK are disabled – DC generator of the DCO is disabled – Crystal oscillator is stopped – Complete data retention • Low-power mode 4.5 (LPM4.5) – Internal regulator disabled – No data retention – Wake-up input from RST/NMI, P1, and P2. 50 Detailed Description Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com 6.3 SLAS645L – JULY 2009 – REVISED MAY 2020 Interrupt Vector Addresses The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see Table 6-1). The vector contains the 16-bit address of the interrupt-handler instruction sequence. Table 6-1. Interrupt Sources, Flags, and Vectors INTERRUPT SOURCE System Reset Power up External reset Watchdog time-out, password violation Flash memory password violation INTERRUPT FLAG WDTIFG, KEYV (SYSRSTIV) (1) (2) SYSTEM INTERRUPT WORD ADDRESS PRIORITY Reset 0FFFEh 63, highest System NMI PMM Vacant memory access JTAG mailbox SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG, VLRLIFG, VLRHIFG, VMAIFG, JMBINIFG, JMBOUTIFG (SYSSNIV) (1) (Non)maskable 0FFFCh 62 User NMI NMI Oscillator fault Flash memory access violation NMIIFG, OFIFG, ACCVIFG, BUSIFG (SYSUNIV) (1) (2) (Non)maskable 0FFFAh 61 Maskable 0FFF8h 60 Maskable 0FFF6h 59 Comp_B Comparator B interrupt flags (CBIV) (1) TB0 TB0CCR0 CCIFG0 (3) (3) TB0 TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6, TB0IFG (TB0IV) (1) (3) Maskable 0FFF4h 58 Watchdog Timer_A interval timer mode WDTIFG Maskable 0FFF2h 57 USCI_A0 receive or transmit UCA0RXIFG, UCA0TXIFG (UCA0IV) (1) USCI_B0 receive or transmit UCB0RXIFG, UCB0TXIFG (UCB0IV) ADC10_A ADC10IFG0 (1) TA0 TA0 USB_UBM DMA 0FFF0h 56 Maskable 0FFEEh 55 Maskable 0FFECh 54 Maskable 0FFEAh 53 Maskable 0FFE8h 52 Maskable 0FFE6h 51 (3) (4) TA0CCR0 CCIFG0 (3) USB interrupts (USBIV) (1) (3) DMA0IFG, DMA1IFG, DMA2IFG (DMAIV) (1) (3) Maskable 0FFE4h 50 TA1 TA1CCR0 CCIFG0 (3) Maskable 0FFE2h 49 TA1 TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2, TA1IFG (TA1IV) (1) (3) Maskable 0FFE0h 48 I/O port P1 P1IFG.0 to P1IFG.7 (P1IV) (1) Maskable 0FFDEh 47 USCI_A1 receive or transmit UCA1RXIFG, UCA1TXIFG (UCA1IV) (1) (3) Maskable 0FFDCh 46 USCI_B1 receive or transmit UCB1RXIFG, UCB1TXIFG (UCB1IV) (1) (3) Maskable 0FFDAh 45 Maskable 0FFD8h 44 Maskable 0FFD6h 43 Maskable 0FFD4h 42 Maskable 0FFD2h 41 0FFD0h 40 TA2 I/O port P2 RTC_A TA2CCR0 CCIFG0 (3) (3) TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2, TA2IFG (TA2IV) (1) (3) P2IFG.0 to P2IFG.7 (P2IV) (1) (3) RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG, RT1PSIFG (RTCIV) (1) (3) Reserved (3) (4) (5) Maskable TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4, TA0IFG (TA0IV) (1) (3) TA2 (1) (2) (3) (1) (3) Reserved (5) ⋮ ⋮ 0FF80h 0, lowest Multiple source flags A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space. (Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable bit cannot disable it. Interrupt flags are in the module. Only on devices with ADC, otherwise reserved. Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain compatibility with other devices, TI recommends reserving these locations. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 51 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 6.4 www.ti.com Memory Organization Table 6-2 summarizes the memory map of all device variants. Table 6-2. Memory Organization (1) Memory (flash) Main: interrupt vector Main: code memory MSP430F5504 MSP430F5500 MSP430F5508 MSP430F5505 MSP430F5501 MSP430F5509 MSP430F5506 MSP430F5502 MSP430F5510 MSP430F5507 MSP430F5503 Total Size 8KB 00FFFFh–00FF80h 00FFFFh–00E000h 16KB 00FFFFh–00FF80h 00FFFFh–00C000h 24KB 00FFFFh–00FF80h 00FFFFh–00A000h 32KB 00FFFFh–00FF80h 00FFFFh–008000h Sector 1 2KB 0033FFh–002C00h 2KB 0033FFh–002C00h 2KB 0033FFh–002C00h 2KB 0033FFh–002C00h Sector 0 2KB 002BFFh–002400h 2KB 002BFFh–002400h 2KB 002BFFh–002400h 2KB 002BFFh–002400h 2KB 0023FFh–001C00h 2KB 0023FFh–001C00h 2KB 0023FFh–001C00h 2KB 0023FFh–001C00h Info A 128 B 0019FFh–001980h 128 B 0019FFh–001980h 128 B 0019FFh–001980h 128 B 0019FFh–001980h Info B 128 B 00197Fh–001900h 128 B 00197Fh–001900h 128 B 00197Fh–001900h 128 B 00197Fh–001900h Info C 128 B 0018FFh–001880h 128 B 0018FFh–001880h 128 B 0018FFh–001880h 128 B 0018FFh–001880h Info D 128 B 00187Fh–001800h 128 B 00187Fh–001800h 128 B 00187Fh–001800h 128 B 00187Fh–001800h BSL 3 512 B 0017FFh–001600h 512 B 0017FFh–001600h 512 B 0017FFh–001600h 512 B 0017FFh–001600h BSL 2 512 B 0015FFh–001400h 512 B 0015FFh–001400h 512 B 0015FFh–001400h 512 B 0015FFh–001400h BSL 1 512 B 0013FFh–001200h 512 B 0013FFh–001200h 512 B 0013FFh–001200h 512 B 0013FFh–001200h BSL 0 512 B 0011FFh–001000h 512 B 0011FFh–001000h 512 B 0011FFh–001000h 512 B 0011FFh–001000h 4KB 000FFFh–0h 4KB 000FFFh–0h 4KB 000FFFh–0h 4KB 000FFFh–0h RAM USB RAM (2) Information memory (flash) Bootloader (BSL) memory (flash) Peripherals (1) (2) 52 Size N/A = Not available USB RAM can be used as general purpose RAM when not used for USB operation. Detailed Description Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com 6.5 SLAS645L – JULY 2009 – REVISED MAY 2020 Bootloader (BSL) The BSL enables users to program the flash memory or RAM using various serial interfaces. Access to the device memory through the BSL is protected by an user-defined password. For complete description of the features of the BSL and its implementation, see MSP430 Programming With the Bootloader (BSL). 6.5.1 USB BSL All devices come preprogrammed with the USB BSL. Use of the USB BSL requires external access to six pins (see Table 6-3). In addition to these pins, the application must support external components necessary for normal USB operation (for example, proper crystal on XT2IN and XT2OUT and proper decoupling). For further details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide. Table 6-3. USB BSL Pin Requirements and Functions DEVICE SIGNAL BSL FUNCTION RST/NMI/SBWTDIO Entry sequence signal PU.0/DP USB data terminal DP PU.1/DM USB data terminal DM PUR USB pullup resistor terminal VBUS USB bus power supply VSSU USB ground supply NOTE The default USB BSL evaluates the logic level of the PUR pin after a BOR reset. If it is pulled high externally, then the BSL is invoked. Therefore, unless the BSL should be invoked, it is important to keep PUR pulled low after a BOR reset, even if BSL or USB is never used. TI recommends applying a 1-MΩ resistor to ground. 6.5.2 UART BSL A UART BSL is also available that can be programmed by the user into the BSL memory by replacing the pre-programmed factory-supplied USB BSL. Use of the UART BSL requires external access to six pins (see Table 6-4). For further details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide. Table 6-4. UART BSL Pin Requirements and Functions DEVICE SIGNAL BSL FUNCTION RST/NMI/SBWTDIO Entry sequence signal TEST/SBWTCK Entry sequence signal P1.1 Data transmit P1.2 Data receive VCC Power supply VSS Ground supply Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 53 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 6.6 6.6.1 www.ti.com JTAG Operation JTAG Standard Interface The MSP430 family supports the standard JTAG interface, which requires four signals for sending and receiving data. The JTAG signals are shared with general-purpose I/Os. The TEST/SBWTCK pin is used to enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430 development tools and device programmers. Table 6-5 lists the JTAG pin requirements. For further details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide. For complete description of the features of the JTAG interface and its implementation, see the MSP430 Memory Programming With the JTAG Interface. Table 6-5. JTAG Pin Requirements and Functions 6.6.2 DEVICE SIGNAL DIRECTION FUNCTION PJ.3/TCK IN JTAG clock input PJ.2/TMS IN JTAG state control PJ.1/TDI/TCLK IN JTAG data input, TCLK input PJ.0/TDO OUT JTAG data output TEST/SBWTCK IN Enable JTAG pins RST/NMI/SBWTDIO IN External reset VCC Power supply VSS Ground supply Spy-Bi-Wire Interface In addition to the standard JTAG interface, the MSP430 family supports the two-wire Spy-Bi-Wire interface. Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. Table 6-6 lists the Spy-Bi-Wire interface pin requirements. For further details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide. For complete description of the features of the JTAG interface and its implementation, see the MSP430 Memory Programming With the JTAG Interface. Table 6-6. Spy-Bi-Wire Pin Requirements and Functions 6.7 DEVICE SIGNAL DIRECTION FUNCTION TEST/SBWTCK IN Spy-Bi-Wire clock input RST/NMI/SBWTDIO IN, OUT Spy-Bi-Wire data input/output VCC Power supply VSS Ground supply Flash Memory (Link to User's Guide) The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the flash memory include: • Flash memory has n segments of main memory and four segments of information memory (A to D) of 128 bytes each. Each segment in main memory is 512 bytes in size. • Segments 0 to n may be erased in one step, or each segment may be individually erased. • Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also called information memory. • Segment A can be locked separately. 54 Detailed Description Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com 6.8 SLAS645L – JULY 2009 – REVISED MAY 2020 RAM (Link to User's Guide) The RAM is made up of n sectors. Each sector can be completely powered down to save leakage; however, all data are lost. Features of the RAM include: • RAM has n sectors. The size of a sector can be found in Section 6.4. • Each sector 0 to n can be completely disabled; however, data retention is lost. • Each sector 0 to n automatically enters low-power retention mode when possible. • For devices that contain USB memory, the USB memory can be used as normal RAM if USB is not required. 6.9 Peripherals Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be handled using all instructions. For complete module descriptions, see the MSP430F5xx and MSP430F6xx Family User's Guide. 6.9.1 Digital I/O (Link to User's Guide) Up to six 8-bit I/O ports are implemented: for 64-pin options, P1, P2, P4, P6, and are complete, P5 is reduced to 6-bit I/O, and P3 to 5-bit I/O. For 48-pin options, P6 is reduced to 4-bit I/O, P2 to 1-bit I/O, and P3 is completely removed. Port PJ contains four individual I/O ports, common to all devices. • All individual I/O bits are independently programmable. • Any combination of input, output, and interrupt conditions is possible. • Pullup or pulldown on all ports is programmable. • Drive strength on all ports is programmable. • Edge-selectable interrupt and LPM4.5 wake-up input capability is available for all bits of ports P1 and P2. • Read and write access to port-control registers is supported by all instructions. • Ports can be accessed byte-wise (P1 through P6) or word-wise in pairs (PA through PC). 6.9.2 Port Mapping Controller (Link to User's Guide) The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P4 (see Table 6-7). Table 6-8 lists the default settings for all pins that support port mapping. Table 6-7. Port Mapping Mnemonics and Functions VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION 0 PM_NONE None DVSS PM_CBOUT0 – Comparator_B output PM_TB0CLK TB0 clock input – PM_ADC10CLK – ADC10CLK PM_DMAE0 DMAE0 input – SVM output 1 2 PM_SVMOUT – PM_TB0OUTH TB0 high impedance input TB0OUTH – 4 PM_TB0CCR0A TB0 CCR0 capture input CCI0A TB0 CCR0 compare output Out0 5 PM_TB0CCR1A TB0 CCR1 capture input CCI1A TB0 CCR1 compare output Out1 6 PM_TB0CCR2A TB0 CCR2 capture input CCI2A TB0 CCR2 compare output Out2 7 PM_TB0CCR3A TB0 CCR3 capture input CCI3A TB0 CCR3 compare output Out3 8 PM_TB0CCR4A TB0 CCR4 capture input CCI4A TB0 CCR4 compare output Out4 9 PM_TB0CCR5A TB0 CCR5 capture input CCI5A TB0 CCR5 compare output Out5 10 PM_TB0CCR6A TB0 CCR6 capture input CCI6A TB0 CCR6 compare output Out6 3 Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 55 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com Table 6-7. Port Mapping Mnemonics and Functions (continued) VALUE PxMAPy MNEMONIC 11 12 13 14 15 16 OUTPUT PIN FUNCTION USCI_A1 UART RXD (Direction controlled by USCI – input) PM_UCA1SOMI USCI_A1 SPI slave out master in (direction controlled by USCI) PM_UCA1TXD USCI_A1 UART TXD (Direction controlled by USCI – output) PM_UCA1SIMO USCI_A1 SPI slave in master out (direction controlled by USCI) PM_UCA1CLK USCI_A1 clock input/output (direction controlled by USCI) PM_UCB1STE USCI_B1 SPI slave transmit enable (direction controlled by USCI) PM_UCB1SOMI USCI_B1 SPI slave out master in (direction controlled by USCI) PM_UCB1SCL USCI_B1 I2C clock (open drain and direction controlled by USCI) PM_UCB1SIMO USCI_B1 SPI slave in master out (direction controlled by USCI) PM_UCB1SDA USCI_B1 I2C data (open drain and direction controlled by USCI) PM_UCB1CLK USCI_B1 clock input/output (direction controlled by USCI) PM_UCA1STE USCI_A1 SPI slave transmit enable (direction controlled by USCI) 17 PM_CBOUT1 None Comparator_B output 18 PM_MCLK None MCLK None RTCCLK output 19 PM_RTCCLK 20 21 22 23 24 25 26–30 31 (0FFh) (1) INPUT PIN FUNCTION PM_UCA1RXD PM_UCA0RXD USCI_A0 UART RXD (Direction controlled by USCI – input) PM_UCA0SOMI USCI_A0 SPI slave out master in (direction controlled by USCI) PM_UCA0TXD USCI_A0 UART TXD (Direction controlled by USCI – output) PM_UCA0SIMO USCI_A0 SPI slave in master out (direction controlled by USCI) PM_UCA0CLK USCI_A0 clock input/output (direction controlled by USCI) PM_UCB0STE USCI_B0 SPI slave transmit enable (direction controlled by USCI) PM_UCB0SOMI USCI_B0 SPI slave out master in (direction controlled by USCI) PM_UCB0SCL USCI_B0 I2C clock (open drain and direction controlled by USCI) PM_UCB0SIMO USCI_B0 SPI slave in master out (direction controlled by USCI) PM_UCB0SDA USCI_B0 I2C data (open drain and direction controlled by USCI) PM_UCB0CLK USCI_B0 clock input/output (direction controlled by USCI) PM_UCA0STE USCI_A0 SPI slave transmit enable (direction controlled by USCI) Reserved (1) None DVSS Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents when applying analog signals. PM_ANALOG The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide, and the upper bits are ignored, which results in a read value of 31. Table 6-8. Default Mapping PIN 56 PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION P4.0/P4MAP0 PM_UCB1STE/PM_UCA1CLK USCI_B1 SPI slave transmit enable (direction controlled by USCI) USCI_A1 clock input/output (direction controlled by USCI) P4.1/P4MAP1 PM_UCB1SIMO/PM_UCB1SDA USCI_B1 SPI slave in master out (direction controlled by USCI) USCI_B1 I2C data (open drain and direction controlled by USCI) P4.2/P4MAP2 PM_UCB1SOMI/PM_UCB1SCL USCI_B1 SPI slave out master in (direction controlled by USCI) USCI_B1 I2C clock (open drain and direction controlled by USCI) P4.3/P4MAP3 PM_UCB1CLK/PM_UCA1STE USCI_A1 SPI slave transmit enable (direction controlled by USCI) USCI_B1 clock input/output (direction controlled by USCI) P4.4/P4MAP4 PM_UCA1TXD/PM_UCA1SIMO USCI_A1 UART TXD (Direction controlled by USCI – output) USCI_A1 SPI slave in master out (direction controlled by USCI) P4.5/P4MAP5 PM_UCA1RXD/PM_UCA1SOMI USCI_A1 UART RXD (Direction controlled by USCI – input) USCI_A1 SPI slave out master in (direction controlled by USCI) P4.6/P4MAP6 PM_NONE None DVSS P4.7/P4MAP7 PM_NONE None DVSS Detailed Description Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com 6.9.3 SLAS645L – JULY 2009 – REVISED MAY 2020 Oscillator and System Clock (Link to User's Guide) The clock system is supported by the Unified Clock System (UCS) module that includes support for a 32kHz watch crystal oscillator (XT1 LF mode; XT1 HF mode is not supported), an internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), an integrated internal digitally controlled oscillator (DCO), and a high-frequency crystal oscillator (XT2). The UCS module is designed to meet the requirements of both low system cost and low power consumption. The UCS module features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the selected FLL reference frequency. The internal DCO provides a fast turnon clock source and stabilizes in less than 5 µs. The UCS module provides the following clock signals: • Auxiliary clock (ACLK), sourced from the XT1, XT2, VLO, REFO, or DCO. • Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made available to ACLK. • Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by same sources made available to ACLK. • ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32. 6.9.4 Power-Management Module (PMM) (Link to User's Guide) The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor (SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is implemented to provide the proper internal reset signal to the device during poweron and power-off. The SVS and SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not automatically reset). SVS and SVM circuitry is available on the primary supply and core supply. 6.9.5 Hardware Multiplier (MPY) (Link to User's Guide) The multiplication operation is supported by a dedicated peripheral module. The module performs operations with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication as well as signed and unsigned multiply-and-accumulate operations. 6.9.6 Real-Time Clock (RTC_A) (Link to User's Guide) The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated real-time clock (RTC) (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit timers that can be cascaded to form a 16-bit timer or counter. Both timers can be read and written by software. Calendar mode integrates an internal calendar that compensates for months with less than 31 days and includes leap year correction. The RTC_A also supports flexible alarm functions and offsetcalibration hardware. 6.9.7 Watchdog Timer (WDT_A) (Link to User's Guide) The primary function of the WDT_A module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 57 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 6.9.8 www.ti.com System Module (SYS) (Link to User's Guide) The SYS module handles many of the system functions within the device. These include power on reset and power up clear handling, NMI source selection and management, reset interrupt vector generators, bootloader entry mechanisms, and configuration management (device descriptors). It also includes a data exchange mechanism through JTAG called a JTAG mailbox that can be used in the application. Table 6-9 lists the SYS module interrupt vector registers. Table 6-9. System Module Interrupt Vector Registers INTERRUPT VECTOR REGISTER SYSRSTIV, System Reset SYSSNIV, System NMI SYSUNIV, User NMI 58 Detailed Description ADDRESS 019Eh 019Ch 019Ah INTERRUPT EVENT VALUE No interrupt pending 00h Brownout (BOR) 02h RST/NMI (POR) 04h PMMSWBOR (BOR) 06h Wake up from LPMx.5 08h Security violation (BOR) 0Ah SVSL (POR) 0Ch SVSH (POR) 0Eh SVML_OVP (POR) 10h SVMH_OVP (POR) 12h PMMSWPOR (POR) 14h WDT time-out (PUC) 16h WDT password violation (PUC) 18h KEYV flash password violation (PUC) 1Ah Reserved 1Ch Peripheral area fetch (PUC) 1Eh PMM password violation (PUC) 20h Reserved 22h to 3Eh No interrupt pending 00h SVMLIFG 02h SVMHIFG 04h SVSMLDLYIFG 06h SVSMHDLYIFG 08h VMAIFG 0Ah JMBINIFG 0Ch JMBOUTIFG 0Eh SVMLVLRIFG 10h SVMHVLRIFG 12h Reserved 14h to 1Eh No interrupt pending 00h NMIIFG 02h OFIFG 04h ACCVIFG 06h Reserved 08h Reserved 0Ah to 1Eh PRIORITY Highest Lowest Highest Lowest Highest Lowest Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com 6.9.9 SLAS645L – JULY 2009 – REVISED MAY 2020 DMA Controller (Link to User's Guide) The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC10_A conversion register to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or from a peripheral. Table 6-10 lists the DMA trigger assignments, which are also used by the USB timestamp generator. Table 6-10. DMA Trigger Assignments (1) TRIGGER (1) (2) CHANNEL 0 1 2 0 DMAREQ DMAREQ DMAREQ 1 TA0CCR0 CCIFG TA0CCR0 CCIFG TA0CCR0 CCIFG 2 TA0CCR2 CCIFG TA0CCR2 CCIFG TA0CCR2 CCIFG 3 TA1CCR0 CCIFG TA1CCR0 CCIFG TA1CCR0 CCIFG 4 TA1CCR2 CCIFG TA1CCR2 CCIFG TA1CCR2 CCIFG 5 TA2CCR0 CCIFG TA2CCR0 CCIFG TA2CCR0 CCIFG 6 TA2CCR2 CCIFG TA2CCR2 CCIFG TA2CCR2 CCIFG 7 TB0CCR0 CCIFG TB0CCR0 CCIFG TB0CCR0 CCIFG 8 TB0CCR2 CCIFG TB0CCR2 CCIFG TB0CCR2 CCIFG 9 Reserved Reserved Reserved 10 Reserved Reserved Reserved 11 Reserved Reserved Reserved 12 Reserved Reserved Reserved 13 Reserved Reserved Reserved 14 Reserved Reserved Reserved 15 Reserved Reserved Reserved 16 UCA0RXIFG UCA0RXIFG UCA0RXIFG 17 UCA0TXIFG UCA0TXIFG UCA0TXIFG 18 UCB0RXIFG UCB0RXIFG UCB0RXIFG 19 UCB0TXIFG UCB0TXIFG UCB0TXIFG 20 UCA1RXIFG UCA1RXIFG UCA1RXIFG 21 UCA1TXIFG UCA1TXIFG UCA1TXIFG 22 UCB1RXIFG UCB1RXIFG UCB1RXIFG 23 UCB1TXIFG UCB1TXIFG UCB1TXIFG 24 ADC10IFG0 (2) ADC10IFG0 (2) ADC10IFG0 (2) 25 Reserved Reserved Reserved 26 Reserved Reserved Reserved 27 USB FNRXD USB FNRXD USB FNRXD 28 USB ready USB ready USB ready 29 MPY ready MPY ready MPY ready 30 DMA2IFG DMA0IFG DMA1IFG 31 DMAE0 DMAE0 DMAE0 If a reserved trigger source is selected, no Trigger1 is generated. Only on devices with ADC. Reserved on devices without ADC. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 59 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com 6.9.10 Universal Serial Communication Interface (USCI) (Links to User's Guide: UART Mode, SPI Mode, I2C Mode) The USCI modules are used for serial data communication. The USCI module supports synchronous communication protocols such as SPI (3- or 4-pin) and I2C, and asynchronous communication protocols such as UART, enhanced UART with automatic baud-rate detection, and IrDA. Each USCI module contains two portions, A and B. The USCI_An module provides support for SPI (3- or 4-pin), UART, enhanced UART, or IrDA. The USCI_Bn module provides support for SPI (3- or 4-pin) or I2C. The MSP430F55xx series includes two complete USCI modules (n = 0, 1). 6.9.11 TA0 (Link to User's Guide) TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. TA0 can support multiple capture/compares, PWM outputs, and interval timing (see Table 6-11). TA0 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 6-11. TA0 Signal Connections INPUT PIN NUMBER RGC, ZXH, ZQE RGZ, PT DEVICE INPUT SIGNAL MODULE INPUT SIGNAL 18, H2-P1.0 14-P1.0 TA0CLK TACLK ACLK (internal) ACLK SMCLK (internal) SMCLK 18, H2-P1.0 14-P1.0 TA0CLK TACLK 19, H3-P1.1 15-P1.1 TA0.0 CCI0A DVSS CCI0B DVSS GND 20, J3-P1.2 21, G4-P1.3 22, H4-P1.4 23, J4-P1.5 16-P1.2 17-P1.3 18-P1.4 19-P1.5 (1) Only on devices with ADC. 60 Detailed Description MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL Timer NA NA CCR0 TA0 OUTPUT PIN NUMBER RGC, ZXH, ZQE RGZ, PT 19, H3-P1.1 15-P1.1 TA0.0 DVCC VCC TA0.1 CCI1A 20, J3-P1.2 16-P1.2 CBOUT (internal) CCI1B ADC10 (internal) (1) ADC10SHSx = {1} ADC10 (internal) (1) ADC10SHSx = {1} DVSS GND 21, G4-P1.3 17-P1.3 22, H4-P1.4 18-P1.4 23, J4-P1.5 19-P1.5 DVCC VCC TA0.2 CCI2A ACLK (internal) CCI2B DVSS GND DVCC VCC TA0.3 CCI3A DVSS CCI3B DVSS GND DVCC VCC TA0.4 CCI4A DVSS CCI4B DVSS GND DVCC VCC CCR1 CCR2 CCR3 CCR4 TA1 TA2 TA3 TA4 TA0.1 TA0.2 TA0.3 TA0.4 Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 6.9.12 TA1 (Link to User's Guide) TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA1 can support multiple capture/compares, PWM outputs, and interval timing (see Table 6-12). TA1 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 6-12. TA1 Signal Connections INPUT PIN NUMBER RGC, ZXH, ZQE 24, G5-P1.6 RGZ, PT DEVICE INPUT SIGNAL MODULE INPUT SIGNAL 20-P1.6 TA1CLK TACLK ACLK (internal) ACLK SMCLK (internal) SMCLK 24, G5-P1.6 20-P1.6 TA1CLK TACLK 25, H5-P1.7 21-P1.7 TA1.0 CCI0A DVSS CCI0B DVSS GND DVCC VCC 26, J5-P2.0 27, G6-P2.1 22-P2.0 TA1.1 CCI1A CBOUT (internal) CCI1B DVSS GND DVCC VCC TA1.2 CCI2A ACLK (internal) CCI2B DVSS GND DVCC VCC MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL Timer NA NA CCR0 CCR1 TA0 TA1 OUTPUT PIN NUMBER RGC, ZXH, ZQE RGZ, PT 25, H5-P1.7 21-P1.7 26, J5-P2.0 22-P2.0 TA1.0 TA1.1 27, G6-P2.1 CCR2 TA2 TA1.2 Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 61 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com 6.9.13 TA2 (Link to User's Guide) TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA2 can support multiple capture/compares, PWM outputs, and interval timing (see Table 6-13). TA2 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 6-13. TA2 Signal Connections INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT SIGNAL TA2CLK TACLK ACLK (internal) ACLK SMCLK (internal) SMCLK 28, J6-P2.2 TA2CLK TACLK 29, H6-P2.3 TA2.0 CCI0A DVSS CCI0B DVSS GND DVCC VCC RGC, ZXH, ZQE RGZ, PT 28, J6-P2.2 30, J7-P2.4 31, J8-P2.5 62 Detailed Description TA2.1 CCI1A CBOUT (internal) CCI1B DVSS GND DVCC VCC TA2.2 CCI2A ACLK (internal) CCI2B DVSS GND DVCC VCC MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL Timer NA NA OUTPUT PIN NUMBER RGC, ZXH, ZQE RGZ, PT 29, H6-P2.3 CCR0 TA0 TA2.0 30, J7-P2.4 CCR1 TA1 TA2.1 31, J8-P2.5 CCR2 TA2 TA2.2 Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 6.9.14 TB0 (Link to User's Guide) TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. TB0 can support multiple capture/compares, PWM outputs, and interval timing (see Table 6-14). TB0 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 6-14. TB0 Signal Connections INPUT PIN NUMBER RGC, ZXH, ZQE (1) (1) (2) RGZ, PT (1) DEVICE INPUT SIGNAL MODULE INPUT SIGNAL TB0CLK TBCLK ACLK (internal) ACLK SMCLK (internal) SMCLK TB0CLK TBCLK TB0.0 CCI0A TB0.0 CCI0B DVSS GND DVCC VCC TB0.1 CCI1A CBOUT (internal) CCI1B DVSS GND DVCC VCC TB0.2 CCI2A TB0.2 CCI2B DVSS GND DVCC VCC TB0.3 CCI3A TB0.3 CCI3B DVSS GND DVCC VCC TB0.4 CCI4A TB0.4 CCI4B DVSS GND DVCC VCC TB0.5 CCI5A TB0.5 CCI5B DVSS GND DVCC VCC TB0.6 CCI6A ACLK (internal) CCI6B DVSS GND DVCC VCC MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL Timer NA NA CCR0 TB0 TB0.0 CCR1 TB1 TB0.1 CCR2 TB2 TB0.2 CCR3 TB3 TB0.3 CCR4 TB4 TB0.4 CCR5 TB5 TB0.5 CCR6 TB6 TB0.6 OUTPUT PIN NUMBER RGC, ZXH, ZQE (1) RGZ, PT (1) ADC10 (internal) (2) ADC10SHSx = {2} ADC10 (internal) (2) ADC10SHSx = {2} ADC10 (internal) ADC10SHSx = {3} ADC10 (internal) ADC10SHSx = {3} Timer functions selectable through the port mapping controller. Only on devices with ADC. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 63 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com 6.9.15 Comparator_B (Link to User's Guide) The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions, battery voltage supervision, and monitoring of external analog signals. 6.9.16 ADC10_A (Link to User's Guide) The ADC10_A module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core, sample select control, reference generator, and a conversion result buffer. A window comparator with lower and upper limits allows CPU-independent result monitoring with three window comparator interrupt flags. 6.9.17 CRC16 (Link to User's Guide) The CRC16 module produces a signature based on a sequence of entered data values and can be used for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard. 6.9.18 Reference (REF) Voltage Reference (Link to User's Guide) The REF module is responsible for generation of all critical reference voltages that can be used by the various analog peripherals in the device. 6.9.19 Universal Serial Bus (USB) (Link to User's Guide) The USB module is a fully integrated USB interface that is compliant with the USB 2.0 specification. The module supports full-speed operation of control, interrupt, and bulk transfers. The module includes an integrated LDO, PHY, and PLL. The PLL is highly flexible and supports a wide range of input clock frequencies. USB RAM, when not used for USB communication, can be used by the system. 6.9.20 Embedded Emulation Module (EEM) (S Version) (Link to User's Guide) The EEM supports real-time in-system debugging. The S version of the EEM has the following features: • Three hardware triggers or breakpoints on memory access • One hardware trigger or breakpoint on CPU register write access • Up to four hardware triggers can be combined to form complex triggers or breakpoints • One cycle counter • Clock control on module level 64 Detailed Description Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 6.10 Peripheral File Map Table 6-15 lists the base address for the registers of all supported peripherals. Table 6-15. Peripherals MODULE NAME BASE ADDRESS OFFSET ADDRESS RANGE Special Functions (see Table 6-16) 0100h 000h–01Fh PMM (see Table 6-17) 0120h 000h–010h Flash Control (see Table 6-18) 0140h 000h–00Fh CRC16 (see Table 6-19) 0150h 000h–007h RAM Control (see Table 6-20) 0158h 000h–001h Watchdog (see Table 6-21) 015Ch 000h–001h UCS (see Table 6-22) 0160h 000h–01Fh SYS (see Table 6-23) 0180h 000h–01Fh Shared Reference (see Table 6-24) 01B0h 000h–001h Port Mapping Control (see Table 6-25) 01C0h 000h–002h Port Mapping Port P4 (see Table 6-25) 01E0h 000h–007h Port P1, P2 (see Table 6-26) 0200h 000h–01Fh Port P3, P4 (see Table 6-27) 0220h 000h–00Bh Port P5, P6 (see Table 6-28) 0240h 000h–00Bh Port PJ (see Table 6-29) 0320h 000h–01Fh TA0 (see Table 6-30) 0340h 000h–02Eh TA1 (see Table 6-31) 0380h 000h–02Eh TB0 (see Table 6-32) 03C0h 000h–02Eh TA2 (see Table 6-33) 0400h 000h–02Eh Real-Time Clock (RTC_A) (see Table 6-34) 04A0h 000h–01Bh 32-Bit Hardware Multiplier (see Table 6-35) 04C0h 000h–02Fh DMA General Control (see Table 6-36) 0500h 000h–00Fh DMA Channel 0 (see Table 6-36) 0510h 000h–00Ah DMA Channel 1 (see Table 6-36) 0520h 000h–00Ah DMA Channel 2 (see Table 6-36) 0530h 000h–00Ah USCI_A0 (see Table 6-37) 05C0h 000h–01Fh USCI_B0 (see Table 6-38) 05E0h 000h–01Fh USCI_A1 (see Table 6-39) 0600h 000h–01Fh USCI_B1 (see Table 6-40) 0620h 000h–01Fh ADC10_A (see Table 6-41) 0740h 000h–01Fh Comparator_B (see Table 6-42) 08C0h 000h–00Fh USB configuration (see Table 6-43) 0900h 000h–014h USB control (see Table 6-44) 0920h 000h–01Fh Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 65 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com Table 6-16. Special Function Registers (Base Address: 0100h) REGISTER DESCRIPTION REGISTER OFFSET SFR interrupt enable SFRIE1 00h SFR interrupt flag SFRIFG1 02h SFR reset pin control SFRRPCR 04h Table 6-17. PMM Registers (Base Address: 0120h) REGISTER DESCRIPTION REGISTER OFFSET PMM control 0 PMMCTL0 00h PMM control 1 PMMCTL1 02h SVS high-side control SVSMHCTL 04h SVS low-side control SVSMLCTL 06h PMM interrupt flags PMMIFG 0Ch PMM interrupt enable PMMIE 0Eh PMM power mode 5 control PM5CTL0 10h Table 6-18. Flash Control Registers (Base Address: 0140h) REGISTER DESCRIPTION REGISTER OFFSET Flash control 1 FCTL1 00h Flash control 3 FCTL3 04h Flash control 4 FCTL4 06h Table 6-19. CRC16 Registers (Base Address: 0150h) REGISTER DESCRIPTION REGISTER OFFSET CRC data input CRC16DI 00h CRC data input reverse byte CRCDIRB 02h CRC initialization and result CRCINIRES 04h CRC result reverse byte CRCRESR 06h Table 6-20. RAM Control Registers (Base Address: 0158h) REGISTER DESCRIPTION RAM control 0 REGISTER RCCTL0 OFFSET 00h Table 6-21. Watchdog Registers (Base Address: 015Ch) REGISTER DESCRIPTION Watchdog timer control 66 Detailed Description REGISTER WDTCTL OFFSET 00h Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 Table 6-22. UCS Registers (Base Address: 0160h) REGISTER DESCRIPTION REGISTER OFFSET UCS control 0 UCSCTL0 00h UCS control 1 UCSCTL1 02h UCS control 2 UCSCTL2 04h UCS control 3 UCSCTL3 06h UCS control 4 UCSCTL4 08h UCS control 5 UCSCTL5 0Ah UCS control 6 UCSCTL6 0Ch UCS control 7 UCSCTL7 0Eh UCS control 8 UCSCTL8 10h Table 6-23. SYS Registers (Base Address: 0180h) REGISTER DESCRIPTION REGISTER OFFSET System control SYSCTL 00h Bootloader configuration area SYSBSLC 02h JTAG mailbox control SYSJMBC 06h JTAG mailbox input 0 SYSJMBI0 08h JTAG mailbox input 1 SYSJMBI1 0Ah JTAG mailbox output 0 SYSJMBO0 0Ch JTAG mailbox output 1 SYSJMBO1 0Eh Bus error vector generator SYSBERRIV 18h User NMI vector generator SYSUNIV 1Ah System NMI vector generator SYSSNIV 1Ch Reset vector generator SYSRSTIV 1Eh Table 6-24. Shared Reference Registers (Base Address: 01B0h) REGISTER DESCRIPTION Shared reference control REGISTER REFCTL OFFSET 00h Table 6-25. Port Mapping Registers (Base Address of Port Mapping Control: 01C0h, Port P4: 01E0h) REGISTER DESCRIPTION REGISTER OFFSET Port mapping key/ID PMAPKEYID 00h Port mapping control PMAPCTL 02h Port P4.0 mapping P4MAP0 00h Port P4.1 mapping P4MAP1 01h Port P4.2 mapping P4MAP2 02h Port P4.3 mapping P4MAP3 03h Port P4.4 mapping P4MAP4 04h Port P4.5 mapping P4MAP5 05h Port P4.6 mapping P4MAP6 06h Port P4.7 mapping P4MAP7 07h Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 67 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com Table 6-26. Port P1, P2 Registers (Base Address: 0200h) REGISTER DESCRIPTION REGISTER OFFSET Port P1 input P1IN 00h Port P1 output P1OUT 02h Port P1 direction P1DIR 04h Port P1 resistor enable P1REN 06h Port P1 drive strength P1DS 08h Port P1 selection P1SEL 0Ah Port P1 interrupt vector word P1IV 0Eh Port P1 interrupt edge select P1IES 18h Port P1 interrupt enable P1IE 1Ah Port P1 interrupt flag P1IFG 1Ch Port P2 input P2IN 01h Port P2 output P2OUT 03h Port P2 direction P2DIR 05h Port P2 resistor enable P2REN 07h Port P2 drive strength P2DS 09h Port P2 selection P2SEL 0Bh Port P2 interrupt vector word P2IV 1Eh Port P2 interrupt edge select P2IES 19h Port P2 interrupt enable P2IE 1Bh Port P2 interrupt flag P2IFG 1Dh Table 6-27. Port P3, P4 Registers (Base Address: 0220h) REGISTER DESCRIPTION REGISTER OFFSET Port P3 input P3IN 00h Port P3 output P3OUT 02h Port P3 direction P3DIR 04h Port P3 resistor enable P3REN 06h Port P3 drive strength P3DS 08h Port P3 selection P3SEL 0Ah Port P4 input P4IN 01h Port P4 output P4OUT 03h Port P4 direction P4DIR 05h Port P4 resistor enable P4REN 07h Port P4 drive strength P4DS 09h Port P4 selection P4SEL 0Bh 68 Detailed Description Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 Table 6-28. Port P5, P6 Registers (Base Address: 0240h) REGISTER DESCRIPTION REGISTER OFFSET Port P5 input P5IN 00h Port P5 output P5OUT 02h Port P5 direction P5DIR 04h Port P5 resistor enable P5REN 06h Port P5 drive strength P5DS 08h Port P5 selection P5SEL 0Ah Port P6 input P6IN 01h Port P6 output P6OUT 03h Port P6 direction P6DIR 05h Port P6 resistor enable P6REN 07h Port P6 drive strength P6DS 09h Port P6 selection P6SEL 0Bh Table 6-29. Port J Registers (Base Address: 0320h) REGISTER DESCRIPTION REGISTER OFFSET Port PJ input PJIN 00h Port PJ output PJOUT 02h Port PJ direction PJDIR 04h Port PJ resistor enable PJREN 06h Port PJ drive strength PJDS 08h Table 6-30. TA0 Registers (Base Address: 0340h) REGISTER DESCRIPTION REGISTER OFFSET TA0 control TA0CTL 00h Capture/compare control 0 TA0CCTL0 02h Capture/compare control 1 TA0CCTL1 04h Capture/compare control 2 TA0CCTL2 06h Capture/compare control 3 TA0CCTL3 08h Capture/compare control 4 TA0CCTL4 0Ah TA0 counter TA0R 10h Capture/compare 0 TA0CCR0 12h Capture/compare 1 TA0CCR1 14h Capture/compare 2 TA0CCR2 16h Capture/compare 3 TA0CCR3 18h Capture/compare 4 TA0CCR4 1Ah TA0 expansion 0 TA0EX0 20h TA0 interrupt vector TA0IV 2Eh Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 69 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com Table 6-31. TA1 Registers (Base Address: 0380h) REGISTER DESCRIPTION REGISTER OFFSET TA1 control TA1CTL 00h Capture/compare control 0 TA1CCTL0 02h Capture/compare control 1 TA1CCTL1 04h Capture/compare control 2 TA1CCTL2 06h TA1 counter TA1R 10h Capture/compare 0 TA1CCR0 12h Capture/compare 1 TA1CCR1 14h Capture/compare 2 TA1CCR2 16h TA1 expansion 0 TA1EX0 20h TA1 interrupt vector TA1IV 2Eh Table 6-32. TB0 Registers (Base Address: 03C0h) REGISTER DESCRIPTION REGISTER OFFSET TB0 control TB0CTL 00h Capture/compare control 0 TB0CCTL0 02h Capture/compare control 1 TB0CCTL1 04h Capture/compare control 2 TB0CCTL2 06h Capture/compare control 3 TB0CCTL3 08h Capture/compare control 4 TB0CCTL4 0Ah Capture/compare control 5 TB0CCTL5 0Ch Capture/compare control 6 TB0CCTL6 0Eh TB0 counter TB0R 10h Capture/compare 0 TB0CCR0 12h Capture/compare 1 TB0CCR1 14h Capture/compare 2 TB0CCR2 16h Capture/compare 3 TB0CCR3 18h Capture/compare 4 TB0CCR4 1Ah Capture/compare 5 TB0CCR5 1Ch Capture/compare 6 TB0CCR6 1Eh TB0 expansion 0 TB0EX0 20h TB0 interrupt vector TB0IV 2Eh Table 6-33. TA2 Registers (Base Address: 0400h) REGISTER DESCRIPTION REGISTER OFFSET TA2 control TA2CTL 00h Capture/compare control 0 TA2CCTL0 02h Capture/compare control 1 TA2CCTL1 04h Capture/compare control 2 TA2CCTL2 06h TA2 counter TA2R 10h Capture/compare 0 TA2CCR0 12h Capture/compare 1 TA2CCR1 14h Capture/compare 2 TA2CCR2 16h TA2 expansion 0 TA2EX0 20h TA2 interrupt vector TA2IV 2Eh 70 Detailed Description Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 Table 6-34. Real-Time Clock Registers (Base Address: 04A0h) REGISTER DESCRIPTION REGISTER OFFSET RTC control 0 RTCCTL0 00h RTC control 1 RTCCTL1 01h RTC control 2 RTCCTL2 02h RTC control 3 RTCCTL3 03h RTC prescaler 0 control RTCPS0CTL 08h RTC prescaler 1 control RTCPS1CTL 0Ah RTC prescaler 0 RTCPS0 0Ch RTC prescaler 1 RTCPS1 0Dh RTC interrupt vector word RTCIV 0Eh RTC seconds/counter 1 RTCSEC/RTCNT1 10h RTC minutes/counter 2 RTCMIN/RTCNT2 11h RTC hours/counter 3 RTCHOUR/RTCNT3 12h RTC day of week/counter register 4 RTCDOW/RTCNT4 13h RTC days RTCDAY 14h RTC month RTCMON 15h RTC year low RTCYEARL 16h RTC year high RTCYEARH 17h RTC alarm minutes RTCAMIN 18h RTC alarm hours RTCAHOUR 19h RTC alarm day of week RTCADOW 1Ah RTC alarm days RTCADAY 1Bh Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 71 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com Table 6-35. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h) REGISTER DESCRIPTION REGISTER OFFSET 16-bit operand 1 – multiply MPY 00h 16-bit operand 1 – signed multiply MPYS 02h 16-bit operand 1 – multiply accumulate MAC 04h 16-bit operand 1 – signed multiply accumulate MACS 06h 16-bit operand 2 OP2 08h 16 × 16 result low word RESLO 0Ah 16 × 16 result high word RESHI 0Ch 16 × 16 sum extension register SUMEXT 0Eh 32-bit operand 1 – multiply low word MPY32L 10h 32-bit operand 1 – multiply high word MPY32H 12h 32-bit operand 1 – signed multiply low word MPYS32L 14h 32-bit operand 1 – signed multiply high word MPYS32H 16h 32-bit operand 1 – multiply accumulate low word MAC32L 18h 32-bit operand 1 – multiply accumulate high word MAC32H 1Ah 32-bit operand 1 – signed multiply accumulate low word MACS32L 1Ch 32-bit operand 1 – signed multiply accumulate high word MACS32H 1Eh 32-bit operand 2 – low word OP2L 20h 32-bit operand 2 – high word OP2H 22h 32 × 32 result 0 – least significant word RES0 24h 32 × 32 result 1 RES1 26h 32 × 32 result 2 RES2 28h 32 × 32 result 3 – most significant word RES3 2Ah MPY32 control 0 MPY32CTL0 2Ch 72 Detailed Description Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 Table 6-36. DMA Registers (Base Address DMA General Control: 0500h, DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h) REGISTER DESCRIPTION REGISTER OFFSET DMA channel 0 control DMA0CTL 00h DMA channel 0 source address low DMA0SAL 02h DMA channel 0 source address high DMA0SAH 04h DMA channel 0 destination address low DMA0DAL 06h DMA channel 0 destination address high DMA0DAH 08h DMA channel 0 transfer size DMA0SZ 0Ah DMA channel 1 control DMA1CTL 00h DMA channel 1 source address low DMA1SAL 02h DMA channel 1 source address high DMA1SAH 04h DMA channel 1 destination address low DMA1DAL 06h DMA channel 1 destination address high DMA1DAH 08h DMA channel 1 transfer size DMA1SZ 0Ah DMA channel 2 control DMA2CTL 00h DMA channel 2 source address low DMA2SAL 02h DMA channel 2 source address high DMA2SAH 04h DMA channel 2 destination address low DMA2DAL 06h DMA channel 2 destination address high DMA2DAH 08h DMA channel 2 transfer size DMA2SZ 0Ah DMA module control 0 DMACTL0 00h DMA module control 1 DMACTL1 02h DMA module control 2 DMACTL2 04h DMA module control 3 DMACTL3 06h DMA module control 4 DMACTL4 08h DMA interrupt vector DMAIV 0Ah Table 6-37. USCI_A0 Registers (Base Address: 05C0h) REGISTER DESCRIPTION REGISTER OFFSET USCI control 1 UCA0CTL1 00h USCI control 0 UCA0CTL0 01h USCI baud rate 0 UCA0BR0 06h USCI baud rate 1 UCA0BR1 07h USCI modulation control UCA0MCTL 08h USCI status UCA0STAT 0Ah USCI receive buffer UCA0RXBUF 0Ch USCI transmit buffer UCA0TXBUF 0Eh USCI LIN control UCA0ABCTL 10h USCI IrDA transmit control UCA0IRTCTL 12h USCI IrDA receive control UCA0IRRCTL 13h USCI interrupt enable UCA0IE 1Ch USCI interrupt flags UCA0IFG 1Dh USCI interrupt vector word UCA0IV 1Eh Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 73 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com Table 6-38. USCI_B0 Registers (Base Address: 05E0h) REGISTER DESCRIPTION REGISTER OFFSET USCI synchronous control 1 UCB0CTL1 00h USCI synchronous control 0 UCB0CTL0 01h USCI synchronous bit rate 0 UCB0BR0 06h USCI synchronous bit rate 1 UCB0BR1 07h USCI synchronous status UCB0STAT 0Ah USCI synchronous receive buffer UCB0RXBUF 0Ch USCI synchronous transmit buffer UCB0TXBUF 0Eh USCI I2C own address UCB0I2COA 10h USCI I2C slave address UCB0I2CSA 12h USCI interrupt enable UCB0IE 1Ch USCI interrupt flags UCB0IFG 1Dh USCI interrupt vector word UCB0IV 1Eh Table 6-39. USCI_A1 Registers (Base Address: 0600h) REGISTER DESCRIPTION REGISTER OFFSET USCI control 1 UCA1CTL1 00h USCI control 0 UCA1CTL0 01h USCI baud rate 0 UCA1BR0 06h USCI baud rate 1 UCA1BR1 07h USCI modulation control UCA1MCTL 08h USCI status UCA1STAT 0Ah USCI receive buffer UCA1RXBUF 0Ch USCI transmit buffer UCA1TXBUF 0Eh USCI LIN control UCA1ABCTL 10h USCI IrDA transmit control UCA1IRTCTL 12h USCI IrDA receive control UCA1IRRCTL 13h USCI interrupt enable UCA1IE 1Ch USCI interrupt flags UCA1IFG 1Dh USCI interrupt vector word UCA1IV 1Eh Table 6-40. USCI_B1 Registers (Base Address: 0620h) REGISTER DESCRIPTION REGISTER OFFSET USCI synchronous control 1 UCB1CTL1 00h USCI synchronous control 0 UCB1CTL0 01h USCI synchronous bit rate 0 UCB1BR0 06h USCI synchronous bit rate 1 UCB1BR1 07h USCI synchronous status UCB1STAT 0Ah USCI synchronous receive buffer UCB1RXBUF 0Ch USCI synchronous transmit buffer UCB1TXBUF 0Eh USCI I2C own address UCB1I2COA 10h USCI I2C slave address UCB1I2CSA 12h USCI interrupt enable UCB1IE 1Ch USCI interrupt flags UCB1IFG 1Dh USCI interrupt vector word UCB1IV 1Eh 74 Detailed Description Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 Table 6-41. ADC10_A Registers (Base Address: 0740h) REGISTER DESCRIPTION REGISTER OFFSET ADC10_A control 0 ADC10CTL0 00h ADC10_A control 1 ADC10CTL1 02h ADC10_A control 2 ADC10CTL2 04h ADC10_A window comparator low threshold ADC10LO 06h ADC10_A window comparator high threshold ADC10HI 08h ADC10_A memory control 0 ADC10MCTL0 0Ah ADC10_A conversion memory ADC10MEM0 12h ADC10_A interrupt enable ADC10IE 1Ah ADC10_A interrupt flags ADC10IGH 1Ch ADC10_A interrupt vector word ADC10IV 1Eh Table 6-42. Comparator_B Registers (Base Address: 08C0h) REGISTER DESCRIPTION REGISTER OFFSET Comp_B control 0 CBCTL0 00h Comp_B control 1 CBCTL1 02h Comp_B control 2 CBCTL2 04h Comp_B control 3 CBCTL3 06h Comp_B interrupt CBINT 0Ch Comp_B interrupt vector word CBIV 0Eh Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 75 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com Table 6-43. USB Configuration Registers (Base Address: 0900h) REGISTER DESCRIPTION REGISTER OFFSET USB key/ID USBKEYPID 00h USB module configuration USBCNF 02h USB PHY control USBPHYCTL 04h USB power control USBPWRCTL 08h USB PLL control USBPLLCTL 10h USB PLL divider USBPLLDIVB 12h USB PLL interrupts USBPLLIR 14h Table 6-44. USB Control Registers (Base Address: 0920h) REGISTER DESCRIPTION REGISTER OFFSET Input endpoint_0 configuration USBIEPCNF_0 00h Input endpoint_0 byte count USBIEPCNT_0 01h Output endpoint_0 configuration USBOEPCNF_0 02h Output endpoint_0 byte count USBOEPCNT_0 03h Input endpoint interrupt enables USBIEPIE 0Eh Output endpoint interrupt enables USBOEPIE 0Fh Input endpoint interrupt flags USBIEPIFG 10h Output endpoint interrupt flags USBOEPIFG 11h USB interrupt vector USBIV 12h USB maintenance USBMAINT 16h Time stamp USBTSREG 18h USB frame number USBFN 1Ah USB control USBCTL 1Ch USB interrupt enables USBIE 1Dh USB interrupt flags USBIFG 1Eh Function address USBFUNADR 1Fh 76 Detailed Description Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 6.11 Input/Output Diagrams 6.11.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger Figure 6-2 shows the port diagram. Table 6-45 summarizes the selection of the pin functions. Pad Logic P1REN.x P1DIR.x 0 From module 1 P1OUT.x 0 From module 1 DVSS 0 DVCC 1 Direction 0: Input 1: Output P1DS.x 0: Low drive 1: High drive P1SEL.x P1IN.x EN To module 1 P1.0/TA0CLK/ACLK P1.1/TA0.0 P1.2/TA0.1 P1.3/TA0.2 P1.4/TA0.3 P1.5/TA0.4 P1.6/TA1CLK/CBOUT P1.7/TA1.0 D P1IE.x EN P1IRQ.x Q P1IFG.x P1SEL.x P1IES.x Set Interrupt Edge Select Figure 6-2. Port P1 (P1.0 to P1.7) Diagram Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 77 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com Table 6-45. Port P1 (P1.0 to P1.7) Pin Functions PIN NAME (P1.x) P1.0/TA0CLK/ACLK x 0 FUNCTION P1DIR.x P1SEL.x P1.0 (I/O) I: 0; O: 1 0 TA0CLK 0 1 ACLK P1.1 (I/O) P1.1/TA0.0 1 TA0.CCI0A TA0.0 P1.2 (I/O) P1.2/TA0.1 2 TA0.CCI1A TA0.1 3 4 P1.6/TA1CLK/CBOUT 5 6 78 Detailed Description 7 1 1 1 I: 0; O: 1 0 0 1 0 TA0.CCI2A 0 1 TA0.2 1 1 I: 0; O: 1 0 TA0.CCI3A 0 1 TA0.3 1 1 I: 0; O: 1 0 TA0.CCI4A 0 1 TA0.4 1 1 P1.6 (I/O) I: 0; O: 1 0 TA1CLK 0 1 CBOUT comparator B 1 1 I: 0; O: 1 0 TA1.CCI0A 0 1 TA1.0 1 1 P1.7 (I/O) P1.7/TA1.0 0 0 1 P1.5 (I/O) P1.5/TA0.4 1 1 P1.4 (I/O) P1.4/TA0.3 1 I: 0; O: 1 I: 0; O: 1 P1.3 (I/O) P1.3/TA0.2 CONTROL BITS OR SIGNALS Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 6.11.2 Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger Figure 6-3 shows the port diagram. Table 6-46 summarizes the selection of the pin functions. Pad Logic P2REN.x P2DIR.x 0 From module 1 P2OUT.x 0 From module 1 DVSS 0 DVCC 1 Direction 0: Input 1: Output P2DS.x 0: Low drive 1: High drive P2SEL.x P2IN.x EN To module 1 P2.0/TA1.1 P2.1/TA1.2 P2.2/TA2CLK/SMCLK P2.3/TA2.0 P2.4/TA2.1 P2.5/TA2.2 P2.6/RTCCLK/DMAE0 P2.7/UB0STE/UCA0CLK D P2IE.x EN To module Q P2IFG.x P2SEL.x P2IES.x Set Interrupt Edge Select Figure 6-3. Port P2 (P2.0 to P2.7) Diagram Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 79 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com Table 6-46. Port P2 (P2.0 to P2.7) Pin Functions PIN NAME (P2.x) x FUNCTION P2.0 (I/O) P2.0/TA1.1 0 TA1.CCI1A TA1.1 P2.1 (I/O) P2.1/TA1.2 1 TA1.CCI2A TA1.2 P2.2/TA2CLK/SMCLK 2 4 5 P2.7/UCB0STE/UCA0CLK (1) (2) (3) 80 6 7 1 1 I: 0; O: 1 0 0 1 0 TA2CLK 0 1 1 1 I: 0; O: 1 0 TA2.CCI0A 0 1 TA2.0 1 1 I: 0; O: 1 0 TA2.CCI1A 0 1 TA2.1 1 1 I: 0; O: 1 0 TA2.CCI2A 0 1 TA2.2 1 1 P2.6 (I/O) P2.6/RTCCLK/DMAE0 1 1 P2.5 (I/O) P2.5/TA2.2 0 0 1 P2.4 (I/O) P2.4/TA2.1 P2SEL.x I: 0; O: 1 P2.3 (I/O) 3 P2DIR.x I: 0; O: 1 P2.2 (I/O) SMCLK P2.3/TA2.0 CONTROL BITS OR SIGNALS (1) I: 0; O: 1 0 DMAE0 0 1 RTCCLK 1 1 P2.7 (I/O) I: 0; O: 1 0 X 1 UCB0STE/UCA0CLK (2) (3) X = Don't care The pin direction is controlled by the USCI module. UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI_B0 is forced to 3-wire SPI mode if 4-wire SPI mode is selected. Detailed Description Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 6.11.3 Port P3 (P3.0 to P3.4) Input/Output With Schmitt Trigger Figure 6-4 shows the port diagram. Table 6-47 summarizes the selection of the pin functions. Pad Logic P3REN.x P3DIR.x 0 From module 1 P3OUT.x 0 From module 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P3DS.x 0: Low drive 1: High drive P3SEL.x P3IN.x P3.0/UCB0SIMO/UCB0SDA P3.1/UCB0SOMI/UCB0SCL P3.2/UCB0CLK/UCA0STE P3.3/UCA0TXD/UCA0SIMO P3.4/UCA0RXD/UCA0SOMI EN To module D Figure 6-4. Port P3 (P3.0 to P3.7) Diagram Table 6-47. Port P3 (P3.0 to P3.7) Pin Functions PIN NAME (P3.x) P3.0/UCB0SIMO/UCB0SDA P3.1/UCB0SOMI/UCB0SCL P3.2/UCB0CLK/UCA0STE x 0 1 2 P3.3/UCA0TXD/UCA0SIMO 3 P3.4/UCA0RXD/UCA0SOMI 4 (1) (2) (3) (4) FUNCTION P3.0 (I/O) UCB0SIMO/UCB0SDA (2) (3) P3.1 (I/O) UCB0SOMI/UCB0SCL (2) (3) P3.2 (I/O) UCB0CLK/UCA0STE (2) (4) P3.3 (I/O) UCA0TXD/UCA0SIMO (2) P3.4 (I/O) UCA0RXD/UCA0SOMI (2) CONTROL BITS OR SIGNALS (1) P3DIR.x P3SEL.x I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 X = Don't care The pin direction is controlled by the USCI module. If the I2C functionality is selected, the output drives only the logical 0 to VSS level. UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output, USCI_A0 is forced to 3-wire SPI mode if 4-wire SPI mode is selected. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 81 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com 6.11.4 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger Figure 6-5 shows the port diagram. Table 6-48 summarizes the selection of the pin functions. Pad Logic P4REN.x P4DIR.x 0 From Port Mapping Control 1 P4OUT.x 0 From Port Mapping Control 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P4.0/P4MAP0 P4.1/P4MAP1 P4.2/P4MAP2 P4.3/P4MAP3 P4.4/P4MAP4 P4.5/P4MAP5 P4.6/P4MAP6 P4.7/P4MAP7 P4DS.x 0: Low drive 1: High drive P4SEL.x P4IN.x EN D To Port Mapping Control Figure 6-5. Port P4 (P4.0 to P4.7) Diagram Table 6-48. Port P4 (P4.0 to P4.7) Pin Functions PIN NAME (P4.x) x P4.0/P4MAP0 0 P4.1/P4MAP1 1 P4.2/P4MAP2 2 P4.3/P4MAP3 3 P4.4/P4MAP4 4 P4.5/P4MAP5 5 P4.6/P4MAP6 6 P4.7/P4MAP7 (1) 82 7 FUNCTION P4.0 (I/O) Mapped secondary digital function P4.1 (I/O) Mapped secondary digital function P4.2 (I/O) Mapped secondary digital function P4.3 (I/O) Mapped secondary digital function P4.4 (I/O) Mapped secondary digital function P4.5 (I/O) Mapped secondary digital function P4.6 (I/O) Mapped secondary digital function P4.7 (I/O) Mapped secondary digital function CONTROL BITS OR SIGNALS P4DIR.x (1) P4SEL.x I: 0; O: 1 0 X X 1 ≤ 30 I: 0; O: 1 0 X ≤ 30 P4MAPx X 1 I: 0; O: 1 0 X X 1 ≤ 30 I: 0; O: 1 0 X X 1 ≤ 30 I: 0; O: 1 0 X X 1 ≤ 30 I: 0; O: 1 0 X X 1 ≤ 30 I: 0; O: 1 0 X ≤ 30 X 1 I: 0; O: 1 0 X X 1 ≤ 30 The direction of some mapped secondary functions are controlled directly by the module. See Table 6-7 for specific direction control information of mapped secondary functions. Detailed Description Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 6.11.5 Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger Figure 6-6 shows the port diagram. Table 6-49 summarizes the selection of the pin functions. Pad Logic To or from Reference to ADC10 INCHx = x P5REN.x P5DIR.x DVSS 0 DVCC 1 1 0 1 P5OUT.x 0 From module 1 P5.0/(A8/VeREF+) P5.1/(A9/VeREF–) P5DS.x 0: Low drive 1: High drive P5SEL.x P5IN.x Bus Keeper EN To module D Figure 6-6. Port P5 (P5.0 and P5.1) Diagram Table 6-49. Port P5 (P5.0 and P5.1) Pin Functions PIN NAME (P5.x) P5.0/A8/VeREF+ (2) P5.1/A9/VeREF– (5) (1) (2) (3) (4) (5) (6) x 0 1 FUNCTION P5.0 (I/O) (3) A8/VeREF+ (4) P5.1 (I/O) (3) A9/VeREF– (6) CONTROL BITS OR SIGNALS (1) P5DIR.x P5SEL.x I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 X = Don't care VeREF+ available on devices with ADC10_A. Default condition Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. An external voltage can be applied to VeREF+ and used as the reference for the ADC10_A when available. VeREF- available on devices with ADC10_A. Setting the P5SEL.1 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. An external voltage can be applied to VeREF- and used as the reference for the ADC10_A when available. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 83 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com 6.11.6 Port P5 (P5.2) Input/Output With Schmitt Trigger Figure 6-7 shows the port diagram. Table 6-50 summarizes the selection of the pin functions. Pad Logic To XT2 P5REN.2 P5DIR.2 DVSS 0 DVCC 1 1 0 1 P5OUT.2 0 Module X OUT 1 P5DS.2 0: Low drive 1: High drive P5SEL.2 P5.2/XT2IN P5IN.2 EN Module X IN Bus Keeper D Figure 6-7. Port P5 (P5.2) Diagram 84 Detailed Description Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 6.11.7 Port P5 (P5.3) Input/Output With Schmitt Trigger Figure 6-8 shows the port diagram. Table 6-50 summarizes the selection of the pin functions. Pad Logic To XT2 P5REN.3 P5DIR.3 DVSS 0 DVCC 1 1 0 1 P5OUT.3 0 Module X OUT 1 P5.3/XT2OUT P5DS.3 0: Low drive 1: High drive P5SEL.2 XT2BYPASS P5SEL.3 P5IN.3 Bus Keeper EN Module X IN D Figure 6-8. Port P5 (P5.3) Diagram Table 6-50. Port P5 (P5.2 and P5.3) Pin Functions PIN NAME (P5.x) x FUNCTION P5.2 (I/O) P5.2/XT2IN 2 XT2IN crystal mode (2) XT2IN bypass mode (2) P5.3 (I/O) P5.3/XT2OUT 3 XT2OUT crystal mode (3) P5.3 (I/O) (1) (2) (3) (3) CONTROL BITS OR SIGNALS (1) P5DIR.x P5SEL.2 P5SEL.3 XT2BYPASS I: 0; O: 1 0 X X X 1 X 0 X 1 X 1 I: 0; O: 1 0 0 X X 1 X 0 X 1 0 1 X = Don't care Setting P5SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P5.2 is configured for crystal mode or bypass mode. Setting P5SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.3 can be used as general-purpose I/O. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 85 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com 6.11.8 Port P5 (P5.4 and P5.5) Input/Output With Schmitt Trigger Figure 6-9 and Figure 6-10 show the port diagrams. Table 6-51 summarizes the selection of the pin functions. Pad Logic to XT1 P5REN.4 P5DIR.4 DVSS 0 DVCC 1 1 0 1 P5OUT.4 0 Module X OUT 1 P5DS.4 0: Low drive 1: High drive P5SEL.4 P5.4/XIN P5IN.4 EN Module X IN Bus Keeper D Figure 6-9. Port P5 (P5.4) Diagram 86 Detailed Description Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 Pad Logic to XT1 P5REN.5 P5DIR.5 0 DVSS 0 DVCC 1 1 1 P5OUT.5 0 Module X OUT 1 P5.5/XOUT P5DS.5 0: Low drive 1: High drive P5SEL.4 XT1BYPASS P5SEL.5 P5IN.5 Bus Keeper EN Module X IN D Figure 6-10. Port P5 (P5.5) Diagram Table 6-51. Port P5 (P5.4 and P5.5) Pin Functions PIN NAME (P7.x) x FUNCTION P5DIR.x P5SEL.4 P5SEL.5 XT1BYPASS I: 0; O: 1 0 X X X 1 X 0 X 1 X 1 I: 0; O: 1 0 0 X XOUT crystal mode (3) X 1 X 0 (3) X 1 0 1 P5.4 (I/O) P5.4/XIN 4 XIN crystal mode (2) XIN bypass mode (2) P5.5 (I/O) P5.5/XOUT 5 P5.5 (I/O) (1) (2) (3) CONTROL BITS OR SIGNALS (1) X = Don't care Setting P5SEL.4 causes the general-purpose I/O to be disabled. Pending the setting of XT1BYPASS, P5.4 is configured for crystal mode or bypass mode. Setting P5SEL.4 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.5 can be used as general-purpose I/O. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 87 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com 6.11.9 Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger Figure 6-11 shows the port diagram. Table 6-52 summarizes the selection of the pin functions. Pad Logic to ADC10 INCHx = x to Comparator_B from Comparator_B CBPD.x P6REN.x P6DIR.x 0 0 From module 1 0 DVCC 1 P6DS.x 0: Low drive 1: High drive P6SEL.x P6IN.x EN To module 1 Direction 0: Input 1: Output 1 P6OUT.x DVSS Bus Keeper P6.0/CB0/(A0) P6.1/CB1/(A1) P6.2/CB2/(A2) P6.3/CB3/(A3) P6.4/CB4/(A4) P6.5/CB5/(A5) P6.6/CB6/(A6) P6.7/CB7/(A7) D Figure 6-11. Port P6 (P6.0 to P6.7) Diagram 88 Detailed Description Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 Table 6-52. Port P6 (P6.0 to P6.7) Pin Functions PIN NAME (P6.x) x FUNCTION P6.0 (I/O) P6.0/CB0/(A0) 0 A0 (only on devices with ADC) CB0 (1) P6.1 (I/O) P6.1/CB1/(A1) 1 A1 (only on devices with ADC) CB1 (1) P6.2 (I/O) P6.2/CB2/(A2) 2 A2 (only on devices with ADC) CB2 (1) 3 4 5 6 (1) X 1 X X I: 0; O: 1 0 0 X 1 X 1 X X I: 0; O: 1 0 0 X 1 X 1 0 X 1 X CB3 (1) X X 1 I: 0; O: 1 0 0 A4 (only on devices with ADC) X 1 X CB4 (1) X X 1 I: 0; O: 1 0 0 A5 (only on devices with ADC) X 1 X CB5 (1) X X 1 I: 0; O: 1 0 0 X 1 X X X 1 I: 0; O: 1 0 0 A6 (only on devices with ADC) P6.7 (I/O) 7 1 A3 (only on devices with ADC) CB6 (1) P6.7/CB7/(A7) 0 X 0 P6.6 (I/O) P6.6/CB6/(A6) CBPDx X P6.5 (I/O) P6.5/CB5/(A5) 0 X P6.4 (I/O) P6.4/CB4/(A4) P6SEL.x I: 0; O: 1 I: 0; O: 1 P6.3 (I/O) P6.3/CB3/(A3) CONTROL BITS OR SIGNALS P6DIR.x A7 (only on devices with ADC) X 1 X CB7 (1) X X 1 Setting the CBPDx bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Selecting the CBx input pin to the comparator multiplexer with the CBx bits automatically disables output driver and input buffer for that pin, regardless of the state of the associated CBPDx bit. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 89 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com 6.11.10 Port U (PU.0/DP, PU.1/DM, PUR) USB Ports Figure 6-12 shows the port diagram. Table 6-53 through Table 6-55 summarize the selection of the pin functions. PUSEL PUOPE 0 USB output enable 1 PUOUT0 0 USB DP output 1 VUSB VSSU Pad Logic PU.0/DP PUIN0 USB DP input PUIPE PUIN1 USB DM input PUOUT1 0 USB DM output 1 PU.1/DM VUSB VSSU Pad Logic PUREN PUR “1 ” PUSEL PURIN Figure 6-12. Port U (PU.0/DP, PU.1/DM, PUR) Diagram 90 Detailed Description Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 Table 6-53. Port U (PU.0/DP and PU.1/DM) Output Functions (1) CONTROL BITS (1) (2) PIN NAME PUSEL PUOPE PUOUT1 PUOUT0 PU.1/DM PU.0/DP 0 0 X X Output disabled Output disabled 0 1 0 0 Output low Output low 0 1 0 1 Output low Output high 0 1 1 0 Output high Output low 0 1 1 1 Output high Output high 1 X X X DM (2) DP (2) PU.1/DM and PU.0/DP inputs and outputs are supplied from VUSB. VUSB can be generated by the device using the integrated 3.3-V LDO when enabled. VUSB can also be supplied externally when the 3.3-V LDO is not being used and is disabled. Output state set by the USB module. Table 6-54. Port U (PU.0/DP and PU.1/DM) Input Functions (1) CONTROL BITS (1) PIN NAME PUSEL PUIPE PU.1/DM PU.0/DP 0 0 Input disabled Input disabled 0 1 Input enabled Input enabled 1 X DM input DP input PU.1/DM and PU.0/DP inputs and outputs are supplied from VUSB. VUSB can be generated by the device using the integrated 3.3-V LDO when enabled. VUSB can also be supplied externally when the 3.3-V LDO is not being used and is disabled. Table 6-55. Port U (PUR) Input Functions CONTROL BITS FUNCTION PUSEL PUREN 0 0 Input disabled Pullup disabled 0 1 Input disabled Pullup enabled 1 0 Input enabled Pullup disabled 1 1 Input enabled Pullup enabled Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 91 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com 6.11.11 Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output Figure 6-13 shows the port diagram. Table 6-56 summarizes the selection of the pin functions. Pad Logic PJREN.0 PJDIR.0 0 DVCC 1 PJOUT.0 0 From JTAG 1 DVSS 0 DVCC 1 PJDS.0 0: Low drive 1: High drive From JTAG 1 PJ.0/TDO PJIN.0 EN D Figure 6-13. Port PJ (PJ.0) Diagram 92 Detailed Description Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 6.11.12 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output Figure 6-14 shows the port diagram. Table 6-56 summarizes the selection of the pin functions. Pad Logic PJREN.x PJDIR.x 0 DVSS 1 PJOUT.x 0 From JTAG 1 DVSS 0 DVCC 1 1 PJDS.x 0: Low drive 1: High drive From JTAG PJ.1/TDI/TCLK PJ.2/TMS PJ.3/TCK PJIN.x EN D To JTAG Figure 6-14. Port PJ (PJ.1 to PJ.3) Diagram Table 6-56. Port PJ (PJ.0 to PJ.3) Pin Functions PIN NAME (PJ.x) x FUNCTION CONTROL BITS OR SIGNALS (1) PJDIR.x PJ.0/TDO 0 PJ.1/TDI/TCLK PJ.2/TMS PJ.3/TCK (1) (2) (3) (4) 1 2 3 PJ.0 (I/O) (2) I: 0; O: 1 TDO (3) X PJ.1 (I/O) (2) TDI/TCLK (3) I: 0; O: 1 (4) PJ.2 (I/O) (2) TMS (3) (4) PJ.3 (I/O) (2) TCK (3) (4) X I: 0; O: 1 X I: 0; O: 1 X X = Don't care Default condition The pin direction is controlled by the JTAG module. In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 93 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com 6.12 Device Descriptors Table 6-57 and Table 6-58 list the complete contents of the device descriptor tag-length-value (TLV) structure for each device type. Table 6-57. F5504 to F5510 Device Descriptor Table (1) VALUE DESCRIPTION Info Block Die Record ADC10 Calibration REF Calibration (1) 94 ADDRESS SIZE (bytes) F5510 RGC, ZXH, ZQE F5509 RGZ, PT RGC, ZXH, ZQE F5508 RGZ, PT RGC, ZXH, ZQE RGZ, PT F5507 F5506 F5505 F5504 Info length 01A00h 1 06h 06h 06h 06h 06h 06h 06h 06h 06h 06h CRC length 01A01h 1 06h 06h 06h 06h 06h 06h 06h 06h 06h 06h CRC value 01A02h 2 Device ID 01A04h 1 31h 31h 3Ah 3Ah 39h 39h 38h 37h 36h 35h Device ID 01A05h 1 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h Hardware revision 01A06h 1 Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Firmware revision 01A07h 1 Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Die record tag 01A08h 1 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h Die record length 01A09h 1 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Lot/wafer ID 01A0Ah 4 Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Die X position 01A0Eh 2 Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Die Y position 01A10h 2 Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Test results 01A12h 2 Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit ADC10 calibration tag 01A14h 1 13h 13h 13h 13h 13h 13h 13h 13h 13h 13h ADC10 calibration length 01A15h 1 10h 10h 10h 10h 10h 10h 10h 10h 10h 10h ADC gain factor 01A16h 2 Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit ADC offset 01A18h 2 Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit ADC 1.5-V reference Temp. sensor 30°C 01A1Ah 2 Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit ADC 1.5-V reference Temp. sensor 85°C 01A1Ch 2 Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit ADC 2.0-V reference Temp. sensor 30°C 01A1Eh 2 Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit ADC 2.0-V reference Temp. sensor 85°C 01A20h 2 Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit ADC 2.5-V reference Temp. sensor 30°C 01A22h 2 Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit ADC 2.5-V reference Temp. sensor 85°C 01A24h 2 Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit REF calibration tag 01A26h 1 12h 12h 12h 12h 12h 12h 12h 12h 12h 12h REF calibration length 01A27h 1 06h 06h 06h 06h 06h 06h 06h 06h 06h 06h REF 1.5-V reference factor 01A28h 2 Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit REF 2.0-V reference factor 01A2Ah 2 Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit REF 2.5-V reference factor 01A2Ch 2 Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit N/A = Not applicable Detailed Description Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 Table 6-57. F5504 to F5510 Device Descriptor Table (1) (continued) VALUE DESCRIPTION ADDRESS SIZE (bytes) RGC, ZXH, ZQE F5509 RGZ, PT RGC, ZXH, ZQE F5508 RGZ, PT RGC, ZXH, ZQE RGZ, PT F5507 F5506 F5505 F5504 Peripheral descriptor tag 01A2Eh 1 02h 02h 02h 02h 02h 02h 02h 02h 02h 02h Peripheral descriptor length 01A2Fh 1 61h 61h 62h 62h 61h 61h 5Dh 5Eh 5Dh 5Dh Memory 1 2 08h 8Ah 08h 8Ah 08h 8Ah 08h 8Ah 08h 8Ah 08h 8Ah 08h 8Ah 08h 8Ah 08h 8Ah 08h 8Ah Memory 2 2 0Ch 86h 0Ch 86h 0Ch 86h 0Ch 86h 0Ch 86h 0Ch 86h 0Ch 86h 0Ch 86h 0Ch 86h 0Ch 86h Memory 3 2 0Eh 2Ah 0Eh 2Ah 0Eh 2Ah 00Eh 2Ah 0Eh 2Ah 0Eh 2Ah 0Eh 2Ah 0Eh 2Ah 0Eh 2Ah 0Eh 2Ah Memory 4 2 12h 2Ch 12h 2Ch 12h 2Ch 12h 2Ch 12h 2Ch 12h 2Ch 12h 2Ch 12h 2Ch 12h 2Ch 12h 2Ch Memory 5 2 40h 92h 40h 92h 50h 91h 50h 91h 60h 90h 60h 90h 40h 92h 50h 91h 60h 90h 70h 8Eh N/A Memory 6 Peripheral Descriptor F5510 N/A N/A 8Eh 8Eh N/A N/A N/A 8Eh N/A Delimiter 1 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h Peripheral count 1 20h 20h 20h 20h 20h 20h 1Eh 1Eh 1Eh 1Eh MSP430CPUXV2 2 00h 23h 00h 23h 00h 23h 00h 23h 00h 23h 00h 23h 00h 23h 00h 23h 00h 23h 00h 23h JTAG 2 00h 09h 00h 09h 00h 09h 00h 09h 00h 09h 00h 09h 00h 09h 00h 09h 00h 09h 00h 09h SBW 2 00h 0Fh 00h 0Fh 00h 0Fh 00h 0Fh 00h 0Fh 00h 0Fh 00h 0Fh 00h 0Fh 00h 0Fh 00h 0Fh EEM-S 2 00h 03h 00h 03h 00h 03h 00h 03h 00h 03h 00h 03h 00h 03h 00h 03h 00h 03h 00h 03h TI BSL 2 00h FCh 00h FCh 00h FCh 00h FCh 00h FCh 00h FCh 00h FCh 00h FCh 00h FCh 00h FCh SFR 2 10h 41h 10h 41h 10h 41h 10h 41h 10h 41h 10h 41h 10h 41h 10h 41h 10h 41h 10h 41h PMM 2 02h 30h 02h 30h 02h 30h 02h 30h 02h 30h 02h 30h 02h 30h 02h 30h 02h 30h 02h 30h FCTL 2 02h 38h 02h 38h 02h 38h 02h 38h 02h 38h 02h 38h 02h 38h 02h 38h 02h 38h 02h 38h CRC16 2 01h 3Ch 01h 3Ch 01h 3Ch 01h 3Ch 01h 3Ch 01h 3Ch 01h 3Ch 01h 3Ch 01h 3Ch 01h 3Ch CRC16_RB 2 00h 3Dh 00h 3Dh 00h 3Dh 00h 3Dh 00h 3Dh 00h 3Dh 00h 3Dh 00h 3Dh 00h 3Dh 00h 3Dh RAMCTL 2 00h 44h 00h 44h 00h 44h 00h 44h 00h 44h 00h 44h 00h 44h 00h 44h 00h 44h 00h 44h WDT_A 2 00h 40h 00h 40h 00h 40h 00h 40h 00h 40h 00h 40h 00h 40h 00h 40h 00h 40h 00h 40h UCS 2 01h 48h 01h 48h 01h 48h 01h 48h 01h 48h 01h 48h 01h 48h 01h 48h 01h 48h 01h 48h SYS 2 02h 42h 02h 42h 02h 42h 02h 42h 02h 42h 02h 42h 02h 42h 02h 42h 02h 42h 02h 42h REF 2 03h A0h 03h A0h 03h A0h 03h A0h 03h A0h 03h A0h 03h A0h 03h A0h 03h A0h 03h A0h Port Mapping 2 01h 10h 01h 10h 01h 10h 01h 10h 01h 10h 01h 10h 01h 10h 01h 10h 01h 10h 01h 10h Port 1 and 2 2 04h 51h 04h 51h 04h 51h 04h 51h 04h 51h 04h 51h 04h 51h 04h 51h 04h 51h 04h 51h Port 3 and 4 2 02h 52h 02h 52h 02h 52h 02h 52h 02h 52h 02h 52h 02h 52h 02h 52h 02h 52h 02h 52h Port 5 and 6 2 02h 53h 02h 53h 02h 53h 02h 53h 02h 53h 02h 53h 02h 53h 02h 53h 02h 53h 02h 53h Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 95 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com Table 6-57. F5504 to F5510 Device Descriptor Table (1) (continued) VALUE DESCRIPTION Peripheral Descriptor (continued) Interrupts 96 ADDRESS SIZE (bytes) F5510 RGC, ZXH, ZQE F5509 RGZ, PT RGC, ZXH, ZQE F5508 RGZ, PT RGC, ZXH, ZQE RGZ, PT F5507 F5506 F5505 F5504 JTAG 2 0Eh 5Fh 0Eh 5Fh 0Eh 5Fh 0Eh 5Fh 0Eh 5Fh 0Eh 5Fh 0Eh 5Fh 0Eh 5Fh 0Eh 5Fh 0Eh 5Fh TA0 2 02h 62h 02h 62h 02h 62h 02h 62h 02h 62h 02h 62h 02h 62h 02h 62h 02h 62h 02h 62h TA1 2 04h 61h 04h 61h 04h 61h 04h 61h 04h 61h 04h 61h 04h 61h 04h 61h 04h 61h 04h 61h TB0 2 04h 67h 04h 67h 04h 67h 04h 67h 04h 67h 04h 67h 04h 67h 04h 67h 04h 67h 04h 67h TA2 2 04h 61h 04h 61h 04h 61h 04h 61h 04h 61h 04h 61h 04h 61h 04h 61h 04h 61h 04h 61h RTC 2 0Ah 68h 0Ah 68h 0Ah 68h 0Ah 68h 0Ah 68h 0Ah 68h 0Ah 68h 0Ah 68h 0Ah 68h 0Ah 68h MPY32 2 02h 85h 02h 85h 02h 85h 02h 85h 02h 85h 02h 85h 02h 85h 02h 85h 02h 85h 02h 85h DMA-3 2 04h 47h 04h 47h 04h 47h 04h 47h 04h 47h 04h 47h 04h 47h 04h 47h 04h 47h 04h 47h USCI_A and USCI_B 2 0Ch 90h 0Ch 90h 0Ch 90h 0Ch 90h 0Ch 90h 0Ch 90h 10h 90h 10h 90h 10h 90h 10h 90h USCI_A and USCI_B 2 04h 90h 04h 90h 04h 90h 04h 90h 04h 90h 04h 90h N/A N/A N/A N/A ADC10_A 2 14h D3h 14h D3h 14h D3h 14h D3h 14h D3h 14h D3h 14h D3h 14h D3h 14h D3h 14h D3h COMP_B 2 18h A8h 18h A8h 18h A8h 18h A8h 18h A8h 18h A8h N/A N/A N/A N/A USB 2 04h 98h 04h 98h 04h 98h 04h 98h 04h 98h 04h 98h 1Ch 98h 1Ch 98h 1Ch 98h 1Ch 98h COMP_B 1 A8h A8h A8h A8h A8h A8h 01h 01h 01h 01h TB0.CCIFG0 1 64h 64h 64h 64h 64h 64h 64h 64h 64h 64h TB0.CCIFG1..6 1 65h 65h 65h 65h 65h 65h 65h 65h 65h 65h WDTIFG 1 40h 40h 40h 40h 40h 40h 40h 40h 40h 40h USCI_A0 1 90h 90h 90h 90h 90h 90h 01h 01h 01h 01h USCI_B0 1 91h 91h 91h 91h 91h 91h 01h 01h 01h 01h ADC10_A 1 D0h D0h D0h D0h D0h D0h D0h D0h D0h D0h TA0.CCIFG0 1 60h 60h 60h 60h 60h 60h 60h 60h 60h 60h TA0.CCIFG1..4 1 61h 61h 61h 61h 61h 61h 61h 61h 61h 61h USB 1 98h 98h 98h 98h 98h 98h 98h 98h 98h 98h DMA 1 46h 46h 46h 46h 46h 46h 46h 46h 46h 46h TA1.CCIFG0 1 62h 62h 62h 62h 62h 62h 62h 62h 62h 62h TA1.CCIFG1..2 1 63h 63h 63h 63h 63h 63h 63h 63h 63h 63h P1 1 50h 50h 50h 50h 50h 50h 50h 50h 50h 50h USCI_A1 1 92h 92h 92h 92h 92h 92h 92h 92h 92h 92h USCI_B1 1 93h 93h 93h 93h 93h 93h 93h 93h 93h 93h TA1.CCIFG0 1 66h 66h 66h 66h 66h 66h 66h 66h 66h 66h TA1.CCIFG1..2 1 67h 67h 67h 67h 67h 67h 67h 67h 67h 67h P2 1 51h 51h 51h 51h 51h 51h 51h 51h 51h 51h RTC_A 1 68h 68h 68h 68h 68h 68h 68h 68h 68h 68h Delimiter 1 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h Detailed Description Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 Table 6-58. F5500 to F5503 Device Descriptor (1) Info Block Die Record ADC10 Calibration REF Calibration Peripheral Descriptor (1) VALUE ADDRESS SIZE (bytes) F5503 F5502 F5501 F5500 Info length 01A00h 1 06h 06h 06h 06h CRC length 01A01h 1 06h 06h 06h 06h CRC value 01A02h 2 Per unit Per unit Per unit Per unit Device ID 01A04h 1 34h 33h 32h 3Bh Device ID 01A05h 1 80h 80h 80h 80h Hardware revision 01A06h 1 Per unit Per unit Per unit Per unit Firmware revision 01A07h 1 Per unit Per unit Per unit Per unit Die record tag 01A08h 1 08h 08h 08h 08h Die record length 01A09h 1 0Ah 0Ah 0Ah 0Ah DESCRIPTION Lot/wafer ID 01A0Ah 4 Per unit Per unit Per unit Per unit Die X position 01A0Eh 2 Per unit Per unit Per unit Per unit Die Y position 01A10h 2 Per unit Per unit Per unit Per unit Test results 01A12h 2 Per unit Per unit Per unit Per unit Empty tag 01A14h 1 05h 05h 05h 05h Empty tag length 01A15h 1 10h 10h 10h 10h REF calibration tag 01A26h 1 12h 12h 12h 12h REF calibration length 01A27h 1 06h 06h 06h 06h REF 1.5-V reference factor 01A28h 2 Per unit Per unit Per unit Per unit REF 2.0-V reference factor 01A2Ah 2 Per unit Per unit Per unit Per unit REF 2.5-V reference factor 01A2Ch 2 Per unit Per unit Per unit Per unit Peripheral descriptor tag 01A2Eh 1 02h 02h 02h 02h Peripheral descriptor length 01A2Fh 1 5Dh 5Eh 5Dh 5Dh Memory 1 2 08h 8Ah 08h 8Ah 08h 8Ah 08h 8Ah Memory 2 2 0Ch 86h 0Ch 86h 0Ch 86h 0Ch 86h Memory 3 2 0Eh 2Ah 0Eh 2Ah 0Eh 2Ah 0Eh 2Ah Memory 4 2 12h 2Ch 12h 2Ch 12h 2Ch 12h 2Ch Memory 5 2 40h 92h 50h 91 60h 90h 70h 8Eh Memory 6 1 N/A 8E N/A N/A Delimiter 1 00h 00h 00h 00h Peripheral count 1 1Eh 1Eh 1Eh 1Eh MSP430CPUXV2 2 00h 23h 00h 23h 00h 23h 00h 23h JTAG 2 00h 09h 00h 09h 00h 09h 00h 09h SBW 2 00h 0Fh 00h 0Fh 00h 0Fh 00h 0Fh EEM-S 2 00h 03h 00h 03h 00h 03h 00h 03h TI BSL 2 00h FCh 00h FCh 00h FCh 00h FCh SFR 2 10h 41h 10h 41h 10h 41h 10h 41h PMM 2 02h 30h 02h 30h 02h 30h 02h 30h FCTL 2 02h 38h 02h 38h 02h 38h 02h 38h N/A = Not applicable Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 97 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com Table 6-58. F5500 to F5503 Device Descriptor(1) (continued) DESCRIPTION SIZE (bytes) VALUE F5503 F5502 F5501 F5500 01h 3Ch 01h 3Ch 01h 3Ch CRC16 2 01h 3Ch CRC16_RB 2 00h 3Dh 00h 3Dh 00h 3Dh 00h 3Dh RAMCTL 2 00h 44h 00h 44h 00h 44h 00h 44h WDT_A 2 00h 40h 00h 40h 00h 40h 00h 40h UCS 2 01h 48h 01h 48h 01h 48h 01h 48h SYS 2 02h 42h 02h 42h 02h 42h 02h 42h REF 2 03h A0h 03h A0h 03h A0h 03h A0h Port Mapping 2 01h 10h 01h 10h 01h 10h 01h 10h Port 1 and 2 2 04h 51h 04h 51h 04h 51h 04h 51h Port 3 and 4 2 02h 52h 02h 52h 02h 52h 02h 52h Port 5 and 6 2 02h 53h 02h 53h 02h 53h 02h 53h JTAG 2 0Eh 5Fh 0Eh 5Fh 0Eh 5Fh 0Eh 5Fh TA0 2 02h 62h 02h 62h 02h 62h 02h 62h TA1 2 04h 61h 04h 61h 04h 61h 04h 61h TB0 2 04h 67h 04h 67h 04h 67h 04h 67h TA2 2 04h 61h 04h 61h 04h 61h 04h 61h RTC 2 0Ah 68h 0Ah 68h 0Ah 68h 0Ah 68h MPY32 2 02h 85h 02h 85h 02h 85h 02h 85h DMA-3 2 04h 47h 04h 47h 04h 47h 04h 47h USCI_A and USCI_B 2 10h 90h 10h 90h 10h 90h 10h 90h ADC10_A 2 N/A N/A N/A N/A COMP_B 2 2Ch A8h 2Ch A8h 2Ch A8h 2Ch A8h USB 2 04h 98h 04h 98h 04h 98h 04h 98h Peripheral Descriptor (continued) 98 ADDRESS Detailed Description Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 Table 6-58. F5500 to F5503 Device Descriptor(1) (continued) Interrupts VALUE SIZE (bytes) F5503 F5502 F5501 F5500 COMP_B 1 A8h A8h A8h A8h TB0.CCIFG0 1 64h 64h 64h 64h TB0.CCIFG1..6 1 65h 65h 65h 65h WDTIFG 1 40h 40h 40h 40h USCI_A0 1 01h 01h 01h 01h USCI_B0 1 01h 01h 01h 01h ADC10_A 1 01h 01h 01h 01h TA0.CCIFG0 1 60h 60h 60h 60h TA0.CCIFG1..4 1 61h 61h 61h 61h USB 1 98h 98h 98h 98h DMA 1 46h 46h 46h 46h DESCRIPTION ADDRESS TA1.CCIFG0 1 62h 62h 62h 62h TA1.CCIFG1..2 1 63h 63h 63h 63h P1 1 50h 50h 50h 50h USCI_A1 1 92h 92h 92h 92h USCI_B1 1 93h 93h 93h 93h TA1.CCIFG0 1 66h 66h 66h 66h TA1.CCIFG1..2 1 67h 67h 67h 67h P2 1 51h 51h 51h 51h RTC_A 1 68h 68h 68h 68h Delimiter 1 00h 00h 00h 00h Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 99 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com 7 Device and Documentation Support 7.1 Getting Started and Next Steps For an introduction to the MSP430™ family of microcontrollers and the tools and libraries that are available to help with your development, visit the MSP430 ultra-low-power sensing & measurement MCUs overview. 7.2 Device Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS. These prefixes represent evolutionary stages of product development from engineering prototypes (XMS) through fully qualified production devices (MSP). XMS – Experimental device that is not necessarily representative of the final device's electrical specifications MSP – Fully qualified production device XMS devices are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices. TI recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature range, package type, and distribution format. Figure 7-1 provides a legend for reading the complete device name. 100 Device and Documentation Support Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 MSP 430 F 5 438 A I PM T -EP Processor Family Optional: Additional Features MCU Platform Optional: Tape and Reel Device Type Packaging Series Feature Set Processor Family Optional: Temperature Range Optional: Revision CC = Embedded RF Radio MSP = Mixed-Signal Processor XMS = Experimental Silicon PMS = Prototype Device 430 = MSP430 low-power microcontroller platform MCU Platform Device Type Memory Type C = ROM F = Flash FR = FRAM G = Flash L = No nonvolatile memory Specialized Application AFE = Analog front end BQ = Contactless power CG = ROM medical FE = Flash energy meter FG = Flash medical FW = Flash electronic flow meter Series 1 = Up to 8 MHz 2 = Up to 16 MHz 3 = Legacy 4 = Up to 16 MHz with LCD driver 5 = Up to 25 MHz 6 = Up to 25 MHz with LCD driver 0 = Low-voltage series Feature Set Various levels of integration within a series Optional: Revision Updated version of the base part number Optional: Temperature Range S = 0°C to 50°C C = 0°C to 70°C I = –40°C to 85°C T = –40°C to 105°C Packaging http://www.ti.com/packaging Optional: Tape and Reel T = Small reel R = Large reel No markings = Tube or tray Optional: Additional Features -EP = Enhanced product (–40°C to 105°C) -HT = Extreme temperature parts (–55°C to 150°C) -Q1 = Automotive Q100 qualified Figure 7-1. Device Nomenclature Device and Documentation Support Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 101 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 7.3 www.ti.com Tools and Software All MSP microcontrollers are supported by a wide variety of software and hardware development tools. Tools are available from TI and various third parties. See them all at MSP430 Ultra-Low-Power MCUs – Tools & software. Table 7-1 lists the debug features of the MSP430F5510 and MSP430F550x MCUs. See the Code Composer Studio IDE for MSP430 User's Guide for details on the available features. Table 7-1. Hardware Features MSP430 ARCHITECTURE 4-WIRE JTAG 2-WIRE JTAG BREAKPOINTS (N) RANGE BREAKPOINTS CLOCK CONTROL STATE SEQUENCER TRACE BUFFER LPMx.5 DEBUGGING SUPPORT MSP430Xv2 Yes Yes 8 Yes Yes Yes Yes No Design Kits and Evaluation Modules 64-Pin Target Development Board and MSP-FET Programmer Bundle for MSP430F5x MCUs The MSP-FET430U64USB is a powerful flash emulation tool that allows you to quickly begin application development on the MSP430 MCU. It includes USB debugging interface used to program and debug the MSP430 in-system through the JTAG interface or the pin saving Spy Bi-Wire (2-wire JTAG) protocol. The flash memory can be erased and programmed in seconds with only a few keystrokes, and because the MSP430 flash is ultra-low power, no external power supply is required. MSP-TS430RGC64USB - 64-pin Target Development Board for MSP430F5x MCUs The MSPTS430RGC64USB is a stand-alone 64-pin ZIF socket target board used to program and debug the MSP430 MCU in-system through the JTAG interface or the Spy Bi-Wire (2-wire JTAG) protocol. Software MSP430Ware™ Software MSP430Ware software is a collection of code examples, data sheets, and other design resources for all MSP430 devices delivered in a convenient package. In addition to providing a complete collection of existing MSP430 design resources, MSP430Ware software also includes a high-level API called MSP Driver Library. This library makes it easy to program MSP430 hardware. MSP430Ware software is available as a component of Code Composer Studio™ IDE or as a stand-alone package. MSP430F550x, MSP430F5510 C Code Examples C Code examples are available for every MSP device that configures each of the integrated peripherals for various application needs. MSP Driver Library Driver Library's abstracted API keeps you above the bits and bytes of the MSP430 hardware by providing easy-to-use function calls. Thorough documentation is delivered through a helpful API Guide, which includes details on each function call and the recognized parameters. Developers can use Driver Library functions to write complete projects with minimal overhead. MSP EnergyTrace™ Technology EnergyTrace technology for MSP430 microcontrollers is an energybased code analysis tool that measures and displays the application’s energy profile and helps to optimize it for ultra-low-power consumption. ULP (Ultra-Low Power) Advisor ULP Advisor™ software is a tool for guiding developers to write more efficient code to fully utilize the unique ultra-low power features of MSP and MSP432 microcontrollers. Aimed at both experienced and new microcontroller developers, ULP Advisor checks your code against a thorough ULP checklist to squeeze every last nano amp out of your application. At build time, ULP Advisor will provide notifications and remarks to highlight areas of your code that can be further optimized for lower power. MSP430 USB Developers Package The USB Developers Package for MSP430 is a software package containing all necessary source code and sample applications required for developing a USB-based MSP430 project. The package only supports MSP430 USB devices. 102 Device and Documentation Support Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 IEC60730 Software Package The IEC60730 MSP430 software package was developed to be useful in assisting customers in complying with IEC 60730-1:2010 (Automatic Electrical Controls for Household and Similar Use – Part 1: General Requirements) for up to Class B products, which includes home appliances, arc detectors, power converters, power tools, e-bikes, and many others. The IEC60730 MSP430 software package can be embedded in customer applications running on MSP430s to help simplify the customer’s certification efforts of functional safety-compliant consumer devices to IEC 60730-1:2010 Class B. Fixed Point Math Library for MSP The MSP IQmath and Qmath Libraries are a collection of highly optimized and high-precision mathematical functions for C programmers to seamlessly port a floating-point algorithm into fixed-point code on MSP430 and MSP432 devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed, high accuracy, and ultra-low energy are critical. By using the IQmath and Qmath libraries, it is possible to achieve execution speeds considerably faster and energy consumption considerably lower than equivalent code written using floating-point math. Floating Point Math Library for MSP430 Continuing to innovate in the low power and low cost microcontroller space, TI brings you MSPMATHLIB. Leveraging the intelligent peripherals of our devices, this floating point math library of scalar functions brings you up to 26x better performance. Mathlib is easy to integrate into your designs. This library is free and is integrated in both Code Composer Studio and IAR IDEs. Read the user’s guide for an in depth look at the math library and relevant benchmarks. Development Tools Code Composer Studio™ Integrated Development Environment for MSP Microcontrollers Code Composer Studio is an integrated development environment (IDE) that supports all MSP microcontroller devices. Code Composer Studio comprises a suite of embedded software utilities used to develop and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment, debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking you through each step of the application development flow. Familiar utilities and interfaces allow users to get started faster than ever before. Code Composer Studio combines the advantages of the Eclipse software framework with advanced embedded debug capabilities from TI resulting in a compelling feature-rich development environment for embedded developers. When using CCS with an MSP MCU, a unique and powerful set of plugins and embedded software utilities are made available to fully leverage the MSP microcontroller. Command-Line Programmer MSP Flasher is an open-source shell-based interface for programming MSP microcontrollers through a FET programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP Flasher can download binary files (.txt or .hex) files directly to the MSP microcontroller without an IDE. MSP MCU Programmer and Debugger The MSP-FET is a powerful emulation development tool – often called a debug probe – which allows users to quickly begin application development on MSP low-power microcontrollers (MCU). Creating MCU software usually requires downloading the resulting binary program to the MSP device for validation and debugging. The MSP-FET provides a debug communication pathway between a host computer and the target MSP. Furthermore, the MSP-FET also provides a Backchannel UART connection between the computer's USB interface and the MSP UART. This affords the MSP programmer a convenient method for communicating serially between the MSP and a terminal running on the computer. It also supports loading programs (often called firmware) to the MSP target using the BSL (bootloader) through the UART and I2C communication protocols. MSP-GANG Production Programmer The MSP Gang Programmer is an MSP430 or MSP432 device programmer that can program up to eight identical MSP430 or MSP432 Flash or FRAM devices at the same time. The MSP Gang Programmer connects to a host PC using a standard RS-232 or USB connection and provides flexible programming options that allow the user to fully customize the process. The MSP Gang Programmer is provided with an expansion board, called the Gang Splitter, that implements the interconnections between the MSP Gang Programmer and multiple target devices. Eight cables are provided that connect the expansion board to eight target devices (through JTAG or Spy-Bi-Wire connectors). The programming can be done with a PC or as a stand-alone device. A PC-side graphical user interface is also available and is DLL-based. Device and Documentation Support Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 103 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 7.4 www.ti.com Documentation Support The following documents describe the MSP430F550x microcontrollers. Copies of these documents are available on the Internet at www.ti.com. Receiving Notification of Document Updates To receive notification of documentation updates—including silicon errata—go to the product folder for your device on ti.com (for links to the product folders, see Table 7-2). In the upper right corner, click the "Alert me" button. This registers you to receive a weekly digest of product information that has changed (if any). For change details, check the revision history of any revised document. Errata MSP430F5510 Device Erratasheet Describes the known exceptions to the functional specifications for the MSP430F5510 device. MSP430F5509 Device Erratasheet Describes the known exceptions to the functional specifications for the MSP430F5509 device. MSP430F5508 Device Erratasheet Describes the known exceptions to the functional specifications for the MSP430F5508 device. MSP430F5507 Device Erratasheet Describes the known exceptions to the functional specifications for the MSP430F5507 device. MSP430F5506 Device Erratasheet Describes the known exceptions to the functional specifications for the MSP430F5506 device. MSP430F5505 Device Erratasheet Describes the known exceptions to the functional specifications for the MSP430F5505 device. MSP430F5504 Device Erratasheet Describes the known exceptions to the functional specifications for the MSP430F5504 device. MSP430F5503 Device Erratasheet Describes the known exceptions to the functional specifications for the MSP430F5503 device. MSP430F5502 Device Erratasheet Describes the known exceptions to the functional specifications for the MSP430F5502 device. MSP430F5501 Device Erratasheet Describes the known exceptions to the functional specifications for the MSP430F5501 device. MSP430F5500 Device Erratasheet Describes the known exceptions to the functional specifications for the MSP430F5500 device. User's Guides MSP430F5xx and MSP430F6xx Family User's Guide peripherals available in this device family. Detailed information on the modules and MSP430 Flash Device Bootloader (BSL) User's Guide The MSP430 bootloader (BSL) lets users communicate with embedded memory in the MSP430 microcontroller during the prototyping phase, final production, and in service. Both the programmable memory (flash memory) and the data memory (RAM) can be modified as required. Do not confuse the bootloader with the bootstrap loader programs found in some digital signal processors (DSPs) that automatically load program code (and data) from external memory to the internal memory of the DSP. MSP430 Programming With the JTAG Interface This document describes the functions that are required to erase, program, and verify the memory module of the MSP430 flash-based and FRAM-based microcontroller families using the JTAG communication port. In addition, it describes how to program the JTAG access security fuse that is available on all MSP430 devices. This document describes device access using both the standard 4-wire JTAG interface and the 2-wire JTAG interface, which is also referred to as Spy-Bi-Wire (SBW). MSP430 Hardware Tools User's Guide This manual describes the hardware of the TI MSP-FET430 Flash Emulation Tool (FET). The FET is the program development tool for the MSP430 ultralow-power microcontroller. Both available interface types, the parallel port interface and the USB interface, are described. 104 Device and Documentation Support Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 Application Reports MSP430 32-kHz Crystal Oscillators Selection of the right crystal, correct load circuit, and proper board layout are important for a stable crystal oscillator. This application report summarizes crystal oscillator function and explains the parameters to select the correct crystal for MSP430 ultralow-power operation. In addition, hints and examples for correct board layout are given. The document also contains detailed information on the possible oscillator tests to ensure stable oscillator operation in mass production. MSP430 System-Level ESD Considerations System-Level ESD has become increasingly demanding with silicon technology scaling towards lower voltages and the need for designing costeffective and ultra-low-power components. This application report addresses three different ESD topics to help board designers and OEMs understand and design robust system-level designs: (1) Component-level ESD testing and system-level ESD testing, their differences and why component-level ESD rating does not ensure system-level robustness. (2) General design guidelines for system-level ESD protection at different levels including enclosures, cables, PCB layout, and on-board ESD protection devices. (3) Introduction to System Efficient ESD Design (SEED), a co-design methodology of on-board and on-chip ESD protection to achieve system-level ESD robustness, with example simulations and test results. A few real-world system-level ESD protection design examples and their results are also discussed. 7.5 Related Links Table 7-2 lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 7-2. Related Links 7.6 PARTS PRODUCT FOLDER ORDER NOW TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY MSP430F5510 Click here Click here Click here Click here Click here MSP430F5509 Click here Click here Click here Click here Click here MSP430F5508 Click here Click here Click here Click here Click here MSP430F5507 Click here Click here Click here Click here Click here MSP430F5506 Click here Click here Click here Click here Click here MSP430F5505 Click here Click here Click here Click here Click here MSP430F5504 Click here Click here Click here Click here Click here MSP430F5503 Click here Click here Click here Click here Click here MSP430F5502 Click here Click here Click here Click here Click here MSP430F5501 Click here Click here Click here Click here Click here MSP430F5500 Click here Click here Click here Click here Click here Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers. TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices. Device and Documentation Support Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 105 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 7.7 www.ti.com Trademarks MicroStar Junior, MSP430, MSP430Ware, Code Composer Studio, EnergyTrace, ULP Advisor, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 7.8 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 7.9 Export Control Notice Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled product restricted by other applicable national regulations, received from disclosing party under nondisclosure obligations (if any), or any direct product of such technology, to any destination to which such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S. Department of Commerce and other competent Government authorities to the extent required by those laws. 7.10 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 106 Device and Documentation Support Copyright © 2009–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 8 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Mechanical, Packaging, and Orderable Information Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Copyright © 2009–2020, Texas Instruments Incorporated 107 PACKAGE OPTION ADDENDUM www.ti.com 13-Apr-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) MSP430F5500IRGZR ACTIVE VQFN RGZ 48 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430 F5500 MSP430F5500IRGZT ACTIVE VQFN RGZ 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430 F5500 MSP430F5501IRGZR ACTIVE VQFN RGZ 48 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430 F5501 MSP430F5501IRGZT ACTIVE VQFN RGZ 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430 F5501 MSP430F5502IRGZR ACTIVE VQFN RGZ 48 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430 F5502 MSP430F5502IRGZT ACTIVE VQFN RGZ 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430 F5502 MSP430F5503IRGZR ACTIVE VQFN RGZ 48 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430 F5503 MSP430F5503IRGZT ACTIVE VQFN RGZ 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430 F5503 MSP430F5504IPT ACTIVE LQFP PT 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430F5504 MSP430F5504IPTR ACTIVE LQFP PT 48 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430F5504 MSP430F5504IRGZR ACTIVE VQFN RGZ 48 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430 F5504 MSP430F5504IRGZT ACTIVE VQFN RGZ 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430 F5504 MSP430F5505IRGZR ACTIVE VQFN RGZ 48 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430 F5505 MSP430F5505IRGZT ACTIVE VQFN RGZ 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430 F5505 MSP430F5506IRGZR ACTIVE VQFN RGZ 48 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430 F5506 MSP430F5506IRGZT ACTIVE VQFN RGZ 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430 F5506 MSP430F5507IRGZR ACTIVE VQFN RGZ 48 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430 F5507 Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 13-Apr-2022 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) MSP430F5507IRGZT ACTIVE VQFN RGZ 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430 F5507 MSP430F5508IPT ACTIVE LQFP PT 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430F5508 MSP430F5508IPTR ACTIVE LQFP PT 48 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430F5508 MSP430F5508IRGCR ACTIVE VQFN RGC 64 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430F5508 MSP430F5508IRGCT ACTIVE VQFN RGC 64 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430F5508 MSP430F5508IRGZR ACTIVE VQFN RGZ 48 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430 F5508 MSP430F5508IRGZT ACTIVE VQFN RGZ 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430 F5508 MSP430F5508IZXH ACTIVE NFBGA ZXH 80 576 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 F5508 MSP430F5509IPT ACTIVE LQFP PT 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430F5509 MSP430F5509IRGCR ACTIVE VQFN RGC 64 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430F5509 MSP430F5509IRGCT ACTIVE VQFN RGC 64 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430F5509 MSP430F5509IRGZR ACTIVE VQFN RGZ 48 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430 F5509 MSP430F5509IRGZT ACTIVE VQFN RGZ 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430 F5509 MSP430F5509IZXH ACTIVE NFBGA ZXH 80 576 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 F5509 MSP430F5509IZXHR ACTIVE NFBGA ZXH 80 2500 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 F5509 MSP430F5510IPT ACTIVE LQFP PT 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430F5510 MSP430F5510IPTR ACTIVE LQFP PT 48 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430F5510 MSP430F5510IRGCR ACTIVE VQFN RGC 64 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430F5510 MSP430F5510IRGCT ACTIVE VQFN RGC 64 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430F5510 MSP430F5510IRGZR ACTIVE VQFN RGZ 48 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430 F5510 Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 13-Apr-2022 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) MSP430F5510IRGZT ACTIVE VQFN RGZ 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 M430 F5510 MSP430F5510IZXH ACTIVE NFBGA ZXH 80 576 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 F5510 MSP430F5510IZXHR ACTIVE NFBGA ZXH 80 2500 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 F5510 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of