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MSP430F6459-HIREL
SLASEC3A – AUGUST 2016 – REVISED AUGUST 2016
MSP430F6459-HIREL Mixed-Signal Microcontroller
1 Device Overview
1.1
Features
1
• Low-Supply Voltage Range:
3.6 V Down to 1.8 V
• Ultra-Low-Power Consumption
– Active Mode (AM):
All System Clocks Active:
295 µA/MHz at 8 MHz, 3 V, Flash Program
Execution (Typical)
– Standby Mode (LPM3):
Watchdog With Crystal, and Supply Supervisor
Operational, Full RAM Retention, Fast Wakeup:
2 µA at 2.2 V, 2.2 µA at 3 V (Typical)
– Shutdown, Real-Time Clock (RTC) Mode
(LPM3.5):
Shutdown Mode, Active RTC With Crystal:
1.1 µA at 3 V (Typical)
– Shutdown Mode (LPM4.5):
0.45 µA at 3 V (Typical)
• Wake up From Standby Mode in 3 µs (Typical)
• 16-Bit RISC Architecture, Extended Memory, up to
20-MHz System Clock
• Flexible Power-Management System
– Fully Integrated LDO With Programmable
Regulated Core Supply Voltage
– Supply Voltage Supervision, Monitoring, and
Brownout
• Unified Clock System
– FLL Control Loop for Frequency Stabilization
– Low-Power Low-Frequency Internal Clock
Source (VLO)
– Low-Frequency Trimmed Internal Reference
1.2
•
•
•
•
•
•
•
•
•
•
•
•
•
Source (REFO)
– 32-kHz Crystals (XT1)
– High-Frequency Crystals up to 32 MHz (XT2)
Four 16-Bit Timers With 3, 5, or 7
Capture/Compare Registers
Three Universal Serial Communication Interfaces
(USCIs)
– USCI_A0, USCI_A1, and USCI_A2 Each
Support:
• Enhanced UART With Automatic Baud-Rate
Detection
• IrDA Encoder and Decoder
• Synchronous SPI
– USCI_B0, USCI_B1, and USCI_B2 Each
Support:
• I2C
• Synchronous SPI
12-Bit Analog-to-Digital Converter (ADC) With
Internal Shared Reference, Sample-and-Hold, and
Autoscan Feature
Two 12-Bit Digital-to-Analog Converters (DACs)
With Synchronization
Voltage Comparator
Integrated LCD Driver With Contrast Control for up
to 160 Segments
Hardware Multiplier Supports 32-Bit Operations
Serial Onboard Programming, No External
Programming Voltage Needed
Six-Channel Internal DMA
RTC Module With Supply Voltage Backup Switch
Applications
Analog and Digital Sensor Systems
Digital Motor Controls
Remote Controls
•
•
•
Thermostats
Digital Timers
Hand-Held Meters
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430F6459-HIREL
SLASEC3A – AUGUST 2016 – REVISED AUGUST 2016
1.3
www.ti.com
Description
The TI MSP430™ family of ultra-low-power microcontrollers consists of several devices that feature
different sets of peripherals targeted for various applications. The architecture, combined with five lowpower modes, is optimized to achieve extended battery life in portable measurement applications. The
device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to
maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from lowpower modes to active mode in 3 µs (typical).
The MSP430F6459-HIREL is a microcontroller configured with an integrated 3.3-V LDO, four 16-bit timers,
a high-performance 12-bit ADC, three USCIs, a hardware multiplier, DMA, an RTC module with alarm
capabilities, a comparator, and up to 74 I/O pins.
Typical applications for these devices include analog and digital sensor systems, digital motor control,
remote controls, thermostats, digital timers, and hand-held meters.
Device Information (1)
PART NUMBER
MSP430F6459-HIREL
(1)
(2)
PACKAGE
BODY SIZE (NOM) (2)
PZ (100)
16.0 mm × 16.0 mm
For the most current device, package, and ordering information, see the Package Option Addendum in Section 9, or see the TI website
at www.ti.com.
The sizes shown here are approximations. For the package dimensions with tolerances, see the Mechanical Data in Section 9.
1.4
Functional Block Diagram
Figure 1-1 shows the functional block diagram for this device.
XIN XOUT
DVCC
DVSS
AVCC
AVSS
RST/NMI
P1.x
XT2IN
XT2OUT
Unified
Clock
System
ACLK
SMCLK
MCLK
512KB
384KB
Flash
MID
Memory
Integrity
Detection
64KB
32KB
RAM
+2KB RAM
+8B Backup
RAM
Power
Management
SYS
Watchdog
LDO
SVM, SVS
Brownout
P2 Port
Mapping
Controller
PA
P2.x
P3.x
PB
P4.x
PC
P6.x
P5.x
P7.x
PD
P8.x
I/O Ports
P1, P2
2×8 I/Os
Interrupt
Capability
I/O Ports
P3, P4
2×8 I/Os
Interrupt
Capability
I/O Ports
P5, P6
2×8 I/Os
I/O Ports
P7, P8
1×6 I/Os
1×8 I/Os
PA
1×16 I/Os
PB
1×16 I/Os
PC
1×16 I/Os
PD
1×14 I/Os
PU.0
LDOO LDOI
PU.1
P9.x
I/O Ports
P9
1×8 I/Os
USCI0,1,2
PE
1×8 I/Os
Bx: SPI, I2C
PU Port
Ax: UART,
IrDA, SPI
LDO
CPUXV2
and
Working
Registers
EEM
(L: 8+2)
JTAG,
SBW
Interface
Port PJ
PJ.x
DMA
TA0
MPY32
Timer_A
5 CC
Registers
TA1 and
TA2
2 Timer_A
each with
3 CC
Registers
ADC12_A
RTC_B
TB0
Timer_B
7 CC
Registers
CRC16
Comp_B
Battery
Backup
System
12 bit
200 ksps
16 channels
(12 ext, 4 int)
Autoscan
LCD_B
DAC12_A
REF
12 bit
2 channels
voltage out
Reference
1.5 V, 2.0 V,
2.5 V
6 Channel
160
Segments
Copyright © 2016, Texas Instruments Incorporated
Figure 1-1. Functional Block Diagram
2
Device Overview
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SLASEC3A – AUGUST 2016 – REVISED AUGUST 2016
Table of Contents
1
2
3
4
5
Device Overview ......................................... 1
1.1
Features .............................................. 1
1.2
Applications ........................................... 1
1.3
Description ............................................ 2
1.4
Functional Block Diagram ............................ 2
Revision History ......................................... 4
Device Comparison ..................................... 5
Terminal Configuration and Functions .............. 6
Pin Diagram
4.2
Signal Descriptions ................................... 7
6
Specifications ........................................... 14
5.1
Absolute Maximum Ratings ......................... 14
5.2
ESD Ratings
........................................
14
5.3
5.4
Recommended Operating Conditions ...............
Active Mode Supply Current Into VCC Excluding
External Current .....................................
Low-Power Mode Supply Currents (Into VCC)
Excluding External Current..........................
Low-Power Mode With LCD Supply Currents (Into
VCC) Excluding External Current ....................
14
.....
Leakage Current – General-Purpose I/O ...........
19
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.13
5.14
6
..........................................
4.1
Schmitt-Trigger Inputs – General-Purpose I/O
16
7
16
18
8
19
Outputs – General-Purpose I/O (Full Drive
Strength) ............................................ 19
Outputs – General-Purpose I/O (Reduced Drive
Strength) ............................................ 19
Thermal Resistance Characteristics for PZ Package
...................................................... 20
Typical Characteristics – Outputs, Reduced Drive
Strength (PxDS.y = 0) ............................... 21
Typical Characteristics – Outputs, Full Drive
Strength (PxDS.y = 1) ............................... 22
Timing and Switching Characteristics ............... 23
Detailed Description ................................... 50
9
............................................ 50
................................................. 50
6.3
Instruction Set ....................................... 51
6.4
Operating Modes .................................... 52
6.5
Interrupt Vector Addresses.......................... 53
6.6
Memory Organization ............................... 55
6.7
Bootloader (BSL) .................................... 55
6.8
JTAG Operation ..................................... 57
6.9
Flash Memory ....................................... 57
6.10 Memory Integrity Detection (MID) ................... 58
6.11 RAM ................................................. 58
6.12 Backup RAM ........................................ 59
6.13 Peripherals .......................................... 59
6.14 Input/Output Schematics ............................ 86
6.15 Device Descriptors ................................. 109
Applications, Implementation, and Layout ...... 110
7.1
Device Connection and Layout Fundamentals .... 110
6.1
Overview
6.2
CPU
7.2
Peripheral- and Interface-Specific Design
Information ......................................... 114
Device and Documentation Support .............. 116
...................
8.1
Getting Started and Next Steps
8.2
Device Nomenclature .............................. 116
8.3
Tools and Software
8.4
Documentation Support ............................ 119
8.5
Receiving Notification of Documentation Updates. 120
8.6
Community Resources............................. 120
8.7
Trademarks ........................................ 120
8.8
Electrostatic Discharge Caution
8.9
Export Control Notice .............................. 120
8.10
Glossary............................................ 120
................................
...................
116
117
120
Mechanical, Packaging, and Orderable
Information ............................................. 121
Table of Contents
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SLASEC3A – AUGUST 2016 – REVISED AUGUST 2016
www.ti.com
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (July 2016) to Revision A
•
4
Page
Changed status to Production Data and full data manual released ............................................................ 1
Revision History
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3 Device Comparison
Table 3-1. Device Comparison (1) (2)
USCI
DEVICE
MSP430F6459
(1)
(2)
(3)
(4)
(5)
FLASH
(KB)
SRAM
(KB) (3)
Timer_A (4)
Timer_B (5)
512
66
5, 3, 3
7
CHANNEL
A:
UART, IrDA,
SPI
CHANNEL
B:
SPI, I2C
ADC12_A
(Ch)
DAC12_A
(Ch)
Comp_B
(Ch)
I/O
USB
LCD
PACKAGE
3
3
12 ext, 4 int
2
12
74
No
Yes
100 PZ
For the most current device, package, and ordering information, see the Package Option Addendum in Section 9, or see the TI website at www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging.
The additional 2KB of USB SRAM that is listed can be used as general-purpose SRAM when USB is not in use.
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output
generators, respectively.
Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output
generators, respectively.
Device Comparison
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MSP430F6459-HIREL
SLASEC3A – AUGUST 2016 – REVISED AUGUST 2016
www.ti.com
4 Terminal Configuration and Functions
4.1
Pin Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P9.7/S0
P9.6/UCB2SOMI/UCB2SCL/S1
P9.5/UCB2SIMO/UCB2SDA/S2
P9.4/UCB2CLK/UCA2STE/S3
P9.3/UCA2RXD/UCA2SOMI/S4
P9.2/UCA2TXD/UCA2SIMO/S5
P9.1/UCB2STE/UCA2CLK/S6
P9.0/S7
P8.7/S8
P8.6/UCB1SOMI/UCB1SCL/S9
P8.5/UCB1SIMO/UCB1SDA/S10
DVCC2
DVSS2
P8.4/UCB1CLK/UCA1STE/S11
P8.3/UCA1RXD/UCA1SOMI/S12
P8.2/UCA1TXD/UCA1SIMO/S13
P8.1/UCB1STE/UCA1CLK/S14
P8.0/TB0CLK/S15
P4.7/TB0OUTH/SVMOUT/S16
P4.6/TB0.6/S17
P4.5/TB0.5/S18
P4.4/TB0.4/S19
P4.3/TB0.3/S20
P4.2/TB0.2/S21
P4.1/TB0.1/S22
P5.2/R23
LCDCAP/R33
COM0
P5.3/COM1/S42
P5.4/COM2/S41
P5.5/COM3/S40
P1.0/TA0CLK/ACLK/S39
P1.1/TA0.0/S38
P1.2/TA0.1/S37
P1.3/TA0.2/S36
P1.4/TA0.3/S35
P1.5/TA0.4/S34
P1.6/TA0.1/S33
P1.7/TA0.2/S32
P3.0/TA1CLK/CBOUT/S31
P3.1/TA1.0/S30
P3.2/TA1.1/S29
P3.3/TA1.2/S28
P3.4/TA2CLK/SMCLK/S27
P3.5/TA2.0/S26
P3.6/TA2.1/S25
P3.7/TA2.2/S24
P4.0/TB0.0/S23
DVSS1
VCORE
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P6.4/CB4/A4
P6.5/CB5/A5
P6.6/CB6/A6/DAC0
P6.7/CB7/A7/DAC1
P7.4/CB8/A12
P7.5/CB9/A13
P7.6/CB10/A14/DAC0
P7.7/CB11/A15/DAC1
P5.0/VREF+/VeREF+
P5.1/VREF−/VeREF−
AVCC1
AVSS1
XIN
XOUT
AVSS2
P5.6/ADC12CLK/DMAE0
P2.0/P2MAP0
P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5
P2.6/P2MAP6/R03
P2.7/P2MAP7/LCDREF/R13
DVCC1
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
P6.3/CB3/A3
P6.2/CB2/A2
P6.1/CB1/A1
P6.0/CB0/A0
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK
DVSS3
DVCC3
P5.7/RTCCLK
VBAT
VBAK
P7.3/XT2OUT
P7.2/XT2IN
AVSS3
NC
LDOO
LDOI
PU.1
NC
PU.0
VSSU
Figure 4-1 shows the pinout diagram.
Figure 4-1. PZ S-PQFP-G100 Package
6
Terminal Configuration and Functions
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4.2
SLASEC3A – AUGUST 2016 – REVISED AUGUST 2016
Signal Descriptions
Table 4-1 describes the signals for all device variants and package options.
Table 4-1. Signal Descriptions
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
General-purpose digital I/O
P6.4/CB4/A4
1
I/O
Comparator_B input CB4
Analog input A4 – ADC
General-purpose digital I/O
P6.5/CB5/A5
2
I/O
Comparator_B input CB5
Analog input A5 – ADC
General-purpose digital I/O
Comparator_B input CB6
P6.6/CB6/A6/DAC0
3
I/O
Analog input A6 – ADC
DAC12.0 output
General-purpose digital I/O
Comparator_B input CB7
P6.7/CB7/A7/DAC1
4
I/O
Analog input A7 – ADC
DAC12.1 output
General-purpose digital I/O
P7.4/CB8/A12
5
I/O
Comparator_B input CB8
Analog input A12 –ADC
General-purpose digital I/O
P7.5/CB9/A13
6
I/O
Comparator_B input CB9
Analog input A13 – ADC
General-purpose digital I/O
Comparator_B input CB10
P7.6/CB10/A14/DAC0
7
I/O
Analog input A14 – ADC
DAC12.0 output
General-purpose digital I/O
Comparator_B input CB11
P7.7/CB11/A15/DAC1
8
I/O
Analog input A15 – ADC
DAC12.1 output
General-purpose digital I/O
P5.0/VREF+/VeREF+
9
I/O
Output of reference voltage to the ADC
Input for an external reference voltage to the ADC
General-purpose digital I/O
P5.1/VREF-/VeREF-
10
AVCC1
11
AVSS1
12
XIN
13
I
Input terminal for crystal oscillator XT1
XOUT
14
O
Output terminal of crystal oscillator XT1
AVSS2
15
(1)
I/O
Negative terminal for the ADC's reference voltage for both sources, the internal
reference voltage, or an external applied reference voltage
Analog power supply
Analog ground supply
Analog ground supply
I = input, O = output, N/A = not available on this package offering.
Terminal Configuration and Functions
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Table 4-1. Signal Descriptions (continued)
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
General-purpose digital I/O
P5.6/ADC12CLK/DMAE0
16
I/O
Conversion clock output ADC
DMA external trigger input
General-purpose digital I/O with port interrupt and mappable secondary function
P2.0/P2MAP0
17
I/O
Default mapping: USCI_B0 SPI slave transmit enable; USCI_A0 clock input/output
General-purpose digital I/O with port interrupt and mappable secondary function
P2.1/P2MAP1
18
I/O
Default mapping: USCI_B0 SPI slave in, master out; USCI_B0 I2C data
General-purpose digital I/O with port interrupt and mappable secondary function
P2.2/P2MAP2
19
I/O
Default mapping: USCI_B0 SPI slave out, master in; USCI_B0 I2C clock
General-purpose digital I/O with port interrupt and mappable secondary function
P2.3/P2MAP3
20
I/O
Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave transmit enable
General-purpose digital I/O with port interrupt and mappable secondary function
P2.4/P2MAP4
21
I/O
Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in, master out
General-purpose digital I/O with port interrupt and mappable secondary function
P2.5/P2MAP5
22
I/O
Default mapping: USCI_A0 UART receive data; USCI_A0 slave out, master in
General-purpose digital I/O with port interrupt and mappable secondary function
P2.6/P2MAP6/R03
23
I/O
Default mapping: no secondary function
Input/output port of lowest analog LCD voltage (V5)
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: no secondary function
P2.7/P2MAP7/LCDREF/R13
24
I/O
External reference voltage input for regulated LCD voltage
Input/output port of third most positive analog LCD voltage (V3 or V4)
DVCC1
25
Digital power supply
DVSS1
26
Digital ground supply
27
Regulated core power supply (internal use only, no external current loading)
VCORE
(2)
General-purpose digital I/O
P5.2/R23
28
I/O
Input/output port of second most positive analog LCD voltage (V2)
LCD capacitor connection
LCDCAP/R33
29
I/O
COM0
30
O
Input/output port of most positive analog LCD voltage (V1)
LCD common output COM0 for LCD backplane
General-purpose digital I/O
P5.3/COM1/S42
31
I/O
LCD common output COM1 for LCD backplane
LCD segment output S42
General-purpose digital I/O
P5.4/COM2/S41
32
I/O
LCD common output COM2 for LCD backplane
LCD segment output S41
General-purpose digital I/O
P5.5/COM3/S40
33
I/O
LCD common output COM3 for LCD backplane
LCD segment output S40
(2)
8
VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE.
Terminal Configuration and Functions
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Table 4-1. Signal Descriptions (continued)
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
General-purpose digital I/O with port interrupt
Timer TA0 clock signal TACLK input
P1.0/TA0CLK/ACLK/S39
34
I/O
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
LCD segment output S39
General-purpose digital I/O with port interrupt
Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output
P1.1/TA0.0/S38
35
I/O
BSL transmit output
LCD segment output S38
General-purpose digital I/O with port interrupt
Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output
P1.2/TA0.1/S37
36
I/O
BSL receive input
LCD segment output S37
General-purpose digital I/O with port interrupt
P1.3/TA0.2/S36
37
I/O
Timer TA0 CCR2 capture: CCI2A input, compare: Out2 output
LCD segment output S36
General-purpose digital I/O with port interrupt
P1.4/TA0.3/S35
38
I/O
Timer TA0 CCR3 capture: CCI3A input compare: Out3 output
LCD segment output S35
General-purpose digital I/O with port interrupt
P1.5/TA0.4/S34
39
I/O
Timer TA0 CCR4 capture: CCI4A input, compare: Out4 output
LCD segment output S34
General-purpose digital I/O with port interrupt
P1.6/TA0.1/S33
40
I/O
Timer TA0 CCR1 capture: CCI1B input, compare: Out1 output
LCD segment output S33
General-purpose digital I/O with port interrupt
P1.7/TA0.2/S32
41
I/O
Timer TA0 CCR2 capture: CCI2B input, compare: Out2 output
LCD segment output S32
General-purpose digital I/O with port interrupt
Timer TA1 clock input
P3.0/TA1CLK/CBOUT/S31
42
I/O
Comparator_B output
LCD segment output S31
General-purpose digital I/O with port interrupt
P3.1/TA1.0/S30
43
I/O
Timer TA1 capture CCR0: CCI0A/CCI0B input, compare: Out0 output
LCD segment output S30
General-purpose digital I/O with port interrupt
P3.2/TA1.1/S29
44
I/O
Timer TA1 capture CCR1: CCI1A/CCI1B input, compare: Out1 output
LCD segment output S29
General-purpose digital I/O with port interrupt
P3.3/TA1.2/S28
45
I/O
Timer TA1 capture CCR2: CCI2A/CCI2B input, compare: Out2 output
LCD segment output S28
Terminal Configuration and Functions
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Table 4-1. Signal Descriptions (continued)
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
General-purpose digital I/O with port interrupt
Timer TA2 clock input
P3.4/TA2CLK/SMCLK/S27
46
I/O
SMCLK output
LCD segment output S27
General-purpose digital I/O with port interrupt
P3.5/TA2.0/S26
47
I/O
Timer TA2 capture CCR0: CCI0A/CCI0B input, compare: Out0 output
LCD segment output S26
General-purpose digital I/O with port interrupt
P3.6/TA2.1/S25
48
I/O
Timer TA2 capture CCR1: CCI1A/CCI1B input, compare: Out1 output
LCD segment output S25
General-purpose digital I/O with port interrupt
P3.7/TA2.2/S24
49
I/O
Timer TA2 capture CCR2: CCI2A/CCI2B input, compare: Out2 output
LCD segment output S24
General-purpose digital I/O with port interrupt
P4.0/TB0.0/S23
50
I/O
Timer TB0 capture CCR0: CCI0A/CCI0B input, compare: Out0 output
LCD segment output S23
General-purpose digital I/O with port interrupt
P4.1/TB0.1/S22
51
I/O
Timer TB0 capture CCR1: CCI1A/CCI1B input, compare: Out1 output
LCD segment output S22
General-purpose digital I/O with port interrupt
P4.2/TB0.2/S21
52
I/O
Timer TB0 capture CCR2: CCI2A/CCI2B input, compare: Out2 output
LCD segment output S21
General-purpose digital I/O with port interrupt
P4.3/TB0.3/S20
53
I/O
Timer TB0 capture CCR3: CCI3A/CCI3B input, compare: Out3 output
LCD segment output S20
General-purpose digital I/O with port interrupt
P4.4/TB0.4/S19
54
I/O
Timer TB0 capture CCR4: CCI4A/CCI4B input, compare: Out4 output
LCD segment output S19
General-purpose digital I/O with port interrupt
P4.5/TB0.5/S18
55
I/O
Timer TB0 capture CCR5: CCI5A/CCI5B input, compare: Out5 output
LCD segment output S18
General-purpose digital I/O with port interrupt
P4.6/TB0.6/S17
56
I/O
Timer TB0 capture CCR6: CCI6A/CCI6B input, compare: Out6 output
LCD segment output S17
General-purpose digital I/O with port interrupt
Timer TB0: Switch all PWM outputs high impedance
P4.7/TB0OUTH/SVMOUT/S16
57
I/O
SVM output
LCD segment output S16
General-purpose digital I/O
P8.0/TB0CLK/S15
58
I/O
Timer TB0 clock input
LCD segment output S15
10
Terminal Configuration and Functions
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Table 4-1. Signal Descriptions (continued)
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
General-purpose digital I/O
USCI_B1 SPI slave transmit enable
P8.1/UCB1STE/UCA1CLK/S14
59
I/O
USCI_A1 clock input/output
LCD segment output S14
General-purpose digital I/O
USCI_A1 UART transmit data
P8.2/UCA1TXD/UCA1SIMO/S13
60
I/O
USCI_A1 SPI slave in, master out
LCD segment output S13
General-purpose digital I/O
USCI_A1 UART receive data
P8.3/UCA1RXD/UCA1SOMI/S12
61
I/O
USCI_A1 SPI slave out, master in
LCD segment output S12
General-purpose digital I/O
USCI_B1 clock input/output
P8.4/UCB1CLK/UCA1STE/S11
62
I/O
USCI_A1 SPI slave transmit enable
LCD segment output S11
DVSS2
63
Digital ground supply
DVCC2
64
Digital power supply
General-purpose digital I/O
USCI_B1 SPI slave in, master out
P8.5/UCB1SIMO/UCB1SDA/S10
65
I/O
USCI_B1 I2C data
LCD segment output S10
General-purpose digital I/O
USCI_B1 SPI slave out, master in
P8.6/UCB1SOMI/UCB1SCL/S9
66
I/O
USCI_B1 I2C clock
LCD segment output S9
General-purpose digital I/O
P8.7/S8
67
I/O
LCD segment output S8
General-purpose digital I/O
P9.0/S7
68
I/O
LCD segment output S7
General-purpose digital I/O
USCI_B2 SPI slave transmit enable
P9.1/UCB2STE/UCA2CLK/S6
69
I/O
USCI_A2 clock input/output
LCD segment output S6
General-purpose digital I/O
USCI_A2 UART transmit data
P9.2/UCA2TXD/UCA2SIMO/S5
70
I/O
USCI_A2 SPI slave in, master out
LCD segment output S5
General-purpose digital I/O
USCI_A2 UART receive data
P9.3/UCA2RXD/UCA2SOMI/S4
71
I/O
USCI_A2 SPI slave out, master in
LCD segment output S4
Terminal Configuration and Functions
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Table 4-1. Signal Descriptions (continued)
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
General-purpose digital I/O
USCI_B2 clock input/output
P9.4/UCB2CLK/UCA2STE/S3
72
I/O
USCI_A2 SPI slave transmit enable
LCD segment output S3
General-purpose digital I/O
USCI_B2 SPI slave in, master out
P9.5/UCB2SIMO/UCB2SDA/S2
73
I/O
USCI_B2 I2C data
LCD segment output S2
General-purpose digital I/O
USCI_B2 SPI slave out, master in
P9.6/UCB2SOMI/UCB2SCL/S1
74
I/O
USCI_B2 I2C clock
LCD segment output S1
General-purpose digital I/O
P9.7/S0
75
I/O
VSSU
76
PU.0/DP
77
NC
78
PU.1/DM
79
LDOI
80
LDO input
LDOO
81
LDO output
NC
82
Not connected
AVSS3
83
Analog ground supply
P7.2/XT2IN
84
LCD segment output S0
PU ground supply
I/O
PU control register (Port U is supplied the LDOO rail)
Not connected
I/O
PU control register (Port U is supplied the LDOO rail)
General-purpose digital I/O
I/O
Input terminal for crystal oscillator XT2
General-purpose digital I/O
P7.3/XT2OUT
85
I/O
Output terminal of crystal oscillator XT2
VBAK
86
Capacitor for backup subsystem. Do not load this pin externally. For capacitor values,
see CBAK in Section 5.3.
VBAT
87
Backup supply voltage. If backup voltage is not supplied, connect to DVCC externally.
P5.7/RTCCLK
88
DVCC3
89
Digital power supply
DVSS3
90
Digital ground supply
TEST/SBWTCK
91
General-purpose digital I/O
I/O
RTCCLK output
Test mode pin – select digital I/O on JTAG pins
I
Spy-Bi-Wire input clock
General-purpose digital I/O
PJ.0/TDO
92
I/O
Test data output port
General-purpose digital I/O
PJ.1/TDI/TCLK
93
I/O
Test data input or test clock input
General-purpose digital I/O
PJ.2/TMS
94
I/O
Test mode select
General-purpose digital I/O
PJ.3/TCK
95
I/O
Test clock
12
Terminal Configuration and Functions
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Table 4-1. Signal Descriptions (continued)
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
Reset input active low (3)
RST/NMI/SBWTDIO
96
I/O
Nonmaskable interrupt input
Spy-Bi-Wire data input/output
General-purpose digital I/O
P6.0/CB0/A0
97
I/O
Comparator_B input CB0
Analog input A0 – ADC
General-purpose digital I/O
P6.1/CB1/A1
98
I/O
Comparator_B input CB1
Analog input A1 – ADC
General-purpose digital I/O
P6.2/CB2/A2
99
I/O
Comparator_B input CB2
Analog input A2 – ADC
General-purpose digital I/O
P6.3/CB3/A3
100
I/O
Comparator_B input CB3
Analog input A3 – ADC
Reserved
(3)
N/A
Reserved BGA package balls. TI recommends connecting to ground (DVSS, AVSS).
When this pin is configured as reset, the internal pullup resistor is enabled by default.
Terminal Configuration and Functions
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5 Specifications
5.1
Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted) (1)
Voltage applied at VCC to VSS
Voltage applied to any pin (excluding VCORE, VBUS, V18)
(2)
MIN
MAX
–0.3
4.1
–0.3
VCC + 0.3
Diode current at any device pin
UNIT
V
V
±2
mA
Maximum junction temperature, TJ
–40
105
°C
Storage temperature, Tstg (3)
–55
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2
ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
5.3
Recommended Operating Conditions
Typical values are specified at VCC = 3.3 V and TJ = 25°C (unless otherwise noted)
MIN
PMMCOREVx = 0
NOM
MAX
1.8
3.6
2
3.6
PMMCOREVx = 0, 1, 2
2.2
3.6
PMMCOREVx = 0, 1, 2, 3
2.4
UNIT
VCC
Supply voltage during program execution and flash
programming (AVCC1 = DVCC1 = DVCC2 = DVCC3 =
DVCC = VCC) (1) (2)
VSS
Supply voltage (AVSS1 = AVSS2 = AVSS3 = DVSS1 = DVSS2 = DVSS3 = VSS)
VBAT,RTC
Backup-supply voltage with RTC operational
TJ = –40°C to 105°C
VBAT,MEM
Backup-supply voltage with backup memory retained
TJ = –40°C to 105°C
1.2
3.6
V
TJ
Operating junction temperature
T version
–40
105
°C
CBAK
Capacitance at pin VBAK
10
nF
Capacitor at VCORE
CDVCC /
CVCORE
Capacitor ratio of DVCC to VCORE
(2)
(3)
14
1.7
1
V
3.6
0
(3)
CVCORE
(1)
PMMCOREVx = 0, 1
V
3.6
4.7
470
V
nF
10
TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the Table 5-11 threshold parameters for
the exact values and further details.
A capacitor tolerance of ±20% or better is required.
Specifications
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Recommended Operating Conditions (continued)
Typical values are specified at VCC = 3.3 V and TJ = 25°C (unless otherwise noted)
MIN
fSYSTEM
(4)
(5)
Processor frequency (maximum MCLK frequency) (4) (5)
(see Figure 5-1)
NOM
MAX
PMMCOREVx = 0,
1.8 V ≤ VCC ≤ 3.6 V
(default condition)
0
8
PMMCOREVx = 1,
2 V ≤ VCC ≤ 3.6 V
0
12
PMMCOREVx = 2,
2.2 V ≤ VCC ≤ 3.6 V
0
16
PMMCOREVx = 3,
2.4 V ≤ VCC ≤ 3.6 V
0
20
UNIT
MHz
The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the
specified maximum frequency.
Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
25
System Frequency - MHz
20
3
16
2
2, 3
1
1, 2
1, 2, 3
0, 1
0, 1, 2
0, 1, 2, 3
12
8
0
0
1.8
2.0
2.2
2.4
3.6
Supply Voltage - V
NOTE: The numbers within the fields denote the supported PMMCOREVx settings.
Figure 5-1. Frequency vs Supply Voltage
Specifications
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Active Mode Supply Current Into VCC Excluding External Current
over recommended operating junction temperature (unless otherwise noted) (1)
(2) (3)
FREQUENCY (fDCO = fMCLK = fSMCLK)
PARAMETER
IAM,
IAM,
(1)
(2)
(3)
EXECUTION
MEMORY
VCC
Flash
Flash
3V
RAM
RAM
3V
PMMCOREVx
1 MHz
8 MHz
12 MHz
TYP
MAX
TYP
MAX
0
0.36
0.45
2.4
2.7
1
0.41
2
0.46
3
0.51
0
0.18
MAX
2.7
4.0
4.4
2.9
4.3
1
0.20
1.2
1.7
2
0.22
1.3
2.0
3
0.23
1.4
2.2
3.1
0.25
20 MHz
TYP
4.5
1.0
TYP
mA
7.4
1.3
1.9
mA
3.6
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
Characterized with program executing typical data processing.
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0.
5.5
Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted) (1)
PARAMETER
ILPM0,1MHz
Low-power mode 0 (3)
(4)
ILPM2
Low-power mode 2 (5)
(4)
ILPM3,XT1LF
(1)
(2)
(3)
(4)
(5)
(6)
(7)
16
60°C
105°C
2.2 V
0
69
73
95
79
101
135
3V
3
79
83
120
87
116
155
2.2 V
0
6.1
6.7
9.0
8.0
22
40
3V
3
6.5
7.1
9.5
8.5
24
42
0
1.5
2.0
3.3
3.3
18
34
1
1.7
2.2
3.6
8.5
2
1.9
2.4
3.8
18.7
0
1.8
2.2
3.6
18.3
1
1.9
2.4
3.8
18.7
2
2.1
2.6
4.0
18.8
3
2.1
2.6
4.2
4.0
19.4
37
0
1.0
1.3
2.7
2.7
17.2
34
1
1.1
1.5
2.8
17.5
2
1.1
1.6
2.9
17.6
3
1.1
1.6
2.9
18.2
3V
ILPM3,VLO,
25°C
PMMCOREVx
Low-power mode 3,
crystal mode (6) (4)
Low-power mode 3,
VLO mode, Watchdog
enabled (7) (4)
–40°C
(2)
VCC
2.2 V
WDT
UNIT
MAX
3V
TYP
MAX
TYP
MAX
3.5
3.2
TYP
MAX
TYP
MAX
35
UNIT
µA
µA
µA
µA
35
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance are chosen to closely match the required 9 pF.
Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz
Current for brownout included. Low-side supervisor and monitors disabled (SVSL, SVML). High-side supervisor and monitor disabled
(SVSH, SVMH). RAM retention enabled.
Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low frequency crystal operation
(XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz, DCO
setting = 1 MHz operation, DCO bias generator enabled.
Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low frequency crystal operation
(XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
Current for watchdog timer clocked by VLO included.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = fMCLK = fSMCLK = fDCO = 0 MHz
Specifications
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Low-Power Mode Supply Currents (Into VCC) Excluding External Current (continued)
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)(1) (2)
PARAMETER
ILPM4
Low-power mode 4 (8)
VCC
(4)
3V
PMMCOREVx
–40°C
TYP
MAX
25°C
TYP
0
0.9
1.3
1
1.0
2
1.0
3
1.0
1.4
60°C
MAX
2.5
TYP
MAX
105°C
TYP
MAX
2.5
17.1
1.3
2.6
17.3
1.4
2.7
17.5
2.7
18
36
3.1
UNIT
34
µA
Low-power mode 3.5
ILPM3.5,RTC, (LPM3.5) current with
active RTC into primary
VCC
supply pin DVCC (9)
3V
0.5
1.25
2.3
µA
Low-power mode 3.5
ILPM3.5,RTC, (LPM3.5) current with
active RTC into backup
VBAT
supply pin VBAT (10)
3V
0.6
0.78
1.3
µA
Total Low-power mode
3.5 (LPM3.5) current
with active RTC (11)
3V
1.0
1.1
1.2
1.93
3.3
µA
Low-power mode 4.5 (12)
3V
0.4
0.45
0.5
1.21
2.4
µA
ILPM3.5,RTC,
TOT
ILPM4.5
0.6
(8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
(9) VVBAT = VCC - 0.2 V, fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active
(10) VVBAT = VCC - 0.2 V, fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active, no
current drawn on VBAK
(11) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active, no current drawn on VBAK
(12) Internal regulator disabled. No data retention.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
Specifications
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Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted) (1) (2)
TEMPERATURE (TJ)
PARAMETER
VCC
PMMCOREVx
–40°C
TYP
ILPM3 LCD,
int. bias
Low-power mode 3
(LPM3) current, LCD 4mux mode, internal
biasing, charge pump
disabled (3) (4)
3V
2.2 V
ILPM3
LCD,CP
(1)
(2)
(3)
(4)
(5)
18
Low-power mode 3
(LPM3) current, LCD 4mux mode, internal
biasing, charge pump
enabled (3) (5)
3V
MAX
25°C
TYP
60°C
MAX
TYP
105°C
TYP
0
2.7
3.3
4.7
18.3
1
2.9
3.5
5.0
18.7
2
3.0
3.7
5.2
19
3
3.1
3.7
5.2
19.3
0
3.6
1
3.7
2
4.0
0
3.5
1
3.7
2
3.8
3
3.9
4.8
MAX
5.3
UNIT
MAX
35
µA
37
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance are chosen to closely match the required 9 pF.
Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low frequency crystal operation
(XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
Current for brownout included. Low-side supervisor (SVSL) and low-side monitor (SVML) disabled. High-side supervisor (SVSH) and
high-side monitor (SVMH) disabled. RAM retention enabled.
LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump
disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.
LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge pump
enabled), VLCDx = 1000 (VLCD = 3 V, typical), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.
Specifications
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Schmitt-Trigger Inputs – General-Purpose I/O (1)
5.7
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup or pulldown resistor (2)
For pullup: VIN = VSS
For pulldown: VIN = VCC
CI
Input capacitance
VIN = VSS or VCC
(1)
(2)
VCC
MIN
TYP
1.8 V
0.80
1.40
3V
1.50
2.10
1.8 V
0.45
1.00
3V
0.75
1.65
1.8 V
0.3
0.8
3V
0.4
1.0
20
35
MAX
50
5
UNIT
V
V
V
kΩ
pF
The same parametrics apply to the clock input pin when the crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).
Also applies to RST pin when pullup or pulldown resistor is enabled.
5.8
Leakage Current – General-Purpose I/O
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
Ilkg(Px.y)
(1)
(2)
5.9
TEST CONDITIONS
VCC
(1) (2)
High-impedance leakage current
MIN
1.8 V, 3 V
MAX
UNIT
±50
nA
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
Outputs – General-Purpose I/O (Full Drive Strength)
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –3 mA (1)
VOH
High-level output voltage
I(OHmax) = –10 mA (2)
I(OHmax) = –5 mA
I(OLmax) = 3 mA (1)
Low-level output voltage
I(OLmax) = 10 mA (2)
I(OLmax) = 5 mA
(2)
3V
1.8 V
(1)
I(OLmax) = 15 mA (2)
(1)
1.8 V
(1)
I(OHmax) = –15 mA (2)
VOL
VCC
3V
MIN
MAX
VCC – 0.25
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.60
VCC
VSS
VSS + 0.25
VSS
VSS + 0.60
VSS
VSS + 0.25
VSS
VSS + 0.60
UNIT
V
V
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
5.10 Outputs – General-Purpose I/O (Reduced Drive Strength)
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
I(OHmax) = –1 mA (2)
VOH
High-level output voltage
I(OHmax) = –3 mA (3)
I(OHmax) = –2 mA (2)
I(OHmax) = –6 mA (3)
(1)
(2)
(3)
VCC
1.8 V
3V
MIN
MAX
VCC – 0.25
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.60
VCC
UNIT
V
Selecting reduced drive strength may reduce EMI.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage
drop specified.
Specifications
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Outputs – General-Purpose I/O (Reduced Drive Strength) (continued)
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
I(OLmax) = 1 mA (2)
VOL
1.8 V
I(OLmax) = 3 mA (3)
Low-level output voltage
I(OLmax) = 2 mA
(2)
3V
I(OLmax) = 6 mA (3)
MIN
MAX
VSS
VSS + 0.25
VSS
VSS + 0.60
VSS
VSS + 0.25
VSS
VSS + 0.60
UNIT
V
5.11 Thermal Resistance Characteristics for PZ Package
VALUE
UNIT
θJA
Junction-to-ambient thermal resistance, still air (1)
PARAMETER
QFP (PZ)
122
°C/W
θJC(TOP)
Junction-to-case (top) thermal resistance (2)
QFP (PZ)
83
°C/W
θJB
Junction-to-board thermal resistance (3)
QFP (PZ)
98
°C/W
(1)
(2)
(3)
20
PACKAGE
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
Specifications
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5.12 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
8.0
IOL – Typical Low-Level Output Current – mA
IOL – Typical Low-Level Output Current – mA
25.0
TJ = 25°C
20.0
TJ = 105°C
15.0
10.0
5.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
6.0
4.0
3.0
2.0
1.0
0.0
0.0
3.5
1.5
2.0
0.0
IOH – Typical High-Level Output Current – mA
IOH – Typical High-Level Output Current – mA
1.0
Figure 5-3. Typical Low-Level Output Current vs Low-Level
Output Voltage
0.0
−5.0
−10.0
−25.0
0.0
0.5
VOL – Low-Level Output Voltage – V
VCC = 1.8 V
Figure 5-2. Typical Low-Level Output Current vs Low-Level
Output Voltage
−20.0
TJ = 105°C
5.0
VOL – Low-Level Output Voltage – V
VCC = 3 V
−15.0
TJ = 25°C
7.0
TJ = 105°C
TJ = 25°C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOH – High-Level Output Voltage – V
VCC = 3 V
Figure 5-4. Typical High-Level Output Current vs High-Level
Output Voltage
−1.0
−2.0
−3.0
−4.0
−5.0
−6.0
TJ = 105°C
TJ = 25°C
−7.0
−8.0
0.0
0.5
1.0
1.5
VOH – High-Level Output Voltage – V
VCC = 1.8 V
2.0
Figure 5-5. Typical High-Level Output Current vs High-Level
Output Voltage
Specifications
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5.13 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
24
TJ = 25°C
55.0
IOL – Typical Low-Level Output Current – mA
IOL – Typical Low-Level Output Current – mA
60.0
50.0
TJ = 105°C
45.0
40.0
35.0
30.0
25.0
20.0
15.0
10.0
TJ = 25°C
20
16
12
8
4
5.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.0
3.5
Figure 5-6. Typical Low-Level Output Current vs Low-Level
Output Voltage
IOH – Typical High-Level Output Current – mA
IOH – Typical High-Level Output Current – mA
1.5
2.0
0
−5.0
−10.0
−15.0
−20.0
−25.0
−30.0
−35.0
−40.0
−45.0
TJ = 105°C
−55.0
−60.0
0.0
1.0
Figure 5-7. Typical Low-Level Output Current vs Low-Level
Output Voltage
0.0
−50.0
0.5
VOL – Low-Level Output Voltage – V
VCC = 1.8 V
VOL – Low-Level Output Voltage – V
VCC = 3 V
TJ = 25°C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOH – High-Level Output Voltage – V
VCC = 3 V
Figure 5-8. Typical High-Level Output Current vs High-Level
Output Voltage
22
TJ = 105°C
−4
−8
−12
TJ = 105°C
−16
TJ = 25°C
−20
0.0
0.5
1.0
1.5
2.0
VOH – High-Level Output Voltage – V
VCC = 1.8 V
Figure 5-9. Typical High-Level Output Current vs High-Level
Output Voltage
Specifications
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5.14 Timing and Switching Characteristics
5.14.1 Power Supply Sequencing
TI recommends powering the AVCC and DVCC pins from the same source. At a minimum, during power
up, power down, and device operation, the voltage difference between AVCC and DVCC must not exceed
the limits specified in the Absolute Maximum Ratings section. Exceeding the specified limits may cause
malfunction of the device including erroneous writes to RAM and FRAM.
Table 5-1. PMM, Brownout Reset (BOR)
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V(DVCC_BOR_IT–)
BORH on voltage, DVCC falling level
| dDVCC/dt | < 3 V/s
V(DVCC_BOR_IT+)
BORH off voltage, DVCC rising level
| dDVCC/dt | < 3 V/s
V(DVCC_BOR_hys)
BORH hysteresis
tRESET
Pulse duration required at RST/NMI pin to accept a reset
MIN
0.80
TYP
1.30
60
MAX
UNIT
1.45
V
1.50
V
250
mV
2
µs
5.14.2 Clock Specifications
Table 5-2. Inputs – Ports P1, P2, P3, and P4 (1)
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
t(int)
(1)
(2)
PARAMETER
TEST CONDITIONS
VCC
External interrupt timing (2)
Port P1, P2, P3, P4: P1.x to P4.x, External trigger pulse
duration to set interrupt flag
2.2 V, 3 V
MIN
MAX
20
UNIT
ns
Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int).
Table 5-3. Output Frequency – Ports P1, P2, and P3
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
fPx.y
fPort_CLK
(1)
(2)
(3)
TEST CONDITIONS
Port output frequency
(with load)
P3.4/TA2CLK/SMCLK/S27,
CL = 20 pF, RL = 1 kΩ (1) or 3.2 kΩ (2)
Clock output frequency
P1.0/TA0CLK/ACLK/S39,
P3.4/TA2CLK/SMCLK/S27,
P2.0/P2MAP0 (P2MAP0 = PM_MCLK),
CL = 20 pF (3)
(3)
MIN
MAX
VCC = 1.8 V,
PMMCOREVx = 0
8
VCC = 3 V,
PMMCOREVx = 3
20
VCC = 1.8 V,
PMMCOREVx = 0
8
VCC = 3 V,
PMMCOREVx = 3
20
UNIT
MHz
MHz
Full drive strength of port: A resistive divider with 2 × 0.5 kΩ between VCC and VSS is used as load. The output is connected to the
center tap of the divider.
Reduced drive strength of port: A resistive divider with 2 × 1.6 kΩ between VCC and VSS is used as load. The output is connected to the
center tap of the divider.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
Specifications
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Table 5-4. Crystal Oscillator, XT1, Low-Frequency Mode (1)
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1, TJ = 25°C
ΔIDVCC,LF
Differential XT1 oscillator
crystal current consumption fOSC = 32768 Hz, XTS = 0,
from lowest drive setting,
XT1BYPASS = 0, XT1DRIVEx = 2, TJ = 25°C
LF mode
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3, TJ = 25°C
fXT1,LF0
XT1 oscillator crystal
frequency, LF mode
XTS = 0, XT1BYPASS = 0
fXT1,LF,SW
XT1 oscillator logic-level
square-wave input
frequency, LF mode
XTS = 0, XT1BYPASS = 1 (2)
OALF
Oscillation allowance for
LF crystals (4)
Integrated effective load
capacitance, LF mode (5)
3V
0.170
0.290
(3)
XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,LF = 32768 Hz, CL,eff = 12 pF, TJ = 25°C
10
fFault,LF
tSTART,LF
kΩ
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
24
1
XTS = 0, XCAPx = 3
12.0
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TJ = 25°C, CL,eff = 12 pF
kHz
300
8.5
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
TJ = 25°C, CL,eff = 6 pF
50
210
5.5
XTS = 0 (8)
Hz
3V
XTS = 0, XCAPx = 2
Oscillator fault frequency,
LF mode (7)
Start-up time, LF mode
32.768
XTS = 0, XCAPx = 1
XTS = 0, Measured at ACLK,
fXT1,LF = 32768 Hz
UNIT
µA
32768
XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,LF = 32768 Hz, CL,eff = 6 pF, TJ = 25°C
Duty cycle, LF mode
MAX
0.075
XTS = 0, XCAPx = 0 (6)
CL,eff
TYP
pF
30%
70%
10
10000
Hz
1000
3V
ms
500
To improve EMI on the XT1 oscillator, the following guidelines should be observed.
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
When XT1BYPASS is set, XT1 circuit is automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-trigger Inputs section of this data sheet.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
• For XT1DRIVEx = 0, CL,eff ≤ 6 pF.
• For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF.
• For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF.
• For XT1DRIVEx = 3, CL,eff ≥ 6 pF.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Specifications
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Table 5-5. Crystal Oscillator, XT2
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
VCC
MIN
fOSC = 4 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 0, TJ = 25°C
IDVCC,XT2
fOSC = 12 MHz, XT2OFF = 0,
XT2 oscillator crystal current XT2BYPASS = 0, XT2DRIVEx = 1, TJ = 25°C
consumption
fOSC = 20 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 2, TJ = 25°C
(2)
TYP
MAX
UNIT
200
260
3V
µA
325
fOSC = 32 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 3, TJ = 25°C
450
fXT2,HF0
XT2 oscillator crystal
frequency, mode 0
XT2DRIVEx = 0, XT2BYPASS = 0 (3)
4
8
MHz
fXT2,HF1
XT2 oscillator crystal
frequency, mode 1
XT2DRIVEx = 1, XT2BYPASS = 0 (3)
8
16
MHz
fXT2,HF2
XT2 oscillator crystal
frequency, mode 2
XT2DRIVEx = 2, XT2BYPASS = 0 (3)
16
24
MHz
fXT2,HF3
XT2 oscillator crystal
frequency, mode 3
XT2DRIVEx = 3, XT2BYPASS = 0 (3)
24
32
MHz
fXT2,HF,SW
XT2 oscillator logic-level
square-wave input
frequency
XT2BYPASS = 1 (4)
0.7
32
MHz
(3)
XT2DRIVEx = 0, XT2BYPASS = 0,
fXT2,HF0 = 6 MHz, CL,eff = 15 pF, TJ = 25°C
OAHF
XT2DRIVEx = 1, XT2BYPASS = 0,
fXT2,HF1 = 12 MHz, CL,eff = 15 pF, TJ = 25°C
Oscillation allowance for
HF crystals (5)
XT2DRIVEx = 2, XT2BYPASS = 0,
fXT2,HF2 = 20 MHz, CL,eff = 15 pF, TJ = 25°C
450
320
Ω
3V
200
XT2DRIVEx = 3, XT2BYPASS = 0,
fXT2,HF3 = 32 MHz, CL,eff = 15 pF, TJ = 25°C
tSTART,HF
CL,eff
fOSC = 6 MHz, XT2BYPASS = 0, XT2DRIVEx = 0,
TJ = 25°C, CL,eff = 15 pF
Start-up time
Integrated effective load
capacitance, HF mode (6)
fOSC = 20 MHz, XT2BYPASS = 0, XT2DRIVEx = 3,
TJ = 25°C, CL,eff = 15 pF
fFault,HF
(3)
(4)
(5)
(6)
(7)
(8)
Oscillator fault frequency
0.5
3V
ms
0.3
1
(1)
Duty cycle
(1)
(2)
200
Measured at ACLK, fXT2,HF2 = 20 MHz
(7)
XT2BYPASS = 1
(8)
40%
30
50%
pF
60%
300
kHz
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
To improve EMI on the XT2 oscillator the following guidelines should be observed.
• Keep the traces between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.
• Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
Maximum frequency of operation of the entire device cannot be exceeded.
When XT2BYPASS is set, the XT2 circuit is automatically powered down.
Oscillation allowance is based on a safety factor of 5 for recommended crystals.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Specifications
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Table 5-6. Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
fVLO
TEST CONDITIONS
VLO frequency
dfVLO/dT
Measured at ACLK
VLO frequency temperature drift
Duty cycle
(1)
(2)
MIN
TYP
MAX
6
9.4
14
(1)
1.8 V to 3.6 V
0.5
Measured at ACLK (2)
1.8 V to 3.6 V
4
Measured at ACLK
1.8 V to 3.6 V
Measured at ACLK
dfVLO/dVCC VLO frequency supply voltage drift
VCC
1.8 V to 3.6 V
40%
50%
UNIT
kHz
%/°C
%/V
60%
Calculated using the box method: (MAX(–40°C to 105°C) – MIN(–40°C to 105°C)) / MIN(–40°C to 105°C) / (105°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
Table 5-7. Internal Reference, Low-Frequency Oscillator (REFO)
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
REFO oscillator current
consumption
TJ = 25°C
1.8 V to 3.6 V
3
µA
REFO frequency calibrated
Measured at ACLK
1.8 V to 3.6 V
32768
Hz
REFO absolute tolerance
calibrated
Full temperature range
1.8 V to 3.6 V
dfREFO/dT
REFO frequency temperature drift
Measured at ACLK (1)
1.8 V to 3.6 V
0.01
%/°C
dfREFO/dVCC
REFO frequency supply voltage
drift
Measured at ACLK (2)
1.8 V to 3.6 V
1.0
%/V
Duty cycle
Measured at ACLK
1.8 V to 3.6 V
REFO start-up time
40%/60% duty cycle
1.8 V to 3.6 V
IREFO
fREFO
tSTART
(1)
(2)
26
TJ = 25°C
±3.5%
3V
±1.5%
40%
50%
60%
25
µs
Calculated using the box method: (MAX(–40°C to 105°C) – MIN(–40°C to 105°C)) / MIN(–40°C to 105°C) / (105°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
Specifications
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Table 5-8. DCO Frequency
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
fDCO(0,0)
TEST CONDITIONS
DCO frequency (0, 0) (1)
(1)
MAX
UNIT
DCORSELx = 0, DCOx = 0, MODx = 0
0.07
MIN
TYP
0.20
MHz
fDCO(0,31)
DCO frequency (0, 31)
DCORSELx = 0, DCOx = 31, MODx = 0
0.70
1.70
MHz
fDCO(1,0)
DCO frequency (1, 0) (1)
DCORSELx = 1, DCOx = 0, MODx = 0
0.15
0.36
MHz
fDCO(1,31)
DCO frequency (1, 31) (1)
DCORSELx = 1, DCOx = 31, MODx = 0
1.47
3.45
MHz
fDCO(2,0)
DCO frequency (2, 0) (1)
DCORSELx = 2, DCOx = 0, MODx = 0
0.32
0.75
MHz
(1)
fDCO(2,31)
DCO frequency (2, 31)
DCORSELx = 2, DCOx = 31, MODx = 0
3.17
7.38
MHz
fDCO(3,0)
DCO frequency (3, 0) (1)
DCORSELx = 3, DCOx = 0, MODx = 0
0.64
1.51
MHz
fDCO(3,31)
DCO frequency (3, 31) (1)
DCORSELx = 3, DCOx = 31, MODx = 0
6.07
14.0
MHz
(1)
fDCO(4,0)
DCO frequency (4, 0)
DCORSELx = 4, DCOx = 0, MODx = 0
1.3
3.2
MHz
fDCO(4,31)
DCO frequency (4, 31) (1)
DCORSELx = 4, DCOx = 31, MODx = 0
12.3
28.2
MHz
fDCO(5,0)
DCO frequency (5, 0) (1)
DCORSELx = 5, DCOx = 0, MODx = 0
2.5
6.0
MHz
(1)
fDCO(5,31)
DCO frequency (5, 31)
DCORSELx = 5, DCOx = 31, MODx = 0
23.7
54.1
MHz
fDCO(6,0)
DCO frequency (6, 0) (1)
DCORSELx = 6, DCOx = 0, MODx = 0
4.6
10.7
MHz
fDCO(6,31)
DCO frequency (6, 31) (1)
DCORSELx = 6, DCOx = 31, MODx = 0
39.0
88.0
MHz
fDCO(7,0)
DCO frequency (7, 0) (1)
DCORSELx = 7, DCOx = 0, MODx = 0
8.5
19.6
MHz
(1)
fDCO(7,31)
DCO frequency (7, 31)
DCORSELx = 7, DCOx = 31, MODx = 0
60
135
MHz
SDCORSEL
Frequency step between range
DCORSEL and DCORSEL + 1
SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO)
1.2
2.3
ratio
SDCO
Frequency step between tap
DCO and DCO + 1
SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO)
1.02
1.12
ratio
40%
Duty cycle
Measured at SMCLK
dfDCO/dT
DCO frequency temperature drift
fDCO = 1 MHz,
0.1
%/°C
dfDCO/dVCC
DCO frequency voltage drift
fDCO = 1 MHz
1.9
%/V
(1)
50%
60%
When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within the
range of fDCO(n, 0),MAX ≤ fDCO ≤ fDCO(n, 31),MIN, where fDCO(n, 0),MAX represents the maximum frequency specified for the DCO frequency,
range n, tap 0 (DCOx = 0) and fDCO(n,31),MIN represents the minimum frequency specified for the DCO frequency, range n, tap 31
(DCOx = 31). This ensures that the target DCO frequency resides within the range selected. It should also be noted that if the actual
fDCO frequency for the selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the
selected range is at its minimum or maximum tap setting.
100
VCC = 3.0 V
TA = 25°C
fDCO – MHz
10
DCOx = 31
1
0.1
DCOx = 0
0
1
2
3
4
5
6
7
DCORSEL
Figure 5-10. Typical DCO Frequency
Specifications
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Table 5-9. Wake-Up Times From Low-Power Modes
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
tWAKE-UP-FAST
TEST CONDITIONS
Wake-up time from LPM2, LPM3, or LPM4
to active mode (1)
TYP
MAX
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 1,
fMCLK ≥ 4.0 MHz
MIN
3
6.5
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 1,
1 MHz < fMCLK < 4.0 MHz
4
8.0
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 0
150
165
UNIT
µs
tWAKE-UP-SLOW
Wake-up time from LPM2, LPM3 or LPM4
to active mode (2)
tWAKE-UP LPM5
Wake-up time from LPM3.5 or LPM4.5 to
active mode (3)
2
3
ms
tWAKE-UP-RESET
Wake-up time from RST or BOR event to
active mode (3)
2
3
ms
(1)
(2)
(3)
This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance
mode of the low-side supervisor (SVSL) and low-side monitor (SVML). Fastest wake-up times are possible with SVSL and SVML in fullperformance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVSL and SVML while
operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx
and MSP430x6xx Family User's Guide (SLAU208).
This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance
mode of the low-side supervisor (SVSL) and low-side monitor (SVML). In this case, the SVSL and SVML are in normal mode (low
current) mode when operating in AM, LPM0, and LPM1. Various options are available for SVSL and SVML while operating in LPM2,
LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx
Family User's Guide (SLAU208).
This value represents the time from the wake-up event to the reset vector execution.
5.14.3 Peripherals
Table 5-10. PMM, Core Voltage
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCORE3(AM)
Core voltage, active mode,
PMMCOREV = 3
2.4 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 21 mA
1.90
V
VCORE2(AM)
Core voltage, active mode,
PMMCOREV = 2
2.2 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 21 mA
1.80
V
VCORE1(AM)
Core voltage, active mode,
PMMCOREV = 1
2 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 17 mA
1.60
V
VCORE0(AM)
Core voltage, active mode,
PMMCOREV = 0
1.8 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 13 mA
1.40
V
VCORE3(LPM)
Core voltage, low-current mode,
2.4 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA
PMMCOREV = 3
1.94
V
VCORE2(LPM)
Core voltage, low-current mode,
2.2 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA
PMMCOREV = 2
1.84
V
VCORE1(LPM)
Core voltage, low-current mode,
2 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA
PMMCOREV = 1
1.64
V
VCORE0(LPM)
Core voltage, low-current mode,
1.8 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA
PMMCOREV = 0
1.44
V
28
Specifications
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Table 5-11. PMM, SVS High Side
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVSHE = 0, DVCC = 3.6 V
I(SVSH)
SVS current consumption
V(SVSH_IT+)
SVSH on voltage level (1)
SVSH off voltage level (1)
tpd(SVSH)
SVSH propagation delay
t(SVSH)
SVSH on or off delay time
dVDVCC/dt
DVCC rise time
(1)
MAX
0
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0
2.0
µA
SVSHE = 1, SVSHRVL = 0
1.59
1.64
1.69
SVSHE = 1, SVSHRVL = 1
1.79
1.84
1.91
SVSHE = 1, SVSHRVL = 2
1.98
2.04
2.11
SVSHE = 1, SVSHRVL = 3
2.10
2.16
2.23
SVSHE = 1, SVSMHRRL = 0
1.62
1.74
1.81
SVSHE = 1, SVSMHRRL = 1
1.88
1.94
2.01
SVSHE = 1, SVSMHRRL = 2
2.07
2.14
2.21
SVSHE = 1, SVSMHRRL = 3
2.20
2.26
2.33
SVSHE = 1, SVSMHRRL = 4
2.32
2.40
2.48
SVSHE = 1, SVSMHRRL = 5
2.56
2.70
2.84
SVSHE = 1, SVSMHRRL = 6
2.85
3.00
3.15
SVSHE = 1, SVSMHRRL = 7
2.85
3.00
3.15
SVSHE = 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1
2.5
SVSHE = 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0
20
SVSHE = 0→1, SVSHFP = 1
12.5
SVSHE = 0→1, SVSHFP = 0
100
0
UNIT
nA
200
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1
V(SVSH_IT–)
TYP
V
V
µs
µs
1000
V/s
The SVSH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings and usage.
Table 5-12. PMM, SVM High Side
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVMHE = 0, DVCC = 3.6 V
I(SVMH)
V(SVMH)
SVMH current consumption
SVMH on or off voltage level
(1)
SVMH propagation delay
t(SVMH)
SVMH on or off delay time
(1)
MAX
0
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 0
200
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1
2.0
UNIT
nA
µA
SVMHE = 1, SVSMHRRL = 0
1.65
1.74
1.86
SVMHE = 1, SVSMHRRL = 1
1.85
1.94
2.02
SVMHE = 1, SVSMHRRL = 2
2.02
2.14
2.22
SVMHE = 1, SVSMHRRL = 3
2.18
2.26
2.35
SVMHE = 1, SVSMHRRL = 4
2.32
2.40
2.48
SVMHE = 1, SVSMHRRL = 5
2.56
2.70
2.84
SVMHE = 1, SVSMHRRL = 6
2.85
3.00
3.15
SVMHE = 1, SVSMHRRL = 7
2.85
3.00
3.15
SVMHE = 1, SVMHOVPE = 1
tpd(SVMH)
TYP
V
3.75
SVMHE = 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1
2.5
SVMHE = 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0
20
SVMHE = 0→1, SVSMFP = 1
12.5
SVMHE = 0→1, SVMHFP = 0
100
µs
µs
The SVMH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings and usage.
Specifications
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Table 5-13. PMM, SVS Low Side
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVSLE = 0, PMMCOREV = 2
I(SVSL)
SVSL current consumption
tpd(SVSL)
SVSL propagation delay
t(SVSL)
SVSL on or off delay time
TYP
MAX
0
SVSLE = 1, PMMCOREV = 2, SVSLFP = 0
200
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1
2.0
SVSLE = 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1
2.5
SVSLE = 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0
20
SVSLE = 0→1, SVSLFP = 1
12.5
SVSLE = 0→1, SVSLFP = 0
100
UNIT
nA
µA
µs
µs
Table 5-14. PMM, SVM Low Side
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVMLE = 0, PMMCOREV = 2
I(SVML)
SVML current consumption
tpd(SVML)
SVML propagation delay
t(SVML)
SVML on or off delay time
30
TYP
0
SVMLE = 1, PMMCOREV = 2, SVMLFP = 0
200
SVMLE = 1, PMMCOREV = 2, SVMLFP = 1
2.0
SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1
2.5
SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0
20
SVMLE = 0→1, SVMLFP = 1
12.5
SVMLE = 0→1, SVMLFP = 0
100
Specifications
MAX
UNIT
nA
µA
µs
µs
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Table 5-15. Timer_A – Timers TA0, TA1, and TA2
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTA
Timer_A input clock frequency
Internal: SMCLK, ACLK
External: TACLK
Duty cycle = 50% ±10%
tTA,cap
Timer_A capture timing
All capture inputs, Minimum pulse duration
required for capture
VCC
1.8 V, 3 V
1.8 V, 3 V
MIN
MAX
UNIT
20
MHz
20
ns
Table 5-16. Timer_B – Timer TB0
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTB
Timer_B input clock frequency
Internal: SMCLK, ACLK
External: TBCLK
Duty cycle = 50% ±10%
tTB,cap
Timer_B capture timing
All capture inputs, Minimum pulse duration
required for capture
VCC
1.8 V, 3 V
1.8 V, 3 V
MIN
MAX
UNIT
20
MHz
20
ns
Table 5-17. Battery Backup
over operating junction temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VBAT = 1.7 V,
DVCC not connected,
RTC running
IVBAT
Current into VBAT terminal if no
primary battery is connected
VBAT = 2.2 V,
DVCC not connected,
RTC running
VBAT = 3 V,
DVCC not connected,
RTC running
VCC
MIN
TJ = –40°C
0.43
TJ = 25°C
0.52
TJ = 60°C
0.58
TJ = 105°C
0.66
TJ = –40°C
0.50
TJ = 25°C
0.59
TJ = 60°C
0.64
TJ = 105°C
0.72
TJ = –40°C
0.68
TJ = 25°C
0.75
TJ = 60°C
0.79
TJ = 105°C
Switch-over level (VCC to VBAT)
CVCC = 4.7 µF
RON_VBAT
On-resistance of switch between
VBAT = 1.8 V
VBAT and VBAK
VBAT3
VBAT to ADC input channel 12:
VBAT divided, VBAT3 ≈ VBAT/3
tSample,
µA
SVSHRL = 0
1.59
1.69
SVSHRL = 1
1.79
1.91
SVSHRL = 2
1.98
2.11
SVSHRL = 3
2.10
2.23
0V
0.35
1
1.8 V
0.6
±5%
3V
1.0
±5%
3.6 V
1.2
±5%
VBAT to ADC: Sampling time
required if VBAT3 selected
ADC12ON = 1,
Error of conversion result ≤ 2 LSB
1000
VCHVx
Charger end voltage
CHVx = 2
2.65
Charge limiting resistor
2.7
2.9
5.2
CHCx = 2
10.2
CHCx = 3
20
Specifications
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kΩ
V
ns
CHCx = 1
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UNIT
VSVSH_IT-
VBAT3
RCHARGE
MAX
0.87
General
VSWITCH
TYP
V
kΩ
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Table 5-18. USCI (UART Mode)
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
fUSCI
USCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
tτ
UART receive deglitch time (1)
(1)
TEST CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ±10%
MAX
UNIT
fSYSTEM
MHz
1
MHz
2.2 V
50
600
3V
50
600
ns
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To make sure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
Table 5-19. USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted) (1)
(see Figure 5-11 and )
PARAMETER
fUSCI
USCI input clock frequency
TEST CONDITIONS
PMMCOREV = 0
tSU,MI
SOMI input data setup time
PMMCOREV = 3
PMMCOREV = 0
tHD,MI
SOMI input data hold time
PMMCOREV = 3
tVALID,MO
SIMO output data valid time (2)
(2)
(3)
32
1.8 V
55
3V
38
2.4 V
30
3V
25
1.8 V
0
3V
0
2.4 V
0
3V
0
TYP
MAX
UNIT
fSYSTEM
MHz
ns
ns
UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 0
20
3V
18
UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 3
2.4 V
16
SIMO output data hold time (3)
CL = 20 pF, PMMCOREV = 3
(1)
MIN
1.8 V
CL = 20 pF, PMMCOREV = 0
tHD,MO
VCC
SMCLK or ACLK,
Duty cycle = 50% ±10%
3V
1.8 V
ns
15
–10
3V
–8
2.4 V
–10
3V
–8
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave) refer to the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-11 and Figure 5-12.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 511 and Figure 5-12.
Specifications
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1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tHD,MO
tVALID,MO
SIMO
Figure 5-11. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tHD,MO
tVALID,MO
SIMO
Figure 5-12. SPI Master Mode, CKPH = 1
Specifications
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Table 5-20. USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted) (1)
(see Figure 5-13 and Figure 5-14)
PARAMETER
TEST CONDITIONS
PMMCOREV = 0
tSTE,LEAD
STE lead time, STE low to clock
PMMCOREV = 3
PMMCOREV = 0
tSTE,LAG
STE lag time, last clock to STE high
PMMCOREV = 3
PMMCOREV = 0
tSTE,ACC
STE access time, STE low to SOMI data
out
PMMCOREV = 3
PMMCOREV = 0
STE disable time, STE high to SOMI high
impedance
tSTE,DIS
PMMCOREV = 3
PMMCOREV = 0
tSU,SI
SIMO input data setup time
PMMCOREV = 3
PMMCOREV = 0
tHD,SI
SIMO input data hold time
PMMCOREV = 3
tVALID,SO
SOMI output data valid time (2)
(2)
(3)
34
11
3V
8
2.4 V
7
3V
6
1.8 V
1
3V
1
2.4 V
1
3V
1
TYP
MAX
ns
1.8 V
66
3V
50
2.4 V
36
3V
30
1.8 V
30
3V
30
2.4 V
30
3V
ns
ns
30
1.8 V
5
3V
5
2.4 V
2
3V
2
1.8 V
5
3V
5
2.4 V
5
3V
5
ns
ns
76
3V
60
UCLK edge to SOMI valid,
CL = 20 pF, PMMCOREV = 3
2.4 V
44
SOMI output data hold time (3)
UNIT
ns
UCLK edge to SOMI valid,
CL = 20 pF, PMMCOREV = 0
CL = 20 pF, PMMCOREV = 3
(1)
MIN
1.8 V
CL = 20 pF, PMMCOREV = 0
tHD,SO
VCC
1.8 V
3V
ns
40
1.8 V
12
3V
12
2.4 V
12
3V
12
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)).
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-13 and Figure 5-14.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-13
and Figure 5-14.
Specifications
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tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tSU,SI
tLO/HI
tHD,SI
SIMO
tHD,SO
tVALID,SO
tSTE,ACC
tSTE,DIS
SOMI
Figure 5-13. SPI Slave Mode, CKPH = 0
tSTE,LAG
tSTE,LEAD
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tHD,SI
tSU,SI
SIMO
tSTE,ACC
tHD,MO
tVALID,SO
tSTE,DIS
SOMI
Figure 5-14. SPI Slave Mode, CKPH = 1
Specifications
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Table 5-21. USCI (I2C Mode)
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted) (see Figure 5-15)
PARAMETER
TEST CONDITIONS
fUSCI
USCI input clock frequency
fSCL
SCL clock frequency
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ±10%
2.2 V, 3 V
fSCL ≤ 100 kHz
2.2 V, 3 V
0
MAX
UNIT
fSYSTEM
MHz
400
kHz
4.0
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
2.2 V, 3 V
0
ns
tSU,DAT
Data setup time
2.2 V, 3 V
250
ns
fSCL > 100 kHz
fSCL ≤ 100 kHz
2.2 V, 3 V
fSCL > 100 kHz
fSCL ≤ 100 kHz
tSU,STO
Setup time for STOP
tSP
Pulse duration of spikes suppressed by
input filter
2.2 V, 3 V
fSCL > 100 kHz
tSU,STA
tHD,STA
µs
0.6
4.7
µs
0.6
4.0
µs
0.6
2.2 V
50
600
3V
50
600
tHD,STA
ns
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 5-15. I2C Mode Timing
36
Specifications
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Table 5-22. LCD_B Operating Characteristics
over operating junction temperature range (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
LCDCPEN = 1, 0000 < VLCDx ≤ 1111
(charge pump enabled, VLCD ≤ 3.6 V)
2.2
3.6
V
VCC,LCD_B,CP
en,3.6
Supply voltage range, charge
pump enabled, VLCD ≤ 3.6 V
VCC,LCD_B,CP
en,3.3
Supply voltage range, charge
pump enabled, VLCD ≤ 3.3 V
LCDCPEN = 1, 0000 < VLCDx ≤ 1100
(charge pump enabled, VLCD ≤ 3.3 V)
2.0
3.6
V
VCC,LCD_B,int. bias
Supply voltage range, internal
biasing, charge pump disabled
LCDCPEN = 0, VLCDEXT = 0
2.4
3.6
V
VCC,LCD_B,ext.
Supply voltage range, external
biasing, charge pump disabled
LCDCPEN = 0, VLCDEXT = 0
2.4
3.6
V
VCC,LCD_B,VLCDEXT
Supply voltage range, external
LCD voltage, internal or
external biasing, charge pump
disabled
LCDCPEN = 0, VLCDEXT = 1
2.0
3.6
V
VLCDCAP/R33
External LCD voltage at
LCDCAP/R33, internal or
external biasing, charge pump
disabled
LCDCPEN = 0, VLCDEXT = 1
2.4
3.6
V
CLCDCAP
Capacitor on LCDCAP when
charge pump enabled
LCDCPEN = 1, VLCDx > 0000 (charge
pump enabled)
10
µF
fFrame
LCD frame frequency range
fLCD = 2 × mux × fFRAME with mux = 1
(static), 2, 3, 4
100
Hz
fACLK,in
ACLK input frequency range
CPanel
Panel capacitance
bias
4.7
0
40
kHz
100-Hz frame frequency
30
32
10000
pF
VCC +
0.2
V
VR33
Analog input voltage at R33
LCDCPEN = 0, VLCDEXT = 1
2.4
VR23,1/3bias
Analog input voltage at R23
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0
VR13
VR03 + 2/3
× (VR33 –
VR03)
VR33
V
VR13,1/3bias
Analog input voltage at R13
with 1/3 biasing
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0
VR03
VR03 + 1/3
× (VR33 –
VR03)
VR23
V
VR13,1/2bias
Analog input voltage at R13
with 1/2 biasing
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 1
VR03
VR03 + 1/2
× (VR33 –
VR03)
VR33
V
VR03
Analog input voltage at R03
R0EXT = 1
VSS
VLCD-VR03
Voltage difference between
VLCD and R03
LCDCPEN = 0, R0EXT = 1
2.4
VLCDREF/R13
External LCD reference
voltage applied at
LCDREF/R13
VLCDREFx = 01
0.8
V
1.2
VCC +
0.2
V
1.5
V
Specifications
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Table 5-23. LCD_B Electrical Characteristics
over operating junction temperature range (unless otherwise noted)
PARAMETER
VLCD
LCD voltage
TEST CONDITIONS
VCC
MIN
TYP
VLCDx = 0000, VLCDEXT = 0
2.4 V to 3.6 V
VCC
LCDCPEN = 1, VLCDx = 0001
2 V to 3.6 V
2.59
LCDCPEN = 1, VLCDx = 0010
2 V to 3.6 V
2.66
LCDCPEN = 1, VLCDx = 0011
2 V to 3.6 V
2.72
LCDCPEN = 1, VLCDx = 0100
2 V to 3.6 V
2.79
LCDCPEN = 1, VLCDx = 0101
2 V to 3.6 V
2.85
LCDCPEN = 1, VLCDx = 0110
2 V to 3.6 V
2.92
LCDCPEN = 1, VLCDx = 0111
2 V to 3.6 V
2.98
LCDCPEN = 1, VLCDx = 1000
2 V to 3.6 V
3.05
LCDCPEN = 1, VLCDx = 1001
2 V to 3.6 V
3.10
LCDCPEN = 1, VLCDx = 1010
2 V to 3.6 V
3.17
LCDCPEN = 1, VLCDx = 1011
2 V to 3.6 V
3.24
LCDCPEN = 1, VLCDx = 1100
2 V to 3.6 V
3.30
LCDCPEN = 1, VLCDx = 1101
2.2 V to 3.6 V
3.36
LCDCPEN = 1, VLCDx = 1110
2.2 V to 3.6 V
3.42
MAX
UNIT
V
LCDCPEN = 1, VLCDx = 1111
2.2 V to 3.6 V
3.48
ICC,Peak,CP
Peak supply currents due to
charge pump activities
3.6
LCDCPEN = 1, VLCDx = 1111
2.2 V
400
tLCD,CP,on
Time to charge CLCD when
discharged
CLCD = 4.7 µF, LCDCPEN = 0→1,
VLCDx = 1111
2.2 V
100
ICP,Load
Maximum charge pump load
current
LCDCPEN = 1, VLCDx = 1111
2.2 V
RLCD,Seg
LCD driver output impedance,
segment lines
LCDCPEN = 1, VLCDx = 1000,
ILOAD = ±10 µA
2.2 V
10
kΩ
RLCD,COM
LCD driver output impedance,
common lines
LCDCPEN = 1, VLCDx = 1000,
ILOAD = ±10 µA
2.2 V
10
kΩ
µA
500
50
ms
µA
Table 5-24. 12-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
AVCC
Analog supply voltage
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
V(Ax)
Analog input voltage range (2)
All ADC12 analog input pins Ax
IADC12_A
Operating supply current into
AVCC terminal (3)
fADC12CLK = 5.0 MHz (4)
CI
Input capacitance
Only one terminal Ax can be selected at one
time
RI
Input MUX ON resistance
0 V ≤ VIN ≤ V(AVCC)
(1)
(2)
(3)
(4)
38
VCC
MIN
TYP
2.2
0
MAX
UNIT
3.6
V
AVCC
V
2.2 V
150
200
3V
150
250
2.2 V
20
25
pF
200
1900
Ω
10
µA
The leakage current is specified by the digital I/O input leakage.
The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. If the
reference voltage is supplied by an external source or if the internal voltage is used and REFOUT = 1, then decoupling capacitors are
required. See Table 5-30 and Table 5-31.
The internal reference supply current is not included in current consumption parameter IADC12.
ADC12ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC12DIV = 0
Specifications
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Table 5-25. 12-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
For specified performance of ADC12 linearity
parameters using an external reference voltage or
AVCC as reference (1)
fADC12CLK
ADC conversion clock
For specified performance of ADC12 linearity
parameters using the internal reference (2)
2.2 V, 3 V
For specified performance of ADC12 linearity
parameters using the internal reference (3)
fADC12OSC
tCONVERT
tSample
(1)
(2)
(3)
(4)
(5)
(6)
Internal ADC12
oscillator (4)
Conversion time
Sampling time
MIN
TYP
MAX
0.45
4.8
5.0
0.45
2.4
4.0
0.45
2.4
2.7
4.8
5.4
ADC12DIV = 0, fADC12CLK = fADC12OSC
2.2 V, 3 V
4.2
REFON = 0, Internal oscillator,
ADC12OSC used for ADC conversion clock
2.2 V, 3 V
2.4
External fADC12CLK from ACLK, MCLK or SMCLK,
ADC12SSEL ≠ 0
RS = 400 Ω, RI = 200 Ω, CI = 20 pF,
τ = [RS + RI] × CI (6)
UNIT
MHz
MHz
3.1
µs
See
(5)
2.2 V, 3 V
1000
ns
REFOUT = 0, external reference voltage: SREF2 = 0, SREF1 = 1, SREF0 = 0. AVCC as reference voltage: SREF2 = 0, SREF1 = 0,
SREF0 = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC. For other clock sources, the
specified performance of the ADC12 linearity is ensured with fADC12CLK maximum of 5.0 MHz.
SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 1
SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 0. The specified performance of the ADC12 linearity is ensured when
using the ADC12OSC divided by 2.
The ADC12OSC is sourced directly from MODOSC inside the UCS.
13 × ADC12DIV × 1/fADC12CLK
Approximately 10 Tau (τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) x (RS + RI) × CI + 800 ns, where n = ADC resolution = 12, RS = external source resistance
Table 5-26. 12-Bit ADC, Linearity Parameters Using an External Reference Voltage
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
EI
Integral linearity error (1)
ED
Differential linearity error (1)
EO
Offset error (3)
EG
Gain error (3)
ET
(1)
(2)
(3)
Total unadjusted error
TEST CONDITIONS
1.4 V ≤ dVREF ≤ 1.6 V
1.6 V < dVREF
See
VCC
MIN
TYP
(2)
(2)
(2)
MAX
±2
2.2 V, 3 V
±1.7
2.2 V, 3 V
±1
(2)
2.2 V, 3 V
±3
±5.6
dVREF > 2.2 V (2)
2.2 V, 3 V
±1.5
±3.5
dVREF ≤ 2.2 V
See
(2)
2.2 V, 3 V
±1
±2.5
(2)
2.2 V, 3 V
±3.5
±7.1
dVREF > 2.2 V (2)
2.2 V, 3 V
±2
±5
dVREF ≤ 2.2 V
UNIT
LSB
LSB
LSB
LSB
LSB
Parameters are derived using the histogram method.
The external reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 0. dVREF = VR+ – VR–. VR+ < AVCC. VR– > AVSS.
Unless otherwise mentioned dVREF > 1.5 V. Impedance of the external reference voltage R < 100 Ω and two decoupling capacitors, 10
µF and 100 nF, should be connected to VREF to decouple the dynamic current. See also the MSP430F5xx and MSP430F6xx Family
User's Guide (SLAU208).
Parameters are derived using a best fit curve.
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Table 5-27. 12-Bit ADC, Linearity Parameters Using AVCC as Reference Voltage
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Integral linearity error (1)
EI
(2)
2.2 V, 3 V
2.2 V, 3 V
MIN
TYP
MAX
UNIT
±2.0
LSB
ED
Differential linearity error
See
(2)
±1
LSB
EO
Offset error (3)
See
(2)
2.2 V, 3 V
±1
±2
LSB
EG
Gain error (3)
See
(2)
2.2 V, 3 V
±2
±4
LSB
ET
Total unadjusted error
See
(2)
2.2 V, 3 V
±2
±5
LSB
MAX
UNIT
(1)
(2)
(3)
(1)
VCC
See
Parameters are derived using the histogram method.
AVCC as reference voltage is selected by: SREF2 = 0, SREF1 = 0, SREF0 = 0.
Parameters are derived using a best fit curve.
Table 5-28. 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
EI
Integral
linearity error (2)
ED
Differential
linearity error (2)
EO
Offset error (3)
EG
Gain error (3)
Total unadjusted
error
ET
(1)
(2)
(3)
(4)
ADC12SR = 0, REFOUT = 1
fADC12CLK ≤ 4.0 MHz
ADC12SR = 0, REFOUT = 0
fADC12CLK ≤ 2.7 MHz
ADC12SR = 0, REFOUT = 1
fADC12CLK ≤ 4.0 MHz
ADC12SR = 0, REFOUT = 1
fADC12CLK ≤ 2.7 MHz
ADC12SR = 0, REFOUT = 0
fADC12CLK ≤ 2.7 MHz
ADC12SR = 0, REFOUT = 1
fADC12CLK ≤ 4.0 MHz
ADC12SR = 0, REFOUT = 0
fADC12CLK ≤ 2.7 MHz
ADC12SR = 0, REFOUT = 1
fADC12CLK ≤ 4.0 MHz
ADC12SR = 0, REFOUT = 0
fADC12CLK ≤ 2.7 MHz
ADC12SR = 0, REFOUT = 1
fADC12CLK ≤ 4.0 MHz
ADC12SR = 0, REFOUT = 0
fADC12CLK ≤ 2.7 MHz
VCC
MIN
TYP
±2.0
2.2 V, 3 V
±2.5
–1
+1.5
2.2 V, 3 V
±1
–1
2.2 V, 3 V
2.2 V, 3 V
LSB
+2.5
±2
±4
±2
±4
±1
±2.5
LSB
LSB
(4)
VREF
±5
LSB
±1%
±2
2.2 V, 3 V
LSB
±1% (4) VREF
The external reference voltage is selected by: SREF2 = 0, SREF1 = 0, SREF0 = 1. dVREF = VR+ – VR–.
Parameters are derived using the histogram method.
Parameters are derived using a best fit curve.
The gain error and the total unadjusted error are dominated by the accuracy of the integrated reference module absolute accuracy. In
this mode, the reference voltage used by the ADC12_A is not available on a pin.
Table 5-29. 12-Bit ADC, Temperature Sensor and Built-In VMID (1)
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
VSENSOR
TEST CONDITIONS
See Figure 5-16 (2)
ADC12ON = 1, INCH = 0Ah, TJ = 0°C
VCC
MIN
TYP
2.2 V
680
3V
680
MAX
mV
tSENSOR(sample Sample time required if channel 10
is selected (3)
)
ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
2.2 V
30
3V
30
VMID
AVCC divider at channel 11
ADC12ON = 1, INCH = 0Bh,
VMID ≈ 0.5 × VAVCC
2.2 V
1.06
1.1
1.14
3V
1.46
1.5
1.54
tVMID(sample)
Sample time required if channel 11
is selected (4)
ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
2.2 V, 3 V
1000
(1)
(2)
(3)
(4)
40
UNIT
µs
V
ns
The temperature sensor is provided by the REF module. See the REF module parametric, IREF+, regarding the current consumption of
the temperature sensor.
The temperature sensor offset can be significant. TI recommends a single-point calibration to minimize the offset error of the built-in
temperature sensor. The TLV structure contains calibration values for 30°C ±3°C and 105°C ±3°C for each of the available reference
voltage levels. The sensor voltage can be computed as VSENSE = TCSENSOR × (Temperature,°C) + VSENSOR, where TCSENSOR and
VSENSOR can be computed from the calibration values for higher accuracy. See also the MSP430F5xx and MSP430F6xx Family User's
Guide (SLAU208).
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
Specifications
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Typical Temperature Sensor Voltage (mV)
1000
950
900
850
800
750
700
650
600
550
500
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
Ambient Temperature (°C)
Figure 5-16. Typical Temperature Sensor Voltage
Table 5-30. REF, External Reference
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted) (1)
PARAMETER
MIN
MAX
UNIT
VeREF+ > VREF–/VeREF–
(2)
1.4
AVCC
V
Negative external reference
voltage input
VeREF+ > VREF–/VeREF–
(3)
0
1.2
V
Differential external reference
voltage input
VeREF+ > VREF–/VeREF–
(4)
1.4
AVCC
V
–32
32
VeREF+
Positive external reference
voltage input
VREF–/VeREF–
(VeREF+ –
VREF–/VeREF–)
IVeREF+,
IVREF–/VeREF–
CVREF+/(1)
(2)
(3)
(4)
(5)
Static input current
TEST CONDITIONS
VCC
1.4 V ≤ VeREF+ ≤ VAVCC, VeREF– = 0 V,
fADC12CLK = 5 MHz, ADC12SHTx = 1h,
Conversion rate 200 ksps
2.2 V, 3 V
1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V,
fADC12CLK = 5 MHZ, ADC12SHTx = 8h,
Conversion rate 20 ksps
2.2 V, 3 V
Capacitance at VREF+ or
VREF- terminal (5)
µA
–1.2
+1.2
10
µF
The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external
reference source if it is used for the ADC12_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).
Specifications
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Table 5-31. REF, Built-In Reference
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted) (1)
PARAMETER
Positive built-in
reference voltage
output
VREF+
AVCC(min)
AVCC minimum
voltage, Positive
built-in reference
active
TEST CONDITIONS
VCC
REFVSEL = {2} for 2.5 V,
REFON = REFOUT = 1, IVREF+ = 0 A
MIN
TYP
MAX
3V
2.5
±1%
REFVSEL = {1} for 2 V,
REFON = REFOUT = 1, IVREF+ = 0 A
3V
2.0
±1%
REFVSEL = {0} for 1.5 V,
REFON = REFOUT = 1, IVREF+ = 0 A
2.2 V, 3 V
1.5
±1%
REFVSEL = {0} for 1.5 V
2.2
REFVSEL = {1} for 2 V
2.3
REFVSEL = {2} for 2.5 V
2.8
ADC12SR = 1 (4),
REFON = 1, REFOUT = 0, REFBURST = 0
UNIT
V
V
70
100
µA
0.45
0.75
mA
210
310
µA
ADC12SR = 0 (4),
REFON = 1, REFOUT = 1, REFBURST = 0
0.95
1.7
mA
IL(VREF+)
Load-current
regulation, VREF+
terminal (5)
REFVSEL = {0, 1, 2},
IVREF+ = +10 µA or –1000 µA,
AVCC = AVCC(min) for each reference level,
REFVSEL = {0, 1, 2}, REFON = REFOUT = 1
1500
2500
µV/mA
CVREF+
Capacitance at
VREF+ terminal
REFON = REFOUT = 1 (6),
0 mA ≤ IVREF+ ≤ IVREF+(max)
100
pF
TCREF+
Temperature
coefficient of built-in
reference (7)
IVREF+ is a constant in the range of
0 mA ≤ IVREF+ ≤ –1 mA
REFOUT = 0
2.2 V, 3 V
20
TCREF+
Temperature
coefficient of built-in
reference (7)
IVREF+ is a constant in the range of
0 mA ≤ IVREF+ ≤ –1 mA
REFOUT = 1
2.2 V, 3 V
20
50
ppm/
°C
PSRR_DC
Power supply
rejection ratio (DC)
AVCC = AVCC(min) to AVCC(max), TJ = 25°C,
REFVSEL = {0, 1, 2}, REFON = 1,
REFOUT = 0 or 1
120
300
µV/V
PSRR_AC
Power supply
rejection ratio (AC)
AVCC = AVCC(min) to AVCC(max), TJ = 25°C,
REFVSEL = {0, 1, 2}, REFON = 1,
REFOUT = 0 or 1
1
Operating supply
current into AVCC
terminal (2) (3)
IREF+
tSETTLE
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
42
Settling time of
reference voltage (8)
ADC12SR = 1 (4),
REFON = 1, REFOUT = 1, REFBURST = 0
3V
(4)
ADC12SR = 0 ,
REFON = 1, REFOUT = 0, REFBURST = 0
2.2 V, 3 V
20
AVCC = AVCC(min) to AVCC(max),
REFVSEL = {0, 1, 2}, REFOUT = 0,
REFON = 0 → 1
75
AVCC = AVCC(min) to AVCC(max),
CVREF = CVREF(max), REFVSEL = {0, 1, 2},
REFOUT = 1, REFON = 0 → 1
75
ppm/
°C
mV/V
µs
The reference is supplied to the ADC by the REF module and is buffered locally inside the ADC. The ADC uses two internal buffers, one
smaller and one larger for driving the VREF+ terminal. When REFOUT = 1, the reference is available at the VREF+ terminal and is used
as the reference for the conversion and uses the larger buffer. When REFOUT = 0, the reference is only used as the reference for the
conversion and uses the smaller buffer.
The internal reference current is supplied from the AVCC terminal. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. REFOUT = 0 represents the current contribution of the smaller buffer. REFOUT = 1 represents the current
contribution of the larger buffer without external load.
The temperature sensor is provided by the REF module. Its current is supplied from the AVCC terminal and is equivalent to IREF+ with
REFON = 1 and REFOUT = 0.
For devices without the ADC12, the parametric with ADC12SR = 0 are applicable.
Contribution only due to the reference and buffer including package. This does not include resistance due to PCB trace or other causes.
Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external
reference source if it is used for the ADC12_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).
Calculated using the box method: (MAX(–40°C to 105°C) – MIN(–40°C to 105°C)) / MIN(–40°C to 105°C)/(105°C – (–40°C)).
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load when REFOUT = 1.
Specifications
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Table 5-32. 12-Bit DAC, Supply Specifications
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
AVCC
Analog supply voltage
TEST CONDITIONS
DAC12AMPx = 2, DAC12IR = 0, DAC12IOG = 1
DAC12_xDAT = 0800h
VeREF+ = VREF+ = 1.5 V
Supply current, single
DAC channel (1) (2)
IDD
VCC
AVCC = DVCC, AVSS = DVSS = 0 V
3V
DAC12AMPx = 2, DAC12IR = 1,
DAC12_xDAT = 0800h,
VeREF+ = VREF+ = AVCC
DAC12AMPx = 5, DAC12IR = 1,
DAC12_xDAT = 0800h,
VeREF+ = VREF+ = AVCC
PSRR
(1)
(2)
(3)
(4)
DAC12_xDAT = 800h, VeREF+ = 1.5 V,
ΔAVCC = 100 mV
DAC12_xDAT = 800h, VeREF+ = 1.5 V or 2.5 V,
ΔAVCC = 100 mV
TYP
MAX
UNIT
3.60
V
65
110
65
110
250
300
750
1000
µA
2.2 V, 3 V
DAC12AMPx = 7, DAC12IR = 1,
DAC12_xDAT = 0800h,
VeREF+ = VREF+ = AVCC
Power supply rejection
ratio (3) (4)
MIN
2.20
2.2 V
70
3V
70
dB
No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly.
Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Table 5-35.
PSRR = 20 log (ΔAVCC / ΔVDAC12_xOUT)
The internal reference is not used.
Specifications
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Table 5-33. 12-Bit DAC, Linearity Specifications
See Figure 5-17, over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
Resolution
TEST CONDITIONS
INL
Integral nonlinearity (1)
DNL
Differential nonlinearity (1)
MIN
2.2 V
±2
±4
3V
±2
±4
VeREF+ = 1.5 V, DAC12AMPx = 7, DAC12IR = 1
2.2 V
±0.4
±1
VeREF+ = 2.5 V, DAC12AMPx = 7, DAC12IR = 1
3V
±0.4
±1
(1) (2)
With calibration
Offset error temperature
coefficient (1)
EG
Gain error
dE(G)/dT
Gain temperature
coefficient (1)
tOffset_Cal
Time for offset
calibration (3)
(1) (2)
VeREF+ = 1.5 V,
DAC12AMPx = 7,
DAC12IR = 1
2.2 V
±21
VeREF+ = 2.5 V,
DAC12AMPx = 7,
DAC12IR = 1
3V
±21
VeREF+ = 1.5 V,
DAC12AMPx = 7,
DAC12IR = 1
2.2 V
±1.5
VeREF+ = 2.5 V,
DAC12AMPx = 7,
DAC12IR = 1
3V
±1.5
With calibration
2.2 V, 3 V
±10
VeREF+ = 1.5 V
2.2 V
±2.5
VeREF+ = 2.5 V
3V
±2.5
2.2 V, 3 V
LSB
µV/°C
%FSR
ppm of
FSR/°C
10
165
DAC12AMPx = 3, 5
2.2 V, 3 V
66
DAC12AMPx = 4, 6, 7
(2)
(3)
LSB
mV
DAC12AMPx = 2
(1)
UNIT
bits
VeREF+ = 2.5 V, DAC12AMPx = 7, DAC12IR = 1
Offset voltage
dE(O)/dT
TYP MAX
12
VeREF+ = 1.5 V, DAC12AMPx = 7, DAC12IR = 1
Without calibration
EO
VCC
12-bit monotonic
ms
16.5
Parameters calculated from the best-fit curve from 0x0F to 0xFFF. The best-fit curve method is used to deliver coefficients “a” and “b” of
the first-order equation: y = a + bx. VDAC12_xOUT = EO + (1 + EG) × (VeREF+/4095) × DAC12_xDAT, DAC12IR = 1.
The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON.
The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx =
{0, 1}. TI recommends configuring the DAC12 module before initiating calibration. Port activity during calibration may affect accuracy
and is not recommended.
DAC VOUT
DAC Output
VR+
RLoad = ¥
Ideal transfer
function
AVCC
2
CLoad = 100 pF
Offset Error
Positive
Negative
Gain Error
DAC Code
Figure 5-17. Linearity Test Load Conditions and Gain/Offset Definition
44
Specifications
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Table 5-34. 12-Bit DAC, Output Specifications
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
No load, VeREF+ = AVCC, DAC12_xDAT = 0h,
DAC12IR = 1, DAC12AMPx = 7
No load, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
Output voltage
range (1) (see
Figure 5-18)
VO
Maximum DAC12
load capacitance
IL(DAC12)
Maximum DAC12
load current
MAX
0
0.005
AVCC
– 0.05
AVCC
0
0.1
AVCC
– 0.13
AVCC
DAC12AMPx = 2, DAC12_xDAT = 0FFFh,
VO/P(DAC12) > AVCC – 0.3
100
mA
1
RLoad = 3 kΩ, VO/P(DAC12) > AVCC – 0.3 V,
DAC12_xDAT = 0FFFh
2.2 V, 3 V
150
250
150
250
RLoad = 3 kΩ,
0.3 V ≤ VO/P(DAC12) ≤ AVCC – 0.3 V
(1)
pF
–1
2.2 V, 3 V
DAC12AMPx = 2, DAC12_xDAT = 0h,
VO/P(DAC12) < 0.3 V
Output resistance
(see Figure 5-18)
UNIT
V
2.2 V, 3 V
RLoad = 3 kΩ, VO/P(DAC12) < 0.3 V,
DAC12AMPx = 2, DAC12_xDAT = 0h
RO/P(DAC12)
TYP
2.2 V, 3 V
RLoad = 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
RLoad = 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
CL(DAC12)
MIN
Ω
6
Data is valid after the offset calibration of the output amplifier.
RO/P(DAC12_x)
Max
RLoad
ILoad
AVCC
DAC12
2
O/P(DAC12_x)
CLoad = 100 pF
Min
0.3
AVCC – 0.3 V
VOUT
AVCC
Figure 5-18. DAC12_x Output Resistance Tests
Specifications
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Table 5-35. 12-Bit DAC, Reference Input Specifications
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DAC12IR = 0 (1)
VeREF+
VCC
MIN
(2)
Reference input voltage range
MAX
AVCC/3
AVCC
+ 0.2
AVCC
AVCC
+ 0.2
2.2 V, 3 V
DAC12IR = 1 (3)
(4)
DAC12_0 IR = DAC12_1 IR = 0
Ri(VREF+),
Ri(VeREF+)
TYP
20
DAC12_0 IR = 0, DAC12_1 IR = 1
52
2.2 V, 3 V
52
DAC12_0 IR = DAC12_1 IR = 1,
DAC12_0 SREFx = DAC12_1 SREFx (5)
(1)
(2)
(3)
(4)
(5)
V
MΩ
DAC12_0 IR = 1, DAC12_1 IR = 0
Reference input resistance
UNIT
kΩ
26
For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / [3 × (1 + EG)].
For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / (1 + EG).
When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel
reducing the reference input resistance.
Table 5-36. 12-Bit DAC, Dynamic Specifications
VREF = VCC, DAC12IR = 1 (see Figure 5-19 and Figure 5-20), over recommended ranges of supply voltage and operating
junction temperature (unless otherwise noted)
PARAMETER
tON
TEST CONDITIONS
DAC12_xDAT = 800h,
ErrorV(O) < ±0.5 LSB (1)
(see Figure 5-19)
DAC12 on time
VCC
MIN
DAC12AMPx = 0 → {2, 3, 4}
DAC12AMPx = 0 → {5, 6}
2.2 V, 3 V
DAC12AMPx = 0 → 7
DAC12AMPx = 2
tS(FS)
DAC12_xDAT =
80h → F7Fh → 80h
Settling time, full scale
DAC12AMPx = 3, 5
2.2 V, 3 V
DAC12AMPx = 4, 6, 7
tS(C-C)
DAC12_xDAT =
3F8h → 408h → 3F8h,
BF8h → C08h → BF8h
Settling time, code to
code
DAC12AMPx = 2
DAC12_xDAT =
80h → F7Fh → 80h (2)
Slew rate
2.2 V, 3 V
DAC12_xDAT =
800h → 7FFh → 800h
(1)
(2)
120
15
30
6
12
100
200
40
80
15
30
2
DAC12AMPx = 4, 6, 7
UNIT
µs
µs
µs
1
DAC12AMPx = 3, 5
2.2 V, 3 V
DAC12AMPx = 4, 6, 7
Glitch energy
60
5
DAC12AMPx = 3, 5
DAC12AMPx = 2
SR
TYP MAX
DAC12AMPx = 7
0.05
0.35
0.35
1.10
1.50
5.20
2.2 V, 3 V
35
V/µs
nV-s
RLoad and CLoad connected to AVSS (not AVCC/2) in Figure 5-19.
Slew rate applies to output voltage steps ≥ 200 mV.
Conversion 1
VOUT
DAC Output
ILoad
RLoad = 3 kW
Conversion 2
Conversion 3
±1/2 LSB
Glitch
Energy
AVCC
2
RO/P(DAC12.x)
±1/2 LSB
CLoad = 100 pF
tsettleLH
tsettleHL
Figure 5-19. Settling Time and Glitch Energy Testing
46
Specifications
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Conversion 1
Conversion 2
Conversion 3
VOUT
90%
90%
10%
10%
tSRLH
tSRHL
Figure 5-20. Slew Rate Testing
Table 5-37. 12-Bit DAC, Dynamic Specifications (Continued)
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
TJ = 25°C
BW–3dB
3-dB bandwidth,
VDC = 1.5 V,
VAC = 0.1 VPP (see
Figure 5-21)
DAC12AMPx = {5, 6}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
TJ = 25°C
(1)
MAX
UNIT
40
2.2 V, 3 V
DAC12AMPx = 7, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
TJ = 25°C
180
kHz
550
DAC12_0DAT = 800h, No load,
DAC12_1DAT = 80h ↔ F7Fh, RLoad = 3 kΩ,
fDAC12_1OUT = 10 kHz at 50/50 duty cycle,
TJ = 25°C
Channel-to-channel
crosstalk (1) (see Figure 522)
TYP
DAC12_0DAT = 80h ↔ F7Fh, RLoad = 3 kΩ,
DAC12_1DAT = 800h, No load,
fDAC12_0OUT = 10 kHz at 50/50 duty cycle,
TJ = 25°C
–80
2.2 V, 3 V
dB
–80
RLoad = 3 kΩ, CLoad = 100 pF
RLoad = 3 kW
ILoad
VeREF+
AVCC
DAC12_x
2
DACx
AC
CLoad = 100 pF
DC
Figure 5-21. Test Conditions for 3-dB Bandwidth Specification
RLoad
ILoad
AVCC
DAC12_0
2
DAC0
DAC12_xDAT 080h
F7Fh
080h
F7Fh
080h
VOUT
CLoad = 100 pF
VREF+
VDAC12_yOUT
RLoad
ILoad
AVCC
DAC12_1
VDAC12_xOUT
2
DAC1
1/fToggle
CLoad = 100 pF
Figure 5-22. Crosstalk Test Conditions
Specifications
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Table 5-38. Comparator_B
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
VCC
TEST CONDITIONS
VCC
Supply voltage
MIN
TYP
1.8
3.6
1.8 V
IAVCC_COM
P
Comparator operating supply
current into AVCC terminal,
Excludes reference resistor ladder
CBPWRMD = 00
30
50
3V
40
65
CBPWRMD = 01
2.2 V, 3 V
10
30
CBPWRMD = 10
2.2 V, 3 V
0.1
0.5
IAVCC_REF
VIC
Common mode input range
Input offset voltage
CIN
Input capacitance
RSIN
Series input resistance
tPD
Propagation delay, response time
tPD,filter
Propagation delay with filter active
0
5
3
mV
pF
4
50
kΩ
MΩ
CBPWRMD = 00, CBF = 0
450
CBPWRMD = 01, CBF = 0
600
CBPWRMD = 10, CBF = 0
50
ns
µs
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 00
0.35
0.6
1.0
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 01
0.6
1.0
1.8
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 10
1.0
1.8
3.4
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 11
1.8
3.4
6.5
1
2
µs
0.3
1.5
µs
VIN ×
(n + 1)
/ 32
VIN ×
(n + 1.5)
/ 32
V
CBON = 0 to CBON = 1
CBPWRMD = 00, 01, 10
tEN_REF
Resistor reference enable time
CBON = 0 to CBON = 1
48
V
±10
Comparator enable time, settling
time
Reference voltage for a given tap
VCC – 1
CBPWRMD = 01, 10
ON, switch closed
µA
µA
±20
tEN_CMP
VCB_REF
V
22
CBPWRMD = 00
OFF, switch opened
UNIT
40
2.2 V
Quiescent current of local reference CBREFACC = 1,
voltage amplifier into AVCC terminal CBREFLx = 01
VOFFSET
MAX
VIN = reference into resistor
ladder, n = 0 to 31
Specifications
µs
VIN ×
(n +
0.5)
/ 32
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Table 5-39. Flash Memory
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
DVCC(PGM/ERASE) Program and erase supply voltage
MIN
TYP
1.8
MAX
3.6
UNIT
V
IPGM
Average supply current from DVCC during program
3
5
mA
IERASE
Average supply current from DVCC during erase
6
17
mA
IMERASE, IBANK
Average supply current from DVCC during mass erase or bank
erase
6
17
mA
tCPT
Cumulative program time
See
(1)
16
103
Program and erase endurance
105
ms
cycles
tRetention
Data retention duration
TJ = 25°C
tWord
Word or byte program time
See
(2)
64
85
µs
tBlock,
0
Block program time for first byte or word
See
(2)
49
65
µs
1–(N–1)
Block program time for each additional byte or word, except for last
byte or word
See
(2)
37
49
µs
Block program time for last byte or word
See
(2)
55
73
µs
Erase time for segment, mass erase, and bank erase when
available
See
(2)
23
32
ms
0
1
MHz
tBlock,
tBlock,
tSeg
N
Erase
fMCLK,MRG
(1)
(2)
MCLK frequency in marginal read mode
(FCTL4.MRG0 = 1 or FCTL4.MRG1 = 1)
100
years
The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word write, individual byte write, and block write modes.
These values are hardwired into the state machine of the flash controller.
5.14.4 Emulation and Debug
Table 5-40. JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
2.2 V, 3 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse duration
2.2 V, 3 V
0.025
15
µs
tSBW, En
Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge) (1)
2.2 V, 3 V
1
µs
tSBW,Rst
Spy-Bi-Wire return to normal operation time
µs
fTCK
TCK input frequency for 4-wire JTAG (2)
Rinternal
Internal pulldown resistance on TEST
(1)
(2)
15
100
2.2 V
0
5
3V
0
10
2.2 V, 3 V
45
60
80
MHz
kΩ
Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
Specifications
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6 Detailed Description
6.1
Overview
The MSP430F6459 is an ultra-low-power microcontroller that consists of several features which include
different sets of peripherals targeted for various applications. The architecture, combined with five lowpower modes, is optimized to achieve extended battery life in portable measurement applications.
The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute
to maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from
low-power modes to active mode in 3 μs (typical).
6.2
CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and
constant generator, respectively. The remaining registers are general-purpose registers (see Figure 6-1).
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
For further details, see the CPUX Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)
(SLAU391).
Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
Constant Generator
SR/CG1/R2
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Figure 6-1. CPU Registers
50
Detailed Description
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6.3
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Instruction Set
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word and
byte data. Table 6-1 shows examples of the three types of instruction formats; Table 6-2 shows the
address modes.
Table 6-1. Instruction Word Formats
INSTRUCTION WORD FORMAT
EXAMPLE
Dual operands, source-destination
ADD
Single operands, destination only
R4 + R5 → R5
R8
PC → (TOS), R8 → PC
CALL
Relative jump, unconditional or conditional
OPERATION
R4,R5
JNE
Jump-on-equal bit = 0
Table 6-2. Address Mode Descriptions
(1)
ADDRESS MODE
S (1)
D (1)
SYNTAX
EXAMPLE
Register
+
+
MOV Rs,Rd
MOV R10,R11
R10 → R11
Indexed
+
+
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
M(2+R5) → M(6+R6)
Symbolic (PC relative)
+
+
MOV EDE,TONI
Absolute
+
+
MOV &MEM, &TCDAT
Indirect
+
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) → M(Tab+R6)
Indirect auto-increment
+
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) → R11
R10 + 2 → R10
Immediate
+
MOV #X,TONI
MOV #45,TONI
#45 → M(TONI)
OPERATION
M(EDE) → M(TONI)
M(MEM) → M(TCDAT)
S = source, D = destination
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Operating Modes
The MCUs have one active mode and seven software selectable low-power modes of operation. An
interrupt event can wake up the device from any of the low-power modes, service the request, and restore
back to the low-power mode on return from the interrupt program.
Software can configure the following operating modes:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– FLL loop control remains active
• Low-power mode 1 (LPM1)
– CPU is disabled
– FLL loop control is disabled
– ACLK and SMCLK remain active, MCLK is disabled
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO is disabled
– Crystal oscillator is stopped
– Complete data retention
• Low-power mode 3.5 (LPM3.5)
– Internal regulator disabled
– No data retention
– RTC enabled and clocked by low-frequency oscillator
– Wake-up signal from RST/NMI, RTC_B, P1, P2, P3, and P4
• Low-power mode 4.5 (LPM4.5)
– Internal regulator disabled
– No data retention
– Wake-up signal from RST/NMI, P1, P2, P3, and P4
52
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6.5
SLASEC3A – AUGUST 2016 – REVISED AUGUST 2016
Interrupt Vector Addresses
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see
Table 6-3). The vector contains the 16-bit address of the appropriate interrupt-handler instruction
sequence.
Table 6-3. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
INTERRUPT FLAG
System Reset
Power-Up, External Reset
Watchdog Time-out, Key Violation
Flash Memory Key Violation
WDTIFG, KEYV (SYSRSTIV) (1)
(2)
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
Reset
0FFFEh
63, highest
System NMI
PMM
Vacant Memory Access
JTAG Mailbox
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
SVMLVLRIFG, SVMHVLRIFG, VMAIFG,
JMBNIFG, JMBOUTIFG (SYSSNIV) (1)
(Non)maskable
0FFFCh
62
User NMI
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG, OFIFG, ACCVIFG, BUSIFG
(SYSUNIV) (1) (2)
(Non)maskable
0FFFAh
61
Maskable
0FFF8h
60
Comparator B interrupt flags (CBIV) (1)
Comp_B
Timer TB0
Timer TB0
TB0CCR0 CCIFG0
Maskable
0FFF6h
59
TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,
TB0IFG (TB0IV) (1) (3)
Maskable
0FFF4h
58
WDTIFG
Watchdog Interval Timer Mode
Maskable
0FFF2h
57
USCI_A0 Receive or Transmit
UCA0RXIFG, UCA0TXIFG (UCA0IV) (1)
(3)
Maskable
0FFF0h
56
USCI_B0 Receive or Transmit
UCB0RXIFG, UCB0TXIFG (UCB0IV) (1)
(3)
Maskable
0FFEEh
55
(1) (3)
ADC12_A
Maskable
0FFECh
54
Timer TA0
TA0CCR0 CCIFG0 (3)
Maskable
0FFEAh
53
Timer TA0
TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,
TA0IFG (TA0IV) (1) (3)
Maskable
0FFE8h
52
LDO-PWR
(4)
ADC12IFG0 to ADC12IFG15 (ADC12IV)
LDOOFFIG, LDOONIFG, LDOOVLIFG
Maskable
0FFE6h
51
DMA
DMA0IFG, DMA1IFG, DMA2IFG, DMA3IFG,
DMA4IFG, DMA5IFG (DMAIV) (1) (3)
Maskable
0FFE4h
50
Timer TA1
TA1CCR0 CCIFG0 (3)
Maskable
0FFE2h
49
Timer TA1
TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,
TA1IFG (TA1IV) (1) (3)
Maskable
0FFE0h
48
I/O Port P1
P1IFG.0 to P1IFG.7 (P1IV) (1) (3)
Maskable
0FFDEh
47
Maskable
0FFDCh
46
Maskable
0FFDAh
45
Maskable
0FFD8h
44
Maskable
0FFD6h
43
Maskable
0FFD4h
42
Maskable
0FFD2h
41
Maskable
0FFD0h
40
Maskable
0FFCEh
39
(3)
Maskable
0FFCCh
38
(1) (3)
Maskable
0FFCAh
37
UCA1RXIFG, UCA1TXIFG (UCA1IV)
USCI_B1 Receive or Transmit
UCB1RXIFG, UCB1TXIFG (UCB1IV) (1)
I/O Port P2
P2IFG.0 to P2IFG.7 (P2IV) (1)
(5)
(3)
(3)
LCD_B Interrupt Flags (LCDBIV)
(1)
RTC_B
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RT0PSIFG, RT1PSIFG, RTCOFIFG (RTCIV) (1)
DAC12_A
DAC12_0IFG, DAC12_1IFG (1)
Timer TA2
Timer TA2
TA2CCR0 CCIFG0
(3)
(3)
(3)
TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,
TA2IFG (TA2IV) (1) (3)
I/O Port P3
I/O Port P4
(3)
(4)
(5)
(1) (3)
USCI_A1 Receive or Transmit
LCD_B
(1)
(2)
(3)
(3)
P3IFG.0 to P3IFG.7 (P3IV) (1)
P4IFG.0 to P4IFG.7 (P4IV)
Multiple source flags
A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
Interrupt flags are in the module.
Only on devices with peripheral module LDO-PWR.
Only on devices with peripheral module LCD_B, otherwise reserved.
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Table 6-3. Interrupt Sources, Flags, and Vectors (continued)
INTERRUPT SOURCE
USCI_A2 Receive or Transmit
USCI_B2 Receive or Transmit
Reserved
(6)
54
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
(3)
0FFC8h
36
(1) (3)
0FFC6h
35
0FFC4h
34
INTERRUPT FLAG
UCA2RXIFG, UCA2TXIFG (UCA2IV) (1)
UCB2RXIFG, UCB2TXIFG (UCB2IV)
Reserved
(6)
⋮
⋮
0FF80h
0, lowest
Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, TI recommends reserving these locations.
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6.6
SLASEC3A – AUGUST 2016 – REVISED AUGUST 2016
Memory Organization
Table 6-4 summarizes the memory map.
Table 6-4. Memory Organization (1)
DESCRIPTION
Memory (flash)
Total Size
Main: interrupt vector
Main: code memory
MID support software (ROM)
RAM
RAM
Information memory (flash)
Bootloader (BSL) memory (flash)
Peripherals
(1)
6.7
512KB
00FFFFh–00FF80h
Bank 3
128KB
087FFFh-068000h
Bank 2
128KB
067FFFh-48000h
Bank 1
128KB
047FFFh-028000h
Bank 0
128KB
027FFFh-008000h
Total Size
1KB
006FFFh-006C00h
Sector 3
16KB
0FBFFFh-0F8000h
Sector 2
16KB
0F7FFFh-0F4000h
Sector 1
16KB
0F3FFFh-0F0000h
Sector 0
16KB
0063FFh–002400h
(mirrored at address range
0FFFFFh-0FC000h)
Sector 7
2KB
0023FFh-001C00h
Info A
128 B
0019FFh–001980h
Info B
128 B
00197Fh–001900h
Info C
128 B
0018FFh–001880h
Info D
128 B
00187Fh–001800h
BSL 3
512 B
0017FFh–001600h
BSL 2
512 B
0015FFh–001400h
BSL 1
512 B
0013FFh–001200h
BSL 0
512 B
0011FFh–001000h
Size
4KB
000FFFh–000000h
N/A = Not available
Bootloader (BSL)
The BSL enables users to program the flash memory or RAM using various serial interfaces. Access to
the device memory by the BSL is protected by an user-defined password. For complete description of the
features of the BSL and its implementation, see MSP430 Programming WIth the Bootloader (BSL)
(SLAU319).
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UART BSL
MSP4306459 comes preprogrammed with the UART BSL. Use of the UART BSL requires external access
to six pins (see Table 6-5).
Table 6-5. UART BSL Pin Requirements and Functions
56
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
TEST/SBWTCK
Entry sequence signal
P1.1
Data transmit
P1.2
Data receive
VCC
Power supply
VSS
Ground supply
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6.8
6.8.1
SLASEC3A – AUGUST 2016 – REVISED AUGUST 2016
JTAG Operation
JTAG Standard Interface
The MSP430 family supports the standard JTAG interface which requires four signals for sending and
receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to
enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with
MSP430 development tools and device programmers. Table 6-6 lists the JTAG pin requirements. For
further details on interfacing to development tools and device programmers, see the MSP430 Hardware
Tools User's Guide (SLAU278). For a complete description of the features of the BSL and its
implementation, see the MSP430 Programming With the Bootloader User's Guide (SLAU319).
Table 6-6. JTAG Pin Requirements and Functions
6.8.2
DEVICE SIGNAL
DIRECTION
FUNCTION
PJ.3/TCK
IN
JTAG clock input
PJ.2/TMS
IN
JTAG state control
PJ.1/TDI/TCLK
IN
JTAG data input, TCLK input
PJ.0/TDO
OUT
JTAG data output
TEST/SBWTCK
IN
Enable JTAG pins
RST/NMI/SBWTDIO
IN
External reset
VCC
Power supply
VSS
Ground supply
Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire
interface. Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers.
Table 6-7 lists the Spy-Bi-Wire interface pin requirements. For further details on interfacing to
development tools and device programmers, see the MSP430 Hardware Tools User's Guide (SLAU278).
For a complete description of the features of the JTAG interface and its implementation, see MSP430
Programming Via the JTAG Interface (SLAU320).
Table 6-7. Spy-Bi-Wire Pin Requirements and Functions
6.9
DEVICE SIGNAL
DIRECTION
FUNCTION
TEST/SBWTCK
IN
Spy-Bi-Wire clock input
RST/NMI/SBWTDIO
IN, OUT
Spy-Bi-Wire data input and output
VCC
Power supply
VSS
Ground supply
Flash Memory
The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system
by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory.
Features of the flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are
also called information memory.
• Segment A can be locked separately.
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For further information, see the Flash Controller Module (Chapter Excerpt From MSP430x5xx Family,
SLAU208) (SLAU392).
6.10 Memory Integrity Detection (MID)
The MID is an add-on to the MSP430 flash memory controller. MID provides additional functionality over
the regular flash operation methods. Main purpose of the MID function is gaining higher reliability of flash
content and overall system integrity in harsh environments and application areas requiring such features.
The on-chip MID ROM contains the factory programmed MID support software. This software package
provides several software functions that allow to use all MID features.
The MID functionality can be enabled for different flash memory ranges. These memory ranges are
selectable by the cw0 parameter of the MID function MidEnable(). Details about address range coverage
is listed in Table 6-8.
For further information, see the MID Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)
(SLAU459).
Table 6-8. Address Range Coverage of cw0 Parameter
of MidEnable() Function
BITS OF cw0 PARAMETER
ADDRESS RANGE
cw0.15
087FFFh-080000h
cw0.14
07FFFFh-078000h
cw0.13
077FFFh-070000h
cw0.12
06FFFFh-068000h
cw0.11
067FFFh-060000h
cw0.10
05FFFFh-058000h
cw0.9
057FFFh-050000h
cw0.8
04FFFFh-048000h
cw0.7
047FFFh-040000h
cw0.6
03FFFFh-038000h
cw0.5
037FFFh-030000h
cw0.4
02FFFFh-028000h
cw0.3
027FFFh-020000h
cw0.2
01FFFFh-018000h
cw0.1
017FFFh-010000h
cw0.0
00FFFFh-008000h
6.11 RAM
The RAM is made up of n sectors. Each sector can be completely powered down to save leakage;
however, all data is lost. Features of the RAM include:
• RAM has n sectors. The size of a sector can be found in Section 6.6.
• Each sector 0 to n can be complete disabled; however, data retention is lost.
• Each sector 0 to n automatically enters low-power retention mode when possible.
For further information, see the RAM Controller Module (Chapter Excerpt From MSP430x5xx Family,
SLAU208) (SLAU393).
58
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6.12 Backup RAM
The backup RAM provides a limited number of bytes of RAM that are retained during LPMx.5 and during
operation from a backup supply if the battery backup system module is implemented.
There are 8 bytes of backup RAM available. It can be word-wise accessed by the control registers
BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3.
For further information, see the Backup RAM Module (Chapter Excerpt From MSP430x5xx Family,
SLAU208) (SLAU394).
6.13 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be
handled using all instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx
Family User's Guide (SLAU208).
6.13.1 Digital I/O
There are up to nine 8-bit I/O ports implemented: P1 through P9 are complete and port PJ contains four
individual I/O ports.
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports.
• Programmable drive strength on all ports.
• Edge-selectable interrupt input capability for all the eight bits of ports P1, P2, P3, and P4.
• Read and write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise (P1 through P9) or word-wise in pairs (PA through PD).
For further information, see the Digital I/O Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)
(SLAU396).
6.13.2 Port Mapping Controller
The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P2.
Table 6-9 lists the available mappings, and Table 6-10 lists the default settings.
For further information, see the Port Mapping Controller Module (Chapter Excerpt From MSP430x5xx
Family, SLAU208) (SLAU397).
Table 6-9. Port Mapping Mnemonics and Functions
VALUE
PxMAPy MNEMONIC
INPUT PIN FUNCTION
0
PM_NONE
None
DVSS
PM_CBOUT
–
Comparator_B output
PM_TB0CLK
Timer TB0 clock input
–
PM_ADC12CLK
–
ADC12CLK
PM_DMAE0
DMAE0 Input
–
PM_SVMOUT
–
SVM output
PM_TB0OUTH
Timer TB0 high impedance input
TB0OUTH
–
4
PM_TB0CCR0B
Timer TB0 CCR0 capture input CCI0B
Timer TB0: TB0.0 compare output Out0
5
PM_TB0CCR1B
Timer TB0 CCR1 capture input CCI1B
Timer TB0: TB0.1 compare output Out1
6
PM_TB0CCR2B
Timer TB0 CCR2 capture input CCI2B
Timer TB0: TB0.2 compare output Out2
7
PM_TB0CCR3B
Timer TB0 CCR3 capture input CCI3B
Timer TB0: TB0.3 compare output Out3
8
PM_TB0CCR4B
Timer TB0 CCR4 capture input CCI4B
Timer TB0: TB0.4 compare output Out4
9
PM_TB0CCR5B
Timer TB0 CCR5 capture input CCI5B
Timer TB0: TB0.5 compare output Out5
1
2
3
OUTPUT PIN FUNCTION
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Table 6-9. Port Mapping Mnemonics and Functions (continued)
VALUE
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
10
PM_TB0CCR6B
Timer TB0 CCR6 capture input CCI6B
Timer TB0: TB0.6 compare output Out6
11
12
13
14
15
16
PM_UCA0RXD
USCI_A0 UART RXD (Direction controlled by USCI - input)
PM_UCA0SOMI
USCI_A0 SPI slave out master in (direction controlled by USCI)
PM_UCA0TXD
USCI_A0 UART TXD (Direction controlled by USCI - output)
PM_UCA0SIMO
USCI_A0 SPI slave in master out (direction controlled by USCI)
PM_UCA0CLK
USCI_A0 clock input/output (direction controlled by USCI)
PM_UCB0STE
USCI_B0 SPI slave transmit enable (direction controlled by USCI - input)
PM_UCB0SOMI
USCI_B0 SPI slave out master in (direction controlled by USCI)
PM_UCB0SCL
USCI_B0 I2C clock (open drain and direction controlled by USCI)
PM_UCB0SIMO
USCI_B0 SPI slave in master out (direction controlled by USCI)
PM_UCB0SDA
USCI_B0 I2C data (open drain and direction controlled by USCI)
PM_UCB0CLK
USCI_B0 clock input/output (direction controlled by USCI)
PM_UCA0STE
USCI_A0 SPI slave transmit enable (direction controlled by USCI - input)
17
PM_MCLK
–
18
Reserved
Reserved for test purposes. Do not use this setting.
19
Reserved
20-30
Reserved
31 (0FFh) (1)
PM_ANALOG
(1)
MCLK
Reserved for test purposes. Do not use this setting.
None
DVSS
Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents
when applying analog signals.
The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide, and the upper bits are
ignored, which results in a read out value of 31.
Table 6-10. Default Mapping
PIN
PxMAPy MNEMONIC
P2.0/P2MAP0
PM_UCB0STE,
PM_UCA0CLK
P2.1/P2MAP1
P2.2/P2MAP2
OUTPUT PIN FUNCTION
USCI_B0 SPI slave transmit enable (direction controlled by USCI - input),
USCI_A0 clock input/output (direction controlled by USCI)
PM_UCB0SIMO,
PM_UCB0SDA
USCI_B0 SPI slave in master out (direction controlled by USCI),
PM_UCB0SOMI,
PM_UCB0SCL
USCI_B0 SPI slave out master in (direction controlled by USCI),
USCI_B0 I2C data (open drain and direction controlled by USCI)
USCI_B0 I2C clock (open drain and direction controlled by USCI)
PM_UCB0CLK,
PM_UCA0STE
USCI_B0 clock input/output (direction controlled by USCI),
PM_UCA0TXD,
PM_UCA0SIMO
USCI_A0 UART TXD (direction controlled by USCI - output),
P2.5/P2MAP5
PM_UCA0RXD,
PM_UCA0SOMI
USCI_A0 UART RXD (direction controlled by USCI - input),
P2.6/P2MAP6/ R03
PM_NONE
–
DVSS
P2.7/P2MAP7/LCDREF/R13
PM_NONE
–
DVSS
P2.3/P2MAP3
P2.4/P2MAP4
60
INPUT PIN FUNCTION
USCI_A0 SPI slave transmit enable (direction controlled by USCI - input)
USCI_A0 SPI slave in master out (direction controlled by USCI)
USCI_A0 SPI slave out master in (direction controlled by USCI)
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6.13.3 Oscillator and System Clock
The clock system is supported by the Unified Clock System (UCS) module that includes support for a 32kHz watch crystal oscillator (in XT1 LF mode; XT1 HF mode is not supported), an internal very-low-power
low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), an integrated internal
digitally controlled oscillator (DCO), and a high-frequency crystal oscillator (XT2). The UCS module is
designed to meet the requirements of both low system cost and low power consumption. The UCS module
features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator,
stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal
DCO provides a fast turnon clock source and stabilizes in 3 µs (typical). The UCS module provides the
following clock signals:
• Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (XT1), a high-frequency crystal (XT2), the
internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal
digitally-controlled oscillator DCO.
• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources
available to ACLK.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be
sourced by same sources available to ACLK.
• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
For further information, see the UCS Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)
(SLAU390).
6.13.4 Power-Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device and
contains programmable output levels to provide for power optimization. The PMM also includes supply
voltage supervisor (SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection.
The brownout circuit is implemented to provide the proper internal reset signal to the device during poweron and power-off. The SVS and SVM circuitry detects if the supply voltage drops below a user-selectable
level and supports both supply voltage supervision (the device is automatically reset) and supply voltage
monitoring (the device is not automatically reset). SVS and SVM circuitry is available on the primary
supply and core supply.
For further information, see the PMM Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)
(SLAU388).
6.13.5 Hardware Multiplier (MPY)
The multiplication operation is supported by a dedicated peripheral module. The module performs
operations with 32-bit, 24-bit, 16-bit, and 8-bit operands. The module supports signed and unsigned
multiplication as well as signed and unsigned multiply-and-accumulate operations.
For further information, see the MPY Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)
(SLAU404).
6.13.6 Real-Time Clock (RTC_B)
The RTC_B module can be configured for real-time clock (RTC) or calendar mode providing seconds,
minutes, hours, day of week, day of month, month, and year. Calendar mode integrates an internal
calendar which compensates for months with less than 31 days and includes leap year correction. The
RTC_B also supports flexible alarm functions and offset-calibration hardware. The implementation on this
device supports operation in LPM3.5 mode and operation from a backup supply.
The application report Using the MSP430 RTC_B Module With Battery Backup Supply (SLAA665)
describes how to use the RTC_B with battery backup supply functionality to retain the time and keep the
RTC counting through loss of main power supply, as well as how to handle correct reinitialization when the
main power supply is restored.
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For further information, see the RTC_B Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)
(SLAU403).
6.13.7 Watchdog Timer (WDT_A)
The primary function of the WDT_A module is to perform a controlled system restart after a software
problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function
is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
For further information, see the WDT_A Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)
(SLAU399).
6.13.8 System Module (SYS)
The SYS module handles many of the system functions within the device. These include power-on reset
and power-up clear handling, NMI source selection and management, reset interrupt vector generators
(see Table 6-11), bootloader entry mechanisms, and configuration management (device descriptors). SYS
also includes a data exchange mechanism using JTAG called a JTAG mailbox that can be used in the
application.
For further information, see the SYS Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)
(SLAU387).
Table 6-11. System Module Interrupt Vector Registers
INTERRUPT VECTOR
REGISTER
SYSRSTIV, System Reset
62
INTERRUPT EVENT
WORD ADDRESS
OFFSET
No interrupt pending
00h
Brownout (BOR)
02h
RST/NMI (BOR)
04h
PMMSWBOR (BOR)
06h
LPM3.5 or LPM4.5 wakeup (BOR)
08h
Security violation (BOR)
0Ah
SVSL (POR)
0Ch
SVSH (POR)
0Eh
SVML_OVP (POR)
SVMH_OVP (POR)
019Eh
Highest
10h
12h
PMMSWPOR (POR)
14h
WDT time-out (PUC)
16h
WDT key violation (PUC)
18h
KEYV flash key violation (PUC)
1Ah
Reserved
1Ch
Peripheral area fetch (PUC)
1Eh
PMM key violation (PUC)
20h
Reserved
22h to 3Eh
Detailed Description
PRIORITY
Lowest
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Table 6-11. System Module Interrupt Vector Registers (continued)
INTERRUPT VECTOR
REGISTER
INTERRUPT EVENT
WORD ADDRESS
No interrupt pending
00h
SVMLIFG
02h
SVMHIFG
04h
DLYLIFG
06h
DLYHIFG
SYSSNIV, System NMI
SYSUNIV, User NMI
SYSBERRIV, Bus Error
OFFSET
VMAIFG
0Ah
0Ch
JMBOUTIFG
0Eh
SVMLVLRIFG
10h
SVMHVLRIFG
12h
Reserved
14h to 1Eh
No interrupt pending
00h
NMIIFG
02h
OFIFG
019Ah
Highest
06h
08h
Reserved
0Ah to 1Eh
No interrupt pending
00h
02h
0198h
Lowest
04h
BUSIFG
Reserved
Highest
08h
019Ch
JMBINIFG
ACCVIFG
PRIORITY
Lowest
Highest
04h
MID error
06h
Reserved
08h to 1Eh
Lowest
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6.13.9 DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU
intervention. For example, the DMA controller can be used to move data from the ADC12_A conversion
memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA
controller reduces system power consumption by allowing the CPU to remain in sleep mode, without
having to awaken to move data to or from a peripheral.
For further information, see the DMA Controller Module (Chapter Excerpt From MSP430x5xx Family,
SLAU208) (SLAU395).
Table 6-12. DMA Trigger Assignments (1)
TRIGGER
CHANNEL
0
1
1
TA0CCR0 CCIFG
2
TA0CCR2 CCIFG
3
TA1CCR0 CCIFG
4
TA1CCR2 CCIFG
5
TA2CCR0 CCIFG
6
TA2CCR2 CCIFG
7
TBCCR0 CCIFG
8
TBCCR2 CCIFG
9
Reserved
10
Reserved
11
Reserved
12
UCA2RXIFG
13
UCA2TXIFG
14
UCB2RXIFG
15
UCB2TXIFG
16
UCA0RXIFG
17
UCA0TXIFG
18
UCB0RXIFG
19
UCB0TXIFG
20
UCA1RXIFG
21
UCA1TXIFG
22
UCB1RXIFG
23
UCB1TXIFG
24
ADC12IFGx
25
DAC12_0IFG
26
DAC12_1IFG
27
Reserved
28
Reserved
30
31
64
3
DMAREQ
29
(1)
2
0
4
5
DMA3IFG
DMA4IFG
MPY ready
DMA5IFG
DMA0IFG
DMA1IFG
DMA2IFG
DMAE0
Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers do not
cause any DMA trigger event when selected.
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6.13.10 Universal Serial Communication Interface (USCI)
The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3-pin or 4-pin) and I2C, and asynchronous communication
protocols such as UART, enhanced UART with automatic baudrate detection, and IrDA. Each USCI
module contains two portions, A and B.
The USCI_An module provides support for SPI (3-pin or 4-pin), UART, enhanced UART, or IrDA.
The USCI_Bn module provides support for SPI (3-pin or 4-pin) or I2C.
The MSP430F665x, MSP430F645x, MSP430F565x, MSP430F535x series includes three complete USCI
modules (n = 0 to 2).
For further information, see the following User's Guides:
• USCI UART Module (Chapter Excerpt From MSP430x5xx Family, SLAU208) (SLAU410)
• USCI SPI Module (Chapter Excerpt From MSP430x5xx Family, SLAU208) (SLAU411)
• USCI I2C Module (Chapter Excerpt From MSP430x5xx Family, SLAU208) (SLAU412)
6.13.11 Timer TA0
Timer TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers (see Table 6-13).
TA0 supports multiple capture/compares, PWM outputs, and interval timing. TA0 also has extensive
interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each
of the capture/compare registers.
For further information, see the Timer_A Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)
(SLAU400).
Table 6-13. Timer TA0 Signal Connections
INPUT PIN
NUMBER
DEVICE INPUT
SIGNAL
MODULE INPUT
SIGNAL
34-P1.0
TA0CLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
34-P1.0
TA0CLK
TACLK
35-P1.1
TA0.0
CCI0A
DVSS
CCI0B
DVSS
GND
DVCC
VCC
36-P1.2
TA0.1
CCI1A
40-P1.6
TA0.1
CCI1B
DVSS
GND
DVCC
VCC
37-P1.3
TA0.2
CCI2A
41-P1.7
TA0.2
CCI2B
DVSS
GND
38-P1.4
DVCC
VCC
TA0.3
CCI3A
DVSS
CCI3B
DVSS
GND
DVCC
VCC
MODULE BLOCK
Timer
MODULE
DEVICE OUTPUT
OUTPUT SIGNAL
SIGNAL
NA
OUTPUT PIN
NUMBER
NA
35-P1.1
CCR0
TA0
TA0.0
36-P1.2
40-P1.6
CCR1
TA1
TA0.1
ADC12_A
(internal)
ADC12SHSx = {1}
37-P1.3
CCR2
TA2
TA0.2
41-P1.7
38-P1.4
CCR3
TA3
TA0.3
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Table 6-13. Timer TA0 Signal Connections (continued)
66
INPUT PIN
NUMBER
DEVICE INPUT
SIGNAL
MODULE INPUT
SIGNAL
39-P1.5
TA0.4
CCI4A
DVSS
CCI4B
DVSS
GND
DVCC
VCC
MODULE BLOCK
MODULE
DEVICE OUTPUT
OUTPUT SIGNAL
SIGNAL
OUTPUT PIN
NUMBER
39-P1.5
CCR4
TA4
Detailed Description
TA0.4
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6.13.12 Timer TA1
Timer TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers (see Table 6-14).
TA1 supports multiple capture/compares, PWM outputs, and interval timing. TA1 also has extensive
interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each
of the capture/compare registers.
For further information, see the Timer_A Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)
(SLAU400).
Table 6-14. Timer TA1 Signal Connections
INPUT PIN
NUMBER
DEVICE INPUT
SIGNAL
MODULE INPUT
SIGNAL
42-P3.0
TA1CLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
42-P3.0
TA1CLK
TACLK
43-P3.1
TA1.0
CCI0A
DVSS
CCI0B
DVSS
GND
44-P3.2
45-P3.3
MODULE BLOCK
Timer
MODULE
DEVICE OUTPUT
OUTPUT SIGNAL
SIGNAL
NA
OUTPUT PIN
NUMBER
NA
43-P3.1
CCR0
TA0
TA1.0
DVCC
VCC
TA1.1
CCI1A
44-P3.2
CBOUT (internal)
CCI1B
DAC12_A
DAC12_0,
DAC12_1
(internal)
DVSS
GND
DVCC
VCC
TA1.2
CCI2A
ACLK (internal)
CCI2B
DVSS
GND
DVCC
VCC
CCR1
TA1
TA1.1
45-P3.3
CCR2
TA2
TA1.2
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6.13.13 Timer TA2
Timer TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers (see Table 6-15).
TA2 supports multiple capture/compares, PWM outputs, and interval timing. TA2 also has extensive
interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each
of the capture/compare registers.
For further information, see the Timer_A Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)
(SLAU400).
Table 6-15. Timer TA2 Signal Connections
INPUT PIN
NUMBER
DEVICE INPUT
SIGNAL
MODULE INPUT
SIGNAL
46-P3.4
TA2CLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
46-P3.4
TA2CLK
TACLK
47-P3.5
TA2.0
CCI0A
DVSS
CCI0B
DVSS
GND
48-P3.6
49-P3.7
68
DVCC
VCC
TA2.1
CCI1A
CBOUT (internal)
CCI1B
DVSS
GND
DVCC
VCC
TA2.2
CCI2A
ACLK (internal)
CCI2B
DVSS
GND
DVCC
VCC
MODULE BLOCK
Timer
MODULE
DEVICE OUTPUT
OUTPUT SIGNAL
SIGNAL
NA
OUTPUT PIN
NUMBER
NA
47-P3.5
CCR0
TA0
TA2.0
48-P3.6
CCR1
TA1
TA2.1
49-P3.7
CCR2
TA2
Detailed Description
TA2.2
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6.13.14 Timer TB0
Timer TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers (see Table 6-16).
TB0 supports multiple capture/compares, PWM outputs, and interval timing. TB0 also has extensive
interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each
of the capture/compare registers.
For further information, see the Timer_B Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)
(SLAU401).
Table 6-16. Timer TB0 Signal Connections
INPUT PIN
NUMBER
DEVICE INPUT
SIGNAL
MODULE INPUT
SIGNAL
58-P8.0
P2MAPx (1)
TB0CLK
TB0CLK
ACLK
ACLK
SMCLK
SMCLK
58-P8.0
P2MAPx (1)
TB0CLK
TB0CLK
50-P4.0
TB0.0
CCI0A
50-P4.0
P2MAPx (1)
TB0.0
CCI0B
P2MAPx (1)
DVSS
GND
Timer
CCR0
MODULE
DEVICE OUTPUT
OUTPUT SIGNAL
SIGNAL
NA
TB0
OUTPUT PIN
NUMBER
NA
TB0.0
ADC12 (internal)
ADC12SHSx = {2}
DVCC
VCC
51-P4.1
TB0.1
CCI1A
51-P4.1
P2MAPx (1)
TB0.1
CCI1B
P2MAPx (1)
DVSS
GND
52-P4.2
P2MAPx
(1)
53-P4.3
P2MAPx
(1)
MODULE BLOCK
(1)
CCR1
TB1
TB0.1
ADC12 (internal)
ADC12SHSx = {3}
DVCC
VCC
TB0.2
CCI2A
52-P4.2
TB0.2
CCI2B
P2MAPx (1)
DVSS
GND
DVCC
VCC
TB0.3
CCI3A
TB0.3
CCI3B
CCR2
TB2
TB0.2
DAC12_A
DAC12_0,
DAC12_1
(internal)
53-P4.3
CCR3
TB3
TB0.3
P2MAPx (1)
DVSS
GND
DVCC
VCC
54-P4.4
TB0.4
CCI4A
54-P4.4
P2MAPx (1)
TB0.4
CCI4B
P2MAPx (1)
DVSS
GND
DVCC
VCC
55-P4.5
TB0.5
CCI5A
55-P4.5
P2MAPx (1)
TB0.5
CCI5B
P2MAPx (1)
DVSS
GND
CCR4
CCR5
TB4
TB5
TB0.4
TB0.5
DVCC
VCC
56-P4.6
TB0.6
CCI6A
56-P4.6
P2MAPx (1)
TB0.6
CCI6B
P2MAPx (1)
DVSS
GND
DVCC
VCC
CCR6
TB6
TB0.6
Timer functions are selectable through the port mapping controller.
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6.13.15 Comparator_B
The primary function of the Comparator_B module is to support precision slope analog-to-digital
conversions, battery voltage supervision, and monitoring of external analog signals.
For further information, see the COMP_B Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)
(SLAU408).
6.13.16 ADC12_A
The ADC12_A module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit
SAR core, sample select control, reference generator, and a 16 word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored
without any CPU intervention.
For further information, see the ADC12_A Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)
(SLAU406).
6.13.17 DAC12_A
The DAC12_A module is a 12-bit, R-ladder, voltage output DAC. The DAC12_A may be used in 8-bit or
12-bit mode, and may be used in conjunction with the DMA controller. When multiple DAC12_A modules
are present, they may be grouped together for synchronous operation.
6.13.18 CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used
for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
For further information, see the CRC Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)
(SLAU398).
6.13.19 Voltage Reference (REF) Module
The REF module is responsible for generation of all critical reference voltages that can be used by the
various analog peripherals in the device.
For further information, see the REF Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)
(SLAU405).
6.13.20 LCD_B
The LCD_B driver generates the segment and common signals that are required to drive a liquid crystal
display (LCD). The LCD_B controller has dedicated data memories to hold segment drive information.
Common and segment signals are generated as defined by the mode. Static, 2-mux, 3-mux, and 4-mux
LCDs are supported. The module can provide a LCD voltage independent of the supply voltage with its
integrated charge pump. It is possible to control the level of the LCD voltage, and thus contrast, by
software. The module also provides an automatic blinking capability for individual segments.
The LCD_B module is only available on the MSP430F665x and MSP430F645x devices.
For further information, see the LCD_B Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)
(SLAU409).
6.13.21 LDO and PU Port
The integrated 3.3-V power system incorporates an integrated 3.3-V LDO regulator that allows the entire
MSP430 microcontroller to be powered from nominal 5-V LDOI when it is made available for the system.
Alternatively, the power system can supply power only to other components within the system, or it can be
unused altogether.
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The Port U Pins (PU.0 and PU.1) function as general-purpose high-current I/O pins. These pins can only
be configured together as either both inputs or both outputs. Port U is supplied by the LDOO rail. If the
3.3-V LDO is not being used in the system (disabled), the LDOO pin can be supplied externally.
The LDO-PWR module (LDO and PU Port) is only available on the MSP430F645x and MSP430F535x
devices.
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6.13.22 Embedded Emulation Module (EEM) (L Version)
The EEM supports real-time in-system debugging. The L version of the EEM has the following features:
• Eight hardware triggers or breakpoints on memory access
• Two hardware triggers or breakpoints on CPU register write access
• Up to ten hardware triggers can be combined to form complex triggers or breakpoints
• Two cycle counters
• Sequencer
• State storage
• Clock control on module level
For further information, see the EEM Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)
(SLAU414).
6.13.23 Peripheral File Map
Table 6-17 lists the base register address for each available peripheral.
Table 6-17. Peripherals
(1)
72
MODULE NAME
BASE ADDRESS
OFFSET ADDRESS RANGE (1)
Special Functions (see Table 6-18)
0100h
000h-01Fh
PMM (see Table 6-19)
0120h
000h-010h
Flash Control (see Table 6-20)
0140h
000h-00Fh
CRC16 (see Table 6-21)
0150h
000h-007h
RAM Control (see Table 6-22)
0158h
000h-001h
Watchdog (see Table 6-23)
015Ch
000h-001h
UCS (see Table 6-24)
0160h
000h-01Fh
SYS (see Table 6-25)
0180h
000h-01Fh
Shared Reference (see Table 6-26)
01B0h
000h-001h
000h-003h
Port Mapping Control (see Table 6-27)
01C0h
Port Mapping Port P2 (see Table 6-27)
01D0h
000h-007h
Port P1, P2 (see Table 6-28)
0200h
000h-01Fh
Port P3, P4 (see Table 6-29)
0220h
000h-01Fh
Port P5, P6 (see Table 6-30)
0240h
000h-00Bh
Port P7, P8 (see Table 6-31)
0260h
000h-00Bh
Port P9 (see Table 6-32)
0280h
000h-00Bh
Port PJ (see Table 6-33)
0320h
000h-01Fh
Timer TA0 (see Table 6-34)
0340h
000h-02Eh
Timer TA1 (see Table 6-35)
0380h
000h-02Eh
Timer TB0 (see Table 6-36)
03C0h
000h-02Eh
Timer TA2 (see Table 6-37)
0400h
000h-02Eh
Battery Backup (see Table 6-38)
0480h
000h-01Fh
RTC_B (see Table 6-39)
04A0h
000h-01Fh
32-Bit Hardware Multiplier (see Table 6-40)
04C0h
000h-02Fh
DMA General Control (see Table 6-41)
0500h
000h-00Fh
DMA Channel 0 (see Table 6-41)
0510h
000h-00Ah
DMA Channel 1 (see Table 6-41)
0520h
000h-00Ah
DMA Channel 2 (see Table 6-41)
0530h
000h-00Ah
DMA Channel 3 (see Table 6-41)
0540h
000h-00Ah
For a detailed description of the individual control register offset addresses, see the MSP430F5xx and MSP430F6xx Family User's
Guide (SLAU208).
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Table 6-17. Peripherals (continued)
MODULE NAME
BASE ADDRESS
OFFSET ADDRESS RANGE (1)
DMA Channel 4 (see Table 6-41)
0550h
000h-00Ah
DMA Channel 5 (see Table 6-41)
0560h
000h-00Ah
USCI_A0 (see Table 6-42)
05C0h
000h-01Fh
USCI_B0 (see Table 6-43)
05E0h
000h-01Fh
USCI_A1 (see Table 6-44)
0600h
000h-01Fh
USCI_B1 (see Table 6-45)
0620h
000h-01Fh
USCI_A2 (see Table 6-46)
0640h
000h-01Fh
USCI_B2 (see Table 6-47)
0660h
000h-01Fh
ADC12_A (see Table 6-48)
0700h
000h-03Fh
DAC12_A (see Table 6-49)
0780h
000h-01Fh
Comparator_B (see Table 6-50)
08C0h
000h-00Fh
LDO-PWR; LDO and Port U configuration (see Table 6-51)
LCD_B control (see Table 6-52)
(2)
(3)
(3)
(2)
0900h
000h-014h
0A00h
000h-05Fh
Only on devices with peripheral module LDO-PWR.
Only on devices with peripheral module LCD_B.
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Table 6-18. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
REGISTER
OFFSET
SFR interrupt enable
SFRIE1
00h
SFR interrupt flag
SFRIFG1
02h
SFR reset pin control
SFRRPCR
04h
Table 6-19. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
REGISTER
OFFSET
PMM control 0
PMMCTL0
00h
PMM control 1
PMMCTL1
02h
SVS high-side control
SVSMHCTL
04h
SVS low-side control
SVSMLCTL
06h
PMM interrupt flags
PMMIFG
0Ch
PMM interrupt enable
PMMIE
0Eh
PMM power mode 5 control
PM5CTL0
10h
Table 6-20. Flash Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Flash control 1
FCTL1
00h
Flash control 3
FCTL3
04h
Flash control 4
FCTL4
06h
Table 6-21. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
REGISTER
OFFSET
CRC data input
CRC16DI
00h
CRC result
CRC16INIRES
04h
Table 6-22. RAM Control Registers (Base Address: 0158h)
REGISTER DESCRIPTION
RAM control 0
REGISTER
RCCTL0
OFFSET
00h
Table 6-23. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
Watchdog timer control
REGISTER
WDTCTL
OFFSET
00h
Table 6-24. UCS Registers (Base Address: 0160h)
REGISTER DESCRIPTION
REGISTER
OFFSET
UCS control 0
UCSCTL0
00h
UCS control 1
UCSCTL1
02h
UCS control 2
UCSCTL2
04h
UCS control 3
UCSCTL3
06h
UCS control 4
UCSCTL4
08h
UCS control 5
UCSCTL5
0Ah
UCS control 6
UCSCTL6
0Ch
UCS control 7
UCSCTL7
0Eh
UCS control 8
UCSCTL8
10h
74
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Table 6-25. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
OFFSET
System control
SYSCTL
00h
Bootloader configuration area
SYSBSLC
02h
JTAG mailbox control
SYSJMBC
06h
JTAG mailbox input 0
SYSJMBI0
08h
JTAG mailbox input 1
SYSJMBI1
0Ah
JTAG mailbox output 0
SYSJMBO0
0Ch
JTAG mailbox output 1
SYSJMBO1
0Eh
Bus error vector generator
SYSBERRIV
18h
User NMI vector generator
SYSUNIV
1Ah
System NMI vector generator
SYSSNIV
1Ch
Reset vector generator
SYSRSTIV
1Eh
Table 6-26. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
Shared reference control
REGISTER
OFFSET
REFCTL
00h
Table 6-27. Port Mapping Registers
(Base Address of Port Mapping Control: 01C0h, Port P4: 01D0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port mapping password
PMAPPWD
00h
Port mapping control
PMAPCTL
02h
Port P2.0 mapping
P2MAP0
00h
Port P2.1 mapping
P2MAP1
01h
Port P2.2 mapping
P2MAP2
02h
Port P2.3 mapping
P2MAP3
03h
Port P2.4 mapping
P2MAP4
04h
Port P2.5 mapping
P2MAP5
05h
Port P2.6 mapping
P2MAP6
06h
Port P2.7 mapping
P2MAP7
07h
Table 6-28. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P1 input
P1IN
00h
Port P1 output
P1OUT
02h
Port P1 direction
P1DIR
04h
Port P1 pullup/pulldown enable
P1REN
06h
Port P1 drive strength
P1DS
08h
Port P1 selection
P1SEL
0Ah
Port P1 interrupt vector word
P1IV
0Eh
Port P1 interrupt edge select
P1IES
18h
Port P1 interrupt enable
P1IE
1Ah
Port P1 interrupt flag
P1IFG
1Ch
Port P2 input
P2IN
01h
Port P2 output
P2OUT
03h
Port P2 direction
P2DIR
05h
Port P2 pullup/pulldown enable
P2REN
07h
Detailed Description
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Table 6-28. Port P1, P2 Registers (Base Address: 0200h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P2 drive strength
P2DS
09h
Port P2 selection
P2SEL
0Bh
Port P2 interrupt vector word
P2IV
1Eh
Port P2 interrupt edge select
P2IES
19h
Port P2 interrupt enable
P2IE
1Bh
Port P2 interrupt flag
P2IFG
1Dh
Table 6-29. Port P3, P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3 input
P3IN
00h
Port P3 output
P3OUT
02h
Port P3 direction
P3DIR
04h
Port P3 pullup/pulldown enable
P3REN
06h
Port P3 drive strength
P3DS
08h
Port P3 selection
P3SEL
0Ah
Port P3 interrupt vector word
P3IV
0Eh
Port P3 interrupt edge select
P3IES
18h
Port P3 interrupt enable
P3IE
1Ah
Port P3 interrupt flag
P3IFG
1Ch
Port P4 input
P4IN
01h
Port P4 output
P4OUT
03h
Port P4 direction
P4DIR
05h
Port P4 pullup/pulldown enable
P4REN
07h
Port P4 drive strength
P4DS
09h
Port P4 selection
P4SEL
0Bh
Port P4 interrupt vector word
P4IV
1Eh
Port P4 interrupt edge select
P4IES
19h
Port P4 interrupt enable
P4IE
1Bh
Port P4 interrupt flag
P4IFG
1Dh
Table 6-30. Port P5, P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P5 input
P5IN
00h
Port P5 output
P5OUT
02h
Port P5 direction
P5DIR
04h
Port P5 pullup/pulldown enable
P5REN
06h
Port P5 drive strength
P5DS
08h
Port P5 selection
P5SEL
0Ah
Port P6 input
P6IN
01h
Port P6 output
P6OUT
03h
Port P6 direction
P6DIR
05h
Port P6 pullup/pulldown enable
P6REN
07h
Port P6 drive strength
P6DS
09h
Port P6 selection
P6SEL
0Bh
76
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Table 6-31. Port P7, P8 Registers (Base Address: 0260h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P7 input
P7IN
00h
Port P7 output
P7OUT
02h
Port P7 direction
P7DIR
04h
Port P7 pullup/pulldown enable
P7REN
06h
Port P7 drive strength
P7DS
08h
Port P7 selection
P7SEL
0Ah
Port P8 input
P8IN
01h
Port P8 output
P8OUT
03h
Port P8 direction
P8DIR
05h
Port P8 pullup/pulldown enable
P8REN
07h
Port P8 drive strength
P8DS
09h
Port P8 selection
P8SEL
0Bh
Table 6-32. Port P9 Register (Base Address: 0280h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P9 input
P9IN
00h
Port P9 output
P9OUT
02h
Port P9 direction
P9DIR
04h
Port P9 pullup/pulldown enable
P9REN
06h
Port P9 drive strength
P9DS
08h
Port P9 selection
P9SEL
0Ah
Table 6-33. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port PJ input
PJIN
00h
Port PJ output
PJOUT
02h
Port PJ direction
PJDIR
04h
Port PJ pullup/pulldown enable
PJREN
06h
Port PJ drive strength
PJDS
08h
Table 6-34. TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA0 control
TA0CTL
00h
Capture/compare control 0
TA0CCTL0
02h
Capture/compare control 1
TA0CCTL1
04h
Capture/compare control 2
TA0CCTL2
06h
Capture/compare control 3
TA0CCTL3
08h
Capture/compare control 4
TA0CCTL4
0Ah
TA0 counter
TA0R
10h
Capture/compare 0
TA0CCR0
12h
Capture/compare 1
TA0CCR1
14h
Capture/compare 2
TA0CCR2
16h
Capture/compare 3
TA0CCR3
18h
Capture/compare 4
TA0CCR4
1Ah
TA0 expansion 0
TA0EX0
20h
TA0 interrupt vector
TA0IV
2Eh
Detailed Description
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Table 6-35. TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA1 control
TA1CTL
00h
Capture/compare control 0
TA1CCTL0
02h
Capture/compare control 1
TA1CCTL1
04h
Capture/compare control 2
TA1CCTL2
06h
TA1 counter
TA1R
10h
Capture/compare 0
TA1CCR0
12h
Capture/compare 1
TA1CCR1
14h
Capture/compare 2
TA1CCR2
16h
TA1 expansion 0
TA1EX0
20h
TA1 interrupt vector
TA1IV
2Eh
Table 6-36. TB0 Registers (Base Address: 03C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TB0 control
TB0CTL
00h
Capture/compare control 0
TB0CCTL0
02h
Capture/compare control 1
TB0CCTL1
04h
Capture/compare control 2
TB0CCTL2
06h
Capture/compare control 3
TB0CCTL3
08h
Capture/compare control 4
TB0CCTL4
0Ah
Capture/compare control 5
TB0CCTL5
0Ch
Capture/compare control 6
TB0CCTL6
0Eh
TB0 counter
TB0R
10h
Capture/compare 0
TB0CCR0
12h
Capture/compare 1
TB0CCR1
14h
Capture/compare 2
TB0CCR2
16h
Capture/compare 3
TB0CCR3
18h
Capture/compare 4
TB0CCR4
1Ah
Capture/compare 5
TB0CCR5
1Ch
Capture/compare 6
TB0CCR6
1Eh
TB0 expansion 0
TB0EX0
20h
TB0 interrupt vector
TB0IV
2Eh
Table 6-37. TA2 Registers (Base Address: 0400h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA2 control
TA2CTL
00h
Capture/compare control 0
TA2CCTL0
02h
Capture/compare control 1
TA2CCTL1
04h
Capture/compare control 2
TA2CCTL2
06h
TA2 counter
TA2R
10h
Capture/compare 0
TA2CCR0
12h
Capture/compare 1
TA2CCR1
14h
Capture/compare 2
TA2CCR2
16h
TA2 expansion 0
TA2EX0
20h
TA2 interrupt vector
TA2IV
2Eh
78
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Table 6-38. Battery Backup Registers (Base Address: 0480h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Battery backup memory 0
BAKMEM0
00h
Battery backup memory 1
BAKMEM1
02h
Battery backup memory 2
BAKMEM2
04h
Battery backup memory 3
BAKMEM3
06h
Battery backup control
BAKCTL
1Ch
Battery charger control
BAKCHCTL
1Eh
Table 6-39. Real-Time Clock Registers (Base Address: 04A0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
RTC control 0
RTCCTL0
00h
RTC control 1
RTCCTL1
01h
RTC control 2
RTCCTL2
02h
RTC control 3
RTCCTL3
03h
RTC prescaler 0 control
RTCPS0CTL
08h
RTC prescaler 1 control
RTCPS1CTL
0Ah
RTC prescaler 0
RTCPS0
0Ch
RTC prescaler 1
RTCPS1
0Dh
RTC interrupt vector word
RTCIV
0Eh
RTC seconds
RTCSEC
10h
RTC minutes
RTCMIN
11h
RTC hours
RTCHOUR
12h
RTC day of week
RTCDOW
13h
RTC days
RTCDAY
14h
RTC month
RTCMON
15h
RTC year low
RTCYEARL
16h
RTC year high
RTCYEARH
17h
RTC alarm minutes
RTCAMIN
18h
RTC alarm hours
RTCAHOUR
19h
RTC alarm day of week
RTCADOW
1Ah
RTC alarm days
RTCADAY
1Bh
Binary-to-BCD conversion
BIN2BCD
1Ch
BCD-to-binary conversion
BCD2BIN
1Eh
Table 6-40. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
16-bit operand 1 – multiply
MPY
00h
16-bit operand 1 – signed multiply
MPYS
02h
16-bit operand 1 – multiply accumulate
MAC
04h
16-bit operand 1 – signed multiply accumulate
MACS
06h
16-bit operand 2
OP2
08h
16 × 16 result low word
RESLO
0Ah
16 × 16 result high word
RESHI
0Ch
16 × 16 sum extension
SUMEXT
0Eh
32-bit operand 1 – multiply low word
MPY32L
10h
32-bit operand 1 – multiply high word
MPY32H
12h
32-bit operand 1 – signed multiply low word
MPYS32L
14h
32-bit operand 1 – signed multiply high word
MPYS32H
16h
Detailed Description
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Table 6-40. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
32-bit operand 1 – multiply accumulate low word
MAC32L
18h
32-bit operand 1 – multiply accumulate high word
MAC32H
1Ah
32-bit operand 1 – signed multiply accumulate low word
MACS32L
1Ch
32-bit operand 1 – signed multiply accumulate high word
MACS32H
1Eh
32-bit operand 2 – low word
OP2L
20h
32-bit operand 2 – high word
OP2H
22h
32 × 32 result 0 – least significant word
RES0
24h
32 × 32 result 1
RES1
26h
32 × 32 result 2
RES2
28h
32 × 32 result 3 – most significant word
RES3
2Ah
MPY32 control 0
MPY32CTL0
2Ch
Table 6-41. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h, DMA Channel 3: 0540h, DMA
Channel 4: 0550h, DMA Channel 5: 0560h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA general control: DMA module control 0
DMACTL0
00h
DMA general control: DMA module control 1
DMACTL1
02h
DMA general control: DMA module control 2
DMACTL2
04h
DMA general control: DMA module control 3
DMACTL3
06h
DMA general control: DMA module control 4
DMACTL4
08h
DMA general control: DMA interrupt vector
DMAIV
0Ah
DMA channel 0 control
DMA0CTL
00h
DMA channel 0 source address low
DMA0SAL
02h
DMA channel 0 source address high
DMA0SAH
04h
DMA channel 0 destination address low
DMA0DAL
06h
DMA channel 0 destination address high
DMA0DAH
08h
DMA channel 0 transfer size
DMA0SZ
0Ah
DMA channel 1 control
DMA1CTL
00h
DMA channel 1 source address low
DMA1SAL
02h
DMA channel 1 source address high
DMA1SAH
04h
DMA channel 1 destination address low
DMA1DAL
06h
DMA channel 1 destination address high
DMA1DAH
08h
DMA channel 1 transfer size
DMA1SZ
0Ah
DMA channel 2 control
DMA2CTL
00h
DMA channel 2 source address low
DMA2SAL
02h
DMA channel 2 source address high
DMA2SAH
04h
DMA channel 2 destination address low
DMA2DAL
06h
DMA channel 2 destination address high
DMA2DAH
08h
DMA channel 2 transfer size
DMA2SZ
0Ah
DMA channel 3 control
DMA3CTL
00h
DMA channel 3 source address low
DMA3SAL
02h
DMA channel 3 source address high
DMA3SAH
04h
DMA channel 3 destination address low
DMA3DAL
06h
DMA channel 3 destination address high
DMA3DAH
08h
DMA channel 3 transfer size
DMA3SZ
0Ah
DMA channel 4 control
DMA4CTL
00h
80
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Table 6-41. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h, DMA Channel 3: 0540h, DMA
Channel 4: 0550h, DMA Channel 5: 0560h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA channel 4 source address low
DMA4SAL
02h
DMA channel 4 source address high
DMA4SAH
04h
DMA channel 4 destination address low
DMA4DAL
06h
DMA channel 4 destination address high
DMA4DAH
08h
DMA channel 4 transfer size
DMA4SZ
0Ah
DMA channel 5 control
DMA5CTL
00h
DMA channel 5 source address low
DMA5SAL
02h
DMA channel 5 source address high
DMA5SAH
04h
DMA channel 5 destination address low
DMA5DAL
06h
DMA channel 5 destination address high
DMA5DAH
08h
DMA channel 5 transfer size
DMA5SZ
0Ah
Table 6-42. USCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI control 0
UCA0CTL0
00h
USCI control 1
UCA0CTL1
01h
USCI baud rate 0
UCA0BR0
06h
USCI baud rate 1
UCA0BR1
07h
USCI modulation control
UCA0MCTL
08h
USCI status
UCA0STAT
0Ah
USCI receive buffer
UCA0RXBUF
0Ch
USCI transmit buffer
UCA0TXBUF
0Eh
USCI LIN control
UCA0ABCTL
10h
USCI IrDA transmit control
UCA0IRTCTL
12h
USCI IrDA receive control
UCA0IRRCTL
13h
USCI interrupt enable
UCA0IE
1Ch
USCI interrupt flags
UCA0IFG
1Dh
USCI interrupt vector word
UCA0IV
1Eh
Table 6-43. USCI_B0 Registers (Base Address: 05E0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI synchronous control 0
UCB0CTL0
00h
USCI synchronous control 1
UCB0CTL1
01h
USCI synchronous bit rate 0
UCB0BR0
06h
USCI synchronous bit rate 1
UCB0BR1
07h
USCI synchronous status
UCB0STAT
0Ah
USCI synchronous receive buffer
UCB0RXBUF
0Ch
USCI synchronous transmit buffer
UCB0TXBUF
0Eh
USCI I2C own address
UCB0I2COA
10h
USCI I2C slave address
UCB0I2CSA
12h
USCI interrupt enable
UCB0IE
1Ch
USCI interrupt flags
UCB0IFG
1Dh
USCI interrupt vector word
UCB0IV
1Eh
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Table 6-44. USCI_A1 Registers (Base Address: 0600h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI control 0
UCA1CTL0
00h
USCI control 1
UCA1CTL1
01h
USCI baud rate 0
UCA1BR0
06h
USCI baud rate 1
UCA1BR1
07h
USCI modulation control
UCA1MCTL
08h
USCI status
UCA1STAT
0Ah
USCI receive buffer
UCA1RXBUF
0Ch
USCI transmit buffer
UCA1TXBUF
0Eh
USCI LIN control
UCA1ABCTL
10h
USCI IrDA transmit control
UCA1IRTCTL
12h
USCI IrDA receive control
UCA1IRRCTL
13h
USCI interrupt enable
UCA1IE
1Ch
USCI interrupt flags
UCA1IFG
1Dh
USCI interrupt vector word
UCA1IV
1Eh
Table 6-45. USCI_B1 Registers (Base Address: 0620h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI synchronous control 0
UCB1CTL0
00h
USCI synchronous control 1
UCB1CTL1
01h
USCI synchronous bit rate 0
UCB1BR0
06h
USCI synchronous bit rate 1
UCB1BR1
07h
USCI synchronous status
UCB1STAT
0Ah
USCI synchronous receive buffer
UCB1RXBUF
0Ch
USCI synchronous transmit buffer
UCB1TXBUF
0Eh
USCI I2C own address
UCB1I2COA
10h
USCI I2C slave address
UCB1I2CSA
12h
USCI interrupt enable
UCB1IE
1Ch
USCI interrupt flags
UCB1IFG
1Dh
USCI interrupt vector word
UCB1IV
1Eh
Table 6-46. USCI_A2 Registers (Base Address: 0640h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI control 0
UCA2CTL0
00h
USCI control 1
UCA2CTL1
01h
USCI baud rate 0
UCA2BR0
06h
USCI baud rate 1
UCA2BR1
07h
USCI modulation control
UCA2MCTL
08h
USCI status
UCA2STAT
0Ah
USCI receive buffer
UCA2RXBUF
0Ch
USCI transmit buffer
UCA2TXBUF
0Eh
USCI LIN control
UCA2ABCTL
10h
USCI IrDA transmit control
UCA2IRTCTL
12h
USCI IrDA receive control
UCA2IRRCTL
13h
USCI interrupt enable
UCA2IE
1Ch
USCI interrupt flags
UCA2IFG
1Dh
USCI interrupt vector word
UCA2IV
1Eh
82
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Table 6-47. USCI_B2 Registers (Base Address: 0660h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI synchronous control 0
UCB2CTL0
00h
USCI synchronous control 1
UCB2CTL1
01h
USCI synchronous bit rate 0
UCB2BR0
06h
USCI synchronous bit rate 1
UCB2BR1
07h
USCI synchronous status
UCB2STAT
0Ah
USCI synchronous receive buffer
UCB2RXBUF
0Ch
USCI synchronous transmit buffer
UCB2TXBUF
0Eh
USCI I2C own address
UCB2I2COA
10h
USCI I2C slave address
UCB2I2CSA
12h
USCI interrupt enable
UCB2IE
1Ch
USCI interrupt flags
UCB2IFG
1Dh
USCI interrupt vector word
UCB2IV
1Eh
Table 6-48. ADC12_A Registers (Base Address: 0700h)
REGISTER DESCRIPTION
REGISTER
OFFSET
ADC12 control 0
ADC12CTL0
00h
ADC12 control 1
ADC12CTL1
02h
ADC12 control 2
ADC12CTL2
04h
Interrupt flag
ADC12IFG
0Ah
Interrupt enable
ADC12IE
0Ch
Interrupt vector word
ADC12IV
0Eh
ADC memory control 0
ADC12MCTL0
10h
ADC memory control 1
ADC12MCTL1
11h
ADC memory control 2
ADC12MCTL2
12h
ADC memory control 3
ADC12MCTL3
13h
ADC memory control 4
ADC12MCTL4
14h
ADC memory control 5
ADC12MCTL5
15h
ADC memory control 6
ADC12MCTL6
16h
ADC memory control 7
ADC12MCTL7
17h
ADC memory control 8
ADC12MCTL8
18h
ADC memory control 9
ADC12MCTL9
19h
ADC memory control 10
ADC12MCTL10
1Ah
ADC memory control 11
ADC12MCTL11
1Bh
ADC memory control 12
ADC12MCTL12
1Ch
ADC memory control 13
ADC12MCTL13
1Dh
ADC memory control 14
ADC12MCTL14
1Eh
ADC memory control 15
ADC12MCTL15
1Fh
Conversion memory 0
ADC12MEM0
20h
Conversion memory 1
ADC12MEM1
22h
Conversion memory 2
ADC12MEM2
24h
Conversion memory 3
ADC12MEM3
26h
Conversion memory 4
ADC12MEM4
28h
Conversion memory 5
ADC12MEM5
2Ah
Conversion memory 6
ADC12MEM6
2Ch
Conversion memory 7
ADC12MEM7
2Eh
Conversion memory 8
ADC12MEM8
30h
Conversion memory 9
ADC12MEM9
32h
Detailed Description
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Table 6-48. ADC12_A Registers (Base Address: 0700h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
Conversion memory 10
ADC12MEM10
34h
Conversion memory 11
ADC12MEM11
36h
Conversion memory 12
ADC12MEM12
38h
Conversion memory 13
ADC12MEM13
3Ah
Conversion memory 14
ADC12MEM14
3Ch
Conversion memory 15
ADC12MEM15
3Eh
Table 6-49. DAC12_A Registers (Base Address: 0780h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DAC12_A channel 0 control 0
DAC12_0CTL0
00h
DAC12_A channel 0 control 1
DAC12_0CTL1
02h
DAC12_A channel 0 data
DAC12_0DAT
04h
DAC12_A channel 0 calibration control
DAC12_0CALCTL
06h
DAC12_A channel 0 calibration data
DAC12_0CALDAT
08h
DAC12_A channel 1 control 0
DAC12_1CTL0
10h
DAC12_A channel 1 control 1
DAC12_1CTL1
12h
DAC12_A channel 1 data
DAC12_1DAT
14h
DAC12_A channel 1 calibration control
DAC12_1CALCTL
16h
DAC12_A channel 1 calibration data
DAC12_1CALDAT
18h
DAC12_A interrupt vector word
DAC12IV
1Eh
Table 6-50. Comparator_B Registers (Base Address: 08C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Comp_B control 0
CBCTL0
00h
Comp_B control 1
CBCTL1
02h
Comp_B control 2
CBCTL2
04h
Comp_B control 3
CBCTL3
06h
Comp_B interrupt
CBINT
0Ch
Comp_B interrupt vector word
CBIV
0Eh
Table 6-51. LDO and Port U Configuration Registers (Base Address: 0900h)
REGISTER DESCRIPTION
REGISTER
OFFSET
LDO key/ID
LDOKEYID
00h
PU port control
PUCTL
04h
LDO power control
LDOPWRCTL
08h
Table 6-52. LCD_B Registers (Base Address: 0A00h)
REGISTER DESCRIPTION
REGISTER
OFFSET
LCD_B control 0
LCDBCTL0
000h
LCD_B control 1
LCDBCTL1
002h
LCD_B blinking control
LCDBBLKCTL
004h
LCD_B memory control
LCDBMEMCTL
006h
LCD_B voltage control
LCDBVCTL
008h
LCD_B port control 0
LCDBPCTL0
00Ah
LCD_B port control 1
LCDBPCTL1
00Ch
LCD_B port control 2
LCDBPCTL2
00Eh
84
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Table 6-52. LCD_B Registers (Base Address: 0A00h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
LCD_B charge pump control
LCDBCTL0
012h
LCD_B interrupt vector word
LCDBIV
01Eh
LCD_B memory 1
LCDM1
020h
LCD_B memory 2
LCDM2
021h
⋮
⋮
⋮
LCD_B memory 22
LCDM22
035h
LCD_B blinking memory 1
LCDBM1
040h
LCD_B blinking memory 2
LCDBM2
041h
⋮
LCD_B blinking memory 22
⋮
LCDBM22
⋮
055h
Detailed Description
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6.14 Input/Output Schematics
6.14.1 Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
Figure 6-2 shows the port schematic. summarizes selection of the pin function.
Pad Logic
S32...S39
LCDS32...LCDS39
P1REN.x
P1DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P1OUT.x
DVSS
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1IN.x
Bus
Keeper
EN
P1.0/TA0CLK/ACLK/S39
P1.1/TA0.0/S38
P1.2/TA0.1/S37
P1.3/TA0.2/S36
P1.4/TA0.3/S35
P1.5/TA0.4/S34
P1.6/TA0.1/S33
P1.7/TA0.2/S32
D
Module X IN
P1IE.x
EN
P1IRQ.x
Q
P1IFG.x
P1SEL.x
P1IES.x
Set
Interrupt
Edge
Select
Figure 6-2. Port P1 (P1.0 to P1.7) Schematic
86
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Port P1 (P1.0 to P1.7) Pin Functions
PIN NAME (P1.x)
x
FUNCTION
P1.0 (I/O)
P1.0/TA0CLK/ACLK/
S39
0
2
0
0
1
0
ACLK
1
1
0
Timer TA0.CCI0A capture input
3
4
5
(1)
7
0
1
0
1
I: 0; O: 1
0
0
0
1
0
Timer TA0.CCI1A capture input
Timer TA0.1 output
1
1
0
S37
X
X
1
I: 0; O: 1
0
0
Timer TA0.CCI2A capture input
0
1
0
Timer TA0.2 output
1
1
0
S36
X
X
1
I: 0; O: 1
0
0
Timer TA0.CCI3A capture input
0
1
0
Timer TA0.3 output
1
1
0
S35
X
X
1
I: 0; O: 1
0
0
Timer TA0.CCI4A capture input
0
1
0
Timer TA0.4 output
1
1
0
Timer TA0.CCI1B capture input
X
X
1
I: 0; O: 1
0
0
0
1
0
Timer TA0.1 output
1
1
0
S33
X
X
1
I: 0; O: 1
0
0
0
1
0
P1.7 (I/O)
P1.7/TA0.2/S32
1
X
P1.6 (I/O)
6
0
0
1
S34
P1.6/TA0.1/S33
1
0
X
P1.5 (I/O)
P1.5/TA0.4/S34
X
S38
P1.4 (I/O)
P1.4/TA0.3/S35
X
I: 0; O: 1
Timer TA0.0 output
P1.3 (I/O)
P1.3/TA0.2/S36
LCDS32...39
0
P1.2 (I/O)
P1.2/TA0.1/S37
P1SEL.x
I: 0; O: 1
P1.1 (I/O)
1
P1DIR.x
Timer TA0.TA0CLK
S39
P1.1/TA0.0/S38
CONTROL BITS OR SIGNALS (1)
Timer TA0.CCI2B capture input
Timer TA0.2 output
1
1
0
S32
X
X
1
X = Don't care
Detailed Description
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6.14.2 Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger
Figure 6-3 shows the port schematic. summarizes selection of the pin function.
Pad Logic
To LCD_B
From LCD_B
P2REN.x
P2DIR.x
0
From Port Mapping
1
P2OUT.x
0
From Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2IN.x
From Port Mapping
P2.0/P2MAP0
P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5
P2.6/P2MAP6/R03
P2.7/P2MAP7/LCDREF/R13
EN
D
To Port Mapping
P2IE.x
EN
P2IRQ.x
Q
P2IFG.x
P2SEL.x
P2IES.x
Set
Interrupt
Edge
Select
Figure 6-3. Port P2 (P2.0 to P2.7) Schematic
88
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Port P2 (P2.0 to P2.7) Pin Functions
PIN NAME (P2.x)
P2.0/P2MAP0
P2.1/P2MAP1
x
0
1
P2.2/P2MAP2
2
P2.3/P2MAP3
3
P2.4/P2MAP4
4
P2.5/P2MAP5
5
FUNCTION
P2.0 (I/O)
Mapped secondary digital function
P2.1 (I/O)
Mapped secondary digital function
6
(1)
7
P2SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
P2MAPx
≤ 19
≤ 19
X
1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
Mapped secondary digital function
X
1
≤ 19
R03
X
1
= 31
I: 0; O: 1
0
Mapped secondary digital function
X
1
≤ 19
LCDREF/R13
X
1
= 31
Mapped secondary digital function
P2.3 (I/O)
Mapped secondary digital function
P2.4 (I/O)
Mapped secondary digital function
P2.5 (I/O
Mapped secondary digital function
P2.7 (I/O)
P2.7/P2MAP7/
LCDREF/R13
P2DIR.x
I: 0; O: 1
P2.2 (I/O)
P2.6 (I/O)
P2.6/P2MAP6/R03
CONTROL BITS OR SIGNALS (1)
≤ 19
≤ 19
≤ 19
≤ 19
X = Don't care
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6.14.3 Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger
Figure 6-4 shows the port schematic. summarizes selection of the pin function.
Pad Logic
S24...S31
LCDS24...LCDS31
P3REN.x
P3DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P3OUT.x
DVSS
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3IN.x
Bus
Keeper
EN
P3.0/TA1CLK/CBOUT/S31
P3.1/TA1.0/S30
P3.2/TA1.1/S29
P3.3/TA1.2/S28
P3.4/TA2CLK/SMCLK/S27
P3.5/TA2.0/S26
P3.6/TA2.1/S25
P3.7/TA2.2/S24
D
Module X IN
P3IE.x
EN
P3IRQ.x
Q
P3IFG.x
P3SEL.x
P3IES.x
Set
Interrupt
Edge
Select
Figure 6-4. Port P3 (P3.0 to P3.7) Schematic
90
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Port P3 (P3.0 to P3.7) Pin Functions
PIN NAME (P3.x)
x
FUNCTION
P3.0 (I/O)
P3.0/TA1CLK/CBOUT/
S31
0
2
0
0
1
0
CBOUT
1
1
0
Timer TA1.CCI0A capture input
3
4
5
(1)
7
0
1
0
1
I: 0; O: 1
0
0
0
1
0
Timer TA1.CCI1A capture input
Timer TA1.1 output
1
1
0
S29
X
X
1
I: 0; O: 1
0
0
Timer TA1.CCI2A capture input
0
1
0
Timer TA1.2 output
1
1
0
S28
X
X
1
I: 0; O: 1
0
0
Timer TA2.TA2CLK
0
1
0
SMCLK
1
1
0
S27
X
X
1
I: 0; O: 1
0
0
Timer TA2.CCI0A capture input
0
1
0
Timer TA2.0 output
1
1
0
Timer TA2.CCI1A capture input
X
X
1
I: 0; O: 1
0
0
0
1
0
Timer TA2.1 output
1
1
1
S25
X
X
1
I: 0; O: 1
0
0
0
1
0
P3.7 (I/O)
P3.7/TA2.2/S24
1
X
P3.6 (I/O)
6
0
0
1
S26
P3.6/TA2.1/S25
1
0
X
P3.5 (I/O)
P3.5/TA2.0/S26
X
S30
P3.4 (I/O)
P3.4/TA2CLK/SMCLK/
S27
X
I: 0; O: 1
Timer TA1.0 output
P3.3 (I/O)
P3.3/TA1.2/S28
LCDS24...31
0
P3.2 (I/O)
P3.2/TA1.1/S29
P3SEL.x
I: 0; O: 1
P3.1 (I/O)
1
P3DIR.x
Timer TA1.TA1CLK
S31
P3.1/TA1.0/S30
CONTROL BITS OR SIGNALS (1)
Timer TA2.CCI2A capture input
Timer TA2.2 output
1
1
0
S24
X
X
1
X = Don't care
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6.14.4 Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
Figure 6-5 shows the port schematic. summarizes selection of the pin function.
Pad Logic
S16...S23
LCDS16...LCDS23
P4REN.x
P4DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P4OUT.x
DVSS
P4.0/TB0.0/S23
P4.1/TB0.1/S22
P4.2/TB0.2/S21
P4.3/TB0.3/S20
P4.4/TB0.4/S19
P4.5/TB0.5/S18
P4.6/TB0.6/S17
P4.7/TB0OUTH/SVMOUT/S16
P4DS.x
0: Low drive
1: High drive
P4SEL.x
P4IN.x
Bus
Keeper
EN
Module X IN
D
P4IE.x
EN
P4IRQ.x
Q
P4IFG.x
P4SEL.x
P4IES.x
Set
Interrupt
Edge
Select
Figure 6-5. Port P4 (P4.0 to P4.7) Schematic
92
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Port P4 (P4.0 to P4.7) Pin Functions
PIN NAME (P4.x)
x
FUNCTION
P4.0 (I/O)
P4.0/TB0.0/S23
0
0
0
1
0
Timer TB0.0 output (2)
1
1
0
Timer TB0.CCI1A capture input
Timer TB0.1 output
(2)
P4.2 (I/O)
2
Timer TB0.CCI2A capture input
Timer TB0.2 output
(2)
4
5
(1)
(2)
1
0
X
1
I: 0; O: 1
0
0
0
1
0
1
0
Timer TB0.CCI3A capture input
0
1
0
Timer TB0.3 output (2)
1
1
0
S20
X
X
1
I: 0; O: 1
0
0
Timer TB0.CCI4A capture input
0
1
0
Timer TB0.4 output (2)
1
1
0
S19
X
X
1
I: 0; O: 1
0
0
Timer TB0.CCI5A capture input
0
1
0
Timer TB0.5 output (2)
1
1
0
Timer TB0.CCI6A capture input
Timer TB0.6 output
(2)
P4.7 (I/O)
7
1
X
0
S17
P4.7/TB0OUTH/
SVMOUT/S16
0
I: 0; O: 1
P4.6 (I/O)
6
1
0
S18
P4.6/TB0.6/S17
0
0
1
P4.5 (I/O)
P4.5/TB0.5/S18
1
0
X
P4.4 (I/O)
P4.4/TB0.4/S19
X
1
P4.3 (I/O)
3
X
I: 0; O: 1
X
S21
P4.3/TB0.3/S20
LCDS16...23
0
S22
P4.2/TB0.2/S21
P4SEL.x
I: 0; O: 1
P4.1 (I/O)
1
P4DIR.x
Timer TB0.CCI0A capture input
S23
P4.1/TB0.1/S22
CONTROL BITS OR SIGNALS (1)
Timer TB0.TB0OUTH
X
X
1
I: 0; O: 1
0
0
0
1
0
1
1
0
X
X
1
I: 0; O: 1
0
0
0
1
0
SVMOUT
1
1
0
S16
X
X
1
X = Don't care
Setting TB0OUTH causes all Timer_B configured outputs to be set to high impedance.
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6.14.5 Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
Figure 6-6 shows the port schematic. summarizes selection of the pin function.
Pad Logic
To/From
Reference
P5REN.x
P5DIR.x
DVSS
0
DVCC
1
1
0
1
P5OUT.x
0
Module X OUT
1
P5.0/VREF+/VeREF+
P5.1/VREF–/VeREF–
P5DS.x
0: Low drive
1: High drive
P5SEL.x
P5IN.x
Bus
Keeper
EN
Module X IN
D
Figure 6-6. Port P5 (P5.0 and P5.1) Schematic
Port P5 (P5.0 and P5.1) Pin Functions
PIN NAME (P5.x)
x
FUNCTION
P5.0 (I/O)
P5.0/VREF+/VeREF+
0
(1)
(2)
(3)
(4)
(5)
(6)
94
1
P5DIR.x
P5SEL.x
REFOUT
I: 0; O: 1
0
X
VeREF+ (3)
X
1
0
VREF+ (4)
X
1
1
P5.1 (I/O)
P5.1/VREF–/VeREF–
(2)
CONTROL BITS OR SIGNALS (1)
(2)
I: 0; O: 1
0
X
VeREF– (5)
X
1
0
VREF– (6)
X
1
1
X = Don't care
Default condition
Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals. An external voltage can be applied to VeREF+ and used as the reference for the ADC12_A, Comparator_B, or DAC12_A.
Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals. The ADC12_A, VREF+ reference is available at the pin.
Setting the P5SEL.1 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals. An external voltage can be applied to VeREF- and used as the reference for the ADC12_A, Comparator_B, or DAC12_A.
Setting the P5SEL.1 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals. The ADC12_A, VREF– reference is available at the pin.
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6.14.6 Port P5, P5.2 to P5.7, Input/Output With Schmitt Trigger
Figure 6-7 shows the port schematic. summarizes selection of the pin function.
Pad Logic
S40...S42
LCDS40...LCDS42
P5REN.x
P5DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P5OUT.x
DVSS
P5.2/R23
P5.3/COM1/S42
P5.4/COM2/S41
P5.5/COM3/S40
P5.6/ADC12CLK/DMAE0
P5.7/RTCCLK
P5DS.x
0: Low drive
1: High drive
P5SEL.x
P5IN.x
Bus
Keeper
EN
Module X IN
D
Figure 6-7. Port P5 (P5.2 to P5.7) Schematic
Port P5 (P5.2 to P5.7) Pin Functions
PIN NAME (P5.x)
P5.2/R23
x
2
FUNCTION
P5DIR.x
P5SEL.x
LCDS40...42
I: 0; O: 1
0
N/A
X
1
N/A
I: 0; O: 1
0
0
COM1
X
1
X
S42
X
0
1
I: 0; O: 1
0
0
COM2
X
1
X
S41
X
0
1
I: 0; O: 1
0
0
COM3
X
1
X
S40
X
0
1
I: 0; O: 1
0
N/A
1
1
N/A
P5.2 (I/O)
R23
P5.3 (I/O)
P5.3/COM1/S42
3
P5.4 (I/O)
P5.4/COM2/S41
4
P5.5 (I/O)
P5.5/COM3/S40
5
P5.6 (I/O)
P5.6/ADC12CLK/DMAE0
6
CONTROL BITS OR SIGNALS (1)
ADC12CLK
DMAE0
P5.7/RTCCLK
(1)
7
0
1
N/A
P5.7 (I/O)
I: 0; O: 1
0
N/A
RTCCLK
1
1
N/A
X = Don't care
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6.14.7 Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger
Figure 6-8 shows the port schematic. summarizes selection of the pin function.
Pad Logic
To ADC12
INCHx = y
0
Dvss
1
From DAC12_A
2
0 if DAC12AMPx=0
1 if DAC12AMPx=1
2 if DAC12AMPx>1
To Comparator_B
From Comparator_B
CBPD.x
DAC12AMPx>0
DAC12OPS
P6REN.x
DVSS
0
DVCC
1
1
P6DIR.x
P6OUT.x
P6DS.x
0: Low drive
1: High drive
P6SEL.x
P6IN.x
Bus
Keeper
P6.0/CB0/A0
P6.1/CB1/A1
P6.2/CB2/A2
P6.3/CB3/A3
P6.4/CB4/A4
P6.5/CB5/A5
P6.6/CB6/A6/DAC0
P6.7/CB7/A7/DAC1
Figure 6-8. Port P6 (P6.0 to P6.7) Schematic
96
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Port P6 (P6.0 to P6.7) Pin Functions
PIN NAME (P6.x)
x
FUNCTION
P6.0 (I/O)
P6.0/CB0/A0
0
1
2
3
4
5
0
N/A
N/A
1
N/A
N/A
A0 (2) (3)
X
1
X
N/A
N/A
I: 0; O: 1
0
0
N/A
N/A
CB1
X
X
1
N/A
N/A
A1 (2) (3)
X
1
X
N/A
N/A
I: 0; O: 1
0
0
N/A
N/A
CB2
X
X
1
N/A
N/A
A2 (2) (3)
X
1
X
N/A
N/A
I: 0; O: 1
0
0
N/A
N/A
CB3
X
X
1
N/A
N/A
A3 (2) (3)
X
1
X
N/A
N/A
I: 0; O: 1
0
0
N/A
N/A
CB4
X
X
1
N/A
N/A
A4 (2) (3)
X
1
X
N/A
N/A
I: 0; O: 1
0
0
N/A
N/A
CB5
X
X
1
N/A
N/A
A5 (2) (3)
X
1
X
N/A
N/A
I: 0; O: 1
0
0
X
0
X
X
1
X
0
X
1
X
X
0
X
X
X
0
>1
I: 0; O: 1
0
0
X
0
CB7
X
X
1
X
0
A7 (2) (3)
X
1
X
X
0
DAC1
X
X
X
0
>1
P6.6 (I/O)
P6.6/CB6/A6/DAC0
6
CB6
A6
(2) (3)
DAC0
P6.7 (I/O)
P6.7/CB7/A7/DAC1
(1)
(2)
(3)
7
DAC12AMPx
0
P6.5 (I/O)
P6.5/CB5/A5
DAC12OPS
X
P6.4 (I/O)
P6.4/CB4/A4
CBPD.x
X
P6.3 (I/O)
P6.3/CB3/A3
P6SEL.x
I: 0; O: 1
P6.2 (I/O)
P6.2/CB2/A2
P6DIR.x
CB0
P6.1 (I/O)
P6.1/CB1/A1
CONTROL BITS OR SIGNALS (1)
X = Don't care
Setting the P6SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals.
The ADC12_A channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
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6.14.8 Port P7, P7.2, Input/Output With Schmitt Trigger
Figure 6-9 shows the port schematic. summarizes selection of the pin function.
Pad Logic
To XT2
P7REN.2
P7DIR.2
DVSS
0
DVCC
1
1
0
1
P7OUT.2
P7DS.2
0: Low drive
1: High drive
P7SEL.2
P7.2/XT2IN
P7IN.2
Bus
Keeper
Figure 6-9. Port P7 (P7.2) Schematic
98
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6.14.9 Port P7, P7.3, Input/Output With Schmitt Trigger
Figure 6-10 shows the port schematic. summarizes selection of the pin function.
Pad Logic
To XT2
P7REN.3
P7DIR.3
DVSS
0
DVCC
1
1
0
1
P7OUT.3
P7SEL.2
P7.3/XT2OUT
P7DS.3
0: Low drive
1: High drive
XT2BYPASS
P7SEL.3
P7IN.3
Bus
Keeper
Figure 6-10. Port P7 (P7.3) Schematic
Port P7 (P7.2 and P7.3) Pin Functions
PIN NAME (P5.x)
x
FUNCTION
P7.2 (I/O)
P7.2/XT2IN
2
XT2IN crystal mode (2)
XT2IN bypass mode
(2)
P7.3 (I/O)
P7.3/XT2OUT
3
XT2OUT crystal mode (3)
P7.3 (I/O)
(1)
(2)
(3)
(3)
CONTROL BITS OR SIGNALS (1)
P7DIR.x
P7SEL.2
P7SEL.3
XT2BYPASS
I: 0; O: 1
0
X
X
X
1
X
0
X
1
X
1
I: 0; O: 1
0
0
X
X
1
X
0
X
1
0
1
X = Don't care
Setting P7SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P7.2 is configured for crystal
mode or bypass mode.
Setting P7SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P7.3 can be used as
general-purpose I/O.
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6.14.10 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger
Figure 6-11 shows the port schematic. summarizes selection of the pin function.
0
Dvss
1
From DAC12_A
2
Pad Logic
0 if DAC12AMPx = 0
1 if DAC12AMPx = 1
2 if DAC12AMPx > 1
To ADC12
INCHx = y
To Comparator_B
From Comparator_B
CBPD.x
DAC12AMPx>0
DAC12OPS
P7REN.x
DVSS
0
DVCC
1
1
P7DIR.x
P7OUT.x
P7DS.x
0: Low drive
1: High drive
P7SEL.x
P7.4/CB8/A12
P7.5/CB9/A13
P7.6/CB10/A14/DAC0
P7.7/CB11/A15/DAC1
P7IN.x
Bus
Keeper
Figure 6-11. Port P7 (P7.4 to P7.7) Schematic
100
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Port P7 (P7.4 to P7.7) Pin Functions
PIN NAME (P7.x)
x
FUNCTION
P7.4 (I/O)
P7.4/CB8/A12
P7.5/CB9/A13
P7.6/CB10/A14/DAC0
P7.7/CB11/A15/DAC1
(1)
(2)
(3)
4
5
6
7
CONTROL BITS OR SIGNALS (1)
P7DIR.x
P7SEL.x
CBPD.x
DAC12OPS
DAC12AMPx
I: 0; O: 1
0
0
N/A
N/A
Comparator_B input CB8
X
X
1
N/A
N/A
A12 (2) (3)
X
1
X
N/A
N/A
P7.5 (I/O)
I: 0; O: 1
0
0
N/A
N/A
Comparator_B input CB9
X
X
1
N/A
N/A
A13 (2) (3)
X
1
X
N/A
N/A
P7.6 (I/O)
I: 0; O: 1
0
0
X
0
Comparator_B input CB10
X
X
1
X
0
A14 (2) (3)
X
1
X
X
0
DAC12_A output DAC0
X
X
X
1
>1
P7.7 (I/O)
I: 0; O: 1
0
0
X
0
A15 (2) (3)
X
1
X
X
0
DAC12_A output DAC1
X
X
X
1
>1
X = Don't care
Setting the P7SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals.
The ADC12_A channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
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6.14.11 Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger
Figure 6-12 shows the port schematic. summarizes selection of the pin function.
Pad Logic
S8...S15
LCDS8...LCDS15
P8REN.x
P8DIR.x
0
From module
1
P8OUT.x
0
Module X OUT
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P8.0/TB0CLK/S15
P8.1/UCB1STE/UCA1CLK/S14
P8.2/UCA1TXD/UCA1SIMO/S13
P8.3/UCA1RXD/UCA1SOMI/S12
P8.4/UCB1CLK/UCA1STE/S11
P8.5/UCB1SIMO//UCB1SDA/S10
P8.6/UCB1SOMI/UCB1SCL/S9
P8.7/S8
P8DS.x
0: Low drive
1: High drive
P8SEL.x
P8IN.x
EN
Module X IN
Bus
Keeper
D
Figure 6-12. Port P8 (P8.0 to P8.7) Schematic
102
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Port P8 (P8.0 to P8.7) Pin Functions
PIN NAME (P9.x)
x
FUNCTION
P8.0 (I/O)
P8.0/TB0CLK/S15
0
1
2
3
0
0
1
0
S15
X
X
1
I: 0; O: 1
0
0
UCB1STE/UCA1CLK
X
1
0
S14
X
X
1
I: 0; O: 1
0
0
UCA1TXD/UCA1SIMO
X
1
0
S13
X
X
1
I: 0; O: 1
0
0
UCA1RXD/UCA1SOMI
X
1
0
S12
X
X
1
I: 0; O: 1
0
0
P8.4 (I/O)
P8.4/UCB1CLK/UCA1STE/S11
4
UCB1CLK/UCA1STE
X
1
0
S11
X
X
1
I: 0; O: 1
0
0
P8.5 (I/O)
P8.5/UCB1SIMO/UCB1SDA/S10
5
UCB1SIMO/UCB1SDA
X
1
0
S10
X
X
1
I: 0; O: 1
0
0
X
1
0
P8.6 (I/O)
P8.6/UCB1SOMI/UCB1SCL/S9
6
UCB1SOMI/UCB1SCL
S9
P8.7/S8
(1)
7
LCDS8...15
0
P8.3 (I/O)
P8.3/UCA1RXD/UCA1SOMI/S12
P8SEL.x
I: 0; O: 1
P8.2 (I/O)
P8.2/UCA1TXD/UCA1SIMO/S13
P8DIR.x
Timer TB0.TB0CLK clock input
P8.1 (I/O)
P8.1/UCB1STE/UCA1CLK/S14
CONTROL BITS OR SIGNALS (1)
P8.7 (I/O)
S8
X
X
1
I: 0; O: 1
0
0
X
X
1
X = Don't care
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6.14.12 Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger
Figure 6-13 shows the port schematic. summarizes selection of the pin function.
Pad Logic
S0...S7
LCDS0...LCDS7
P9REN.x
P9DIR.x
0
From module
1
P9OUT.x
0
Module X OUT
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P9.0/S7
P9.1/UCB2STE/UCA2CLK/S6
P9.2/UCA2TXD/UCA2SIMO/S5
P9.3/UCA2RXD/UCA2SOMI/S4
P9.4/UCB2CLK/UCA2STE/S3
P9.5/UCB2SIMO//UCB2SDA/S2
P9.6/UCB2SOMI/UCB2SCL/S1
P9.7/S0
P9DS.x
0: Low drive
1: High drive
P9SEL.x
P9IN.x
EN
Module X IN
Bus
Keeper
D
Figure 6-13. Port P9 (P9.0 to P9.7) Schematic
104
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Port P9 (P9.0 to P9.7) Pin Functions
PIN NAME (P9.x)
P9.0/S7
x
0
FUNCTION
P9.0 (I/O)
S7
P9.1 (I/O)
P9.1/UCB2STE/UCA2CLK/S6
1
2
3
P9.7/S0
(1)
7
0
0
1
I: 0; O: 1
0
0
UCA2TXD/UCA2SIMO
X
1
0
S5
X
X
1
I: 0; O: 1
0
0
X
1
0
UCA2RXD/UCA2SOMI
UCB2CLK/UCA2STE
UCB2SIMO/UCB2SDA
X
X
1
I: 0; O: 1
0
0
X
1
0
X
X
1
I: 0; O: 1
0
0
X
1
0
X
X
1
I: 0; O: 1
0
0
UCB2SOMI/UCB2SCLK
X
1
0
S1
X
X
1
I: 0; O: 1
0
0
X
X
1
P9.6 (I/O)
6
1
I: 0; O: 1
0
S2
P9.6/UCB2SOMI/UCB2SCLK/S1
0
X
1
P9.5 (I/O)
5
0
X
X
S3
P9.5/UCB2SIMO/UCB2SDA/S2
I: 0; O: 1
X
P9.4 (I/O)
4
LCDS0...7
X
S4
P9.4/UCB2CLK/UCA2STE/S3
P9SEL.x
S6
P9.3 (I/O)
P9.3/UCA2RXD/UCA2SOMI/S4
P9DIR.x
UCB2STE/UCA2CLK
P9.2 (I/O)
P9.2/UCA2TXD/UCA2SIMO/S5
CONTROL BITS OR SIGNALS (1)
P9.7 (I/O)
S0
X = Don't care
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6.14.13 Port PU.0, PU.1 Ports
Figure 6-14 shows the port schematic. Table 6-53 summarizes selection of the pin function.
LDOO
VSSU
Pad Logic
PUOPE
PU.0
PUOUT0
PUIN0
PUIPE
PUIN1
PU.1
PUOUT1
Figure 6-14. Port U (PU.0 and PU.1) Schematic
Table 6-53. Port PU.0, PU.1 Functions (1)
(1)
106
PUIPE
PUOPE
PUOUT1
PUOUT0
PU.1
PU.0
PORT U FUNCTION
0
1
0
0
0
1
0
1
Output low
Output low
Outputs enabled
Output low
Output high
0
1
1
0
Outputs enabled
Output high
Output low
Outputs enabled
0
1
1
1
1
0
X
X
Output high
Output high
Outputs enabled
Input enabled
Input enabled
0
0
X
X
Hi-Z
Inputs enabled
Hi-Z
Outputs and inputs disabled
PU.1 and PU.0 inputs and outputs are supplied from LDOO. LDOO can be generated by the device using the integrated 3.3-V LDO
when enabled. LDOO can also be supplied externally when the 3.3-V LDO is not being used and is disabled.
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6.14.14 Port J, PJ.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
Figure 6-15 shows the port schematic. summarizes selection of the pin function.
Pad Logic
PJREN.0
PJDIR.0
0
DVCC
1
PJOUT.0
0
From JTAG
1
DVSS
0
DVCC
1
PJDS.0
0: Low drive
1: High drive
From JTAG
1
PJ.0/TDO
PJIN.0
EN
D
Figure 6-15. Port PJ (PJ.0) Schematic
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6.14.15 Port J, PJ.1 to PJ.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt
Trigger or Output
Figure 6-16 shows the port schematic. summarizes selection of the pin function.
Pad Logic
PJREN.x
PJDIR.x
0
DVSS
1
PJOUT.x
0
From JTAG
1
DVSS
0
DVCC
1
1
PJDS.x
0: Low drive
1: High drive
From JTAG
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
PJIN.x
EN
D
To JTAG
Figure 6-16. Port PJ (PJ.1 to PJ.3) Schematic
Port PJ (PJ.0 to PJ.3) Pin Functions
PIN NAME (PJ.x)
x
CONTROL BITS OR
SIGNALS (1)
FUNCTION
PJDIR.x
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
(1)
(2)
(3)
(4)
108
0
1
2
3
(2)
I: 0; O: 1
PJ.1 (I/O) (2)
I: 0; O: 1
PJ.0 (I/O)
TDO (3)
X
TDI/TCLK (3)
PJ.2 (I/O)
TMS (3)
X
I: 0; O: 1
(4)
PJ.3 (I/O)
TCK (3)
(4)
(2)
X
(2)
I: 0; O: 1
(4)
X
X = Don't care
Default condition
The pin direction is controlled by the JTAG module.
In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care.
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6.15 Device Descriptors
Table 6-54 lists the contents of the device descriptor tag-length-value (TLV) structure for each device type.
Table 6-54. Device Descriptor Table (1)
Info Block
Die Record
ADC12
Calibration
REF Calibration
(1)
VALUE
ADDRESS
SIZE
(bytes)
F6659
F6658
F6459
F6458
F5659
F5658
F5359
F5358
Info length
01A00h
1
06h
06h
06h
06h
06h
06h
06h
06h
CRC length
01A01h
1
06h
06h
06h
06h
06h
06h
06h
06h
CRC value
01A02h
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
DESCRIPTION
Device ID
01A04h
2
812Bh
812Ch
812Dh
812Eh
8130h
8131h
8132h
8133h
Hardware revision
01A06h
1
10h
10h
10h
10h
10h
10h
10h
10h
Firmware revision
01A07h
1
10h
10h
10h
10h
10h
10h
10h
10h
Die record tag
01A08h
1
08h
08h
08h
08h
08h
08h
08h
08h
Die record length
01A09h
1
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
Lot/wafer ID
01A0Ah
4
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
Die X position
01A0Eh
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
Die Y position
01A10h
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
Test results
01A12h
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
ADC12 calibration tag
01A14h
1
11h
11h
11h
11h
11h
11h
11h
11h
ADC12 calibration length
01A15h
1
10h
10h
10h
10h
10h
10h
10h
10h
ADC gain factor
01A16h
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
ADC offset
01A18h
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
ADC 1.5-V reference
temperature sensor 30°C
01A1Ah
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
ADC 1.5-V reference
temperature sensor 105°C
01A1Ch
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
ADC 2.0-V reference
temperature sensor 30°C
01A1Eh
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
ADC 2.0-V reference
temperature sensor 105°C
01A20h
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
ADC 2.5-V reference
temperature sensor 30°C
01A22h
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
ADC 2.5-V reference
temperature sensor 105°C
01A24h
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
REF calibration tag
01A26h
1
12h
12h
12h
12h
12h
12h
12h
12h
REF calibration length
01A27h
1
06h
06h
06h
06h
06h
06h
06h
06h
REF 1.5-V
reference factor
01A28h
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
REF 2.0-V
reference factor
01A2Ah
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
REF 2.5-V
reference factor
01A2Ch
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
N/A = Not applicable
Detailed Description
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7 Applications, Implementation, and Layout
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
7.1
Device Connection and Layout Fundamentals
This section discusses the recommended guidelines when designing with the MSP430. These guidelines
are to make sure that the device has proper connections for powering, programming, debugging, and
optimum analog performance.
7.1.1
Power Supply Decoupling and Bulk Capacitors
TI recommends connecting a combination of a 1-µF plus a 100-nF low-ESR ceramic decoupling capacitor
to each AVCC and DVCC pin. Higher-value capacitors may be used but can impact supply rail ramp-up
time. Decoupling capacitors must be placed as close as possible to the pins that they decouple (within a
few millimeters). Additionally, separated grounds with a single-point connection are recommend for better
noise isolation from digital to analog circuits on the board and are especially recommended to achieve
high analog accuracy.
DVCC
Digital
Power Supply
Decoupling
+
1 µF
100 nF
DVSS
AVCC
Analog
Power Supply
Decoupling
+
1 µF
100 nF
AVSS
Figure 7-1. Power Supply Decoupling
7.1.2
External Oscillator
Depending on the device variant (see Table 3-1), the device can support a low-frequency crystal (32 kHz)
on the LFXT pins, a high-frequency crystal on the HFXT pins, or both. External bypass capacitors for the
crystal oscillator pins are required.
It is also possible to apply digital clock signals to the LFXIN and HFXIN input pins that meet the
specifications of the respective oscillator if the appropriate LFXTBYPASS or HFXTBYPASS mode is
selected. In this case, the associated LFXOUT and HFXOUT pins can be used for other purposes.
Figure 7-2 shows a typical connection diagram.
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LFXIN
or
HFXIN
CL1
LFXOUT
or
HFXOUT
CL2
Figure 7-2. Typical Crystal Connection
See the application report MSP430 32-kHz Crystal Oscillators (SLAA322) for more information on
selecting, testing, and designing a crystal oscillator with the MSP430 devices.
7.1.3
JTAG
With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or
MSP-FET430UIF) can be used to program and debug code on the target board. In addition, the
connections also support the MSP-GANG production programmers, thus providing an easy way to
program prototype boards, if desired. Figure 7-3 shows the connections between the 14-pin JTAG
connector and the target device required to support in-system programming and debugging for 4-wire
JTAG communication. Figure 7-4 shows the connections for 2-wire JTAG mode (Spy-Bi-Wire).
The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are
identical. Both can supply VCC to the target board (through pin 2). In addition, the MSP-FET and MSPFET430UIF interface modules and MSP-GANG have a VCC sense feature that, if used, requires an
alternate connection (pin 4 instead of pin 2). The VCC-sense feature senses the local VCC present on the
target board (that is, a battery or other local power supply) and adjusts the output signals accordingly.
Figure 7-3 and Figure 7-4 show a jumper block that supports both scenarios of supplying VCC to the
target board. If this flexibility is not required, the desired VCC connections may be hard-wired to eliminate
the jumper block. Pins 2 and 4 must not be connected at the same time.
For additional design information regarding the JTAG interface, see the MSP430 Hardware Tools User's
Guide (SLAU278).
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VCC
Important to connect
MSP430F6459
J1 (see Note A)
AVCC/DVCC
J2 (see Note A)
R1
47 kW
JTAG
VCC TOOL
VCC TARGET
TEST
2
RST/NMI/SBWTDIO
1
4
3
6
5
8
7
10
9
12
11
14
13
TDO/TDI
TDO/TDI
TDI
TDI
TMS
TMS
TCK
TCK
GND
RST
TEST/SBWTCK
C1
2.2 nF
(see Note B)
AVSS/DVSS
Copyright © 2016, Texas Instruments Incorporated
A.
B.
If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used,
make connection J2.
The upper limit for C1 is 2.2 nF when using current TI tools.
Figure 7-3. Signal Connections for 4-Wire JTAG Communication
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VCC
Important to connect
MSP430F6459
J1 (see Note A)
AVCC/DVCC
J2 (see Note A)
R1
47 kΩ
(See Note B)
JTAG
VCC TOOL
VCC TARGET
2
1
4
3
6
5
8
7
10
9
12
11
14
13
TDO/TDI
RST/NMI/SBWTDIO
TCK
GND
TEST/SBWTCK
C1
2.2 nF
(See Note B)
AVSS/DVSS
Copyright © 2016, Texas Instruments Incorporated
A.
B.
Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the
debug or programming adapter.
The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during
JTAG access, and any capacitance that is attached to this signal may affect the ability to establish a connection with
the device. The upper limit for C1 is 2.2 nF when using current TI tools.
Figure 7-4. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire)
7.1.4
Reset
The reset pin can be configured as a reset function (default) or as an NMI function in the Special Function
Register (SFR), SFRRPCR.
In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing
specifications generates a BOR-type device reset.
Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is
edge sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the
external NMI. When an external NMI event occurs, the NMIIFG is set.
The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either
pullup or pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not.
If the RST/NMI pin is unused, it is required either to select and enable the internal pullup or to connect an
external 47-kΩ pullup resistor to the RST/NMI pin with a 2.2-nF pulldown capacitor. The pulldown
capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or
in 4-wire JTAG mode with TI tools like FET interfaces or GANG programmers.
See the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) for more information on the
referenced control registers and bits.
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General Layout Recommendations
•
•
•
•
•
7.1.6
Proper grounding and short traces for external crystal to reduce parasitic capacitance. See the
application report MSP430 32-kHz Crystal Oscillators (SLAA322) for recommended layout guidelines.
Proper bypass capacitors on DVCC, AVCC, and reference pins if used.
Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital
switching signals such as PWM or JTAG signals away from the oscillator circuit.
Refer to the Circuit Board Layout Techniques design guide (SLOA089) for a detailed discussion of
PCB layout considerations. This document is written primarily about op amps, but the guidelines are
generally applicable for all mixed-signal applications.
Proper ESD level protection should be considered to protect the device from unintended high-voltage
electrostatic discharge. See the application report MSP430 System-Level ESD Considerations
(SLAA530) for guidelines.
Do's and Don'ts
TI recommends powering the AVCC and DVCC pins from the same source. At a minimum, during power
up, power down, and device operation, the voltage difference between AVCC and DVCC must not exceed
the limits specified in the Absolute Maximum Ratings section. Exceeding the specified limits may cause
malfunction of the device including erroneous writes to RAM and FRAM.
7.2
Peripheral- and Interface-Specific Design Information
7.2.1
ADC12_B Peripheral
7.2.1.1
Partial Schematic
AVSS
VREF+/VEREF+
Using an
External
Positive
Reference
+
10 µF
4.7 µF
VEREF-
Using an
External
Negative
Reference
+
10 µF
4.7 µF
Figure 7-5. ADC12_B Grounding and Noise Considerations
7.2.1.2
Design Requirements
As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should
be followed to eliminate ground loops, unwanted parasitic effects, and noise.
Ground loops are formed when return current from the ADC flows through paths that are common with
other analog or digital circuitry. If care is not taken, this current can generate small unwanted offset
voltages that can add to or subtract from the reference or input voltages of the ADC. The general
guidelines in Section 7.1.1 combined with the connections shown in Section 7.2.1.1 prevent this.
In addition to grounding, ripple and noise spikes on the power-supply lines that are caused by digital
switching or switching power supplies can corrupt the conversion result. A noise-free design using
separate analog and digital ground planes with a single-point connection is recommend to achieve high
accuracy.
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Figure 7-5 shows the recommended decoupling circuit when an external voltage reference is used. The
internal reference module has a maximum drive current as specified in the Reference module's IO(VREF+)
specification.
The reference voltage must be a stable voltage for accurate measurements. The capacitor values that are
selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage
enters the device. In this case, the 10-µF capacitor is used to buffer the reference pin and filter any lowfrequency ripple. A bypass capacitor of 4.7 µF is used to filter out any high frequency noise.
7.2.1.3
Detailed Design Procedure
For additional design information, see the ADC12_A section in the application report MSP430x5xx and
MSP430x6xx Family User's Guide (SLAU208).
7.2.1.4
Layout Guidelines
Component that are shown in the partial schematic (see Figure 7-5) should be placed as close as possible
to the respective device pins. Avoid long traces, because they add additional parasitic capacitance,
inductance, and resistance on the signal.
Avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency PWM),
because the high-frequency switching can be coupled into the analog signal.
If differential mode is used for the ADC12_B, the analog differential input signals must be routed closely
together to minimize the effect of noise on the resulting signal.
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8 Device and Documentation Support
8.1
Getting Started and Next Steps
For more information on the MSP430™ family of devices and the tools and libraries that are available to
help with your development, visit the Getting Started page.
8.2
Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP430 MCU devices and support tools. Each MSP430 MCU commercial family member has one of
three prefixes: MSP, PMS, or XMS (for example, MSP430F5438A). TI recommends two of three possible
prefix designators for its support tools: MSP and MSPX. These prefixes represent evolutionary stages of
product development from engineering prototypes (with XMS for devices and MSPX for tools) through fully
qualified production devices and tools (with MSP for devices and MSP for tools).
Device development evolutionary flow:
XMS – Experimental device that is not necessarily representative of the electrical specifications for the
final device
PMS – Final silicon die that conforms to the electrical specifications for the device but has not completed
quality and reliability verification
MSP – Fully qualified production device
Support tool development evolutionary flow:
MSPX – Development-support product that has not yet completed TI's internal qualification testing.
MSP – Fully-qualified development-support product
XMS and PMS devices and MSPX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices and MSP development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS and PMS) have a greater failure rate than the standard
production devices. TI recommends that these devices not be used in any production system because
their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, PZP) and temperature range (for example, T). Figure 8-1 provides a legend
for reading the complete device name for any family member.
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MSP 430 F 5 438 A I ZQW T -EP
Processor Family
Optional: Additional Features
MCU Platform
Optional: Tape and Reel
Device Type
Packaging
Series
Optional: Temperature Range
Feature Set
Processor Family
Optional: A = Revision
CC = Embedded RF Radio
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
430 = MSP430 low-power microcontroller platform
MCU Platform
Device Type
Memory Type
C = ROM
F = Flash
FR = FRAM
G = Flash or FRAM (Value Line)
L = No Nonvolatile Memory
Series
1 Series = Up to 8 MHz
2 Series = Up to 16 MHz
3 Series = Legacy
4 Series = Up to 16 MHz with LCD
Feature Set
Various Levels of Integration Within a Series
Optional: A = Revision
N/A
Specialized Application
AFE = Analog Front End
BT = Preprogrammed with Bluetooth
BQ = Contactless Power
CG = ROM Medical
FE = Flash Energy Meter
FG = Flash Medical
FW = Flash Electronic Flow Meter
5 Series = Up to 25 MHz
6 Series = Up to 25 MHz with LCD
0 = Low-Voltage Series
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging
http://www.ti.com/packaging
Optional: Tape and Reel
T = Small Reel
R = Large Reel
No Markings = Tube or Tray
Optional: Additional Features -EP = Enhanced Product (–40°C to 105°C)
-HT = Extreme Temperature Parts (–55°C to 150°C)
-Q1 = Automotive Q100 Qualified
Figure 8-1. Device Nomenclature
8.3
Tools and Software
All MSP430™ microcontrollers are supported by a wide variety of software and hardware development
tools. Tools are available from TI and various third parties. See them all at www.ti.com/msp430tools.
8.3.1
Hardware Features
See the Code Composer Studio for MSP430 User's Guide (SLAU157) for details on the available features.
MSP430
ARCHITECTURE
4-WIRE
JTAG
2-WIRE
JTAG
BREAKPOINTS
(N)
RANGE
BREAKPOINTS
CLOCK
CONTROL
STATE
SEQUENCER
TRACE
BUFFER
LPMx.5
DEBUGGING
SUPPORT
MSP430Xv2
Yes
Yes
8
Yes
Yes
Yes
Yes
Yes
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Recommended Hardware Options
8.3.2.1
Target Socket Boards
The target socket boards allow easy programming and debugging of the device using JTAG. They also
feature header pin outs for prototyping. Target socket boards are orderable individually or as a kit with the
JTAG programmer and debugger included. The following table shows the compatible target boards and
the supported packages.
8.3.2.2
PACKAGE
TARGET BOARD AND PROGRAMMER BUNDLE
TARGET BOARD ONLY
100-pin LQFP (PZ)
MSP-FET430U100USB
MSP-TS430PZ100USB
Experimenter Boards
Experimenter Boards and Evaluation kits are available for some MSP430 devices. These kits feature
additional hardware components and connectivity for full system evaluation and prototyping. See
www.ti.com/msp430tools for details.
8.3.2.3
Debugging and Programming Tools
Hardware programming and debugging tools are available from TI and from its third-party suppliers. See
the full list of available tools at www.ti.com/msp430tools.
8.3.2.4
Production Programmers
The production programmers expedite loading firmware to devices by programming several devices
simultaneously.
PART NUMBER
PC PORT
MSP-GANG
Serial and USB
8.3.3
FEATURES
PROVIDER
Program up to eight devices at a time. Works with a PC or as a standalone package.
Texas Instruments
Recommended Software Options
8.3.3.1
Integrated Development Environments
Software development tools are available from TI or from third parties. Open source solutions are also
available.
This device is supported by the Code Composer Studio™ IDE (CCS).
8.3.3.2
MSP430Ware
MSP430Ware is a collection of code examples, data sheets, and other design resources for all MSP430
devices delivered in a convenient package. In addition to providing a complete collection of existing
MSP430 design resources, MSP430Ware also includes a high-level API called MSP430 Driver Library.
This library makes it easy to program MSP430 hardware. MSP430Ware is available as a component of
CCS or as a stand-alone package.
8.3.3.3
TI-RTOS
TI-RTOS is an advanced real-time operating system for the MSP430 microcontrollers. It features
preemptive deterministic multitasking, hardware abstraction, memory management, and real-time analysis.
TI-RTOS is available free of charge and is provided with full source code.
8.3.3.4
Command-Line Programmer
MSP430 Flasher is an open-source shell-based interface for programming MSP430 microcontrollers
through a FET programmer or eZ430™ development tool using JTAG or Spy-Bi-Wire (SBW)
communication. MSP430 Flasher can be used to download binary files (.txt or .hex) files directly to the
MSP430 Flash without the need for an IDE.
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8.4
SLASEC3A – AUGUST 2016 – REVISED AUGUST 2016
Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com (GPN1,
GPN2, …). In the upper right corner, click on Alert me to register and receive a weekly digest of any
product information that has changed. For change details, review the revision history included in any
revised document.
The following documents describe the MSP430F665x, MSP430F645x, MSP430F565x, and MSP430F535x
devices. Copies of these documents are available on the Internet at www.ti.com.
SLAZ491
MSP430F6459-Hirel Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revisions of this device.
SLAU278
MSP430 Hardware Tools User's Guide. This manual describes the hardware of the TI
MSP-FET430 Flash Emulation Tool (FET). The FET is the program development tool for the
MSP430 ultra-low-power microcontroller. Both available interface types, the parallel port
interface and the USB interface, are described.
SLAU319
MSP430 Programming With the Bootloader (BSL). The MSP430 bootloader (BSL) allows
users to communicate with embedded memory in the MSP430 microcontroller during the
prototyping phase, final production, and in service. Both the programmable memory (flash
memory) and the data memory (RAM) can be modified as required. Do not confuse the
bootloader with the bootstrap loader programs found in some digital signal processors
(DSPs) that automatically load program code (and data) from external memory to the internal
memory of the DSP.
SLAU320
MSP430 Programming Via the JTAG Interface. This document describes the functions that
are required to erase, program, and verify the memory module of the MSP430 flash-based
and FRAM-based microcontroller families using the JTAG communication port. In addition, it
describes how to program the JTAG access security fuse that is available on all MSP430
MCUs. This document describes access to the MCU using both the standard 4-wire JTAG
interface and the 2-wire JTAG interface, which is also referred to as Spy-Bi-Wire (SBW).
SLAA322
MSP430 32-kHz Crystal Oscillators. Selection of the right crystal, correct load circuit, and
proper board layout are important for a stable crystal oscillator. This application report
summarizes crystal oscillator function and explains the parameters to select the correct
crystal for MSP430 ultra-low power operation. In addition, hints and examples for correct
board layout are given. The document also contains detailed information on the possible
oscillator tests to ensure stable oscillator operation in mass production.
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8.5
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SLOA089
Circuit Board Layout Techniques. Op amp circuitry is analog circuitry and is very different
from digital circuitry. It must be partitioned in its own section of the board using special layout
techniques. Printed circuit board effects become most apparent in high-speed analog
circuits, but common mistakes described in this chapter can even affect the performance of
audio circuits. The purpose of this chapter is to discuss some of the more common mistakes
made by designers and how they degrade performance, and to provide simple fixes to avoid
the problems.
SLAA530
MSP430 System-Level ESD Considerations. System-Level ESD has become increasingly
demanding with silicon technology scaling towards lower voltages and the need for designing
cost-effective and ultra-low-power components. This application report addresses three
different ESD topics to help board designers and OEMs understand and design robust
system-level designs.
Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the
upper right corner, click on Alert me to register and receive a weekly digest of any product information that
has changed. For change details, review the revision history included in any revised document.
8.6
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At
e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow
engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
8.7
Trademarks
MSP430, the Code Composer Studio, eZ430, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
8.8
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.9
Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
authorization from U.S. Department of Commerce and other competent Government authorities to the
extent required by those laws.
8.10 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
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MSP430F6459-HIREL
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SLASEC3A – AUGUST 2016 – REVISED AUGUST 2016
9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2016, Texas Instruments Incorporated
Mechanical, Packaging, and Orderable Information
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Product Folder Links: MSP430F6459-HIREL
121
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
MSP430F6459TPZR
ACTIVE
LQFP
PZ
100
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
F6459TPZ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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