MSP430F6749AIPZ

Product Folder Order Now Technical Documents Support & Community Tools & Software MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 MSP430F677xA, MSP430F676xA, MSP430F674xA Polyphase Metering SoCs 1 Device Overview 1.1 Features 1 • Accuracy < 0.1% Over 2000:1 Dynamic Range for Phase Current • Meets or Exceeds ANSI C12.20 and IEC 62053 Standards • Support for Multiple Sensors Such as Current Transformers, Rogowski Coils, or Shunts • Power Measurement for up to Three Phases Plus Neutral • Dedicated Pulse Output Pins for Active and Reactive Energy for Calibration • 4-Quadrant Measurement per Phase or Cumulative • Exact Phase-Angle Measurements • Digital Phase Correction for Current Transformers • Temperature-Compensated Energy Measurements • 40-Hz to 70-Hz Line Frequency Range Using Single Calibration • Flexible Power Supply Options With Automatic Switching • Display Operates at Very Low Power During AC Mains Failure: 3 µA in LPM3 • LCD Driver With Contrast Control for up to 320 Segments • Password-Protected Real-Time Clock (RTC) With Tamper Detection, Crystal Offset Calibration, and Temperature Compensation • Integrated Security Modules to Support Anti‑Tamper and Encryption • Multiple Communication Interfaces for Smart Meter Implementations • High-Performance Analog – Up to Seven Independent 24-Bit Sigma-Delta ADCs With Differential Inputs and Variable Gain – 10-Bit 200-ksps SAR ADC With Six External Channels and Two Internal Channels, Including Supply and Temperature Sensor Measurement 1.2 • • • Highly Integrated Digital – Three-Channel Direct Memory Access (DMA) Controller – Integrated Hardware AES-128 Module for Encryption – 16-Bit Cyclic Redundancy Check (CRC) Module – Four 16-Bit Timers With Nine Total Capture/Compare Registers • Six Enhanced Universal Serial Communication Interfaces (eUSCIs) – eUSCI_A0, eUSCI_A1, eUSCI_A2, and eUSCI_A3 Support UART, IrDA, and SPI – eUSCI_B0, eUSCI_B1 Support SPI and I2C • Ultra-Low Power Consumption – Multiple Low-Power Modes – Standby Mode (LPM3): 2.1 µA at 3 V, Wake up in Less Than 5 µs – RTC Mode (LPM3.5): 0.34 µA at 3 V – Shutdown Mode (LPM4.5): 0.18 µA at 3 V • CPU – High-Performance 25-MHz CPU With 32-Bit Multiplier – Wide Input Supply Voltage Range: 3.6 V Down to 1.8 V • Memory – Up to 512KB of Single-Cycle Flash – Up to 32KB of RAM With Single-Cycle Access • Package Options – 128-Pin LQFP (PEU) Package With 90 I/O Pins – 100-Pin LQFP (PZ) Package With 62 I/O Pins • Development Tools (Also See Tools and Software) – Energy Measurement Design Center for MSP430 MCUs with 24-Bit Sigma-Delta ADCs (MSP-EM-DESIGN-CENTER) – Three-Phase Electronic Watt-Hour EVM for Metering (EVM430-F6779) – Target Development Board (MSP‑TS430PEU128) Applications 3-Phase Electronic Watt-Hour Meters Utility Metering • Energy Monitoring 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 1.3 www.ti.com Description MSP430F67xxA polyphase metering SoCs are powerful highly integrated solutions that offer high accuracy and low system cost with few external components. The MSP430F67xxA microcontroller (MCU) family is part of the MSP430™ Metrology and Monitoring MCU portfolio targeting energy measurement and power monitoring applications including smart grid and building automation. MSP430F67xxA MCUs feature up to seven independent 24-bit sigma-delta ADCs that can provide better than 0.1% accuracy. MSP430F67xxA devices integrate a high-performance MSP430 CPU with a 32-bit multiplier to perform all metrology calculations. Family members include up to 512KB of flash, 32KB of RAM, and an LCD controller with support for up to 320 segments. The ultra-low power consumption of the MSP430F67xxA enables the system power supply to be minimized to reduce overall cost. Low standby power requires minimal energy storage, and critical data can be retained longer in case of a mains power failure. The MSP430F67xxA MCU family is supported by an extensive software and hardware ecosystem. The Texas Instruments Energy Measurement Design Center (EMDC) can simplify development and accelerate designs by quickly configuring the Energy Measurement software library, automatically generating code, performing calibration, and viewing results. MSP430F67xxA MCUs execute the Energy Measurement software library, which calculates all relevant energy and power results. Development kits include the EVM430-F6779 three-phase electricity meter evaluation module and the MSP-TS430PEU128 128-pin target development board. Industry standard development tools and hardware platforms are available to speed development of meters that meet all of the ANSI and IEC standards globally. For complete module descriptions, see the MSP430F5xx and MSP430F6xx Family User's Guide. Device Information (1) PACKAGE BODY SIZE (2) MSP430F6779AIPEU LQFP (128) 20 mm × 14 mm MSP430F6779AIPZ LQFP (100) 14 mm × 14 mm PART NUMBER (1) (2) 2 For the most current part, package, and ordering information, see the Package Option Addendum in Section 9, or see the TI website at www.ti.com. The dimensions shown here are approximations. For the package dimensions with tolerances, see the Mechanical Data in Section 9. Device Overview Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com 1.4 SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Application Diagram Figure 1-1 shows a typical application diagram. TOTAL kWh Load Sx, COMx Phase C VCC Phase A MSP430F677xA R33 RST Phase B LCDCAP VSS Px.x Neutral + IA CT Status LEDs ΣΔ Modulator – + IB CT Px.y ΣΔ Modulator – Pulse LEDs + CT IC ΣΔ Modulator – XIN + Ineutral CT 32768 Hz ΣΔ Modulator – VA XOUT AFE + USCIA0 UART or SPI USCIA1 UART or SPI USCIA2 UART or SPI USCIA3 UART or SPI USCIB0 I2C or SPI USCIB1 I2C or SPI ΣΔ Modulator – VB + ΣΔ Modulator – VC + VN ΣΔ Modulator – Vref Neutral Phase B Phase A Phase C Source From Utility Copyright © 2016, Texas Instruments Incorporated Figure 1-1. 3-Phase 4-Wire Star Connection Using MSP430F677xA Device Overview Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 3 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table of Contents 1 2 3 Device Overview ......................................... 1 5.17 ADC10_A ............................................ 60 1.1 Features .............................................. 1 5.18 REF.................................................. 62 1.2 Applications ........................................... 1 5.19 Comparator_B ....................................... 63 1.3 Description ............................................ 2 5.20 Flash 1.4 Application Diagram .................................. 3 5.21 Emulation and Debug ............................... 64 Revision History ......................................... 5 Device Comparison ..................................... 6 ............................................ Overview 6.2 Functional Block Diagrams.......................... 66 Terminal Configuration and Functions .............. 8 6.3 CPU (Link to User's Guide) ......................... 67 4.1 Pin Diagrams ......................................... 8 6.4 Instruction Set ....................................... 68 4.2 Signal Descriptions .................................. 12 5.5 5.6 65 6.5 Operating Modes .................................... 69 25 6.6 Interrupt Vector Addresses.......................... 70 25 6.7 Special Function Registers (SFRs) ................. 71 26 6.8 Bootloader (BSL) .................................... 72 26 6.9 JTAG Operation ..................................... 73 26 6.10 Memory .............................................. 74 26 Active Mode Supply Current Into VCC Excluding External Current ..................................... 28 Low-Power Mode Supply Currents (Into VCC) Excluding External Current.......................... 29 Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current .................... 30 6.11 Peripherals 6.12 Input/Output Diagrams ............................. 103 6.13 Device Descriptors (TLV) .......................... 158 6.14 Identification........................................ 161 ..................................... 4.4 Connection of Unused Pins ......................... Specifications ........................................... 5.1 Absolute Maximum Ratings ......................... 5.2 ESD Ratings ........................................ 5.3 Recommended Operating Conditions ............... Pin Multiplexing 5.4 7 8 .......................................... 77 Applications, Implementation, and Layout ...... 162 Device and Documentation Support .............. 163 ................... 5.7 Thermal Resistance Characteristics ................ 31 8.1 Getting Started and Next Steps 5.8 Timing and Switching Characteristics ............... 32 8.2 Device Nomenclature .............................. 163 5.9 Digital I/Os........................................... 36 8.3 Tools and Software ................................ 165 5.10 Power-Management Module (PMM) ................ 40 8.4 Documentation Support ............................ 167 5.11 Auxiliary Supplies ................................... 42 8.5 Related Links 5.12 Timer_A 45 Community Resources............................. 169 5.13 ............................................. ............................................... RTC Tamper Detect Pin ............................ LCD_C .............................................. SD24_B ............................................. 8.6 eUSCI 45 8.7 Trademarks ........................................ 169 51 8.8 Electrostatic Discharge Caution 5.14 5.15 5.16 4 Detailed Description ................................... 65 6.1 4.3 5 64 Related Products ..................................... 7 3.1 4 6 ................................................ Table of Contents 8.9 52 54 9 ...................................... ................... Glossary............................................ 163 169 169 169 Mechanical, Packaging, and Orderable Information ............................................. 170 Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 2 Revision History Changes from May 29, 2014 to September 28, 2018 • • • • • • • • • • • • • • • • • • • • • • • • • • Page Updated Section 1.1, Features ..................................................................................................... 1 Updated Section 1.3, Description .................................................................................................. 2 Added Section 3.1, Related Products ............................................................................................. 7 Corrected the port number (P4.2) on pin 61 in Figure 4-2, 100-Pin PZ Package (Top View) ............................ 10 Added note to P1.3/ADC10CLK/A3 (pin 8) in Table 4-3, Terminal Functions – PEU Package........................... 12 Added typical conditions statements at the beginning of Section 5, Specifications ........................................ 26 Added SD24_B input pins and AUXVCCx pins to exception list on "Voltage applied to pins" parameter, and added SD24_B input pin limits in "Diode current at pins" parameter in Section 5.1, Absolute Maximum Ratings ..... 26 Added Section 5.2, ESD Ratings.................................................................................................. 26 Added Section 5.7, Thermal Resistance Characteristics ...................................................................... 31 Updated notes (1) and (2) and added note (3) in Table 5-1, Wake-up Times From Low-Power Modes and Reset .. 32 Changed the TYP value of the CL,eff parameter with Test Conditions of "XTS = 0, XCAPx = 0" from 2 pF to 1 pF in Table 5-2, Crystal Oscillator, XT1, Low-Frequency Mode .................................................................. 33 Corrected bit name in Test Conditions of RCHARGE parameter (changed CHCx to AUXCHCx) in Table 5-25, Auxiliary Supplies, Charge Limiting Resistor .................................................................................... 44 Replaced fFrame parameter with fLCD, fFRAME,4mux, and fFRAME,8mux parameters in Table 5-37, LCD_C, Operating Conditions ............................................................................................................................ 52 On the VID,FS parameter in Table 5-39, SD24_B Power Supply and Recommended Operating Conditions: Changed the MIN value from "VREF/GAIN" to "–VREF/GAIN"; Removed "Unipolar mode" test condition (mode is not supported) ....................................................................................................................... 54 Removed ADC10DIV from the formula for the TYP value in the second row of the tCONVERT parameter in Table 548, 10-Bit ADC, Switching Characteristics, because ADC10CLK is after division .......................................... 60 Changed Test Conditions for all parameters in Table 5-49, 10-Bit ADC Linearity Parameters: Removed "VREF–"; Changed from "(VeREF+ – VeREF–)min ≤ (VeREF+ – VeREF–)" to "1.4 V ≤ (VeREF+ – VeREF–)"; Changed from "CVREF+ = 20 pF" to "CVeREF+ = 20 pF"; Added "CVeREF+ = 20 pF" to EI; Added "ADC10SREFx = 11b" to ET and EG .............. 61 Changed from "VREF–/VeREF–" to "VeREF–" in Test Conditions for VeREF+, VeREF–, and (VeREF+ – VeREF–) parameters in Table 5-50, 10-Bit ADC, External Reference ................................................................................. 61 Changed the MIN value of AVCC(min) with Test Conditions of "REFVSEL = {0} for 1.5 V" from 2.2 V to 1.8 V in Table 5-51, REF Built-In Reference .............................................................................................. 62 Changed the MAX value of the tEN_CMP parameter with Test Conditions of "CBPWRMD = 10" from 50 µs to 100 µs in Table 5-52, Comparator_B ............................................................................................. 63 Corrected the name of the RTC module (changed from RTC_CE to RTC_C) in Figure 6-1, Functional Block Diagram – PEU Package ........................................................................................................... 66 Corrected the name of the RTC module (changed from RTC_CE to RTC_C) in Figure 6-2, Functional Block Diagram – PZ Package ............................................................................................................. 66 Throughout document, changed all instances of "bootstrap loader" to "bootloader" ....................................... 72 Corrected spelling of NMIIFG in Table 6-13, System Module Interrupt Vector Registers ................................. 80 Deleted mention of counter mode in Section 6.11.22, Real-Time Clock (RTC_C) (feature is not supported in this device) ................................................................................................................................ 85 Replaced former section Development Tools Support with Section 8.3, Tools and Software .......................... 165 Changed format and added content to Section 8.4, Documentation Support ............................................. 167 Revision History Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 5 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com 3 Device Comparison Table 3-1 summarizes the available family members. Table 3-1. Device Comparison (1) (2) eUSCI (1) (2) (3) 6 CHANNEL A: UART, IrDA, SPI CHANNEL B: SPI, I2C I/Os PACKAGE 3, 2, 2, 2 4 2 90 128 PEU 3, 2, 2, 2 4 2 90 128 PEU 6 ext, 2 int 3, 2, 2, 2 4 2 90 128 PEU 7 6 ext, 2 int 3, 2, 2, 2 4 2 90 128 PEU 16 7 6 ext, 2 int 3, 2, 2, 2 4 2 90 128 PEU 512 32 6 6 ext, 2 int 3, 2, 2, 2 4 2 90 128 PEU MSP430F6768AIPEU 512 16 6 6 ext, 2 int 3, 2, 2, 2 4 2 90 128 PEU MSP430F6767AIPEU 256 32 6 6 ext, 2 int 3, 2, 2, 2 4 2 90 128 PEU MSP430F6766AIPEU 256 16 6 6 ext, 2 int 3, 2, 2, 2 4 2 90 128 PEU MSP430F6765AIPEU 128 16 6 6 ext, 2 int 3, 2, 2, 2 4 2 90 128 PEU MSP430F6749AIPEU 512 32 4 6 ext, 2 int 3, 2, 2, 2 4 2 90 128 PEU MSP430F6748AIPEU 512 16 4 6 ext, 2 int 3, 2, 2, 2 4 2 90 128 PEU MSP430F6747AIPEU 256 32 4 6 ext, 2 int 3, 2, 2, 2 4 2 90 128 PEU MSP430F6746AIPEU 256 16 4 6 ext, 2 int 3, 2, 2, 2 4 2 90 128 PEU MSP430F6745AIPEU 128 16 4 6 ext, 2 int 3, 2, 2, 2 4 2 90 128 PEU MSP430F6779AIPZ 512 32 7 6 ext, 2 int 3, 2, 2, 2 4 2 62 100 PZ MSP430F6778AIPZ 512 16 7 6 ext, 2 int 3, 2, 2, 2 4 2 62 100 PZ MSP430F6777AIPZ 256 32 7 6 ext, 2 int 3, 2, 2, 2 4 2 62 100 PZ MSP430F6776AIPZ 256 16 7 6 ext, 2 int 3, 2, 2, 2 4 2 62 100 PZ MSP430F6775AIPZ 128 16 7 6 ext, 2 int 3, 2, 2, 2 4 2 62 100 PZ MSP430F6769AIPZ 512 32 6 6 ext, 2 int 3, 2, 2, 2 4 2 62 100 PZ MSP430F6768AIPZ 512 16 6 6 ext, 2 int 3, 2, 2, 2 4 2 62 100 PZ MSP430F6767AIPZ 256 32 6 6 ext, 2 int 3, 2, 2, 2 4 2 62 100 PZ MSP430F6766AIPZ 256 16 6 6 ext, 2 int 3, 2, 2, 2 4 2 62 100 PZ MSP430F6765AIPZ 128 16 6 6 ext, 2 int 3, 2, 2, 2 4 2 62 100 PZ MSP430F6749AIPZ 512 32 4 6 ext, 2 int 3, 2, 2, 2 4 2 62 100 PZ MSP430F6748AIPZ 512 16 4 6 ext, 2 int 3, 2, 2, 2 4 2 62 100 PZ MSP430F6747AIPZ 256 32 4 6 ext, 2 int 3, 2, 2, 2 4 2 62 100 PZ MSP430F6746AIPZ 256 16 4 6 ext, 2 int 3, 2, 2, 2 4 2 62 100 PZ MSP430F6745AIPZ 128 16 4 6 ext, 2 int 3, 2, 2, 2 4 2 62 100 PZ DEVICE FLASH (KB) SRAM (KB) SD24_B CONVERTERS ADC10_A CHANNELS MSP430F6779AIPEU 512 32 7 6 ext, 2 int MSP430F6778AIPEU 512 16 7 6 ext, 2 int MSP430F6777AIPEU 256 32 7 MSP430F6776AIPEU 256 16 MSP430F6775AIPEU 128 MSP430F6769AIPEU Timer_A (3) For the most current package and ordering information, see the Package Option Addendum in Section 9, or see the TI website at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively. Device Comparison Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com 3.1 SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Related Products For information about other devices in this family of products or related products, see the following links. Products for TI Microcontrollers TI's low-power and high-performance MCUs, with wired and wireless connectivity options, are optimized for a broad range of applications. Products for MSP430 Ultra-Low-Power Microcontrollers One platform. One ecosystem. Endless possibilities. Enabling the connected world with innovations in ultra-low-power microcontrollers with advanced peripherals for precise sensing and measurement. Companion Products for MSP430F6779A Review products that are frequently purchased or used with this product. Reference Designs for MSP430F6779A The TI Designs Reference Design Library is a robust reference design library that spans analog, embedded processor, and connectivity. Created by TI experts to help you jump start your system design, all TI Designs include schematic or block diagrams, BOMs, and design files to speed your time to market. Device Comparison Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 7 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com 4 Terminal Configuration and Functions 4.1 Pin Diagrams SD0N0 SD0P0 SD1P0 SD1N0 SD2N0 SD2P0 SD3P0 SD3N0 VASYS2 AVSS2 VREF SD4P0 SD4N0 SD5P0 SD5N0 SD6P0 SD6N0 AVSS1 AVCC VASYS1 AUXVCC2 AUXVCC1 93 P2.0/PM_TA0.0/BSL_TX P1.0/TA1.1/VeREF-/A0 11 92 P11.5/TACLK/RTCCLK P2.4/PM_TA2.0 12 91 P11.4/CBOUT P2.5/PM_UCB0SOMI/PM_UCB0SCL 13 90 P11.3/TA2.1 P2.6/PM_UCB0SIMO/PM_UCB0SDA 14 89 P11.2/TA1.1 P2.7/PM_UCB0CLK 15 88 P11.1/TA3.1/CB3 P3.0/PM_UCA0RXD/PM_UCA0SOMI 16 87 P11.0/S0 P3.1/PM_UCA0TXD/PM_UCA0SIMO 17 86 P10.7/S1 P3.2/PM_UCA0CLK 18 85 P10.6/S2 P3.3/PM_UCA1CLK 19 84 P10.5/S3 P3.4/PM_UCA1RXD/PM_UCA1SOMI 20 83 P10.4/S4 P3.5/PM_UCA1TXD/PM_UCA1SIMO 21 82 P10.3/S5 COM0 22 81 P10.2/S6 COM1 23 80 P10.1/S7 P1.6/COM2 24 79 P10.0/S8 P1.7/COM3 25 78 P9.7/S9 P5.0/COM4 26 77 P9.6/S10 P5.1/COM5 27 76 P9.5/S11 P5.2/COM6 28 75 P9.4/S12 P5.3/COM7 29 74 P9.3/S13 LCDCAP/R33 30 73 P9.2/S14 P5.4/SDCLK/R23 31 72 P9.1/S15 P5.5/SD0DIO/LCDREF/R13 32 71 P9.0/S16 P5.6/SD1DIO/R03 33 70 DVSS2 P5.7/SD2DIO/CB2 34 69 VDSYS2 P6.0/SD3DIO 35 68 P8.7/S17 P3.6/PM_UCA2RXD/PM_UCA2SOMI 36 67 P8.6/S18 P3.7/PM_UCA2TXD/PM_UCA2SIMO 37 66 P8.5/S19 38 65 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 P8.4/S20 P8.3/S21 10 P8.2/S22 P2.1/PM_TA0.1/BSL_RX P1.1/TA2.1/VeREF+/A1 P8.1/S23 94 P8.0/S24 9 P7.7/S25 P2.2/PM_TA0.2 P1.2/ACLK/A2 P7.6/S26 95 P7.5/S27 8 P7.4/S28 P2.3/PM_TA1.0 P1.3/ADC10CLK/A3 P7.3/S29 96 P7.2/S30 7 P7.1/S31 TEST/SBWTCK P1.4/MCLK/CB1/A4 P7.0/S32 97 P6.7/S33 6 P6.6/S34 PJ.0/TDO P1.5/SMCLK/CB0/A5 P6.5/S35 98 P6.4/S36 5 P6.3/SD6DIO/S37 PJ.1/TDI/TCLK RTCCAP0 P6.2/SD5DIOS38 99 P6.1/SD4DIO/S39 4 P4.7/PM_TA3.0 PJ.2/TMS RTCCAP1 P4.6/PM_UCB1CLK 100 P4.1/PM_UCA3RXD/M_UCA3SOMI C. VDSYS1 3 P4.4/PM_UCB1SOMI/PM_UCB1SCL PJ.3/TCK AUXVCC3 P4.5/PM_UCB1SIMO/PM_UCB1SDA 101 P4.0/PM_UCA2CLK B. DVSS1 2 P4.3/PM_UCA3CLK RST/NMI/SBWTDIO XOUT P4.2/PM_UCA3TXD/PM_UCA3SIMO 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 1 102 XIN A. DVCC VCORE Figure 4-1 shows the pinout for the 128-pin PEU package. Table 4-1 summarizes the differences in the pinout among the device variants. The secondary digital functions on Ports P2, P3, and P4 are fully mappable. This pinout shows only the default mapping. See Section 6.11.6 for details. The pair of pins VDSYS1 and VDSYS2, VASYS1 and VASYS2 must be connected externally on board for proper device operation. CAUTION: The LCDCAP/R33 pin must be connected to DVSS if it is not used. Figure 4-1. 128-Pin PEU Package (Top View) 8 Terminal Configuration and Functions Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 4-1. Pinout Differences for PEU Package, F677xA, F676xA, and F674xA PIN NAME PIN NUMBER MSP430F677xAIPEU MSP430F676xAIPEU MSP430F674xAIPEU 46 P6.1/SD4DIO/S39 P6.1/SD4DIO/S39 P6.1/S39 47 P6.2/SD5DIO/S38 P6.2/SD5DIO/S38 P6.2/S38 48 P6.3/SD6DIO/S37 P6.3/S37 P6.3/S37 113 VREF VREF VREF 114 SD4P0 SD4P0 NC 115 SD4N0 SD4N0 NC 116 SD5P0 SD5P0 NC 117 SD5N0 SD5NO NC 118 SD6P0 NC NC 119 SD6N0 NC NC Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 9 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com C. DVSS2 P6.0/S16 P6.1/S15 P6.3/S13 P6.2/S14 P6.4/S12 P6.5/S11 P6.6/S10 P6.7/S9 P7.0/S8 P7.1/S7 P7.2/S6 P7.3/S5 P7.4/S4 P7.5/S3 P7.6/S2 P7.7/S1 P8.0/S0 P8.1/TACLK/RTCCLKCB3 TEST/SBWTCK PJ.0/TDO PJ.1TDI/TCLK 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 VDSYS2 SD0N0 2 74 P5.7/SD6DIO/S17 SD1P0 3 73 P5.6/SD5DIO/S18 SD1N0 4 72 P5.5/SD4DIO/S19 SD2P0 5 71 P5.4/SD3DIO/S20 SD2N0 6 70 P5.3/SD2DIO/S21 SD3P0 7 69 P5.2/SD1DIO/S22 SD3N0 8 68 P5.1/SD0DIO/S23 VASYS2 9 67 P5.0/SDCLK/S24 AVSS2 10 66 P4.7/PM_TA3.0/S25 VREF 11 65 P4.6/PM_UCB1CLK/S26 SD4P0 12 64 P4.5/PM_UCB1SIMO/PM_UCB1SDA/S27 SD4N0 13 63 P4.4/PM_UCB1SOMI/PM_UCB1SCL/S28 SD5P0 14 62 P4.3/PM_UCA3CLK/S29 SD5N0 15 61 P4.2/PM_UCA3TXD/PM_UCA3SIMO/S30 SD6P0 16 60 P4.1/PM_UCA3RXD/PM_UCA3SOMI/S31 SD6N0 17 59 P4.0/PM_UCA2CLK/S32 AVSS1 18 58 P3.7/PM_UCA2TXD/PM_UCA2SIMO/S33 AVCC 19 57 P3.6/PM_UCA2RXD/PM_UCA2SOMI/S34 VASYS1 20 56 P3.5/PM_UCA1TXD/PM_UCA1SIMO/S35 AUXVCC2 21 55 P3.4/PM_UCA1RXD/PM_UCA1SOMI/S36 AUXVCC1 22 54 P3.3/PM_UCA1CLK/S37 VDSYS1 23 53 P3.2/PM_UCA0CLK/S38 DVCC 24 52 P3.1/PM_UCA0TXD/PM_UCA0SIMO/S39 P3.0/PM_UCA0RXD/PM_UCA0SOMI P2.7/PM_UCB0CLK/CB2 P2.6/PM_UCB0SIMO/PM_UCB0SDA/R03 P2.5/PM_UCB0SOMI/PM_UCB0SCL/LCDREF/R13 P2.4/PM_TA2.0/R23 LCDCAP/R33 P2.3/PM_TA1.0/COM7 P2.2/PM_TA0.2/COM6 P2.1/PM_TA0.1/BSL_RX/COM5 P2.0/PM_TA0.0/BSL_TX/COM4 P1.7/COM3 P1.6/COM2 COM1 COM0 P1.0/TA1.1/VeREF-/A0 P1.1/TA2.1/CBOUT/VeREF+/A1 P1.2/ACLK/A2 P1.3/ADC10CLK/A3 P1.4/MCLK/CB1/A4 P1.5/SMCLK/CB0/A5 RTCCAP0 RTCCAP1 AUXVCC3 XOUT XIN 25 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VCORE B. PJ.3/TCK SD0P0 DVSS1 A. PJ.2/TMS RST/NMI/SBWTDIO Figure 4-2 shows the pinout for the 100-pin PZ package. Table 4-2 summarizes the differences in the pinout among the device variants. The secondary digital functions on Ports P2, P3, and P4 are fully mappable. This pinout shows only the default mapping. See Section 6.11.6 for details. The pair of pins VDSYS1 and VDSYS2, VASYS1 and VASYS2 must be connected externally on board for proper device operation. CAUTION: The LCDCAP/R33 pin must be connected to DVSS if it is not used. Figure 4-2. 100-Pin PZ Package (Top View) 10 Terminal Configuration and Functions Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 4-2. Pinout Differences for PZ Package, F677xA, F676xA, and F674xA PIN NAME PIN NUMBER MSP430F677xAIPZ MSP430F676xAIPZ MSP430F674xAIPZ 11 VREF VREF VREF 12 SD4P0 SD4P0 NC 13 SD4N0 SD4N0 NC 14 SD5P0 SD5P0 NC 15 SD5N0 SD5NO NC 16 SD6P0 NC NC 17 SD6N0 NC NC 72 P5.5/SD4DIO/S19 P5.5/SD4DIO/S19 P5.5/S19 73 P5.6/SD5DIO/S18 P5.6/SD5DIO/S18 P5.6/S18 74 P5.7/SD6DIO/S17 P5.7/S17 P5.7/S17 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 11 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 4.2 www.ti.com Signal Descriptions Table 4-3 describes the signals for devices in the PEU package. See Table 4-4 for the signals in the PZ package. Table 4-3. Terminal Functions – PEU Package TERMINAL NAME NO. I/O (1) DESCRIPTION PEU XIN 1 I/O Input terminal for crystal oscillator XOUT 2 I/O Output terminal for crystal oscillator AUXVCC3 3 RTCCAP1 4 I External time capture pin 1 for RTC_C RTCCAP0 5 I External time capture pin 0 for RTC_C Auxiliary power supply AUXVCC3 for backup subsystem General-purpose digital I/O with port interrupt P1.5/SMCLK/CB0/A5 6 I/O SMCLK clock output Comparator_B input CB0 Analog input A5 for 10-bit ADC General-purpose digital I/O with port interrupt P1.4/MCLK/CB1/A4 7 I/O MCLK clock output Comparator_B input CB1 Analog input A4 for 10-bit ADC General-purpose digital I/O with port interrupt P1.3/ADC10CLK/A3 (2) 8 I/O ADC10_A clock output Analog input A3 for 10-bit ADC General-purpose digital I/O with port interrupt P1.2/ACLK/A2 9 I/O ACLK clock output Analog input A2 for 10-bit ADC General-purpose digital I/O with port interrupt P1.1/TA2.1/VeREF+/A1 10 I/O Timer TA2 CCR1 capture: CCI1A input, compare: Out1 output Positive terminal for the ADC reference voltage for an external applied reference voltage Analog input A1 for 10-bit ADC General-purpose digital I/O with port interrupt P1.0/TA1.1/VeREF-/A0 11 I/O Timer TA1 CCR1 capture: CCI1A input, compare: Out1 output Negative terminal for the ADC reference voltage for an external applied reference voltage Analog input A0 for 10-bit ADC P2.4/PM_TA2.0 12 I/O P2.5/PM_UCB0SOMI/ PM_UCB0SCL 13 I/O P2.6/PM_UCB0SIMO/ PM_UCB0SDA 14 P2.7/PM_UCB0CLK 15 General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: Timer TA2 capture CCR0: CCI0A input, compare: Out0 output General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: eUSCI_B0 SPI slave out master in Default mapping: eUSCI_B0 I2C clock General-purpose digital I/O with port interrupt and mappable secondary function (1) (2) 12 I/O Default mapping: eUSCI_B0 SPI slave in master out Default mapping: eUSCI_B0 I2C data I/O General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: eUSCI_B0 clock input/output I = input, O = output Before enabling the analog function (A3), pull this pin low by setting the port function to output low or to input with the internal pulldown resistor enabled. Terminal Configuration and Functions Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 4-3. Terminal Functions – PEU Package (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION PEU General-purpose digital I/O with mappable secondary function P3.0/PM_UCA0RXD/ PM_UCA0SOMI 16 I/O Default mapping: eUSCI_A0 UART receive data Default mapping: eUSCI_A0 SPI slave out master in General-purpose digital I/O with mappable secondary function P3.1/PM_UCA0TXD/ PM_UCA0SIMO 17 I/O Default mapping: eUSCI_A0 UART transmit data Default mapping: eUSCI_A0 SPI slave in master out P3.2/PM_UCA0CLK 18 I/O P3.3/PM_UCA1CLK 19 I/O P3.4/PM_UCA1RXD/ PM_UCA1SOMI 20 I/O General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A0 clock input/output General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A1 clock input/output General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A1 UART receive data Default mapping: eUSCI_A1 SPI slave out master in General-purpose digital I/O with mappable secondary function P3.5/PM_UCA1TXD/ PM_UCA1SIMO 21 I/O COM0 22 O LCD common output COM0 for LCD backplane COM1 23 O LCD common output COM1 for LCD backplane P1.6/COM2 24 I/O P1.7/COM3 25 I/O P5.0/COM4 26 I/O P5.1/COM5 27 I/O P5.2/COM6 28 I/O P5.3/COM7 29 I/O LCDCAP/R33 30 I/O Default mapping: eUSCI_A1 UART transmit data Default mapping: eUSCI_A1 SPI slave in master out General-purpose digital I/O with port interrupt LCD common output COM2 for LCD backplane General-purpose digital I/O with port interrupt LCD common output COM3 for LCD backplane General-purpose digital I/O LCD common output COM4 for LCD backplane General-purpose digital I/O LCD common output COM5 for LCD backplane General-purpose digital I/O LCD common output COM6 for LCD backplane General-purpose digital I/O LCD common output COM7 for LCD backplane LCD capacitor connection Input/output port of most positive analog LCD voltage (V1) CAUTION: This pin must be connected to DVSS if not used. General-purpose digital I/O P5.4/SDCLK/R23 31 I/O SD24_B bit-stream clock input/output Input/Output port of second most positive analog LCD voltage (V2) General-purpose digital I/O P5.5/SD0DIO/ LCDREF/R13 32 I/O SD24_B converter 0 bit-stream data input/output External reference voltage input for regulated LCD voltage Input/output port of third most positive analog LCD voltage (V3 or V4) General-purpose digital I/O P5.6/SD1DIO/R03 33 I/O SD24_B converter 1 bit-stream data input/output Input/output port of lowest analog LCD voltage (V5) Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 13 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 4-3. Terminal Functions – PEU Package (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION PEU General-purpose digital I/O P5.7/SD2DIO/CB2 34 I/O SD24_B converter 2 bit-stream data input/output Comparator_B input CB2 P6.0/SD3DIO 35 I/O P3.6/PM_UCA2RXD/ PM_UCA2SOMI 36 I/O General-purpose digital I/O SD24_B converter 3 bit-stream data input/output General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A2 UART receive data Default mapping: eUSCI_A2 SPI slave out master in General-purpose digital I/O with mappable secondary function P3.7/PM_UCA2TXD/ PM_UCA2SIMO 37 I/O Default mapping: eUSCI_A2 UART transmit data Default mapping: eUSCI_A2 SPI slave in master out P4.0/PM_UCA2CLK 38 I/O P4.1/PM_UCA3RXD/ PM_UCA3SOMI 39 I/O General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A2 clock input/output General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A3 UART receive data Default mapping: eUSCI_A3 SPI slave out master in General-purpose digital I/O with mappable secondary function P4.2/PM_UCA3TXD/ PM_UCA3SIMO 40 I/O Default mapping: eUSCI_A3 UART transmit data Default mapping: eUSCI_A3 SPI slave in master out P4.3/PM_UCA3CLK 41 I/O General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A3 clock input/output General-purpose digital I/O with mappable secondary function P4.4/PM_UCB1SOMI/ PM_UCB1SCL 42 I/O Default mapping: eUSCI_B1 SPI slave out, master in Default mapping: eUSCI_B1 I2C clock General-purpose digital I/O with mappable secondary function P4.5/PM_UCB1SIMO/ PM_UCB1SDA 43 P4.6/PM_UCB1CLK 44 I/O P4.7/PM_TA3.0 45 I/O I/O Default mapping: eUSCI_B1 SPI slave in, master out Default mapping: eUSCI_B1 I2C data General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_B1 clock input/output General-purpose digital I/O with mappable secondary function Default mapping: Timer TA3 capture CCR0: CCI0A input, compare: Out0 output General-purpose digital I/O P6.1/SD4DIO/S39 46 I/O SD24_B converter 4 bit-stream data input/output (not available in F674xA devices) LCD segment output S39 General-purpose digital I/O P6.2/SD5DIO/S38 47 I/O SD24_B converter 5 bit-stream data input/output (not available in F674xA devices) LCD segment output S38 General-purpose digital I/O P6.3/SD6DIO/S37 48 I/O SD24_B converter 6 bit-stream data input/output (not available in F676xA, F674xA devices) LCD segment output S37 P6.4/S36 49 I/O P6.5/S35 50 I/O 14 General-purpose digital I/O LCD segment output S36 General-purpose digital I/O LCD segment output S35 Terminal Configuration and Functions Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 4-3. Terminal Functions – PEU Package (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION PEU General-purpose digital I/O P6.6/S34 51 I/O P6.7/S33 52 I/O P7.0/S32 53 I/O P7.1/S31 54 I/O P7.2/S30 55 I/O P7.3/S29 56 I/O P7.4/S28 57 I/O P7.5/S27 58 I/O P7.6/S26 59 I/O P7.7/S25 60 I/O P8.0/S24 61 I/O P8.1/S23 62 I/O P8.2/S22 63 I/O P8.3/S21 64 I/O P8.4/S20 65 I/O P8.5/S19 66 I/O P8.6/S18 67 I/O P8.7/S17 68 I/O VDSYS2 (3) 69 Digital power supply for I/Os DVSS2 70 Digital ground supply P9.0/S16 71 I/O P9.1/S15 72 I/O P9.2/S14 73 I/O (3) LCD segment output S34 General-purpose digital I/O LCD segment output S33 General-purpose digital I/O LCD segment output S32 General-purpose digital I/O LCD segment output S31 General-purpose digital I/O LCD segment output S30 General-purpose digital I/O LCD segment output S29 General-purpose digital I/O LCD segment output S28 General-purpose digital I/O LCD segment output S27 General-purpose digital I/O LCD segment output S26 General-purpose digital I/O LCD segment output S25 General-purpose digital I/O LCD segment output S24 General-purpose digital I/O LCD segment output S23 General-purpose digital I/O LCD segment output S22 General-purpose digital I/O LCD segment output S21 General-purpose digital I/O LCD segment output S20 General-purpose digital I/O LCD segment output S19 General-purpose digital I/O LCD segment output S18 General-purpose digital I/O LCD segment output S17 General-purpose digital I/O LCD segment output S16 General-purpose digital I/O LCD segment output S15 General-purpose digital I/O LCD segment output S14 The pins VDSYS1 and VDSYS2 must be connected externally on board for proper device operation. Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 15 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 4-3. Terminal Functions – PEU Package (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION PEU P9.3/S13 74 I/O P9.4/S12 75 I/O P9.5/S11 76 I/O P9.6/S10 77 I/O P9.7/S9 78 I/O P10.0/S8 79 I/O P10.1/S7 80 I/O P10.2/S6 81 I/O P10.3/S5 82 I/O P10.4/S4 83 I/O P10.5/S3 84 I/O P10.6/S2 85 I/O P10.7/S1 86 I/O P11.0/S0 87 I/O General-purpose digital I/O LCD segment output S13 General-purpose digital I/O LCD segment output S12 General-purpose digital I/O LCD segment output S11 General-purpose digital I/O LCD segment output S10 General-purpose digital I/O LCD segment output S9 General-purpose digital I/O LCD segment output S8 General-purpose digital I/O LCD segment output S7 General-purpose digital I/O LCD segment output S6 General-purpose digital I/O LCD segment output S5 General-purpose digital I/O LCD segment output S4 General-purpose digital I/O LCD segment output S3 General-purpose digital I/O LCD segment output S2 General-purpose digital I/O LCD segment output S1 General-purpose digital I/O LCD segment output S0 General-purpose digital I/O P11.1/TA3.1/CB3 88 I/O Timer TA3 capture CCR1: CCI1A input, compare: Out1 output Comparator_B input CB3 P11.2/TA1.1 89 I/O P11.3/TA2.1 90 I/O P11.4/CBOUT 91 I/O P11.5/TACLK/RTCCLK 92 I/O General-purpose digital I/O Timer TA1 capture CCR1: CCI1A input, compare: Out1 output General-purpose digital I/O Timer TA2 capture CCR1: CCI1A input, compare: Out1 output General-purpose digital I/O Comparator_B output General-purpose digital I/O Timer clock input TACLK for TA0, TA1, TA2, TA3 RTCCLK clock output General-purpose digital I/O with port interrupt and mappable secondary function P2.0/PM_TA0.0/BSL_TX 93 I/O Default mapping: Timer TA0 capture CCR0: CCI0A input, compare: Out0 output Bootloader: Data transmit 16 Terminal Configuration and Functions Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 4-3. Terminal Functions – PEU Package (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION PEU General-purpose digital I/O with port interrupt and mappable secondary function P2.1/PM_TA0.1/BSL_RX 94 I/O Default mapping: Timer TA0 capture CCR1: CCI1A input, compare: Out1 output Bootloader: Data receive P2.2/PM_TA0.2 95 I/O P2.3/PM_TA1.0 96 I/O TEST/SBWTCK 97 I PJ.0/TDO 98 I/O General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: Timer TA0 capture CCR2: CCI2A input, compare: Out2 output General-purpose digital I/O port interrupt and with mappable secondary function Default mapping: Timer TA1 capture CCR0: CCI0A input, compare: Out0 output Test mode pin – select digital I/O on JTAG pins Spy-Bi-Wire input clock General-purpose digital I/O Test data output General-purpose digital I/O PJ.1/TDI/TCLK 99 I/O Test data input Test clock input PJ.2/TMS 100 I/O PJ.3/TCK 101 I/O General-purpose digital I/O Test mode select General-purpose digital I/O Test clock Reset input, active-low (4) RST/NMI/SBWTDIO 102 I/O Nonmaskable interrupt input SD0P0 103 I SD24_B positive analog input for converter 0 (5) SD0N0 104 I SD24_B negative analog input for converter 0 (5) SD1P0 105 I SD24_B positive analog input for converter 1 (5) SD1N0 106 I SD24_B negative analog input for converter 1 (5) SD2P0 107 I SD24_B positive analog input for converter 2 (5) SD2N0 108 I SD24_B negative analog input for converter 2 (5) SD3P0 109 I SD24_B positive analog input for converter 3 (5) SD3N0 110 I SD24_B negative analog input for converter 3 (4) VASYS2 111 Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of CVSYS. AVSS2 112 Analog ground supply VREF 113 I SD24_B external reference voltage SD4P0 114 I SD24_B positive analog input for converter 4 (5) (not available on F674xA devices) SD4N0 115 I SD24_B negative analog input for converter 4 (5) (not available on F674xA devices) SD5P0 116 I SD24_B positive analog input for converter 5 (5) (not available on F674xA devices) SD5N0 117 I SD24_B negative analog input for converter 5 (5) (not available on F674xA devices) SD6P0 118 I SD24_B positive analog input for converter 6 (5) (not available on F676xA, F674xA devices) SD6N0 119 I SD24_B negative analog input for converter 6 (5) (not available on F676xA, F674xA devices) AVSS1 120 Analog ground supply AVCC 121 Analog power supply VASYS1 122 Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of CVSYS. AUXVCC2 123 Auxiliary power supply AUXVCC2 Spy-By-Wire data input/output (4) (5) When this pin is configured as reset, the internal pullup resistor is enabled by default. TI recommends shorting unused analog input pairs and connecting them to analog ground. Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 17 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 4-3. Terminal Functions – PEU Package (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION PEU AUXVCC1 124 Auxiliary power supply AUXVCC1 VDSYS1 (3) 125 Digital power supply selected between DVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of CVSYS. DVCC 126 Digital power supply DVSS1 127 Digital ground supply VCORE (6) 128 Regulated core power supply (internal use only, no external current loading) (6) 18 VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended capacitor value, CVCORE. Terminal Configuration and Functions Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 4-4 describes the signals for devices in the PZ package. See Table 4-3 for the signals in the PEU package. Table 4-4. Terminal Functions – PZ Package TERMINAL NAME NO. I/O (1) DESCRIPTION PZ SD0P0 1 I SD24_B positive analog input for converter 0 (2) SD0N0 2 I SD24_B negative analog input for converter 0 (2) SD1P0 3 I SD24_B positive analog input for converter 1 (2) SD1N0 4 I SD24_B negative analog input for converter 1 (2) SD2P0 5 I SD24_B positive analog input for converter 2 (2) SD2N0 6 I SD24_B negative analog input for converter 2 (2) SD3P0 7 I SD24_B positive analog input for converter 3 (2) SD3N0 8 I SD24_B negative analog input for converter 3 (2) VASYS2 9 AVSS2 10 VREF 11 I SD24_B external reference voltage SD4P0 12 I SD24_B positive analog input for converter 4 (2) (not available on F674x devices) SD4N0 13 I SD24_B negative analog input for converter 4 (2) (not available on F674xA devices) SD5P0 14 I SD24_B positive analog input for converter 5 (2) (not available on F674xA devices) SD5N0 15 I SD24_B negative analog input for converter 5 (2) (not available on F674xA devices) SD6P0 16 I SD24_B positive analog input for converter 6 (2) (not available on F676xA, F674xA devices) SD6N0 17 I SD24_B negative analog input for converter 6 (2) (not available on F676xA, F674xA devices) AVSS1 18 Analog ground supply AVCC 19 Analog power supply VASYS1 20 Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of CVSYS AUXVCC2 21 Auxiliary power supply AUXVCC2 AUXVCC1 22 Auxiliary power supply AUXVCC1 23 Digital power supply selected between DVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of CVSYS. 24 Digital power supply 25 Digital ground supply VDSYS1 (3) DVCC DVSS1 VCORE (4) Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of CVSYS. Analog ground supply 26 Regulated core power supply (internal use only, no external current loading) XIN 27 I/O Input terminal for crystal oscillator XOUT 28 I/O Output terminal for crystal oscillator AUXVCC3 29 RTCCAP1 30 I External time capture pin 1 for RTC_C RTCCAP0 31 I External time capture pin 0 for RTC_C Auxiliary power supply AUXVCC3 for backup subsystem General-purpose digital I/O with port interrupt P1.5/SMCLK/CB0/A5 32 I/O SMCLK clock output Comparator_B input CB0 Analog input A5 for 10-bit ADC (1) (2) (3) (4) I = input, O = output TI recommends shorting unused analog input pairs and connecting them to analog ground. The pins VDSYS1 and VDSYS2 must be connected externally on board for proper device operation. VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended capacitor value, CVCORE. Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 19 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 4-4. Terminal Functions – PZ Package (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION PZ General-purpose digital I/O with port interrupt P1.4/MCLK/CB1/A4 33 I/O MCLK clock output Comparator_B input CB1 Analog input A4 for 10-bit ADC General-purpose digital I/O with port interrupt P1.3/ADC10CLK/A3 34 I/O ADC10_A clock output Analog input A3 for 10-bit ADC General-purpose digital I/O with port interrupt P1.2/ACLK/A2 35 I/O ACLK clock output Analog input A2 for 10-bit ADC General-purpose digital I/O with port interrupt Timer TA2 CCR1 capture: CCI1A input, compare: Out1 output P1.1/TA2.1/CBOUT/ VeREF+/A1 36 I/O Comparator_B Output Positive terminal for the ADC reference voltage for an external applied reference voltage Analog input A1 for 10-bit ADC General-purpose digital I/O with port interrupt P1.0/TA1.1/VeREF-/A0 37 I/O Timer TA1 CCR1 capture: CCI1A input, compare: Out1 output Negative terminal for the ADC reference voltage for an external applied reference voltage Analog input A0 for 10-bit ADC COM0 38 I/O LCD common output COM0 for LCD backplane COM1 39 I/O LCD common output COM1 for LCD backplane P1.6/COM2 40 I/O P1.7/COM3 41 I/O General-purpose digital I/O with port interrupt LCD common output COM2 for LCD backplane General-purpose digital I/O with port interrupt LCD common output COM3 for LCD backplane General-purpose digital I/O with port interrupt and mappable secondary function P2.0/PM_TA0.0/ BSL_TX/COM4 42 I/O Default Mapping: Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output Bootloader: Data transmit LCD common output COM4 for LCD backplane General-purpose digital I/O with port interrupt and mappable secondary function P2.1/PM_TA0.1/ BSL_RX/COM5 43 I/O Default Mapping: Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output Bootloader: Data receive LCD common output COM5 for LCD backplane General-purpose digital I/O with port interrupt and mappable secondary function P2.2/PM_TA0.2/COM6 44 I/O Default Mapping: Timer TA0 CCR0 capture: CCI2A input, compare: Out2 output LCD common output COM6 for LCD backplane General-purpose digital I/O with port interrupt and mappable secondary function P2.3/PM_TA1.0/COM7 45 I/O Default Mapping: Timer TA1 CCR0 capture: CCI0A input, compare: Out0 output LCD common output COM7 for LCD backplane LCD capacitor connection LCDCAP/R33 46 I/O Input/output port of most positive analog LCD voltage (V1) CAUTION: This pin must be connected to DVSS if not used. General-purpose digital I/O with port interrupt and mappable secondary function P2.4/PM_TA2.0/R23 47 I/O Default Mapping: Timer TA2 CCR0 capture: CCI0A input, compare: Out0 output Input/output port of second most positive analog LCD voltage (V2) 20 Terminal Configuration and Functions Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 4-4. Terminal Functions – PZ Package (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION PZ General-purpose digital I/O with port interrupt and mappable secondary function P2.5/PM_UCB0SOMI/ PM_UCB0SCL/LCDREF/ R13 Default mapping: eUSCI_B0 SPI slave out, master in 48 I/O Default mapping: eUSCI_B0 I2C clock External reference voltage input for regulated LCD voltage Input/output port of third most positive analog LCD voltage (V3 or V4) General-purpose digital I/O with port interrupt and mappable secondary function P2.6/PM_UCB0SIMO/ PM_UCB0SDA/R03 49 I/O Default mapping: eUSCI_B0 SPI slave in, master out Default mapping: eUSCI_B0 I2C data Input/output port of lowest analog LCD voltage (V5) General-purpose digital I/O with port interrupt and mappable secondary function P2.7/PM_UCB0CLK/CB2 50 I/O Default mapping: eUSCI_B0 clock input/output Comparator_B input CB2 General-purpose digital I/O with mappable secondary function P3.0/PM_UCA0RXD/ PM_UCA0SOMI 51 I/O Default mapping: eUSCI_A0 UART receive data Default mapping: eUSCI_A0 SPI slave out, master in General-purpose digital I/O with mappable secondary function P3.1/PM_UCA0TXD/ PM_UCA0SIMO/S39 52 I/O Default mapping: eUSCI_A0 UART transmit data Default mapping: eUSCI_A0 SPI slave in, master out LCD segment output S39 General-purpose digital I/O with mappable secondary function P3.2/PM_UCA0CLK/S38 53 I/O Default mapping: eUSCI_A0 clock input/output LCD segment output S38 General-purpose digital I/O with mappable secondary function P3.3/PM_UCA1CLK/S37 54 I/O Default mapping: eUSCI_A1 clock input/output LCD segment output S37 General-purpose digital I/O with mappable secondary function P3.4/PM_UCA1RXD/ PM_UCA1SOMI/S36 55 I/O Default mapping: eUSCI_A1 UART receive data Default mapping: eUSCI_A1 SPI slave out, master in LCD segment output S36 General-purpose digital I/O with mappable secondary function P3.5/PM_UCA1TXD/ PM_UCA1SIMO/S35 56 I/O Default mapping: eUSCI_A1 UART transmit data Default mapping: eUSCI_A1 SPI slave in, master out LCD segment output S35 General-purpose digital I/O with mappable secondary function P3.6/PM_UCA2RXD/ PM_UCA2SOMI/S34 57 I/O Default mapping: eUSCI_A2 UART receive data Default mapping: eUSCI_A2 SPI slave out, master in LCD segment output S34 General-purpose digital I/O with mappable secondary function P3.7/PM_UCA2TXD/ PM_UCA2SIMO/S33 58 I/O Default mapping: eUSCI_A2 UART transmit data Default mapping: eUSCI_A2 SPI slave in, master out LCD segment output S33 General-purpose digital I/O with mappable secondary function P4.0/PM_UCA2CLK/S32 59 I/O Default mapping: eUSCI_A2 clock input/output LCD segment output S32 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 21 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 4-4. Terminal Functions – PZ Package (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION PZ General-purpose digital I/O with mappable secondary function P4.1/PM_UCA3RXD/ PM_UCA3SOMI/S31 60 I/O Default mapping: eUSCI_A3 UART receive data Default mapping: eUSCI_A3 SPI slave out, master in LCD segment output S31 General-purpose digital I/O with mappable secondary function P4.2/PM_UCA3TXD/ PM_UCA3SIMO/S30 61 I/O Default mapping: eUSCI_A3 UART transmit data Default mapping: eUSCI_A3 SPI slave in, master out LCD segment output S30 General-purpose digital I/O with mappable secondary function P4.3/PM_UCA3CLK/S29 62 I/O Default mapping: eUSCI_A3 clock input/output LCD segment output S29 General-purpose digital I/O with mappable secondary function P4.4/PM_UCB1SOMI/ PM_UCB1SCL/S28 63 I/O Default mapping: eUSCI_B1 SPI slave out, master in Default mapping: eUSCI_B1 I2C clock LCD segment output S28 General-purpose digital I/O with mappable secondary function P4.5/PM_UCB1SIMO/ PM_UCB1SDA/S27 64 I/O Default mapping: eUSCI_B1 SPI slave in, master out Default mapping: eUSCI_B1 I2C data LCD segment output S27 General-purpose digital I/O with mappable secondary function P4.6/PM_UCB1CLK/S26 65 I/O Default mapping: eUSCI_B1 clock input/output LCD segment output S26 General-purpose digital I/O with mappable secondary function P4.7/PM_TA3.0/S25 66 I/O Default Mapping: Timer TA3 CCR0 capture: CCI0A input, compare: Out0 output LCD segment output S25 General-purpose digital I/O P5.0/SDCLK/S24 67 I/O SD24_B bit-stream clock input/output LCD segment output S24 General-purpose digital I/O P5.1/PM_SD0DIO/S23 68 I/O Default mapping: SD24_B converter 0 bit-stream data input/output LCD segment output S23 General-purpose digital I/O P5.2/PM_SD1DIO/S22 69 I/O Default mapping: SD24_B converter 1 bit-stream data input/output LCD segment output S22 General-purpose digital I/O P5.3/PM_SD2DIO/S21 70 I/O Default mapping: SD24_B converter 2 bit-stream data input/output LCD segment output S21 General-purpose digital I/O P5.4/PM_SD3DIO/S20 71 I/O Default mapping: SD24_B converter 3 bit-stream data input/output LCD segment output S20 General-purpose digital I/O P5.5/PM_SD4DIO/S19 72 I/O Default mapping: SD24_B converter 4 bit-stream data input/output (not available on F674xA devices) LCD segment output S19 22 Terminal Configuration and Functions Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 4-4. Terminal Functions – PZ Package (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION PZ General-purpose digital I/O P5.6/PM_SD5DIO/S18 73 I/O Default mapping: SD24_B converter 5 bit-stream data input/output (not available on F674xA devices) LCD segment output S18 General-purpose digital I/O I/O Default mapping: SD24_B converter 6 bit-stream data input/output (not available on F676xA or F674xA devices) P5.7/PM_SD6DIO/S17 74 VDSYS2 (3) 75 Digital power supply for I/Os DVSS2 76 Digital ground supply P6.0/S16 77 I/O P6.1/S15 78 I/O P6.2/S14 79 I/O P6.3/S13 80 I/O P6.4/S12 81 I/O P6.5/S11 82 I/O P6.6/S10 83 I/O P6.7/S9 84 I/O P7.0/S8 85 I/O P7.1/S7 86 I/O P7.2/S6 87 I/O P7.3/S5 88 I/O P7.4/S4 89 I/O P7.5/S3 90 I/O P7.6/S2 91 I/O P7.7/S1 92 I/O P8.0/S0 93 I/O LCD segment output S17 General-purpose digital I/O LCD segment output S16 General-purpose digital I/O LCD segment output S15 General-purpose digital I/O LCD segment output S14 General-purpose digital I/O LCD segment output S13 General-purpose digital I/O LCD segment output S12 General-purpose digital I/O LCD segment output S11 General-purpose digital I/O LCD segment output S10 General-purpose digital I/O LCD segment output S9 General-purpose digital I/O LCD segment output S8 General-purpose digital I/O LCD segment output S7 General-purpose digital I/O LCD segment output S6 General-purpose digital I/O LCD segment output S5 General-purpose digital I/O LCD segment output S4 General-purpose digital I/O LCD segment output S3 General-purpose digital I/O LCD segment output S2 General-purpose digital I/O LCD segment output S1 General-purpose digital I/O LCD segment output S0 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 23 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 4-4. Terminal Functions – PZ Package (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION PZ General-purpose digital I/O P8.1/TACLK/RTCCLK/CB3 94 I/O Timer clock input TACLK for TA0, TA1, TA2, TA3 RTCCLK clock output Comparator_B input CB3 TEST/SBWTCK 95 I PJ.0/TDO 96 I/O PJ.1/TDI/TCLK 97 I/O PJ.2/TMS 98 I/O PJ.3/TCK 99 I/O Test mode pin – select digital I/O on JTAG pins Spy-By-Wire input clock General-purpose digital I/O Test data output General-purpose digital I/O Test data input or Test clock input General-purpose digital I/O Test mode select General-purpose digital I/O Test clock Reset input active low (5) RST/NMI/SBWTDIO 100 I/O Nonmaskable interrupt input Spy-By-Wire data input/output (5) 24 When this pin is configured as reset, the internal pullup resistor is enabled by default. Terminal Configuration and Functions Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com 4.3 SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Pin Multiplexing Pin multiplexing for these devices is controlled by both register settings and operating modes (for example, if the device is in test mode). For details of the settings for each pin and schematics of the multiplexed ports, see Section 6.12. 4.4 Connection of Unused Pins Table 4-5 lists the correct termination of unused pins. Table 4-5. Connection of Unused Pins (1) PIN POTENTIAL AVCC DVCC AVSS DVSS Px.y Open Switched to port function, output direction (PxDIR.n = 1). Px.y represents port x and bit y of port x (for example, P1.0, P1.1, P2.2, PJ.0, PJ.1) XIN DVSS For dedicated XIN pins only. XIN pins with shared GPIO functions should be programmed to GPIO and follow Px.y recommendations. XOUT Open For dedicated XOUT pins only. XOUT pins with shared GPIO functions should be programmed to GPIO and follow Px.y recommendations. LCDCAP DVSS RST/NMI DVCC or VCC 47-kΩ pullup or internal pullup selected with 10-nF (2.2 nF) pulldown (2) PJ.0/TDO PJ.1/TDI PJ.2/TMS PJ.3/TCK Open The JTAG pins are shared with general-purpose I/O function (PJ.x). If not being used, these should be switched to port function, output direction (PJDIR.n = 1). When used as JTAG pins, these pins should remain open. TEST Open This pin always has an internal pulldown enabled. (1) (2) COMMENT Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.y unused pin connection guidelines. The pulldown capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG mode with TI tools such as FET interfaces or GANG programmers. Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 25 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com 5 Specifications All graphs in this section are for typical conditions, unless otherwise noted. Typical (TYP) values are specified at VCC = 3.3 V and TA = 25°C, unless otherwise noted. 5.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Voltage applied at DVCC to DVSS Voltage applied to pins (2) (3) All pins except VCORE , SD24_B input pins (SDxN0, SDxP0) AUXVCC1, AUXVCC2, and AUXVCC3 (5) MIN MAX –0.3 4.1 V –0.3 VCC + 0.3 V (4) , All pins except SD24_B input pins (SDxN0, SDxP0) Diode current at pins ±2 SD0N0, SD0P0, SD1N0, SD1P0, SD2N0, SD2P0, SD3N0, SD3P0, SD4N0, SD4P0, SD5N0, SD5P0, SD6N0, SD6P0 (6) Storage temperature, Tstg (7) (2) (3) (4) (5) (6) (7) mA 2 Maximum junction temperature, TJ (1) UNIT –55 95 °C 105 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages referenced to VSS = VDVSS = VAVSS. VCORE is for internal device use only. No external DC loading or voltage should be applied. See Table 5-39 for SD24_B specifications. See Table 5-18 for AUX specifications. A protection diode is connected to VCC for the SD24_B input pins. No protection diode is connected to VSS. Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. 5.2 ESD Ratings VALUE V(ESD) (1) (2) 5.3 Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±1000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±250 Recommended Operating Conditions MAX 1.8 3.6 PMMCOREVx = 0, 1 2.0 3.6 PMMCOREVx = 0, 1,3 2 2.2 3.6 PMMCOREVx = 0, 1, 2, 3 2.4 Supply voltage during program execution and flash programming (VAVCC = VDVCC = VCC) (1) (2) VSS Supply voltage VAVSS = VDVSS = VSS TA Operating free-air temperature I version –40 TJ Operating junction temperature I version –40 CVCORE Recommended capacitor at VCORE CDVCC/ CVCORE Capacitor ratio of DVCC to VCORE 26 NOM PMMCOREVx = 0 VCC (2) V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±1000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V may actually have higher performance. MIN (1) UNIT UNIT V 3.6 0 V 85 85 470 °C °C nF 10 TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between V(AVCC) and V(DVCC) can be tolerated during power up and operation. The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the Table 5-14 threshold parameters for the exact values and further details. Specifications Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Recommended Operating Conditions (continued) MIN fSYSTEM Processor frequency (maximum MCLK frequency) (3) (see Figure 5-1) (4) NOM MAX PMMCOREVx = 0, 1.8 V ≤ VCC ≤ 3.6 V (default condition) 0 8.0 PMMCOREVx = 1, 2 V ≤ VCC ≤ 3.6 V 0 12.0 PMMCOREVx = 2, 2.2 V ≤ VCC ≤ 3.6 V 0 20.0 PMMCOREVx = 3, 2.4 V ≤ VCC ≤ 3.6 V 0 25.0 UNIT MHz ILOAD, DVCCD Maximum load current that can be drawn from DVCC for core and IO (ILOAD = ICORE + IIO) 20 mA ILOAD, AUX1D Maximum load current that can be drawn from AUXVCC1 for core and IO (ILOAD = ICORE + IIO) 20 mA ILOAD, AUX2D Maximum load current that can be drawn from AUXVCC2 for core and IO (ILOAD = ICORE + IIO) 20 mA ILOAD, AVCCA Maximum load current that can be drawn from AVCC for analog modules (ILOAD = IModules) 10 mA ILOAD, AUX1A Maximum load current that can be drawn from AUXVCC1 for analog modules (ILOAD = IModules) 5 mA ILOAD, AUX2A Maximum load current that can be drawn from AUXVCC2 for analog modules (ILOAD = IModules) 5 mA PINT Internal power dissipation VCC x I(DVCC) W W W PIO I/O power dissipation of the I/O pins powered by DVCC (VCC – VIOH) x IIOH + VIOL x IIOL PMAX Maximum allowed power dissipation, PMAX > PIO + PINT (TJ – TA) / θJA (3) (4) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the specified maximum frequency. Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet. 25 System Frequency - MHz 3 20 2 2, 3 1 1, 2 1, 2, 3 0, 1 0, 1, 2 0, 1, 2, 3 12 8 0 0 1.8 2.0 2.2 2.4 3.6 Supply Voltage - V The numbers within the fields denote the supported PMMCOREVx settings. Figure 5-1. Maximum System Frequency Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 27 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 5.4 www.ti.com Active Mode Supply Current Into VCC Excluding External Current over recommended operating free-air temperature (unless otherwise noted) (1) (2) (3) FREQUENCY (fDCO = fMCLK = fSMCLK) PARAMETER IAM, IAM, (1) (2) (3) (4) (5) 28 Flash RAM (4) (5) EXECUTION MEMORY Flash RAM VCC 3V 3V PMMCOREV x 1 MHz 8 MHz TYP MAX TYP MAX 0 0.32 0.50 2.08 2.84 1 0.35 2 12 MHz 20 MHz TYP MAX 2.35 3.50 4.76 0.39 2.68 3 0.41 2.83 0 0.19 1.04 1 0.21 1.20 1.77 2 0.23 1.38 2.04 3.35 3 0.24 1.47 2.18 3.58 25 MHz TYP MAX 3.99 6.61 8.3 4.22 6.98 TYP UNIT MAX mA 8.67 11.75 mA 4.44 All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The currents are characterized with a Micro Crystal MS1 V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are chosen to closely match the required 12.5 pF. Characterized with program executing typical data processing. fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency. XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0. Active mode supply current when program executes in flash at a nominal supply voltage of 3.0 V. Active mode supply current when program executes in RAM at a nominal supply voltage of 3.0 V. Specifications Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com 5.5 SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Low-Power Mode Supply Currents (Into VCC) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) TEMPERATURE (TA) PARAMETER VCC PMMCOREVx –40°C TYP ILPM0,1MHz Low-power mode 0 (3) (4) ILPM2 Low-power mode 2 (5) (4) ILPM3,XT1LF ILPM3,XT1LF ILPM3,VLO ILPM4 Low-power mode 3, crystal mode (6) (4) Low-power mode 3, crystal mode (6) (4) Low-power mode 3, VLO mode (7) (4) Low-power mode 4 (8) ILPM3.5 Low-power mode 3.5, RTC active on AUXVCC3 (9) ILPM4.5 Low-power mode 4.5 (10) TYP 85°C MAX TYP 105 100 2.2 V 0 70 75 3V 3 81 87 2.2 V 0 5.9 6.5 3V 3 6.7 7.3 0 1.50 2.0 7.8 1 1.65 2.2 8.3 2 1.80 2.4 8.6 3 1.84 2.4 8.6 0 2.0 2.5 8.5 1 2.1 2.7 9.0 2 2.3 2.9 9.3 3 2.3 2.9 9.3 0 1.3 1.7 7.5 1 1.3 1.8 7.9 2 1.4 1.9 8.2 3 1.4 1.9 8.2 0 1.2 1.6 7.4 1 1.2 1.7 7.8 2 1.3 1.7 7.9 3 2.2 V 3V 3V (4) 25°C MAX 3V UNIT MAX 86 130 12.5 18 13.8 30 µA µA µA µA 25 µA 25.0 µA 1.3 1.7 8.0 2.2 V 0.7 0.9 1.4 23.0 3V 1.0 1.2 1.5 1.8 3.0 3V 0.6 0.7 1.0 1.2 2.0 µA µA (1) (2) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The currents are characterized with a Micro Crystal MS1 V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are chosen to closely match the required 12.5 pF. (3) Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz (4) Current for brownout, high-side supervisor (SVSH) normal mode included. Low-side supervisor (SVSL) and low-side monitor (SVML) disabled. High-side monitor (SVMH) disabled. RAM retention enabled. (5) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz, DCO setting = 1-MHz operation, DCO bias generator enabled. (6) Current for watchdog timer and RTC clocked by low-frequency clock included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz (7) Current for watchdog timer and RTC clocked by low-frequency clock included. ACLK = VLO. CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz (8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz (9) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC active on AUXVCC3 supply (10) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 0 Hz, PMMREGOFF = 1 Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 29 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 5.6 www.ti.com Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) TEMPERATURE (TA) PARAMETER VCC PMMCOREVx –40°C TYP ILPM3 LCD, ext. bias ILPM3 LCD, int. bias Low-power mode 3 (LPM3) current, LCD 4-mux mode, external biasing (3) (4) Low-power mode 3 (LPM3) current, LCD 4-mux mode, internal biasing, charge pump disabled (3) (5) 3V 3V 2.2 V ILPM3 LCD,CP (1) (2) (3) (4) (5) (6) 30 Low-power mode 3 (LPM3) current, LCD 4-mux mode, internal biasing, charge pump enabled (3) (6) 3V 25°C MAX TYP 85°C MAX TYP 0 2.5 3.1 9.1 1 2.6 3.3 9.5 2 2.8 3.5 9.9 3 2.8 3.5 0 2.9 3.5 9.7 1 3.1 3.7 10.1 2 3.2 4.0 10.5 3 3.3 4.0 0 2.2 2.8 8.8 1 2.3 3.0 9.1 2 2.5 3.2 9.5 0 2.6 3.2 9.3 1 2.8 3.4 9.7 2 2.9 3.6 10.1 3 3.0 3.7 10.2 6.0 5.5 10.0 10.5 UNIT MAX µA 25.0 µA 25.0 µA µA All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The currents are characterized with a Micro Crystal MS1 V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are chosen to closely match the required 12.5 pF. Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz Current for brownout and high-side supervisor (SVSH) in normal mode included. Low-side supervisor (SVSL) and low-side monitor (SVML) disabled. High-side monitor (SVMH) disabled. RAM retention enabled. LCDMx = 11 (4-mux mode), LCDREXT = 1, LCDEXTBIAS = 1 (external biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz) Current through external resistors not included (voltage levels are supplied by test equipment). Even segments (S0, S2, ...) = 0, and odd segments (S1, S3, ...) = 1. No LCD panel load. LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz) Even segments (S0, S2, ...) = 0, and odd segments (S1, S3, ...) = 1. No LCD panel load. LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge pump enabled), VLCDx = 1000 (VLCD = 3 V typical), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz) Even segments (S0, S2, ...) = 0, and odd segments (S1, S3, ...) = 1. No LCD panel load. Specifications Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com 5.7 SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Thermal Resistance Characteristics THERMAL METRIC (1) (2) RθJA Junction-to-ambient thermal resistance, still air RθJC(TOP) Junction-to-case (top) thermal resistance RθJC(BOTTOM) Junction-to-case (bottom) thermal resistance RθJB Junction-to-board thermal resistance ΨJT Junction-to-package-top thermal characterization parameter ΨJB Junction-to-board thermal characterization parameter (1) (2) (3) VALUE LQFP 128 (PEU) 44.4 LQFP 100 (PZ) 42.9 LQFP 128 (PEU) 10.5 LQFP 100 (PZ) 9.3 LQFP 128 (PEU) N/A (3) LQFP 100 (PZ) N/A LQFP 128 (PEU) 23.1 LQFP 100 (PZ) 20.6 LQFP 128 (PEU) 0.4 LQFP 100 (PZ) 0.3 LQFP 128 (PEU) 22.8 LQFP 100 (PZ) 20.3 UNIT °C/W °C/W °C/W °C/W °C/W °C/W For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics. These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RθJC] value, which is based on a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards: • JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air) • JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages • JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages • JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements N/A = not applicable Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 31 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 5.8 www.ti.com Timing and Switching Characteristics 5.8.1 Reset Timing Table 5-1 lists the device wake-up times. Table 5-1. Wake-up Times From Low-Power Modes and Reset over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS tWAKE-UP-FAST Wake-up time from LPM2, LPM3, or LPM4 to active mode (1) PMMCOREV = SVSMLRRL = n (where n = 0, 1, 2, or 3), SVSLFP = 1 tWAKE-UP-SLOW Wake-up time from LPM2, LPM3, or LPM4 to active mode (2) (3) PMMCOREV = SVSMLRRL = n (where n = 0, 1, 2, or 3), SVSLFP = 0 tWAKE-UP-LPM4.5 tWAKE-UP-RESET (1) (2) (3) (4) 32 MIN TYP MAX fMCLK ≥ 4.0 MHz 5 fMCLK < 4.0 MHz 10 UNIT µs 150 165 µs Wake-up time from LPM4.5 to active mode (4) 2 3 ms Wake-up time from RST or BOR event to active mode (4) 2 3 ms This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-FAST is possible with SVSL and SVML in full performance mode or disabled. For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode Selection section in the Power Management Module and Supply Voltage Supervisor chapter of the MSP430x5xx and MSP430x6xx Family User's Guide. This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-SLOW is set with SVSL and SVML in normal mode (low current mode). For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode Selection section in the Power Management Module and Supply Voltage Supervisor chapter of the MSP430x5xx and MSP430x6xx Family User's Guide. The wake-up times from LPM0 and LPM1 to AM are not specified. They are proportional to MCLK cycle time but are not affected by the performance mode settings as for LPM2, LPM3, and LPM4. This value represents the time from the wake-up event to the reset vector execution. Specifications Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com 5.8.2 SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Clock Specifications Table 5-2 lists the characteristics of the crystal oscillator in low-frequency mode. Table 5-2. Crystal Oscillator, XT1, Low-Frequency Mode (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER ΔIDVCC.LF Differential XT1 oscillator crystal current consumption from lowest drive setting, LF mode TEST CONDITIONS VCC MIN fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1, TA = 25°C fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 2, TA = 25°C 3V 0.170 0.290 XTS = 0, XT1BYPASS = 0 32768 XT1 oscillator crystal frequency, LF mode fXT1,LF,SW XT1 oscillator logic-level square-wave input frequency, XTS = 0, XT1BYPASS = 1 (2) LF mode OALF Oscillation allowance for LF crystals (4) (3) 10 fFault,LF tSTART,LF 210 XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1, fXT1,LF = 32768 Hz, CL,eff = 12 pF 300 (1) (2) (3) (4) (5) (6) (7) (8) XTS = 0, XCAPx = 2 8.5 XTS = 0, XCAPx = 3 12.0 Oscillator fault frequency, LF mode (7) XTS = 0 (8) fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0, TA = 25°C, CL,eff = 6 pF fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 3, TA = 25°C, CL,eff = 12 pF µA Hz 50 kHz 1 5.5 Duty cycle, LF mode UNIT kΩ XTS = 0, XCAPx = 1 XTS = 0, Measured at ACLK, fXT1,LF = 32768 Hz Start-up time, LF mode 32.768 XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0, fXT1,LF = 32768 Hz, CL,eff = 6 pF XTS = 0, XCAPx = 0 (6) CL,eff MAX 0.075 fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 3, TA = 25°C fXT1,LF0 Integrated effective load capacitance, LF mode (5) TYP pF 30% 70% 10 10000 Hz 1000 3V ms 500 To improve EMI on the XT1 oscillator, the following guidelines should be observed. • Keep the trace between the device and the crystal as short as possible. • Design a good ground plane around the oscillator pins. • Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. • Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. • Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins. • If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins. When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in the Schmitt-trigger Inputs section of this data sheet. Maximum frequency of operation of the entire device cannot be exceeded. Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following guidelines, but should be evaluated based on the actual crystal selected for the application: • For XT1DRIVEx = 0, CL,eff ≤ 6 pF. • For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF. • For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF. • For XT1DRIVEx = 3, CL,eff ≥ 6 pF. Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal. Requires external capacitors at both terminals. Values are specified by crystal manufacturers. Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag. Measured with logic-level input frequency but also applies to operation with crystals. Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 33 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 5-3 lists the characteristics of the VLO. Table 5-3. Internal Very-Low-Power Low-Frequency Oscillator (VLO) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX 6 9.6 15 fVLO VLO frequency Measured at ACLK 1.8 V to 3.6 V dfVLO/dT VLO frequency temperature drift Measured at ACLK 1.8 V to 3.6 V 0.5 Measured at ACLK 1.8 V to 3.6 V 4 Measured at ACLK 1.8 V to 3.6 V dfVLO/dVCC VLO frequency supply voltage drift Duty cycle 40% UNIT kHz %/°C %/V 50% 60% TYP MAX Table 5-4 lists the characteristics of the REFO. Table 5-4. Internal Reference, Low-Frequency Oscillator (REFO) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER IREFO fREFO TEST CONDITIONS VCC MIN REFO oscillator current consumption TA = 25°C 1.8 V to 3.6 V REFO frequency calibrated Measured at ACLK 1.8 V to 3.6 V Full temperature range 1.8 V to 3.6 V –3.5% +3.5% 3V –1.5% +1.5% REFO absolute tolerance calibrated TA = 25°C 3 REFO frequency temperature drift Measured at ACLK 1.8 V to 3.6 V 0.01 dfREFO/dVCC REFO frequency supply voltage drift Measured at ACLK 1.8 V to 3.6 V 1.0 Duty cycle Measured at ACLK 1.8 V to 3.6 V REFO start-up time 40%/60% duty cycle 1.8 V to 3.6 V tSTART 34 Specifications µA 32768 dfREFO/dT 40% 50% 25 UNIT Hz %/°C %/V 60% µs Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 5-5 lists the frequency characteristics of the DCO. Table 5-5. DCO Frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-2) PARAMETER fDCO(0,0) TEST CONDITIONS DCO frequency (0, 0) (1) (1) MAX UNIT DCORSELx = 0, DCOx = 0, MODx = 0 0.07 MIN TYP 0.20 MHz fDCO(0,31) DCO frequency (0, 31) DCORSELx = 0, DCOx = 31, MODx = 0 0.70 1.70 MHz fDCO(1,0) DCO frequency (1, 0) (1) DCORSELx = 1, DCOx = 0, MODx = 0 0.15 0.36 MHz fDCO(1,31) DCO frequency (1, 31) (1) DCORSELx = 1, DCOx = 31, MODx = 0 1.47 3.45 MHz fDCO(2,0) DCO frequency (2, 0) (1) DCORSELx = 2, DCOx = 0, MODx = 0 0.32 0.75 MHz (1) fDCO(2,31) DCO frequency (2, 31) DCORSELx = 2, DCOx = 31, MODx = 0 3.17 7.38 MHz fDCO(3,0) DCO frequency (3, 0) (1) DCORSELx = 3, DCOx = 0, MODx = 0 0.64 1.51 MHz fDCO(3,31) DCO frequency (3, 31) (1) DCORSELx = 3, DCOx = 31, MODx = 0 6.07 14.0 MHz (1) fDCO(4,0) DCO frequency (4, 0) DCORSELx = 4, DCOx = 0, MODx = 0 1.3 3.2 MHz fDCO(4,31) DCO frequency (4, 31) (1) DCORSELx = 4, DCOx = 31, MODx = 0 12.3 28.2 MHz fDCO(5,0) DCO frequency (5, 0) (1) DCORSELx = 5, DCOx = 0, MODx = 0 2.5 6.0 MHz (1) fDCO(5,31) DCO frequency (5, 31) DCORSELx = 5, DCOx = 31, MODx = 0 23.7 54.1 MHz fDCO(6,0) DCO frequency (6, 0) (1) DCORSELx = 6, DCOx = 0, MODx = 0 4.6 10.7 MHz fDCO(6,31) DCO frequency (6, 31) (1) DCORSELx = 6, DCOx = 31, MODx = 0 39.0 88.0 MHz fDCO(7,0) DCO frequency (7, 0) (1) DCORSELx = 7, DCOx = 0, MODx = 0 8.5 19.6 MHz (1) fDCO(7,31) DCO frequency (7, 31) DCORSELx = 7, DCOx = 31, MODx = 0 60 135 MHz SDCORSEL Frequency step between range DCORSEL and DCORSEL + 1 SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO) 1.2 2.3 ratio SDCO Frequency step between tap DCO and DCO + 1 SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO) 1.02 1.12 ratio 40% Duty cycle Measured at SMCLK dfDCO/dT DCO frequency temperature drift fDCO = 1 MHz 0.1 %/°C dfDCO/dVCORE DCO frequency voltage drift fDCO = 1 MHz 1.9 %/V (1) 50% 60% When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within the range of fDCO(n, 0),MAX ≤ fDCO ≤ fDCO(n, 31),MIN, where fDCO(n, 0),MAX represents the maximum frequency specified for the DCO frequency, range n, tap 0 (DCOx = 0) and fDCO(n,31),MIN represents the minimum frequency specified for the DCO frequency, range n, tap 31 (DCOx = 31). This ensures that the target DCO frequency resides within the range selected. It should also be noted that if the actual fDCO frequency for the selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the selected range is at its minimum or maximum tap setting. 100 VCC = 3.0 V TA = 25°C fDCO – MHz 10 DCOx = 31 1 0.1 DCOx = 0 0 1 2 3 4 5 6 7 DCORSEL Figure 5-2. Typical DCO Frequency Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 35 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 5.9 www.ti.com Digital I/Os Table 5-6 lists the input characteristics of the Schmitt-trigger GPIOs. Table 5-6. Schmitt-Trigger Inputs – General-Purpose I/O over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VIT+ Positive-going input threshold voltage VIT– Negative-going input threshold voltage Vhys Input voltage hysteresis (VIT+ – VIT–) RPull Pullup or pulldown resistor For pullup: VIN = VSS, For pulldown: VIN = VCC CI Input capacitance VIN = VSS or VCC VCC MIN 1.8 V 0.80 1.40 3V 1.50 2.10 1.8 V 0.45 1.00 3V 0.75 1.65 1.8 V 0.3 0.85 3V 0.4 1.0 20 TYP 35 MAX UNIT V V V 50 kΩ 5 pF Table 5-7 lists the input characteristics of the GPIOs. Table 5-7. Inputs – Ports P1 and P2 (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER t(int) (1) (2) External interrupt timing (2) TEST CONDITIONS VCC Port P1, P2: P1.x to P2.x, External trigger pulse duration to set interrupt flag 2.2 V, 3 V MIN MAX UNIT 20 ns Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions. An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals shorter than t(int). Table 5-8 lists the leakage characteristics of the GPIOs. Table 5-8. Leakage Current – General-Purpose I/O over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER Ilkg(Px.y) (1) (2) 36 High-impedance leakage current TEST CONDITIONS (1) (2) VCC MIN MAX UNIT 1.8 V, 3 V –50 +50 nA The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is disabled. Specifications Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 5-9 lists the output characteristics of the GPIOs in full drive strength mode. Table 5-9. Outputs – General-Purpose I/O (Full Drive Strength) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Section 5.9.2) PARAMETER TEST CONDITIONS I(OHmax) = –3 mA (1) VOH 1.8 V I(OHmax) = –10 mA (1) High-level output voltage I(OHmax) = –5 mA (1) 3V I(OHmax) = –15 mA (1) I(OLmax) = 3 mA (2) VOL I(OLmax) = 10 mA Low-level output voltage 1.8 V (3) I(OLmax) = 5 mA (2) 3V I(OLmax) = 15 mA (3) (1) (2) (3) VCC MIN MAX 1.55 1.80 1.20 1.80 2.75 3.00 2.40 3.00 0.00 0.25 0.00 0.60 0.00 0.25 0.00 0.60 UNIT V V The maximum total current, I(OHmax), for all outputs combined should not exceed ±20 mA to hold the maximum voltage drop specified. See Section 5.3 for more details. The maximum total current, I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop specified. The maximum total current, I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage drop specified. Table 5-10 lists the output characteristics of the GPIOs in reduced drive strength mode. Table 5-10. Outputs – General-Purpose I/O (Reduced Drive Strength) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (see Section 5.9.1) PARAMETER TEST CONDITIONS I(OHmax) = –1 mA VOH I(OHmax) = –3 mA (2) High-level output voltage I(OHmax) = –2 mA (2) I(OHmax) = –6 mA (2) I(OLmax) = 1 mA (3) VOL I(OLmax) = 3 mA (4) Low-level output voltage I(OLmax) = 2 mA (3) (4) 1.8 V 3V 1.8 V (3) I(OLmax) = 6 mA (4) (1) (2) VCC (2) 3V MIN MAX 1.55 1.80 1.20 1.80 2.75 3.00 2.40 3.00 0.00 0.25 0.00 0.60 0.00 0.25 0.00 0.60 UNIT V V Selecting reduced drive strength may reduce EMI. The maximum total current, I(OHmax), for all outputs combined should not exceed ±20 mA to hold the maximum voltage drop specified. See Section 5.3 for more details. The maximum total current, I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop specified. The maximum total current, I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage drop specified. Table 5-11 lists the output frequency of the GPIOs. Table 5-11. Output Frequency – General-Purpose I/O over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fPx.y Port output frequency (with load) fPort_CLK (1) (2) Clock output frequency TEST CONDITIONS See (1) (2) ACLK SMCLK MCLK CL = 20 pF (2) MIN MAX VCC = 1.8 V, PMMCOREVx = 0 16 VCC = 3 V, PMMCOREVx = 3 25 VCC = 1.8 V, PMMCOREVx = 0 16 VCC = 3 V, PMMCOREVx = 3 25 UNIT MHz MHz A resistive divider with 2 × R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For full drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency. Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 37 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 5.9.1 www.ti.com Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) 8 20 18 7 IOL – Low-Level Output Current – mA IOL – Low-Level Output Current – mA TA = 25°C 16 TA = 85°C 14 12 10 8 6 4 TA = 25°C 6 TA = 85°C 5 4 3 2 1 2 0 0 0 0.5 1 1.5 2 2.5 0 3 0.2 0.4 VOL – Low-Level Output Voltage – V VCC = 3 V 0.6 0.8 1 1.2 1.4 1.6 1.8 VOL – Low-Level Output Voltage – V Reduced drive strength VCC = 1.8 V Figure 5-3. Typical Low-Level Output Current vs Low-Level Output Voltage Reduced drive strength Figure 5-4. Typical Low-Level Output Current vs Low-Level Output Voltage 0 0 -5 IOH – High-Level Output Current – mA IOH – High-Level Output Current – mA -1 -10 -15 TA = 85°C -20 TA = 25°C -2 -3 -4 -5 TA = 85°C -6 -7 TA = 25°C -8 -25 0 0.5 1 1.5 2 2.5 VOH – High-Level Output Voltage – V VCC = 3 V Reduced drive strength Figure 5-5. Typical High-Level Output Current vs High-Level Output Voltage 38 Specifications 3 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOH – High-Level Output Voltage – V VCC = 1.8 V Reduced drive strength Figure 5-6. Typical High-Level Output Current vs High-Level Output Voltage Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com 5.9.2 SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) 60 25 IOL – Low-Level Output Current – mA IOL – Low-Level Output Current – mA 50 TA = 25°C TA = 85°C 40 30 20 10 0 20 TA = 25°C TA = 85°C 15 10 5 0 0 0.5 1 1.5 2 2.5 3 0 0.2 0.4 VOL – Low-Level Output Voltage – V VCC = 3 V Full drive strength VCC = 1.8 V Figure 5-7. Typical Low-Level Output Current vs Low-Level Output Voltage 0.8 1 1.2 1.4 1.6 1.8 Full drive strength Figure 5-8. Typical Low-Level Output Current vs Low-Level Output Voltage 0 0 IOH – High-Level Output Current – mA -10 IOH – High-Level Output Current – mA 0.6 VOL – Low-Level Output Voltage – V -20 -30 -40 TA = 85°C -50 -5 -10 -15 TA = 85°C -20 TA = 25°C TA = 25°C -60 -25 0 0.5 1 1.5 2 2.5 3 0 0.2 0.4 VOH – High-Level Output Voltage – V VCC = 3 V Full drive strength Figure 5-9. Typical High-Level Output Current vs High-Level Output Voltage 0.6 0.8 1 1.2 1.4 1.6 VCC = 1.8 V Full drive strength Figure 5-10. Typical High-Level Output Current vs High-Level Output Voltage Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 1.8 VOH – High-Level Output Voltage – V 39 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com 5.10 Power-Management Module (PMM) Table 5-12 lists the characteristics of the BOR. Table 5-12. PMM, Brownout Reset (BOR) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS V(DVCC_BOR_IT–) BORH on voltage, DVCC falling level | dDVCC/dt | < 3 V/s V(DVCC_BOR_IT+) BORH off voltage, DVCC rising level | dDVCC/dt | < 3 V/s V(DVCC_BOR_hys) BORH hysteresis tRESET Pulse duration required at RST/NMI pin to accept a reset MIN TYP 0.80 1.20 50 MAX UNIT 1.45 V 1.50 V 250 mV 2 µs Table 5-13 lists the core voltage characteristics of the PMM. Table 5-13. PMM, Core Voltage over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCORE3(AM) Core voltage, active mode, PMMCOREV = 3 2.4 V ≤ DVCC ≤ 3.6 V 1.91 V VCORE2(AM) Core voltage, active mode, PMMCOREV = 2 2.2 V ≤ DVCC ≤ 3.6 V 1.81 V VCORE1(AM) Core voltage, active mode, PMMCOREV = 1 2 V ≤ DVCC ≤ 3.6 V 1.61 V VCORE0(AM) Core voltage, active mode, PMMCOREV = 0 1.8 V ≤ DVCC ≤ 3.6 V 1.41 V VCORE3(LPM) Core voltage, low-current mode, PMMCOREV = 3 2.4 V ≤ DVCC ≤ 3.6 V 1.94 V VCORE2(LPM) Core voltage, low-current mode, PMMCOREV = 2 2.2 V ≤ DVCC ≤ 3.6 V 1.92 V VCORE1(LPM) Core voltage, low-current mode, PMMCOREV = 1 2 V ≤ DVCC ≤ 3.6 V 1.73 V VCORE0(LPM) Core voltage, low-current mode, PMMCOREV = 0 1.8 V ≤ DVCC ≤ 3.6 V 1.52 V Table 5-14 lists the characteristics of the high-side SVS. Table 5-14. PMM, SVS High Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN SVSHE = 0, DVCC = 3.6 V I(SVSH) SVS current consumption V(SVSH_IT–) V(SVSH_IT+) SVSH on voltage level SVSH off voltage level tpd(SVSH) SVSH propagation delay t(SVSH) SVSH on or off delay time dVDVCC/dt DVCC rise time 40 Specifications TYP MAX 0 SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0 200 SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1 1.5 nA µA SVSHE = 1, SVSHRVL = 0 1.60 1.65 1.75 SVSHE = 1, SVSHRVL = 1 1.77 1.84 1.95 SVSHE = 1, SVSHRVL = 2 1.93 2.00 2.12 SVSHE = 1, SVSHRVL = 3 2.09 2.16 2.29 SVSHE = 1, SVSMHRRL = 0 1.65 1.75 1.85 SVSHE = 1, SVSMHRRL = 1 1.85 1.95 2.05 SVSHE = 1, SVSMHRRL = 2 2.05 2.15 2.25 SVSHE = 1, SVSMHRRL = 3 2.15 2.25 2.35 SVSHE = 1, SVSMHRRL = 4 2.30 2.40 2.55 SVSHE = 1, SVSMHRRL = 5 2.57 2.70 2.83 SVSHE = 1, SVSMHRRL = 6 2.90 3.05 3.20 SVSHE = 1, SVSMHRRL = 7 2.90 3.05 3.20 SVSHE = 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1 2.5 SVSHE = 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0 20 SVSHE = 0 → 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1 12.5 SVSHE = 0 → 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0 100 0 UNIT V V µs µs 1000 V/s Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 5-15 lists the characteristics of the high-side SVM. Table 5-15. PMM, SVM High Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN SVMHE = 0, DVCC = 3.6 V I(SVMH) SVMH current consumption SVMHE = 1, DVCC = 3.6 V, SVMHFP = 0 SVMH on or off voltage level (1) t(SVMH) (1) SVMH propagation delay SVMH on or off delay time UNIT nA 200 1.5 µA SVMHE = 1, SVSMHRRL = 0 1.63 1.73 1.83 SVMHE = 1, SVSMHRRL = 1 1.83 1.93 2.03 SVMHE = 1, SVSMHRRL = 2 2.03 2.13 2.23 SVMHE = 1, SVSMHRRL = 3 2.13 2.23 2.33 SVMHE = 1, SVSMHRRL = 4 2.28 2.40 2.53 SVMHE = 1, SVSMHRRL = 5 2.55 2.70 2.81 SVMHE = 1, SVSMHRRL = 6 2.88 3.02 3.18 SVMHE = 1, SVSMHRRL = 7 2.88 3.02 3.18 SVMHE = 1, SVMHOVPE = 1 tpd(SVMH) MAX 0 SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1 V(SVMH) TYP V 3.77 SVMHE = 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1 2.5 SVMHE = 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0 20 SVMHE = 0 → 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1 12.5 SVMHE = 0 → 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0 100 µs µs The SVMH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide on recommended settings and use. Table 5-16 lists the characteristics of the low-side SVS. Table 5-16. PMM, SVS Low Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS SVSLE = 0, PMMCOREV = 2 I(SVSL) tpd(SVSL) t(SVSL) SVSL current consumption SVSL propagation delay SVSL on or off delay time MIN TYP MAX 0 SVSLE = 1, PMMCOREV = 2, SVSLFP = 0 200 SVSLE = 1, PMMCOREV = 2, SVSLFP = 1 1.5 SVSLE = 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1 2.5 SVSLE = 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0 20 SVSLE = 0 → 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1 12.5 SVSLE = 0 → 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0 100 nA µA µs µs Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated UNIT 41 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 5-17 lists the characteristics of the low-side SVM. Table 5-17. PMM, SVM Low Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP SVMLE = 0, PMMCOREV = 2 I(SVML) SVML current consumption tpd(SVML) SVML propagation delay t(SVML) SVML on or off delay time MAX 0 SVMLE = 1, PMMCOREV = 2, SVMLFP = 0 200 SVMLE = 1, PMMCOREV = 2, SVMLFP = 1 1.5 SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1 2.5 SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0 20 SVMLE = 0 → 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1 12.5 SVMLE = 0 → 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0 100 UNIT nA µA µs µs 5.11 Auxiliary Supplies Table 5-18 lists the recommended operating conditions of the auxiliary supplies. Table 5-18. Auxiliary Supplies, Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN Supply voltage range for all supplies at pins DVCC, AVCC, AUXVCC1, AUXVCC2, AUXVCC3 VCC Digital system supply voltage range, VDSYS = VCC – RON × ILOAD VDSYS NOM MAX 1.8 3.6 PMMCOREVx = 0 1.8 3.6 PMMCOREVx = 1 2.0 3.6 PMMCOREVx = 2 2.2 3.6 PMMCOREVx = 3 2.4 3.6 See module specifications VASYS Analog system supply voltage range, VASYS = VCC – RON × ILOAD TA Ambient temperature range TA,HTOL Ambient temperature during HTOL (module should be functional during HTOL) CVCC,CAUX Recommended capacitor at pins DVCC, AVCC, AUXVCC1, AUXVCC2 –40 UNIT V V V 85 °C 150 °C 4.7 µF 1/2 CVSYS Recommended capacitor at pins VDSYS1, VDSYS2 and VASYS1, VASYS2 4.7 µF CVCORE Recommended capacitance at pin VCORE 0.47 µF CAUX3 Recommended capacitor at pin AUXVCC3 0.47 µF Table 5-19 lists the current consumption of the backup subsystem. Table 5-19. Auxiliary Supplies, AUXVCC3 (Backup Subsystem) Currents over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IAUX3,RTCon AUXVCC3 current with RTC enabled RTC and 32-kHz oscillator in backup subsystem enabled 3V IAUX3,RTCoff AUXVCC3 current with RTC disabled RTC and 32-kHz oscillator in backup subsystem disabled 3V 42 Specifications TA MIN MAX 25°C 0.86 85°C 1.2 25°C 120 85°C 220 UNIT µA nA Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 5-20 lists the characteristics of the auxiliary supply monitor. Table 5-20. Auxiliary Supplies, Auxiliary Supply Monitor over operating free-air temperature range (unless otherwise noted) PARAMETER MAX UNIT ICC,Monitor Average supply current for monitoring circuitry drawn from VDSYS LOCKAUX = 0, AUXMRx = 0 AUX0MD = 0, AUX1MD = 0, AUX2MD = 1, VDSYS = DVCC, VASYS = AVCC, Current measured at VDSYS TEST CONDITIONS MIN 1.10 µA IMeas,Montior Average current drawn from monitored supply during measurement cycle LOCKAUX = 0, AUXMRx = 0 AUX0MD = 0, AUX1MD = 0, AUX2MD = 1, VDSYS = DVCC, VASYS = AVCC, Current measured at AUXVCC1 0.13 µA VSVMH (SVSMHRRL x= AUXLVLx) General TYP VSVMH (SVSMHRRL x= AUXLVLx) VSVMH (SVSMHRRLx = AUXLVLx) X – 5% Auxiliary supply threshold level (same as high-side SVM) VMonitor X + 5% AUXLVLx = 0 1.65 1.75 1.85 AUXLVLx = 1 1.85 1.95 2.05 AUXLVLx = 2 2.05 2.15 2.25 AUXLVLx = 3 2.15 2.25 2.35 AUXLVLx = 4 2.30 2.40 2.55 AUXLVLx = 5 2.57 2.70 2.83 AUXLVLx = 6 2.90 3.00 3.20 AUXLVLx = 7 2.90 3.00 3.20 V Table 5-21 lists the ON-resistance characteristics of the switches. Table 5-21. Auxiliary Supplies, Switch ON-Resistance over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT RON,DVCC ON-resistance of switch between DVCC and VDSYS ILOAD = ICORE + IIO = 10 mA + 10 mA = 20 mA 5 Ω RON,DAUX1 ON-resistance of switch between AUXVCC1 and VDSYS ILOAD = ICORE + IIO = 10 mA + 10 mA = 20 mA 5 Ω RON,DAUX2 ON-resistance of switch between AUXVCC2 and VDSYS ILOAD = ICORE + IIO = 10 mA + 10 mA = 20 mA 5 Ω RON,AVCC ON-resistance of switch between AVCC and VASYS ILOAD = IModules = 10 mA 5 Ω RON,AAUX1 ON-resistance of switch between AUXVCC1 and VASYS ILOAD = IModules = 5 mA 20 Ω RON,AAUX2 ON-resistance of switch between AUXVCC2 and VASYS ILOAD = IModules = 5 mA 20 Ω Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 43 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 5-22 lists the switching times of the auxiliary supplies. Table 5-22. Auxiliary Supplies, Switching Time over operating free-air temperature range (unless otherwise noted) PARAMETER MIN tSwitch Time from occurrence of trigger (SVM or software) to "new" supply connected to system supplies tRecover "Recovery time" after a switch over takes place. During this time, another switch cannot occur. 170 MAX UNIT 100 ns 480 µs Table 5-23 lists the leakage characteristics of the switch. Table 5-23. Auxiliary Supplies, Switch Leakage over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS ISW,Lkg Current into DVCC, AVCC, AUXVCC1, or AUXVCC2 if not selected IVmax Current drawn from highest supply MIN Per supply (but not the highest supply) TYP MAX UNIT 75 250 nA 500 700 nA Table 5-24 lists the characteristics of the auxiliary supplies to the ADC. Table 5-24. Auxiliary Supplies, Auxiliary Supplies to ADC10_A over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS Supply voltage divider V3 = VSupply / 3 V3 RV3 Load resistance tSample,V3 VCC MIN TYP MAX 1.8 V 0.57 0.6 0.63 3V 0.95 1.0 1.05 3.6 V 1.14 1.2 1.26 AUXADCRx = 0 15 AUXADCRx = 1 1.5 AUXADCRx = 2 0.6 Error of conversion Sampling time required if V3 is selected result ≤ 1 LSB AUXADCRx = 0 1000 AUXADCRx = 1 1000 AUXADCRx = 2 1000 UNIT V kΩ ns Table 5-25 lists the characteristics of the charge limiting resistor. Table 5-25. Auxiliary Supplies, Charge Limiting Resistor over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP AUXCHCx = 1 RCHARGE Charge limiting resistor AUXCHCx = 2 Specifications UNIT 5 3V AUXCHCx = 3 44 MAX 10 kΩ 20 Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 5.12 Timer_A Table 5-26 lists the characteristics of the Timer_A. Table 5-26. Timer_A over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN fTA Timer_A input clock frequency Internal: SMCLK or ACLK, External: TACLK, Duty cycle = 50% ±10% 1.8 V, 3 V tTA,cap Timer_A capture timing All capture inputs, Minimum pulse duration required for capture 1.8 V, 3 V MAX UNIT 25 MHz 20 ns 5.13 eUSCI Table 5-27 lists the supported clock frequencies of the eUSCI in UART mode. Table 5-27. eUSCI (UART Mode) Clock Frequency PARAMETER feUSCI eUSCI input clock frequency fBITCLK BITCLK clock frequency (equals baud rate in MBaud) TEST CONDITIONS MIN Internal: SMCLK or ACLK, External: UCLK, Duty cycle = 50% ±10% MAX UNIT fSYSTEM MHz 5 MHz Table 5-28 lists the switching characteristics of the eUSCI in UART mode. Table 5-28. eUSCI (UART Mode) Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC UCGLITx = 0 tt UART receive deglitch time (1) UCGLITx = 1 UCGLITx = 2 UCGLITx = 3 (1) 2 V, 3 V MIN TYP MAX 10 15 25 30 50 85 50 80 150 70 120 200 UNIT ns Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To make sure that pulses are correctly recognized, their duration should exceed the maximum specification of the deglitch time. Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 45 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 5-29 lists the supported clock frequencies of the eUSCI in SPI master mode. Table 5-29. eUSCI (SPI Master Mode) Clock Frequency PARAMETER feUSCI eUSCI input clock frequency TEST CONDITIONS MIN Internal: SMCLK or ACLK, Duty cycle = 50% ±10% MAX UNIT fSYSTEM MHz Table 5-30 lists the switching characteristics of the eUSCI in SPI master mode. Table 5-30. eUSCI (SPI Master Mode) Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER tSTE,LEAD STE lead time, STE low to clock tSTE,LAG STE lag time, Last clock to STE high TEST CONDITIONS VCC UCSTEM = 0, UCMODEx = 01 or 10 UCSTEM = 1, UCMODEx = 01 or 10 UCSTEM = 0, UCMODEx = 01 or 10 UCSTEM = 1, UCMODEx = 01 or 10 UCSTEM = 0, UCMODEx = 01 or 10 tSTE,ACC STE access time, STE low to SIMO data out UCSTEM = 1, UCMODEx = 01 or 10 UCSTEM = 0, UCMODEx = 01 or 10 STE disable time, STE high to SIMO high impedance tSTE,DIS UCSTEM = 1, UCMODEx = 01 or 10 tSU,MI SOMI input data setup time tHD,MI SOMI input data hold time tVALID,MO SIMO output data valid time (2) UCLK edge to SIMO valid, CL = 20 pF tHD,MO SIMO output data hold time (3) CL = 20 pF (1) (2) (3) 46 2 V, 3 V 2 V, 3 V MIN MAX 150 ns 150 200 ns 200 2V 50 3V 30 2V 50 3V 30 2V 40 3V 25 2V 40 3V UNIT ns ns 25 2V 50 3V 30 2V 0 3V 0 ns ns 2V 9 3V 5 2V 0 3V 0 ns ns fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)) For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave. Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams in Figure 5-11 and Figure 5-12. Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 511 and Figure 5-12. Specifications Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tLOW/HIGH tSU,MI tHD,MI SOMI tVALID,MO SIMO Figure 5-11. SPI Master Mode, CKPH = 0 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tLOW/HIGH tSU,MI tHD,MI SOMI tVALID,MO SIMO Figure 5-12. SPI Master Mode, CKPH = 1 Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 47 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 5-31 lists the characteristics of the eUSCI in SPI slave mode. Table 5-31. eUSCI (SPI Slave Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TEST CONDITIONS tSTE,LEAD STE lead time, STE low to clock tSTE,LAG STE lag time, Last clock to STE high tSTE,ACC STE access time, STE low to SOMI data out tSTE,DIS STE disable time, STE high to SOMI high impedance tSU,SI SIMO input data setup time tHD,SI SIMO input data hold time tVALID,SO SOMI output data valid time (2) UCLK edge to SOMI valid, CL = 20 pF tHD,SO SOMI output data hold time (3) CL = 20 pF (1) (2) (3) 48 VCC MIN 2V 4 3V 3 2V 0 3V 0 TYP MAX ns ns 2V 46 3V 24 2V 38 3V 25 2V 2 3V 1 2V 2 3V 2 55 32 3V 16 ns ns 3V 24 ns ns 2V 2V UNIT ns ns fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)) For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master. Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams in Figure 5-13 and Figure 5-14. Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-13 and Figure 5-14. Specifications Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 UCMODEx = 01 tSTE,LEAD STE tSTE,LAG UCMODEx = 10 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tSU,SIMO tLOW/HIGH tHD,SIMO SIMO tVALID,SOMI tACC tDIS SOMI Figure 5-13. SPI Slave Mode, CKPH = 0 tSTE,LAG tSTE,LEAD STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tLOW/HIGH tHD,SI tSU,SI SIMO tACC tVALID,SO tDIS SOMI Figure 5-14. SPI Slave Mode, CKPH = 1 Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 49 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 5-32 lists the characteristics of the eUSCI in I2C mode. Table 5-32. eUSCI (I2C Mode) Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-15) PARAMETER TEST CONDITIONS feUSCI eUSCI input clock frequency fSCL SCL clock frequency MIN 2 V, 3 V tHD,STA Hold time (repeated) START tSU,STA Setup time for a repeated START tHD,DAT Data hold time fSCL = 100 kHz 2 V, 3 V fSCL > 100 kHz fSCL = 100 kHz 2 V, 3 V fSCL > 100 kHz 2 V, 3 V fSCL = 100 kHz tSU,DAT Data setup time tSU,STO Setup time for STOP 2 V, 3 V fSCL > 100 kHz fSCL = 100 kHz 2 V, 3 V fSCL > 100 kHz Pulse duration of spikes suppressed by input filter tSP VCC TYP Internal: SMCLK or ACLK, External: UCLK, Duty cycle = 50% ±10% fSYSTEM MHz 400 kHz 0 5.1 µs 1.5 5.1 µs 1.4 0.4 µs 5.0 µs 1.3 5.2 µs 1.7 75 220 UCGLITx = 1 35 120 30 60 2 V, 3 V UCGLITx = 2 20 30 UCCLTOx = 2 2 V, 3 V 33 UCCLTOx = 3 tSU,STA tHD,STA ns 35 UCCLTOx = 1 Clock low time-out UNIT UCGLITx = 0 UCGLITx = 3 tTIMEOUT MAX ms 37 tHD,STA tBUF SDA tLOW tHIGH tSP SCL tSU,DAT tSU,STO tHD,DAT Figure 5-15. I2C Mode Timing 50 Specifications Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 5.14 RTC Tamper Detect Pin Table 5-33 lists the input characteristics of the tamper detect pin. Table 5-33. Schmitt-Trigger Inputs, RTC Tamper Detect Pin over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VIT+ Positive-going input threshold voltage VIT– Negative-going input threshold voltage Vhys Input voltage hysteresis (VIT+ – VIT–) RPull Pullup or pulldown resistor For pullup: VIN = VSS For pulldown: VIN = AUXVCC3 CI Input capacitance VIN = VSS or AUXVCC3 AUXVCC3 MIN 1.8 V 0.80 1.40 3V 1.50 2.10 1.8 V 0.45 1.00 3V 0.75 1.65 1.8 V 0.3 0.85 3V 0.4 1.0 20 TYP 35 MAX UNIT V V V 50 kΩ 5 pF Table 5-34 lists the input requirements of the tamper detect pin. Table 5-34. Inputs, RTC Tamper Detect Pin (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER t(int) (1) (2) External interrupt timing (2) TEST CONDITIONS AUXVCC3 MIN Port P1, P2: P1.x to P2.x, External trigger pulse duration to set interrupt flag 2.2 V, 3 V 20 MAX UNIT ns Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions. An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals shorter than t(int). Table 5-35 lists the leakage current of the tamper detect pin. Table 5-35. Leakage Current, RTC Tamper Detect Pin over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER Ilkg(Px.y) (1) (2) TEST CONDITIONS High-impedance leakage current See (1) (2) AUXVCC3 MIN MAX UNIT 1.8 V, 3 V –50 +50 nA The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is disabled. Table 5-36 lists the output characteristics of the tamper detect pin. Table 5-36. Outputs, RTC Tamper Detect Pin over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS I(OHmax) = –100 µA (1) VOH High-level output voltage I(OHmax) = –200 µA (1) I(OHmax) = –100 µA I(OLmax) = 100 µA (2) Low-level output voltage I(OLmax) = 200 µA (2) I(OLmax) = 100 µA (2) I(OLmax) = 200 µA (2) (1) (2) 1.8 V (1) I(OHmax) = –200 µA (1) VOL AUXVCC3 3V 1.8 V 3V MIN MAX 1.50 1.80 1.20 1.80 2.70 3.00 2.40 3.00 0.00 0.25 0.00 0.60 0.00 0.25 0.00 0.60 UNIT V V The maximum total current, I(OHmax), for all outputs combined should not exceed ±20 mA to hold the maximum voltage drop specified. See Section 5.3 for more details. The maximum total current, I(OHmax), for all outputs combined should not exceed ±20 mA to hold the maximum voltage drop specified. See Section 5.3 for more details. Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 51 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com 5.15 LCD_C Table 5-37 lists the operating conditions of the LCD controller. Table 5-37. LCD_C, Operating Conditions PARAMETER TEST CONDITIONS MIN VCC,LCD_C,CP en,3.6 Supply voltage range, charge pump enabled, VLCD ≤ 3.6 V LCDCPEN = 1, 0000 < VLCDx ≤ 1111 (charge pump enabled, VLCD ≤ 3.6 V) NOM MAX 2.2 3.6 V VCC,LCD_C,CP en,3.3 Supply voltage range, charge pump enabled, VLCD ≤ 3.3 V LCDCPEN = 1, 0000 < VLCDx ≤ 1100 (charge pump enabled, VLCD ≤ 3.3 V) 2.0 3.6 V VCC,LCD_C,int. bias Supply voltage range, internal biasing, charge pump disabled LCDCPEN = 0, VLCDEXT = 0 2.4 3.6 V VCC,LCD_C,ext. bias Supply voltage range, external biasing, charge pump disabled LCDCPEN = 0, VLCDEXT = 0 2.4 3.6 V VCC,LCD_C,VLCDEXT Supply voltage range, external LCD voltage, internal or external biasing, charge pump disabled LCDCPEN = 0, VLCDEXT = 1 2.0 3.6 V VLCDCAP/R33 External LCD voltage at LCDCAP/R33, internal or external biasing, charge pump disabled LCDCPEN = 0, VLCDEXT = 1 2.4 3.6 V CLCDCAP Capacitor on LCDCAP when charge pump enabled LCDCPEN = 1, VLCDx > 0000 (charge pump enabled) 4.7 10 µF fLCD LCD frequency range fFRAME = 1/(2 × mux) × fLCD with mux = 1 (static) to 8 1024 Hz fFRAME,4mux LCD frame frequency range fFRAME,4mux(MAX) = 1/(2 × 4) × fLCD(MAX) = 1/(2 × 4) × 1024 Hz 128 Hz fFRAME,8mux LCD frame frequency range fFRAME,8mux(MAX) = 1/(2 × 4) × fLCD(MAX) = 1/(2 × 8) × 1024 Hz 64 Hz fACLK,in ACLK input frequency range CPanel Panel capacitance 100-Hz frame frequency VR33 Analog input voltage at R33 LCDCPEN = 0, VLCDEXT = 1 4.7 0 30 32 2.4 UNIT 40 kHz 10000 pF VCC + 0.2 V VR33 V VR23,1/3bias Analog input voltage at R23 LCDREXT = 1, LCDEXTBIAS = 1, LCD2B = 0 VR13 VR03 + 2/3 × (VR33 – VR03) VR13,1/3bias Analog input voltage at R13 with 1/3 biasing LCDREXT = 1, LCDEXTBIAS = 1, LCD2B = 0 VR03 VR03 + 1/3 × (VR33 – VR03) VR23 V VR13,1/2bias Analog input voltage at R13 with 1/2 biasing LCDREXT = 1, LCDEXTBIAS = 1, LCD2B = 1 VR03 VR03 + 1/2 × (VR33 – VR03) VR33 V VR03 Analog input voltage at R03 R03EXT = 1 VSS VLCD – VR03 Voltage difference between VLCD and R03 LCDCPEN = 0, R03EXT = 1 2.4 VLCDREF/R13 External LCD reference voltage applied at LCDREF/R13 VLCDREFx = 01 0.8 52 Specifications V VCC + 0.2 V 1.5 V 1.2 Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 5-38 lists the characteristics of the LCD controller. Table 5-38. LCD_C, Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER VLCD LCD voltage TEST CONDITIONS VCC MIN TYP VLCDx = 0000, VLCDEXT = 0 2.4 V to 3.6 V VCC LCDCPEN = 1, VLCDx = 0001 2 V to 3.6 V 2.60 LCDCPEN = 1, VLCDx = 0010 2 V to 3.6 V 2.66 LCDCPEN = 1, VLCDx = 0011 2 V to 3.6 V 2.72 LCDCPEN = 1, VLCDx = 0100 2 V to 3.6 V 2.78 LCDCPEN = 1, VLCDx = 0101 2 V to 3.6 V 2.84 LCDCPEN = 1, VLCDx = 0110 2 V to 3.6 V 2.90 LCDCPEN = 1, VLCDx = 0111 2 V to 3.6 V 2.96 LCDCPEN = 1, VLCDx = 1000 2 V to 3.6 V 3.02 LCDCPEN = 1, VLCDx = 1001 2 V to 3.6 V 3.08 LCDCPEN = 1, VLCDx = 1010 2 V to 3.6 V 3.14 LCDCPEN = 1, VLCDx = 1011 2 V to 3.6 V 3.20 LCDCPEN = 1, VLCDx = 1100 2 V to 3.6 V 3.26 LCDCPEN = 1, VLCDx = 1101 2.2 V to 3.6 V 3.32 LCDCPEN = 1, VLCDx = 1110 2.2 V to 3.6 V 3.38 MAX UNIT V LCDCPEN = 1, VLCDx = 1111 2.2 V to 3.6 V 3.50 ICC,Peak,CP Peak supply currents due to charge pump activities 3.72 LCDCPEN = 1, VLCDx = 1111 2.2 V 200 tLCD,CP,on Time to charge CLCD when discharged CLCD = 4.7 µF, LCDCPEN = 0→1, VLCDx = 1111 2.2 V 100 ICP,Load Maximum charge pump load current LCDCPEN = 1, VLCDx = 1111 2.2 V RLCD,Seg LCD driver output impedance, segment lines LCDCPEN = 1, VLCDx = 1000, ILOAD = ±10 µA 2.2 V 10 kΩ RLCD,COM LCD driver output impedance, common lines LCDCPEN = 1, VLCDx = 1000, ILOAD = ±10 µA 2.2 V 10 kΩ µA 500 50 µA Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated ms 53 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com 5.16 SD24_B Table 5-39 lists the operating conditions of the SD24_B. Table 5-39. SD24_B, Power Supply and Operating Conditions MIN MAX TA Ambient temperature –40 85 °C fSD Modulator clock frequency 0.03 2.3 MHz VI Absolute input voltage AVSS – 1 AVCC VIC Common-mode input voltage VID,FS Differential full-scale input voltage CREF (2) Bipolar mode, VID = VI,A+ – VI,A– Differential input voltage for specified performance (1) VID VREF load capacitance (2) 2.4 REFON = 1 3.6 UNIT Analog supply voltage (1) AVCC = DVCC, AVSS = DVSS = 0 V TYP AVCC AVSS – 1 AVCC –VREF/GAIN +VREF/GAIN SD24GAINx = 1 ±900 ±930 SD24GAINx = 2 ±450 ±460 SD24GAINx = 4 ±225 ±230 SD24GAINx = 8 ±112 ±120 SD24GAINx = 16 ±56 ±60 SD24GAINx = 32 ±28 ±30 SD24GAINx = 64 ±14 ±14 SD24GAINx = 128 ±7 ±7.25 SD24REFS = 1 V V V mV mV 100 nF The full-scale range (FSR) is defined by VFS+ = +VREF/GAIN and VFS– = –VREF/GAIN: FSR = VFS+ – VFS– = 2 × VREF/GAIN. If VREF is sourced externally, the analog input range should not exceed 80% of VFS+ or VFS–, that is, VID = 0.8 VFS– to 0.8 VFS+. If VREF is sourced internally, the given VID ranges apply. MIN values are calculated based on a VREF of 1.125 V. TYP values are calculated based on a VREF of 1.16 V. There is no capacitance required on VREF. However, TI recommends using a capacitance of 100 nF to reduce any reference voltage noise. Table 5-40 lists the analog input characteristics of the SD24_B. Table 5-40. SD24_B, Analog Inputs (1) Also see Figure 5-16 PARAMETER CI Input capacitance TEST CONDITIONS VCC MIN 5.0 SD24GAINx = 2 5.0 SD24GAINx = 4 5.0 SD24GAINx = 8 5.0 SD24GAINx = 16 5.0 SD24GAINx = 32, 64, 128 5.0 SD24GAINx = 1 ZI Input impedance (pin A+ or A- to AVSS) fSD24 = 1 MHz SD24GAINx = 8 fSD24 = 1 MHz SD24GAINx = 8 SD24GAINx = 32 (1) 54 UNIT pF 200 kΩ 200 SD24GAINx = 1 Differential input impedance (pin A+ to pin A-) MAX 200 3V SD24GAINx = 32 ZID TYP SD24GAINx = 1 300 3V 400 400 300 kΩ 400 All parameters pertain to each SD24_B converter. Specifications Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 1600 1400 Input Leakage Current – nA 1200 1000 800 600 400 200 0 -200 -1 -0.5 0 0.5 1 1.5 2 2.5 3 Input Voltage – V Figure 5-16. Input Leakage Current vs Input Voltage (Modulator OFF) Table 5-41 lists the supply currents of the SD24_B. Table 5-41. SD24_B, Supply Currents PARAMETER TEST CONDITIONS Analog plus digital supply f = 1 MHz, current per converter (reference SD24 SD24OSR = 256 not included) ISD,256 Analog plus digital supply f = 2 MHz, current per converter (reference SD24 SD24OSR = 512 not included) ISD,512 TYP MAX SD24GAIN: 1 490 600 SD24GAIN: 2 490 600 SD24GAIN: 4 490 600 SD24GAIN: 8 559 700 559 700 SD24GAIN: 32 627 800 SD24GAIN: 64 627 800 SD24GAIN: 128 627 800 SD24GAIN: 1 600 700 677 800 740 900 SD24GAIN: 16 SD24GAIN: 8 VCC 3V 3V SD24GAIN: 32 MIN UNIT µA µA ISD24REFonly Current of internal SD24 reference and buffers (includes shared reference) No converter is active, (SD24REFS = 1, SD24BCCTLx.SD24SC = 0) 3V 147 190 µA ISD24REF,Conv0 Current of internal SD24 reference and buffers (includes shared reference) Converter 0 is active, (SD24REFS = 1, SD24BCCTL0.SD24SC = 1) 3V 75 110 µA ISD24REF,notConv0 Current of internal SD24 reference and buffers (includes shared reference) Any converter other than converter 0 is active, (SD24REFS = 1, SD24BCCTL0.SD24SC = 0, SD24BCCTLx.SD24SC = 1) 3V 137 175 µA Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 55 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 5-42 lists the performance characteristics of the SD24_B. Table 5-42. SD24_B, Performance fSD24 = 1 MHz, SD24OSRx = 256, SD24REFON = 1 PARAMETER TEST CONDITIONS VCC SD24GAIN: 1 Integral nonlinearity, endSD24GAIN: 8 point fit SD24GAIN: 32 INL Gnom 3V +0.01 % of FSR SD24GAIN: 2 2 SD24GAIN: 4 4 8 3V 16 32 SD24GAIN: 64 64 SD24GAIN: 128 128 SD24GAIN: 8, with external reference (1.2 V) 3V SD24GAIN: 32, with external reference (1.2 V) ΔEG/ΔT Gain error temperature coefficient (2), internal reference ΔEG/ΔT Gain error temperature coefficient (2), external reference SD24GAIN: 1, 8, or 32 (with internal reference) –1% +1% –2% +2% –2% +2% 3V 80 SD24GAIN: 1 (with external reference) SD24GAIN: 8 (with external reference) Gain error vs VCC (3) 3V 15 SD24GAIN: 32 (with external reference) SD24GAIN: 8 0.1 3V 0.1 %/V 0.4 SD24GAIN: 1 (with Vdiff = 0 V) Offset error (4) SD24GAIN: 8 2.3 3V 1 SD24GAIN: 32 Offset error (4) SD24GAIN: 8 3V SD24GAIN: 32 Offset error temperature coefficient (5) SD24GAIN: 8 SD24GAIN: 32 (1) (2) (3) (4) (5) 56 –0.2 +0.2 –0.7 +0.7 –1.4 SD24GAIN: 1 ΔEOS/ΔT mV 0.5 SD24GAIN: 1 (with Vdiff = 0 V) EOS[FS] ppm/°C 15 SD24GAIN: 32 EOS[V] ppm/°C 15 SD24GAIN: 1 ΔEG/ΔVCC +0.01 1 SD24GAIN: 1, with external reference (1.2 V) Gain error (1) UNIT –0.01 SD24GAIN: 1 SD24GAIN: 16 MAX +0.01 SD24GAIN: 32 EG TYP –0.01 SD24GAIN: 8 Nominal gain MIN –0.01 % FS +1.4 2 3V 0.25 µV/°C 0.1 The gain error EG specifies the deviation of the actual gain Gact from the nominal gain Gnom: EG = (Gact – Gnom)/Gnom. It covers process, temperature, and supply voltage variations. The gain error temperature coefficient ΔEG/ ΔT specifies the variation of the gain error EG over temperature (EG(T) = (Gact(T) – Gnom)/Gnom) using the box method (that is, minimum and maximum values): ΔEG/ ΔT = (MAX(EG(T)) – MIN(EG(T) ) / (MAX(T) – MIN(T)) = (MAX(Gact(T)) – MIN(Gact(T)) / Gnom / (MAX(T) – MIN(T)) with T ranging from –40°C to 85°C. The gain error vs VCC coefficient ΔEG/ ΔVCC specifies the variation of the gain error EG over supply voltage (EG(VCC) = (Gact(VCC) – Gnom)/Gnom) using the box method (that is, minimum and maximum values): ΔEG/ ΔVCC = (MAX(EG(VCC)) – MIN(EG(VCC) ) / (MAX(VCC) – MIN(VCC)) = (MAX(Gact(VCC)) – MIN(Gact(VCC)) / Gnom / (MAX(VCC) – MIN(VCC)) with VCC ranging from 2.4 V to 3.6 V. The offset error EOS is measured with shorted inputs in 2s-complement mode with +100% FS = VREF/G and –100% FS = –VREF/G. Conversion between EOS [FS] and EOS [V] is as follows: EOS [FS] = EOS [V] × G/VREF, EOS [V] = EOS [FS] × VREF/G. The offset error temperature coefficient ΔEOS/ ΔT specifies the variation of the offset error EOS over temperature using the box method (that is, minimum and maximum values): ΔEOS/ ΔT = (MAX(EOS(T)) – MIN(EOS(T) ) / (MAX(T) – MIN(T)) with T ranging from –40°C to 85°C. Specifications Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 5-42. SD24_B, Performance (continued) fSD24 = 1 MHz, SD24OSRx = 256, SD24REFON = 1 PARAMETER TEST CONDITIONS VCC SD24GAIN: 1 ΔEOS/ΔVCC Offset error vs VCC (6) SD24GAIN: 8 3V SD24GAIN: 8 3V SD24GAIN: 8, fCM = 50 Hz, VCM = 120 mV AC PSRR, ext AC PSRR, int AC power supply rejection ratio, internal reference (9) Crosstalk between converters (10) –110 –110 SD24GAIN: 1, VCC = 3 V + 50 mV × sin(2π × fVCC × t), fVCC = 50 Hz –61 SD24GAIN: 8, VCC = 3 V + 50 mV × sin(2π × fVCC × t), fVCC = 50 Hz –75 SD24GAIN: 32, VCC = 3 V + 50 mV × sin(2π × fVCC × t), fVCC = 50 Hz –79 SD24GAIN: 1, VCC = 3 V + 50 mV × sin(2π × fVCC × t), fVCC = 50 Hz –61 SD24GAIN: 8, VCC = 3 V + 50 mV × sin(2π × fVCC × t), fVCC = 50 Hz –75 SD24GAIN: 32, VCC = 3 V + 50 mV × sin(2π × fVCC × t), fVCC = 50 Hz –79 Crosstalk source: SD24GAIN: 1, Sine-wave with maximum possible Vpp, fIN = 50 Hz or 100 Hz, Converter under test: SD24GAIN: 8 Crosstalk source: SD24GAIN: 1, Sine-wave with maximum possible Vpp, fIN = 50 Hz or 100 Hz, Converter under test: SD24GAIN: 32 dB dB –100 Crosstalk source: SD24GAIN: 1, Sine-wave with maximum possible Vpp, fIN = 50 Hz or 100 Hz, Converter under test: SD24GAIN: 1 XT µV/V –120 3V SD24GAIN: 32, fCM = 50 Hz, VCM = 30 mV AC power supply rejection ratio, external reference (9) 125 –100 SD24GAIN: 1, fCM = 50 Hz, VCM = 930 mV Common-mode rejection at 50 Hz (8) UNIT –120 SD24GAIN: 32 CMRR,50Hz MAX 50 SD24GAIN: 1 Common-mode rejection at DC (7) TYP 500 SD24GAIN: 32 CMRR,DC MIN dB dB –120 3V –115 dB –110 (6) The offset error vs VCC ΔEOS/ ΔVCC specifies the variation of the offset error EOS over supply voltage using the box method (that is, minimum and maximum values): ΔEOS/ ΔVCC = (MAX(EOS(VCC)) – MIN(EOS(VCC) ) / (MAX(VCC) – MIN(VCC)) with VCC ranging from 2.4 V to 3.6 V. (7) The DC CMRR specifies the change in the measured differential input voltage value when the common-mode voltage varies: DC CMRR = –20log(ΔMAX/FSR) with ΔMAX being the difference between the minium value and the maximum value measured when sweeping the common-mode voltage. The DC CMRR is measured with both inputs connected to the common-mode voltage (that is, no differential input signal is applied), and the common-mode voltage is swept from –1 V to VCC. (8) The AC CMRR is the difference between a hypothetical signal with the amplitude and frequency of the applied common-mode ripple applied to the inputs of the ADC and the actual common-mode signal spur visible in the FFT spectrum: AC CMRR = Error Spur [dBFS] – 20log(VCM / 1.2 V / G) [dBFS] with a common-mode signal of VCM × sin(2π × fCM × t) applied to the analog inputs. The AC CMRR is measured with the both inputs connected to the common-mode signal; that is, no differential input signal is applied. With the specified typical values the error spur is within the noise floor (as specified by the SINAD values). (9) The AC PSRR is the difference between a hypothetical signal with the amplitude and frequency of the applied supply voltage ripple applied to the inputs of the ADC and the actual supply ripple spur visible in the FFT spectrum: AC PSRR = Error Spur [dBFS] – 20log(50 mV / 1.2 V / G) [dBFS] with a signal of 50 mV × sin(2π × fVCC × t) added to VCC. The AC PSRR is measured with the inputs grounded; that is, no analog input signal is applied. With the specified typical values the error spur is within the noise floor (as specified by the SINAD values). SD24GAIN: 1 → Hypothetical signal: 20log(50 mV / 1.2 V / 1) = –27.6 dBFS SD24GAIN: 8 → Hypothetical signal: 20log(50 mV / 1.2 V / 8) = –9.5 dBFS SD24GAIN: 32 → Hypothetical signal: 20log(50 mV / 1.2 V / 32) = 2.5 dBFS (10) The crosstalk XT is specified as the tone level of the signal applied to the crosstalk source seen in the spectrum of the converter under test. It is measured with the inputs of the converter under test being grounded. Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 57 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 5-43 lists the AC performance characteristics of the SD24_B. Table 5-43. SD24_B, AC Performance fSD24 = 1 MHz, SD24OSRx = 256, SD24REFON = 1 PARAMETER TEST CONDITIONS VCC SD24GAIN: 1 MIN TYP 82 86 SD24GAIN: 2 84 Signal-to-noise + distortion SD24GAIN: 8 ratio SD24GAIN: 16 fIN = 50 Hz (1) 3V SD24GAIN: 32 81 Total harmonic distortion 71 dB 73 SD24GAIN: 64 67 SD24GAIN: 128 61 95 fIN = 50 Hz (1) SD24GAIN: 8 3V 90 SD24GAIN: 32 (1) 83 80 SD24GAIN: 1 THD UNIT 85 SD24GAIN: 4 SINAD MAX dB 86 The following voltages were applied to the SD24_B inputs: VI,A+(t) = 0 V + VPP / 2 × sin(2π × fIN × t) and VI,A–(t) = 0 V – VPP/2 × sin(2π × fIN × t) resulting in a differential voltage of VID = VI,A+(t) – VI,A–(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value allowed for a given range (according to SD24_B recommended operating conditions). Table 5-44 lists the AC performance characteristics of the SD24_B. Table 5-44. SD24_B, AC Performance fSD24 = 2 MHz, SD24OSRx = 512, SD24REFON = 1 PARAMETER SINAD (1) 58 TEST CONDITIONS VCC MIN TYP SD24GAIN: 1 87 SD24GAIN: 2 85 SD24GAIN: 4 84 Signal-to-noise + distortion SD24GAIN: 8 ratio SD24GAIN: 16 fIN = 50 Hz (1) 3V 83 81 SD24GAIN: 32 76 SD24GAIN: 64 71 SD24GAIN: 128 65 MAX UNIT dB The following voltages were applied to the SD24_B inputs: VI,A+(t) = 0 V + VPP / 2 × sin(2π × fIN × t) and VI,A–(t) = 0 V – VPP/2 × sin(2π × fIN × t) resulting in a differential voltage of VID = VI,A+(t) – VI,A–(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value allowed for a given range (according to SD24_B recommended operating conditions). Specifications Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 5-45 lists the AC performance characteristics of the SD24_B. Table 5-45. SD24_B, AC Performance fSD24 = 32 kHz, SD24OSRx = 512, SD24REFON = 1 (see Figure 5-17 and Figure 5-18) PARAMETER VCC MIN TYP 89 SD24GAIN: 2 85 SD24GAIN: 4 84 Signal-to-noise + distortion SD24GAIN: 8 ratio SD24GAIN: 16 SINAD (1) TEST CONDITIONS SD24GAIN: 1 fIN = 50 Hz (1) MAX UNIT 82 3V dB 80 SD24GAIN: 32 76 SD24GAIN: 64 67 SD24GAIN: 128 61 The following voltages were applied to the SD24_B inputs: VI,A+(t) = 0 V + VPP / 2 × sin(2π × fIN × t) and VI,A–(t) = 0 V – VPP/2 × sin(2π × fIN × t) resulting in a differential voltage of VID = VI,A+(t) – VI,A–(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value allowed for a given range (according to SD24_B recommended operating conditions). 110.0 100.0 Theoretical limit (second order) 100.0 80.0 SINAD – dB SINAD − dB 90.0 80.0 60.0 40.0 70.0 20.0 60.0 0.0 50.0 10 100 1000 0 0.2 0.4 0.6 Vpp – Vref/Gain OSR Figure 5-17. SINAD vs OSR (fSD24 = 1 MHz, SD24REFON = 1, SD24GAIN = 1) 0.8 1 Figure 5-18. SINAD vs VPP Table 5-46 lists the external reference requirements of the SD24_B. Table 5-46. SD24_B External Reference Input ensure correct input voltage range according to VREF VCC MIN TYP MAX VREF(I) Input voltage PARAMETER SD24REFS = 0 TEST CONDITIONS 3V 1.0 1.20 1.5 V IREF(I) Input current SD24REFS = 0 3V 50 nA Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated UNIT 59 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com 5.17 ADC10_A Table 5-47 lists the input requirements of the ADC. Table 5-47. 10-Bit ADC, Power Supply and Input Range Conditions over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC AVCC Analog supply voltage AVCC and DVCC are connected together, AVSS and DVSS are connected together, V(AVSS) = V(DVSS) = 0 V V(Ax) Analog input voltage range (1) All ADC10_A pins Operating supply current into AVCC terminal, REF module and reference buffer off fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF = 00 Operating supply current into AVCC terminal, REF module on, reference buffer on fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 1, SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF = 01 Operating supply current into AVCC terminal, REF module off, reference buffer on MIN TYP MAX 1.8 3.6 V 0 AVCC V 2.2 V 68 100 3V 78 110 3V 124 180 fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF = 10, VEREF = 2.5 V 3V 105 160 Operating supply current into AVCC terminal, REF module off, reference buffer off fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF = 11, VEREF = 2.5 V 3V 72 110 CI Input capacitance Only one terminal Ax can be selected at one time from the pad to the ADC10_A capacitor array including wiring and pad 2.2 V 3.5 RI Input MUX ON resistance IADC10_A (1) UNIT µA pF AVCC > 2.0 V, 0 V ≤ VAx ≤ AVCC 36 1.8 V < AVCC < 2.0 V, 0 V ≤ VAx ≤ AVCC 96 kΩ The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. The external reference voltage requires decoupling capacitors. Connect two decoupling capacitors, 10 µF and 100 nF, to VREF to decouple the dynamic current required for an external reference source if it is used for the ADC10_A. Also see the MSP430x5xx and MSP430x6xx Family User's Guide. Table 5-48 lists the switching characteristics of the ADC. Table 5-48. 10-Bit ADC, Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC MIN TYP MAX UNIT For specified performance of ADC10_A linearity parameters 2.2 V, 3 V 0.45 5 5.5 MHz Internal ADC10_A oscillator (1) ADC10DIV = 0, fADC10CLK = fADC10OSC 2.2 V, 3 V 4.4 4.9 5.6 MHz 2.2 V, 3 V 2.4 Conversion time REFON = 0, Internal oscillator, 12 ADC10CLK cycles, 10-bit mode, fADC10OSC = 4 MHz to 5 MHz fADC10CLK fADC10OSC tCONVERT TEST CONDITIONS µs External fADC10CLK from ACLK, MCLK, or SMCLK, ADC10SSEL ≠ 0 tADC10ON Turn-on settling time of the ADC tSample Sampling time (1) (2) (3) 60 See 3.0 12 × 1 / fADC10CLK (2) 100 RS = 1000 Ω, RI = 96 kΩ, CI = 3.5 pF (3) 1.8 V 3 RS = 1000 Ω, RI = 36 kΩ, CI = 3.5 pF (3) 3V 1 ns µs The ADC10OSC is sourced directly from MODOSC inside the UCS. The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already settled. Approximately 8 Tau (τ) are needed to get an error of less than ±0.5 LSB Specifications Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 5-49 lists the linearity parameters of the ADC. Table 5-49. 10-Bit ADC, Linearity Parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS 1.4 V ≤ (VeREF+ – VeREF–) ≤ 1.6 V, CVeREF+ = 20 pF VCC MAX +1.0 –1.0 +1.0 UNIT EI Integral linearity error ED Differential linearity error 1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF 2.2 V, 3 V –1.0 +1.0 LSB EO Offset error 1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF Internal impedance of source RS < 100 Ω 2.2 V, 3 V –1.0 +1.0 LSB EG Gain error 1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF, ADC10SREFx = 11b 2.2 V, 3 V –1.0 +1.0 LSB ET Total unadjusted error 1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF, ADC10SREFx = 11b 2.2 V, 3 V –2.0 +2.0 LSB MIN MAX UNIT 1.6 V < (VeREF+ – VeREF–) ≤ VAVCC, CVeREF+ = 20 pF 2.2 V, 3 V MIN –1.0 LSB Table 5-50 lists the requirement for the ADC external reference. Table 5-50. 10-Bit ADC, External Reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TEST CONDITIONS VCC VeREF+ Positive external reference voltage input VeREF+ > VeREF– (2) 1.4 AVCC V VeREF– Negative external reference voltage input VeREF+ > VeREF– (3) 0 1.2 V (VeREF+ – VeREF–) Differential external reference voltage input VeREF+ > VeREF– (4) 1.4 AVCC V –26 +26 IVeREF+, IVeREF– CVREF+ (1) (2) (3) (4) (5) Static input current 1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V, fADC10CLK = 5 MHz, ADC10SHTx = 0x0001, Conversion rate 200 ksps 1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V, fADC10CLK = 5 MHZ, ADC10SHTX = 0x1000, Conversion rate 20 ksps Capacitance at VREF+ terminal See (5) 2.2 V, 3 V µA –1 +1 10 µF The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements. Connect two decoupling capacitors, 10 µF and 100 nF, to VREF to decouple the dynamic current required for an external reference source if it is used for the ADC10_A. Also see the MSP430x5xx and MSP430x6xx Family User's Guide. Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 61 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com 5.18 REF Table 5-51 lists the characteristics of the REF. Table 5-51. REF Built-In Reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS REFVSEL = {2} for 2.5 V, REFON = 1 Positive built-in reference voltage VREF+ REFVSEL = {1} for 2 V, REFON = 1 REFVSEL = {0} for 1.5 V, REFON = 1 AVCC(min) AVCC minimum voltage, Positive built-in reference active VCC 3V 2.2 V, 3 V MIN TYP MAX 2.47 2.51 2.55 1.96 1.99 2.02 1.48 1.5 1.52 REFVSEL = {0} for 1.5 V 1.8 REFVSEL = {1} for 2 V 2.2 REFVSEL = {2} for 2.5 V 2.7 fADC10CLK = 5.0 MHz, REFON = 1, REFBURST = 0, REFVSEL = {2} for 2.5 V V V 18 24 16.1 21 fADC10CLK = 5.0 MHz, REFON = 1, REFBURST = 0, REFVSEL = {0} for 1.5 V 14.4 21 IVREF+ = 0 A, REFVSEL = {0, 1, 2}, REFON = 1 < 18 50 ppm/ °C f = 5.0 MHz, Operating supply current into ADC10CLK REFON = 1, REFBURST = 0, AVCC terminal (1) REFVSEL = {1} for 2 V IREF+ UNIT 3V µA TCREF+ Temperature coefficient of built-in reference (2) ISENSOR Operating supply current into REFON = 0, INCH = 0Ah, AVCC terminal (3) ADC10ON = N/A, TA = 30°C VSENSOR See VMID AVCC divider at channel 11 ADC10ON = 1, INCH = 0Bh, VMID ≈ 0.5 × VAVCC tSENSOR(sample) Sample time required if channel 10 is selected (5) ADC10ON = 1, INCH = 0Ah, Error of conversion result ≤ 1 LSB 30 µs tVMID(sample) Sample time required if channel 11 is selected (6) ADC10ON = 1, INCH = 0Bh, Error of conversion result ≤ 1 LSB 1 µs PSRR_DC Power supply rejection ratio (DC) AVCC = AVCC (min) to AVCC(max), TA = 25°C, REFVSEL = {0, 1, 2}, REFON = 1 120 µV/V PSRR_AC Power supply rejection ratio (AC) AVCC = AVCC (min) to AVCC(max), TA = 25°C, f = 1 kHz, ΔVpp = 100 mV, REFVSEL = {0, 1, 2}, REFON = 1 6.4 mV/V tSETTLE Settling time of reference voltage (7) AVCC = AVCC (min) to AVCC(max), REFVSEL = {0, 1, 2}, REFON = 0 → 1 75 µs VSD24REF SD24_B internal reference voltage SD24REFS = 1 3V tON SD24_B internal reference turnon time SD24REFS = 0→1, CREF = 100 nF 3V (1) (2) (3) (4) (5) (6) (7) 62 (4) ADC10ON = 1, INCH = 0Ah, TA = 30°C 2.2 V 17 22 3V 17 22 2.2 V 770 3V 770 mV 2.2 V 1.06 1.1 1.14 3V 1.46 1.5 1.54 1.151 1.1623 µA 1.174 200 V V µs The internal reference current is supplied from the AVCC terminal. Consumption is independent of the ADC10ON control bit, unless a conversion is active. The REFON bit enables to settle the built-in reference before starting an analog-to-digital conversion. Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C – (–40°C)). The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is high). When REFON = 1, ISENSOR is already included in IREF+. The temperature sensor offset can be significant. TI recommends a single-point calibration to minimize the offset error of the built-in temperature sensor. The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on). The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed. The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. Specifications Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 5.19 Comparator_B Table 5-52 lists the characteristics of the comparator. Table 5-52. Comparator_B over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC TEST CONDITIONS VCC Supply voltage MIN TYP 1.8 3.6 1.8 V IAVCC_COMP Comparator operating supply current into AVCC, excludes reference resistor ladder CBPWRMD = 00, CBON = 1, CBRSx = 00 CBPWRMD = 01, CBON = 1, CBRSx = 00 CBPWRMD = 10, CBON = 1, CBRSx = 00 IAVCC_REF Quiescent current of resistor ladder into AVCC, includes REF module current VIC Common-mode input range VOFFSET Input offset voltage CIN Input capacitance RSIN tPD tPD,filter tEN_CMP Series input resistance Propagation delay, response time Propagation delay with filter active Comparator enable time CBREFACC = 1, CBREFLx = 01, CBRSx = 10, REFON = 0, CBON = 0 CBREFACC = 0, CBREFLx = 01, CBRSx = 10, REFON = 0, CBON = 0 2.2 V 22 50 3V 32 65 2.2 V, 3 V 10 30 0.2 0.85 10 22 33 40 2.2 V, 3 V VCC – 1 CBPWRMD = 00 –20 20 CBPWRMD = 01 or 10 –20 20 5 On (switch closed) 3 Resistor reference enable time 50 TCREF Temperature coefficient reference VCB_REF Reference voltage for a given tap CBPWRMD = 01, CBF = 0 600 CBPWRMD = 10, CBF = 0 50 CBPWRMD = 00, CBON = 1, CBF = 1, CBFDLY = 00 0.30 0.6 1.5 CBPWRMD = 00, CBON = 1, CBF = 1, CBFDLY = 01 0.5 1.0 1.8 CBPWRMD = 00, CBON = 1, CBF = 1, CBFDLY = 10 0.8 1.8 3.4 CBPWRMD = 00, CBON = 1, CBF = 1, CBFDLY = 11 1.5 3.4 6.5 1 2 VIN = reference into resistor ladder, n = 0 to 31 mV kΩ ns µs µs µs 100 1.0 1.5 µs 50 ppm/ °C VIN × VIN × VIN × (n + (n + 1) (n + 1.5) / 32 / 32 0.5) / 32 Specifications Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated V MΩ 450 CBON = 0 to CBON = 1 µA pF 4 CBPWRMD = 00, CBF = 0 CBON = 0 to CBON = 1, CBPWRMD = 00 or 01 V µA 0 Off (switch open) UNIT 40 CBON = 0 to CBON = 1, CBPWRMD = 10 tEN_REF MAX V 63 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com 5.20 Flash Table 5-53 lists the characteristics of the flash memory. Table 5-53. Flash Memory over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TJ MIN TYP Program and erase supply voltage IPGM Average supply current from DVCC during program 3 5 mA IERASE Average supply current from DVCC during erase 6 15 mA IMERASE, IBANK Average supply current from DVCC during mass erase or bank erase 6 15 mA Cumulative program time 3.6 UNIT DVCC(PGM/ERASE) tCPT 1.8 MAX (1) 16 104 Program and erase endurance ms cycles tRetention Data retention duration tWord Word or byte program time (2) 64 85 µs tBlock, 0 Block program time for first byte or word (2) 49 65 µs 1–(N–1) Block program time for each additional byte or word, except for last byte or word (2) 37 49 µs 55 73 µs 23 32 ms 0 1 MHz tBlock, tBlock, Block program time for last byte or word N 25°C 105 V (2) tErase Erase time for segment erase, mass erase, and bank erase when available (2) fMCLK,MGR MCLK frequency in marginal read mode (FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1) (1) (2) 100 years The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming methods: individual word or byte write and block write modes. These values are hardwired into the state machine of the flash controller. 5.21 Emulation and Debug Table 5-54 lists the characteristics of the JTAG and SBW interface. Table 5-54. JTAG and Spy-Bi-Wire (SBW) Interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC MIN TYP MAX UNIT fSBW Spy-Bi-Wire input frequency 2.2 V, 3 V 0 20 MHz tSBW,Low Spy-Bi-Wire low clock pulse duration 2.2 V, 3 V 0.025 15 µs tSBW, En Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge) (1) 2.2 V, 3 V 1 µs tSBW,Rst Spy-Bi-Wire return to normal operation time fTCK TCK input frequency for 4-wire JTAG (2) Rinternal Internal pulldown resistance on TEST (1) (2) 64 15 100 2.2 V 0 5 MHz 3V 0 10 MHz 2.2 V, 3 V 45 80 kΩ 60 µs Tools that access the Spy-Bi-Wire interface must wait for the minimum tSBW,En time after pulling the TEST/SBWTCK pin high before applying the first SBWTCK clock edge. fTCK may be restricted to meet the timing requirements of the module selected. Specifications Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 6 Detailed Description 6.1 Overview The TI MSP430F67xxA family of polyphase metering SoCs are powerful highly-integrated solutions for revenue meters that offer accuracy and low system cost with few external components. The MSP430F67xxA uses the low-power MSP430 CPU with a 32-bit multiplier to perform all energy calculations, metering applications such as tariff rate management, and communications with AMR and AMI modules. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 65 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 6.2 www.ti.com Functional Block Diagrams Figure 6-1 shows the functional block diagram for the MSP430F677xA, MSP430F676xA, and MSP430F674xA devices in the PEU package. XIN XOUT DVCC DVSS AVCC AVSS AUX1 AUX2 AUX3 PA P1.x P2.x RST/NMI PB P3.x P4.x PC P5.x P6.x P7.x PD P8.x PE P9.x P10.x PF P11.x (32 kHz) ACLK Unified Clock System 512KB 256KB 128KB 32KB 16KB Flash RAM SMCLK MCLK SYS Watchdog Port Mapping Controller MPY32 CRC16 AES128 I/O Ports P1, P2 2×8 I/Os Interrupt, Wakeup I/O Ports P3, P4 2×8 I/Os I/O Ports P5, P6 2×8 I/Os I/O Ports P7, P8 2×8 I/Os I/O Ports P9, P10 2×8 I/O I/O Ports P11 1×6 I/O PA 1×16 I/Os PB 1×16 I/Os PC 1×16 I/Os PD 1×16 I/Os PE 1×16 I/O PF 1×6 I/O TA0 TA1 TA2 TA3 eUSCI_A0 eUSCI_A1 eUSCI_A2 eUSCI_A3 eUSCI_B0 eUSCI_B1 CPUXV2 and Working Registers (25 MHz) EEM (S: 8+2) JTAG. SBW Interface Port PJ PMM Auxiliary Supplies SD24_B ADC10_A LCD_C REF LDO, SVM, SVS, BOR 7 Channel 6 Channel 4 Channel 10 Bit 200 ksps 8-Mux Up to 320 Segments Reference 1.5 V, 2.0 V, 2.5 V RTC_C Timer_A 3 CC Registers PJ.x Timer_A 2 CC Registers (UART, IrDA,SPI) DMA COMP_B 3 Channel (External Voltage Monitoring) 2 (SPI, I C) Copyright © 2016, Texas Instruments Incorporated Figure 6-1. Functional Block Diagram – PEU Package Figure 6-2 shows the functional block diagram for the MSP430F677xA, MSP430F676xA, and MSP430F674xA devices in the PZ package. XIN XOUT DVCC DVSS AVCC AVSS AUX1 AUX2 AUX3 PA P1.x P2.x RST/NMI PB P3.x P4.x PC P5.x P6.x P7.x PD P8.x (32 kHz) ACLK Unified Clock System 512KB 256KB 128KB 32KB 16KB Flash RAM SMCLK MCLK SYS Watchdog Port Mapping Controller CRC16 MPY32 AES128 I/O Ports P1, P2 2×8 I/Os Interrupt, Wakeup I/O Ports P3, P4 2×8 I/Os I/O Ports P5, P6 2×8 I/Os I/O Ports P7, P8 1×8 I/Os 1×2 I/Os PA 1×16 I/Os PB 1×16 I/Os PC 1×16 I/Os PD 1×10 I/Os TA0 TA1 TA2 TA3 eUSCI_A0 eUSCI_A1 eUSCI_A2 eUSCI_A3 eUSCI_B0 eUSCI_B1 CPUXV2 and Working Registers (25 MHz) EEM (S: 8+2) JTAG, SBW Interface Port PJ PMM Auxiliary Supplies LDO, SVM, SVS, BOR PJ.x SD24_B 7 Channel 6 Channel 4 Channel ADC10_A 10 Bit 200 ksps LCD_C 8-Mux Up to 320 Segments REF Reference 1.5 V, 2.0 V, 2.5 V RTC_C Timer_A 3 CC Registers Timer_A 2 CC Registers (UART, IrDA,SPI) DMA COMP_B 3 Channel (External Voltage Monitoring) 2 (SPI, I C) Copyright © 2016, Texas Instruments Incorporated Figure 6-2. Functional Block Diagram – PZ Package 66 Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com 6.3 SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 CPU (Link to User's Guide) The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers (see Figure 6-3). Peripherals are connected to the CPU using data, address, and control buses. Peripherals can be managed with all instructions. Program Counter PC/R0 Stack Pointer SP/R1 Status Register Constant Generator SR/CG1/R2 CG2/R3 General-Purpose Register R4 General-Purpose Register R5 General-Purpose Register R6 General-Purpose Register R7 General-Purpose Register R8 General-Purpose Register R9 General-Purpose Register R10 General-Purpose Register R11 General-Purpose Register R12 General-Purpose Register R13 General-Purpose Register R14 General-Purpose Register R15 Figure 6-3. CPU Registers Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 67 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 6.4 www.ti.com Instruction Set The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data. Table 6-1 lists examples of the three types of instruction formats. Table 6-2 lists the address modes. Table 6-1. Instruction Word Formats INSTRUCTION WORD FORMAT EXAMPLE Dual operands, source and destination ADD Single operands, destination only R4 + R5 → R5 R8 PC → (TOS), R8 → PC CALL Relative jump, conditional or unconditional OPERATION R4,R5 JNE Jump-on-equal bit = 0 Table 6-2. Address Mode Descriptions S (1) D (1) SYNTAX EXAMPLE Register ✓ ✓ MOV Rs,Rd MOV R10,R11 R10 → R11 Indexed ✓ ✓ MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) → M(6+R6) Symbolic (PC relative) ✓ ✓ MOV EDE,TONI Absolute ✓ ✓ MOV & MEM, & TCDAT Indirect ✓ MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) → M(Tab+R6) Indirect autoincrement ✓ MOV @Rn+,Rm MOV @R10+,R11 M(R10) → R11 R10 + 2 → R10 Immediate ✓ MOV #X,TONI MOV #45,TONI #45 → M(TONI) ADDRESS MODE (1) S = source, D = destination 68 Detailed Description OPERATION M(EDE) → M(TONI) M(MEM) → M(TCDAT) Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com 6.5 SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Operating Modes These microcontrollers have one active mode and six software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. Software can configure the following operating modes: • Active mode (AM) – All clocks are active • Low-power mode 0 (LPM0) – CPU is disabled – ACLK and SMCLK remain active, MCLK is disabled – FLL loop control remains active • Low-power mode 1 (LPM1) – CPU is disabled – FLL loop control is disabled – ACLK and SMCLK remain active, MCLK is disabled • Low-power mode 2 (LPM2) – CPU is disabled – MCLK and FLL loop control and DCOCLK are disabled – DC generator of the DCO remains enabled – ACLK remains active • Low-power mode 3 (LPM3) – CPU is disabled – MCLK, FLL loop control, and DCOCLK are disabled – DC generator of the DCO is disabled – ACLK remains active • Low-power mode 4 (LPM4) – CPU is disabled – ACLK is disabled – MCLK, FLL loop control, and DCOCLK are disabled – DC generator of the DCO is disabled – Crystal oscillator is stopped – Complete data retention • Low-power mode 3.5 (LPM3.5) – Internal regulator disabled – No RAM retention, backup RAM retained – I/O pad state retention – RTC clocked by low-frequency oscillator – Wake-up input from RST/NMI, RTC_C events, port P1, or port P2 • Low-power mode 4.5 (LPM4.5) – Internal regulator disabled – No RAM retention, backup RAM retained – RTC is disabled – I/O pad state retention – Wake-up input from RST/NMI, port P1, or port P2 Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 69 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 6.6 www.ti.com Interrupt Vector Addresses The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see Table 6-3). The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 6-3. Interrupt Sources, Flags, and Vectors INTERRUPT SOURCE System Reset Power up External reset Watchdog time-out, key violation Flash memory key violation INTERRUPT FLAG WDTIFG, KEYV (SYSRSTIV) (1) (2) SYSTEM INTERRUPT WORD ADDRESS PRIORITY Reset 0FFFEh 63, highest System NMI PMM Vacant memory access JTAG mailbox SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG, VLRLIFG, VLRHIFG, VMAIFG, JMBINIFG, JMBOUTIFG (SYSSNIV) (1) (3) (Non)maskable 0FFFCh 62 User NMI NMI Oscillator fault Flash memory access violation Supply switched NMIIFG, OFIFG, ACCVIFG, AUXSWGIFG (SYSUNIV) (1) (3) (Non)maskable 0FFFAh 61 Watchdog Timer_A interval timer mode WDTIFG Maskable 0FFF8h 60 (4) Maskable 0FFF6h 59 (1) (4) Maskable 0FFF4h 58 Maskable 0FFF2h 57 Maskable 0FFF0h 56 Maskable 0FFEEh 55 Maskable 0FFECh 54 Maskable 0FFEAh 53 Maskable 0FFE8h 52 AUXSWGIFG, AUXIFG0, AUXIFG1, AUXIFG2 (AUXIV) (1) (4) Maskable 0FFE6h 51 (1) (4) eUSCI_A0 receive or transmit eUSCI_B0 receive or transmit ADC10_A SD24_B Timer TA0 Timer TA0 ADC10IFG0, ADC10INIFG, ADC10LOIFG, ADC10HIIFG, ADC10TOVIFG, ADC10OVIFG (ADC10IV) (1) (4) SD24_B Interrupt Flags (SD24IV) (1) TA0CCR0 CCIFG0 (4) (4) TA0CCR1 CCIFG1, TA0CCR2 CCIFG2, TA0IFG (TA0IV) (1) (4) (1) (4) UCA1RXIFG, UCA1TXIFG (UCA1IV) eUSCI_A2 receive or transmit UCA2RXIFG, UCA2TXIFG (UCA2IV) (1) DMA Maskable 0FFE4h 50 Timer TA1 TA1CCR0 CCIFG0 Maskable 0FFE2h 49 Timer TA1 TA1CCR1 CCIFG1, TA1IFG (TA1IV) (1) (4) Maskable 0FFE0h 48 (4) Maskable 0FFDEh 47 (1) (4) Maskable 0FFDCh 46 Maskable 0FFDAh 45 Maskable 0FFD8h 44 Maskable 0FFD6h 43 Maskable 0FFD4h 42 Maskable 0FFD2h 41 Maskable 0FFD0h 40 Maskable 0FFCEh 39 eUSCI_B1 receive or transmit I/O port P1 DMA0IFG, DMA1IFG, DMA2IFG (DMAIV) (4) (4) eUSCI_A3 receive or transmit UCA3RXIFG, UCA3TXIFG (UCA3IV) (1) UCB1RXIFG, UCB1TXIFG (UCB1IV) P1IFG.0 to P1IFG.7 (P1IV) (1) Timer TA2 TA2CCR0 CCIFG0 (4) Timer TA2 TA2CCR1 CCIFG1, TA2IFG (TA2IV) (1) (4) I/O port P2 P2IFG.0 to P2IFG.7 (P2IV) Timer TA3 TA3CCR0 CCIFG0 (4) Timer TA3 TA3CCR1 CCIFG1, TA3IFG (TA3IV) (1) (4) LCD_C 70 UCB0RXIFG, UCB0TXIFG (UCB0IV) eUSCI_A1 receive or transmit Auxiliary supplies (1) (2) (3) (4) UCA0RXIFG, UCA0TXIFG (UCA0IV) (1) (4) (1) (4) LCD_C Interrupt Flags (LCDCIV) (1) (4) Multiple source flags A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space. (Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable bit cannot disable it. Interrupt flags are in the module. Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 6-3. Interrupt Sources, Flags, and Vectors (continued) INTERRUPT SOURCE INTERRUPT FLAG RTCOFIFG, RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG, RT1PSIFG (RTCIV) (1) RTC_C Comparator_B Comparator_B Interrupt Flags (CBIV) AES AESRDYIFG WORD ADDRESS PRIORITY Maskable 0FFCCh 38 Maskable 0FFCAh 37 Maskable 0FFC8h 36 0FFC6h 35 Reserved (5) Reserved (5) (4) (1) SYSTEM INTERRUPT ⋮ ⋮ 0FF80h 0, lowest Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain compatibility with other devices, TI recommends reserving these locations. 6.7 Special Function Registers (SFRs) The SFRs are in the lowest address space and can be accessed in word or byte formats. Legend rw rw-0, rw-1 rw-(0), rw-(1) rw-[0], rw-[1] – Bit can be read and written. Bit can be read and written. It is reset or set by PUC. Bit can be read and written. It is reset or set by POR. Bit can be read and written. It is reset or set by BOR. SFR bit is not present in device. Figure 6-4. Interrupt Enable 1 Register 15 – 14 – 13 – 12 – 11 – 10 – 9 AUXSWNMIE rw-0 8 – 7 JMBOUTIE rw-0 6 JMBINIE rw-0 5 ACCVIE rw-0 4 NMIIE rw-0 3 VMAIE rw-0 2 – 1 OFIE rw-0 0 WDTIE rw-0 Table 6-4. Interrupt Enable 1 Register Description Bit Field Type Reset Description 9 AUXSWNMIE RW 0h Supply switched nonmaskable interrupt enable 7 JMBOUTIE RW 0h JTAG mailbox output interrupt enable 6 JMBINIE RW 0h JTAG mailbox input interrupt enable 5 ACCVIE RW 0h Flash access violation interrupt enable 4 NMIIE RW 0h Nonmaskable interrupt enable 3 VMAIE RW 0h Vacant memory access interrupt enable 1 OFIE RW 0h Oscillator fault interrupt enable 0 WDTIE RW 0h Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured as a general-purpose timer. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 71 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Figure 6-5. Interrupt Flag 1 Register 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 JMBOUTIFG rw-[0] 6 JMBINIFG rw-[0] 5 – 4 NMIIFG rw-0 3 VMAIFG rw-0 2 – 1 OFIFG rw-0 0 WDTIFG rw-0 Table 6-5. Interrupt Flag 1 Register Description Bit 6.8 Field Type Reset Description 7 JMBOUTIFG RW 0h Set on JTAG mailbox output register ready for next message 6 JMBINIFG RW 0h Set on JTAG mailbox input message 4 NMIIFG RW 0h Set by RST/NMI pin 3 VMAIFG RW 0h Set on vacant memory access 1 OFIFG RW 0h Flag set on oscillator fault 0 WDTIFG RW 0h Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode. Bootloader (BSL) The BSL enables users to program the flash memory or RAM using various serial interfaces.Table 6-6 lists the BSL interface pin requirements. Access to the device memory by the BSL is protected by an userdefined password. BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For a complete description of the features of the BSL and its implementation, see the MSP430™ Flash Device Bootloader (BSL) User's Guide. Table 6-6. UART BSL Pin Requirements and Functions 72 Detailed Description DEVICE SIGNAL BSL FUNCTION RST/NMI/SBWTDIO Entry sequence signal TEST/SBWTCK Entry sequence signal P2.0 Data transmit P2.1 Data receive DVCC Power supply DVSS Ground supply Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com 6.9 6.9.1 SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 JTAG Operation JTAG Standard Interface The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430 development tools and device programmers. Table 6-7 lists the JTAG interface pin requirements. For further details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide. For a complete description of the features of the JTAG interface and its implementation, see MSP430 Programming With the JTAG Interface. Table 6-7. JTAG Pin Requirements and Functions 6.9.2 DEVICE SIGNAL DIRECTION FUNCTION PJ.3/TCK IN JTAG clock input PJ.2/TMS IN JTAG state control PJ.1/TDI/TCLK IN JTAG data input, TCLK input PJ.0/TDO OUT JTAG data output TEST/SBWTCK IN Enable JTAG pins RST/NMI/SBWTDIO IN External reset DVCC Power supply DVSS Ground supply Spy-Bi-Wire Interface In addition to the standard JTAG interface, the MSP430 family supports the 2-wire Spy-Bi-Wire interface. Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. Table 6-8 lists the Spy-Bi-Wire interface pin requirements. For further details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide. For a complete description of the features of the JTAG interface and its implementation, see MSP430 Programming With the JTAG Interface. Table 6-8. Spy-Bi-Wire Pin Requirements and Functions DEVICE SIGNAL DIRECTION FUNCTION TEST/SBWTCK IN Spy-Bi-Wire clock input RST/NMI/SBWTDIO IN, OUT Spy-Bi-Wire data input and output DVCC Power supply DVSS Ground supply Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 73 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com 6.10 Memory 6.10.1 Memory Organization Table 6-9 summarizes the memory map of the MSP430F67x9A, MSP430F67x8A, and MSP430F67x7A devices. Table 6-9. Memory Organization – MSP430F67x9A, MSP430F67x8A, and MSP430F67x7A MSP430F6779A MSP430F6769A MSP430F6749A MSP430F6778A MSP430F6768A MSP430F6748A MSP430F6777A MSP430F6767A MSP430F6747A 512KB 512KB 256KB Main: interrupt vector 00FFFFh to 00FF80h 00FFFFh to 00FF80h 00FFFFh to 00FF80h Main: code memory Bank 3 128KB 08BFFFh to 06C000h 128KB 08BFFFh to 06C000h Not available Bank 2 128KB 06BFFFh to 04C000h 128KB 06BFFFh to 04C000h Not available Bank 1 128KB 04BFFFh to 02C000h 128KB 04BFFFh to 02C000h 128KB 04BFFFh to 02C000h Bank 0 128KB 02BFFFh to 00C000h 128KB 02BFFFh to 00C000h 128KB 02BFFFh to 00C000h 32KB 16KB 32KB Sector 7 4KB 009BFFh to 008C00h Not available 4KB 009BFFh to 008C00h Sector 6 4KB 008BFFh to 007C00h Not available 4KB 008BFFh to 007C00h Sector 5 4KB 007BFFh to 006C00h Not available 4KB 007BFFh to 006C00h Sector 4 4KB 006BFFh to 005C00h Not available 4KB 006BFFh to 005C00h Sector 3 4KB 005BFFh to 004C00h 4KB 005BFFh to 004C00h 4KB 005BFFh to 004C00h Sector 2 4KB 004BFFh to 003C00h 4KB 004BFFh to 003C00h 4KB 004BFFh to 003C00h Sector 1 4KB 003BFFh to 002C00h 4KB 003BFFh to 002C00h 4KB 003BFFh to 002C00h Sector 0 4KB 002BFFh to 001C00h 4KB 002BFFh to 001C00h 4KB 002BFFh to 001C00h 128 B 001AFFh to 001A80h 128 B 001AFFh to 001A80h 128 B 001AFFh to 001A80h 128 B 001A7Fh to 001A00h 128 B 001A7Fh to 001A00h 128 B 001A7Fh to 001A00h Info A 128 B 0019FFh to 001980h 128 B 0019FFh to 001980h 128 B 0019FFh to 001980h Info B 128 B 00197Fh to 001900h 128 B 00197Fh to 001900h 128 B 00197Fh to 001900h Info C 128 B 0018FFh to 001880h 128 B 0018FFh to 001880h 128 B 0018FFh to 001880h Info D 128 B 00187Fh to 001800h 128 B 00187Fh to 001800h 128 B 00187Fh to 001800h BSL 3 512 B 0017FFh to 001600h 512 B 0017FFh to 001600h 512 B 0017FFh to 001600h BSL 2 512 B 0015FFh to 001400h 512 B 0015FFh to 001400h 512 B 0015FFh to 001400h BSL 1 512 B 0013FFh to 001200h 512 B 0013FFh to 001200h 512 B 0013FFh to 001200h BSL 0 512 B 0011FFh to 001000h 512 B 0011FFh to 001000h 512 B 0011FFh to 001000h Main memory (flash) RAM Total Size Total Size Device descriptor Information memory (flash) Bootloader (BSL) memory (flash) 74 Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 6-9. Memory Organization – MSP430F67x9A, MSP430F67x8A, and MSP430F67x7A (continued) Peripherals MSP430F6779A MSP430F6769A MSP430F6749A MSP430F6778A MSP430F6768A MSP430F6748A MSP430F6777A MSP430F6767A MSP430F6747A 4KB 000FFFh to 0h 4KB 000FFFh to 0h 4KB 000FFFh to 0h Table 6-10 summarizes the memory map of the MSP430F67x6A and MSP430F67x5A devices. Table 6-10. Memory Organization – MSP430F67x6A and MSP430F67x5A Main memory (flash) Total Size Main: interrupt vector Main: code memory 256KB 128KB 00FFFFh to 00FF80h 00FFFFh to 00FF80h Not available Not available Bank 2 Not available Not available Bank 1 128KB 04BFFFh to 02C000h Not available Bank 0 128KB 02BFFFh to 00C000h 128KB 02BFFFh to 00C000h 16KB 16KB Sector 7 Not available Not available Sector 6 Not available Not available Sector 5 Not available Not available Sector 4 Not available Not available Sector 3 4KB 005BFFh to 004C00h 4KB 005BFFh to 004C00h Sector 2 4KB 004BFFh to 003C00h 4KB 004BFFh to 003C00h Sector 1 4KB 003BFFh to 002C00h 4KB 003BFFh to 002C00h Sector 0 4KB 002BFFh to 001C00h 4KB 002BFFh to 001C00h 128 B 001AFFh to 001A80h 128 B 001AFFh to 001A80h 128 B 001A7Fh to 001A00h 128 B 001A7Fh to 001A00h Info A 128 B 0019FFh to 001980h 128 B 0019FFh to 001980h Info B 128 B 00197Fh to 001900h 128 B 00197Fh to 001900h Info C 128 B 0018FFh to 001880h 128 B 0018FFh to 001880h Info D 128 B 00187Fh to 001800h 128 B 00187Fh to 001800h BSL 3 512 B 0017FFh to 001600h 512 B 0017FFh to 001600h BSL 2 512 B 0015FFh to 001400h 512 B 0015FFh to 001400h BSL 1 512 B 0013FFh to 001200h 512 B 0013FFh to 001200h BSL 0 512 B 0011FFh to 001000h 512 B 0011FFh to 001000h 4KB 000FFFh to 0h 4KB 000FFFh to 0h Device descriptor Information memory (flash) Bootloader (BSL) memory (flash) MSP430F6775A MSP430F6765A MSP430F6745A Bank 3 Total Size RAM MSP430F6776A MSP430F6766A MSP430F6746A Peripherals Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 75 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com 6.10.2 Flash Memory (Link to User's Guide) The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the flash memory include: • Flash memory has n segments of main memory and four segments of information memory (A to D) of 128 bytes each. Each segment in main memory is 512 bytes in size. • Segments 0 to n may be erased in one step, or each segment may be individually erased. • Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also called information memory. • Segment A can be locked separately. 6.10.3 RAM (Link to User's Guide) The RAM is made up of n sectors. Each sector can be completely powered down to save leakage; however, all data are lost in the sector that is powered down. Features of the RAM include: • RAM has n sectors of 4KB each. • Each sector 0 to n can be completely disabled; however, data retention is lost in the disabled sector. • Each sector 0 to n automatically enters low-power retention mode when possible. 6.10.4 Backup RAM (Link to User's Guide) The backup RAM provides a limited number of bytes of RAM that are retained during LPM3.5. This backup RAM is part of the backup subsystem that operates on dedicated power supply AUXVCC3. Eight bytes of backup RAM are available in this device. The backup RAM can be word-wise accessed using the registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3. The backup RAM registers cannot be accessed by CPU when the high-side SVS is disabled by the user application. 76 Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 6.11 Peripherals Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be controlled using all instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx Family User's Guide. 6.11.1 Oscillator and System Clock (Link to User's Guide) The Unified Clock System (UCS) module includes support for a 32768-Hz watch crystal oscillator, an internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), and an integrated internal digitally controlled oscillator (DCO). The UCS module is designed to meet the requirements of both low system cost and low power consumption. The UCS module features digital frequency-locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the selected FLL reference frequency. The internal DCO provides a fast turnon clock source and stabilizes in less than 5 µs. The UCS module provides the following clock signals: • Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, the internal low-frequency oscillator (VLO), or the trimmed low-frequency oscillator (REFO). • Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made available to ACLK. • Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by same sources made available to ACLK. • ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32. 6.11.2 Power-Management Module (PMM) (Link to User's Guide) The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor (SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. The SVS and SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not automatically reset). SVS and SVM circuitry is available on the primary supply and core supply. 6.11.3 Auxiliary-Supply System (Link to User's Guide) The auxiliary supply system provides the option to operate the device from auxiliary supplies when the primary supply fails. There are two auxiliary supplies (AUXVCC1 and AUXVCC2) supported in MSP430F67xx. This module supports automatic and manual switching from primary supply to auxiliary supplies while maintaining full functionality. The auxiliary supply system allows threshold-based monitoring of primary and auxiliary supplies. The device can be started from primary supply or AUXVCC1, whichever is higher. Auxiliary supply system enables internal monitoring of voltage levels on primary and auxiliary supplies using ADC10_A. This module also implements a simple charger for backup capacitors. 6.11.4 Backup Subsystem The backup subsystem operates on a dedicated power supply AUXVCC3. This subsystem includes lowfrequency oscillator, real-time clock module, and backup RAM. The functionality of the backup subsystem is retained during LPM3.5. The backup subsystem module registers cannot be accessed by CPU when the high-side SVS is disabled by user. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 77 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com 6.11.5 Digital I/O (Link to User's Guide) Up to eleven 8-bit I/O ports are implemented. For 128-pin options, ports P1 to P10 are complete, and port P11 is 6 bits wide. For 100-pin options, ports P1 to P7 are complete, port P8 is 2 bits wide, and ports P9, P10, and P11 are completely removed. Port PJ contains four individual I/O pins, common to all devices. All I/O bits are individually programmable. • Any combination of input, output, and interrupt conditions is possible. • Programmable pullup or pulldown on all ports. • Programmable drive strength on all ports. • Edge-selectable interrupt and LPM3.5, LPM4.5 wake-up input capability available for all bits of ports P1 and P2. • Read-write access to port-control registers is supported by all instructions. • Ports can be accessed byte-wise (P1 to P11) or word-wise in pairs (PA to PF). 6.11.6 Port Mapping Controller (Link to User's Guide) The port mapping controller allows flexible and reconfigurable mapping of digital functions to ports P2, P3, and P4 (see Table 6-11). Table 6-12 lists the default settings for all pins that support port mapping. Table 6-11. Port Mapping Mnemonics and Functions VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION 0 PM_NONE None DVSS 1 2 eUSCI_A0 UART RXD (direction controlled by eUSCI – Input) PM_UCA0SOMI eUSCI_A0 SPI slave out master in (direction controlled by eUSCI) PM_UCA0TXD eUSCI_A0 UART TXD (direction controlled by eUSCI – Output) PM_UCA0SIMO eUSCI_A0 SPI slave in master out (direction controlled by eUSCI) 3 PM_UCA0CLK eUSCI_A0 clock input/output (direction controlled by eUSCI) 4 PM_UCA0STE eUSCI_A0 SPI slave transmit enable (direction controlled by eUSCI) 5 6 PM_UCA1RXD eUSCI_A1 UART RXD (direction controlled by eUSCI – Input) PM_UCA1SOMI eUSCI_A1 SPI slave out master in (direction controlled by eUSCI) PM_UCA1TXD eUSCI_A1 UART TXD (direction controlled by eUSCI – Output) PM_UCA1SIMO eUSCI_A1 SPI slave in master out (direction controlled by eUSCI) 7 PM_UCA1CLK eUSCI_A1 clock input/output (direction controlled by eUSCI) 8 PM_UCA1STE eUSCI_A1 SPI slave transmit enable (direction controlled by eUSCI) 9 10 PM_UCA2RXD eUSCI_A2 UART RXD (direction controlled by eUSCI – Input) PM_UCA2SOMI eUSCI_A2 SPI slave out master in (direction controlled by eUSCI) PM_UCA2TXD eUSCI_A2 UART TXD (direction controlled by eUSCI – Output) PM_ UCA2SIMO eUSCI_A2 SPI slave in master out (direction controlled by eUSCI) 11 PM_UCA2CLK eUSCI_A2 clock input/output (direction controlled by eUSCI) 12 PM_UCA2STE eUSCI_A2 SPI slave transmit enable (direction controlled by eUSCI) 13 14 PM_UCA3RXD eUSCI_A3 UART RXD (direction controlled by eUSCI – Input) PM_UCA3SOMI eUSCI_A3 SPI slave out master in (direction controlled by eUSCI) PM_UCA3TXD eUSCI_A3 UART TXD (direction controlled by eUSCI – Output) PM_ UCA3SIMO eUSCI_A3 SPI slave in master out (direction controlled by eUSCI) 15 PM_UCA3CLK eUSCI_A3 clock input/output (direction controlled by eUSCI) 16 PM_UCA3STE eUSCI_A3 SPI slave transmit enable (direction controlled by eUSCI) 17 18 78 PM_UCA0RXD PM_UCB0SIMO eUSCI_B0 SPI slave in master out (direction controlled by eUSCI) PM_UCB0SDA eUSCI_B0 I2C data (open drain and direction controlled by eUSCI) PM_UCB0SOMI eUSCI_B0 SPI slave out master in (direction controlled by eUSCI) PM_UCB0SCL eUSCI_B0 I2C clock (open drain and direction controlled by eUSCI) 19 PM_UCB0CLK eUSCI_B0 clock input/output (direction controlled by eUSCI) 20 PM_UCB0STE eUSCI_B0 SPI slave transmit enable (direction controlled by eUSCI) Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 6-11. Port Mapping Mnemonics and Functions (continued) VALUE PxMAPy MNEMONIC 21 22 OUTPUT PIN FUNCTION eUSCI_B1 SPI slave in master out (direction controlled by eUSCI) PM_UCB1SDA eUSCI_B1 I2C data (open drain and direction controlled by eUSCI) PM_UCB1SOMI eUSCI_B1 SPI slave out master in (direction controlled by eUSCI) PM_UCB1SCL eUSCI_B1 I2C clock (open drain and direction controlled by eUSCI) 23 PM_UCB1CLK eUSCI_B1 clock input/output (direction controlled by eUSCI) 24 PM_UCB1STE eUSCI_B1 SPI slave transmit enable (direction controlled by eUSCI) 25 PM_TA0.0 TA0 CCR0 capture input CCI0A TA0 CCR0 compare output Out0 26 PM_TA0.1 TA0 CCR1 capture input CCI1A TA0 CCR1 compare output Out1 27 PM_TA0.2 TA0 CCR2 capture input CCI2A TA0 CCR2 compare output Out2 28 PM_TA1.0 TA1 CCR0 capture input CCI0A TA1 CCR0 compare output Out0 29 PM_TA2.0 TA2 CCR0 capture input CCI0A TA2 CCR0 compare output Out0 30 PM_TA3.0 TA3 CCR0 capture input CCI0A TA3 CCR0 compare output Out0 31 (0FFh) (1) INPUT PIN FUNCTION PM_UCB1SIMO (1) Disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. PM_ANALOG The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide, and the upper bits are ignored, which results in a read value of 31. Table 6-12. Default Port Mapping PIN NAME PEU PZ PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION P2.0/PM_TA0.0 P2.0/PM_TA0.0/COM4 PM_TA0.0 TA0 CCR0 capture input CCI0A TA0 CCR0 compare output Out0 P2.1/PM_TA0.1 P2.1/PM_TA0.1/COM5 PM_TA0.1 TA0 CCR1 capture input CCI1A TA0 CCR1 compare output Out1 P2.2/PM_TA0.2 P2.2/PM_TA0.2/COM6 PM_TA0.2 TA0 CCR2 capture input CCI2A TA0 CCR2 compare output Out2 P2.3/PM_TA1.0 P2.3/PM_TA1.0/COM7 PM_TA1.0 TA1 CCR0 capture input CCI0A TA1 CCR0 compare output Out0 P2.4/PM_TA2.0 P1.1/PM_TA2.0/R23 PM_TA2.0 TA2 CCR0 capture input CCI0A TA2 CCR0 compare output Out0 P2.5/PM_UCB0SOMI/ PM_UCB0SCL P2.0/PM_UCB0SOMI/ PM_UCB0SCL/R13 PM_UCB0SOMI/ PM_UCB0SCL eUSCI_B0 SPI slave out master in (direction controlled by eUSCI), eUSCI_B0 I2C clock (open drain and direction controlled by eUSCI) P2.6/PM_UCB0SIMO/ PM_UCB0SDA P2.6/PM_UCB0SIMO/ PM_UCB0SDA/R03 PM_UCB0SIMO/ PM_UCB0SDA eUSCI_B0 SPI slave in master out (direction controlled by eUSCI), eUSCI_B0 I2C data (open drain and direction controlled by eUSCI) P2.7/PM_UCB0CLK P2.7/PM_UCB0CLK/CB2 PM_UCB0CLK eUSCI_B0 clock input/output (direction controlled by eUSCI) P3.0/PM_UCA0RXD/ PM_UCA0SOMI P3.0/PM_UCA0RXD/ PM_UCA0SOMI PM_UCA0RXD/ PM_UCA0SOMI eUSCI_A0 UART RXD (direction controlled by eUSCI – input), eUSCI_A0 SPI slave out master in (direction controlled by eUSCI) P3.1/PM_UCA0TXD/ PM_UCA0SIMO P3.1/PM_UCA0TXD/ PM_UCA0SIMO/S39 PM_UCA0TXD/ PM_UCA0SIMO eUSCI_A0 UART TXD (direction controlled by eUSCI – output), eUSCI_A0 SPI slave in master out (direction controlled by eUSCI) P3.2/PM_UCA0CLK P3.2/PM_UCA0CLK/S38 PM_UCA0CLK eUSCI_A0 clock input/output (direction controlled by eUSCI) P3.3/PM_UCA1CLK P3.3/PM_UCA1CLK/S37 PM_UCA1CLK eUSCI_A1 clock input/output (direction controlled by eUSCI) P3.4/PM_UCA1RXD/ PM_UCA1SOMI/ P3.4/PM_UCA1RXD/ PM_UCA1SOMI/S36 PM_UCA1RXD/ PM_UCA1SOMI eUSCI_A1 UART RXD (direction controlled by eUSCI – input), eUSCI_A1 SPI slave out master in (direction controlled by eUSCI) P3.5/PM_UCA1TXD/ PM_UCA1SIMO P3.5/PM_UCA1TXD/ PM_UCA1SIMO/S35 PM_UCA1TXD/ PM_UCA1SIMO eUSCI_A1 UART TXD (direction controlled by eUSCI – output), eUSCI_A1 SPI slave in master out (direction controlled by eUSCI) P3.6/PM_UCA2RXD/ PM_UCA2SOMI/ P3.6/PM_UCA2RXD/ PM_UCA2SOMI/S34 PM_UCA2RXD/ PM_UCA2SOMI eUSCI_A2 UART RXD (direction controlled by eUSCI – input), eUSCI_A2 SPI slave out master in (direction controlled by eUSCI) P3.7/PM_UCA2TXD/ PM_UCA2SIMO P3.7/PM_UCA2TXD/ PM_UCA2SIMO/S33 PM_UCA2TXD/ PM_UCA2SIMO eUSCI_A2 UART TXD (direction controlled by eUSCI – output), eUSCI_A2 SPI slave in master out (direction controlled by eUSCI) P4.0/PM_UCA2CLK P4.0/PM_UCA2CLK/S32 PM_UCA2CLK eUSCI_A2 clock input/output (direction controlled by eUSCI) P4.1/PM_UCA3RXD/ PM_UCA3SOMI/ P4.1/PM_UCA3RXD/ PM_UCA3SOMI/S31 PM_UCA3RXD/ PM_UCA3SOMI eUSCI_A3 UART RXD (direction controlled by eUSCI – input), eUSCI_A3 SPI slave out master in (direction controlled by eUSCI) P4.2/PM_UCA3TXD/ PM_UCA3SIMO P4.2/PM_UCA3TXD/ PM_UCA3SIMO/S30 PM_UCA3TXD/ PM_UCA3SIMO eUSCI_A3 UART TXD (direction controlled by eUSCI – output), eUSCI_A3 SPI slave in master out (direction controlled by eUSCI) P4.3/PM_UCA3CLK P4.3/PM_UCA3CLK/S29 PM_UCA3CLK eUSCI_A3 clock input/output (direction controlled by eUSCI) P4.4/PM_UCB1SOMI/ PM_UCB1SCL P4.4/PM_UCB1SOMI/ PM_UCB1SCL/S28 PM_UCB1SOMI/ PM_UCB1SCL eUSCI_B1 SPI slave out master in (direction controlled by eUSCI), eUSCI_B1 I2C clock (open drain and direction controlled by eUSCI) P4.5/PM_UCB1SIMO/ PM_UCB1SDA P4.5/PM_UCB1SIMO/ PM_UCB1SDA/S27 PM_UCB1SIMO/ PM_UCB1SDA eUSCI_B1 SPI slave in master out (direction controlled by eUSCI), eUSCI_B1 I2C data (open drain and direction controlled by eUSCI) P4.6/PM_UCB1CLK P4.6/PM_UCB1CLK/S26 P4.7/PM_TA3.0 P4.7/PM_TA3.0/S25 PM_UCB1CLK PM_TA3.0 eUSCI_B1 clock input/output (direction controlled by eUSCI) TA3 CCR0 capture input CCI0A TA3 CCR0 compare output Out0 Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 79 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com 6.11.7 System Module (SYS) (Link to User's Guide) The SYS module handles many of the system functions within the device. These include power-on reset (POR) and power-up clear (PUC) handling, NMI source selection and management, reset interrupt vector generators, bootloader entry mechanisms, and configuration management (device descriptors). The SYS module also includes a data exchange mechanism using JTAG called a JTAG mailbox that can be used in the application. Table 6-13 lists the SYS module interrupt vector registers. Table 6-13. System Module Interrupt Vector Registers INTERRUPT VECTOR REGISTER SYSRSTIV, System Reset SYSSNIV, System NMI SYSUNIV, User NMI ADDRESS 019Eh 019Ch 019Ah INTERRUPT EVENT VALUE No interrupt pending 00h Brownout (BOR) 02h RST/NMI (POR) 04h DoBOR (BOR) 06h Wake up from LPMx.5 08h Security violation (BOR) 0Ah SVSL (POR) 0Ch SVSH (POR) 0Eh SVML_OVP (POR) 10h SVMH_OVP (POR) 12h DoPOR (POR) 14h WDT time-out (PUC) 16h WDT key violation (PUC) 18h KEYV flash key violation (PUC) 1Ah Reserved 1Ch Peripheral area fetch (PUC) 1Eh PMM key violation (PUC) 20h Reserved 22h to 3Eh No interrupt pending 00h SVMLIFG 02h SVMHIFG 04h DLYLIFG 06h DLYHIFG 08h VMAIFG 0Ah JMBINIFG 0Ch JMBOUTIFG 0Eh VLRLIFG 10h VLRHIFG 12h Reserved 14h to 1Eh No interrupt pending 00h NMIIFG 02h OFIFG 04h ACCVIFG 06h AUXSWGIFG 08h Reserved 0Ah to 1Eh PRIORITY Highest Lowest Highest Lowest Highest Lowest 6.11.8 Watchdog Timer (WDT_A) (Link to User's Guide) The primary function of the WDT_A is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the timer can be configured as an interval timer and can generate interrupts at selected time intervals. 80 Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 6.11.9 DMA Controller (Link to User's Guide) The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC10_A conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or from a peripheral. Table 6-14 lists the available DMA triggers. Table 6-14. DMA Trigger Assignments (1) TRIGGER (1) CHANNEL 0 1 2 0 DMAREQ DMAREQ DMAREQ 1 TA0CCR0 CCIFG TA0CCR0 CCIFG TA0CCR0 CCIFG 2 TA0CCR2 CCIFG TA0CCR2 CCIFG TA0CCR2 CCIFG 3 TA1CCR0 CCIFG TA1CCR0 CCIFG TA1CCR0 CCIFG 4 Reserved Reserved Reserved 5 TA2CCR0 CCIFG TA2CCR0 CCIFG TA2CCR0 CCIFG 6 Reserved Reserved Reserved 7 TA3CCR0 CCIFG TA3CCR0 CCIFG TA3CCR0 CCIFG 8 Reserved Reserved Reserved 9 Reserved Reserved Reserved 10 Reserved Reserved Reserved 11 Reserved Reserved Reserved 12 Reserved Reserved Reserved 13 SD24IFG SD24IFG SD24IFG 14 Reserved Reserved Reserved 15 Reserved Reserved Reserved 16 UCA0RXIFG UCA0RXIFG UCA0RXIFG 17 UCA0TXIFG UCA0TXIFG UCA0TXIFG 18 UCA1RXIFG UCA1RXIFG UCA1RXIFG 19 UCA1TXIFG UCA1TXIFG UCA1TXIFG 20 UCA2RXIFG UCA2RXIFG UCA2RXIFG 21 UCA2TXIFG UCA2TXIFG UCA2TXIFG 22 UCB0RXIFG0 UCB0RXIFG0 UCB0RXIFG0 23 UCB0TXIFG0 UCB0TXIFG0 UCB0TXIFG0 24 ADC10IFG0 ADC10IFG0 ADC10IFG0 25 UCA3RXIFG UCA3RXIFG UCA3RXIFG 26 UCA3TXIFG UCA3TXIFG UCA3TXIFG 27 UCB1RXIFG0 UCB1RXIFG0 UCB1RXIFG0 28 UCB1TXIFG0 UCB1TXIFG0 UCB1TXIFG0 29 MPY ready MPY ready MPY ready 30 DMA2IFG DMA0IFG DMA1IFG 31 Reserved Reserved Reserved Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers do not cause any DMA trigger event when selected. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 81 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com 6.11.10 CRC16 (Link to User's Guide) The CRC16 module produces a signature based on a sequence of entered data values and can be used for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard. 6.11.11 Hardware Multiplier (Link to User's Guide) The multiplication operation is supported by a dedicated peripheral module. The module performs operations with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication as well as signed and unsigned multiply-and-accumulate operations. 6.11.12 AES128 Accelerator (Link to User's Guide) The AES accelerator module performs encryption and decryption of 128-bit data with 128-bit keys according to the Advanced Encryption Standard (AES) (FIPS PUB 197) in hardware. 6.11.13 Enhanced Universal Serial Communication Interface (eUSCI) (Links to User's Guide: UART Mode, SPI Mode, I2C Mode) The eUSCI module is used for serial data communication. The eUSCI module supports synchronous communication protocols such as SPI (3- or 4-pin) and I2C, and asynchronous communication protocols such as UART, enhanced UART with automatic baud-rate detection, and IrDA. The eUSCI_An module provides support for SPI (3- or 4-pin), UART, enhanced UART, and IrDA. The eUSCI_Bn module provides support for SPI (3- or 4-pin) and I2C. Four eUSCI_A and two eUSCI_B module are implemented in the MSP430F67xxA MCUs. 6.11.14 ADC10_A (Link to User's Guide) The ADC10_A module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core, sample select control, reference generator and a conversion results buffer. A window comparator with a lower and upper limit allows CPU independent result monitoring with three window comparator interrupt flags. 6.11.15 SD24_B (Link to User's Guide) The SD24_B module integrates up to seven independent 24-bit sigma-delta ADCs. Each converter is designed with a fully differential analog input pair and programmable gain amplifier input stage. Also the converters are based on second-order oversampling sigma-delta modulators and digital decimation filters. The decimation filters are comb filters with selectable oversampling ratios of up to 1024. 82 Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 6.11.16 TA0 (Link to User's Guide) TA0 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA0 can support multiple capture/compares, PWM outputs, and interval timing (see Table 6-15). TA0 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 6-15. TA0 Signal Connections DEVICE INPUT SIGNAL MODULE INPUT NAME PM_TACLK TACLK ACLK (internal) ACLK SMCLK (internal) SMCLK PM_TACLK INCLK MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL Timer NA NA PM_TA0.0 CCI0A CBOUT (internal) CCI0B PM_TA0.0 DVSS GND DVCC VCC PM_TA0.1 CCI1A PM_TA0.1 ACLK (internal) CCI1B ADC10_A (internal) ADC10SHSx = 001b DVSS GND CCR0 TA0 CCR1 DVCC VCC PM_TA0.2 CCI2A DVSS CCI2B DVSS GND DVCC VCC TA1 SD24_B (internal) SD24CHx.SD24SCSx = 001b PM_TA0.2 CCR2 TA2 6.11.17 TA1 (Link to User's Guide) TA1 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers (see Table 6-16). TA1 can support multiple capture/compares, PWM outputs, and interval timing. TA1 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 6-16. TA1 Signal Connections DEVICE INPUT SIGNAL MODULE INPUT NAME PM_TACLK TACLK ACLK (internal) ACLK SMCLK (internal) SMCLK PM_TACLK INCLK PM_TA1.0 CCI0A CBOUT (internal) CCI0B DVSS GND DVCC VCC PM_TA1.1 CCI1A ACLK (internal) CCI1B DVSS GND DVCC VCC MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL Timer NA NA PM_TA1.0 CCR0 TA0 PM_TA1.1 CCR1 TA1 Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 83 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com 6.11.18 TA2 (Link to User's Guide) TA2 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers. TA2 can support multiple capture/compares, PWM outputs, and interval timing (see Table 6-17). TA2 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 6-17. TA2 Signal Connections DEVICE INPUT SIGNAL MODULE INPUT NAME PM_TACLK TACLK ACLK (internal) ACLK SMCLK (internal) SMCLK PM_TACLK INCLK MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL Timer NA NA PM_TA2.0 CCI0A CBOUT (internal) CCI0B PM_TA2.0 DVSS GND DVCC VCC PM_TA2.1 CCI1A PM_TA2.1 ACLK (internal) CCI1B SD24_B (internal) SD24CHx.SD24SCSx = 010b DVSS GND DVCC VCC CCR0 CCR1 TA0 TA1 6.11.19 TA3 (Link to User's Guide) TA3 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers. TA3 can support multiple capture/compares, PWM outputs, and interval timing (see Table 6-18). TA3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 6-18. TA3 Signal Connections 84 DEVICE INPUT SIGNAL MODULE INPUT NAME PM_TACLK TACLK MODULE BLOCK MODULE OUTPUT SIGNAL Timer NA DEVICE OUTPUT SIGNAL ACLK (internal) ACLK SMCLK (internal) SMCLK PM_TACLK INCLK PM_TA3.0 CCI0A PM_TA3.0 CBOUT (internal) CCI0B TA0 ADC10_A (internal) ADC10SHSx = 010b DVSS GND TA1 CCR0 DVCC VCC PM_TA3.1 CCI1A PM_TA3.1 ACLK (internal) CCI1B SD24_B (internal) SD24CHx.SD24SCSx = 011b DVSS GND DVCC VCC Detailed Description CCR1 Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 6.11.20 SD24_B Triggers Table 6-19 lists the input trigger connections to SD24_B converters from Timer_A modules and output trigger pulse connection from SD24_B to ADC10_A. Table 6-19. SD24_B Input/Output Trigger Connections DEVICE INPUT SIGNAL MODULE INPUT SIGNAL MODULE BLOCK TA0.1 (internal) SD24_B SD24CHx.SD24SCSx = 001b TA2.1 (internal) SD24_B SD24CHx.SD24SCSx = 010b TA3.1 (internal) SD24_B SD24CHx.SD24SCSx = 011b MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL Trigger Pulse ADC10_A (internal) ADC10SHSx = 011b SD24_B 6.11.21 ADC10_A Triggers Table 6-20 lists the input trigger connections to ADC10_A from Timer_A modules and SD24_B. Table 6-20. ADC10_A Input Trigger Connections DEVICE INPUT SIGNAL MODULE INPUT SIGNAL TA0.1 (internal) ADC10_A ADC10SHSx = 001b TA3.0 (internal) ADC10_A ADC10SHSx = 010b SD24_B trigger pulse (internal) ADC10_A ADC10SHSx = 011b MODULE BLOCK ADC10_A 6.11.22 Real-Time Clock (RTC_C) (Link to User's Guide) The RTC_C module can be configured for calendar mode providing seconds, hours, day of week, day of month, month, and year. The RTC_C control and configuration registers are password protected to ensure clock integrity against runaway code. Calendar mode integrates an internal calendar that compensates for months with less than 31 days and includes leap year correction. The RTC_C also supports flexible alarm functions, offset calibration, temperature compensation, and time capture on two external events. The RTC_C on this device operates on dedicated AUXVCC3 supply and supports operation in LPM3.5. 6.11.23 Reference (REF) Module Voltage Reference (Link to User's Guide) The REF module generates all of the critical reference voltages that can be used by the various analog peripherals in the device. The analog peripherals include the ADC10_A, LCD_C, and SD24_B modules. 6.11.24 LCD_C (Link to User's Guide) The LCD_C driver generates the segment and common signals required to drive a liquid crystal display (LCD). The LCD_C controller has dedicated data memories to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2-mux, 3-mux, 4-mux, up to 8-mux LCDs are supported. The module can provide a LCD voltage independent of the supply voltage with its integrated charge pump. It is possible to control the level of the LCD voltage, and thus contrast, by software. The module also provides an automatic blinking capability for individual segments in static, 2mux, 3-mux, and 4-mux modes. 6.11.25 Comparator_B (Link to User's Guide) The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions, battery voltage supervision, and monitoring of external analog signals. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 85 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com 6.11.26 Embedded Emulation Module (EEM) (Link to User's Guide) The EEM supports real-time in-system debugging. The L version of the EEM has the following features: • Eight hardware triggers or breakpoints on memory access • Two hardware triggers or breakpoints on CPU register write access • Up to 10 hardware triggers that can be combined to form complex triggers or breakpoints • Two cycle counters • Sequencer • State storage • Clock control on module level 6.11.27 Peripheral File Map Table 6-21 shows the base address for the registers of each supported peripheral. Table 6-22 through Table 6-64 show the offset addresses for each register. For complete description of these registers, see the MSP430x5xx and MSP430x6xx Family User's Guide. Table 6-21. Peripherals 86 MODULE NAME BASE ADDRESS OFFSET ADDRESS RANGE Special Functions (see Table 6-22) 0100h 000h to 01Fh PMM (see Table 6-23) 0120h 000h to 01Fh Flash Control (see Table 6-24) 0140h 000h to 00Fh CRC16 (see Table 6-25) 0150h 000h to 007h RAM Control (see Table 6-26) 0158h 000h to 001h Watchdog (see Table 6-27) 015Ch 000h to 001h UCS (see Table 6-28) 0160h 000h to 01Fh SYS (see Table 6-29) 0180h 000h to 01Fh Shared Reference (see Table 6-30) 01B0h 000h to 001h Port Mapping Control (see Table 6-31) 01C0h 000h to 007h Port Mapping Port P2 (see Table 6-32) 01D0h 000h to 007h Port Mapping Port P3 (see Table 6-33) 01D8h 000h to 007h Port Mapping Port P4 (see Table 6-34) 01E0h 000h to 007h Port P1, P2 (see Table 6-35) 0200h 000h to 01Fh Port P3, P4 (see Table 6-36) 0220h 000h to 00Bh Port P5, P6 (see Table 6-37) 0240h 000h to 00Bh Port P7, P8 (see Table 6-38) 0260h 000h to 00Bh Port P9, P10 (see Table 6-39) (Ports P9 and P10 not available in PZ package) 0280h 000h to 00Bh Port P11 (see Table 6-40) (Port P11 not available in PZ package) 02A0h 000h to 00Bh Port PJ (see Table 6-41) 0320h 000h to 01Fh Timer TA0 (see Table 6-42) 0340h 000h to 03Fh Timer TA1 (see Table 6-43) 0380h 000h to 03Fh Timer TA2 (see Table 6-44) 0400h 000h to 03Fh Timer TA3 (see Table 6-45) 0440h 000h to 03Fh Backup Memory (see Table 6-46) 0480h 000h to 00Fh 32-Bit Hardware Multiplier (see Table 6-48) 04C0h 000h to 02Fh DMA General Control (see Table 6-49) 0500h 000h to 00Fh DMA Channel 0 (see Table 6-50) 0500h 010h to 01Fh DMA Channel 1 (see Table 6-51) 0500h 020h to 02Fh Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 6-21. Peripherals (continued) BASE ADDRESS OFFSET ADDRESS RANGE DMA Channel 2 (see Table 6-52) 0500h 030h to 03Fh RTC_C (see Table 6-47) 0C80h 000h to 03Fh eUSCI_A0 (see Table 6-53) 05C0h 000h to 01Fh eUSCI_A1 (see Table 6-54) 05E0h 000h to 01Fh eUSCI_A2 (see Table 6-55) 0600h 000h to 01Fh eUSCI_A3 (see Table 6-56) 0620h 000h to 01Fh eUSCI_B0 (see Table 6-57) 0640h 000h to 02Fh eUSCI_B1 ( see Table 6-58 ) 0680h 000h to 02Fh ADC10_A (see Table 6-59) 0740h 000h to 01Fh SD24_B (see Table 6-60) 0800h 000h to 06Fh MODULE NAME Comparator_B (see Table 6-61 ) 08C0h 000h to 00Fh AES Accelerator (see Table 6-62) 09C0h 000h to 00Fh Auxiliary Supply (see Table 6-63) 09E0h 000h to 01Fh LCD_C (see Table 6-64) 0A00h 000h to 05Fh Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 87 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 6-22. Special Function Registers (Base Address: 0100h) REGISTER DESCRIPTION REGISTER OFFSET SFR interrupt enable SFRIE1 00h SFR interrupt flag SFRIFG1 02h SFR reset pin control SFRRPCR 04h Table 6-23. PMM Registers (Base Address: 0120h) REGISTER DESCRIPTION REGISTER OFFSET PMM control 0 PMMCTL0 00h PMM control 1 PMMCTL1 02h SVS high-side control SVSMHCTL 04h SVS low-side control SVSMLCTL 06h PMM interrupt flags PMMIFG 0Ch PMM interrupt enable PMMIE 0Eh PMM power mode 5 control 0 PM5CTL0 10h Table 6-24. Flash Control Registers (Base Address: 0140h) REGISTER DESCRIPTION REGISTER OFFSET Flash control 1 FCTL1 00h Flash control 3 FCTL3 04h Flash control 4 FCTL4 06h Table 6-25. CRC16 Registers (Base Address: 0150h) REGISTER DESCRIPTION REGISTER OFFSET CRC data input CRC16DI 00h CRC result CRCINIRES 04h Table 6-26. RAM Control Registers (Base Address: 0158h) REGISTER DESCRIPTION RAM control 0 REGISTER RCCTL0 OFFSET 00h Table 6-27. Watchdog Registers (Base Address: 015Ch) REGISTER DESCRIPTION Watchdog timer control REGISTER WDTCTL OFFSET 00h Table 6-28. UCS Registers (Base Address: 0160h) REGISTER DESCRIPTION REGISTER OFFSET UCS control 0 UCSCTL0 00h UCS control 1 UCSCTL1 02h UCS control 2 UCSCTL2 04h UCS control 3 UCSCTL3 06h UCS control 4 UCSCTL4 08h UCS control 5 UCSCTL5 0Ah UCS control 6 UCSCTL6 0Ch UCS control 7 UCSCTL7 0Eh UCS control 8 UCSCTL8 10h 88 Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 6-29. SYS Registers (Base Address: 0180h) REGISTER DESCRIPTION REGISTER OFFSET System control SYSCTL 00h Bootloader configuration area SYSBSLC 02h JTAG mailbox control SYSJMBC 06h JTAG mailbox input 0 SYSJMBI0 08h JTAG mailbox input 1 SYSJMBI1 0Ah JTAG mailbox output 0 SYSJMBO0 0Ch JTAG mailbox output 1 SYSJMBO1 0Eh Bus Error vector generator SYSBERRIV 18h User NMI vector generator SYSUNIV 1Ah System NMI vector generator SYSSNIV 1Ch Reset vector generator SYSRSTIV 1Eh Table 6-30. Shared Reference Registers (Base Address: 01B0h) REGISTER DESCRIPTION Shared reference control REGISTER REFCTL OFFSET 00h Table 6-31. Port Mapping Controller (Base Address: 01C0h) REGISTER DESCRIPTION REGISTER OFFSET Port mapping password PMAPPWD 00h Port mapping control PMAPCTL 02h Table 6-32. Port Mapping for Port P2 (Base Address: 01D0h) REGISTER DESCRIPTION REGISTER OFFSET Port P2.0 mapping P2MAP0 00h Port P2.1 mapping P2MAP1 01h Port P2.2 mapping P2MAP2 02h Port P2.3 mapping P2MAP3 03h Port P2.4 mapping P2MAP4 04h Port P2.5 mapping P2MAP5 05h Port P2.6 mapping P2MAP6 06h Port P2.7 mapping P2MAP7 07h Table 6-33. Port Mapping for Port P3 (Base Address: 01D8h) REGISTER DESCRIPTION REGISTER OFFSET Port P3.0 mapping P3MAP0 00h Port P3.1 mapping P3MAP1 01h Port P3.2 mapping P3MAP2 02h Port P3.3 mapping P3MAP3 03h Port P3.4 mapping P3MAP4 04h Port P3.5 mapping P3MAP5 05h Port P3.6 mapping P3MAP6 06h Port P3.7 mapping P3MAP7 07h Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 89 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 6-34. Port Mapping for Port P4 (Base Address: 01E0h) REGISTER DESCRIPTION REGISTER OFFSET Port P4.0 mapping P4MAP0 00h Port P4.1 mapping P4MAP1 01h Port P4.2 mapping P4MAP2 02h Port P4.3 mapping P4MAP3 03h Port P4.4 mapping P4MAP4 04h Port P4.5 mapping P4MAP5 05h Port P4.6 mapping P4MAP6 06h Port P4.7 mapping P4MAP7 07h Table 6-35. Port P1, P2 Registers (Base Address: 0200h) REGISTER DESCRIPTION REGISTER OFFSET Port P1 input P1IN 00h Port P1 output P1OUT 02h Port P1 direction P1DIR 04h Port P1 resistor enable P1REN 06h Port P1 drive strength P1DS 08h Port P1 selection 0 P1SEL0 0Ah Port P1 selection 1 P1SEL1 0Ch Port P1 interrupt vector word P1IV 0Eh Port P1 interrupt edge select P1IES 18h Port P1 interrupt enable P1IE 1Ah Port P1 interrupt flag P1IFG 1Ch Port P2 input P2IN 01h Port P2 output P2OUT 03h Port P2 direction P2DIR 05h Port P2 resistor enable P2REN 07h Port P2 drive strength P2DS 09h Port P2 selection 0 P2SEL0 0Bh Port P2 selection 1 (1) P2SEL1 0Dh Port P2 interrupt vector word P2IV 1Eh Port P2 interrupt edge select P2IES 19h Port P2 interrupt enable P2IE 1Bh Port P2 interrupt flag P2IFG 1Dh (1) 90 P2SEL1 is an empty control register to be consistent with P1SEL1 in 16-bit access. Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 6-36. Port P3, P4 Registers (Base Address: 0220h) REGISTER DESCRIPTION REGISTER OFFSET Port P3 input P3IN 00h Port P3 output P3OUT 02h Port P3 direction P3DIR 04h Port P3 resistor enable P3REN 06h Port P3 drive strength P3DS 08h Port P3 selection 0 P3SEL0 0Ah Port P4 input P4IN 01h Port P4 output P4OUT 03h Port P4 direction P4DIR 05h Port P4 resistor enable P4REN 07h Port P4 drive strength P4DS 09h Port P4 selection 0 P4SEL0 0Bh Table 6-37. Port P5, P6 Registers (Base Address: 0240h) REGISTER DESCRIPTION REGISTER OFFSET Port P5 input P5IN 00h Port P5 output P5OUT 02h Port P5 direction P5DIR 04h Port P5 resistor enable P5REN 06h Port P5 drive strength P5DS 08h Port P5 selection 0 P5SEL0 0Ah Port P5 selection 1 P5SEL1 0Ch Port P6 input P6IN 01h Port P6 output P6OUT 03h Port P6 direction P6DIR 05h Port P6 resistor enable P6REN 07h Port P6 drive strength P6DS 09h Port P6 selection 0 P6SEL0 0Bh Port P6 selection 1 (1) P6SEL1 0Dh (1) P6SEL1 is an empty control register to be consistent with P5SEL1 in 16-bit access. Table 6-38. Port P7, P8 Registers (Base Address: 0260h) REGISTER DESCRIPTION REGISTER OFFSET Port P7 input P7IN 00h Port P7 output P7OUT 02h Port P7 direction P7DIR 04h Port P7 resistor enable P7REN 06h Port P7 drive strength P7DS 08h Port P7 selection 0 P7SEL0 0Ah Port P8 input P8IN 01h Port P8 output P8OUT 03h Port P8 direction P8DIR 05h Port P8 resistor enable P8REN 07h Port P8 drive strength P8DS 09h Port P8 selection 0 P8SEL0 0Bh Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 91 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 6-39. Port P9, P10 Registers (Base Address: 0280h) REGISTER DESCRIPTION REGISTER OFFSET Port P9 input P9IN 00h Port P9 output P9OUT 02h Port P9 direction P9DIR 04h Port P9 resistor enable P9REN 06h Port P9 drive strength P9DS 08h Port P9 selection 0 P9SEL0 0Ah Port P10 input P10IN 01h Port P10 output P10OUT 03h Port P10 direction P10DIR 05h Port P10 resistor enable P10REN 07h Port P10 drive strength P10DS 09h Port P10 selection 0 P10SEL0 0Bh Table 6-40. Port 11 Registers (Base Address: 02A0h) REGISTER DESCRIPTION REGISTER OFFSET Port P11 input P11IN 00h Port P11 output P11OUT 02h Port P11 direction P11DIR 04h Port P11 resistor enable P11REN 06h Port P11 drive strength P11DS 08h Port P11 selection 0 P11SEL0 0Ah Table 6-41. Port J Registers (Base Address: 0320h) REGISTER DESCRIPTION REGISTER OFFSET Port PJ input PJIN 00h Port PJ output PJOUT 02h Port PJ direction PJDIR 04h Port PJ resistor enable PJREN 06h Port PJ drive strength PJDS 08h Port PJ selection PJSEL 0Ah Table 6-42. TA0 Registers (Base Address: 0340h) REGISTER DESCRIPTION REGISTER OFFSET TA0 control TA0CTL 00h Capture/compare control 0 TA0CCTL0 02h Capture/compare control 1 TA0CCTL1 04h Capture/compare control 2 TA0CCTL2 06h TA0 counter TA0R 10h Capture/compare 0 TA0CCR0 12h Capture/compare 1 TA0CCR1 14h Capture/compare 2 TA0CCR2 16h TA0 expansion 0 TA0EX0 20h TA0 interrupt vector TA0IV 2Eh 92 Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 6-43. TA1 Registers (Base Address: 0380h) REGISTER DESCRIPTION REGISTER OFFSET TA1 control TA1CTL 00h Capture/compare control 0 TA1CCTL0 02h Capture/compare control 1 TA1CCTL1 04h TA1 counter TA1R 10h Capture/compare 0 TA1CCR0 12h Capture/compare 1 TA1CCR1 14h TA1 expansion 0 TA1EX0 20h TA1 interrupt vector TA1IV 2Eh Table 6-44. TA2 Registers (Base Address: 0400h) REGISTER DESCRIPTION REGISTER OFFSET TA2 control TA2CTL 00h Capture/compare control 0 TA2CCTL0 02h Capture/compare control 1 TA2CCTL1 04h TA2 counter TA2R 10h Capture/compare 0 TA2CCR0 12h Capture/compare 1 TA2CCR1 14h TA2 expansion 0 TA2EX0 20h TA2 interrupt vector TA2IV 2Eh Table 6-45. TA3 Registers (Base Address: 0440h) REGISTER DESCRIPTION REGISTER OFFSET TA3 control TA3CTL 00h Capture/compare control 0 TA3CCTL0 02h Capture/compare control 1 TA3CCTL1 04h TA3 counter TA3R 10h Capture/compare 0 TA3CCR0 12h Capture/compare 1 TA3CCR1 14h TA3 expansion 0 TA3EX0 20h TA3 interrupt vector TA3IV 2Eh Table 6-46. Backup Memory Registers (Base Address: 0480h) REGISTER DESCRIPTION REGISTER OFFSET Backup memory 0 BAKMEM0 00h Backup memory 1 BAKMEM1 02h Backup memory 2 BAKMEM2 04h Backup memory 3 BAKMEM3 06h Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 93 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 6-47. RTC_C Registers (Base Address: 0C80h) REGISTER DESCRIPTION REGISTER OFFSET RTC control 0 RTCCTL0 00h RTC password RTCPWD 01h RTC control 1 RTCCTL1 02h RTC control 3 RTCCTL3 03h RTC offset calibration RTCOCAL 04h RTC temperature compensation RTCTCMP 06h RTC prescaler 0 control RTCPS0CTL 08h RTC prescaler 1 control RTCPS1CTL 0Ah RTC prescaler 0 RTCPS0 0Ch RTC prescaler 1 RTCPS1 0Dh RTC interrupt vector word RTCIV 0Eh RTC seconds RTCSEC 10h RTC minutes RTCMIN 11h RTC hours RTCHOUR 12h RTC day of week RTCDOW 13h RTC days RTCDAY 14h RTC month RTCMON 15h RTC year RTCYEAR 16h RTC alarm minutes RTCAMIN 18h RTC alarm hours RTCAHOUR 19h RTC alarm day of week RTCADOW 1Ah RTC alarm days RTCADAY 1Bh Binary-to-BCD conversion BIN2BCD 1Ch BCD-to-binary conversion BCD2BIN 1Eh Real-time clock time capture control RTCTCCTL 20h Tamper detect pin 0 control RTCCAP0CTL 21h Tamper detect pin 1 control RTCCAP1CTL 22h RTC seconds backup 0 RTCSECBAK0 30h RTC minutes backup 0 RTCMINBAK0 31h RTC hours backup 0 RTCHOURBAK0 32h RTC days backup 0 RTCDAYBAK0 33h RTC month backup 0 RTCMONBAK0 34h RTC year backup 0 RTCYEARBAK0 36h RTC seconds backup 1 RTCSECBAK1 38h RTC minutes backup 1 RTCMINBAK1 39h RTC hours backup 1 RTCHOURBAK1 3Ah RTC days backup 1 RTCDAYBAK1 3Bh RTC month backup 1 RTCMONBAK1 3Ch RTC year backup 1 RTCYEARBAK1 3Eh 94 Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 6-48. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h) REGISTER DESCRIPTION REGISTER OFFSET 16-bit operand 1 – multiply MPY 00h 16-bit operand 1 – signed multiply MPYS 02h 16-bit operand 1 – multiply accumulate MAC 04h 16-bit operand 1 – signed multiply accumulate MACS 06h 16-bit operand 2 OP2 08h 16 × 16 result low word RESLO 0Ah 16 × 16 result high word RESHI 0Ch 16 × 16 sum extension SUMEXT 0Eh 32-bit operand 1 – multiply low word MPY32L 10h 32-bit operand 1 – multiply high word MPY32H 12h 32-bit operand 1 – signed multiply low word MPYS32L 14h 32-bit operand 1 – signed multiply high word MPYS32H 16h 32-bit operand 1 – multiply accumulate low word MAC32L 18h 32-bit operand 1 – multiply accumulate high word MAC32H 1Ah 32-bit operand 1 – signed multiply accumulate low word MACS32L 1Ch 32-bit operand 1 – signed multiply accumulate high word MACS32H 1Eh 32-bit operand 2 – low word OP2L 20h 32-bit operand 2 – high word OP2H 22h 32 × 32 result 0 – least significant word RES0 24h 32 × 32 result 1 RES1 26h 32 × 32 result 2 RES2 28h 32 × 32 result 3 – most significant word RES3 2Ah MPY32 control 0 MPY32CTL0 2Ch Table 6-49. DMA General Control Registers (Base Address: 0500h) REGISTER DESCRIPTION REGISTER OFFSET DMA module control 0 DMACTL0 00h DMA module control 1 DMACTL1 02h DMA module control 2 DMACTL2 04h DMA module control 3 DMACTL3 06h DMA module control 4 DMACTL4 08h DMA interrupt vector DMAIV 0Eh Table 6-50. DMA Channel 0 Registers (Base Address: 0500h) REGISTER DESCRIPTION REGISTER OFFSET DMA channel 0 control DMA0CTL 10h DMA channel 0 source address low DMA0SAL 12h DMA channel 0 source address high DMA0SAH 14h DMA channel 0 destination address low DMA0DAL 16h DMA channel 0 destination address high DMA0DAH 18h DMA channel 0 transfer size DMA0SZ 1Ah Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 95 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 6-51. DMA Channel 1 Registers (Base Address: 0500h) REGISTER DESCRIPTION REGISTER OFFSET DMA channel 1 control DMA1CTL 20h DMA channel 1 source address low DMA1SAL 22h DMA channel 1 source address high DMA1SAH 24h DMA channel 1 destination address low DMA1DAL 26h DMA channel 1 destination address high DMA1DAH 28h DMA channel 1 transfer size DMA1SZ 2Ah Table 6-52. DMA Channel 2 Registers (Base Address: 0500h) REGISTER DESCRIPTION REGISTER OFFSET DMA channel 2 control DMA2CTL 30h DMA channel 2 source address low DMA2SAL 32h DMA channel 2 source address high DMA2SAH 34h DMA channel 2 destination address low DMA2DAL 36h DMA channel 2 destination address high DMA2DAH 38h DMA channel 2 transfer size DMA2SZ 3Ah Table 6-53. eUSCI_A0 Registers (Base Address: 05C0h) REGISTER DESCRIPTION REGISTER OFFSET USCI_A control word 0 UCA0CTLW0 00h USCI _A control word 1 UCA0CTLW1 02h USCI_A baud rate 0 UCA0BR0 06h USCI_A baud rate 1 UCA0BR1 07h USCI_A modulation control UCA0MCTLW 08h USCI_A status UCA0STAT 0Ah USCI_A receive buffer UCA0RXBUF 0Ch USCI_A transmit buffer UCA0TXBUF 0Eh USCI_A LIN control UCA0ABCTL 10h USCI_A IrDA transmit control UCA0IRTCTL 12h USCI_A IrDA receive control UCA0IRRCTL 13h USCI_A interrupt enable UCA0IE 1Ah USCI_A interrupt flags UCA0IFG 1Ch USCI_A interrupt vector word UCA0IV 1Eh 96 Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 6-54. eUSCI_A1 Registers (Base Address:05E0h) REGISTER DESCRIPTION REGISTER OFFSET USCI_A control word 0 UCA1CTLW0 00h USCI _A control word 1 UCA1CTLW1 02h USCI_A baud rate 0 UCA1BR0 06h USCI_A baud rate 1 UCA1BR1 07h USCI_A modulation control UCA1MCTLW 08h USCI_A status UCA1STAT 0Ah USCI_A receive buffer UCA1RXBUF 0Ch USCI_A transmit buffer UCA1TXBUF 0Eh USCI_A LIN control UCA1ABCTL 10h USCI_A IrDA transmit control UCA1IRTCTL 12h USCI_A IrDA receive control UCA1IRRCTL 13h USCI_A interrupt enable UCA1IE 1Ah USCI_A interrupt flags UCA1IFG 1Ch USCI_A interrupt vector word UCA1IV 1Eh Table 6-55. eUSCI_A2 Registers (Base Address:0600h) REGISTER DESCRIPTION REGISTER OFFSET USCI_A control word 0 UCA2CTLW0 00h USCI _A control word 1 UCA2CTLW1 02h USCI_A baud rate 0 UCA2BR0 06h USCI_A baud rate 1 UCA2BR1 07h USCI_A modulation control UCA2MCTLW 08h USCI_A status UCA2STAT 0Ah USCI_A receive buffer UCA2RXBUF 0Ch USCI_A transmit buffer UCA2TXBUF 0Eh USCI_A LIN control UCA2ABCTL 10h USCI_A IrDA transmit control UCA2IRTCTL 12h USCI_A IrDA receive control UCA2IRRCTL 13h USCI_A interrupt enable UCA2IE 1Ah USCI_A interrupt flags UCA2IFG 1Ch USCI_A interrupt vector word UCA2IV 1Eh Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 97 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 6-56. eUSCI_A3 Registers (Base Address: 0620h) REGISTER DESCRIPTION REGISTER OFFSET USCI_A control word 0 UCA3CTLW0 00h USCI _A control word 1 UCA3CTLW1 02h USCI_A baud rate 0 UCA3BR0 06h USCI_A baud rate 1 UCA3BR1 07h USCI_A modulation control UCA3MCTLW 08h USCI_A status UCA3STAT 0Ah USCI_A receive buffer UCA3RXBUF 0Ch USCI_A transmit buffer UCA3TXBUF 0Eh USCI_A LIN control UCA3ABCTL 10h USCI_A IrDA transmit control UCA3IRTCTL 12h USCI_A IrDA receive control UCA3IRRCTL 13h USCI_A interrupt enable UCA3IE 1Ah USCI_A interrupt flags UCA3IFG 1Ch USCI_A interrupt vector word UCA3IV 1Eh Table 6-57. eUSCI_B0 Registers (Base Address: 0640h) REGISTER DESCRIPTION REGISTER OFFSET USCI_B control word 0 UCB0CTLW0 00h USCI_B control word 1 UCB0CTLW1 02h USCI_B bit rate 0 UCB0BR0 06h USCI_B bit rate 1 UCB0BR1 07h USCI_B status word UCB0STATW 08h USCI_B byte counter threshold UCB0TBCNT 0Ah USCI_B receive buffer UCB0RXBUF 0Ch USCI_B transmit buffer UCB0TXBUF 0Eh USCI_B I2C own address 0 UCB0I2COA0 14h USCI_B I2C own address 1 UCB0I2COA1 16h USCI_B I2C own address 2 UCB0I2COA2 18h USCI_B I2C own address 3 UCB0I2COA3 1Ah USCI_B received address UCB0ADDRX 1Ch USCI_B address mask UCB0ADDMASK 1Eh USCI I2C slave address UCB0I2CSA 20h USCI interrupt enable UCB0IE 2Ah USCI interrupt flags UCB0IFG 2Ch USCI interrupt vector word UCB0IV 2Eh 98 Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 6-58. eUSCI_B1 Registers (Base Address: 0680h) REGISTER DESCRIPTION REGISTER OFFSET USCI_B control word 0 UCB1CTLW0 00h USCI_B control word 1 UCB1CTLW1 02h USCI_B bit rate 0 UCB1BR0 06h USCI_B bit rate 1 UCB1BR1 07h USCI_B status word UCB1STATW 08h USCI_B byte counter threshold UCB1TBCNT 0Ah USCI_B receive buffer UCB1RXBUF 0Ch USCI_B transmit buffer UCB1TXBUF 0Eh USCI_B I2C own address 0 UCB1I2COA0 14h USCI_B I2C own address 1 UCB1I2COA1 16h USCI_B I2C own address 2 UCB1I2COA2 18h USCI_B I2C own address 3 UCB1I2COA3 1Ah USCI_B received address UCB1ADDRX 1Ch USCI_B address mask UCB1ADDMASK 1Eh USCI I2C slave address UCB1I2CSA 20h USCI interrupt enable UCB1IE 2Ah USCI interrupt flags UCB1IFG 2Ch USCI interrupt vector word UCB1IV 2Eh Table 6-59. ADC10_A Registers (Base Address: 0740h) REGISTER DESCRIPTION REGISTER OFFSET ADC10_A control 0 ADC10CTL0 00h ADC10_A control 1 ADC10CTL1 02h ADC10_A control 2 ADC10CTL2 04h ADC10_A window comparator low threshold ADC10LO 06h ADC10_A window comparator high threshold ADC10HI 08h ADC10_A memory control 0 ADC10MCTL0 0Ah ADC10_A conversion memory ADC10MCTL0 12h ADC10_A interrupt enable ADC10IE 1Ah ADC10_A interrupt flags ADC10IGH 1Ch ADC10_A interrupt vector word ADC10IV 1Eh Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 99 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 6-60. SD24_B Registers (Base Address: 0800h) REGISTER DESCRIPTION REGISTER OFFSET SD24_B control 0 SD24BCTL0 00h SD24_B control 1 SD24BCTL1 02h SD24_B trigger control SD24BTRGCTL 04h SD24_B trigger OSR control SD24BTRGOSR 06h SD24_B trigger preload SD24BTRGPRE 08h SD24_B interrupt flag SD24BIFG 0Ah SD24_B interrupt enable SD24BIE 0Ch SD24_B interrupt vector SD24BIV 0Eh SD24_B converter 0 control SD24BCCTL0 10h SD24_B converter 0 input control SD24BINCTL0 12h SD24_B converter 0 OSR control SD24BOSR0 14h SD24_B converter 0 preload SD24BPRE0 16h SD24_B converter 1 control SD24BCCTL1 18h SD24_B converter 1 input control SD24BINCTL1 1Ah SD24_B converter 1 OSR control SD24BOSR1 1Ch SD24_B converter 1 preload SD24BPRE1 1Eh SD24_B converter 2 control SD24BCCTL2 20h SD24_B converter 2 input control SD24BINCTL2 22h SD24_B converter 2 OSR control SD24BOSR2 24h SD24_B converter 2 preload SD24BPRE2 26h SD24_B converter 3 control SD24BCCTL3 28h SD24_B converter 3 input control SD24BINCTL3 2Ah SD24_B converter 3 OSR control SD24BOSR3 2Ch SD24_B converter 3 preload SD24BPRE3 2Eh SD24_B converter 4 control SD24BCCTL4 30h SD24_B converter 4 input control SD24BINCTL4 32h SD24_B converter 4 OSR control SD24BOSR4 34h SD24_B converter 4 preload SD24BPRE4 36h SD24_B converter 5 control SD24BCCTL5 38h SD24_B converter 5 Input control SD24BINCTL5 3Ah SD24_B converter 5 OSR control SD24BOSR5 3Ch SD24_B converter 5 preload SD24BPRE5 3Eh SD24_B converter 6 control SD24BCCTL6 40h SD24_B converter 6 Input control SD24BINCTL6 42h SD24_B converter 6 OSR control SD24BOSR6 44h SD24_B converter 6 preload SD24BPRE6 46h SD24_B converter 0 conversion memory low word SD24BMEML0 50h SD24_B converter 0 conversion memory high word SD24BMEMH0 52h SD24_B converter 1 conversion memory low word SD24BMEML1 54h SD24_B converter 1 conversion memory high word SD24BMEMH1 56h SD24_B converter 2 conversion memory low word SD24BMEML2 58h SD24_B converter 2 conversion memory high word SD24BMEMH2 5Ah SD24_B converter 3 conversion memory low word SD24BMEML3 5Ch SD24_B converter 3 conversion memory high word SD24BMEMH3 5Eh SD24_B converter 4 conversion memory low word SD24BMEML4 60h SD24_B converter 4 conversion memory high word SD24BMEMH4 62h SD24_B converter 5 conversion memory low word SD24BMEML5 64h 100 Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 6-60. SD24_B Registers (Base Address: 0800h) (continued) REGISTER DESCRIPTION REGISTER OFFSET SD24_B converter 5 conversion memory high word SD24BMEMH5 66h SD24_B converter 6 conversion memory low word SD24BMEML6 68h SD24_B converter 6 conversion memory high word SD24BMEMH6 6Ah Table 6-61. Comparator_B Register (Base Address: 08C0h) REGISTER DESCRIPTION REGISTER OFFSET Comp_B control 0 CBCTL0 00h Comp_B control 1 CBCTL1 02h Comp_B control 2 CBCTL2 04h Comp_B control 3 CBCTL3 06h Comp_B interrupt CBINT 0Ch Comp_B interrupt vector word CBIV 0Eh Table 6-62. AES Accelerator Registers (Base Address: 09C0h) REGISTER DESCRIPTION REGISTER OFFSET AES accelerator control 0 AESACTL0 00h AES accelerator status AESASTAT 04h AES accelerator key AESAKEY 06h AES accelerator data in AESADIN 08h AES accelerator data out AESADOUT 0Ah Table 6-63. Auxiliary Supply Registers (Base Address: 09E0h) REGISTER DESCRIPTION REGISTER OFFSET Auxiliary supply control 0 AUXCTL0 00h Auxiliary supply control 1 AUXCTL1 02h Auxiliary supply control 2 AUXCTL2 04h AUX2 charger control AUX2CHCTL 12h AUX3 charger control AUX3CHCTL 14h AUX ADC control AUXADCCTL 16h AUX interrupt flag AUXIFG 1Ah AUX interrupt enable AUXIE 1Ch AUX interrupt vector word AUXIV 1Eh Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 101 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 6-64. LCD_C Registers (Base Address: 0A00h) REGISTER DESCRIPTION REGISTER OFFSET LCD_C control 0 LCDCCTL0 000h LCD_C control 1 LCDCCTL1 002h LCD_C blinking control LCDCBLKCTL 004h LCD_C memory control LCDCMEMCTL 006h LCD_C voltage control LCDCVCTL 008h LCD_C port control 0 LCDCPCTL0 00Ah LCD_C port control 1 LCDCPCTL1 00Ch LCD_C port control 2 LCDCPCTL2 00Eh LCD_C charge pump control LCDCCPCTL 012h LCD_C interrupt vector LCDCIV 01Eh LCD_C memory 1 LCDM1 020h LCD_C memory 2 LCDM2 021h Static and 2- to 4-mux modes ⋮ ⋮ ⋮ LCD_C memory 20 LCDM20 033h LCD_C blinking memory 1 LCDBM1 040h LCD_C blinking memory 2 LCDBM2 041h ⋮ ⋮ LCD_C blinking memory 20 ⋮ LCDBM20 053h LCD_C memory 1 LCDM1 020h LCD_C memory 2 LCDM2 021h 5- to 8-mux modes ⋮ ⋮ LCD_C memory 40 102 Detailed Description ⋮ LCDM40 047h Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 6.12 Input/Output Diagrams 6.12.1 Port P1 (P1.0 to P1.3) Input/Output With Schmitt Trigger (PEU Package Only) Figure 6-6 shows the port diagram. Table 6-65 summarizes the selection of the pin functions. A0 to A3 From ADC P1REN.x P1DIR.x DVSS 0 DVCC 1 00 01 10 11 P1OUT.x 00 From Timer_A, ACLK, ADC10CLK 01 DVSS 11 10 (MSP430F677xAIPEU only) P1.0/TA1.1/VeREF-/A0 P1.1/TA2.1/VeREF+/A1 P1.2/ACLK/A2 P1.3/ADC10CLK/A3 P1DS.x P1SEL0.x P1SEL1.x P1IN.x EN To Timer_A D Bus Keeper P1IE.x P1IRQ.x Q P1IFG.x P1SEL.x P1IES.x EN SET Interrupt Edge Select Figure 6-6. Port P1 (P1.0 to P1.3) Diagram (PEU Package Only) Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 103 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 6-65. Port P1 (P1.0 to P1.3) Pin Functions (PEU Package Only) PIN NAME (P1.x) x FUNCTION P1SEL1.x P1SEL0.x I:0; O:1 0 0 TA1.CCI1A 0 0 1 TA1.1 1 0 1 N/A 0 1 0 DVSS 1 1 0 VeREF-/A0 X 1 1 I:0; O:1 0 0 TA2.CCI1A 0 0 1 TA2.1 1 0 1 N/A 0 1 0 DVSS 1 1 0 VeREF+/A1 X 1 1 I:0; O:1 0 0 ACLK 1 0 1 N/A 0 1 0 DVSS 1 1 0 A2 X 1 1 I:0; O:1 0 0 ADC10CLK 1 0 1 N/A 0 1 0 DVSS 1 1 0 A3 X 1 1 P1.0 (I/O) P1.0/TA1.1/VeREF-/A0 0 P1.1 (I/O) P1.1/TA2.1/VeREF+/A1 1 P1.2 (I/O) P1.2/ACLK/A2 2 P1.3 (I/O) P1.3/ADC10CLK/A3 (1) 104 3 CONTROL BITS OR SIGNALS (1) P1DIR.x X = don't care Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 6.12.2 Port P1 (P1.0 to P1.3) Input/Output With Schmitt Trigger (PZ Package Only) Figure 6-7 shows the port diagram. Table 6-66 summarizes the selection of the pin functions. A0 to A3 From ADC P1REN.x P1DIR.x DVSS 0 DVCC 1 00 01 10 11 P1OUT.x 00 From Comparator_B From Timer_A, ACLK, ADC10CLK DVSS 01 10 11 (MSP430F677xAIPZ only) P1.0/TA1.1/VeREF-/A0 P1.1/TA2.1/CBOUT/VeREF+/A1 P1.2/ACLK/A2 P1.3/ADC10CLK/A3 P1DS.x P1SEL0.x P1SEL1.x P1IN.x EN To Timer_A D Bus Keeper P1IE.x P1IRQ.x P1IFG.x P1SEL.x P1IES.x Q EN SET Interrupt Edge Select Figure 6-7. Port P1 (P1.0 to P1.3) Diagram (PZ Package Only) Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 105 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 6-66. Port P1 (P1.0 to P1.3) Pin Functions (PZ Package Only) PIN NAME (P1.x) x FUNCTION P1SEL1.x P1SEL0.x I:0; O:1 0 0 TA1.CCI1A 0 0 1 TA1.1 1 0 1 N/A 0 1 0 DVSS 1 1 0 VeREF-/A0 X 1 1 I:0; O:1 0 0 TA2.CCI1A 0 0 1 TA2.1 1 0 1 N/A 0 1 0 CBOUT 1 1 0 VeREF+/A1 X 1 1 I:0; O:1 0 0 ACLK 1 0 1 N/A 0 1 0 DVSS 1 1 0 A2 X 1 1 I:0; O:1 0 0 ADC10CLK 1 0 1 N/A 0 1 0 DVSS 1 1 0 A3 X 1 1 P1.0 (I/O) P1.0/TA1.1/VeREF-/A0 0 P1.1 (I/O) P1.1/TA2.1/CBOUT/VeREF+/A1 1 P1.2 (I/O) P1.2/ACLK/A2 2 P1.3 (I/O) P1.3/ADC10CLK/A3 (1) 106 3 CONTROL BITS OR SIGNALS (1) P1DIR.x X = don't care Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 6.12.3 Port P1 (P1.4 and P1.5) Input/Output With Schmitt Trigger Figure 6-8 shows the port diagram. Table 6-67 summarizes the selection of the pin functions. To Comparator_B From Comparator_B CBPD.z A0 to A3 From ADC P1REN.x P1DIR.x DVSS 0 DVCC 1 00 01 10 11 P1OUT.x 00 01 From MCLK, SMCLK 10 DVSS 11 P1.4/MCLK/CB1/A4 P1.5/SMCLK/CB0/A5 P1DS.x P1SEL0.x P1SEL1.x P1IN.x EN Not used D Bus Keeper P1IE.x P1IRQ.x Q P1IFG.x EN SET P1SEL.x Interrupt Edge Select P1IES.x Figure 6-8. Port P1 (P1.4 and P1.5) Diagram Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 107 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 6-67. Port P1 (P1.4 and P1.5) Pin Functions PIN NAME (P1.x) x FUNCTION P1SEL1.x P1SEL0.x CPBD.z I:0; O:1 0 0 0 MCLK 1 0 1 0 N/A 0 1 0 0 DVSS 1 1 0 0 A4 X 1 1 0 CB1 X X X 1 (z = 1) P1.4 (I/O) P1.4/MCLK/CB1/A4 4 P1.5 (I/O) P1.5/SMCLK/CB0/A5 (1) 108 5 CONTROL BITS OR SIGNALS (1) P1DIR.x I:0; O:1 0 0 0 SMCLK 1 0 1 0 N/A 0 1 0 0 DVSS 1 1 0 0 A5 X 1 1 0 CB0 X X X 1 (z = 0) X = don't care Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 6.12.4 Port P1 (P1.6 and P1.7) Input/Output With Schmitt Trigger Figure 6-9 shows the port diagram. Table 6-68 summarizes the selection of the pin functions. COM2 to COM3 From LCD_C P1REN.x P1DIR.x DVSS 0 DVCC 1 00 01 10 11 P1OUT.x 00 01 DVSS 10 11 P1.6/COM2 P1.7/COM3 P1DS.x P1SEL0.x P1SEL1.x P1IN.x EN Not used D Bus Keeper P1IE.x P1IRQ.x Q P1IFG.x P1SEL.x P1IES.x EN SET Interrupt Edge Select Figure 6-9. Port P1 (P1.6 and P1.7) Diagram Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 109 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 6-68. Port P1 (P1.6 and P1.7) Pin Functions PIN NAME (P1.x) x FUNCTION P1SEL1.x P1SEL0.x COM Enable I:0; O:1 X 0 0 N/A 0 X 1 0 DVSS 1 X 1 0 P1.6 (I/O) P1.6/COM2 6 COM2 X X X 1 I:0; O:1 X 0 0 N/A 0 X 1 0 DVSS 1 X 1 0 COM3 X X X 1 P1.7 (I/O) P1.7/COM3 (1) 110 7 CONTROL BITS OR SIGNALS (1) P1DIR.x X = don't care Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 6.12.5 Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger (PEU Package Only) Figure 6-10 shows the port diagram. Table 6-69 summarizes the selection of the pin functions. P2REN.x P2MAP.x = PMAP_ANALOG P2DIR.x 0 From Port Mapping 1 P2OUT.x 0 From Port Mapping 1 DVSS 0 DVCC 1 (MSP430F677xAIPEU only) P2.0/PM_TA0.0 P2.1/PM_TA0.1 P2.2/PM_TA0.2 P2.3/PM_TA1.0 P2.4/PM_TA2.0 P2.5/PM_UCB0SOMI/PM_UCB0SCL P2.6/PM_UCB0SIMO/PM_UCB0SDA P2.7/PM_UCB0CLK P2DS.x P2SEL0.x P2IN.x EN To Port Mapping D Bus Keeper P2IE.x P2IRQ.x Q P2IFG.x EN SET P2SEL.x Interrupt Edge Select P2IES.x Figure 6-10. Port P2 (P2.0 to P2.7) Diagram (PEU Package Only) Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 111 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 6-69. Port P2 (P2.0 to P2.7) Pin Functions (PEU Package Only) PIN NAME (P2.x) x FUNCTION P2SEL0.x I:0; O:1 0 X Mapped secondary digital function X 1 ≤ 30 Output driver and input Schmitt trigger disabled X 1 = 31 I:0; O:1 0 X X 1 ≤ 30 = 31 P2.0 (I/O) P2.0/PM_TA0.0 0 P2.1 (I/O) P2.1/PM_TA0.1 1 Mapped secondary digital function Output driver and input Schmitt trigger disabled P2.2 (I/O) P2.2/PM_TA0.2 2 Mapped secondary digital function Output driver and input Schmitt trigger disabled P2.3 (I/O) P2.3/PM_TA1.0 3 Mapped secondary digital function Output driver and input Schmitt trigger disabled P2.4 (I/O) P2.4/PM_TA2.0 4 Mapped secondary digital function Output driver and input Schmitt trigger disabled P2.5 (I/O) P2.5/PM_UCB0SOMI/ PM_UCB0SCL 5 Mapped secondary digital function Output driver and input Schmitt trigger disabled P2.6 (I/O) P2.6/PM_UCB0SIMO/ PM_UCB0SDA 6 Mapped secondary digital function Output driver and input Schmitt trigger disabled (1) 112 7 P2MAP.x X 1 I:0; O:1 0 X X 1 ≤ 30 = 31 X 1 I:0; O:1 0 X X 1 ≤ 30 = 31 X 1 I:0; O:1 0 X X 1 ≤ 30 = 31 X 1 I:0; O:1 0 X X 1 ≤ 30 = 31 X 1 I:0; O:1 0 X X 1 ≤ 30 = 31 X 1 I:0; O:1 0 X Mapped secondary digital function X 1 ≤ 30 Output driver and input Schmitt trigger disabled X 1 = 31 P2.7 (I/O) P2.7/PM_UCB0CLK CONTROL BITS OR SIGNALS (1) P2DIR.x X = don't care Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 6.12.6 Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger (PZ Package Only) Figure 6-11 shows the port diagram. Table 6-70 summarizes the selection of the pin functions. COM4 to COM7 From LCD_C P2REN.x P2MAP.x = PMAP_ANALOG P2DIR.x 0 From Port Mapping 1 P2OUT.x 0 From Port Mapping 1 DVSS 0 DVCC 1 (MSP430F677xAIPZ only) P2.0/PM_TA0.0/COM4 P2.1/PM_TA0.1/COM5 P2.2/PM_TA0.2/COM6 P2.3/PM_TA1.0/COM7 P2DS.x P2SEL0.x P2IN.x EN To Port Mapping D Bus Keeper P2IE.x P2IRQ.x Q P2IFG.x EN SET P2SEL.x Interrupt Edge Select P2IES.x Figure 6-11. Port P2 (P2.0 to P2.3) Diagram (PZ Package Only) Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 113 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 6-70. Port P2 (P2.0 to P2.3) Pin Functions (PZ Package Only) CONTROL BITS OR SIGNALS (1) PIN NAME (P2.x) x FUNCTION P2.0 (I/O) P2.0/PM_TA0.0/ COM4 0 2 0 X 0 1 ≤ 30 0 Output driver and input Schmitt trigger disabled X 1 = 31 0 X X X 1 I:0; O:1 0 X 0 Mapped secondary digital function X 1 ≤ 30 0 Output driver and input Schmitt trigger disabled X 1 = 31 0 COM5 X X X 1 I:0; O:1 0 X 0 Mapped secondary digital function X 1 ≤ 30 0 Output driver and input Schmitt trigger disabled X 1 = 31 0 COM6 X X X 1 I:0; O:1 0 X 0 Mapped secondary digital function X 1 ≤ 30 0 Output driver and input Schmitt trigger disabled X 1 = 31 0 COM7 X X X 1 P2.3 (I/O) P2.3/PM_TA1.0/ COM7 (1) 114 3 COM Enable X P2.2 (I/O) P2.2/PM_TA0.2/ COM6 P2MAP.x I:0; O:1 P2.1 (I/O) 1 P2SEL0.x Mapped secondary digital function COM4 P2.1/PM_TA0.1/ COM5 P2DIR.x X = don't care Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 6.12.7 Port P2 (P2.4 to P2.6) Input/Output With Schmitt Trigger (PZ Package Only) Figure 6-12 shows the port diagram. Table 6-71 summarizes the selection of the pin functions. P2REN.x P2MAP.x = PMAP_ANALOG P2DIR.x 0 From Port Mapping 1 P2OUT.x 0 From Port Mapping 1 DVSS 0 DVCC 1 (MSP430F677xAIPZ only) P2.4/PM_TA2.0 P2.5/PM_UCB0SOMI/PM_UCB0SCL P2.6/PM_UCB0SIMO/PM_UCB0SDA P2DS.x P2SEL0.x P2IN.x EN To Port Mapping D Bus Keeper P2IE.x P2IRQ.x Q P2IFG.x EN SET P2SEL.x Interrupt Edge Select P2IES.x Figure 6-12. Port P2 (P2.4 to P2.6) Diagram (PZ Package Only) Table 6-71. Port P2 (P2.4 to P2.6) Pin Functions (PZ Package Only) PIN NAME (P2.x) x FUNCTION P2.4 (I/O) P2.4/PM_TA2.0/R23 4 Mapped secondary digital function R23 5 (1) 6 0 P2MAP.x X X 1 ≤ 30 X 1 = 31 0 X Mapped secondary digital function X 1 ≤ 30 R13 X 1 = 31 P2.6 (I/O) P2.6/PM_UCB0SIMO/ PM_UCB0SDA/R03 P2SEL0.x I:0; O:1 I:0; O:1 P2.5 (I/O) P2.5/PM_UCB0SOMI/ PM_UCB0SCL/R13 CONTROL BITS OR SIGNALS (1) P2DIR.x I:0; O:1 0 X Mapped secondary digital function X 1 ≤ 30 R03 X 1 = 31 X = don't care Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 115 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com 6.12.8 Port P2 (P2.7) Input/Output With Schmitt Trigger (PZ Package Only) Figure 6-13 shows the port diagram. Table 6-72 summarizes the selection of the pin functions. Comparator_B CBPD.z P2REN.x P2MAP.x = PMAP_ANALOG DVSS 0 DVCC 1 0 P2DIR.x 1 From Port Mapping 0 P2OUT.x 1 From Port Mapping (MSP430F677xAIPZ only) P2.7/PM_UCB0CLK/CB2 P2DS.x P2SEL0.x P2IN.x EN To Port Mapping D Bus Keeper P2IE.x P2IRQ.x Q P2IFG.x EN SET P2SEL.x Interrupt Edge Select P2IES.x Figure 6-13. Port P2 (P2.7) Diagram (PZ Package Only) Table 6-72. Port P2 (P2.7) Pin Functions (PZ Package Only) PIN NAME (P2.x) x FUNCTION P2DIR.x P2SEL0.x P2MAP.x CBPD.z I:0; O:1 0 X 0 Mapped secondary digital function X 1 ≤ 30 0 Output driver and input Schmitt trigger disabled X 1 = 31 0 CB2 X X X 1 (z = 2) P2.7 (I/O) P2.7/PM_UCB0CLK/ CB2 (1) 116 7 CONTROL BITS OR SIGNALS (1) X = don't care Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 6.12.9 Ports P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger (PEU Package Only) Figure 6-14 shows the port diagram. Table 6-73 summarizes the selection of the pin functions. P3REN.x P3MAP.x = PMAP_ANALOG P3DIR.x 0 From Port Mapping 1 P3OUT.x 0 From Port Mapping 1 DVSS 0 DVCC 1 (MSP430F677xAIPEU only) P3.0/PM_UCA0RXD/PM_UCA0SOMI P3.1/PM_UCA0TXD/PM_UCA0SIMO P3.2/PM_UCA0CLK P3.3/PM_UCA1CLK P3.4/PM_UCA1RXD/PM_UCA1SOMI P3.5/PM_UCA1TXD/PM_UCA1SIMO P3.6/PM_UCA2RXD/PM_UCA2SOMI P3.7/PM_UCA2TXD/PM_UCA2SIMO P3DS.x P3SEL0.x P3IN.x EN To Port Mapping D Bus Keeper Figure 6-14. Ports P3 (P3.0 to P3.7) Diagram (PEU Package Only) Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 117 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 6-73. Ports P3 (P3.0 to P3.7) Pin Functions (PEU Package Only) PIN NAME (P3.x) x FUNCTION P3SEL0.x I:0; O:1 0 X Mapped secondary digital function X 1 ≤ 30 Output driver and input Schmitt trigger disabled X 1 = 31 I:0; O:1 0 X X 1 ≤ 30 = 31 P3.0 (I/O) P3.0/PM_UCA0RXD/ PM_UCA0SOMI 0 P3.1 (I/O) P3.1/PM_UCA0TXD/ PM_UCA0SIMO 1 Mapped secondary digital function Output driver and input Schmitt trigger disabled P3.2 (I/O) P3.2/PM_UCA0CLK 2 Mapped secondary digital function Output driver and input Schmitt trigger disabled P3.3 (I/O) P3.3/PM_UCA1CLK 3 Mapped secondary digital function Output driver and input Schmitt trigger disabled P3.4 (I/O) P3.4/PM_UCA1RXD/ PM_UCA1SOMI 4 Mapped secondary digital function Output driver and input Schmitt trigger disabled P3.5 (I/O) P3.5/PM_UCA1TXD/ PM_UCA1SIMO 5 Mapped secondary digital function Output driver and input Schmitt trigger disabled P3.6 (I/O) P3.6/PM_UCA2RXD/ PM_UCA2SOMI 6 Mapped secondary digital function Output driver and input Schmitt trigger disabled (1) 118 7 P3MAP.x X 1 I:0; O:1 0 X X 1 ≤ 30 = 31 X 1 I:0; O:1 0 X X 1 ≤ 30 = 31 X 1 I:0; O:1 0 X X 1 ≤ 30 = 31 X 1 I:0; O:1 0 X X 1 ≤ 30 = 31 X 1 I:0; O:1 0 X X 1 ≤ 30 = 31 X 1 I:0; O:1 0 X Mapped secondary digital function X 1 ≤ 30 Output driver and input Schmitt trigger disabled X 1 = 31 P3.7 (I/O) P3.7/PM_UCA2TXD/ PM_UCA2SIMO CONTROL BITS OR SIGNALS (1) P3DIR.x X = don't care Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 6.12.10 Ports P3 (P3.0) Input/Output With Schmitt Trigger (PZ Package Only) Figure 6-15 shows the port diagram. Table 6-74 summarizes the selection of the pin functions. P3REN.x P3MAP.x = PMAP_ANALOG P3DIR.x 0 From Port Mapping 1 P3OUT.x 0 From Port Mapping 1 DVSS 0 DVCC 1 (MSP430F677xAIPZ only) P3.0/PM_UCA0RXD/PM_UCA0SOMI P3DS.x P3SEL0.x P3IN.x EN D To Port Mapping Bus Keeper Figure 6-15. Ports P3 (P3.0) Diagram (PZ Package Only) Table 6-74. Ports P3 (P3.0) Pin Functions (PZ Package Only) PIN NAME (P3.x) x FUNCTION P3DIR.x P3SEL0.x I:0; O:1 0 X Mapped secondary digital function X 1 ≤ 30 Output driver and input Schmitt trigger disabled X 1 = 31 P3.0 (I/O) P3.0/PM_UCA0RXD/ PM_UCA0SOMI (1) 0 CONTROL BITS OR SIGNALS (1) P3MAP.x X = don't care Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 119 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com 6.12.11 Ports P3 (P3.1 to P3.7) Input/Output With Schmitt Trigger (PZ Package Only) Figure 6-16 shows the port diagram. Table 6-75 summarizes the selection of the pin functions. S39 to S33 LCDS39 to LCDS33 P3REN.x P3MAP.x = PMAP_ANALOG P3DIR.x 0 From Port Mapping 1 P3OUT.x 0 From Port Mapping 1 DVSS 0 DVCC 1 (MSP430F677xAIPZ only) P3.1/PM_UCA0TXD/PM_UCA0SIMO/S39 P3.2/PM_UCA0CLK/S38 P3.3/PM_UCA1CLK/S37 P3.4/PM_UCA1RXD/PM_UCA1SOMI/S36 P3.5/PM_UCA1TXD/PM_UCA1SIMO/S35 P3.6/PM_UCA2RXD/PM_UCA2SOMI/S34 P3.7/PM_UCA2TXD/PM_UCA2SIMO/S33 P3DS.x P3SEL0.x P3IN.x EN D To Port Mapping Bus Keeper Figure 6-16. Ports P3 (P3.1 to P3.7) Diagram (PZ Package Only) 120 Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 6-75. Ports P3 (P3.1 to P3.7) Pin Functions (PZ Package Only) CONTROL BITS OR SIGNALS (1) PIN NAME (P3.x) x FUNCTION P3.1 (I/O) P3.1/PM_UCA0TXD/ PM_UCA0SIMO/S39 1 3 0 X 0 1 ≤ 30 0 Output driver and input Schmitt trigger disabled X 1 = 31 0 X X X 1 I:0; O:1 0 X 0 Mapped secondary digital function X 1 ≤ 30 0 Output driver and input Schmitt trigger disabled X 1 = 31 0 S38 X X X 1 I:0; O:1 0 X 0 Mapped secondary digital function X 1 ≤ 30 0 Output driver and input Schmitt trigger disabled X 1 = 31 0 S37 X X X 1 I:0; O:1 0 X 0 Mapped secondary digital function X 1 ≤ 30 0 Output driver and input Schmitt trigger disabled X 1 = 31 0 S36 X X X 1 I:0; O:1 0 X 0 Mapped secondary digital function X 1 ≤ 30 0 Output driver and input Schmitt trigger disabled X 1 = 31 0 S35 X X X 1 I:0; O:1 0 X 0 Mapped secondary digital function X 1 ≤ 30 0 Output driver and input Schmitt trigger disabled X 1 = 31 0 P3.4 (I/O) P3.4/PM_UCA1RXD/ PM_UCA1SOMI/S36 4 P3.5 (I/O) P3.5/PM_UCA1TXD/ PM_UCA1SIMO/S35 5 P3.6 (I/O) P3.6/PM_UCA2RXD/ PM_UCA2SOMI/S34 6 S34 X X X 1 I:0; O:1 0 X 0 Mapped secondary digital function X 1 ≤ 30 0 Output driver and input Schmitt trigger disabled X 1 = 31 0 S33 X X X 1 P3.7 (I/O) P3.7/PM_UCA2TXD/ PM_UCA2SIMO/S33 (1) 7 LCDS39 to LCDS33 X P3.3 (I/O) P3.3/PM_UCA1CLK/ S37 P3MAP.x I:0; O:1 P3.2 (I/O) 2 P3SEL0.x Mapped secondary digital function S39 P3.2/PM_UCA0CLK/ S38 P3DIR.x X = don't care Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 121 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com 6.12.12 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger (PEU Package Only) Figure 6-17 shows the port diagram. Table 6-76 summarizes the selection of the pin functions. P4REN.x P4MAP.x = PMAP_ANALOG P4DIR.x 0 From Port Mapping 1 P4OUT.x 0 From Port Mapping 1 DVSS 0 DVCC 1 (MSP430F677xAIPEU only) P4.0/PM_UCA2CLK P4.1/PM_UCA3RXD/PM_UCA3SOMI P4.2/PM_UCA3TXD/PM_UCA3SIMO P4.3/PM_UCA3CLK P4.4/PM_UCB1SOMI/PM_UCB1SCL P4.5/PM_UCB1SIMO/PM_UCB1SDA P4.6/PM_UCB1CLK P4.7/PM_TA3.0 P4DS.x P4SEL0.x P4IN.x EN D To Port Mapping Bus Keeper Figure 6-17. Port P4 (P4.0 to P4.7) Diagram (PEU Package Only) 122 Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 6-76. Port P4 (P4.0 to P4.7) Pin Functions (PEU Package Only) PIN NAME (P4.x) x FUNCTION P4SEL0.x I:0; O:1 0 X Mapped secondary digital function X 1 ≤ 30 Output driver and input Schmitt trigger disabled X 1 = 31 I:0; O:1 0 X X 1 ≤ 30 = 31 P4.0 (I/O) P4.0/PM_UCA2CLK 0 P4.1 (I/O) P4.1/PM_UCA3RXD/ PM_UCA3SOMI 1 Mapped secondary digital function Output driver and input Schmitt trigger disabled P4.2 (I/O) P4.2/PM_UCA3TXD/ PM_UCA3SIMO 2 Mapped secondary digital function Output driver and input Schmitt trigger disabled P4.3 (I/O) P4.3/PM_UCA3CLK 3 Mapped secondary digital function Output driver and input Schmitt trigger disabled P4.4 (I/O) P4.4/PM_UCB1SOMI/ PM_UCB1SCL 4 Mapped secondary digital function Output driver and input Schmitt trigger disabled P4.5 (I/O) P4.5/PM_UCB1SIMO/ PM_UCB1SDA 5 Mapped secondary digital function Output driver and input Schmitt trigger disabled P4.6 (I/O) P4.6/PM_UCB1CLK 6 Mapped secondary digital function Output driver and input Schmitt trigger disabled (1) 7 P4MAP.x X 1 I:0; O:1 0 X X 1 ≤ 30 = 31 X 1 I:0; O:1 0 X X 1 ≤ 30 = 31 X 1 I:0; O:1 0 X X 1 ≤ 30 = 31 X 1 I:0; O:1 0 X X 1 ≤ 30 = 31 X 1 I:0; O:1 0 X X 1 ≤ 30 = 31 X 1 I:0; O:1 0 X Mapped secondary digital function X 1 ≤ 30 Output driver and input Schmitt trigger disabled X 1 = 31 P4.7 (I/O) P4.7/PM_TA3.0 CONTROL BITS OR SIGNALS (1) P4DIR.x X = don't care Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 123 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com 6.12.13 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger (PZ Package Only) Figure 6-18 shows the port diagram. Table 6-77 summarizes the selection of the pin functions. S32 to S25 LCDS32 to LCDS25 P4REN.x P4MAP.x = PMAP_ANALOG P4DIR.x 0 From Port Mapping 1 P4OUT.x 0 From Port Mapping 1 DVSS 0 DVCC 1 (MSP430F677xAIPZ only) P4.0/PM_UCA2CLK/S32 P4.1/PM_UCA3RXD/PM_UCA3SOMI/S31 P4.2/PM_UCA3TXD/PM_UCA3SIMO/S30 P4.3/PM_UCA3CLK/S29 P4.4/PM_UCB1SOMI/PM_UCB1SCL/S28 P4.5/PM_UCB1SIMO/PM_UCB1SDA/S27 P4.6/PM_UCB1CLK/S26 P4.7/PM_TA3.0/S25 P4DS.x P4SEL0.x P4IN.x EN To Port Mapping D Bus Keeper Figure 6-18. Port P4 (P4.0 to P4.7) Diagram (PZ Package Only) 124 Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 6-77. Port P4 (P4.0 to P4.7) Pin Functions (PZ Package Only) CONTROL BITS OR SIGNALS (1) PIN NAME (P4.x) x FUNCTION P4.0 (I/O) P4.0/PM_UCA2CLK/ S32 0 2 0 X 0 1 ≤ 30 0 Output driver and input Schmitt trigger disabled X 1 = 31 0 X X X 1 I:0; O:1 0 X 0 Mapped secondary digital function X 1 ≤ 30 0 Output driver and input Schmitt trigger disabled X 1 = 31 0 S31 X X X 1 I:0; O:1 0 X 0 Mapped secondary digital function X 1 ≤ 30 0 Output driver and input Schmitt trigger disabled X 1 = 31 0 S30 X X X 1 I:0; O:1 0 X 0 Mapped secondary digital function X 1 ≤ 30 0 Output driver and input Schmitt trigger disabled X 1 = 31 0 S29 X X X 1 I:0; O:1 0 X 0 Mapped secondary digital function X 1 ≤ 30 0 Output driver and input Schmitt trigger disabled X 1 = 31 0 S28 X X X 1 I:0; O:1 0 X 0 Mapped secondary digital function X 1 ≤ 30 0 Output driver and input Schmitt trigger disabled X 1 = 31 0 P4.3 (I/O) P4.3/PM_UCA3CLK/ S29 3 P4.4 (I/O) P4.4/ PM_UCB1SOMI/ PM_UCB1SCL/S28 4 P4.5 (I/O) P4.5/ PM_UCB1SIMO/ PM_UCB1SDA/S27 5 S27 X X X 1 I:0; O:1 0 X 0 Mapped secondary digital function X 1 ≤ 30 0 Output driver and input Schmitt trigger disabled X 1 = 31 0 S26 X X X 1 I:0; O:1 0 X 0 Mapped secondary digital function X 1 ≤ 30 0 Output driver and input Schmitt trigger disabled X 1 = 31 0 S25 X X X 1 P4.6 (I/O) P4.6/PM_UCB1CLK/ S26 6 P4.7 (I/O) P4.7/PM_TA3.0/S25 (1) 7 LCD32 to LCDS25 X P4.2 (I/O) P4.2/PM_UCA3TXD/ PM_UCA3SIMO/S30 P4MAP.x I:0; O:1 P4.1 (I/O) 1 P4SEL0.x Mapped secondary digital function S32 P4.1/PM_UCA3RXD/ PM_UCA3SOMI/S31 P4DIR.x X = don't care Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 125 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com 6.12.14 Port P5 (P5.0 to P5.3) Input/Output With Schmitt Trigger (PEU Package Only) Figure 6-19 shows the port diagram. Table 6-78 summarizes the selection of the pin functions. COM4 to COM7 From LCD_C P5REN.x P5DIR.x DVSS 0 DVCC 1 00 01 10 11 P5OUT.x 00 01 DVSS 10 11 (MSP430F677xAIPEU only) P5.0/COM4 P5.1/COM5 P5.2/COM6 P5.3/COM7 P5DS.x P5SEL0.x P5SEL1.x P5IN.x EN D Not used Bus Keeper Figure 6-19. Port P5 (P5.0 to P5.3) Diagram (PEU Package Only) 126 Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 6-78. Port P5 (P5.0 to P5.3) Pin Functions (PEU Package Only) PIN NAME (P5.x) x FUNCTION P5SEL1.x P5SEL0.x COM Enable I:0; O:1 X 0 0 N/A 0 X 1 0 DVSS 1 X 1 0 P5.0 (I/O) P5.0/COM4 0 COM4 X X X 1 I:0; O:1 X 0 0 N/A 0 X 1 0 DVSS 1 X 1 0 COM5 X X X 1 I:0; O:1 X 0 0 N/A 0 X 1 0 DVSS 1 X 1 0 COM6 X X X 1 I:0; O:1 X 0 0 N/A 0 X 1 0 DVSS 1 X 1 0 COM7 X X X 1 P5.1 (I/O) P5.1/COM5 1 P5.2 (I/O) P5.2/COM6 2 P5.3 (I/O) P5.3/COM7 (1) 3 CONTROL BITS OR SIGNALS (1) P5DIR.x X = don't care Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 127 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com 6.12.15 Port P5 (P5.4 to P5.6) Input/Output With Schmitt Trigger (PEU Package Only) Figure 6-20 shows the port diagram. Table 6-79 summarizes the selection of the pin functions. R23, R13, R03, LCDREF P5REN.x P5DIR.x DVSS 0 DVCC 1 00 01 From SD24_B 10 11 P5OUT.x 00 01 From SD24_B 10 DVSS 11 (MSP430F677xAIPEU only) P5.4/SDCLK/R23 P5.5/SD0DIO/LCDREF/R13 P5.6/SD1DIO/R03 P5DS.x P5SEL0.x P5SEL1.x P5IN.x EN D To SD24_B Bus Keeper Figure 6-20. Port P5 (P5.4 to P5.6) Diagram (PEU Package Only) 128 Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 6-79. Port P5 (P5.4 to P5.6) Pin Functions (PEU Package Only) PIN NAME (P5.x) x FUNCTION P5SEL1.x P5SEL0.x I:0; O:1 0 0 Secondary digital function X 0 1 N/A 0 1 0 DVSS 1 1 0 R23 X 1 1 I:0; O:1 0 0 Secondary digital function X 0 1 N/A 0 1 0 DVSS 1 1 0 LCDREF/R13 X 1 1 I:0; O:1 0 0 Secondary digital function X 0 1 N/A 0 1 0 DVSS 1 1 0 R03 X 1 1 P5.4 (I/O) P5.4/SDCLK/R23 4 P5.5 (I/O) P5.5/SD0DIO/LCDREF/R13 5 P5.6 (I/O) PT.6/SD1DIO/R03 (1) 6 CONTROL BITS OR SIGNALS (1) P5DIR.x X = don't care Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 129 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com 6.12.16 Port P5 (P5.7) Input/Output With Schmitt Trigger (PEU Package Only) Figure 6-21 shows the port diagram. Table 6-80 summarizes the selection of the pin functions. To Comparator_B CBPD.z P5REN.x P5DIR.x DVSS 0 DVCC 1 00 01 From SD24_B 10 11 P5OUT.x 00 01 10 From SD24_B 11 (MSP430F677xAIPEU only) P5.7/SD2DIO/CB2 P5DS.x P5SEL0.x P5SEL1.x P5IN.x EN D To SD24_B Bus Keeper Figure 6-21. Port P5 (P5.7) Diagram (PEU Package Only) Table 6-80. Port P5 (P5.7) Pin Function (PEU Package Only) PIN NAME (P5.x) x FUNCTION P5.7 (I/O) P5.7/SD2DIO/CB2 7 Secondary digital function CB2 (1) 130 CONTROL BITS OR SIGNALS (1) P5DIR.x P5SEL1.x P5SEL0.x CBPD.z I:0; O:1 X 0 0 X X 1 0 X X X 1 (z = 2) X = don't care Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 6.12.17 Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger (PZ Package Only) Figure 6-22 shows the port diagram. Table 6-81 summarizes the selection of the pin functions. S24 to S17 LCDS24 to LCDS17 P5REN.x P5DIR.x DVSS 0 DVCC 1 00 01 From SD24_B 10 11 P5OUT.x 00 01 From SD24_B 10 11 (MSP430F677xAIPZ only) P5.0/SDCLK/S24 P5.1/SD0DIO/S23 P5.2/SD1DIO/S22 P5.3/SD2DIO/S21 P5.4/SD3DIO/S20 P5.5/SD4DIO/S19 P5.6/SD5DIO/S18 P5.7/SD6DIO/S17 P5DS.x P5SEL0.x P5SEL1.x P5IN.x EN To SD24_B D Bus Keeper Figure 6-22. Port P5 (P5.0 to P5.7) Diagram (PZ Package Only) Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 131 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 6-81. Port P5 (P5.0 to P5.7) Pin Function (PZ Package Only) CONTROL BITS OR SIGNALS (1) PIN NAME (P5.x) x FUNCTION P5.0 (I/O) P5.0/SDCLK/S24 0 Secondary digital function S24 P5.1 (I/O) P5.1/SD0DIO/S23 1 Secondary digital function S23 P5.2 (I/O) P5.2/SD1DIO/S22 2 Secondary digital function S22 P5.3 (I/O) P5.3/SD2DIO/S21 3 Secondary digital function S21 P5.4 (I/O) P5.4/SD3DIO/S20 4 Secondary digital function S20 P5.5 (I/O) P5.5/SD4DIO/S19 5 Secondary digital function S19 P5.6 (I/O) P5.6/SD5DIO/S18 6 Secondary digital function S18 P5.7 (I/O) P5.7/SD6DIO/S17 7 Secondary digital function S17 (1) 132 P5DIR.x P5SEL1.x P5SEL0.x LCDS24 to LCDS17 I:0; O:1 X 0 0 X X 1 0 X X X 1 I:0; O:1 X 0 0 X X 1 0 X X X 1 I:0; O:1 X 0 0 X X 1 0 X X X 1 I:0; O:1 X 0 0 X X 1 0 X X X 1 I:0; O:1 X 0 0 X X 1 0 X X X 1 I:0; O:1 X 0 0 X X 1 0 X X X 1 I:0; O:1 X 0 0 X X 1 0 X X X 1 I:0; O:1 X 0 0 X X 1 0 X X X 1 X = don't care Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 6.12.18 Port P6 (P6.0) Input/Output With Schmitt Trigger (PEU Package Only) Figure 6-23 shows the port diagram. Table 6-82 summarizes the selection of the pin functions. P6REN.x P6DIR.x 0 From SD24_B 1 P6OUT.x 0 From SD24_B 1 DVSS 0 DVCC 1 (MSP430F677xAIPEU only) P6.0/SD3DIO P6DS.x P6SEL0.x P6IN.x EN To SD24_B D Bus Keeper Figure 6-23. Port P6 (P6.0) Diagram (PEU Package Only) Table 6-82. Port P6 (P6.0) Pin Functions (PEU Package Only) PIN NAME (P6.x) P6.0/SD3DIO (1) x 0 FUNCTION P6.0 (I/O) Secondary digital function CONTROL BITS OR SIGNALS (1) P6DIR.x P6SEL0.x I:0; O:1 0 X 1 X = don't care Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 133 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com 6.12.19 Port P6 (P6.1 to P6.3) Input/Output With Schmitt Trigger (PEU Package Only) Figure 6-24 shows the port diagram. Table 6-83 summarizes the selection of the pin functions. S39 to S37 LCDS39 to LCDS37 P6REN.x P6DIR.x 0 From SD24_B 1 P6OUT.x 0 From SD24_B 1 DVSS 0 DVCC 1 (MSP430F677xAIPEU only) P6.1/SD4DIO/S39 P6.2/SD5DIO/S38 P6.3/SD6DIO/S37 P6DS.x P6SEL0.x P6IN.x EN To SD24_B D Bus Keeper Figure 6-24. Port P6 (P6.1 to P6.3) Diagram (PEU Package Only) Table 6-83. Port P6 (P6.1 to P6.3) Pin Functions (PEU Package Only) CONTROL BITS OR SIGNALS (1) PIN NAME (P6.x) x FUNCTION P6.1 (I/O) P6.1/SD4DIO/S39 1 2 (1) 134 3 LCD39 to LCDS37 I:0; O:1 0 0 X 1 0 S39 X X 1 I:0; O:1 0 0 Secondary digital function X 1 0 S38 X X 1 I:0; O:1 0 0 P6.3 (I/O) P6.3/SD6DIO/S37 P6SEL0.x Secondary digital function P6.2 (I/O) P6.2/SD5DIO/S38 P6DIR.x Secondary digital function X 1 0 S37 X X 1 X = don't care Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 6.12.20 Port P6 (P6.4 to P6.7) Input/Output With Schmitt Trigger (PEU Package Only) Figure 6-25 shows the port diagram. Table 6-84 summarizes the selection of the pin functions. S36 to S0 LCDS36 to LCDS0 P6REN.x P6DIR.x DVSS 0 DVCC 1 0 1 P6OUT.x 0 DVSS 1 (MSP430F677xAIPEU only) P6.4/S36 P6.5/S35 P6.6/S34 P6.7/S33 P6DS.x P6SEL0.x P6IN.x EN Not used D Bus Keeper Figure 6-25. Port P6 (P6.4 to P6.7) Diagram (PEU Package Only) Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 135 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 6-84. Port P6 (P6.4 to P6.7) Pin Functions (PEU Package Only) CONTROL BITS OR SIGNALS (1) PIN NAME (P6.x) x FUNCTION P6.4 (I/O) P6.4/S36 4 0 0 0 1 0 DVSS 1 1 0 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S35 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S34 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S33 X X 1 P6.6(I/O) P6.6/S34 6 P6.7 (I/O) P6.7/S33 (1) 136 7 LCDS36 to LCDS33 I:0; O:1 P6.5 (I/O) 5 P6SEL0.x N/A S36 P6.5/S35 P6DIR.x X = don't care Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 6.12.21 Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger (PZ Package Only) Figure 6-26 shows the port diagram. Table 6-85 summarizes the selection of the pin functions. S16 to S9 LCDS16 to LCDS9 P6REN.x P6DIR.x DVSS 0 DVCC 1 0 1 P6OUT.x 0 DVSS 1 (MSP430F677xAIPZ only) P6.0/S16 P6.1/S15 P6.2/S14 P6.3/S13 P6.4/S12 P6.5/S11 P6.6/S10 P6.7/S9 P6DS.x P6SEL0.x P6IN.x EN Not used D Bus Keeper Figure 6-26. Port P6 (P6.0 to P6.7) Diagram (PZ Package Only) Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 137 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 6-85. Port P6 (P6.0 to P6.7) Pin Functions (PZ Package Only) CONTROL BITS OR SIGNALS (1) PIN NAME (P6.x) x FUNCTION P6.0 (I/O) P6.0/S16 0 0 0 0 1 0 DVSS 1 1 0 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S15 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S14 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S13 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S12 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 P6.2 (I/O) P6.2/S14 2 P6.3 (I/O) P6.3/S13 3 P6.4 (I/O) P6.4/S12 4 P6.5 (I/O) P6.5/S11 5 S11 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S10 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S9 X X 1 P6.6 (I/O) P6.6/S10 6 P6.7 (I/O) P6.7/S9 (1) 138 7 LCDS16 to LCDS9 I:0; O:1 P6.1 (I/O) 1 P6SEL0.x N/A S16 P6.1/S15 P6DIR.x X = don't care Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 6.12.22 Port P7 (P7.0 to P7.7) Input/Output With Schmitt Trigger (PEU Package Only) Figure 6-27 shows the port diagram. Table 6-86 summarizes the selection of the pin functions. S32 to S25 LCDS32 to LCDS25 P7REN.x P7DIR.x DVSS 0 DVCC 1 0 1 P7OUT.x 0 DVSS 1 (MSP430F677xAIPEU only) P7.0/S32 P7.1/S31 P7.2/S30 P7.3/S29 P7.4/S28 P7.5/S27 P7.6/S26 P7.7/S25 P7DS.x P7SEL0.x P7IN.x EN Not used D Bus Keeper Figure 6-27. Port P7 (P7.0 to P7.7) Diagram (PEU Package Only) Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 139 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 6-86. Port P7 (P7.0 to P7.7) Pin Functions (PEU Package Only) CONTROL BITS OR SIGNALS (1) PIN NAME (P7.x) x FUNCTION P7.0 (I/O) P7.0/S32 0 0 0 0 1 0 DVSS 1 1 0 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S31 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S30 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S29 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S28 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 P7.2 (I/O) P7.2/S30 2 P7.3 (I/O) P7.3/S29 3 P7.4 (I/O) P7.4/S28 4 P7.5 (I/O) P7.5/S27 5 S27 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S26 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S25 X X 1 P7.6 (I/O) P7.6/S26 6 P7.7 (I/O) P7.7/S25 (1) 140 7 LCDS32 to LCDS25 I:0; O:1 P7.1 (I/O) 1 P7SEL0.x N/A S32 P7.1/S31 P7DIR.x X = don't care Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 6.12.23 Port P7 (P7.0 to P7.7) Input/Output With Schmitt Trigger (PZ Package Only) Figure 6-28 shows the port diagram. Table 6-87 summarizes the selection of the pin functions. S8 to S1 LCDS8 to LCDS1 P7REN.x P7DIR.x DVSS 0 DVCC 1 0 1 P7OUT.x 0 DVSS 1 (MSP430F677xAIPZ only) P7.0/S8 P7.1/S7 P7.2/S6 P7.3/S5 P7.4/S4 P7.5/S3 P7.6/S2 P7.7/S1 P7DS.x P7SEL0.x P7IN.x EN Not used D Bus Keeper Figure 6-28. Port P7 (P7.0 to P7.7) Diagram (PZ Package Only) Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 141 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 6-87. Port P7 (P7.0 to P7.7) Pin Functions (PZ Package Only) CONTROL BITS OR SIGNALS (1) PIN NAME (P7.x) x FUNCTION P7.0 (I/O) P7.0/S8 0 0 0 0 1 0 DVSS 1 1 0 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S7 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S6 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S5 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S4 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 P7.2 (I/O) P7.2/S6 2 P7.3 (I/O) P7.3/S5 3 P7.4 (I/O) P7.4/S4 4 P7.5 (I/O) P7.5/S3 5 S3 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S2 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S1 X X 1 P7.6 (I/O) P7.6/S2 6 P7.7 (I/O) P7.7/S1 (1) 142 7 LCDS8 to LCDS1 I:0; O:1 P7.1 (I/O) 1 P7SEL0.x N/A S8 P7.1/S7 P7DIR.x X = don't care Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 6.12.24 Port P8 (P8.0 to P8.7) Input/Output With Schmitt Trigger (PEU Package Only) Figure 6-29 shows the port diagram. Table 6-88 summarizes the selection of the pin functions. S24 to S17 LCDS24 to LCDS17 P8REN.x P8DIR.x DVSS 0 DVCC 1 0 1 P8OUT.x 0 DVSS 1 (MSP430F677xAIPEU only) P8.0/S24 P8.1/S23 P8.2/S22 P8.3/S21 P8.4/S20 P8.5/S19 P8.6/S18 P8.7/S17 P8DS.x P8SEL0.x P8IN.x EN Not used D Bus Keeper Figure 6-29. Port P8 (P8.0 to P8.7) Diagram (PEU Package Only) Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 143 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 6-88. Port P8 (P8.0 to P8.7) Pin Functions (PEU Package Only) CONTROL BITS OR SIGNALS (1) PIN NAME (P8.x) x FUNCTION P8.0 (I/O) P8.0/S24 0 0 0 0 1 0 DVSS 1 1 0 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S23 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S22 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S21 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S20 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 P8.2 (I/O) P8.2/S22 2 P8.3 (I/O) P8.3/S21 3 P8.4 (I/O) P8.4/S20 4 P8.5 (I/O) P8.5/S19 5 S19 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S18 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S17 X X 1 P8.6 (I/O) P8.6/S18 6 P8.7 (I/O) P8.7/S17 (1) 144 7 LCDS24 to LCDS17 I:0; O:1 P8.1 (I/O) 1 P8SEL0.x N/A S24 P8.1/S23 P8DIR.x X = don't care Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 6.12.25 Port P8 (P8.0) Input/Output With Schmitt Trigger (PZ Package Only) Figure 6-30 shows the port diagram. Table 6-89 summarizes the selection of the pin functions. S0 LCDS0 P8REN.x DVSS 0 DVCC 1 0 P8DIR.x 1 P8OUT.x 0 DVSS 1 (MSP430F677xAIPZ only) P8.0/S0 P8DS.x P8SEL0.x P8IN.x EN D Not used Bus Keeper Figure 6-30. Port P8 (P8.0) Diagram (PZ Package Only) Table 6-89. Port P8 (P8.0) Pin Functions (PZ Package Only) PIN NAME (P8.x) x FUNCTION P8DIR.x P8SEL0.x LCDS0 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S0 X X 1 P8.0 (I/O) P8.0/S0 (1) 0 CONTROL BITS OR SIGNALS (1) X = don't care Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 145 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com 6.12.26 Port P8 (P8.1) Input/Output With Schmitt Trigger (PZ Package Only) Figure 6-31 shows the port diagram. Table 6-90 summarizes the selection of the pin functions. To Comparator_B CBPD.z P8REN.x DVSS 0 DVCC 1 0 P8DIR.x 1 P8OUT.x 0 RTCCLK 1 (MSP430F677xAIPZ only) P8.1/TACLK/RTCCLK/CB3 P8DS.x P8SEL0.x P8IN.x EN D To TACLK Bus Keeper Figure 6-31. Port P8 (P8.1) Diagram (PZ Package Only) Table 6-90. Port P8 (P8.1) Pin Functions (PZ Package Only) PIN NAME (P8.x) x FUNCTION P8DIR.x P8SEL0.x CBPD.z I:0; O:1 0 0 TACLK 0 1 0 RTCCLK 1 1 0 CB3 X X 1 (z = 3) P8.1 (I/O) P8.1/TACLK/RTCCLK/CB3 (1) 146 1 CONTROL BITS OR SIGNALS (1) X = don't care Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 6.12.27 Port P9 (P9.0 to P9.7) Input/Output With Schmitt Trigger (PEU Package Only) Figure 6-32 shows the port diagram. Table 6-91 summarizes the selection of the pin functions. S16 to S9 LCDS16 to LCDS9 P9REN.x P9DIR.x DVSS 0 DVCC 1 0 1 P9OUT.x 0 DVSS 1 (MSP430F677xAIPEU only) P9.0/S16 P9.1/S15 P9.2/S14 P9.3/S13 P9.4/S12 P9.5/S11 P9.6/S10 P9.7/S9 P9DS.x P9SEL0.x P9IN.x EN Not used D Bus Keeper Figure 6-32. Port P9 (P9.0 to P9.7) Diagram (PEU Package Only) Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 147 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 6-91. Port P9 (P9.0 to P9.7) Pin Functions (PEU Package Only) CONTROL BITS OR SIGNALS (1) PIN NAME (P9.x) x FUNCTION P9.0 (I/O) P9.0/S16 0 0 0 0 1 0 DVSS 1 1 0 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S15 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S14 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S13 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S12 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 P9.2 (I/O) P9.2/S14 2 P9.3 (I/O) P9.3/S13 3 P9.4 (I/O) P9.4/S12 4 P9.5 (I/O) P9.5/S11 5 S11 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S10 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S9 X X 1 P9.6 (I/O) P9.6/S10 6 P9.7 (I/O) P9.7/S9 (1) 148 7 LCDS16 to LCDS9 I:0; O:1 P9.1 (I/O) 1 P9SEL0.x N/A S16 P9.1/S15 P9DIR.x X = don't care Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 6.12.28 Port P10 (P10.0 to P10.7) Input/Output With Schmitt Trigger (PEU Package Only) Figure 6-33 shows the port diagram. Table 6-92 summarizes the selection of the pin functions. S8 to S1 LCDS8 to LCDS1 P10REN.x P10DIR.x DVSS 0 DVCC 1 0 1 P10OUT.x 0 DVSS 1 (MSP430F677xIPEU only) P10.0/S8 P10.1/S7 P10.2/S6 P10.3/S5 P10.4/S4 P10.5/S3 P10.6/S2 P10.7/S1 P10DS.x P10SEL0.x P10IN.x EN Not used D Bus Keeper Figure 6-33. Port P10 (P10.0 to P10.7) Diagram (PEU Package Only) Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 149 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 6-92. Port P10 (P10.0 to P10.7) Pin Functions (PEU Package Only) CONTROL BITS OR SIGNALS (1) PIN NAME (P10.x) x FUNCTION P10.0 (I/O) P10.0/S8 0 0 0 0 1 0 DVSS 1 1 0 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S7 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S6 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S5 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S4 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 P10.2 (I/O) P10.2/S6 2 P10.3 (I/O) P10.3/S5 3 P10.4 (I/O) P10.4/S4 4 P10.5 (I/O) P10.5/S3 5 S3 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S2 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S1 X X 1 P10.6 (I/O) P10.6/S2 6 P10.7 (I/O) P10.7/S1 (1) 150 7 LCDS8 to LCDS1 I:0; O:1 P10.1 (I/O) 1 P10SEL0.x N/A S8 P10.1/S7 P10DIR.x X = don't care Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 6.12.29 Port P11 (P11.0) Input/Output With Schmitt Trigger (PEU Package Only) Figure 6-34 shows the port diagram. Table 6-93 summarizes the selection of the pin functions. S0 LCDS0 P11REN.x DVSS 0 DVCC 1 0 P11DIR.x 1 P11OUT.x 0 DVSS 1 (MSP430F677xIPEU only) P11.0/S0 P11DS.x P11SEL0.x P11IN.x EN D Not used Bus Keeper Figure 6-34. Port P11 (P11.0) Diagram (PEU Package Only) Table 6-93. Port P11 (P11.0) Pin Functions (PEU Package Only) PIN NAME (P11.x) x FUNCTION P11DIR.x P11SEL0.x LCDS0 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 S0 X X 1 P11.0 (I/O) P11.0/S0 (1) 0 CONTROL BITS OR SIGNALS (1) X = don't care Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 151 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com 6.12.30 Port P11 (P11.1) Input/Output With Schmitt Trigger (PEU Package Only) Figure 6-35 shows the port diagram. Table 6-94 summarizes the selection of the pin functions. To Comparator_B CBPD.z P11REN.x DVSS 0 DVCC 1 0 P11DIR.x 1 P11OUT.x 0 From Timer_A 1 (MSP430F677xIPEU only) P11.1/TA3.1/CB3 P11DS.x P11SEL0.x P11IN.x EN To Timer_A D Bus Keeper Figure 6-35. Port P11 (P11.1) Diagram (PEU Package Only) Table 6-94. Port P11 (P11.1) Pin Functions (PEU Package Only) PIN NAME (P11.x) P11.1/TA3.1/CB3 (1) 152 x 1 FUNCTION CONTROL BITS OR SIGNALS (1) P11DIR.x P11SEL0.x CBPD.z P11.1 (I/O) I:0; O:1 0 0 TA3.CCI1A 0 1 0 TA3.1 1 1 0 CB3 X X 1 X = don't care Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 6.12.31 Port P11 (P11.2 and P11.3) Input/Output With Schmitt Trigger (PEU Package Only) Figure 6-36 shows the port diagram. Table 6-95 summarizes the selection of the pin functions. P11REN.x DVSS 0 DVCC 1 0 P11DIR.x 1 0 P11OUT.x 1 From Timer_A (MSP430F677xIPEU only) P11.2/TA1.1 P11.3/TA2.1 P11DS.x P11SEL0.x P11IN.x EN To Timer_A D Bus Keeper Figure 6-36. Port P11 (P11.2 and P11.3) Diagram (PEU Package Only) Table 6-95. Port P11 (P11.2 and P11.3) Pin Functions (PEU Package Only) PIN NAME (P11.x) P11.2/TA1.1 P11.3/TA2.1 x 2 3 FUNCTION CONTROL BITS OR SIGNALS P11DIR.x P11SEL0.x P11.2 (I/O) I:0; O:1 0 TA1.CCI1A 0 1 TA1.1 1 1 P11.3 (I/O) I:0; O:1 0 TA2.CCI1A 0 1 TA2.1 1 1 Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 153 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com 6.12.32 Port P11 (P11.4 and P11.5) Input/Output With Schmitt Trigger (PEU Package Only) Figure 6-37 shows the port diagram. Table 6-96 summarizes the selection of the pin functions. P11REN.x DVSS 0 DVCC 1 0 P11DIR.x 1 P11OUT.x 0 From Comparator_B RTCCLK 1 (MSP430F677xIPEU only) P11.4/CBOUT P11.5/TACLK/RTCCLK P11DS.x P11SEL0.x P11IN.x EN To TACLK D Bus Keeper Figure 6-37. Port P11 (P11.4 and P11.5) Diagram (PEU Package Only) Table 6-96. Port P11 (P11.4 and P11.5) Pin Functions (PEU Package Only) PIN NAME (P11.x) x FUNCTION P11SEL0.x I:0; O:1 0 N/A 0 1 CBOUT 1 1 I:0; O:1 0 TACLK 0 1 RTCCLK 1 1 P11.4 (I/O) P11.4/CBOUT 4 P11.5 (I/O) P11.5/TACLK/RTCCLK 154 Detailed Description 5 CONTROL BITS OR SIGNALS P11DIR.x Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 6.12.33 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output Figure 6-38 shows the port diagram. Table 6-97 summarizes the selection of the pin functions. Pad Logic PJREN.x PJDIR.x 0 DVCC 1 PJOUT.x 00 From JTAG 01 SMCLK 10 DVSS 0 DVCC 1 PJDS.0 0: Low drive 1: High drive 11 1 PJ.0/SMCLK/TDO PJSEL.x From JTAG PJIN.x Bus Holder EN D Figure 6-38. Port PJ (PJ.0) Diagram Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 155 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com 6.12.34 Port PJ (PJ.0 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output Figure 6-39 shows the port diagram. Table 6-97 summarizes the selection of the pin functions. Pad Logic PJREN.x PJDIR.x DVSS DVSS 0 DVCC 1 1 0 1 PJOUT.x 00 From JTAG 01 MCLK/ADC10CLK/ACLK 10 PJDS.x 0: Low drive 1: High drive 11 PJ.1/MCLK/TDI/TCLK PJ.2/ADC10CLK/TMS PJ.3/ACLK/TCK PJSEL.x From JTAG PJIN.x EN To JTAG Bus Holder D Figure 6-39. Port PJ (PJ.1 to PJ.3) Diagram 156 Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 6-97. Port PJ (PJ.0 to PJ.3) Pin Functions PIN NAME (PJ.x) x FUNCTION PJSEL.x JTAG MODE I: 0; O: 1 0 0 SMCLK 1 1 0 TDO (3) x x 1 I: 0; O: 1 0 0 1 1 0 x x 1 PJ.2 (I/O) (2) I: 0; O: 1 0 0 ADC10CLK 1 1 0 TMS (3) x x 1 I: 0; O: 1 0 0 1 1 0 x x 1 PJ.0 (I/O) (2) PJ.0/SMCLK/TDO 0 PJ.1 (I/O) PJ.1/MCLK/TDI/TCLK 1 (2) MCLK TDI/TCLK (3) PJ.2/ADC10CLK/TMS 2 (4) (4) PJ.3 (I/O) (2) PJ.3/ACLK/TCK 3 ACLK TCK (3) (1) (2) (3) (4) CONTROL BITS OR SIGNALS (1) PJDIR.x (4) X = don't care Default condition The pin direction is controlled by the JTAG module. In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 157 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com 6.13 Device Descriptors (TLV) Table 6-98 through Table 6-100 list the contents of the device descriptor tag-length-value (TLV) structure for each device type. Table 6-98. F677xA Device Descriptor DESCRIPTION Info Block Die Record ADC10 Calibration 158 ADDRESS SIZE (bytes) Info length 1A00h CRC length VALUE F6779A F6778A F6777A F6776A F6775A 1 06h 06h 06h 06h 06h 1A01h 1 06h 06h 06h 06h 06h CRC value 1A02h 2 Per unit Per unit Per unit Per unit Per unit Device ID 1A04h 2 8224h 8223h 8222h 8221h 8220h Hardware revision 1A06h 1 Per unit Per unit Per unit Per unit Per unit Firmware revision 1A07h 1 Per unit Per unit Per unit Per unit Per unit Die record tag 1A08h 1 08h 08h 08h 08h 08h Die record length 1A09h 1 0Ah 0Ah 0Ah 0Ah 0Ah Lot ID 1A0Ah 4 Per unit Per unit Per unit Per unit Per unit X position 1A0Eh 2 Per unit Per unit Per unit Per unit Per unit Y position 1A10h 2 Per unit Per unit Per unit Per unit Per unit Test record CP 1A12h 1 Per unit Per unit Per unit Per unit Per unit Test record FT 1A13h 1 Per unit Per unit Per unit Per unit Per unit ADC calibration tag 1A14h 1 13h 13h 13h 13h 13h ADC calibration length 1A15h 1 10h 10h 10h 10h 10h ADC gain factor 1A16h 2 Per unit Per unit Per unit Per unit Per unit ADC offset 1A18h 2 Per unit Per unit Per unit Per unit Per unit ADC 15T30 1A1Ah 2 Per unit Per unit Per unit Per unit Per unit ADC 15T85 1A1Ch 2 Per unit Per unit Per unit Per unit Per unit ADC 20T30 1A1Eh 2 Per unit Per unit Per unit Per unit Per unit ADC 20T85 1A20h 2 Per unit Per unit Per unit Per unit Per unit ADC 25T30 1A22h 2 Per unit Per unit Per unit Per unit Per unit ADC 25T85 1A24h 2 Per unit Per unit Per unit Per unit Per unit Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Table 6-99. F676xA Device Descriptor DESCRIPTION Info Block Die Record ADC10 Calibration ADDRESS SIZE (bytes) Info length 1A00h CRC length VALUE F6769A F6768A F6767A F6766A F6765A 1 06h 06h 06h 06h 06h 1A01h 1 06h 06h 06h 06h 06h CRC value 1A02h 2 Per unit Per unit Per unit Per unit Per unit Device ID 1A04h 2 821Fh 821Eh 821Dh 821Ch 821Bh Hardware revision 1A06h 1 Per unit Per unit Per unit Per unit Per unit Firmware revision 1A07h 1 Per unit Per unit Per unit Per unit Per unit Die record tag 1A08h 1 08h 08h 08h 08h 08h Die record length 1A09h 1 0Ah 0Ah 0Ah 0Ah 0Ah Lot ID 1A0Ah 4 Per unit Per unit Per unit Per unit Per unit X position 1A0Eh 2 Per unit Per unit Per unit Per unit Per unit Y position 1A10h 2 Per unit Per unit Per unit Per unit Per unit Test record CP 1A12h 1 Per unit Per unit Per unit Per unit Per unit Test record FT 1A13h 1 Per unit Per unit Per unit Per unit Per unit ADC calibration tag 1A14h 1 13h 13h 13h 13h 13h ADC calibration length 1A15h 1 10h 10h 10h 10h 10h ADC gain factor 1A16h 2 Per unit Per unit Per unit Per unit Per unit ADC offset 1A18h 2 Per unit Per unit Per unit Per unit Per unit ADC 15T30 1A1Ah 2 Per unit Per unit Per unit Per unit Per unit ADC 15T85 1A1Ch 2 Per unit Per unit Per unit Per unit Per unit ADC 20T30 1A1Eh 2 Per unit Per unit Per unit Per unit Per unit ADC 20T85 1A20h 2 Per unit Per unit Per unit Per unit Per unit ADC 25T30 1A22h 2 Per unit Per unit Per unit Per unit Per unit ADC 25T85 1A24h 2 Per unit Per unit Per unit Per unit Per unit Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 159 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Table 6-100. F674xA Device Descriptor DESCRIPTION Info Block Die Record ADC10 Calibration 160 ADDRESS SIZE (bytes) Info length 1A00h CRC length VALUE F6749A F6748A F6747A F6746A F6745A 1 06h 06h 06h 06h 06h 1A01h 1 06h 06h 06h 06h 06h CRC value 1A02h 2 Per unit Per unit Per unit Per unit Per unit Device ID 1A04h 2 821Ah 8219h 8218h 8217h 8216h Hardware revision 1A06h 1 Per unit Per unit Per unit Per unit Per unit Firmware revision 1A07h 1 Per unit Per unit Per unit Per unit Per unit Die record tag 1A08h 1 08h 08h 08h 08h 08h Die record length 1A09h 1 0Ah 0Ah 0Ah 0Ah 0Ah Lot ID 1A0Ah 4 Per unit Per unit Per unit Per unit Per unit X position 1A0Eh 2 Per unit Per unit Per unit Per unit Per unit Y position 1A10h 2 Per unit Per unit Per unit Per unit Per unit Test record CP 1A12h 1 Per unit Per unit Per unit Per unit Per unit Test record FT 1A13h 1 Per unit Per unit Per unit Per unit Per unit ADC calibration tag 1A14h 1 13h 13h 13h 13h 13h ADC calibration length 1A15h 1 10h 10h 10h 10h 10h ADC gain factor 1A16h 2 Per unit Per unit Per unit Per unit Per unit ADC offset 1A18h 2 Per unit Per unit Per unit Per unit Per unit ADC 15T30 1A1Ah 2 Per unit Per unit Per unit Per unit Per unit ADC 15T85 1A1Ch 2 Per unit Per unit Per unit Per unit Per unit ADC 20T30 1A1Eh 2 Per unit Per unit Per unit Per unit Per unit ADC 20T85 1A20h 2 Per unit Per unit Per unit Per unit Per unit ADC 25T30 1A22h 2 Per unit Per unit Per unit Per unit Per unit ADC 25T85 1A24h 2 Per unit Per unit Per unit Per unit Per unit Detailed Description Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 6.14 Identification 6.14.1 Revision Identification The device revision information is shown as part of the top-side marking on the device package. The device-specific errata sheet describes these markings. For links to all of the errata sheets for the devices in this data sheet, see Section 8.4. The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For details on this value, see the "Hardware Revision" entries in Section 6.13. 6.14.2 Device Identification The device type can be identified from the top-side marking on the device package. The device-specific errata sheet describes these markings. For links to all of the errata sheets for the devices in this data sheet, see Section 8.4. A device identification value is also stored in the Device Descriptor structure in the Info Block section. For details on this value, see the "Device ID" entries in Section 6.13. 6.14.3 JTAG Identification Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in detail in the MSP430 Programming With the JTAG Interface. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 161 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com 7 Applications, Implementation, and Layout NOTE Information in the following Applications section is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. The following resources provide application guidelines and best practices when designing with the MSP430F677xA, MSP430F676xA, and MSP430F674xA devices. Implementation of a 3-Phase Electronic Watt-Hour Meter Using the MSP430F677x(A) This application report describes the implementation of a 3-phase electronic electricity meter using the TI MSP430F677x(A) metering processors. This application report includes the necessary information with regard to metrology software and hardware procedures for this single-chip implementation. High-Accuracy 3-Phase Electricity Meter With Tamper Detection The design implements a highly accurate 3-phase electric meter system using the MSP430F6779 smart meter SoC. It exceeds all of the requirements for ANSI C12.20 and IEC-62053 Class 0.2 meters. The F6779 SoC is the most integrated polyphase e-meter SoC with 512KB of flash. This allows developers to create a true single-chip smart e-meter with the highest performance and accuracy. In addition, this EVM has tamper detection capabilities which help the engineer develop methods to prevent theft of electricity from utilities. Features • Comprehensive design includes schematics, BOMs, design files, and test reports. • Three-phase electricity meter which exceeds Class 0.2 accuracy requirements from ANSI and IEC • TI Energy Library firmware calculates all energy measurement parameters including active and reactive power and energy, RMS current and voltage, power factor, and line frequency. • Add-on communications modules for wireless communications standards such as ZigBee®, Wi-Fi®, Wireless M-Bus, and IEEE Std 802.15.4g, both 2.4 GHz and sub-1 GHz • Built-in 160-segment display powered from 3-phase line voltage 162 Applications, Implementation, and Layout Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 8 Device and Documentation Support 8.1 Getting Started and Next Steps For more information on the MSP430™ family of devices and the tools and libraries that are available to help with your development, visit the Getting Started page. 8.2 Device Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS. These prefixes represent evolutionary stages of product development from engineering prototypes (XMS) through fully qualified production devices (MSP). XMS – Experimental device that is not necessarily representative of the final device's electrical specifications MSP – Fully qualified production device XMS devices are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices. TI recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature range, package type, and distribution format. Figure 8-1 provides a legend for reading the complete device name. Device and Documentation Support Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 163 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com MSP 430 F 5 438 A I ZQW T -EP Processor Family Optional: Additional Features MCU Platform Optional: Tape and Reel Device Type Packaging Series Feature Set Processor Family MCU Platform Optional: Temperature Range Optional: A = Revision CC = Embedded RF Radio MSP = Mixed-Signal Processor XMS = Experimental Silicon PMS = Prototype Device 430 = MSP430 low-power microcontroller platform Device Type Memory Type C = ROM F = Flash FR = FRAM G = Flash or FRAM (Value Line) L = No Nonvolatile Memory Specialized Application AFE = Analog Front End BQ = Contactless Power CG = ROM Medical FE = Flash Energy Meter FG = Flash Medical FW = Flash Electronic Flow Meter Series 1 = Up to 8 MHz 2 = Up to 16 MHz 3 = Legacy 4 = Up to 16 MHz with LCD 5 = Up to 25 MHz 6 = Up to 25 MHz with LCD 0 = Low-Voltage Series Feature Set Various levels of integration within a series Optional: A = Revision N/A Optional: Temperature Range S = 0°C to 50°C C = 0°C to 70°C I = –40°C to 85°C T = –40°C to 105°C Packaging http://www.ti.com/packaging Optional: Tape and Reel T = Small reel R = Large reel No markings = Tube or tray Optional: Additional Features -EP = Enhanced Product (–40°C to 105°C) -HT = Extreme Temperature Parts (–55°C to 150°C) -Q1 = Automotive Q100 Qualified Figure 8-1. Device Nomenclature 164 Device and Documentation Support Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com 8.3 SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Tools and Software All MSP microcontrollers are supported by a wide variety of software and hardware development tools. Tools are available from TI and various third parties. See them all at MSP430 Ultra-Low-Power MCUs – Tools & software. Table 8-1 lists the debug features of the MSP430F677xA, MSP430F676xA, and MSP430F674xA MCUs. See the Code Composer Studio for MSP430 User's Guide for details on the available features. Table 8-1. Hardware Debug Features MSP430 ARCHITECTURE 4-WIRE JTAG 2-WIRE JTAG BREAKPOINTS (N) RANGE BREAKPOINTS CLOCK CONTROL STATE SEQUENCER TRACE BUFFER LPMx.5 DEBUGGING SUPPORT MSP430Xv2 Yes Yes 3 Yes Yes No No Yes Design Kits and Evaluation Modules 3-Phase Electronic Watt-Hour EVM for Metering (EVM430-F6779) This EVM430-F6779 is a threephase electricity meter evaluation module based on the MSP430F6779A device. The Emeter has inputs for three voltages and three currents, as well as an additional connection to demonstrate antitampering. The EVM lets you test the new F677x, F674x, F676x, F677x1, F674x1, F676x1 series and see the accuracy results, wide dynamic range achieved, and ease of calibration. The easy-to-use Energy Library provides metrology software for fast startup with this EVM. The software is also programmable for any user’s needs. Three-Phase Metrology With Enhanced ESD Protection and Tamper Detection Reference Design This design implements an ANSI/IEC Class 0.2 three-phase energy meter with enhanced ESD protection. The design also features tamper detection to limit the feasibility of energy theft and communications through ZigBee connectivity. The e-meter SoC is used to perform all metrology functions and sends active power results to the CC2530EM add-on board. Developers can use the companion In Home Display TI Design (TIDM-LOWEND-IHD) to display results remotely. 128-Pin Target Development Board and MSP-FET Programmer Bundle for MSP430F6x MCUs The MSP-FET430U128 is a powerful flash emulation tool to quickly begin application development on the MSP430 MCU. It includes a USB debugging interface used to program and debug the MSP430 in system through the JTAG interface or the pin-saving Spy-Bi-Wire (2-wire JTAG) protocol. Software MSP430Ware™ Software MSP430Ware software is a collection of code examples, data sheets, and other design resources for all MSP430 devices delivered in a convenient package. In addition to providing a complete collection of existing MSP430 design resources, MSP430Ware software also includes a high-level API called MSP Driver Library. This library makes it easy to program MSP430 hardware. MSP430Ware software is available as a component of CCS or as a stand-alone package. Energy Measurement Design Center for MSP430 MCUs The Energy Measurement Design Center is a rapid development tool that enables energy measurement using TI MSP430i20xx and MSP430F67xx flash-based microcontrollers (MCUs). It includes a graphical user interface (GUI), documentation, software library, and examples that can simplify development and accelerate designs in a wide range of power monitoring and energy measurement applications, including smart grid and building automation. Using the Design Center, you can configure, calibrate, and view results without writing a single line of code. MSP Driver Library The abstracted API of MSP Driver Library provides easy-to-use function calls that free you from directly manipulating the bits and bytes of the MSP430 hardware. Thorough documentation is delivered through a helpful API Guide, which includes details on each function call and the recognized parameters. Developers can use Driver Library functions to write complete projects with minimal overhead. MSP430F677x(1)A, MSP430F676x(1)A, MSP430F674x(1)A Code Examples C code examples that configure each of the integrated peripherals for various application needs are available for every MSP device. Device and Documentation Support Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 165 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com MSP EnergyTrace™ Technology EnergyTrace technology for MSP430 microcontrollers is an energybased code analysis tool that measures and displays the energy profile of the application and helps to optimize it for ultra-low-power consumption. ULP (Ultra-Low Power) Advisor ULP Advisor™ software is a tool for guiding developers to write more efficient code to fully use the unique ultra-low-power features of MSP and MSP432 microcontrollers. Aimed at both experienced and new microcontroller developers, ULP Advisor checks your code against a thorough ULP checklist to help minimize the energy consumption of your application. At build time, ULP Advisor provides notifications and remarks to highlight areas of your code that can be further optimized for lower power. Fixed Point Math Library for MSP The MSP IQmath and Qmath Libraries are a collection of highly optimized and high-precision mathematical functions for C programmers to seamlessly port a floating-point algorithm into fixed-point code on MSP430 and MSP432 devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed, high accuracy, and ultra-low energy are critical. By using the IQmath and Qmath libraries, it is possible to achieve execution speeds considerably faster and energy consumption considerably lower than equivalent code written using floating-point math. Floating Point Math Library for MSP430 Continuing to innovate in the low-power and low-cost microcontroller space, TI provides MSPMATHLIB. Leveraging the intelligent peripherals of our devices, this floating-point math library of scalar functions that are up to 26 times faster than the standard MSP430 math functions. Mathlib is easy to integrate into your designs. This library is free and is integrated in both Code Composer Studio IDE and IAR Embedded Workbench IDE. Development Tools Code Composer Studio™ Integrated Development Environment for MSP Microcontrollers Code Composer Studio (CCS) integrated development environment (IDE) supports all MSP microcontroller devices. CCS comprises a suite of embedded software utilities used to develop and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment, debugger, profiler, and many other features. Command-Line Programmer MSP Flasher is an open-source shell-based interface for programming MSP microcontrollers through a FET programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP Flasher can download binary files (.txt or .hex) directly to the MSP microcontroller without an IDE. MSP MCU Programmer and Debugger The MSP-FET is a powerful emulation development tool – often called a debug probe – which lets users quickly begin application development on MSP lowpower MCUs. Creating MCU software usually requires downloading the resulting binary program to the MSP device for validation and debugging. MSP-GANG Production Programmer The MSP Gang Programmer is an MSP430 or MSP432 device programmer that can program up to eight identical MSP430 or MSP432 flash or FRAM devices at the same time. The MSP Gang Programmer connects to a host PC using a standard RS-232 or USB connection and provides flexible programming options that let the user fully customize the process. 166 Device and Documentation Support Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com 8.4 SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Documentation Support The following documents describe the MSP430F677xA, MSP430F676xA, and MSP430F674xA MCUs. Copies of these documents are available on the Internet at www.ti.com. Receiving Notification of Document Updates To receive notification of documentation updates—including silicon errata—go to the product folder for your device on ti.com (for links to the product folders, see Section 8.5). In the upper right corner, click the "Alert me" button. This registers you to receive a weekly digest of product information that has changed (if any). For change details, check the revision history of any revised document. Errata MSP430F6779A Device Erratasheet Describes the known exceptions to the functional specifications. MSP430F6778A Device Erratasheet Describes the known exceptions to the functional specifications. MSP430F6777A Device Erratasheet Describes the known exceptions to the functional specifications. MSP430F6776A Device Erratasheet Describes the known exceptions to the functional specifications. MSP430F6775A Device Erratasheet Describes the known exceptions to the functional specifications. MSP430F6769A Device Erratasheet Describes the known exceptions to the functional specifications. MSP430F6768A Device Erratasheet Describes the known exceptions to the functional specifications. MSP430F6767A Device Erratasheet Describes the known exceptions to the functional specifications. MSP430F6766A Device Erratasheet Describes the known exceptions to the functional specifications. MSP430F6765A Device Erratasheet Describes the known exceptions to the functional specifications. MSP430F6749A Device Erratasheet Describes the known exceptions to the functional specifications. MSP430F6748A Device Erratasheet Describes the known exceptions to the functional specifications. MSP430F6747A Device Erratasheet Describes the known exceptions to the functional specifications. MSP430F6746A Device Erratasheet Describes the known exceptions to the functional specifications. MSP430F6745A Device Erratasheet Describes the known exceptions to the functional specifications. User's Guides MSP430x5xx and MSP430x6xx Family User's Guide peripherals available in this device family. Detailed information on the modules and MSP430™ Flash Device Bootloader (BSL) User's Guide The MSP430 bootloader (BSL) lets users communicate with embedded memory in the MSP430 microcontroller during the prototyping phase, final production, and in service. Both the programmable memory (flash memory) and the data memory (RAM) can be modified as required. Do not confuse the bootloader with the bootstrap loader programs found in some digital signal processors (DSPs) that automatically load program code (and data) from external memory to the internal memory of the DSP. MSP430 Programming With the JTAG Interface This document describes the functions that are required to erase, program, and verify the memory module of the MSP430 flash-based and FRAM-based microcontroller families using the JTAG communication port. In addition, it describes how to program the JTAG access security fuse that is available on all MSP430 devices. This document describes device access using both the standard 4-wire JTAG interface and the 2-wire JTAG interface, which is also referred to as Spy-Bi-Wire (SBW). MSP430 Hardware Tools User's Guide This manual describes the hardware of the TI MSP-FET430 Flash Emulation Tool (FET). The FET is the program development tool for the MSP430 ultralow-power microcontroller. Both available interface types, the parallel port interface and the USB interface, are described. Device and Documentation Support Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 167 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com Application Reports Implementation of a Three-Phase Electronic Watt-Hour Meter Using MSP430F677x(A) This application report describes the implementation of a three-phase electronic electricity meter using the MSP430F677x(A) metering processor. This application report includes the necessary information with regard to metrology software, hardware procedures for this single-chip implementation. Using TI's DLMS COSEM Library This application report describes in detail the usage of DLMS COSEM library developed by Texas Instruments for customers who use TI's microcontrollers in metering applications. The library is provided as object code with a configuration file for ease of use. The library can be obtained by contacting the regional sales and marketing offices. Differences Between MSP430F67xx and MSP430F67xxA Devices This application report describes the enhancements of the MSP430F67xxA devices from the non-A MSP430F67xx devices. This application report describes the MSP430F67xx errata that are fixed in the MSP430F67xxA and the additional features added to the MSP430F67xxA devices. In addition, metrology results are compared to further show that the changes implemented in the MSP430F67xxA devices do not affect the metrology performance. MSP430 32-kHz Crystal Oscillators Selection of the correct crystal, correct load circuit, and proper board layout are important for a stable crystal oscillator. This application report summarizes crystal oscillator function and explains the parameters to select the correct crystal for MSP430 ultra-low-power operation. In addition, hints and examples for correct board layout are given. The document also contains detailed information on the possible oscillator tests to ensure stable oscillator operation in mass production. MSP430 System-Level ESD Considerations System-Level ESD has become increasingly demanding with silicon technology scaling towards lower voltages and the need for designing costeffective and ultra-low-power components. This application report addresses three different ESD topics to help board designers and OEMs understand and design robust system-level designs. Designing With MSP430 and Segment LCDs Segment liquid crystal displays (LCDs) are needed to provide information to users in a wide variety of applications from smart meters to electronic shelf labels (ESLs) to medical equipment. Several MSP430™ microcontroller families include built-in low-power LCD driver circuitry that allows the MSP430 MCU to directly control the segmented LCD glass. This application note helps explain how segmented LCDs work, the different features of the various LCD modules across the MSP430 MCU family, LCD hardware layout tips, guidance on writing efficient and easy-to-use LCD driver software, and an overview of the portfolio of MSP430 devices that include different LCD features to aid in device selection. 168 Device and Documentation Support Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A www.ti.com 8.5 SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 Related Links Table 8-2 lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 8-2. Related Links PARTS PRODUCT FOLDER ORDER NOW TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY MSP430F6779A Click here Click here Click here Click here Click here MSP430F6778A Click here Click here Click here Click here Click here MSP430F6777A Click here Click here Click here Click here Click here MSP430F6776A Click here Click here Click here Click here Click here MSP430F6775A Click here Click here Click here Click here Click here MSP430F6769A Click here Click here Click here Click here Click here MSP430F6768A Click here Click here Click here Click here Click here MSP430F6767A Click here Click here Click here Click here Click here MSP430F6766A Click here Click here Click here Click here Click here MSP430F6765A Click here Click here Click here Click here Click here MSP430F6749A Click here Click here Click here Click here Click here MSP430F6748A Click here Click here Click here Click here Click here MSP430F6747A Click here Click here Click here Click here Click here MSP430F6746A Click here Click here Click here Click here Click here MSP430F6745A Click here Click here Click here Click here Click here 8.6 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers. TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices. 8.7 Trademarks MSP430, MSP430Ware, EnergyTrace, ULP Advisor, Code Composer Studio, E2E are trademarks of Texas Instruments. Wi-Fi is a registered trademark of Wi-Fi Alliance. ZigBee is a registered trademark of ZigBee Alliance. 8.8 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 8.9 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Device and Documentation Support Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A Copyright © 2014–2018, Texas Instruments Incorporated 169 MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A SLAS982A – MAY 2014 – REVISED SEPTEMBER 2018 www.ti.com 9 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 170 Mechanical, Packaging, and Orderable Information Copyright © 2014–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) MSP430F6745AIPEU ACTIVE LQFP PEU 128 72 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6745A MSP430F6745AIPEUR ACTIVE LQFP PEU 128 750 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6745A MSP430F6745AIPZ ACTIVE LQFP PZ 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6745A MSP430F6745AIPZR ACTIVE LQFP PZ 100 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6745A MSP430F6746AIPEU ACTIVE LQFP PEU 128 72 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6746A MSP430F6746AIPEUR ACTIVE LQFP PEU 128 750 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6746A MSP430F6746AIPZ ACTIVE LQFP PZ 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6746A MSP430F6746AIPZR ACTIVE LQFP PZ 100 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6746A MSP430F6747AIPEU ACTIVE LQFP PEU 128 72 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6747A MSP430F6747AIPEUR ACTIVE LQFP PEU 128 750 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6747A MSP430F6747AIPZ ACTIVE LQFP PZ 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6747A MSP430F6747AIPZR ACTIVE LQFP PZ 100 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6747A MSP430F6748AIPEU ACTIVE LQFP PEU 128 72 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6748A MSP430F6748AIPEUR ACTIVE LQFP PEU 128 750 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6748A MSP430F6748AIPZ ACTIVE LQFP PZ 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6748A MSP430F6748AIPZR ACTIVE LQFP PZ 100 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6748A MSP430F6749AIPEU ACTIVE LQFP PEU 128 72 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6749A MSP430F6749AIPEUR ACTIVE LQFP PEU 128 750 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6749A MSP430F6749AIPZ ACTIVE LQFP PZ 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6749A MSP430F6749AIPZR ACTIVE LQFP PZ 100 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6749A Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 10-Dec-2020 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) MSP430F6765AIPEU ACTIVE LQFP PEU 128 72 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6765A MSP430F6765AIPEUR ACTIVE LQFP PEU 128 750 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6765A MSP430F6765AIPZ ACTIVE LQFP PZ 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6765A MSP430F6765AIPZR ACTIVE LQFP PZ 100 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6765A MSP430F6766AIPEU ACTIVE LQFP PEU 128 72 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6766A MSP430F6766AIPEUR ACTIVE LQFP PEU 128 750 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6766A MSP430F6766AIPZ ACTIVE LQFP PZ 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6766A MSP430F6766AIPZR ACTIVE LQFP PZ 100 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6766A MSP430F6767AIPEU ACTIVE LQFP PEU 128 72 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6767A MSP430F6767AIPEUR ACTIVE LQFP PEU 128 750 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6767A MSP430F6767AIPZ ACTIVE LQFP PZ 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6767A MSP430F6767AIPZR ACTIVE LQFP PZ 100 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6767A MSP430F6768AIPEU ACTIVE LQFP PEU 128 72 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6768A MSP430F6768AIPEUR ACTIVE LQFP PEU 128 750 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6768A MSP430F6768AIPZ ACTIVE LQFP PZ 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6768A MSP430F6768AIPZR ACTIVE LQFP PZ 100 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6768A MSP430F6769AIPEU ACTIVE LQFP PEU 128 72 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6769A MSP430F6769AIPEUR ACTIVE LQFP PEU 128 750 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6769A MSP430F6769AIPZ ACTIVE LQFP PZ 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6769A MSP430F6769AIPZR ACTIVE LQFP PZ 100 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6769A MSP430F6775AIPEU ACTIVE LQFP PEU 128 72 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6775A Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 10-Dec-2020 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) MSP430F6775AIPEUR ACTIVE LQFP PEU 128 750 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6775A MSP430F6775AIPZ ACTIVE LQFP PZ 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6775A MSP430F6775AIPZR ACTIVE LQFP PZ 100 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6775A MSP430F6776AIPEU ACTIVE LQFP PEU 128 72 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6776A MSP430F6776AIPEUR ACTIVE LQFP PEU 128 750 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6776A MSP430F6776AIPZ ACTIVE LQFP PZ 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6776A MSP430F6776AIPZR ACTIVE LQFP PZ 100 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6776A MSP430F6777AIPEU ACTIVE LQFP PEU 128 72 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6777A MSP430F6777AIPEUR ACTIVE LQFP PEU 128 750 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6777A MSP430F6777AIPZ ACTIVE LQFP PZ 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6777A MSP430F6777AIPZR ACTIVE LQFP PZ 100 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6777A MSP430F6778AIPEU ACTIVE LQFP PEU 128 72 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6778A MSP430F6778AIPEUR ACTIVE LQFP PEU 128 750 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6778A MSP430F6778AIPZ ACTIVE LQFP PZ 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6778A MSP430F6778AIPZR ACTIVE LQFP PZ 100 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6778A MSP430F6779AIPEU ACTIVE LQFP PEU 128 72 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6779A MSP430F6779AIPEUR ACTIVE LQFP PEU 128 750 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6779A MSP430F6779AIPZ ACTIVE LQFP PZ 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6779A MSP430F6779AIPZR ACTIVE LQFP PZ 100 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6779A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. Addendum-Page 3 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of